1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/component.h> 18 #include <linux/dma-fence.h> 19 #include <linux/moduleparam.h> 20 #include <linux/of_device.h> 21 #include <linux/thermal.h> 22 23 #include "etnaviv_cmdbuf.h" 24 #include "etnaviv_dump.h" 25 #include "etnaviv_gpu.h" 26 #include "etnaviv_gem.h" 27 #include "etnaviv_mmu.h" 28 #include "common.xml.h" 29 #include "state.xml.h" 30 #include "state_hi.xml.h" 31 #include "cmdstream.xml.h" 32 33 static const struct platform_device_id gpu_ids[] = { 34 { .name = "etnaviv-gpu,2d" }, 35 { }, 36 }; 37 38 static bool etnaviv_dump_core = true; 39 module_param_named(dump_core, etnaviv_dump_core, bool, 0600); 40 41 /* 42 * Driver functions: 43 */ 44 45 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 46 { 47 switch (param) { 48 case ETNAVIV_PARAM_GPU_MODEL: 49 *value = gpu->identity.model; 50 break; 51 52 case ETNAVIV_PARAM_GPU_REVISION: 53 *value = gpu->identity.revision; 54 break; 55 56 case ETNAVIV_PARAM_GPU_FEATURES_0: 57 *value = gpu->identity.features; 58 break; 59 60 case ETNAVIV_PARAM_GPU_FEATURES_1: 61 *value = gpu->identity.minor_features0; 62 break; 63 64 case ETNAVIV_PARAM_GPU_FEATURES_2: 65 *value = gpu->identity.minor_features1; 66 break; 67 68 case ETNAVIV_PARAM_GPU_FEATURES_3: 69 *value = gpu->identity.minor_features2; 70 break; 71 72 case ETNAVIV_PARAM_GPU_FEATURES_4: 73 *value = gpu->identity.minor_features3; 74 break; 75 76 case ETNAVIV_PARAM_GPU_FEATURES_5: 77 *value = gpu->identity.minor_features4; 78 break; 79 80 case ETNAVIV_PARAM_GPU_FEATURES_6: 81 *value = gpu->identity.minor_features5; 82 break; 83 84 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 85 *value = gpu->identity.stream_count; 86 break; 87 88 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 89 *value = gpu->identity.register_max; 90 break; 91 92 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 93 *value = gpu->identity.thread_count; 94 break; 95 96 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 97 *value = gpu->identity.vertex_cache_size; 98 break; 99 100 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 101 *value = gpu->identity.shader_core_count; 102 break; 103 104 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 105 *value = gpu->identity.pixel_pipes; 106 break; 107 108 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 109 *value = gpu->identity.vertex_output_buffer_size; 110 break; 111 112 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 113 *value = gpu->identity.buffer_size; 114 break; 115 116 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 117 *value = gpu->identity.instruction_count; 118 break; 119 120 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 121 *value = gpu->identity.num_constants; 122 break; 123 124 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 125 *value = gpu->identity.varyings_count; 126 break; 127 128 default: 129 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 130 return -EINVAL; 131 } 132 133 return 0; 134 } 135 136 137 #define etnaviv_is_model_rev(gpu, mod, rev) \ 138 ((gpu)->identity.model == chipModel_##mod && \ 139 (gpu)->identity.revision == rev) 140 #define etnaviv_field(val, field) \ 141 (((val) & field##__MASK) >> field##__SHIFT) 142 143 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 144 { 145 if (gpu->identity.minor_features0 & 146 chipMinorFeatures0_MORE_MINOR_FEATURES) { 147 u32 specs[4]; 148 unsigned int streams; 149 150 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 151 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 152 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 153 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 154 155 gpu->identity.stream_count = etnaviv_field(specs[0], 156 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 157 gpu->identity.register_max = etnaviv_field(specs[0], 158 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 159 gpu->identity.thread_count = etnaviv_field(specs[0], 160 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 161 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 162 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 163 gpu->identity.shader_core_count = etnaviv_field(specs[0], 164 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 165 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 166 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 167 gpu->identity.vertex_output_buffer_size = 168 etnaviv_field(specs[0], 169 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 170 171 gpu->identity.buffer_size = etnaviv_field(specs[1], 172 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 173 gpu->identity.instruction_count = etnaviv_field(specs[1], 174 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 175 gpu->identity.num_constants = etnaviv_field(specs[1], 176 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 177 178 gpu->identity.varyings_count = etnaviv_field(specs[2], 179 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 180 181 /* This overrides the value from older register if non-zero */ 182 streams = etnaviv_field(specs[3], 183 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 184 if (streams) 185 gpu->identity.stream_count = streams; 186 } 187 188 /* Fill in the stream count if not specified */ 189 if (gpu->identity.stream_count == 0) { 190 if (gpu->identity.model >= 0x1000) 191 gpu->identity.stream_count = 4; 192 else 193 gpu->identity.stream_count = 1; 194 } 195 196 /* Convert the register max value */ 197 if (gpu->identity.register_max) 198 gpu->identity.register_max = 1 << gpu->identity.register_max; 199 else if (gpu->identity.model == chipModel_GC400) 200 gpu->identity.register_max = 32; 201 else 202 gpu->identity.register_max = 64; 203 204 /* Convert thread count */ 205 if (gpu->identity.thread_count) 206 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 207 else if (gpu->identity.model == chipModel_GC400) 208 gpu->identity.thread_count = 64; 209 else if (gpu->identity.model == chipModel_GC500 || 210 gpu->identity.model == chipModel_GC530) 211 gpu->identity.thread_count = 128; 212 else 213 gpu->identity.thread_count = 256; 214 215 if (gpu->identity.vertex_cache_size == 0) 216 gpu->identity.vertex_cache_size = 8; 217 218 if (gpu->identity.shader_core_count == 0) { 219 if (gpu->identity.model >= 0x1000) 220 gpu->identity.shader_core_count = 2; 221 else 222 gpu->identity.shader_core_count = 1; 223 } 224 225 if (gpu->identity.pixel_pipes == 0) 226 gpu->identity.pixel_pipes = 1; 227 228 /* Convert virtex buffer size */ 229 if (gpu->identity.vertex_output_buffer_size) { 230 gpu->identity.vertex_output_buffer_size = 231 1 << gpu->identity.vertex_output_buffer_size; 232 } else if (gpu->identity.model == chipModel_GC400) { 233 if (gpu->identity.revision < 0x4000) 234 gpu->identity.vertex_output_buffer_size = 512; 235 else if (gpu->identity.revision < 0x4200) 236 gpu->identity.vertex_output_buffer_size = 256; 237 else 238 gpu->identity.vertex_output_buffer_size = 128; 239 } else { 240 gpu->identity.vertex_output_buffer_size = 512; 241 } 242 243 switch (gpu->identity.instruction_count) { 244 case 0: 245 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 246 gpu->identity.model == chipModel_GC880) 247 gpu->identity.instruction_count = 512; 248 else 249 gpu->identity.instruction_count = 256; 250 break; 251 252 case 1: 253 gpu->identity.instruction_count = 1024; 254 break; 255 256 case 2: 257 gpu->identity.instruction_count = 2048; 258 break; 259 260 default: 261 gpu->identity.instruction_count = 256; 262 break; 263 } 264 265 if (gpu->identity.num_constants == 0) 266 gpu->identity.num_constants = 168; 267 268 if (gpu->identity.varyings_count == 0) { 269 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 270 gpu->identity.varyings_count = 12; 271 else 272 gpu->identity.varyings_count = 8; 273 } 274 275 /* 276 * For some cores, two varyings are consumed for position, so the 277 * maximum varying count needs to be reduced by one. 278 */ 279 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 280 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 281 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 282 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 283 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 284 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 285 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 286 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 287 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 288 etnaviv_is_model_rev(gpu, GC880, 0x5107) || 289 etnaviv_is_model_rev(gpu, GC880, 0x5106)) 290 gpu->identity.varyings_count -= 1; 291 } 292 293 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 294 { 295 u32 chipIdentity; 296 297 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 298 299 /* Special case for older graphic cores. */ 300 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 301 gpu->identity.model = chipModel_GC500; 302 gpu->identity.revision = etnaviv_field(chipIdentity, 303 VIVS_HI_CHIP_IDENTITY_REVISION); 304 } else { 305 306 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 307 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 308 309 /* 310 * !!!! HACK ALERT !!!! 311 * Because people change device IDs without letting software 312 * know about it - here is the hack to make it all look the 313 * same. Only for GC400 family. 314 */ 315 if ((gpu->identity.model & 0xff00) == 0x0400 && 316 gpu->identity.model != chipModel_GC420) { 317 gpu->identity.model = gpu->identity.model & 0x0400; 318 } 319 320 /* Another special case */ 321 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 322 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 323 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 324 325 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 326 /* 327 * This IP has an ECO; put the correct 328 * revision in it. 329 */ 330 gpu->identity.revision = 0x1051; 331 } 332 } 333 334 /* 335 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 336 * reality it's just a re-branded GC3000. We can identify this 337 * core by the upper half of the revision register being all 1. 338 * Fix model/rev here, so all other places can refer to this 339 * core by its real identity. 340 */ 341 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 342 gpu->identity.model = chipModel_GC3000; 343 gpu->identity.revision &= 0xffff; 344 } 345 } 346 347 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 348 gpu->identity.model, gpu->identity.revision); 349 350 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 351 352 /* Disable fast clear on GC700. */ 353 if (gpu->identity.model == chipModel_GC700) 354 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 355 356 if ((gpu->identity.model == chipModel_GC500 && 357 gpu->identity.revision < 2) || 358 (gpu->identity.model == chipModel_GC300 && 359 gpu->identity.revision < 0x2000)) { 360 361 /* 362 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 363 * registers. 364 */ 365 gpu->identity.minor_features0 = 0; 366 gpu->identity.minor_features1 = 0; 367 gpu->identity.minor_features2 = 0; 368 gpu->identity.minor_features3 = 0; 369 gpu->identity.minor_features4 = 0; 370 gpu->identity.minor_features5 = 0; 371 } else 372 gpu->identity.minor_features0 = 373 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 374 375 if (gpu->identity.minor_features0 & 376 chipMinorFeatures0_MORE_MINOR_FEATURES) { 377 gpu->identity.minor_features1 = 378 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 379 gpu->identity.minor_features2 = 380 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 381 gpu->identity.minor_features3 = 382 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 383 gpu->identity.minor_features4 = 384 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 385 gpu->identity.minor_features5 = 386 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 387 } 388 389 /* GC600 idle register reports zero bits where modules aren't present */ 390 if (gpu->identity.model == chipModel_GC600) { 391 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 392 VIVS_HI_IDLE_STATE_RA | 393 VIVS_HI_IDLE_STATE_SE | 394 VIVS_HI_IDLE_STATE_PA | 395 VIVS_HI_IDLE_STATE_SH | 396 VIVS_HI_IDLE_STATE_PE | 397 VIVS_HI_IDLE_STATE_DE | 398 VIVS_HI_IDLE_STATE_FE; 399 } else { 400 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 401 } 402 403 etnaviv_hw_specs(gpu); 404 } 405 406 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 407 { 408 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 409 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 410 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 411 } 412 413 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 414 { 415 if (gpu->identity.minor_features2 & 416 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 417 clk_set_rate(gpu->clk_core, 418 gpu->base_rate_core >> gpu->freq_scale); 419 clk_set_rate(gpu->clk_shader, 420 gpu->base_rate_shader >> gpu->freq_scale); 421 } else { 422 unsigned int fscale = 1 << (6 - gpu->freq_scale); 423 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 424 425 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 426 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 427 etnaviv_gpu_load_clock(gpu, clock); 428 } 429 } 430 431 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 432 { 433 u32 control, idle; 434 unsigned long timeout; 435 bool failed = true; 436 437 /* TODO 438 * 439 * - clock gating 440 * - puls eater 441 * - what about VG? 442 */ 443 444 /* We hope that the GPU resets in under one second */ 445 timeout = jiffies + msecs_to_jiffies(1000); 446 447 while (time_is_after_jiffies(timeout)) { 448 /* enable clock */ 449 unsigned int fscale = 1 << (6 - gpu->freq_scale); 450 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 451 etnaviv_gpu_load_clock(gpu, control); 452 453 /* Wait for stable clock. Vivante's code waited for 1ms */ 454 usleep_range(1000, 10000); 455 456 /* isolate the GPU. */ 457 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 458 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 459 460 /* set soft reset. */ 461 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 462 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 463 464 /* wait for reset. */ 465 msleep(1); 466 467 /* reset soft reset bit. */ 468 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 469 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 470 471 /* reset GPU isolation. */ 472 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 473 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 474 475 /* read idle register. */ 476 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 477 478 /* try reseting again if FE it not idle */ 479 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 480 dev_dbg(gpu->dev, "FE is not idle\n"); 481 continue; 482 } 483 484 /* read reset register. */ 485 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 486 487 /* is the GPU idle? */ 488 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 489 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 490 dev_dbg(gpu->dev, "GPU is not idle\n"); 491 continue; 492 } 493 494 /* disable debug registers, as they are not normally needed */ 495 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 496 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 497 498 failed = false; 499 break; 500 } 501 502 if (failed) { 503 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 504 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 505 506 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 507 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 508 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 509 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 510 511 return -EBUSY; 512 } 513 514 /* We rely on the GPU running, so program the clock */ 515 etnaviv_gpu_update_clock(gpu); 516 517 return 0; 518 } 519 520 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 521 { 522 u32 pmc, ppc; 523 524 /* enable clock gating */ 525 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 526 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 527 528 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 529 if (gpu->identity.revision == 0x4301 || 530 gpu->identity.revision == 0x4302) 531 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 532 533 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 534 535 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 536 537 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 538 if (gpu->identity.model >= chipModel_GC400 && 539 gpu->identity.model != chipModel_GC420 && 540 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 541 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 542 543 /* 544 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 545 * present without a bug fix. 546 */ 547 if (gpu->identity.revision < 0x5000 && 548 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 549 !(gpu->identity.minor_features1 & 550 chipMinorFeatures1_DISABLE_PE_GATING)) 551 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 552 553 if (gpu->identity.revision < 0x5422) 554 pmc |= BIT(15); /* Unknown bit */ 555 556 /* Disable TX clock gating on affected core revisions. */ 557 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 558 etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 559 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 560 561 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 562 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 563 564 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 565 } 566 567 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 568 { 569 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 570 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 571 VIVS_FE_COMMAND_CONTROL_ENABLE | 572 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 573 } 574 575 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 576 { 577 /* 578 * Base value for VIVS_PM_PULSE_EATER register on models where it 579 * cannot be read, extracted from vivante kernel driver. 580 */ 581 u32 pulse_eater = 0x01590880; 582 583 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 584 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 585 pulse_eater |= BIT(23); 586 587 } 588 589 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 590 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 591 pulse_eater &= ~BIT(16); 592 pulse_eater |= BIT(17); 593 } 594 595 if ((gpu->identity.revision > 0x5420) && 596 (gpu->identity.features & chipFeatures_PIPE_3D)) 597 { 598 /* Performance fix: disable internal DFS */ 599 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 600 pulse_eater |= BIT(18); 601 } 602 603 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 604 } 605 606 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 607 { 608 u16 prefetch; 609 610 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 611 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 612 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 613 u32 mc_memory_debug; 614 615 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 616 617 if (gpu->identity.revision == 0x5007) 618 mc_memory_debug |= 0x0c; 619 else 620 mc_memory_debug |= 0x08; 621 622 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 623 } 624 625 /* enable module-level clock gating */ 626 etnaviv_gpu_enable_mlcg(gpu); 627 628 /* 629 * Update GPU AXI cache atttribute to "cacheable, no allocate". 630 * This is necessary to prevent the iMX6 SoC locking up. 631 */ 632 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 633 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 634 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 635 636 /* GC2000 rev 5108 needs a special bus config */ 637 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 638 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 639 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 640 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 641 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 642 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 643 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 644 } 645 646 /* setup the pulse eater */ 647 etnaviv_gpu_setup_pulse_eater(gpu); 648 649 /* setup the MMU */ 650 etnaviv_iommu_restore(gpu); 651 652 /* Start command processor */ 653 prefetch = etnaviv_buffer_init(gpu); 654 655 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 656 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer), 657 prefetch); 658 } 659 660 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 661 { 662 int ret, i; 663 664 ret = pm_runtime_get_sync(gpu->dev); 665 if (ret < 0) { 666 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 667 return ret; 668 } 669 670 etnaviv_hw_identify(gpu); 671 672 if (gpu->identity.model == 0) { 673 dev_err(gpu->dev, "Unknown GPU model\n"); 674 ret = -ENXIO; 675 goto fail; 676 } 677 678 /* Exclude VG cores with FE2.0 */ 679 if (gpu->identity.features & chipFeatures_PIPE_VG && 680 gpu->identity.features & chipFeatures_FE20) { 681 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 682 ret = -ENXIO; 683 goto fail; 684 } 685 686 /* 687 * Set the GPU linear window to be at the end of the DMA window, where 688 * the CMA area is likely to reside. This ensures that we are able to 689 * map the command buffers while having the linear window overlap as 690 * much RAM as possible, so we can optimize mappings for other buffers. 691 * 692 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 693 * to different views of the memory on the individual engines. 694 */ 695 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 696 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 697 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 698 if (dma_mask < PHYS_OFFSET + SZ_2G) 699 gpu->memory_base = PHYS_OFFSET; 700 else 701 gpu->memory_base = dma_mask - SZ_2G + 1; 702 } else if (PHYS_OFFSET >= SZ_2G) { 703 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 704 gpu->memory_base = PHYS_OFFSET; 705 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 706 } 707 708 ret = etnaviv_hw_reset(gpu); 709 if (ret) { 710 dev_err(gpu->dev, "GPU reset failed\n"); 711 goto fail; 712 } 713 714 gpu->mmu = etnaviv_iommu_new(gpu); 715 if (IS_ERR(gpu->mmu)) { 716 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 717 ret = PTR_ERR(gpu->mmu); 718 goto fail; 719 } 720 721 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu); 722 if (IS_ERR(gpu->cmdbuf_suballoc)) { 723 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); 724 ret = PTR_ERR(gpu->cmdbuf_suballoc); 725 goto fail; 726 } 727 728 /* Create buffer: */ 729 gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0); 730 if (!gpu->buffer) { 731 ret = -ENOMEM; 732 dev_err(gpu->dev, "could not create command buffer\n"); 733 goto destroy_iommu; 734 } 735 736 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 737 etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) { 738 ret = -EINVAL; 739 dev_err(gpu->dev, 740 "command buffer outside valid memory window\n"); 741 goto free_buffer; 742 } 743 744 /* Setup event management */ 745 spin_lock_init(&gpu->event_spinlock); 746 init_completion(&gpu->event_free); 747 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 748 gpu->event[i].used = false; 749 complete(&gpu->event_free); 750 } 751 752 /* Now program the hardware */ 753 mutex_lock(&gpu->lock); 754 etnaviv_gpu_hw_init(gpu); 755 gpu->exec_state = -1; 756 mutex_unlock(&gpu->lock); 757 758 pm_runtime_mark_last_busy(gpu->dev); 759 pm_runtime_put_autosuspend(gpu->dev); 760 761 return 0; 762 763 free_buffer: 764 etnaviv_cmdbuf_free(gpu->buffer); 765 gpu->buffer = NULL; 766 destroy_iommu: 767 etnaviv_iommu_destroy(gpu->mmu); 768 gpu->mmu = NULL; 769 fail: 770 pm_runtime_mark_last_busy(gpu->dev); 771 pm_runtime_put_autosuspend(gpu->dev); 772 773 return ret; 774 } 775 776 #ifdef CONFIG_DEBUG_FS 777 struct dma_debug { 778 u32 address[2]; 779 u32 state[2]; 780 }; 781 782 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 783 { 784 u32 i; 785 786 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 787 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 788 789 for (i = 0; i < 500; i++) { 790 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 791 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 792 793 if (debug->address[0] != debug->address[1]) 794 break; 795 796 if (debug->state[0] != debug->state[1]) 797 break; 798 } 799 } 800 801 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 802 { 803 struct dma_debug debug; 804 u32 dma_lo, dma_hi, axi, idle; 805 int ret; 806 807 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 808 809 ret = pm_runtime_get_sync(gpu->dev); 810 if (ret < 0) 811 return ret; 812 813 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 814 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 815 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 816 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 817 818 verify_dma(gpu, &debug); 819 820 seq_puts(m, "\tfeatures\n"); 821 seq_printf(m, "\t minor_features0: 0x%08x\n", 822 gpu->identity.minor_features0); 823 seq_printf(m, "\t minor_features1: 0x%08x\n", 824 gpu->identity.minor_features1); 825 seq_printf(m, "\t minor_features2: 0x%08x\n", 826 gpu->identity.minor_features2); 827 seq_printf(m, "\t minor_features3: 0x%08x\n", 828 gpu->identity.minor_features3); 829 seq_printf(m, "\t minor_features4: 0x%08x\n", 830 gpu->identity.minor_features4); 831 seq_printf(m, "\t minor_features5: 0x%08x\n", 832 gpu->identity.minor_features5); 833 834 seq_puts(m, "\tspecs\n"); 835 seq_printf(m, "\t stream_count: %d\n", 836 gpu->identity.stream_count); 837 seq_printf(m, "\t register_max: %d\n", 838 gpu->identity.register_max); 839 seq_printf(m, "\t thread_count: %d\n", 840 gpu->identity.thread_count); 841 seq_printf(m, "\t vertex_cache_size: %d\n", 842 gpu->identity.vertex_cache_size); 843 seq_printf(m, "\t shader_core_count: %d\n", 844 gpu->identity.shader_core_count); 845 seq_printf(m, "\t pixel_pipes: %d\n", 846 gpu->identity.pixel_pipes); 847 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 848 gpu->identity.vertex_output_buffer_size); 849 seq_printf(m, "\t buffer_size: %d\n", 850 gpu->identity.buffer_size); 851 seq_printf(m, "\t instruction_count: %d\n", 852 gpu->identity.instruction_count); 853 seq_printf(m, "\t num_constants: %d\n", 854 gpu->identity.num_constants); 855 seq_printf(m, "\t varyings_count: %d\n", 856 gpu->identity.varyings_count); 857 858 seq_printf(m, "\taxi: 0x%08x\n", axi); 859 seq_printf(m, "\tidle: 0x%08x\n", idle); 860 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 861 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 862 seq_puts(m, "\t FE is not idle\n"); 863 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 864 seq_puts(m, "\t DE is not idle\n"); 865 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 866 seq_puts(m, "\t PE is not idle\n"); 867 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 868 seq_puts(m, "\t SH is not idle\n"); 869 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 870 seq_puts(m, "\t PA is not idle\n"); 871 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 872 seq_puts(m, "\t SE is not idle\n"); 873 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 874 seq_puts(m, "\t RA is not idle\n"); 875 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 876 seq_puts(m, "\t TX is not idle\n"); 877 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 878 seq_puts(m, "\t VG is not idle\n"); 879 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 880 seq_puts(m, "\t IM is not idle\n"); 881 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 882 seq_puts(m, "\t FP is not idle\n"); 883 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 884 seq_puts(m, "\t TS is not idle\n"); 885 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 886 seq_puts(m, "\t AXI low power mode\n"); 887 888 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 889 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 890 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 891 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 892 893 seq_puts(m, "\tMC\n"); 894 seq_printf(m, "\t read0: 0x%08x\n", read0); 895 seq_printf(m, "\t read1: 0x%08x\n", read1); 896 seq_printf(m, "\t write: 0x%08x\n", write); 897 } 898 899 seq_puts(m, "\tDMA "); 900 901 if (debug.address[0] == debug.address[1] && 902 debug.state[0] == debug.state[1]) { 903 seq_puts(m, "seems to be stuck\n"); 904 } else if (debug.address[0] == debug.address[1]) { 905 seq_puts(m, "address is constant\n"); 906 } else { 907 seq_puts(m, "is running\n"); 908 } 909 910 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 911 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 912 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 913 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 914 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 915 dma_lo, dma_hi); 916 917 ret = 0; 918 919 pm_runtime_mark_last_busy(gpu->dev); 920 pm_runtime_put_autosuspend(gpu->dev); 921 922 return ret; 923 } 924 #endif 925 926 /* 927 * Hangcheck detection for locked gpu: 928 */ 929 static void recover_worker(struct work_struct *work) 930 { 931 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 932 recover_work); 933 unsigned long flags; 934 unsigned int i; 935 936 dev_err(gpu->dev, "hangcheck recover!\n"); 937 938 if (pm_runtime_get_sync(gpu->dev) < 0) 939 return; 940 941 mutex_lock(&gpu->lock); 942 943 /* Only catch the first event, or when manually re-armed */ 944 if (etnaviv_dump_core) { 945 etnaviv_core_dump(gpu); 946 etnaviv_dump_core = false; 947 } 948 949 etnaviv_hw_reset(gpu); 950 951 /* complete all events, the GPU won't do it after the reset */ 952 spin_lock_irqsave(&gpu->event_spinlock, flags); 953 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 954 if (!gpu->event[i].used) 955 continue; 956 dma_fence_signal(gpu->event[i].fence); 957 gpu->event[i].fence = NULL; 958 gpu->event[i].used = false; 959 complete(&gpu->event_free); 960 } 961 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 962 gpu->completed_fence = gpu->active_fence; 963 964 etnaviv_gpu_hw_init(gpu); 965 gpu->lastctx = NULL; 966 gpu->exec_state = -1; 967 968 mutex_unlock(&gpu->lock); 969 pm_runtime_mark_last_busy(gpu->dev); 970 pm_runtime_put_autosuspend(gpu->dev); 971 972 /* Retire the buffer objects in a work */ 973 etnaviv_queue_work(gpu->drm, &gpu->retire_work); 974 } 975 976 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) 977 { 978 DBG("%s", dev_name(gpu->dev)); 979 mod_timer(&gpu->hangcheck_timer, 980 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); 981 } 982 983 static void hangcheck_handler(unsigned long data) 984 { 985 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data; 986 u32 fence = gpu->completed_fence; 987 bool progress = false; 988 989 if (fence != gpu->hangcheck_fence) { 990 gpu->hangcheck_fence = fence; 991 progress = true; 992 } 993 994 if (!progress) { 995 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 996 int change = dma_addr - gpu->hangcheck_dma_addr; 997 998 if (change < 0 || change > 16) { 999 gpu->hangcheck_dma_addr = dma_addr; 1000 progress = true; 1001 } 1002 } 1003 1004 if (!progress && fence_after(gpu->active_fence, fence)) { 1005 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); 1006 dev_err(gpu->dev, " completed fence: %u\n", fence); 1007 dev_err(gpu->dev, " active fence: %u\n", 1008 gpu->active_fence); 1009 etnaviv_queue_work(gpu->drm, &gpu->recover_work); 1010 } 1011 1012 /* if still more pending work, reset the hangcheck timer: */ 1013 if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) 1014 hangcheck_timer_reset(gpu); 1015 } 1016 1017 static void hangcheck_disable(struct etnaviv_gpu *gpu) 1018 { 1019 del_timer_sync(&gpu->hangcheck_timer); 1020 cancel_work_sync(&gpu->recover_work); 1021 } 1022 1023 /* fence object management */ 1024 struct etnaviv_fence { 1025 struct etnaviv_gpu *gpu; 1026 struct dma_fence base; 1027 }; 1028 1029 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1030 { 1031 return container_of(fence, struct etnaviv_fence, base); 1032 } 1033 1034 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1035 { 1036 return "etnaviv"; 1037 } 1038 1039 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1040 { 1041 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1042 1043 return dev_name(f->gpu->dev); 1044 } 1045 1046 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence) 1047 { 1048 return true; 1049 } 1050 1051 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1052 { 1053 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1054 1055 return fence_completed(f->gpu, f->base.seqno); 1056 } 1057 1058 static void etnaviv_fence_release(struct dma_fence *fence) 1059 { 1060 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1061 1062 kfree_rcu(f, base.rcu); 1063 } 1064 1065 static const struct dma_fence_ops etnaviv_fence_ops = { 1066 .get_driver_name = etnaviv_fence_get_driver_name, 1067 .get_timeline_name = etnaviv_fence_get_timeline_name, 1068 .enable_signaling = etnaviv_fence_enable_signaling, 1069 .signaled = etnaviv_fence_signaled, 1070 .wait = dma_fence_default_wait, 1071 .release = etnaviv_fence_release, 1072 }; 1073 1074 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1075 { 1076 struct etnaviv_fence *f; 1077 1078 /* 1079 * GPU lock must already be held, otherwise fence completion order might 1080 * not match the seqno order assigned here. 1081 */ 1082 lockdep_assert_held(&gpu->lock); 1083 1084 f = kzalloc(sizeof(*f), GFP_KERNEL); 1085 if (!f) 1086 return NULL; 1087 1088 f->gpu = gpu; 1089 1090 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1091 gpu->fence_context, ++gpu->next_fence); 1092 1093 return &f->base; 1094 } 1095 1096 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 1097 unsigned int context, bool exclusive, bool explicit) 1098 { 1099 struct reservation_object *robj = etnaviv_obj->resv; 1100 struct reservation_object_list *fobj; 1101 struct dma_fence *fence; 1102 int i, ret; 1103 1104 if (!exclusive) { 1105 ret = reservation_object_reserve_shared(robj); 1106 if (ret) 1107 return ret; 1108 } 1109 1110 if (explicit) 1111 return 0; 1112 1113 /* 1114 * If we have any shared fences, then the exclusive fence 1115 * should be ignored as it will already have been signalled. 1116 */ 1117 fobj = reservation_object_get_list(robj); 1118 if (!fobj || fobj->shared_count == 0) { 1119 /* Wait on any existing exclusive fence which isn't our own */ 1120 fence = reservation_object_get_excl(robj); 1121 if (fence && fence->context != context) { 1122 ret = dma_fence_wait(fence, true); 1123 if (ret) 1124 return ret; 1125 } 1126 } 1127 1128 if (!exclusive || !fobj) 1129 return 0; 1130 1131 for (i = 0; i < fobj->shared_count; i++) { 1132 fence = rcu_dereference_protected(fobj->shared[i], 1133 reservation_object_held(robj)); 1134 if (fence->context != context) { 1135 ret = dma_fence_wait(fence, true); 1136 if (ret) 1137 return ret; 1138 } 1139 } 1140 1141 return 0; 1142 } 1143 1144 /* 1145 * event management: 1146 */ 1147 1148 static unsigned int event_alloc(struct etnaviv_gpu *gpu) 1149 { 1150 unsigned long ret, flags; 1151 unsigned int i, event = ~0U; 1152 1153 ret = wait_for_completion_timeout(&gpu->event_free, 1154 msecs_to_jiffies(10 * 10000)); 1155 if (!ret) 1156 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1157 1158 spin_lock_irqsave(&gpu->event_spinlock, flags); 1159 1160 /* find first free event */ 1161 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 1162 if (gpu->event[i].used == false) { 1163 gpu->event[i].used = true; 1164 event = i; 1165 break; 1166 } 1167 } 1168 1169 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1170 1171 return event; 1172 } 1173 1174 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1175 { 1176 unsigned long flags; 1177 1178 spin_lock_irqsave(&gpu->event_spinlock, flags); 1179 1180 if (gpu->event[event].used == false) { 1181 dev_warn(gpu->dev, "event %u is already marked as free", 1182 event); 1183 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1184 } else { 1185 gpu->event[event].used = false; 1186 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1187 1188 complete(&gpu->event_free); 1189 } 1190 } 1191 1192 /* 1193 * Cmdstream submission/retirement: 1194 */ 1195 1196 static void retire_worker(struct work_struct *work) 1197 { 1198 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1199 retire_work); 1200 u32 fence = gpu->completed_fence; 1201 struct etnaviv_cmdbuf *cmdbuf, *tmp; 1202 unsigned int i; 1203 1204 mutex_lock(&gpu->lock); 1205 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { 1206 if (!dma_fence_is_signaled(cmdbuf->fence)) 1207 break; 1208 1209 list_del(&cmdbuf->node); 1210 dma_fence_put(cmdbuf->fence); 1211 1212 for (i = 0; i < cmdbuf->nr_bos; i++) { 1213 struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; 1214 struct etnaviv_gem_object *etnaviv_obj = mapping->object; 1215 1216 atomic_dec(&etnaviv_obj->gpu_active); 1217 /* drop the refcount taken in etnaviv_gpu_submit */ 1218 etnaviv_gem_mapping_unreference(mapping); 1219 } 1220 1221 etnaviv_cmdbuf_free(cmdbuf); 1222 /* 1223 * We need to balance the runtime PM count caused by 1224 * each submission. Upon submission, we increment 1225 * the runtime PM counter, and allocate one event. 1226 * So here, we put the runtime PM count for each 1227 * completed event. 1228 */ 1229 pm_runtime_put_autosuspend(gpu->dev); 1230 } 1231 1232 gpu->retired_fence = fence; 1233 1234 mutex_unlock(&gpu->lock); 1235 1236 wake_up_all(&gpu->fence_event); 1237 } 1238 1239 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1240 u32 fence, struct timespec *timeout) 1241 { 1242 int ret; 1243 1244 if (fence_after(fence, gpu->next_fence)) { 1245 DRM_ERROR("waiting on invalid fence: %u (of %u)\n", 1246 fence, gpu->next_fence); 1247 return -EINVAL; 1248 } 1249 1250 if (!timeout) { 1251 /* No timeout was requested: just test for completion */ 1252 ret = fence_completed(gpu, fence) ? 0 : -EBUSY; 1253 } else { 1254 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1255 1256 ret = wait_event_interruptible_timeout(gpu->fence_event, 1257 fence_completed(gpu, fence), 1258 remaining); 1259 if (ret == 0) { 1260 DBG("timeout waiting for fence: %u (retired: %u completed: %u)", 1261 fence, gpu->retired_fence, 1262 gpu->completed_fence); 1263 ret = -ETIMEDOUT; 1264 } else if (ret != -ERESTARTSYS) { 1265 ret = 0; 1266 } 1267 } 1268 1269 return ret; 1270 } 1271 1272 /* 1273 * Wait for an object to become inactive. This, on it's own, is not race 1274 * free: the object is moved by the retire worker off the active list, and 1275 * then the iova is put. Moreover, the object could be re-submitted just 1276 * after we notice that it's become inactive. 1277 * 1278 * Although the retirement happens under the gpu lock, we don't want to hold 1279 * that lock in this function while waiting. 1280 */ 1281 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1282 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1283 { 1284 unsigned long remaining; 1285 long ret; 1286 1287 if (!timeout) 1288 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1289 1290 remaining = etnaviv_timeout_to_jiffies(timeout); 1291 1292 ret = wait_event_interruptible_timeout(gpu->fence_event, 1293 !is_active(etnaviv_obj), 1294 remaining); 1295 if (ret > 0) { 1296 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 1297 1298 /* Synchronise with the retire worker */ 1299 flush_workqueue(priv->wq); 1300 return 0; 1301 } else if (ret == -ERESTARTSYS) { 1302 return -ERESTARTSYS; 1303 } else { 1304 return -ETIMEDOUT; 1305 } 1306 } 1307 1308 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) 1309 { 1310 return pm_runtime_get_sync(gpu->dev); 1311 } 1312 1313 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) 1314 { 1315 pm_runtime_mark_last_busy(gpu->dev); 1316 pm_runtime_put_autosuspend(gpu->dev); 1317 } 1318 1319 /* add bo's to gpu's ring, and kick gpu: */ 1320 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 1321 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) 1322 { 1323 struct dma_fence *fence; 1324 unsigned int event, i; 1325 int ret; 1326 1327 ret = etnaviv_gpu_pm_get_sync(gpu); 1328 if (ret < 0) 1329 return ret; 1330 1331 /* 1332 * TODO 1333 * 1334 * - flush 1335 * - data endian 1336 * - prefetch 1337 * 1338 */ 1339 1340 event = event_alloc(gpu); 1341 if (unlikely(event == ~0U)) { 1342 DRM_ERROR("no free event\n"); 1343 ret = -EBUSY; 1344 goto out_pm_put; 1345 } 1346 1347 mutex_lock(&gpu->lock); 1348 1349 fence = etnaviv_gpu_fence_alloc(gpu); 1350 if (!fence) { 1351 event_free(gpu, event); 1352 ret = -ENOMEM; 1353 goto out_unlock; 1354 } 1355 1356 gpu->event[event].fence = fence; 1357 submit->fence = dma_fence_get(fence); 1358 gpu->active_fence = submit->fence->seqno; 1359 1360 if (gpu->lastctx != cmdbuf->ctx) { 1361 gpu->mmu->need_flush = true; 1362 gpu->switch_context = true; 1363 gpu->lastctx = cmdbuf->ctx; 1364 } 1365 1366 etnaviv_buffer_queue(gpu, event, cmdbuf); 1367 1368 cmdbuf->fence = fence; 1369 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); 1370 1371 /* We're committed to adding this command buffer, hold a PM reference */ 1372 pm_runtime_get_noresume(gpu->dev); 1373 1374 for (i = 0; i < submit->nr_bos; i++) { 1375 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; 1376 1377 /* Each cmdbuf takes a refcount on the mapping */ 1378 etnaviv_gem_mapping_reference(submit->bos[i].mapping); 1379 cmdbuf->bo_map[i] = submit->bos[i].mapping; 1380 atomic_inc(&etnaviv_obj->gpu_active); 1381 1382 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) 1383 reservation_object_add_excl_fence(etnaviv_obj->resv, 1384 fence); 1385 else 1386 reservation_object_add_shared_fence(etnaviv_obj->resv, 1387 fence); 1388 } 1389 cmdbuf->nr_bos = submit->nr_bos; 1390 hangcheck_timer_reset(gpu); 1391 ret = 0; 1392 1393 out_unlock: 1394 mutex_unlock(&gpu->lock); 1395 1396 out_pm_put: 1397 etnaviv_gpu_pm_put(gpu); 1398 1399 return ret; 1400 } 1401 1402 /* 1403 * Init/Cleanup: 1404 */ 1405 static irqreturn_t irq_handler(int irq, void *data) 1406 { 1407 struct etnaviv_gpu *gpu = data; 1408 irqreturn_t ret = IRQ_NONE; 1409 1410 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1411 1412 if (intr != 0) { 1413 int event; 1414 1415 pm_runtime_mark_last_busy(gpu->dev); 1416 1417 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1418 1419 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1420 dev_err(gpu->dev, "AXI bus error\n"); 1421 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1422 } 1423 1424 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1425 int i; 1426 1427 dev_err_ratelimited(gpu->dev, 1428 "MMU fault status 0x%08x\n", 1429 gpu_read(gpu, VIVS_MMUv2_STATUS)); 1430 for (i = 0; i < 4; i++) { 1431 dev_err_ratelimited(gpu->dev, 1432 "MMU %d fault addr 0x%08x\n", 1433 i, gpu_read(gpu, 1434 VIVS_MMUv2_EXCEPTION_ADDR(i))); 1435 } 1436 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1437 } 1438 1439 while ((event = ffs(intr)) != 0) { 1440 struct dma_fence *fence; 1441 1442 event -= 1; 1443 1444 intr &= ~(1 << event); 1445 1446 dev_dbg(gpu->dev, "event %u\n", event); 1447 1448 fence = gpu->event[event].fence; 1449 gpu->event[event].fence = NULL; 1450 dma_fence_signal(fence); 1451 1452 /* 1453 * Events can be processed out of order. Eg, 1454 * - allocate and queue event 0 1455 * - allocate event 1 1456 * - event 0 completes, we process it 1457 * - allocate and queue event 0 1458 * - event 1 and event 0 complete 1459 * we can end up processing event 0 first, then 1. 1460 */ 1461 if (fence_after(fence->seqno, gpu->completed_fence)) 1462 gpu->completed_fence = fence->seqno; 1463 1464 event_free(gpu, event); 1465 } 1466 1467 /* Retire the buffer objects in a work */ 1468 etnaviv_queue_work(gpu->drm, &gpu->retire_work); 1469 1470 ret = IRQ_HANDLED; 1471 } 1472 1473 return ret; 1474 } 1475 1476 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1477 { 1478 int ret; 1479 1480 if (gpu->clk_bus) { 1481 ret = clk_prepare_enable(gpu->clk_bus); 1482 if (ret) 1483 return ret; 1484 } 1485 1486 if (gpu->clk_core) { 1487 ret = clk_prepare_enable(gpu->clk_core); 1488 if (ret) 1489 goto disable_clk_bus; 1490 } 1491 1492 if (gpu->clk_shader) { 1493 ret = clk_prepare_enable(gpu->clk_shader); 1494 if (ret) 1495 goto disable_clk_core; 1496 } 1497 1498 return 0; 1499 1500 disable_clk_core: 1501 if (gpu->clk_core) 1502 clk_disable_unprepare(gpu->clk_core); 1503 disable_clk_bus: 1504 if (gpu->clk_bus) 1505 clk_disable_unprepare(gpu->clk_bus); 1506 1507 return ret; 1508 } 1509 1510 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1511 { 1512 if (gpu->clk_shader) 1513 clk_disable_unprepare(gpu->clk_shader); 1514 if (gpu->clk_core) 1515 clk_disable_unprepare(gpu->clk_core); 1516 if (gpu->clk_bus) 1517 clk_disable_unprepare(gpu->clk_bus); 1518 1519 return 0; 1520 } 1521 1522 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1523 { 1524 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1525 1526 do { 1527 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1528 1529 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1530 return 0; 1531 1532 if (time_is_before_jiffies(timeout)) { 1533 dev_warn(gpu->dev, 1534 "timed out waiting for idle: idle=0x%x\n", 1535 idle); 1536 return -ETIMEDOUT; 1537 } 1538 1539 udelay(5); 1540 } while (1); 1541 } 1542 1543 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1544 { 1545 if (gpu->buffer) { 1546 /* Replace the last WAIT with END */ 1547 etnaviv_buffer_end(gpu); 1548 1549 /* 1550 * We know that only the FE is busy here, this should 1551 * happen quickly (as the WAIT is only 200 cycles). If 1552 * we fail, just warn and continue. 1553 */ 1554 etnaviv_gpu_wait_idle(gpu, 100); 1555 } 1556 1557 return etnaviv_gpu_clk_disable(gpu); 1558 } 1559 1560 #ifdef CONFIG_PM 1561 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1562 { 1563 int ret; 1564 1565 ret = mutex_lock_killable(&gpu->lock); 1566 if (ret) 1567 return ret; 1568 1569 etnaviv_gpu_update_clock(gpu); 1570 etnaviv_gpu_hw_init(gpu); 1571 1572 gpu->switch_context = true; 1573 gpu->exec_state = -1; 1574 1575 mutex_unlock(&gpu->lock); 1576 1577 return 0; 1578 } 1579 #endif 1580 1581 static int 1582 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1583 unsigned long *state) 1584 { 1585 *state = 6; 1586 1587 return 0; 1588 } 1589 1590 static int 1591 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1592 unsigned long *state) 1593 { 1594 struct etnaviv_gpu *gpu = cdev->devdata; 1595 1596 *state = gpu->freq_scale; 1597 1598 return 0; 1599 } 1600 1601 static int 1602 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1603 unsigned long state) 1604 { 1605 struct etnaviv_gpu *gpu = cdev->devdata; 1606 1607 mutex_lock(&gpu->lock); 1608 gpu->freq_scale = state; 1609 if (!pm_runtime_suspended(gpu->dev)) 1610 etnaviv_gpu_update_clock(gpu); 1611 mutex_unlock(&gpu->lock); 1612 1613 return 0; 1614 } 1615 1616 static struct thermal_cooling_device_ops cooling_ops = { 1617 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1618 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1619 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1620 }; 1621 1622 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1623 void *data) 1624 { 1625 struct drm_device *drm = data; 1626 struct etnaviv_drm_private *priv = drm->dev_private; 1627 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1628 int ret; 1629 1630 if (IS_ENABLED(CONFIG_THERMAL)) { 1631 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1632 (char *)dev_name(dev), gpu, &cooling_ops); 1633 if (IS_ERR(gpu->cooling)) 1634 return PTR_ERR(gpu->cooling); 1635 } 1636 1637 #ifdef CONFIG_PM 1638 ret = pm_runtime_get_sync(gpu->dev); 1639 #else 1640 ret = etnaviv_gpu_clk_enable(gpu); 1641 #endif 1642 if (ret < 0) { 1643 thermal_cooling_device_unregister(gpu->cooling); 1644 return ret; 1645 } 1646 1647 gpu->drm = drm; 1648 gpu->fence_context = dma_fence_context_alloc(1); 1649 spin_lock_init(&gpu->fence_spinlock); 1650 1651 INIT_LIST_HEAD(&gpu->active_cmd_list); 1652 INIT_WORK(&gpu->retire_work, retire_worker); 1653 INIT_WORK(&gpu->recover_work, recover_worker); 1654 init_waitqueue_head(&gpu->fence_event); 1655 1656 setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, 1657 (unsigned long)gpu); 1658 1659 priv->gpu[priv->num_gpus++] = gpu; 1660 1661 pm_runtime_mark_last_busy(gpu->dev); 1662 pm_runtime_put_autosuspend(gpu->dev); 1663 1664 return 0; 1665 } 1666 1667 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1668 void *data) 1669 { 1670 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1671 1672 DBG("%s", dev_name(gpu->dev)); 1673 1674 hangcheck_disable(gpu); 1675 1676 #ifdef CONFIG_PM 1677 pm_runtime_get_sync(gpu->dev); 1678 pm_runtime_put_sync_suspend(gpu->dev); 1679 #else 1680 etnaviv_gpu_hw_suspend(gpu); 1681 #endif 1682 1683 if (gpu->buffer) { 1684 etnaviv_cmdbuf_free(gpu->buffer); 1685 gpu->buffer = NULL; 1686 } 1687 1688 if (gpu->cmdbuf_suballoc) { 1689 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); 1690 gpu->cmdbuf_suballoc = NULL; 1691 } 1692 1693 if (gpu->mmu) { 1694 etnaviv_iommu_destroy(gpu->mmu); 1695 gpu->mmu = NULL; 1696 } 1697 1698 gpu->drm = NULL; 1699 1700 thermal_cooling_device_unregister(gpu->cooling); 1701 gpu->cooling = NULL; 1702 } 1703 1704 static const struct component_ops gpu_ops = { 1705 .bind = etnaviv_gpu_bind, 1706 .unbind = etnaviv_gpu_unbind, 1707 }; 1708 1709 static const struct of_device_id etnaviv_gpu_match[] = { 1710 { 1711 .compatible = "vivante,gc" 1712 }, 1713 { /* sentinel */ } 1714 }; 1715 1716 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1717 { 1718 struct device *dev = &pdev->dev; 1719 struct etnaviv_gpu *gpu; 1720 int err; 1721 1722 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1723 if (!gpu) 1724 return -ENOMEM; 1725 1726 gpu->dev = &pdev->dev; 1727 mutex_init(&gpu->lock); 1728 1729 /* Map registers: */ 1730 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); 1731 if (IS_ERR(gpu->mmio)) 1732 return PTR_ERR(gpu->mmio); 1733 1734 /* Get Interrupt: */ 1735 gpu->irq = platform_get_irq(pdev, 0); 1736 if (gpu->irq < 0) { 1737 dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1738 return gpu->irq; 1739 } 1740 1741 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1742 dev_name(gpu->dev), gpu); 1743 if (err) { 1744 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1745 return err; 1746 } 1747 1748 /* Get Clocks: */ 1749 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1750 DBG("clk_bus: %p", gpu->clk_bus); 1751 if (IS_ERR(gpu->clk_bus)) 1752 gpu->clk_bus = NULL; 1753 1754 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1755 DBG("clk_core: %p", gpu->clk_core); 1756 if (IS_ERR(gpu->clk_core)) 1757 gpu->clk_core = NULL; 1758 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1759 1760 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1761 DBG("clk_shader: %p", gpu->clk_shader); 1762 if (IS_ERR(gpu->clk_shader)) 1763 gpu->clk_shader = NULL; 1764 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1765 1766 /* TODO: figure out max mapped size */ 1767 dev_set_drvdata(dev, gpu); 1768 1769 /* 1770 * We treat the device as initially suspended. The runtime PM 1771 * autosuspend delay is rather arbitary: no measurements have 1772 * yet been performed to determine an appropriate value. 1773 */ 1774 pm_runtime_use_autosuspend(gpu->dev); 1775 pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1776 pm_runtime_enable(gpu->dev); 1777 1778 err = component_add(&pdev->dev, &gpu_ops); 1779 if (err < 0) { 1780 dev_err(&pdev->dev, "failed to register component: %d\n", err); 1781 return err; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1788 { 1789 component_del(&pdev->dev, &gpu_ops); 1790 pm_runtime_disable(&pdev->dev); 1791 return 0; 1792 } 1793 1794 #ifdef CONFIG_PM 1795 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1796 { 1797 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1798 u32 idle, mask; 1799 1800 /* If we have outstanding fences, we're not idle */ 1801 if (gpu->completed_fence != gpu->active_fence) 1802 return -EBUSY; 1803 1804 /* Check whether the hardware (except FE) is idle */ 1805 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1806 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1807 if (idle != mask) 1808 return -EBUSY; 1809 1810 return etnaviv_gpu_hw_suspend(gpu); 1811 } 1812 1813 static int etnaviv_gpu_rpm_resume(struct device *dev) 1814 { 1815 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1816 int ret; 1817 1818 ret = etnaviv_gpu_clk_enable(gpu); 1819 if (ret) 1820 return ret; 1821 1822 /* Re-initialise the basic hardware state */ 1823 if (gpu->drm && gpu->buffer) { 1824 ret = etnaviv_gpu_hw_resume(gpu); 1825 if (ret) { 1826 etnaviv_gpu_clk_disable(gpu); 1827 return ret; 1828 } 1829 } 1830 1831 return 0; 1832 } 1833 #endif 1834 1835 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1836 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1837 NULL) 1838 }; 1839 1840 struct platform_driver etnaviv_gpu_driver = { 1841 .driver = { 1842 .name = "etnaviv-gpu", 1843 .owner = THIS_MODULE, 1844 .pm = &etnaviv_gpu_pm_ops, 1845 .of_match_table = etnaviv_gpu_match, 1846 }, 1847 .probe = etnaviv_gpu_platform_probe, 1848 .remove = etnaviv_gpu_platform_remove, 1849 .id_table = gpu_ids, 1850 }; 1851