1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2015-2018 Etnaviv Project
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17 
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29 
30 static const struct platform_device_id gpu_ids[] = {
31 	{ .name = "etnaviv-gpu,2d" },
32 	{ },
33 };
34 
35 /*
36  * Driver functions:
37  */
38 
39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40 {
41 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42 
43 	switch (param) {
44 	case ETNAVIV_PARAM_GPU_MODEL:
45 		*value = gpu->identity.model;
46 		break;
47 
48 	case ETNAVIV_PARAM_GPU_REVISION:
49 		*value = gpu->identity.revision;
50 		break;
51 
52 	case ETNAVIV_PARAM_GPU_FEATURES_0:
53 		*value = gpu->identity.features;
54 		break;
55 
56 	case ETNAVIV_PARAM_GPU_FEATURES_1:
57 		*value = gpu->identity.minor_features0;
58 		break;
59 
60 	case ETNAVIV_PARAM_GPU_FEATURES_2:
61 		*value = gpu->identity.minor_features1;
62 		break;
63 
64 	case ETNAVIV_PARAM_GPU_FEATURES_3:
65 		*value = gpu->identity.minor_features2;
66 		break;
67 
68 	case ETNAVIV_PARAM_GPU_FEATURES_4:
69 		*value = gpu->identity.minor_features3;
70 		break;
71 
72 	case ETNAVIV_PARAM_GPU_FEATURES_5:
73 		*value = gpu->identity.minor_features4;
74 		break;
75 
76 	case ETNAVIV_PARAM_GPU_FEATURES_6:
77 		*value = gpu->identity.minor_features5;
78 		break;
79 
80 	case ETNAVIV_PARAM_GPU_FEATURES_7:
81 		*value = gpu->identity.minor_features6;
82 		break;
83 
84 	case ETNAVIV_PARAM_GPU_FEATURES_8:
85 		*value = gpu->identity.minor_features7;
86 		break;
87 
88 	case ETNAVIV_PARAM_GPU_FEATURES_9:
89 		*value = gpu->identity.minor_features8;
90 		break;
91 
92 	case ETNAVIV_PARAM_GPU_FEATURES_10:
93 		*value = gpu->identity.minor_features9;
94 		break;
95 
96 	case ETNAVIV_PARAM_GPU_FEATURES_11:
97 		*value = gpu->identity.minor_features10;
98 		break;
99 
100 	case ETNAVIV_PARAM_GPU_FEATURES_12:
101 		*value = gpu->identity.minor_features11;
102 		break;
103 
104 	case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 		*value = gpu->identity.stream_count;
106 		break;
107 
108 	case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 		*value = gpu->identity.register_max;
110 		break;
111 
112 	case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 		*value = gpu->identity.thread_count;
114 		break;
115 
116 	case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 		*value = gpu->identity.vertex_cache_size;
118 		break;
119 
120 	case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 		*value = gpu->identity.shader_core_count;
122 		break;
123 
124 	case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 		*value = gpu->identity.pixel_pipes;
126 		break;
127 
128 	case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 		*value = gpu->identity.vertex_output_buffer_size;
130 		break;
131 
132 	case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 		*value = gpu->identity.buffer_size;
134 		break;
135 
136 	case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 		*value = gpu->identity.instruction_count;
138 		break;
139 
140 	case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 		*value = gpu->identity.num_constants;
142 		break;
143 
144 	case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 		*value = gpu->identity.varyings_count;
146 		break;
147 
148 	case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 		if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 			*value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 		else
152 			*value = ~0ULL;
153 		break;
154 
155 	case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 		*value = gpu->identity.product_id;
157 		break;
158 
159 	case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 		*value = gpu->identity.customer_id;
161 		break;
162 
163 	case ETNAVIV_PARAM_GPU_ECO_ID:
164 		*value = gpu->identity.eco_id;
165 		break;
166 
167 	default:
168 		DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 		return -EINVAL;
170 	}
171 
172 	return 0;
173 }
174 
175 
176 #define etnaviv_is_model_rev(gpu, mod, rev) \
177 	((gpu)->identity.model == chipModel_##mod && \
178 	 (gpu)->identity.revision == rev)
179 #define etnaviv_field(val, field) \
180 	(((val) & field##__MASK) >> field##__SHIFT)
181 
182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
183 {
184 	if (gpu->identity.minor_features0 &
185 	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
186 		u32 specs[4];
187 		unsigned int streams;
188 
189 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
190 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
191 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
192 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
193 
194 		gpu->identity.stream_count = etnaviv_field(specs[0],
195 					VIVS_HI_CHIP_SPECS_STREAM_COUNT);
196 		gpu->identity.register_max = etnaviv_field(specs[0],
197 					VIVS_HI_CHIP_SPECS_REGISTER_MAX);
198 		gpu->identity.thread_count = etnaviv_field(specs[0],
199 					VIVS_HI_CHIP_SPECS_THREAD_COUNT);
200 		gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
201 					VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
202 		gpu->identity.shader_core_count = etnaviv_field(specs[0],
203 					VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
204 		gpu->identity.pixel_pipes = etnaviv_field(specs[0],
205 					VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
206 		gpu->identity.vertex_output_buffer_size =
207 			etnaviv_field(specs[0],
208 				VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
209 
210 		gpu->identity.buffer_size = etnaviv_field(specs[1],
211 					VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
212 		gpu->identity.instruction_count = etnaviv_field(specs[1],
213 					VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
214 		gpu->identity.num_constants = etnaviv_field(specs[1],
215 					VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
216 
217 		gpu->identity.varyings_count = etnaviv_field(specs[2],
218 					VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
219 
220 		/* This overrides the value from older register if non-zero */
221 		streams = etnaviv_field(specs[3],
222 					VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
223 		if (streams)
224 			gpu->identity.stream_count = streams;
225 	}
226 
227 	/* Fill in the stream count if not specified */
228 	if (gpu->identity.stream_count == 0) {
229 		if (gpu->identity.model >= 0x1000)
230 			gpu->identity.stream_count = 4;
231 		else
232 			gpu->identity.stream_count = 1;
233 	}
234 
235 	/* Convert the register max value */
236 	if (gpu->identity.register_max)
237 		gpu->identity.register_max = 1 << gpu->identity.register_max;
238 	else if (gpu->identity.model == chipModel_GC400)
239 		gpu->identity.register_max = 32;
240 	else
241 		gpu->identity.register_max = 64;
242 
243 	/* Convert thread count */
244 	if (gpu->identity.thread_count)
245 		gpu->identity.thread_count = 1 << gpu->identity.thread_count;
246 	else if (gpu->identity.model == chipModel_GC400)
247 		gpu->identity.thread_count = 64;
248 	else if (gpu->identity.model == chipModel_GC500 ||
249 		 gpu->identity.model == chipModel_GC530)
250 		gpu->identity.thread_count = 128;
251 	else
252 		gpu->identity.thread_count = 256;
253 
254 	if (gpu->identity.vertex_cache_size == 0)
255 		gpu->identity.vertex_cache_size = 8;
256 
257 	if (gpu->identity.shader_core_count == 0) {
258 		if (gpu->identity.model >= 0x1000)
259 			gpu->identity.shader_core_count = 2;
260 		else
261 			gpu->identity.shader_core_count = 1;
262 	}
263 
264 	if (gpu->identity.pixel_pipes == 0)
265 		gpu->identity.pixel_pipes = 1;
266 
267 	/* Convert virtex buffer size */
268 	if (gpu->identity.vertex_output_buffer_size) {
269 		gpu->identity.vertex_output_buffer_size =
270 			1 << gpu->identity.vertex_output_buffer_size;
271 	} else if (gpu->identity.model == chipModel_GC400) {
272 		if (gpu->identity.revision < 0x4000)
273 			gpu->identity.vertex_output_buffer_size = 512;
274 		else if (gpu->identity.revision < 0x4200)
275 			gpu->identity.vertex_output_buffer_size = 256;
276 		else
277 			gpu->identity.vertex_output_buffer_size = 128;
278 	} else {
279 		gpu->identity.vertex_output_buffer_size = 512;
280 	}
281 
282 	switch (gpu->identity.instruction_count) {
283 	case 0:
284 		if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
285 		    gpu->identity.model == chipModel_GC880)
286 			gpu->identity.instruction_count = 512;
287 		else
288 			gpu->identity.instruction_count = 256;
289 		break;
290 
291 	case 1:
292 		gpu->identity.instruction_count = 1024;
293 		break;
294 
295 	case 2:
296 		gpu->identity.instruction_count = 2048;
297 		break;
298 
299 	default:
300 		gpu->identity.instruction_count = 256;
301 		break;
302 	}
303 
304 	if (gpu->identity.num_constants == 0)
305 		gpu->identity.num_constants = 168;
306 
307 	if (gpu->identity.varyings_count == 0) {
308 		if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
309 			gpu->identity.varyings_count = 12;
310 		else
311 			gpu->identity.varyings_count = 8;
312 	}
313 
314 	/*
315 	 * For some cores, two varyings are consumed for position, so the
316 	 * maximum varying count needs to be reduced by one.
317 	 */
318 	if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319 	    etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320 	    etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321 	    etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322 	    etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323 	    etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324 	    etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325 	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326 	    etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327 	    etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328 	    etnaviv_is_model_rev(gpu, GC880, 0x5106))
329 		gpu->identity.varyings_count -= 1;
330 }
331 
332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
333 {
334 	u32 chipIdentity;
335 
336 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
337 
338 	/* Special case for older graphic cores. */
339 	if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
340 		gpu->identity.model    = chipModel_GC500;
341 		gpu->identity.revision = etnaviv_field(chipIdentity,
342 					 VIVS_HI_CHIP_IDENTITY_REVISION);
343 	} else {
344 		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
345 
346 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
347 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
348 		gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
349 
350 		/*
351 		 * Reading these two registers on GC600 rev 0x19 result in a
352 		 * unhandled fault: external abort on non-linefetch
353 		 */
354 		if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
355 			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356 			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357 		}
358 
359 		/*
360 		 * !!!! HACK ALERT !!!!
361 		 * Because people change device IDs without letting software
362 		 * know about it - here is the hack to make it all look the
363 		 * same.  Only for GC400 family.
364 		 */
365 		if ((gpu->identity.model & 0xff00) == 0x0400 &&
366 		    gpu->identity.model != chipModel_GC420) {
367 			gpu->identity.model = gpu->identity.model & 0x0400;
368 		}
369 
370 		/* Another special case */
371 		if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
372 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373 
374 			if (chipDate == 0x20080814 && chipTime == 0x12051100) {
375 				/*
376 				 * This IP has an ECO; put the correct
377 				 * revision in it.
378 				 */
379 				gpu->identity.revision = 0x1051;
380 			}
381 		}
382 
383 		/*
384 		 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
385 		 * reality it's just a re-branded GC3000. We can identify this
386 		 * core by the upper half of the revision register being all 1.
387 		 * Fix model/rev here, so all other places can refer to this
388 		 * core by its real identity.
389 		 */
390 		if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
391 			gpu->identity.model = chipModel_GC3000;
392 			gpu->identity.revision &= 0xffff;
393 		}
394 
395 		if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
396 			gpu->identity.eco_id = 1;
397 
398 		if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
399 			gpu->identity.eco_id = 1;
400 	}
401 
402 	dev_info(gpu->dev, "model: GC%x, revision: %x\n",
403 		 gpu->identity.model, gpu->identity.revision);
404 
405 	gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
406 	/*
407 	 * If there is a match in the HWDB, we aren't interested in the
408 	 * remaining register values, as they might be wrong.
409 	 */
410 	if (etnaviv_fill_identity_from_hwdb(gpu))
411 		return;
412 
413 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
414 
415 	/* Disable fast clear on GC700. */
416 	if (gpu->identity.model == chipModel_GC700)
417 		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
418 
419 	if ((gpu->identity.model == chipModel_GC500 &&
420 	     gpu->identity.revision < 2) ||
421 	    (gpu->identity.model == chipModel_GC300 &&
422 	     gpu->identity.revision < 0x2000)) {
423 
424 		/*
425 		 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
426 		 * registers.
427 		 */
428 		gpu->identity.minor_features0 = 0;
429 		gpu->identity.minor_features1 = 0;
430 		gpu->identity.minor_features2 = 0;
431 		gpu->identity.minor_features3 = 0;
432 		gpu->identity.minor_features4 = 0;
433 		gpu->identity.minor_features5 = 0;
434 	} else
435 		gpu->identity.minor_features0 =
436 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
437 
438 	if (gpu->identity.minor_features0 &
439 	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
440 		gpu->identity.minor_features1 =
441 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
442 		gpu->identity.minor_features2 =
443 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
444 		gpu->identity.minor_features3 =
445 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
446 		gpu->identity.minor_features4 =
447 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
448 		gpu->identity.minor_features5 =
449 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
450 	}
451 
452 	/* GC600 idle register reports zero bits where modules aren't present */
453 	if (gpu->identity.model == chipModel_GC600)
454 		gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
455 				 VIVS_HI_IDLE_STATE_RA |
456 				 VIVS_HI_IDLE_STATE_SE |
457 				 VIVS_HI_IDLE_STATE_PA |
458 				 VIVS_HI_IDLE_STATE_SH |
459 				 VIVS_HI_IDLE_STATE_PE |
460 				 VIVS_HI_IDLE_STATE_DE |
461 				 VIVS_HI_IDLE_STATE_FE;
462 
463 	etnaviv_hw_specs(gpu);
464 }
465 
466 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
467 {
468 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
469 		  VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
470 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
471 }
472 
473 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
474 {
475 	if (gpu->identity.minor_features2 &
476 	    chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
477 		clk_set_rate(gpu->clk_core,
478 			     gpu->base_rate_core >> gpu->freq_scale);
479 		clk_set_rate(gpu->clk_shader,
480 			     gpu->base_rate_shader >> gpu->freq_scale);
481 	} else {
482 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
483 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
484 
485 		clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
486 		clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
487 		etnaviv_gpu_load_clock(gpu, clock);
488 	}
489 }
490 
491 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
492 {
493 	u32 control, idle;
494 	unsigned long timeout;
495 	bool failed = true;
496 
497 	/* We hope that the GPU resets in under one second */
498 	timeout = jiffies + msecs_to_jiffies(1000);
499 
500 	while (time_is_after_jiffies(timeout)) {
501 		/* enable clock */
502 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
503 		control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
504 		etnaviv_gpu_load_clock(gpu, control);
505 
506 		/* isolate the GPU. */
507 		control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
508 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
509 
510 		if (gpu->sec_mode == ETNA_SEC_KERNEL) {
511 			gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
512 			          VIVS_MMUv2_AHB_CONTROL_RESET);
513 		} else {
514 			/* set soft reset. */
515 			control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
516 			gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
517 		}
518 
519 		/* wait for reset. */
520 		usleep_range(10, 20);
521 
522 		/* reset soft reset bit. */
523 		control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
524 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
525 
526 		/* reset GPU isolation. */
527 		control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
528 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
529 
530 		/* read idle register. */
531 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
532 
533 		/* try resetting again if FE is not idle */
534 		if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
535 			dev_dbg(gpu->dev, "FE is not idle\n");
536 			continue;
537 		}
538 
539 		/* read reset register. */
540 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
541 
542 		/* is the GPU idle? */
543 		if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
544 		    ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
545 			dev_dbg(gpu->dev, "GPU is not idle\n");
546 			continue;
547 		}
548 
549 		/* disable debug registers, as they are not normally needed */
550 		control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
551 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
552 
553 		failed = false;
554 		break;
555 	}
556 
557 	if (failed) {
558 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
559 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
560 
561 		dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
562 			idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
563 			control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
564 			control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
565 
566 		return -EBUSY;
567 	}
568 
569 	/* We rely on the GPU running, so program the clock */
570 	etnaviv_gpu_update_clock(gpu);
571 
572 	gpu->fe_running = false;
573 	gpu->exec_state = -1;
574 	if (gpu->mmu_context)
575 		etnaviv_iommu_context_put(gpu->mmu_context);
576 	gpu->mmu_context = NULL;
577 
578 	return 0;
579 }
580 
581 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
582 {
583 	u32 pmc, ppc;
584 
585 	/* enable clock gating */
586 	ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
587 	ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
588 
589 	/* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
590 	if (gpu->identity.revision == 0x4301 ||
591 	    gpu->identity.revision == 0x4302)
592 		ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
593 
594 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
595 
596 	pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
597 
598 	/* Disable PA clock gating for GC400+ without bugfix except for GC420 */
599 	if (gpu->identity.model >= chipModel_GC400 &&
600 	    gpu->identity.model != chipModel_GC420 &&
601 	    !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
602 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
603 
604 	/*
605 	 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
606 	 * present without a bug fix.
607 	 */
608 	if (gpu->identity.revision < 0x5000 &&
609 	    gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
610 	    !(gpu->identity.minor_features1 &
611 	      chipMinorFeatures1_DISABLE_PE_GATING))
612 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
613 
614 	if (gpu->identity.revision < 0x5422)
615 		pmc |= BIT(15); /* Unknown bit */
616 
617 	/* Disable TX clock gating on affected core revisions. */
618 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
619 	    etnaviv_is_model_rev(gpu, GC2000, 0x5108))
620 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
621 
622 	/* Disable SE, RA and TX clock gating on affected core revisions. */
623 	if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
624 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
625 		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |
626 		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
627 
628 	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
629 	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
630 
631 	gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
632 }
633 
634 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
635 {
636 	gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
637 	gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
638 		  VIVS_FE_COMMAND_CONTROL_ENABLE |
639 		  VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
640 
641 	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
642 		gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
643 			  VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
644 			  VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
645 	}
646 
647 	gpu->fe_running = true;
648 }
649 
650 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
651 					  struct etnaviv_iommu_context *context)
652 {
653 	u16 prefetch;
654 	u32 address;
655 
656 	/* setup the MMU */
657 	etnaviv_iommu_restore(gpu, context);
658 
659 	/* Start command processor */
660 	prefetch = etnaviv_buffer_init(gpu);
661 	address = etnaviv_cmdbuf_get_va(&gpu->buffer,
662 					&gpu->mmu_context->cmdbuf_mapping);
663 
664 	etnaviv_gpu_start_fe(gpu, address, prefetch);
665 }
666 
667 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
668 {
669 	/*
670 	 * Base value for VIVS_PM_PULSE_EATER register on models where it
671 	 * cannot be read, extracted from vivante kernel driver.
672 	 */
673 	u32 pulse_eater = 0x01590880;
674 
675 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
676 	    etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
677 		pulse_eater |= BIT(23);
678 
679 	}
680 
681 	if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
682 	    etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
683 		pulse_eater &= ~BIT(16);
684 		pulse_eater |= BIT(17);
685 	}
686 
687 	if ((gpu->identity.revision > 0x5420) &&
688 	    (gpu->identity.features & chipFeatures_PIPE_3D))
689 	{
690 		/* Performance fix: disable internal DFS */
691 		pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
692 		pulse_eater |= BIT(18);
693 	}
694 
695 	gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
696 }
697 
698 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
699 {
700 	if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
701 	     etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
702 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
703 		u32 mc_memory_debug;
704 
705 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
706 
707 		if (gpu->identity.revision == 0x5007)
708 			mc_memory_debug |= 0x0c;
709 		else
710 			mc_memory_debug |= 0x08;
711 
712 		gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
713 	}
714 
715 	/* enable module-level clock gating */
716 	etnaviv_gpu_enable_mlcg(gpu);
717 
718 	/*
719 	 * Update GPU AXI cache atttribute to "cacheable, no allocate".
720 	 * This is necessary to prevent the iMX6 SoC locking up.
721 	 */
722 	gpu_write(gpu, VIVS_HI_AXI_CONFIG,
723 		  VIVS_HI_AXI_CONFIG_AWCACHE(2) |
724 		  VIVS_HI_AXI_CONFIG_ARCACHE(2));
725 
726 	/* GC2000 rev 5108 needs a special bus config */
727 	if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
728 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
729 		bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
730 				VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
731 		bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
732 			      VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
733 		gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
734 	}
735 
736 	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
737 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
738 		val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
739 		gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
740 	}
741 
742 	/* setup the pulse eater */
743 	etnaviv_gpu_setup_pulse_eater(gpu);
744 
745 	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
746 }
747 
748 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
749 {
750 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
751 	dma_addr_t cmdbuf_paddr;
752 	int ret, i;
753 
754 	ret = pm_runtime_get_sync(gpu->dev);
755 	if (ret < 0) {
756 		dev_err(gpu->dev, "Failed to enable GPU power domain\n");
757 		goto pm_put;
758 	}
759 
760 	etnaviv_hw_identify(gpu);
761 
762 	if (gpu->identity.model == 0) {
763 		dev_err(gpu->dev, "Unknown GPU model\n");
764 		ret = -ENXIO;
765 		goto fail;
766 	}
767 
768 	/* Exclude VG cores with FE2.0 */
769 	if (gpu->identity.features & chipFeatures_PIPE_VG &&
770 	    gpu->identity.features & chipFeatures_FE20) {
771 		dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
772 		ret = -ENXIO;
773 		goto fail;
774 	}
775 
776 	/*
777 	 * On cores with security features supported, we claim control over the
778 	 * security states.
779 	 */
780 	if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
781 	    (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
782 		gpu->sec_mode = ETNA_SEC_KERNEL;
783 
784 	ret = etnaviv_hw_reset(gpu);
785 	if (ret) {
786 		dev_err(gpu->dev, "GPU reset failed\n");
787 		goto fail;
788 	}
789 
790 	ret = etnaviv_iommu_global_init(gpu);
791 	if (ret)
792 		goto fail;
793 
794 	/*
795 	 * If the GPU is part of a system with DMA addressing limitations,
796 	 * request pages for our SHM backend buffers from the DMA32 zone to
797 	 * hopefully avoid performance killing SWIOTLB bounce buffering.
798 	 */
799 	if (dma_addressing_limited(gpu->dev))
800 		priv->shm_gfp_mask |= GFP_DMA32;
801 
802 	/* Create buffer: */
803 	ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
804 				  PAGE_SIZE);
805 	if (ret) {
806 		dev_err(gpu->dev, "could not create command buffer\n");
807 		goto fail;
808 	}
809 
810 	/*
811 	 * Set the GPU linear window to cover the cmdbuf region, as the GPU
812 	 * won't be able to start execution otherwise. The alignment to 128M is
813 	 * chosen arbitrarily but helps in debugging, as the MMU offset
814 	 * calculations are much more straight forward this way.
815 	 *
816 	 * On MC1.0 cores the linear window offset is ignored by the TS engine,
817 	 * leading to inconsistent memory views. Avoid using the offset on those
818 	 * cores if possible, otherwise disable the TS feature.
819 	 */
820 	cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
821 
822 	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
823 	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
824 		if (cmdbuf_paddr >= SZ_2G)
825 			priv->mmu_global->memory_base = SZ_2G;
826 		else
827 			priv->mmu_global->memory_base = cmdbuf_paddr;
828 	} else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
829 		dev_info(gpu->dev,
830 			 "Need to move linear window on MC1.0, disabling TS\n");
831 		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
832 		priv->mmu_global->memory_base = SZ_2G;
833 	}
834 
835 	/* Setup event management */
836 	spin_lock_init(&gpu->event_spinlock);
837 	init_completion(&gpu->event_free);
838 	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
839 	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
840 		complete(&gpu->event_free);
841 
842 	/* Now program the hardware */
843 	mutex_lock(&gpu->lock);
844 	etnaviv_gpu_hw_init(gpu);
845 	mutex_unlock(&gpu->lock);
846 
847 	pm_runtime_mark_last_busy(gpu->dev);
848 	pm_runtime_put_autosuspend(gpu->dev);
849 
850 	gpu->initialized = true;
851 
852 	return 0;
853 
854 fail:
855 	pm_runtime_mark_last_busy(gpu->dev);
856 pm_put:
857 	pm_runtime_put_autosuspend(gpu->dev);
858 
859 	return ret;
860 }
861 
862 #ifdef CONFIG_DEBUG_FS
863 struct dma_debug {
864 	u32 address[2];
865 	u32 state[2];
866 };
867 
868 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
869 {
870 	u32 i;
871 
872 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
873 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
874 
875 	for (i = 0; i < 500; i++) {
876 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
877 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
878 
879 		if (debug->address[0] != debug->address[1])
880 			break;
881 
882 		if (debug->state[0] != debug->state[1])
883 			break;
884 	}
885 }
886 
887 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
888 {
889 	struct dma_debug debug;
890 	u32 dma_lo, dma_hi, axi, idle;
891 	int ret;
892 
893 	seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
894 
895 	ret = pm_runtime_get_sync(gpu->dev);
896 	if (ret < 0)
897 		goto pm_put;
898 
899 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
900 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
901 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
902 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
903 
904 	verify_dma(gpu, &debug);
905 
906 	seq_puts(m, "\tidentity\n");
907 	seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
908 	seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
909 	seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
910 	seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
911 	seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
912 
913 	seq_puts(m, "\tfeatures\n");
914 	seq_printf(m, "\t major_features: 0x%08x\n",
915 		   gpu->identity.features);
916 	seq_printf(m, "\t minor_features0: 0x%08x\n",
917 		   gpu->identity.minor_features0);
918 	seq_printf(m, "\t minor_features1: 0x%08x\n",
919 		   gpu->identity.minor_features1);
920 	seq_printf(m, "\t minor_features2: 0x%08x\n",
921 		   gpu->identity.minor_features2);
922 	seq_printf(m, "\t minor_features3: 0x%08x\n",
923 		   gpu->identity.minor_features3);
924 	seq_printf(m, "\t minor_features4: 0x%08x\n",
925 		   gpu->identity.minor_features4);
926 	seq_printf(m, "\t minor_features5: 0x%08x\n",
927 		   gpu->identity.minor_features5);
928 	seq_printf(m, "\t minor_features6: 0x%08x\n",
929 		   gpu->identity.minor_features6);
930 	seq_printf(m, "\t minor_features7: 0x%08x\n",
931 		   gpu->identity.minor_features7);
932 	seq_printf(m, "\t minor_features8: 0x%08x\n",
933 		   gpu->identity.minor_features8);
934 	seq_printf(m, "\t minor_features9: 0x%08x\n",
935 		   gpu->identity.minor_features9);
936 	seq_printf(m, "\t minor_features10: 0x%08x\n",
937 		   gpu->identity.minor_features10);
938 	seq_printf(m, "\t minor_features11: 0x%08x\n",
939 		   gpu->identity.minor_features11);
940 
941 	seq_puts(m, "\tspecs\n");
942 	seq_printf(m, "\t stream_count:  %d\n",
943 			gpu->identity.stream_count);
944 	seq_printf(m, "\t register_max: %d\n",
945 			gpu->identity.register_max);
946 	seq_printf(m, "\t thread_count: %d\n",
947 			gpu->identity.thread_count);
948 	seq_printf(m, "\t vertex_cache_size: %d\n",
949 			gpu->identity.vertex_cache_size);
950 	seq_printf(m, "\t shader_core_count: %d\n",
951 			gpu->identity.shader_core_count);
952 	seq_printf(m, "\t pixel_pipes: %d\n",
953 			gpu->identity.pixel_pipes);
954 	seq_printf(m, "\t vertex_output_buffer_size: %d\n",
955 			gpu->identity.vertex_output_buffer_size);
956 	seq_printf(m, "\t buffer_size: %d\n",
957 			gpu->identity.buffer_size);
958 	seq_printf(m, "\t instruction_count: %d\n",
959 			gpu->identity.instruction_count);
960 	seq_printf(m, "\t num_constants: %d\n",
961 			gpu->identity.num_constants);
962 	seq_printf(m, "\t varyings_count: %d\n",
963 			gpu->identity.varyings_count);
964 
965 	seq_printf(m, "\taxi: 0x%08x\n", axi);
966 	seq_printf(m, "\tidle: 0x%08x\n", idle);
967 	idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
968 	if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
969 		seq_puts(m, "\t FE is not idle\n");
970 	if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
971 		seq_puts(m, "\t DE is not idle\n");
972 	if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
973 		seq_puts(m, "\t PE is not idle\n");
974 	if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
975 		seq_puts(m, "\t SH is not idle\n");
976 	if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
977 		seq_puts(m, "\t PA is not idle\n");
978 	if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
979 		seq_puts(m, "\t SE is not idle\n");
980 	if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
981 		seq_puts(m, "\t RA is not idle\n");
982 	if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
983 		seq_puts(m, "\t TX is not idle\n");
984 	if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
985 		seq_puts(m, "\t VG is not idle\n");
986 	if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
987 		seq_puts(m, "\t IM is not idle\n");
988 	if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
989 		seq_puts(m, "\t FP is not idle\n");
990 	if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
991 		seq_puts(m, "\t TS is not idle\n");
992 	if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
993 		seq_puts(m, "\t BL is not idle\n");
994 	if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
995 		seq_puts(m, "\t ASYNCFE is not idle\n");
996 	if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
997 		seq_puts(m, "\t MC is not idle\n");
998 	if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
999 		seq_puts(m, "\t PPA is not idle\n");
1000 	if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1001 		seq_puts(m, "\t WD is not idle\n");
1002 	if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1003 		seq_puts(m, "\t NN is not idle\n");
1004 	if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1005 		seq_puts(m, "\t TP is not idle\n");
1006 	if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1007 		seq_puts(m, "\t AXI low power mode\n");
1008 
1009 	if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1010 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1011 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1012 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1013 
1014 		seq_puts(m, "\tMC\n");
1015 		seq_printf(m, "\t read0: 0x%08x\n", read0);
1016 		seq_printf(m, "\t read1: 0x%08x\n", read1);
1017 		seq_printf(m, "\t write: 0x%08x\n", write);
1018 	}
1019 
1020 	seq_puts(m, "\tDMA ");
1021 
1022 	if (debug.address[0] == debug.address[1] &&
1023 	    debug.state[0] == debug.state[1]) {
1024 		seq_puts(m, "seems to be stuck\n");
1025 	} else if (debug.address[0] == debug.address[1]) {
1026 		seq_puts(m, "address is constant\n");
1027 	} else {
1028 		seq_puts(m, "is running\n");
1029 	}
1030 
1031 	seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1032 	seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1033 	seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1034 	seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1035 	seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1036 		   dma_lo, dma_hi);
1037 
1038 	ret = 0;
1039 
1040 	pm_runtime_mark_last_busy(gpu->dev);
1041 pm_put:
1042 	pm_runtime_put_autosuspend(gpu->dev);
1043 
1044 	return ret;
1045 }
1046 #endif
1047 
1048 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
1049 {
1050 	unsigned int i;
1051 
1052 	dev_err(gpu->dev, "recover hung GPU!\n");
1053 
1054 	if (pm_runtime_get_sync(gpu->dev) < 0)
1055 		goto pm_put;
1056 
1057 	mutex_lock(&gpu->lock);
1058 
1059 	etnaviv_hw_reset(gpu);
1060 
1061 	/* complete all events, the GPU won't do it after the reset */
1062 	spin_lock(&gpu->event_spinlock);
1063 	for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1064 		complete(&gpu->event_free);
1065 	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1066 	spin_unlock(&gpu->event_spinlock);
1067 
1068 	etnaviv_gpu_hw_init(gpu);
1069 
1070 	mutex_unlock(&gpu->lock);
1071 	pm_runtime_mark_last_busy(gpu->dev);
1072 pm_put:
1073 	pm_runtime_put_autosuspend(gpu->dev);
1074 }
1075 
1076 /* fence object management */
1077 struct etnaviv_fence {
1078 	struct etnaviv_gpu *gpu;
1079 	struct dma_fence base;
1080 };
1081 
1082 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1083 {
1084 	return container_of(fence, struct etnaviv_fence, base);
1085 }
1086 
1087 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1088 {
1089 	return "etnaviv";
1090 }
1091 
1092 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1093 {
1094 	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1095 
1096 	return dev_name(f->gpu->dev);
1097 }
1098 
1099 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1100 {
1101 	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1102 
1103 	return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1104 }
1105 
1106 static void etnaviv_fence_release(struct dma_fence *fence)
1107 {
1108 	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1109 
1110 	kfree_rcu(f, base.rcu);
1111 }
1112 
1113 static const struct dma_fence_ops etnaviv_fence_ops = {
1114 	.get_driver_name = etnaviv_fence_get_driver_name,
1115 	.get_timeline_name = etnaviv_fence_get_timeline_name,
1116 	.signaled = etnaviv_fence_signaled,
1117 	.release = etnaviv_fence_release,
1118 };
1119 
1120 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1121 {
1122 	struct etnaviv_fence *f;
1123 
1124 	/*
1125 	 * GPU lock must already be held, otherwise fence completion order might
1126 	 * not match the seqno order assigned here.
1127 	 */
1128 	lockdep_assert_held(&gpu->lock);
1129 
1130 	f = kzalloc(sizeof(*f), GFP_KERNEL);
1131 	if (!f)
1132 		return NULL;
1133 
1134 	f->gpu = gpu;
1135 
1136 	dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1137 		       gpu->fence_context, ++gpu->next_fence);
1138 
1139 	return &f->base;
1140 }
1141 
1142 /* returns true if fence a comes after fence b */
1143 static inline bool fence_after(u32 a, u32 b)
1144 {
1145 	return (s32)(a - b) > 0;
1146 }
1147 
1148 /*
1149  * event management:
1150  */
1151 
1152 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1153 	unsigned int *events)
1154 {
1155 	unsigned long timeout = msecs_to_jiffies(10 * 10000);
1156 	unsigned i, acquired = 0;
1157 
1158 	for (i = 0; i < nr_events; i++) {
1159 		unsigned long ret;
1160 
1161 		ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1162 
1163 		if (!ret) {
1164 			dev_err(gpu->dev, "wait_for_completion_timeout failed");
1165 			goto out;
1166 		}
1167 
1168 		acquired++;
1169 		timeout = ret;
1170 	}
1171 
1172 	spin_lock(&gpu->event_spinlock);
1173 
1174 	for (i = 0; i < nr_events; i++) {
1175 		int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1176 
1177 		events[i] = event;
1178 		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1179 		set_bit(event, gpu->event_bitmap);
1180 	}
1181 
1182 	spin_unlock(&gpu->event_spinlock);
1183 
1184 	return 0;
1185 
1186 out:
1187 	for (i = 0; i < acquired; i++)
1188 		complete(&gpu->event_free);
1189 
1190 	return -EBUSY;
1191 }
1192 
1193 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1194 {
1195 	if (!test_bit(event, gpu->event_bitmap)) {
1196 		dev_warn(gpu->dev, "event %u is already marked as free",
1197 			 event);
1198 	} else {
1199 		clear_bit(event, gpu->event_bitmap);
1200 		complete(&gpu->event_free);
1201 	}
1202 }
1203 
1204 /*
1205  * Cmdstream submission/retirement:
1206  */
1207 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1208 	u32 id, struct drm_etnaviv_timespec *timeout)
1209 {
1210 	struct dma_fence *fence;
1211 	int ret;
1212 
1213 	/*
1214 	 * Look up the fence and take a reference. We might still find a fence
1215 	 * whose refcount has already dropped to zero. dma_fence_get_rcu
1216 	 * pretends we didn't find a fence in that case.
1217 	 */
1218 	rcu_read_lock();
1219 	fence = idr_find(&gpu->fence_idr, id);
1220 	if (fence)
1221 		fence = dma_fence_get_rcu(fence);
1222 	rcu_read_unlock();
1223 
1224 	if (!fence)
1225 		return 0;
1226 
1227 	if (!timeout) {
1228 		/* No timeout was requested: just test for completion */
1229 		ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1230 	} else {
1231 		unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1232 
1233 		ret = dma_fence_wait_timeout(fence, true, remaining);
1234 		if (ret == 0)
1235 			ret = -ETIMEDOUT;
1236 		else if (ret != -ERESTARTSYS)
1237 			ret = 0;
1238 
1239 	}
1240 
1241 	dma_fence_put(fence);
1242 	return ret;
1243 }
1244 
1245 /*
1246  * Wait for an object to become inactive.  This, on it's own, is not race
1247  * free: the object is moved by the scheduler off the active list, and
1248  * then the iova is put.  Moreover, the object could be re-submitted just
1249  * after we notice that it's become inactive.
1250  *
1251  * Although the retirement happens under the gpu lock, we don't want to hold
1252  * that lock in this function while waiting.
1253  */
1254 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1255 	struct etnaviv_gem_object *etnaviv_obj,
1256 	struct drm_etnaviv_timespec *timeout)
1257 {
1258 	unsigned long remaining;
1259 	long ret;
1260 
1261 	if (!timeout)
1262 		return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1263 
1264 	remaining = etnaviv_timeout_to_jiffies(timeout);
1265 
1266 	ret = wait_event_interruptible_timeout(gpu->fence_event,
1267 					       !is_active(etnaviv_obj),
1268 					       remaining);
1269 	if (ret > 0)
1270 		return 0;
1271 	else if (ret == -ERESTARTSYS)
1272 		return -ERESTARTSYS;
1273 	else
1274 		return -ETIMEDOUT;
1275 }
1276 
1277 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1278 	struct etnaviv_event *event, unsigned int flags)
1279 {
1280 	const struct etnaviv_gem_submit *submit = event->submit;
1281 	unsigned int i;
1282 
1283 	for (i = 0; i < submit->nr_pmrs; i++) {
1284 		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1285 
1286 		if (pmr->flags == flags)
1287 			etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1288 	}
1289 }
1290 
1291 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1292 	struct etnaviv_event *event)
1293 {
1294 	u32 val;
1295 
1296 	/* disable clock gating */
1297 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1298 	val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1299 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1300 
1301 	/* enable debug register */
1302 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1303 	val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1304 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1305 
1306 	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1307 }
1308 
1309 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1310 	struct etnaviv_event *event)
1311 {
1312 	const struct etnaviv_gem_submit *submit = event->submit;
1313 	unsigned int i;
1314 	u32 val;
1315 
1316 	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1317 
1318 	for (i = 0; i < submit->nr_pmrs; i++) {
1319 		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1320 
1321 		*pmr->bo_vma = pmr->sequence;
1322 	}
1323 
1324 	/* disable debug register */
1325 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1326 	val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1327 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1328 
1329 	/* enable clock gating */
1330 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1331 	val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1332 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1333 }
1334 
1335 
1336 /* add bo's to gpu's ring, and kick gpu: */
1337 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1338 {
1339 	struct etnaviv_gpu *gpu = submit->gpu;
1340 	struct dma_fence *gpu_fence;
1341 	unsigned int i, nr_events = 1, event[3];
1342 	int ret;
1343 
1344 	if (!submit->runtime_resumed) {
1345 		ret = pm_runtime_get_sync(gpu->dev);
1346 		if (ret < 0) {
1347 			pm_runtime_put_noidle(gpu->dev);
1348 			return NULL;
1349 		}
1350 		submit->runtime_resumed = true;
1351 	}
1352 
1353 	/*
1354 	 * if there are performance monitor requests we need to have
1355 	 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1356 	 *   requests.
1357 	 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1358 	 *   and update the sequence number for userspace.
1359 	 */
1360 	if (submit->nr_pmrs)
1361 		nr_events = 3;
1362 
1363 	ret = event_alloc(gpu, nr_events, event);
1364 	if (ret) {
1365 		DRM_ERROR("no free events\n");
1366 		pm_runtime_put_noidle(gpu->dev);
1367 		return NULL;
1368 	}
1369 
1370 	mutex_lock(&gpu->lock);
1371 
1372 	gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1373 	if (!gpu_fence) {
1374 		for (i = 0; i < nr_events; i++)
1375 			event_free(gpu, event[i]);
1376 
1377 		goto out_unlock;
1378 	}
1379 
1380 	if (!gpu->fe_running)
1381 		etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1382 
1383 	if (submit->prev_mmu_context)
1384 		etnaviv_iommu_context_put(submit->prev_mmu_context);
1385 	submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1386 
1387 	if (submit->nr_pmrs) {
1388 		gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1389 		kref_get(&submit->refcount);
1390 		gpu->event[event[1]].submit = submit;
1391 		etnaviv_sync_point_queue(gpu, event[1]);
1392 	}
1393 
1394 	gpu->event[event[0]].fence = gpu_fence;
1395 	submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1396 	etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1397 			     event[0], &submit->cmdbuf);
1398 
1399 	if (submit->nr_pmrs) {
1400 		gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1401 		kref_get(&submit->refcount);
1402 		gpu->event[event[2]].submit = submit;
1403 		etnaviv_sync_point_queue(gpu, event[2]);
1404 	}
1405 
1406 out_unlock:
1407 	mutex_unlock(&gpu->lock);
1408 
1409 	return gpu_fence;
1410 }
1411 
1412 static void sync_point_worker(struct work_struct *work)
1413 {
1414 	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1415 					       sync_point_work);
1416 	struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1417 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1418 
1419 	event->sync_point(gpu, event);
1420 	etnaviv_submit_put(event->submit);
1421 	event_free(gpu, gpu->sync_point_event);
1422 
1423 	/* restart FE last to avoid GPU and IRQ racing against this worker */
1424 	etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1425 }
1426 
1427 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1428 {
1429 	u32 status_reg, status;
1430 	int i;
1431 
1432 	if (gpu->sec_mode == ETNA_SEC_NONE)
1433 		status_reg = VIVS_MMUv2_STATUS;
1434 	else
1435 		status_reg = VIVS_MMUv2_SEC_STATUS;
1436 
1437 	status = gpu_read(gpu, status_reg);
1438 	dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1439 
1440 	for (i = 0; i < 4; i++) {
1441 		u32 address_reg;
1442 
1443 		if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1444 			continue;
1445 
1446 		if (gpu->sec_mode == ETNA_SEC_NONE)
1447 			address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1448 		else
1449 			address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1450 
1451 		dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1452 				    gpu_read(gpu, address_reg));
1453 	}
1454 }
1455 
1456 static irqreturn_t irq_handler(int irq, void *data)
1457 {
1458 	struct etnaviv_gpu *gpu = data;
1459 	irqreturn_t ret = IRQ_NONE;
1460 
1461 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1462 
1463 	if (intr != 0) {
1464 		int event;
1465 
1466 		pm_runtime_mark_last_busy(gpu->dev);
1467 
1468 		dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1469 
1470 		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1471 			dev_err(gpu->dev, "AXI bus error\n");
1472 			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1473 		}
1474 
1475 		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1476 			dump_mmu_fault(gpu);
1477 			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1478 		}
1479 
1480 		while ((event = ffs(intr)) != 0) {
1481 			struct dma_fence *fence;
1482 
1483 			event -= 1;
1484 
1485 			intr &= ~(1 << event);
1486 
1487 			dev_dbg(gpu->dev, "event %u\n", event);
1488 
1489 			if (gpu->event[event].sync_point) {
1490 				gpu->sync_point_event = event;
1491 				queue_work(gpu->wq, &gpu->sync_point_work);
1492 			}
1493 
1494 			fence = gpu->event[event].fence;
1495 			if (!fence)
1496 				continue;
1497 
1498 			gpu->event[event].fence = NULL;
1499 
1500 			/*
1501 			 * Events can be processed out of order.  Eg,
1502 			 * - allocate and queue event 0
1503 			 * - allocate event 1
1504 			 * - event 0 completes, we process it
1505 			 * - allocate and queue event 0
1506 			 * - event 1 and event 0 complete
1507 			 * we can end up processing event 0 first, then 1.
1508 			 */
1509 			if (fence_after(fence->seqno, gpu->completed_fence))
1510 				gpu->completed_fence = fence->seqno;
1511 			dma_fence_signal(fence);
1512 
1513 			event_free(gpu, event);
1514 		}
1515 
1516 		ret = IRQ_HANDLED;
1517 	}
1518 
1519 	return ret;
1520 }
1521 
1522 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1523 {
1524 	int ret;
1525 
1526 	ret = clk_prepare_enable(gpu->clk_reg);
1527 	if (ret)
1528 		return ret;
1529 
1530 	ret = clk_prepare_enable(gpu->clk_bus);
1531 	if (ret)
1532 		goto disable_clk_reg;
1533 
1534 	ret = clk_prepare_enable(gpu->clk_core);
1535 	if (ret)
1536 		goto disable_clk_bus;
1537 
1538 	ret = clk_prepare_enable(gpu->clk_shader);
1539 	if (ret)
1540 		goto disable_clk_core;
1541 
1542 	return 0;
1543 
1544 disable_clk_core:
1545 	clk_disable_unprepare(gpu->clk_core);
1546 disable_clk_bus:
1547 	clk_disable_unprepare(gpu->clk_bus);
1548 disable_clk_reg:
1549 	clk_disable_unprepare(gpu->clk_reg);
1550 
1551 	return ret;
1552 }
1553 
1554 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1555 {
1556 	clk_disable_unprepare(gpu->clk_shader);
1557 	clk_disable_unprepare(gpu->clk_core);
1558 	clk_disable_unprepare(gpu->clk_bus);
1559 	clk_disable_unprepare(gpu->clk_reg);
1560 
1561 	return 0;
1562 }
1563 
1564 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1565 {
1566 	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1567 
1568 	do {
1569 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1570 
1571 		if ((idle & gpu->idle_mask) == gpu->idle_mask)
1572 			return 0;
1573 
1574 		if (time_is_before_jiffies(timeout)) {
1575 			dev_warn(gpu->dev,
1576 				 "timed out waiting for idle: idle=0x%x\n",
1577 				 idle);
1578 			return -ETIMEDOUT;
1579 		}
1580 
1581 		udelay(5);
1582 	} while (1);
1583 }
1584 
1585 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1586 {
1587 	if (gpu->initialized && gpu->fe_running) {
1588 		/* Replace the last WAIT with END */
1589 		mutex_lock(&gpu->lock);
1590 		etnaviv_buffer_end(gpu);
1591 		mutex_unlock(&gpu->lock);
1592 
1593 		/*
1594 		 * We know that only the FE is busy here, this should
1595 		 * happen quickly (as the WAIT is only 200 cycles).  If
1596 		 * we fail, just warn and continue.
1597 		 */
1598 		etnaviv_gpu_wait_idle(gpu, 100);
1599 
1600 		gpu->fe_running = false;
1601 	}
1602 
1603 	gpu->exec_state = -1;
1604 
1605 	return etnaviv_gpu_clk_disable(gpu);
1606 }
1607 
1608 #ifdef CONFIG_PM
1609 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1610 {
1611 	int ret;
1612 
1613 	ret = mutex_lock_killable(&gpu->lock);
1614 	if (ret)
1615 		return ret;
1616 
1617 	etnaviv_gpu_update_clock(gpu);
1618 	etnaviv_gpu_hw_init(gpu);
1619 
1620 	mutex_unlock(&gpu->lock);
1621 
1622 	return 0;
1623 }
1624 #endif
1625 
1626 static int
1627 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1628 				  unsigned long *state)
1629 {
1630 	*state = 6;
1631 
1632 	return 0;
1633 }
1634 
1635 static int
1636 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1637 				  unsigned long *state)
1638 {
1639 	struct etnaviv_gpu *gpu = cdev->devdata;
1640 
1641 	*state = gpu->freq_scale;
1642 
1643 	return 0;
1644 }
1645 
1646 static int
1647 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1648 				  unsigned long state)
1649 {
1650 	struct etnaviv_gpu *gpu = cdev->devdata;
1651 
1652 	mutex_lock(&gpu->lock);
1653 	gpu->freq_scale = state;
1654 	if (!pm_runtime_suspended(gpu->dev))
1655 		etnaviv_gpu_update_clock(gpu);
1656 	mutex_unlock(&gpu->lock);
1657 
1658 	return 0;
1659 }
1660 
1661 static const struct thermal_cooling_device_ops cooling_ops = {
1662 	.get_max_state = etnaviv_gpu_cooling_get_max_state,
1663 	.get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1664 	.set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1665 };
1666 
1667 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1668 	void *data)
1669 {
1670 	struct drm_device *drm = data;
1671 	struct etnaviv_drm_private *priv = drm->dev_private;
1672 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1673 	int ret;
1674 
1675 	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1676 		gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1677 				(char *)dev_name(dev), gpu, &cooling_ops);
1678 		if (IS_ERR(gpu->cooling))
1679 			return PTR_ERR(gpu->cooling);
1680 	}
1681 
1682 	gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1683 	if (!gpu->wq) {
1684 		ret = -ENOMEM;
1685 		goto out_thermal;
1686 	}
1687 
1688 	ret = etnaviv_sched_init(gpu);
1689 	if (ret)
1690 		goto out_workqueue;
1691 
1692 #ifdef CONFIG_PM
1693 	ret = pm_runtime_get_sync(gpu->dev);
1694 #else
1695 	ret = etnaviv_gpu_clk_enable(gpu);
1696 #endif
1697 	if (ret < 0)
1698 		goto out_sched;
1699 
1700 
1701 	gpu->drm = drm;
1702 	gpu->fence_context = dma_fence_context_alloc(1);
1703 	idr_init(&gpu->fence_idr);
1704 	spin_lock_init(&gpu->fence_spinlock);
1705 
1706 	INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1707 	init_waitqueue_head(&gpu->fence_event);
1708 
1709 	priv->gpu[priv->num_gpus++] = gpu;
1710 
1711 	pm_runtime_mark_last_busy(gpu->dev);
1712 	pm_runtime_put_autosuspend(gpu->dev);
1713 
1714 	return 0;
1715 
1716 out_sched:
1717 	etnaviv_sched_fini(gpu);
1718 
1719 out_workqueue:
1720 	destroy_workqueue(gpu->wq);
1721 
1722 out_thermal:
1723 	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1724 		thermal_cooling_device_unregister(gpu->cooling);
1725 
1726 	return ret;
1727 }
1728 
1729 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1730 	void *data)
1731 {
1732 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1733 
1734 	DBG("%s", dev_name(gpu->dev));
1735 
1736 	destroy_workqueue(gpu->wq);
1737 
1738 	etnaviv_sched_fini(gpu);
1739 
1740 #ifdef CONFIG_PM
1741 	pm_runtime_get_sync(gpu->dev);
1742 	pm_runtime_put_sync_suspend(gpu->dev);
1743 #else
1744 	etnaviv_gpu_hw_suspend(gpu);
1745 #endif
1746 
1747 	if (gpu->mmu_context)
1748 		etnaviv_iommu_context_put(gpu->mmu_context);
1749 
1750 	if (gpu->initialized) {
1751 		etnaviv_cmdbuf_free(&gpu->buffer);
1752 		etnaviv_iommu_global_fini(gpu);
1753 		gpu->initialized = false;
1754 	}
1755 
1756 	gpu->drm = NULL;
1757 	idr_destroy(&gpu->fence_idr);
1758 
1759 	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1760 		thermal_cooling_device_unregister(gpu->cooling);
1761 	gpu->cooling = NULL;
1762 }
1763 
1764 static const struct component_ops gpu_ops = {
1765 	.bind = etnaviv_gpu_bind,
1766 	.unbind = etnaviv_gpu_unbind,
1767 };
1768 
1769 static const struct of_device_id etnaviv_gpu_match[] = {
1770 	{
1771 		.compatible = "vivante,gc"
1772 	},
1773 	{ /* sentinel */ }
1774 };
1775 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1776 
1777 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1778 {
1779 	struct device *dev = &pdev->dev;
1780 	struct etnaviv_gpu *gpu;
1781 	int err;
1782 
1783 	gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1784 	if (!gpu)
1785 		return -ENOMEM;
1786 
1787 	gpu->dev = &pdev->dev;
1788 	mutex_init(&gpu->lock);
1789 	mutex_init(&gpu->fence_lock);
1790 
1791 	/* Map registers: */
1792 	gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1793 	if (IS_ERR(gpu->mmio))
1794 		return PTR_ERR(gpu->mmio);
1795 
1796 	/* Get Interrupt: */
1797 	gpu->irq = platform_get_irq(pdev, 0);
1798 	if (gpu->irq < 0)
1799 		return gpu->irq;
1800 
1801 	err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1802 			       dev_name(gpu->dev), gpu);
1803 	if (err) {
1804 		dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1805 		return err;
1806 	}
1807 
1808 	/* Get Clocks: */
1809 	gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1810 	DBG("clk_reg: %p", gpu->clk_reg);
1811 	if (IS_ERR(gpu->clk_reg))
1812 		return PTR_ERR(gpu->clk_reg);
1813 
1814 	gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1815 	DBG("clk_bus: %p", gpu->clk_bus);
1816 	if (IS_ERR(gpu->clk_bus))
1817 		return PTR_ERR(gpu->clk_bus);
1818 
1819 	gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1820 	DBG("clk_core: %p", gpu->clk_core);
1821 	if (IS_ERR(gpu->clk_core))
1822 		return PTR_ERR(gpu->clk_core);
1823 	gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1824 
1825 	gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1826 	DBG("clk_shader: %p", gpu->clk_shader);
1827 	if (IS_ERR(gpu->clk_shader))
1828 		return PTR_ERR(gpu->clk_shader);
1829 	gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1830 
1831 	/* TODO: figure out max mapped size */
1832 	dev_set_drvdata(dev, gpu);
1833 
1834 	/*
1835 	 * We treat the device as initially suspended.  The runtime PM
1836 	 * autosuspend delay is rather arbitary: no measurements have
1837 	 * yet been performed to determine an appropriate value.
1838 	 */
1839 	pm_runtime_use_autosuspend(gpu->dev);
1840 	pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1841 	pm_runtime_enable(gpu->dev);
1842 
1843 	err = component_add(&pdev->dev, &gpu_ops);
1844 	if (err < 0) {
1845 		dev_err(&pdev->dev, "failed to register component: %d\n", err);
1846 		return err;
1847 	}
1848 
1849 	return 0;
1850 }
1851 
1852 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1853 {
1854 	component_del(&pdev->dev, &gpu_ops);
1855 	pm_runtime_disable(&pdev->dev);
1856 	return 0;
1857 }
1858 
1859 #ifdef CONFIG_PM
1860 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1861 {
1862 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1863 	u32 idle, mask;
1864 
1865 	/* If there are any jobs in the HW queue, we're not idle */
1866 	if (atomic_read(&gpu->sched.hw_rq_count))
1867 		return -EBUSY;
1868 
1869 	/* Check whether the hardware (except FE and MC) is idle */
1870 	mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1871 				  VIVS_HI_IDLE_STATE_MC);
1872 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1873 	if (idle != mask) {
1874 		dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1875 				     idle);
1876 		return -EBUSY;
1877 	}
1878 
1879 	return etnaviv_gpu_hw_suspend(gpu);
1880 }
1881 
1882 static int etnaviv_gpu_rpm_resume(struct device *dev)
1883 {
1884 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1885 	int ret;
1886 
1887 	ret = etnaviv_gpu_clk_enable(gpu);
1888 	if (ret)
1889 		return ret;
1890 
1891 	/* Re-initialise the basic hardware state */
1892 	if (gpu->drm && gpu->initialized) {
1893 		ret = etnaviv_gpu_hw_resume(gpu);
1894 		if (ret) {
1895 			etnaviv_gpu_clk_disable(gpu);
1896 			return ret;
1897 		}
1898 	}
1899 
1900 	return 0;
1901 }
1902 #endif
1903 
1904 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1905 	SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1906 			   NULL)
1907 };
1908 
1909 struct platform_driver etnaviv_gpu_driver = {
1910 	.driver = {
1911 		.name = "etnaviv-gpu",
1912 		.owner = THIS_MODULE,
1913 		.pm = &etnaviv_gpu_pm_ops,
1914 		.of_match_table = etnaviv_gpu_match,
1915 	},
1916 	.probe = etnaviv_gpu_platform_probe,
1917 	.remove = etnaviv_gpu_platform_remove,
1918 	.id_table = gpu_ids,
1919 };
1920