1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/delay.h> 9 #include <linux/dma-fence.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/thermal.h> 17 18 #include "etnaviv_cmdbuf.h" 19 #include "etnaviv_dump.h" 20 #include "etnaviv_gpu.h" 21 #include "etnaviv_gem.h" 22 #include "etnaviv_mmu.h" 23 #include "etnaviv_perfmon.h" 24 #include "etnaviv_sched.h" 25 #include "common.xml.h" 26 #include "state.xml.h" 27 #include "state_hi.xml.h" 28 #include "cmdstream.xml.h" 29 30 #ifndef PHYS_OFFSET 31 #define PHYS_OFFSET 0 32 #endif 33 34 static const struct platform_device_id gpu_ids[] = { 35 { .name = "etnaviv-gpu,2d" }, 36 { }, 37 }; 38 39 /* 40 * Driver functions: 41 */ 42 43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 44 { 45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 46 47 switch (param) { 48 case ETNAVIV_PARAM_GPU_MODEL: 49 *value = gpu->identity.model; 50 break; 51 52 case ETNAVIV_PARAM_GPU_REVISION: 53 *value = gpu->identity.revision; 54 break; 55 56 case ETNAVIV_PARAM_GPU_FEATURES_0: 57 *value = gpu->identity.features; 58 break; 59 60 case ETNAVIV_PARAM_GPU_FEATURES_1: 61 *value = gpu->identity.minor_features0; 62 break; 63 64 case ETNAVIV_PARAM_GPU_FEATURES_2: 65 *value = gpu->identity.minor_features1; 66 break; 67 68 case ETNAVIV_PARAM_GPU_FEATURES_3: 69 *value = gpu->identity.minor_features2; 70 break; 71 72 case ETNAVIV_PARAM_GPU_FEATURES_4: 73 *value = gpu->identity.minor_features3; 74 break; 75 76 case ETNAVIV_PARAM_GPU_FEATURES_5: 77 *value = gpu->identity.minor_features4; 78 break; 79 80 case ETNAVIV_PARAM_GPU_FEATURES_6: 81 *value = gpu->identity.minor_features5; 82 break; 83 84 case ETNAVIV_PARAM_GPU_FEATURES_7: 85 *value = gpu->identity.minor_features6; 86 break; 87 88 case ETNAVIV_PARAM_GPU_FEATURES_8: 89 *value = gpu->identity.minor_features7; 90 break; 91 92 case ETNAVIV_PARAM_GPU_FEATURES_9: 93 *value = gpu->identity.minor_features8; 94 break; 95 96 case ETNAVIV_PARAM_GPU_FEATURES_10: 97 *value = gpu->identity.minor_features9; 98 break; 99 100 case ETNAVIV_PARAM_GPU_FEATURES_11: 101 *value = gpu->identity.minor_features10; 102 break; 103 104 case ETNAVIV_PARAM_GPU_FEATURES_12: 105 *value = gpu->identity.minor_features11; 106 break; 107 108 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 109 *value = gpu->identity.stream_count; 110 break; 111 112 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 113 *value = gpu->identity.register_max; 114 break; 115 116 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 117 *value = gpu->identity.thread_count; 118 break; 119 120 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 121 *value = gpu->identity.vertex_cache_size; 122 break; 123 124 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 125 *value = gpu->identity.shader_core_count; 126 break; 127 128 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 129 *value = gpu->identity.pixel_pipes; 130 break; 131 132 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 133 *value = gpu->identity.vertex_output_buffer_size; 134 break; 135 136 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 137 *value = gpu->identity.buffer_size; 138 break; 139 140 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 141 *value = gpu->identity.instruction_count; 142 break; 143 144 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 145 *value = gpu->identity.num_constants; 146 break; 147 148 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 149 *value = gpu->identity.varyings_count; 150 break; 151 152 case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 153 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 154 *value = ETNAVIV_SOFTPIN_START_ADDRESS; 155 else 156 *value = ~0ULL; 157 break; 158 159 default: 160 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 161 return -EINVAL; 162 } 163 164 return 0; 165 } 166 167 168 #define etnaviv_is_model_rev(gpu, mod, rev) \ 169 ((gpu)->identity.model == chipModel_##mod && \ 170 (gpu)->identity.revision == rev) 171 #define etnaviv_field(val, field) \ 172 (((val) & field##__MASK) >> field##__SHIFT) 173 174 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 175 { 176 if (gpu->identity.minor_features0 & 177 chipMinorFeatures0_MORE_MINOR_FEATURES) { 178 u32 specs[4]; 179 unsigned int streams; 180 181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 182 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 183 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 184 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 185 186 gpu->identity.stream_count = etnaviv_field(specs[0], 187 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 188 gpu->identity.register_max = etnaviv_field(specs[0], 189 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 190 gpu->identity.thread_count = etnaviv_field(specs[0], 191 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 192 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 193 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 194 gpu->identity.shader_core_count = etnaviv_field(specs[0], 195 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 196 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 197 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 198 gpu->identity.vertex_output_buffer_size = 199 etnaviv_field(specs[0], 200 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 201 202 gpu->identity.buffer_size = etnaviv_field(specs[1], 203 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 204 gpu->identity.instruction_count = etnaviv_field(specs[1], 205 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 206 gpu->identity.num_constants = etnaviv_field(specs[1], 207 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 208 209 gpu->identity.varyings_count = etnaviv_field(specs[2], 210 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 211 212 /* This overrides the value from older register if non-zero */ 213 streams = etnaviv_field(specs[3], 214 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 215 if (streams) 216 gpu->identity.stream_count = streams; 217 } 218 219 /* Fill in the stream count if not specified */ 220 if (gpu->identity.stream_count == 0) { 221 if (gpu->identity.model >= 0x1000) 222 gpu->identity.stream_count = 4; 223 else 224 gpu->identity.stream_count = 1; 225 } 226 227 /* Convert the register max value */ 228 if (gpu->identity.register_max) 229 gpu->identity.register_max = 1 << gpu->identity.register_max; 230 else if (gpu->identity.model == chipModel_GC400) 231 gpu->identity.register_max = 32; 232 else 233 gpu->identity.register_max = 64; 234 235 /* Convert thread count */ 236 if (gpu->identity.thread_count) 237 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 238 else if (gpu->identity.model == chipModel_GC400) 239 gpu->identity.thread_count = 64; 240 else if (gpu->identity.model == chipModel_GC500 || 241 gpu->identity.model == chipModel_GC530) 242 gpu->identity.thread_count = 128; 243 else 244 gpu->identity.thread_count = 256; 245 246 if (gpu->identity.vertex_cache_size == 0) 247 gpu->identity.vertex_cache_size = 8; 248 249 if (gpu->identity.shader_core_count == 0) { 250 if (gpu->identity.model >= 0x1000) 251 gpu->identity.shader_core_count = 2; 252 else 253 gpu->identity.shader_core_count = 1; 254 } 255 256 if (gpu->identity.pixel_pipes == 0) 257 gpu->identity.pixel_pipes = 1; 258 259 /* Convert virtex buffer size */ 260 if (gpu->identity.vertex_output_buffer_size) { 261 gpu->identity.vertex_output_buffer_size = 262 1 << gpu->identity.vertex_output_buffer_size; 263 } else if (gpu->identity.model == chipModel_GC400) { 264 if (gpu->identity.revision < 0x4000) 265 gpu->identity.vertex_output_buffer_size = 512; 266 else if (gpu->identity.revision < 0x4200) 267 gpu->identity.vertex_output_buffer_size = 256; 268 else 269 gpu->identity.vertex_output_buffer_size = 128; 270 } else { 271 gpu->identity.vertex_output_buffer_size = 512; 272 } 273 274 switch (gpu->identity.instruction_count) { 275 case 0: 276 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 277 gpu->identity.model == chipModel_GC880) 278 gpu->identity.instruction_count = 512; 279 else 280 gpu->identity.instruction_count = 256; 281 break; 282 283 case 1: 284 gpu->identity.instruction_count = 1024; 285 break; 286 287 case 2: 288 gpu->identity.instruction_count = 2048; 289 break; 290 291 default: 292 gpu->identity.instruction_count = 256; 293 break; 294 } 295 296 if (gpu->identity.num_constants == 0) 297 gpu->identity.num_constants = 168; 298 299 if (gpu->identity.varyings_count == 0) { 300 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 301 gpu->identity.varyings_count = 12; 302 else 303 gpu->identity.varyings_count = 8; 304 } 305 306 /* 307 * For some cores, two varyings are consumed for position, so the 308 * maximum varying count needs to be reduced by one. 309 */ 310 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 311 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 312 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 313 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 314 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 315 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 316 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 317 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 318 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 319 etnaviv_is_model_rev(gpu, GC880, 0x5107) || 320 etnaviv_is_model_rev(gpu, GC880, 0x5106)) 321 gpu->identity.varyings_count -= 1; 322 } 323 324 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 325 { 326 u32 chipIdentity; 327 328 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 329 330 /* Special case for older graphic cores. */ 331 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 332 gpu->identity.model = chipModel_GC500; 333 gpu->identity.revision = etnaviv_field(chipIdentity, 334 VIVS_HI_CHIP_IDENTITY_REVISION); 335 } else { 336 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 337 338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 340 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 341 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 342 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 343 344 /* 345 * !!!! HACK ALERT !!!! 346 * Because people change device IDs without letting software 347 * know about it - here is the hack to make it all look the 348 * same. Only for GC400 family. 349 */ 350 if ((gpu->identity.model & 0xff00) == 0x0400 && 351 gpu->identity.model != chipModel_GC420) { 352 gpu->identity.model = gpu->identity.model & 0x0400; 353 } 354 355 /* Another special case */ 356 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 357 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 358 359 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 360 /* 361 * This IP has an ECO; put the correct 362 * revision in it. 363 */ 364 gpu->identity.revision = 0x1051; 365 } 366 } 367 368 /* 369 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 370 * reality it's just a re-branded GC3000. We can identify this 371 * core by the upper half of the revision register being all 1. 372 * Fix model/rev here, so all other places can refer to this 373 * core by its real identity. 374 */ 375 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 376 gpu->identity.model = chipModel_GC3000; 377 gpu->identity.revision &= 0xffff; 378 } 379 380 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) 381 gpu->identity.eco_id = 1; 382 383 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) 384 gpu->identity.eco_id = 1; 385 } 386 387 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 388 gpu->identity.model, gpu->identity.revision); 389 390 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 391 /* 392 * If there is a match in the HWDB, we aren't interested in the 393 * remaining register values, as they might be wrong. 394 */ 395 if (etnaviv_fill_identity_from_hwdb(gpu)) 396 return; 397 398 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 399 400 /* Disable fast clear on GC700. */ 401 if (gpu->identity.model == chipModel_GC700) 402 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 403 404 if ((gpu->identity.model == chipModel_GC500 && 405 gpu->identity.revision < 2) || 406 (gpu->identity.model == chipModel_GC300 && 407 gpu->identity.revision < 0x2000)) { 408 409 /* 410 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 411 * registers. 412 */ 413 gpu->identity.minor_features0 = 0; 414 gpu->identity.minor_features1 = 0; 415 gpu->identity.minor_features2 = 0; 416 gpu->identity.minor_features3 = 0; 417 gpu->identity.minor_features4 = 0; 418 gpu->identity.minor_features5 = 0; 419 } else 420 gpu->identity.minor_features0 = 421 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 422 423 if (gpu->identity.minor_features0 & 424 chipMinorFeatures0_MORE_MINOR_FEATURES) { 425 gpu->identity.minor_features1 = 426 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 427 gpu->identity.minor_features2 = 428 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 429 gpu->identity.minor_features3 = 430 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 431 gpu->identity.minor_features4 = 432 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 433 gpu->identity.minor_features5 = 434 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 435 } 436 437 /* GC600 idle register reports zero bits where modules aren't present */ 438 if (gpu->identity.model == chipModel_GC600) 439 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 440 VIVS_HI_IDLE_STATE_RA | 441 VIVS_HI_IDLE_STATE_SE | 442 VIVS_HI_IDLE_STATE_PA | 443 VIVS_HI_IDLE_STATE_SH | 444 VIVS_HI_IDLE_STATE_PE | 445 VIVS_HI_IDLE_STATE_DE | 446 VIVS_HI_IDLE_STATE_FE; 447 448 etnaviv_hw_specs(gpu); 449 } 450 451 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 452 { 453 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 454 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 455 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 456 } 457 458 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 459 { 460 if (gpu->identity.minor_features2 & 461 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 462 clk_set_rate(gpu->clk_core, 463 gpu->base_rate_core >> gpu->freq_scale); 464 clk_set_rate(gpu->clk_shader, 465 gpu->base_rate_shader >> gpu->freq_scale); 466 } else { 467 unsigned int fscale = 1 << (6 - gpu->freq_scale); 468 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 469 470 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 471 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 472 etnaviv_gpu_load_clock(gpu, clock); 473 } 474 } 475 476 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 477 { 478 u32 control, idle; 479 unsigned long timeout; 480 bool failed = true; 481 482 /* We hope that the GPU resets in under one second */ 483 timeout = jiffies + msecs_to_jiffies(1000); 484 485 while (time_is_after_jiffies(timeout)) { 486 /* enable clock */ 487 unsigned int fscale = 1 << (6 - gpu->freq_scale); 488 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 489 etnaviv_gpu_load_clock(gpu, control); 490 491 /* isolate the GPU. */ 492 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 493 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 494 495 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 496 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 497 VIVS_MMUv2_AHB_CONTROL_RESET); 498 } else { 499 /* set soft reset. */ 500 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 502 } 503 504 /* wait for reset. */ 505 usleep_range(10, 20); 506 507 /* reset soft reset bit. */ 508 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 509 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 510 511 /* reset GPU isolation. */ 512 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 513 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 514 515 /* read idle register. */ 516 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 517 518 /* try resetting again if FE is not idle */ 519 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 520 dev_dbg(gpu->dev, "FE is not idle\n"); 521 continue; 522 } 523 524 /* read reset register. */ 525 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 526 527 /* is the GPU idle? */ 528 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 529 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 530 dev_dbg(gpu->dev, "GPU is not idle\n"); 531 continue; 532 } 533 534 /* disable debug registers, as they are not normally needed */ 535 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 536 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 537 538 failed = false; 539 break; 540 } 541 542 if (failed) { 543 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 544 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 545 546 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 547 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 548 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 549 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 550 551 return -EBUSY; 552 } 553 554 /* We rely on the GPU running, so program the clock */ 555 etnaviv_gpu_update_clock(gpu); 556 557 return 0; 558 } 559 560 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 561 { 562 u32 pmc, ppc; 563 564 /* enable clock gating */ 565 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 566 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 567 568 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 569 if (gpu->identity.revision == 0x4301 || 570 gpu->identity.revision == 0x4302) 571 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 572 573 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 574 575 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 576 577 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 578 if (gpu->identity.model >= chipModel_GC400 && 579 gpu->identity.model != chipModel_GC420 && 580 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 581 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 582 583 /* 584 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 585 * present without a bug fix. 586 */ 587 if (gpu->identity.revision < 0x5000 && 588 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 589 !(gpu->identity.minor_features1 & 590 chipMinorFeatures1_DISABLE_PE_GATING)) 591 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 592 593 if (gpu->identity.revision < 0x5422) 594 pmc |= BIT(15); /* Unknown bit */ 595 596 /* Disable TX clock gating on affected core revisions. */ 597 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 598 etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 599 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 600 601 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 602 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 603 604 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 605 } 606 607 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 608 { 609 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 610 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 611 VIVS_FE_COMMAND_CONTROL_ENABLE | 612 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 613 614 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 615 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 616 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 617 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 618 } 619 } 620 621 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu) 622 { 623 u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer, 624 &gpu->mmu_context->cmdbuf_mapping); 625 u16 prefetch; 626 627 /* setup the MMU */ 628 etnaviv_iommu_restore(gpu, gpu->mmu_context); 629 630 /* Start command processor */ 631 prefetch = etnaviv_buffer_init(gpu); 632 633 etnaviv_gpu_start_fe(gpu, address, prefetch); 634 } 635 636 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 637 { 638 /* 639 * Base value for VIVS_PM_PULSE_EATER register on models where it 640 * cannot be read, extracted from vivante kernel driver. 641 */ 642 u32 pulse_eater = 0x01590880; 643 644 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 645 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 646 pulse_eater |= BIT(23); 647 648 } 649 650 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 651 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 652 pulse_eater &= ~BIT(16); 653 pulse_eater |= BIT(17); 654 } 655 656 if ((gpu->identity.revision > 0x5420) && 657 (gpu->identity.features & chipFeatures_PIPE_3D)) 658 { 659 /* Performance fix: disable internal DFS */ 660 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 661 pulse_eater |= BIT(18); 662 } 663 664 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 665 } 666 667 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 668 { 669 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 670 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 671 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 672 u32 mc_memory_debug; 673 674 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 675 676 if (gpu->identity.revision == 0x5007) 677 mc_memory_debug |= 0x0c; 678 else 679 mc_memory_debug |= 0x08; 680 681 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 682 } 683 684 /* enable module-level clock gating */ 685 etnaviv_gpu_enable_mlcg(gpu); 686 687 /* 688 * Update GPU AXI cache atttribute to "cacheable, no allocate". 689 * This is necessary to prevent the iMX6 SoC locking up. 690 */ 691 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 692 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 693 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 694 695 /* GC2000 rev 5108 needs a special bus config */ 696 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 697 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 698 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 699 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 700 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 701 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 702 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 703 } 704 705 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 706 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 707 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 708 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 709 } 710 711 /* setup the pulse eater */ 712 etnaviv_gpu_setup_pulse_eater(gpu); 713 714 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 715 } 716 717 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 718 { 719 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 720 int ret, i; 721 722 ret = pm_runtime_get_sync(gpu->dev); 723 if (ret < 0) { 724 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 725 goto pm_put; 726 } 727 728 etnaviv_hw_identify(gpu); 729 730 if (gpu->identity.model == 0) { 731 dev_err(gpu->dev, "Unknown GPU model\n"); 732 ret = -ENXIO; 733 goto fail; 734 } 735 736 /* Exclude VG cores with FE2.0 */ 737 if (gpu->identity.features & chipFeatures_PIPE_VG && 738 gpu->identity.features & chipFeatures_FE20) { 739 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 740 ret = -ENXIO; 741 goto fail; 742 } 743 744 /* 745 * On cores with security features supported, we claim control over the 746 * security states. 747 */ 748 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 749 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 750 gpu->sec_mode = ETNA_SEC_KERNEL; 751 752 ret = etnaviv_hw_reset(gpu); 753 if (ret) { 754 dev_err(gpu->dev, "GPU reset failed\n"); 755 goto fail; 756 } 757 758 ret = etnaviv_iommu_global_init(gpu); 759 if (ret) 760 goto fail; 761 762 /* 763 * Set the GPU linear window to be at the end of the DMA window, where 764 * the CMA area is likely to reside. This ensures that we are able to 765 * map the command buffers while having the linear window overlap as 766 * much RAM as possible, so we can optimize mappings for other buffers. 767 * 768 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 769 * to different views of the memory on the individual engines. 770 */ 771 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 772 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 773 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 774 if (dma_mask < PHYS_OFFSET + SZ_2G) 775 priv->mmu_global->memory_base = PHYS_OFFSET; 776 else 777 priv->mmu_global->memory_base = dma_mask - SZ_2G + 1; 778 } else if (PHYS_OFFSET >= SZ_2G) { 779 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 780 priv->mmu_global->memory_base = PHYS_OFFSET; 781 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 782 } 783 784 /* 785 * If the GPU is part of a system with DMA addressing limitations, 786 * request pages for our SHM backend buffers from the DMA32 zone to 787 * hopefully avoid performance killing SWIOTLB bounce buffering. 788 */ 789 if (dma_addressing_limited(gpu->dev)) 790 priv->shm_gfp_mask |= GFP_DMA32; 791 792 /* Create buffer: */ 793 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, 794 PAGE_SIZE); 795 if (ret) { 796 dev_err(gpu->dev, "could not create command buffer\n"); 797 goto fail; 798 } 799 800 /* Setup event management */ 801 spin_lock_init(&gpu->event_spinlock); 802 init_completion(&gpu->event_free); 803 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 804 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 805 complete(&gpu->event_free); 806 807 /* Now program the hardware */ 808 mutex_lock(&gpu->lock); 809 etnaviv_gpu_hw_init(gpu); 810 gpu->exec_state = -1; 811 mutex_unlock(&gpu->lock); 812 813 pm_runtime_mark_last_busy(gpu->dev); 814 pm_runtime_put_autosuspend(gpu->dev); 815 816 gpu->initialized = true; 817 818 return 0; 819 820 fail: 821 pm_runtime_mark_last_busy(gpu->dev); 822 pm_put: 823 pm_runtime_put_autosuspend(gpu->dev); 824 825 return ret; 826 } 827 828 #ifdef CONFIG_DEBUG_FS 829 struct dma_debug { 830 u32 address[2]; 831 u32 state[2]; 832 }; 833 834 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 835 { 836 u32 i; 837 838 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 839 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 840 841 for (i = 0; i < 500; i++) { 842 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 843 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 844 845 if (debug->address[0] != debug->address[1]) 846 break; 847 848 if (debug->state[0] != debug->state[1]) 849 break; 850 } 851 } 852 853 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 854 { 855 struct dma_debug debug; 856 u32 dma_lo, dma_hi, axi, idle; 857 int ret; 858 859 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 860 861 ret = pm_runtime_get_sync(gpu->dev); 862 if (ret < 0) 863 goto pm_put; 864 865 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 866 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 867 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 868 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 869 870 verify_dma(gpu, &debug); 871 872 seq_puts(m, "\tidentity\n"); 873 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 874 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 875 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 876 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 877 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 878 879 seq_puts(m, "\tfeatures\n"); 880 seq_printf(m, "\t major_features: 0x%08x\n", 881 gpu->identity.features); 882 seq_printf(m, "\t minor_features0: 0x%08x\n", 883 gpu->identity.minor_features0); 884 seq_printf(m, "\t minor_features1: 0x%08x\n", 885 gpu->identity.minor_features1); 886 seq_printf(m, "\t minor_features2: 0x%08x\n", 887 gpu->identity.minor_features2); 888 seq_printf(m, "\t minor_features3: 0x%08x\n", 889 gpu->identity.minor_features3); 890 seq_printf(m, "\t minor_features4: 0x%08x\n", 891 gpu->identity.minor_features4); 892 seq_printf(m, "\t minor_features5: 0x%08x\n", 893 gpu->identity.minor_features5); 894 seq_printf(m, "\t minor_features6: 0x%08x\n", 895 gpu->identity.minor_features6); 896 seq_printf(m, "\t minor_features7: 0x%08x\n", 897 gpu->identity.minor_features7); 898 seq_printf(m, "\t minor_features8: 0x%08x\n", 899 gpu->identity.minor_features8); 900 seq_printf(m, "\t minor_features9: 0x%08x\n", 901 gpu->identity.minor_features9); 902 seq_printf(m, "\t minor_features10: 0x%08x\n", 903 gpu->identity.minor_features10); 904 seq_printf(m, "\t minor_features11: 0x%08x\n", 905 gpu->identity.minor_features11); 906 907 seq_puts(m, "\tspecs\n"); 908 seq_printf(m, "\t stream_count: %d\n", 909 gpu->identity.stream_count); 910 seq_printf(m, "\t register_max: %d\n", 911 gpu->identity.register_max); 912 seq_printf(m, "\t thread_count: %d\n", 913 gpu->identity.thread_count); 914 seq_printf(m, "\t vertex_cache_size: %d\n", 915 gpu->identity.vertex_cache_size); 916 seq_printf(m, "\t shader_core_count: %d\n", 917 gpu->identity.shader_core_count); 918 seq_printf(m, "\t pixel_pipes: %d\n", 919 gpu->identity.pixel_pipes); 920 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 921 gpu->identity.vertex_output_buffer_size); 922 seq_printf(m, "\t buffer_size: %d\n", 923 gpu->identity.buffer_size); 924 seq_printf(m, "\t instruction_count: %d\n", 925 gpu->identity.instruction_count); 926 seq_printf(m, "\t num_constants: %d\n", 927 gpu->identity.num_constants); 928 seq_printf(m, "\t varyings_count: %d\n", 929 gpu->identity.varyings_count); 930 931 seq_printf(m, "\taxi: 0x%08x\n", axi); 932 seq_printf(m, "\tidle: 0x%08x\n", idle); 933 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 934 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 935 seq_puts(m, "\t FE is not idle\n"); 936 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 937 seq_puts(m, "\t DE is not idle\n"); 938 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 939 seq_puts(m, "\t PE is not idle\n"); 940 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 941 seq_puts(m, "\t SH is not idle\n"); 942 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 943 seq_puts(m, "\t PA is not idle\n"); 944 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 945 seq_puts(m, "\t SE is not idle\n"); 946 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 947 seq_puts(m, "\t RA is not idle\n"); 948 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 949 seq_puts(m, "\t TX is not idle\n"); 950 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 951 seq_puts(m, "\t VG is not idle\n"); 952 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 953 seq_puts(m, "\t IM is not idle\n"); 954 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 955 seq_puts(m, "\t FP is not idle\n"); 956 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 957 seq_puts(m, "\t TS is not idle\n"); 958 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 959 seq_puts(m, "\t BL is not idle\n"); 960 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 961 seq_puts(m, "\t ASYNCFE is not idle\n"); 962 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 963 seq_puts(m, "\t MC is not idle\n"); 964 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 965 seq_puts(m, "\t PPA is not idle\n"); 966 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 967 seq_puts(m, "\t WD is not idle\n"); 968 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 969 seq_puts(m, "\t NN is not idle\n"); 970 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 971 seq_puts(m, "\t TP is not idle\n"); 972 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 973 seq_puts(m, "\t AXI low power mode\n"); 974 975 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 976 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 977 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 978 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 979 980 seq_puts(m, "\tMC\n"); 981 seq_printf(m, "\t read0: 0x%08x\n", read0); 982 seq_printf(m, "\t read1: 0x%08x\n", read1); 983 seq_printf(m, "\t write: 0x%08x\n", write); 984 } 985 986 seq_puts(m, "\tDMA "); 987 988 if (debug.address[0] == debug.address[1] && 989 debug.state[0] == debug.state[1]) { 990 seq_puts(m, "seems to be stuck\n"); 991 } else if (debug.address[0] == debug.address[1]) { 992 seq_puts(m, "address is constant\n"); 993 } else { 994 seq_puts(m, "is running\n"); 995 } 996 997 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 998 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 999 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1000 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1001 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1002 dma_lo, dma_hi); 1003 1004 ret = 0; 1005 1006 pm_runtime_mark_last_busy(gpu->dev); 1007 pm_put: 1008 pm_runtime_put_autosuspend(gpu->dev); 1009 1010 return ret; 1011 } 1012 #endif 1013 1014 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) 1015 { 1016 unsigned int i = 0; 1017 1018 dev_err(gpu->dev, "recover hung GPU!\n"); 1019 1020 if (pm_runtime_get_sync(gpu->dev) < 0) 1021 goto pm_put; 1022 1023 mutex_lock(&gpu->lock); 1024 1025 etnaviv_hw_reset(gpu); 1026 1027 /* complete all events, the GPU won't do it after the reset */ 1028 spin_lock(&gpu->event_spinlock); 1029 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1030 complete(&gpu->event_free); 1031 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 1032 spin_unlock(&gpu->event_spinlock); 1033 1034 etnaviv_gpu_hw_init(gpu); 1035 gpu->exec_state = -1; 1036 gpu->mmu_context = NULL; 1037 1038 mutex_unlock(&gpu->lock); 1039 pm_runtime_mark_last_busy(gpu->dev); 1040 pm_put: 1041 pm_runtime_put_autosuspend(gpu->dev); 1042 } 1043 1044 /* fence object management */ 1045 struct etnaviv_fence { 1046 struct etnaviv_gpu *gpu; 1047 struct dma_fence base; 1048 }; 1049 1050 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1051 { 1052 return container_of(fence, struct etnaviv_fence, base); 1053 } 1054 1055 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1056 { 1057 return "etnaviv"; 1058 } 1059 1060 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1061 { 1062 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1063 1064 return dev_name(f->gpu->dev); 1065 } 1066 1067 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1068 { 1069 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1070 1071 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1072 } 1073 1074 static void etnaviv_fence_release(struct dma_fence *fence) 1075 { 1076 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1077 1078 kfree_rcu(f, base.rcu); 1079 } 1080 1081 static const struct dma_fence_ops etnaviv_fence_ops = { 1082 .get_driver_name = etnaviv_fence_get_driver_name, 1083 .get_timeline_name = etnaviv_fence_get_timeline_name, 1084 .signaled = etnaviv_fence_signaled, 1085 .release = etnaviv_fence_release, 1086 }; 1087 1088 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1089 { 1090 struct etnaviv_fence *f; 1091 1092 /* 1093 * GPU lock must already be held, otherwise fence completion order might 1094 * not match the seqno order assigned here. 1095 */ 1096 lockdep_assert_held(&gpu->lock); 1097 1098 f = kzalloc(sizeof(*f), GFP_KERNEL); 1099 if (!f) 1100 return NULL; 1101 1102 f->gpu = gpu; 1103 1104 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1105 gpu->fence_context, ++gpu->next_fence); 1106 1107 return &f->base; 1108 } 1109 1110 /* returns true if fence a comes after fence b */ 1111 static inline bool fence_after(u32 a, u32 b) 1112 { 1113 return (s32)(a - b) > 0; 1114 } 1115 1116 /* 1117 * event management: 1118 */ 1119 1120 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1121 unsigned int *events) 1122 { 1123 unsigned long timeout = msecs_to_jiffies(10 * 10000); 1124 unsigned i, acquired = 0; 1125 1126 for (i = 0; i < nr_events; i++) { 1127 unsigned long ret; 1128 1129 ret = wait_for_completion_timeout(&gpu->event_free, timeout); 1130 1131 if (!ret) { 1132 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1133 goto out; 1134 } 1135 1136 acquired++; 1137 timeout = ret; 1138 } 1139 1140 spin_lock(&gpu->event_spinlock); 1141 1142 for (i = 0; i < nr_events; i++) { 1143 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1144 1145 events[i] = event; 1146 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1147 set_bit(event, gpu->event_bitmap); 1148 } 1149 1150 spin_unlock(&gpu->event_spinlock); 1151 1152 return 0; 1153 1154 out: 1155 for (i = 0; i < acquired; i++) 1156 complete(&gpu->event_free); 1157 1158 return -EBUSY; 1159 } 1160 1161 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1162 { 1163 if (!test_bit(event, gpu->event_bitmap)) { 1164 dev_warn(gpu->dev, "event %u is already marked as free", 1165 event); 1166 } else { 1167 clear_bit(event, gpu->event_bitmap); 1168 complete(&gpu->event_free); 1169 } 1170 } 1171 1172 /* 1173 * Cmdstream submission/retirement: 1174 */ 1175 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1176 u32 id, struct drm_etnaviv_timespec *timeout) 1177 { 1178 struct dma_fence *fence; 1179 int ret; 1180 1181 /* 1182 * Look up the fence and take a reference. We might still find a fence 1183 * whose refcount has already dropped to zero. dma_fence_get_rcu 1184 * pretends we didn't find a fence in that case. 1185 */ 1186 rcu_read_lock(); 1187 fence = idr_find(&gpu->fence_idr, id); 1188 if (fence) 1189 fence = dma_fence_get_rcu(fence); 1190 rcu_read_unlock(); 1191 1192 if (!fence) 1193 return 0; 1194 1195 if (!timeout) { 1196 /* No timeout was requested: just test for completion */ 1197 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1198 } else { 1199 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1200 1201 ret = dma_fence_wait_timeout(fence, true, remaining); 1202 if (ret == 0) 1203 ret = -ETIMEDOUT; 1204 else if (ret != -ERESTARTSYS) 1205 ret = 0; 1206 1207 } 1208 1209 dma_fence_put(fence); 1210 return ret; 1211 } 1212 1213 /* 1214 * Wait for an object to become inactive. This, on it's own, is not race 1215 * free: the object is moved by the scheduler off the active list, and 1216 * then the iova is put. Moreover, the object could be re-submitted just 1217 * after we notice that it's become inactive. 1218 * 1219 * Although the retirement happens under the gpu lock, we don't want to hold 1220 * that lock in this function while waiting. 1221 */ 1222 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1223 struct etnaviv_gem_object *etnaviv_obj, 1224 struct drm_etnaviv_timespec *timeout) 1225 { 1226 unsigned long remaining; 1227 long ret; 1228 1229 if (!timeout) 1230 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1231 1232 remaining = etnaviv_timeout_to_jiffies(timeout); 1233 1234 ret = wait_event_interruptible_timeout(gpu->fence_event, 1235 !is_active(etnaviv_obj), 1236 remaining); 1237 if (ret > 0) 1238 return 0; 1239 else if (ret == -ERESTARTSYS) 1240 return -ERESTARTSYS; 1241 else 1242 return -ETIMEDOUT; 1243 } 1244 1245 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1246 struct etnaviv_event *event, unsigned int flags) 1247 { 1248 const struct etnaviv_gem_submit *submit = event->submit; 1249 unsigned int i; 1250 1251 for (i = 0; i < submit->nr_pmrs; i++) { 1252 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1253 1254 if (pmr->flags == flags) 1255 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 1256 } 1257 } 1258 1259 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1260 struct etnaviv_event *event) 1261 { 1262 u32 val; 1263 1264 /* disable clock gating */ 1265 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 1266 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1267 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 1268 1269 /* enable debug register */ 1270 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1271 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1272 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1273 1274 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1275 } 1276 1277 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1278 struct etnaviv_event *event) 1279 { 1280 const struct etnaviv_gem_submit *submit = event->submit; 1281 unsigned int i; 1282 u32 val; 1283 1284 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1285 1286 for (i = 0; i < submit->nr_pmrs; i++) { 1287 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1288 1289 *pmr->bo_vma = pmr->sequence; 1290 } 1291 1292 /* disable debug register */ 1293 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1294 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1295 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1296 1297 /* enable clock gating */ 1298 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 1299 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1300 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 1301 } 1302 1303 1304 /* add bo's to gpu's ring, and kick gpu: */ 1305 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1306 { 1307 struct etnaviv_gpu *gpu = submit->gpu; 1308 struct dma_fence *gpu_fence; 1309 unsigned int i, nr_events = 1, event[3]; 1310 int ret; 1311 1312 if (!submit->runtime_resumed) { 1313 ret = pm_runtime_get_sync(gpu->dev); 1314 if (ret < 0) { 1315 pm_runtime_put_noidle(gpu->dev); 1316 return NULL; 1317 } 1318 submit->runtime_resumed = true; 1319 } 1320 1321 /* 1322 * if there are performance monitor requests we need to have 1323 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1324 * requests. 1325 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1326 * and update the sequence number for userspace. 1327 */ 1328 if (submit->nr_pmrs) 1329 nr_events = 3; 1330 1331 ret = event_alloc(gpu, nr_events, event); 1332 if (ret) { 1333 DRM_ERROR("no free events\n"); 1334 pm_runtime_put_noidle(gpu->dev); 1335 return NULL; 1336 } 1337 1338 mutex_lock(&gpu->lock); 1339 1340 gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1341 if (!gpu_fence) { 1342 for (i = 0; i < nr_events; i++) 1343 event_free(gpu, event[i]); 1344 1345 goto out_unlock; 1346 } 1347 1348 if (!gpu->mmu_context) { 1349 etnaviv_iommu_context_get(submit->mmu_context); 1350 gpu->mmu_context = submit->mmu_context; 1351 etnaviv_gpu_start_fe_idleloop(gpu); 1352 } else { 1353 etnaviv_iommu_context_get(gpu->mmu_context); 1354 submit->prev_mmu_context = gpu->mmu_context; 1355 } 1356 1357 if (submit->nr_pmrs) { 1358 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1359 kref_get(&submit->refcount); 1360 gpu->event[event[1]].submit = submit; 1361 etnaviv_sync_point_queue(gpu, event[1]); 1362 } 1363 1364 gpu->event[event[0]].fence = gpu_fence; 1365 submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 1366 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 1367 event[0], &submit->cmdbuf); 1368 1369 if (submit->nr_pmrs) { 1370 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1371 kref_get(&submit->refcount); 1372 gpu->event[event[2]].submit = submit; 1373 etnaviv_sync_point_queue(gpu, event[2]); 1374 } 1375 1376 out_unlock: 1377 mutex_unlock(&gpu->lock); 1378 1379 return gpu_fence; 1380 } 1381 1382 static void sync_point_worker(struct work_struct *work) 1383 { 1384 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1385 sync_point_work); 1386 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1387 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1388 1389 event->sync_point(gpu, event); 1390 etnaviv_submit_put(event->submit); 1391 event_free(gpu, gpu->sync_point_event); 1392 1393 /* restart FE last to avoid GPU and IRQ racing against this worker */ 1394 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1395 } 1396 1397 static void dump_mmu_fault(struct etnaviv_gpu *gpu) 1398 { 1399 u32 status_reg, status; 1400 int i; 1401 1402 if (gpu->sec_mode == ETNA_SEC_NONE) 1403 status_reg = VIVS_MMUv2_STATUS; 1404 else 1405 status_reg = VIVS_MMUv2_SEC_STATUS; 1406 1407 status = gpu_read(gpu, status_reg); 1408 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 1409 1410 for (i = 0; i < 4; i++) { 1411 u32 address_reg; 1412 1413 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4)))) 1414 continue; 1415 1416 if (gpu->sec_mode == ETNA_SEC_NONE) 1417 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1418 else 1419 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1420 1421 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, 1422 gpu_read(gpu, address_reg)); 1423 } 1424 } 1425 1426 static irqreturn_t irq_handler(int irq, void *data) 1427 { 1428 struct etnaviv_gpu *gpu = data; 1429 irqreturn_t ret = IRQ_NONE; 1430 1431 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1432 1433 if (intr != 0) { 1434 int event; 1435 1436 pm_runtime_mark_last_busy(gpu->dev); 1437 1438 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1439 1440 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1441 dev_err(gpu->dev, "AXI bus error\n"); 1442 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1443 } 1444 1445 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1446 dump_mmu_fault(gpu); 1447 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1448 } 1449 1450 while ((event = ffs(intr)) != 0) { 1451 struct dma_fence *fence; 1452 1453 event -= 1; 1454 1455 intr &= ~(1 << event); 1456 1457 dev_dbg(gpu->dev, "event %u\n", event); 1458 1459 if (gpu->event[event].sync_point) { 1460 gpu->sync_point_event = event; 1461 queue_work(gpu->wq, &gpu->sync_point_work); 1462 } 1463 1464 fence = gpu->event[event].fence; 1465 if (!fence) 1466 continue; 1467 1468 gpu->event[event].fence = NULL; 1469 1470 /* 1471 * Events can be processed out of order. Eg, 1472 * - allocate and queue event 0 1473 * - allocate event 1 1474 * - event 0 completes, we process it 1475 * - allocate and queue event 0 1476 * - event 1 and event 0 complete 1477 * we can end up processing event 0 first, then 1. 1478 */ 1479 if (fence_after(fence->seqno, gpu->completed_fence)) 1480 gpu->completed_fence = fence->seqno; 1481 dma_fence_signal(fence); 1482 1483 event_free(gpu, event); 1484 } 1485 1486 ret = IRQ_HANDLED; 1487 } 1488 1489 return ret; 1490 } 1491 1492 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1493 { 1494 int ret; 1495 1496 ret = clk_prepare_enable(gpu->clk_reg); 1497 if (ret) 1498 return ret; 1499 1500 ret = clk_prepare_enable(gpu->clk_bus); 1501 if (ret) 1502 goto disable_clk_reg; 1503 1504 ret = clk_prepare_enable(gpu->clk_core); 1505 if (ret) 1506 goto disable_clk_bus; 1507 1508 ret = clk_prepare_enable(gpu->clk_shader); 1509 if (ret) 1510 goto disable_clk_core; 1511 1512 return 0; 1513 1514 disable_clk_core: 1515 clk_disable_unprepare(gpu->clk_core); 1516 disable_clk_bus: 1517 clk_disable_unprepare(gpu->clk_bus); 1518 disable_clk_reg: 1519 clk_disable_unprepare(gpu->clk_reg); 1520 1521 return ret; 1522 } 1523 1524 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1525 { 1526 clk_disable_unprepare(gpu->clk_shader); 1527 clk_disable_unprepare(gpu->clk_core); 1528 clk_disable_unprepare(gpu->clk_bus); 1529 clk_disable_unprepare(gpu->clk_reg); 1530 1531 return 0; 1532 } 1533 1534 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1535 { 1536 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1537 1538 do { 1539 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1540 1541 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1542 return 0; 1543 1544 if (time_is_before_jiffies(timeout)) { 1545 dev_warn(gpu->dev, 1546 "timed out waiting for idle: idle=0x%x\n", 1547 idle); 1548 return -ETIMEDOUT; 1549 } 1550 1551 udelay(5); 1552 } while (1); 1553 } 1554 1555 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1556 { 1557 if (gpu->initialized && gpu->mmu_context) { 1558 /* Replace the last WAIT with END */ 1559 mutex_lock(&gpu->lock); 1560 etnaviv_buffer_end(gpu); 1561 mutex_unlock(&gpu->lock); 1562 1563 /* 1564 * We know that only the FE is busy here, this should 1565 * happen quickly (as the WAIT is only 200 cycles). If 1566 * we fail, just warn and continue. 1567 */ 1568 etnaviv_gpu_wait_idle(gpu, 100); 1569 1570 etnaviv_iommu_context_put(gpu->mmu_context); 1571 gpu->mmu_context = NULL; 1572 } 1573 1574 gpu->exec_state = -1; 1575 1576 return etnaviv_gpu_clk_disable(gpu); 1577 } 1578 1579 #ifdef CONFIG_PM 1580 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1581 { 1582 int ret; 1583 1584 ret = mutex_lock_killable(&gpu->lock); 1585 if (ret) 1586 return ret; 1587 1588 etnaviv_gpu_update_clock(gpu); 1589 etnaviv_gpu_hw_init(gpu); 1590 1591 mutex_unlock(&gpu->lock); 1592 1593 return 0; 1594 } 1595 #endif 1596 1597 static int 1598 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1599 unsigned long *state) 1600 { 1601 *state = 6; 1602 1603 return 0; 1604 } 1605 1606 static int 1607 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1608 unsigned long *state) 1609 { 1610 struct etnaviv_gpu *gpu = cdev->devdata; 1611 1612 *state = gpu->freq_scale; 1613 1614 return 0; 1615 } 1616 1617 static int 1618 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1619 unsigned long state) 1620 { 1621 struct etnaviv_gpu *gpu = cdev->devdata; 1622 1623 mutex_lock(&gpu->lock); 1624 gpu->freq_scale = state; 1625 if (!pm_runtime_suspended(gpu->dev)) 1626 etnaviv_gpu_update_clock(gpu); 1627 mutex_unlock(&gpu->lock); 1628 1629 return 0; 1630 } 1631 1632 static struct thermal_cooling_device_ops cooling_ops = { 1633 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1634 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1635 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1636 }; 1637 1638 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1639 void *data) 1640 { 1641 struct drm_device *drm = data; 1642 struct etnaviv_drm_private *priv = drm->dev_private; 1643 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1644 int ret; 1645 1646 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1647 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1648 (char *)dev_name(dev), gpu, &cooling_ops); 1649 if (IS_ERR(gpu->cooling)) 1650 return PTR_ERR(gpu->cooling); 1651 } 1652 1653 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1654 if (!gpu->wq) { 1655 ret = -ENOMEM; 1656 goto out_thermal; 1657 } 1658 1659 ret = etnaviv_sched_init(gpu); 1660 if (ret) 1661 goto out_workqueue; 1662 1663 #ifdef CONFIG_PM 1664 ret = pm_runtime_get_sync(gpu->dev); 1665 #else 1666 ret = etnaviv_gpu_clk_enable(gpu); 1667 #endif 1668 if (ret < 0) 1669 goto out_sched; 1670 1671 1672 gpu->drm = drm; 1673 gpu->fence_context = dma_fence_context_alloc(1); 1674 idr_init(&gpu->fence_idr); 1675 spin_lock_init(&gpu->fence_spinlock); 1676 1677 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1678 init_waitqueue_head(&gpu->fence_event); 1679 1680 priv->gpu[priv->num_gpus++] = gpu; 1681 1682 pm_runtime_mark_last_busy(gpu->dev); 1683 pm_runtime_put_autosuspend(gpu->dev); 1684 1685 return 0; 1686 1687 out_sched: 1688 etnaviv_sched_fini(gpu); 1689 1690 out_workqueue: 1691 destroy_workqueue(gpu->wq); 1692 1693 out_thermal: 1694 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1695 thermal_cooling_device_unregister(gpu->cooling); 1696 1697 return ret; 1698 } 1699 1700 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1701 void *data) 1702 { 1703 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1704 1705 DBG("%s", dev_name(gpu->dev)); 1706 1707 flush_workqueue(gpu->wq); 1708 destroy_workqueue(gpu->wq); 1709 1710 etnaviv_sched_fini(gpu); 1711 1712 #ifdef CONFIG_PM 1713 pm_runtime_get_sync(gpu->dev); 1714 pm_runtime_put_sync_suspend(gpu->dev); 1715 #else 1716 etnaviv_gpu_hw_suspend(gpu); 1717 #endif 1718 1719 if (gpu->initialized) { 1720 etnaviv_cmdbuf_free(&gpu->buffer); 1721 etnaviv_iommu_global_fini(gpu); 1722 gpu->initialized = false; 1723 } 1724 1725 gpu->drm = NULL; 1726 idr_destroy(&gpu->fence_idr); 1727 1728 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1729 thermal_cooling_device_unregister(gpu->cooling); 1730 gpu->cooling = NULL; 1731 } 1732 1733 static const struct component_ops gpu_ops = { 1734 .bind = etnaviv_gpu_bind, 1735 .unbind = etnaviv_gpu_unbind, 1736 }; 1737 1738 static const struct of_device_id etnaviv_gpu_match[] = { 1739 { 1740 .compatible = "vivante,gc" 1741 }, 1742 { /* sentinel */ } 1743 }; 1744 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1745 1746 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1747 { 1748 struct device *dev = &pdev->dev; 1749 struct etnaviv_gpu *gpu; 1750 int err; 1751 1752 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1753 if (!gpu) 1754 return -ENOMEM; 1755 1756 gpu->dev = &pdev->dev; 1757 mutex_init(&gpu->lock); 1758 mutex_init(&gpu->fence_lock); 1759 1760 /* Map registers: */ 1761 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1762 if (IS_ERR(gpu->mmio)) 1763 return PTR_ERR(gpu->mmio); 1764 1765 /* Get Interrupt: */ 1766 gpu->irq = platform_get_irq(pdev, 0); 1767 if (gpu->irq < 0) { 1768 dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1769 return gpu->irq; 1770 } 1771 1772 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1773 dev_name(gpu->dev), gpu); 1774 if (err) { 1775 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1776 return err; 1777 } 1778 1779 /* Get Clocks: */ 1780 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 1781 DBG("clk_reg: %p", gpu->clk_reg); 1782 if (IS_ERR(gpu->clk_reg)) 1783 return PTR_ERR(gpu->clk_reg); 1784 1785 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1786 DBG("clk_bus: %p", gpu->clk_bus); 1787 if (IS_ERR(gpu->clk_bus)) 1788 return PTR_ERR(gpu->clk_bus); 1789 1790 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1791 DBG("clk_core: %p", gpu->clk_core); 1792 if (IS_ERR(gpu->clk_core)) 1793 return PTR_ERR(gpu->clk_core); 1794 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1795 1796 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1797 DBG("clk_shader: %p", gpu->clk_shader); 1798 if (IS_ERR(gpu->clk_shader)) 1799 return PTR_ERR(gpu->clk_shader); 1800 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1801 1802 /* TODO: figure out max mapped size */ 1803 dev_set_drvdata(dev, gpu); 1804 1805 /* 1806 * We treat the device as initially suspended. The runtime PM 1807 * autosuspend delay is rather arbitary: no measurements have 1808 * yet been performed to determine an appropriate value. 1809 */ 1810 pm_runtime_use_autosuspend(gpu->dev); 1811 pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1812 pm_runtime_enable(gpu->dev); 1813 1814 err = component_add(&pdev->dev, &gpu_ops); 1815 if (err < 0) { 1816 dev_err(&pdev->dev, "failed to register component: %d\n", err); 1817 return err; 1818 } 1819 1820 return 0; 1821 } 1822 1823 static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1824 { 1825 component_del(&pdev->dev, &gpu_ops); 1826 pm_runtime_disable(&pdev->dev); 1827 return 0; 1828 } 1829 1830 #ifdef CONFIG_PM 1831 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1832 { 1833 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1834 u32 idle, mask; 1835 1836 /* If there are any jobs in the HW queue, we're not idle */ 1837 if (atomic_read(&gpu->sched.hw_rq_count)) 1838 return -EBUSY; 1839 1840 /* Check whether the hardware (except FE and MC) is idle */ 1841 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 1842 VIVS_HI_IDLE_STATE_MC); 1843 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1844 if (idle != mask) { 1845 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 1846 idle); 1847 return -EBUSY; 1848 } 1849 1850 return etnaviv_gpu_hw_suspend(gpu); 1851 } 1852 1853 static int etnaviv_gpu_rpm_resume(struct device *dev) 1854 { 1855 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1856 int ret; 1857 1858 ret = etnaviv_gpu_clk_enable(gpu); 1859 if (ret) 1860 return ret; 1861 1862 /* Re-initialise the basic hardware state */ 1863 if (gpu->drm && gpu->initialized) { 1864 ret = etnaviv_gpu_hw_resume(gpu); 1865 if (ret) { 1866 etnaviv_gpu_clk_disable(gpu); 1867 return ret; 1868 } 1869 } 1870 1871 return 0; 1872 } 1873 #endif 1874 1875 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1876 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1877 NULL) 1878 }; 1879 1880 struct platform_driver etnaviv_gpu_driver = { 1881 .driver = { 1882 .name = "etnaviv-gpu", 1883 .owner = THIS_MODULE, 1884 .pm = &etnaviv_gpu_pm_ops, 1885 .of_match_table = etnaviv_gpu_match, 1886 }, 1887 .probe = etnaviv_gpu_platform_probe, 1888 .remove = etnaviv_gpu_platform_remove, 1889 .id_table = gpu_ids, 1890 }; 1891