1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/component.h> 18 #include <linux/dma-fence.h> 19 #include <linux/moduleparam.h> 20 #include <linux/of_device.h> 21 22 #include "etnaviv_cmdbuf.h" 23 #include "etnaviv_dump.h" 24 #include "etnaviv_gpu.h" 25 #include "etnaviv_gem.h" 26 #include "etnaviv_mmu.h" 27 #include "common.xml.h" 28 #include "state.xml.h" 29 #include "state_hi.xml.h" 30 #include "cmdstream.xml.h" 31 32 static const struct platform_device_id gpu_ids[] = { 33 { .name = "etnaviv-gpu,2d" }, 34 { }, 35 }; 36 37 static bool etnaviv_dump_core = true; 38 module_param_named(dump_core, etnaviv_dump_core, bool, 0600); 39 40 /* 41 * Driver functions: 42 */ 43 44 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 45 { 46 switch (param) { 47 case ETNAVIV_PARAM_GPU_MODEL: 48 *value = gpu->identity.model; 49 break; 50 51 case ETNAVIV_PARAM_GPU_REVISION: 52 *value = gpu->identity.revision; 53 break; 54 55 case ETNAVIV_PARAM_GPU_FEATURES_0: 56 *value = gpu->identity.features; 57 break; 58 59 case ETNAVIV_PARAM_GPU_FEATURES_1: 60 *value = gpu->identity.minor_features0; 61 break; 62 63 case ETNAVIV_PARAM_GPU_FEATURES_2: 64 *value = gpu->identity.minor_features1; 65 break; 66 67 case ETNAVIV_PARAM_GPU_FEATURES_3: 68 *value = gpu->identity.minor_features2; 69 break; 70 71 case ETNAVIV_PARAM_GPU_FEATURES_4: 72 *value = gpu->identity.minor_features3; 73 break; 74 75 case ETNAVIV_PARAM_GPU_FEATURES_5: 76 *value = gpu->identity.minor_features4; 77 break; 78 79 case ETNAVIV_PARAM_GPU_FEATURES_6: 80 *value = gpu->identity.minor_features5; 81 break; 82 83 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 84 *value = gpu->identity.stream_count; 85 break; 86 87 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 88 *value = gpu->identity.register_max; 89 break; 90 91 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 92 *value = gpu->identity.thread_count; 93 break; 94 95 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 96 *value = gpu->identity.vertex_cache_size; 97 break; 98 99 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 100 *value = gpu->identity.shader_core_count; 101 break; 102 103 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 104 *value = gpu->identity.pixel_pipes; 105 break; 106 107 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 108 *value = gpu->identity.vertex_output_buffer_size; 109 break; 110 111 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 112 *value = gpu->identity.buffer_size; 113 break; 114 115 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 116 *value = gpu->identity.instruction_count; 117 break; 118 119 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 120 *value = gpu->identity.num_constants; 121 break; 122 123 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 124 *value = gpu->identity.varyings_count; 125 break; 126 127 default: 128 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 129 return -EINVAL; 130 } 131 132 return 0; 133 } 134 135 136 #define etnaviv_is_model_rev(gpu, mod, rev) \ 137 ((gpu)->identity.model == chipModel_##mod && \ 138 (gpu)->identity.revision == rev) 139 #define etnaviv_field(val, field) \ 140 (((val) & field##__MASK) >> field##__SHIFT) 141 142 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 143 { 144 if (gpu->identity.minor_features0 & 145 chipMinorFeatures0_MORE_MINOR_FEATURES) { 146 u32 specs[4]; 147 unsigned int streams; 148 149 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 150 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 151 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 152 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 153 154 gpu->identity.stream_count = etnaviv_field(specs[0], 155 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 156 gpu->identity.register_max = etnaviv_field(specs[0], 157 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 158 gpu->identity.thread_count = etnaviv_field(specs[0], 159 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 160 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 161 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 162 gpu->identity.shader_core_count = etnaviv_field(specs[0], 163 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 164 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 165 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 166 gpu->identity.vertex_output_buffer_size = 167 etnaviv_field(specs[0], 168 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 169 170 gpu->identity.buffer_size = etnaviv_field(specs[1], 171 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 172 gpu->identity.instruction_count = etnaviv_field(specs[1], 173 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 174 gpu->identity.num_constants = etnaviv_field(specs[1], 175 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 176 177 gpu->identity.varyings_count = etnaviv_field(specs[2], 178 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 179 180 /* This overrides the value from older register if non-zero */ 181 streams = etnaviv_field(specs[3], 182 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 183 if (streams) 184 gpu->identity.stream_count = streams; 185 } 186 187 /* Fill in the stream count if not specified */ 188 if (gpu->identity.stream_count == 0) { 189 if (gpu->identity.model >= 0x1000) 190 gpu->identity.stream_count = 4; 191 else 192 gpu->identity.stream_count = 1; 193 } 194 195 /* Convert the register max value */ 196 if (gpu->identity.register_max) 197 gpu->identity.register_max = 1 << gpu->identity.register_max; 198 else if (gpu->identity.model == chipModel_GC400) 199 gpu->identity.register_max = 32; 200 else 201 gpu->identity.register_max = 64; 202 203 /* Convert thread count */ 204 if (gpu->identity.thread_count) 205 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 206 else if (gpu->identity.model == chipModel_GC400) 207 gpu->identity.thread_count = 64; 208 else if (gpu->identity.model == chipModel_GC500 || 209 gpu->identity.model == chipModel_GC530) 210 gpu->identity.thread_count = 128; 211 else 212 gpu->identity.thread_count = 256; 213 214 if (gpu->identity.vertex_cache_size == 0) 215 gpu->identity.vertex_cache_size = 8; 216 217 if (gpu->identity.shader_core_count == 0) { 218 if (gpu->identity.model >= 0x1000) 219 gpu->identity.shader_core_count = 2; 220 else 221 gpu->identity.shader_core_count = 1; 222 } 223 224 if (gpu->identity.pixel_pipes == 0) 225 gpu->identity.pixel_pipes = 1; 226 227 /* Convert virtex buffer size */ 228 if (gpu->identity.vertex_output_buffer_size) { 229 gpu->identity.vertex_output_buffer_size = 230 1 << gpu->identity.vertex_output_buffer_size; 231 } else if (gpu->identity.model == chipModel_GC400) { 232 if (gpu->identity.revision < 0x4000) 233 gpu->identity.vertex_output_buffer_size = 512; 234 else if (gpu->identity.revision < 0x4200) 235 gpu->identity.vertex_output_buffer_size = 256; 236 else 237 gpu->identity.vertex_output_buffer_size = 128; 238 } else { 239 gpu->identity.vertex_output_buffer_size = 512; 240 } 241 242 switch (gpu->identity.instruction_count) { 243 case 0: 244 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 245 gpu->identity.model == chipModel_GC880) 246 gpu->identity.instruction_count = 512; 247 else 248 gpu->identity.instruction_count = 256; 249 break; 250 251 case 1: 252 gpu->identity.instruction_count = 1024; 253 break; 254 255 case 2: 256 gpu->identity.instruction_count = 2048; 257 break; 258 259 default: 260 gpu->identity.instruction_count = 256; 261 break; 262 } 263 264 if (gpu->identity.num_constants == 0) 265 gpu->identity.num_constants = 168; 266 267 if (gpu->identity.varyings_count == 0) { 268 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 269 gpu->identity.varyings_count = 12; 270 else 271 gpu->identity.varyings_count = 8; 272 } 273 274 /* 275 * For some cores, two varyings are consumed for position, so the 276 * maximum varying count needs to be reduced by one. 277 */ 278 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 279 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 280 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 281 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 282 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 283 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 284 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 285 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 286 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 287 etnaviv_is_model_rev(gpu, GC880, 0x5107) || 288 etnaviv_is_model_rev(gpu, GC880, 0x5106)) 289 gpu->identity.varyings_count -= 1; 290 } 291 292 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 293 { 294 u32 chipIdentity; 295 296 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 297 298 /* Special case for older graphic cores. */ 299 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 300 gpu->identity.model = chipModel_GC500; 301 gpu->identity.revision = etnaviv_field(chipIdentity, 302 VIVS_HI_CHIP_IDENTITY_REVISION); 303 } else { 304 305 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 306 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 307 308 /* 309 * !!!! HACK ALERT !!!! 310 * Because people change device IDs without letting software 311 * know about it - here is the hack to make it all look the 312 * same. Only for GC400 family. 313 */ 314 if ((gpu->identity.model & 0xff00) == 0x0400 && 315 gpu->identity.model != chipModel_GC420) { 316 gpu->identity.model = gpu->identity.model & 0x0400; 317 } 318 319 /* Another special case */ 320 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 321 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 322 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 323 324 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 325 /* 326 * This IP has an ECO; put the correct 327 * revision in it. 328 */ 329 gpu->identity.revision = 0x1051; 330 } 331 } 332 333 /* 334 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 335 * reality it's just a re-branded GC3000. We can identify this 336 * core by the upper half of the revision register being all 1. 337 * Fix model/rev here, so all other places can refer to this 338 * core by its real identity. 339 */ 340 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 341 gpu->identity.model = chipModel_GC3000; 342 gpu->identity.revision &= 0xffff; 343 } 344 } 345 346 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 347 gpu->identity.model, gpu->identity.revision); 348 349 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 350 351 /* Disable fast clear on GC700. */ 352 if (gpu->identity.model == chipModel_GC700) 353 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 354 355 if ((gpu->identity.model == chipModel_GC500 && 356 gpu->identity.revision < 2) || 357 (gpu->identity.model == chipModel_GC300 && 358 gpu->identity.revision < 0x2000)) { 359 360 /* 361 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 362 * registers. 363 */ 364 gpu->identity.minor_features0 = 0; 365 gpu->identity.minor_features1 = 0; 366 gpu->identity.minor_features2 = 0; 367 gpu->identity.minor_features3 = 0; 368 gpu->identity.minor_features4 = 0; 369 gpu->identity.minor_features5 = 0; 370 } else 371 gpu->identity.minor_features0 = 372 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 373 374 if (gpu->identity.minor_features0 & 375 chipMinorFeatures0_MORE_MINOR_FEATURES) { 376 gpu->identity.minor_features1 = 377 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 378 gpu->identity.minor_features2 = 379 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 380 gpu->identity.minor_features3 = 381 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 382 gpu->identity.minor_features4 = 383 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 384 gpu->identity.minor_features5 = 385 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 386 } 387 388 /* GC600 idle register reports zero bits where modules aren't present */ 389 if (gpu->identity.model == chipModel_GC600) { 390 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 391 VIVS_HI_IDLE_STATE_RA | 392 VIVS_HI_IDLE_STATE_SE | 393 VIVS_HI_IDLE_STATE_PA | 394 VIVS_HI_IDLE_STATE_SH | 395 VIVS_HI_IDLE_STATE_PE | 396 VIVS_HI_IDLE_STATE_DE | 397 VIVS_HI_IDLE_STATE_FE; 398 } else { 399 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 400 } 401 402 etnaviv_hw_specs(gpu); 403 } 404 405 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 406 { 407 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 408 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 409 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 410 } 411 412 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 413 { 414 u32 control, idle; 415 unsigned long timeout; 416 bool failed = true; 417 418 /* TODO 419 * 420 * - clock gating 421 * - puls eater 422 * - what about VG? 423 */ 424 425 /* We hope that the GPU resets in under one second */ 426 timeout = jiffies + msecs_to_jiffies(1000); 427 428 while (time_is_after_jiffies(timeout)) { 429 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 430 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 431 432 /* enable clock */ 433 etnaviv_gpu_load_clock(gpu, control); 434 435 /* Wait for stable clock. Vivante's code waited for 1ms */ 436 usleep_range(1000, 10000); 437 438 /* isolate the GPU. */ 439 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 440 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 441 442 /* set soft reset. */ 443 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 444 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 445 446 /* wait for reset. */ 447 msleep(1); 448 449 /* reset soft reset bit. */ 450 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 451 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 452 453 /* reset GPU isolation. */ 454 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 455 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 456 457 /* read idle register. */ 458 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 459 460 /* try reseting again if FE it not idle */ 461 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 462 dev_dbg(gpu->dev, "FE is not idle\n"); 463 continue; 464 } 465 466 /* read reset register. */ 467 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 468 469 /* is the GPU idle? */ 470 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 471 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 472 dev_dbg(gpu->dev, "GPU is not idle\n"); 473 continue; 474 } 475 476 failed = false; 477 break; 478 } 479 480 if (failed) { 481 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 482 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 483 484 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 485 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 486 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 487 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 488 489 return -EBUSY; 490 } 491 492 /* We rely on the GPU running, so program the clock */ 493 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 494 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 495 496 /* enable clock */ 497 etnaviv_gpu_load_clock(gpu, control); 498 499 return 0; 500 } 501 502 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 503 { 504 u32 pmc, ppc; 505 506 /* enable clock gating */ 507 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 508 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 509 510 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 511 if (gpu->identity.revision == 0x4301 || 512 gpu->identity.revision == 0x4302) 513 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 514 515 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 516 517 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 518 519 /* Disable PA clock gating for GC400+ except for GC420 */ 520 if (gpu->identity.model >= chipModel_GC400 && 521 gpu->identity.model != chipModel_GC420) 522 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 523 524 /* 525 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 526 * present without a bug fix. 527 */ 528 if (gpu->identity.revision < 0x5000 && 529 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 530 !(gpu->identity.minor_features1 & 531 chipMinorFeatures1_DISABLE_PE_GATING)) 532 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 533 534 if (gpu->identity.revision < 0x5422) 535 pmc |= BIT(15); /* Unknown bit */ 536 537 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 538 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 539 540 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 541 } 542 543 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 544 { 545 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 546 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 547 VIVS_FE_COMMAND_CONTROL_ENABLE | 548 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 549 } 550 551 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 552 { 553 /* 554 * Base value for VIVS_PM_PULSE_EATER register on models where it 555 * cannot be read, extracted from vivante kernel driver. 556 */ 557 u32 pulse_eater = 0x01590880; 558 559 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 560 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 561 pulse_eater |= BIT(23); 562 563 } 564 565 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 566 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 567 pulse_eater &= ~BIT(16); 568 pulse_eater |= BIT(17); 569 } 570 571 if ((gpu->identity.revision > 0x5420) && 572 (gpu->identity.features & chipFeatures_PIPE_3D)) 573 { 574 /* Performance fix: disable internal DFS */ 575 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 576 pulse_eater |= BIT(18); 577 } 578 579 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 580 } 581 582 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 583 { 584 u16 prefetch; 585 586 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 587 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 588 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 589 u32 mc_memory_debug; 590 591 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 592 593 if (gpu->identity.revision == 0x5007) 594 mc_memory_debug |= 0x0c; 595 else 596 mc_memory_debug |= 0x08; 597 598 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 599 } 600 601 /* enable module-level clock gating */ 602 etnaviv_gpu_enable_mlcg(gpu); 603 604 /* 605 * Update GPU AXI cache atttribute to "cacheable, no allocate". 606 * This is necessary to prevent the iMX6 SoC locking up. 607 */ 608 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 609 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 610 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 611 612 /* GC2000 rev 5108 needs a special bus config */ 613 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 614 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 615 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 616 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 617 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 618 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 619 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 620 } 621 622 /* setup the pulse eater */ 623 etnaviv_gpu_setup_pulse_eater(gpu); 624 625 /* setup the MMU */ 626 etnaviv_iommu_restore(gpu); 627 628 /* Start command processor */ 629 prefetch = etnaviv_buffer_init(gpu); 630 631 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 632 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer), 633 prefetch); 634 } 635 636 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 637 { 638 int ret, i; 639 640 ret = pm_runtime_get_sync(gpu->dev); 641 if (ret < 0) { 642 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 643 return ret; 644 } 645 646 etnaviv_hw_identify(gpu); 647 648 if (gpu->identity.model == 0) { 649 dev_err(gpu->dev, "Unknown GPU model\n"); 650 ret = -ENXIO; 651 goto fail; 652 } 653 654 /* Exclude VG cores with FE2.0 */ 655 if (gpu->identity.features & chipFeatures_PIPE_VG && 656 gpu->identity.features & chipFeatures_FE20) { 657 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 658 ret = -ENXIO; 659 goto fail; 660 } 661 662 /* 663 * Set the GPU linear window to be at the end of the DMA window, where 664 * the CMA area is likely to reside. This ensures that we are able to 665 * map the command buffers while having the linear window overlap as 666 * much RAM as possible, so we can optimize mappings for other buffers. 667 * 668 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 669 * to different views of the memory on the individual engines. 670 */ 671 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 672 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 673 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 674 if (dma_mask < PHYS_OFFSET + SZ_2G) 675 gpu->memory_base = PHYS_OFFSET; 676 else 677 gpu->memory_base = dma_mask - SZ_2G + 1; 678 } else if (PHYS_OFFSET >= SZ_2G) { 679 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 680 gpu->memory_base = PHYS_OFFSET; 681 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 682 } 683 684 ret = etnaviv_hw_reset(gpu); 685 if (ret) { 686 dev_err(gpu->dev, "GPU reset failed\n"); 687 goto fail; 688 } 689 690 gpu->mmu = etnaviv_iommu_new(gpu); 691 if (IS_ERR(gpu->mmu)) { 692 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 693 ret = PTR_ERR(gpu->mmu); 694 goto fail; 695 } 696 697 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu); 698 if (IS_ERR(gpu->cmdbuf_suballoc)) { 699 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); 700 ret = PTR_ERR(gpu->cmdbuf_suballoc); 701 goto fail; 702 } 703 704 /* Create buffer: */ 705 gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0); 706 if (!gpu->buffer) { 707 ret = -ENOMEM; 708 dev_err(gpu->dev, "could not create command buffer\n"); 709 goto destroy_iommu; 710 } 711 712 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 713 etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) { 714 ret = -EINVAL; 715 dev_err(gpu->dev, 716 "command buffer outside valid memory window\n"); 717 goto free_buffer; 718 } 719 720 /* Setup event management */ 721 spin_lock_init(&gpu->event_spinlock); 722 init_completion(&gpu->event_free); 723 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 724 gpu->event[i].used = false; 725 complete(&gpu->event_free); 726 } 727 728 /* Now program the hardware */ 729 mutex_lock(&gpu->lock); 730 etnaviv_gpu_hw_init(gpu); 731 gpu->exec_state = -1; 732 mutex_unlock(&gpu->lock); 733 734 pm_runtime_mark_last_busy(gpu->dev); 735 pm_runtime_put_autosuspend(gpu->dev); 736 737 return 0; 738 739 free_buffer: 740 etnaviv_cmdbuf_free(gpu->buffer); 741 gpu->buffer = NULL; 742 destroy_iommu: 743 etnaviv_iommu_destroy(gpu->mmu); 744 gpu->mmu = NULL; 745 fail: 746 pm_runtime_mark_last_busy(gpu->dev); 747 pm_runtime_put_autosuspend(gpu->dev); 748 749 return ret; 750 } 751 752 #ifdef CONFIG_DEBUG_FS 753 struct dma_debug { 754 u32 address[2]; 755 u32 state[2]; 756 }; 757 758 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 759 { 760 u32 i; 761 762 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 763 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 764 765 for (i = 0; i < 500; i++) { 766 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 767 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 768 769 if (debug->address[0] != debug->address[1]) 770 break; 771 772 if (debug->state[0] != debug->state[1]) 773 break; 774 } 775 } 776 777 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 778 { 779 struct dma_debug debug; 780 u32 dma_lo, dma_hi, axi, idle; 781 int ret; 782 783 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 784 785 ret = pm_runtime_get_sync(gpu->dev); 786 if (ret < 0) 787 return ret; 788 789 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 790 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 791 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 792 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 793 794 verify_dma(gpu, &debug); 795 796 seq_puts(m, "\tfeatures\n"); 797 seq_printf(m, "\t minor_features0: 0x%08x\n", 798 gpu->identity.minor_features0); 799 seq_printf(m, "\t minor_features1: 0x%08x\n", 800 gpu->identity.minor_features1); 801 seq_printf(m, "\t minor_features2: 0x%08x\n", 802 gpu->identity.minor_features2); 803 seq_printf(m, "\t minor_features3: 0x%08x\n", 804 gpu->identity.minor_features3); 805 seq_printf(m, "\t minor_features4: 0x%08x\n", 806 gpu->identity.minor_features4); 807 seq_printf(m, "\t minor_features5: 0x%08x\n", 808 gpu->identity.minor_features5); 809 810 seq_puts(m, "\tspecs\n"); 811 seq_printf(m, "\t stream_count: %d\n", 812 gpu->identity.stream_count); 813 seq_printf(m, "\t register_max: %d\n", 814 gpu->identity.register_max); 815 seq_printf(m, "\t thread_count: %d\n", 816 gpu->identity.thread_count); 817 seq_printf(m, "\t vertex_cache_size: %d\n", 818 gpu->identity.vertex_cache_size); 819 seq_printf(m, "\t shader_core_count: %d\n", 820 gpu->identity.shader_core_count); 821 seq_printf(m, "\t pixel_pipes: %d\n", 822 gpu->identity.pixel_pipes); 823 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 824 gpu->identity.vertex_output_buffer_size); 825 seq_printf(m, "\t buffer_size: %d\n", 826 gpu->identity.buffer_size); 827 seq_printf(m, "\t instruction_count: %d\n", 828 gpu->identity.instruction_count); 829 seq_printf(m, "\t num_constants: %d\n", 830 gpu->identity.num_constants); 831 seq_printf(m, "\t varyings_count: %d\n", 832 gpu->identity.varyings_count); 833 834 seq_printf(m, "\taxi: 0x%08x\n", axi); 835 seq_printf(m, "\tidle: 0x%08x\n", idle); 836 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 837 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 838 seq_puts(m, "\t FE is not idle\n"); 839 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 840 seq_puts(m, "\t DE is not idle\n"); 841 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 842 seq_puts(m, "\t PE is not idle\n"); 843 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 844 seq_puts(m, "\t SH is not idle\n"); 845 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 846 seq_puts(m, "\t PA is not idle\n"); 847 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 848 seq_puts(m, "\t SE is not idle\n"); 849 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 850 seq_puts(m, "\t RA is not idle\n"); 851 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 852 seq_puts(m, "\t TX is not idle\n"); 853 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 854 seq_puts(m, "\t VG is not idle\n"); 855 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 856 seq_puts(m, "\t IM is not idle\n"); 857 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 858 seq_puts(m, "\t FP is not idle\n"); 859 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 860 seq_puts(m, "\t TS is not idle\n"); 861 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 862 seq_puts(m, "\t AXI low power mode\n"); 863 864 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 865 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 866 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 867 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 868 869 seq_puts(m, "\tMC\n"); 870 seq_printf(m, "\t read0: 0x%08x\n", read0); 871 seq_printf(m, "\t read1: 0x%08x\n", read1); 872 seq_printf(m, "\t write: 0x%08x\n", write); 873 } 874 875 seq_puts(m, "\tDMA "); 876 877 if (debug.address[0] == debug.address[1] && 878 debug.state[0] == debug.state[1]) { 879 seq_puts(m, "seems to be stuck\n"); 880 } else if (debug.address[0] == debug.address[1]) { 881 seq_puts(m, "address is constant\n"); 882 } else { 883 seq_puts(m, "is running\n"); 884 } 885 886 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 887 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 888 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 889 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 890 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 891 dma_lo, dma_hi); 892 893 ret = 0; 894 895 pm_runtime_mark_last_busy(gpu->dev); 896 pm_runtime_put_autosuspend(gpu->dev); 897 898 return ret; 899 } 900 #endif 901 902 /* 903 * Hangcheck detection for locked gpu: 904 */ 905 static void recover_worker(struct work_struct *work) 906 { 907 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 908 recover_work); 909 unsigned long flags; 910 unsigned int i; 911 912 dev_err(gpu->dev, "hangcheck recover!\n"); 913 914 if (pm_runtime_get_sync(gpu->dev) < 0) 915 return; 916 917 mutex_lock(&gpu->lock); 918 919 /* Only catch the first event, or when manually re-armed */ 920 if (etnaviv_dump_core) { 921 etnaviv_core_dump(gpu); 922 etnaviv_dump_core = false; 923 } 924 925 etnaviv_hw_reset(gpu); 926 927 /* complete all events, the GPU won't do it after the reset */ 928 spin_lock_irqsave(&gpu->event_spinlock, flags); 929 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 930 if (!gpu->event[i].used) 931 continue; 932 dma_fence_signal(gpu->event[i].fence); 933 gpu->event[i].fence = NULL; 934 gpu->event[i].used = false; 935 complete(&gpu->event_free); 936 } 937 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 938 gpu->completed_fence = gpu->active_fence; 939 940 etnaviv_gpu_hw_init(gpu); 941 gpu->lastctx = NULL; 942 gpu->exec_state = -1; 943 944 mutex_unlock(&gpu->lock); 945 pm_runtime_mark_last_busy(gpu->dev); 946 pm_runtime_put_autosuspend(gpu->dev); 947 948 /* Retire the buffer objects in a work */ 949 etnaviv_queue_work(gpu->drm, &gpu->retire_work); 950 } 951 952 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) 953 { 954 DBG("%s", dev_name(gpu->dev)); 955 mod_timer(&gpu->hangcheck_timer, 956 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); 957 } 958 959 static void hangcheck_handler(unsigned long data) 960 { 961 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data; 962 u32 fence = gpu->completed_fence; 963 bool progress = false; 964 965 if (fence != gpu->hangcheck_fence) { 966 gpu->hangcheck_fence = fence; 967 progress = true; 968 } 969 970 if (!progress) { 971 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 972 int change = dma_addr - gpu->hangcheck_dma_addr; 973 974 if (change < 0 || change > 16) { 975 gpu->hangcheck_dma_addr = dma_addr; 976 progress = true; 977 } 978 } 979 980 if (!progress && fence_after(gpu->active_fence, fence)) { 981 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); 982 dev_err(gpu->dev, " completed fence: %u\n", fence); 983 dev_err(gpu->dev, " active fence: %u\n", 984 gpu->active_fence); 985 etnaviv_queue_work(gpu->drm, &gpu->recover_work); 986 } 987 988 /* if still more pending work, reset the hangcheck timer: */ 989 if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) 990 hangcheck_timer_reset(gpu); 991 } 992 993 static void hangcheck_disable(struct etnaviv_gpu *gpu) 994 { 995 del_timer_sync(&gpu->hangcheck_timer); 996 cancel_work_sync(&gpu->recover_work); 997 } 998 999 /* fence object management */ 1000 struct etnaviv_fence { 1001 struct etnaviv_gpu *gpu; 1002 struct dma_fence base; 1003 }; 1004 1005 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1006 { 1007 return container_of(fence, struct etnaviv_fence, base); 1008 } 1009 1010 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1011 { 1012 return "etnaviv"; 1013 } 1014 1015 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1016 { 1017 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1018 1019 return dev_name(f->gpu->dev); 1020 } 1021 1022 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence) 1023 { 1024 return true; 1025 } 1026 1027 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1028 { 1029 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1030 1031 return fence_completed(f->gpu, f->base.seqno); 1032 } 1033 1034 static void etnaviv_fence_release(struct dma_fence *fence) 1035 { 1036 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1037 1038 kfree_rcu(f, base.rcu); 1039 } 1040 1041 static const struct dma_fence_ops etnaviv_fence_ops = { 1042 .get_driver_name = etnaviv_fence_get_driver_name, 1043 .get_timeline_name = etnaviv_fence_get_timeline_name, 1044 .enable_signaling = etnaviv_fence_enable_signaling, 1045 .signaled = etnaviv_fence_signaled, 1046 .wait = dma_fence_default_wait, 1047 .release = etnaviv_fence_release, 1048 }; 1049 1050 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1051 { 1052 struct etnaviv_fence *f; 1053 1054 f = kzalloc(sizeof(*f), GFP_KERNEL); 1055 if (!f) 1056 return NULL; 1057 1058 f->gpu = gpu; 1059 1060 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1061 gpu->fence_context, ++gpu->next_fence); 1062 1063 return &f->base; 1064 } 1065 1066 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 1067 unsigned int context, bool exclusive) 1068 { 1069 struct reservation_object *robj = etnaviv_obj->resv; 1070 struct reservation_object_list *fobj; 1071 struct dma_fence *fence; 1072 int i, ret; 1073 1074 if (!exclusive) { 1075 ret = reservation_object_reserve_shared(robj); 1076 if (ret) 1077 return ret; 1078 } 1079 1080 /* 1081 * If we have any shared fences, then the exclusive fence 1082 * should be ignored as it will already have been signalled. 1083 */ 1084 fobj = reservation_object_get_list(robj); 1085 if (!fobj || fobj->shared_count == 0) { 1086 /* Wait on any existing exclusive fence which isn't our own */ 1087 fence = reservation_object_get_excl(robj); 1088 if (fence && fence->context != context) { 1089 ret = dma_fence_wait(fence, true); 1090 if (ret) 1091 return ret; 1092 } 1093 } 1094 1095 if (!exclusive || !fobj) 1096 return 0; 1097 1098 for (i = 0; i < fobj->shared_count; i++) { 1099 fence = rcu_dereference_protected(fobj->shared[i], 1100 reservation_object_held(robj)); 1101 if (fence->context != context) { 1102 ret = dma_fence_wait(fence, true); 1103 if (ret) 1104 return ret; 1105 } 1106 } 1107 1108 return 0; 1109 } 1110 1111 /* 1112 * event management: 1113 */ 1114 1115 static unsigned int event_alloc(struct etnaviv_gpu *gpu) 1116 { 1117 unsigned long ret, flags; 1118 unsigned int i, event = ~0U; 1119 1120 ret = wait_for_completion_timeout(&gpu->event_free, 1121 msecs_to_jiffies(10 * 10000)); 1122 if (!ret) 1123 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1124 1125 spin_lock_irqsave(&gpu->event_spinlock, flags); 1126 1127 /* find first free event */ 1128 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 1129 if (gpu->event[i].used == false) { 1130 gpu->event[i].used = true; 1131 event = i; 1132 break; 1133 } 1134 } 1135 1136 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1137 1138 return event; 1139 } 1140 1141 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1142 { 1143 unsigned long flags; 1144 1145 spin_lock_irqsave(&gpu->event_spinlock, flags); 1146 1147 if (gpu->event[event].used == false) { 1148 dev_warn(gpu->dev, "event %u is already marked as free", 1149 event); 1150 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1151 } else { 1152 gpu->event[event].used = false; 1153 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1154 1155 complete(&gpu->event_free); 1156 } 1157 } 1158 1159 /* 1160 * Cmdstream submission/retirement: 1161 */ 1162 1163 static void retire_worker(struct work_struct *work) 1164 { 1165 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1166 retire_work); 1167 u32 fence = gpu->completed_fence; 1168 struct etnaviv_cmdbuf *cmdbuf, *tmp; 1169 unsigned int i; 1170 1171 mutex_lock(&gpu->lock); 1172 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { 1173 if (!dma_fence_is_signaled(cmdbuf->fence)) 1174 break; 1175 1176 list_del(&cmdbuf->node); 1177 dma_fence_put(cmdbuf->fence); 1178 1179 for (i = 0; i < cmdbuf->nr_bos; i++) { 1180 struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; 1181 struct etnaviv_gem_object *etnaviv_obj = mapping->object; 1182 1183 atomic_dec(&etnaviv_obj->gpu_active); 1184 /* drop the refcount taken in etnaviv_gpu_submit */ 1185 etnaviv_gem_mapping_unreference(mapping); 1186 } 1187 1188 etnaviv_cmdbuf_free(cmdbuf); 1189 /* 1190 * We need to balance the runtime PM count caused by 1191 * each submission. Upon submission, we increment 1192 * the runtime PM counter, and allocate one event. 1193 * So here, we put the runtime PM count for each 1194 * completed event. 1195 */ 1196 pm_runtime_put_autosuspend(gpu->dev); 1197 } 1198 1199 gpu->retired_fence = fence; 1200 1201 mutex_unlock(&gpu->lock); 1202 1203 wake_up_all(&gpu->fence_event); 1204 } 1205 1206 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1207 u32 fence, struct timespec *timeout) 1208 { 1209 int ret; 1210 1211 if (fence_after(fence, gpu->next_fence)) { 1212 DRM_ERROR("waiting on invalid fence: %u (of %u)\n", 1213 fence, gpu->next_fence); 1214 return -EINVAL; 1215 } 1216 1217 if (!timeout) { 1218 /* No timeout was requested: just test for completion */ 1219 ret = fence_completed(gpu, fence) ? 0 : -EBUSY; 1220 } else { 1221 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1222 1223 ret = wait_event_interruptible_timeout(gpu->fence_event, 1224 fence_completed(gpu, fence), 1225 remaining); 1226 if (ret == 0) { 1227 DBG("timeout waiting for fence: %u (retired: %u completed: %u)", 1228 fence, gpu->retired_fence, 1229 gpu->completed_fence); 1230 ret = -ETIMEDOUT; 1231 } else if (ret != -ERESTARTSYS) { 1232 ret = 0; 1233 } 1234 } 1235 1236 return ret; 1237 } 1238 1239 /* 1240 * Wait for an object to become inactive. This, on it's own, is not race 1241 * free: the object is moved by the retire worker off the active list, and 1242 * then the iova is put. Moreover, the object could be re-submitted just 1243 * after we notice that it's become inactive. 1244 * 1245 * Although the retirement happens under the gpu lock, we don't want to hold 1246 * that lock in this function while waiting. 1247 */ 1248 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1249 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1250 { 1251 unsigned long remaining; 1252 long ret; 1253 1254 if (!timeout) 1255 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1256 1257 remaining = etnaviv_timeout_to_jiffies(timeout); 1258 1259 ret = wait_event_interruptible_timeout(gpu->fence_event, 1260 !is_active(etnaviv_obj), 1261 remaining); 1262 if (ret > 0) { 1263 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 1264 1265 /* Synchronise with the retire worker */ 1266 flush_workqueue(priv->wq); 1267 return 0; 1268 } else if (ret == -ERESTARTSYS) { 1269 return -ERESTARTSYS; 1270 } else { 1271 return -ETIMEDOUT; 1272 } 1273 } 1274 1275 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) 1276 { 1277 return pm_runtime_get_sync(gpu->dev); 1278 } 1279 1280 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) 1281 { 1282 pm_runtime_mark_last_busy(gpu->dev); 1283 pm_runtime_put_autosuspend(gpu->dev); 1284 } 1285 1286 /* add bo's to gpu's ring, and kick gpu: */ 1287 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 1288 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) 1289 { 1290 struct dma_fence *fence; 1291 unsigned int event, i; 1292 int ret; 1293 1294 ret = etnaviv_gpu_pm_get_sync(gpu); 1295 if (ret < 0) 1296 return ret; 1297 1298 /* 1299 * TODO 1300 * 1301 * - flush 1302 * - data endian 1303 * - prefetch 1304 * 1305 */ 1306 1307 event = event_alloc(gpu); 1308 if (unlikely(event == ~0U)) { 1309 DRM_ERROR("no free event\n"); 1310 ret = -EBUSY; 1311 goto out_pm_put; 1312 } 1313 1314 mutex_lock(&gpu->lock); 1315 1316 fence = etnaviv_gpu_fence_alloc(gpu); 1317 if (!fence) { 1318 event_free(gpu, event); 1319 ret = -ENOMEM; 1320 goto out_unlock; 1321 } 1322 1323 gpu->event[event].fence = fence; 1324 submit->fence = fence->seqno; 1325 gpu->active_fence = submit->fence; 1326 1327 if (gpu->lastctx != cmdbuf->ctx) { 1328 gpu->mmu->need_flush = true; 1329 gpu->switch_context = true; 1330 gpu->lastctx = cmdbuf->ctx; 1331 } 1332 1333 etnaviv_buffer_queue(gpu, event, cmdbuf); 1334 1335 cmdbuf->fence = fence; 1336 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); 1337 1338 /* We're committed to adding this command buffer, hold a PM reference */ 1339 pm_runtime_get_noresume(gpu->dev); 1340 1341 for (i = 0; i < submit->nr_bos; i++) { 1342 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; 1343 1344 /* Each cmdbuf takes a refcount on the mapping */ 1345 etnaviv_gem_mapping_reference(submit->bos[i].mapping); 1346 cmdbuf->bo_map[i] = submit->bos[i].mapping; 1347 atomic_inc(&etnaviv_obj->gpu_active); 1348 1349 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) 1350 reservation_object_add_excl_fence(etnaviv_obj->resv, 1351 fence); 1352 else 1353 reservation_object_add_shared_fence(etnaviv_obj->resv, 1354 fence); 1355 } 1356 cmdbuf->nr_bos = submit->nr_bos; 1357 hangcheck_timer_reset(gpu); 1358 ret = 0; 1359 1360 out_unlock: 1361 mutex_unlock(&gpu->lock); 1362 1363 out_pm_put: 1364 etnaviv_gpu_pm_put(gpu); 1365 1366 return ret; 1367 } 1368 1369 /* 1370 * Init/Cleanup: 1371 */ 1372 static irqreturn_t irq_handler(int irq, void *data) 1373 { 1374 struct etnaviv_gpu *gpu = data; 1375 irqreturn_t ret = IRQ_NONE; 1376 1377 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1378 1379 if (intr != 0) { 1380 int event; 1381 1382 pm_runtime_mark_last_busy(gpu->dev); 1383 1384 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1385 1386 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1387 dev_err(gpu->dev, "AXI bus error\n"); 1388 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1389 } 1390 1391 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1392 int i; 1393 1394 dev_err_ratelimited(gpu->dev, 1395 "MMU fault status 0x%08x\n", 1396 gpu_read(gpu, VIVS_MMUv2_STATUS)); 1397 for (i = 0; i < 4; i++) { 1398 dev_err_ratelimited(gpu->dev, 1399 "MMU %d fault addr 0x%08x\n", 1400 i, gpu_read(gpu, 1401 VIVS_MMUv2_EXCEPTION_ADDR(i))); 1402 } 1403 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1404 } 1405 1406 while ((event = ffs(intr)) != 0) { 1407 struct dma_fence *fence; 1408 1409 event -= 1; 1410 1411 intr &= ~(1 << event); 1412 1413 dev_dbg(gpu->dev, "event %u\n", event); 1414 1415 fence = gpu->event[event].fence; 1416 gpu->event[event].fence = NULL; 1417 dma_fence_signal(fence); 1418 1419 /* 1420 * Events can be processed out of order. Eg, 1421 * - allocate and queue event 0 1422 * - allocate event 1 1423 * - event 0 completes, we process it 1424 * - allocate and queue event 0 1425 * - event 1 and event 0 complete 1426 * we can end up processing event 0 first, then 1. 1427 */ 1428 if (fence_after(fence->seqno, gpu->completed_fence)) 1429 gpu->completed_fence = fence->seqno; 1430 1431 event_free(gpu, event); 1432 } 1433 1434 /* Retire the buffer objects in a work */ 1435 etnaviv_queue_work(gpu->drm, &gpu->retire_work); 1436 1437 ret = IRQ_HANDLED; 1438 } 1439 1440 return ret; 1441 } 1442 1443 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1444 { 1445 int ret; 1446 1447 if (gpu->clk_bus) { 1448 ret = clk_prepare_enable(gpu->clk_bus); 1449 if (ret) 1450 return ret; 1451 } 1452 1453 if (gpu->clk_core) { 1454 ret = clk_prepare_enable(gpu->clk_core); 1455 if (ret) 1456 goto disable_clk_bus; 1457 } 1458 1459 if (gpu->clk_shader) { 1460 ret = clk_prepare_enable(gpu->clk_shader); 1461 if (ret) 1462 goto disable_clk_core; 1463 } 1464 1465 return 0; 1466 1467 disable_clk_core: 1468 if (gpu->clk_core) 1469 clk_disable_unprepare(gpu->clk_core); 1470 disable_clk_bus: 1471 if (gpu->clk_bus) 1472 clk_disable_unprepare(gpu->clk_bus); 1473 1474 return ret; 1475 } 1476 1477 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1478 { 1479 if (gpu->clk_shader) 1480 clk_disable_unprepare(gpu->clk_shader); 1481 if (gpu->clk_core) 1482 clk_disable_unprepare(gpu->clk_core); 1483 if (gpu->clk_bus) 1484 clk_disable_unprepare(gpu->clk_bus); 1485 1486 return 0; 1487 } 1488 1489 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1490 { 1491 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1492 1493 do { 1494 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1495 1496 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1497 return 0; 1498 1499 if (time_is_before_jiffies(timeout)) { 1500 dev_warn(gpu->dev, 1501 "timed out waiting for idle: idle=0x%x\n", 1502 idle); 1503 return -ETIMEDOUT; 1504 } 1505 1506 udelay(5); 1507 } while (1); 1508 } 1509 1510 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1511 { 1512 if (gpu->buffer) { 1513 /* Replace the last WAIT with END */ 1514 etnaviv_buffer_end(gpu); 1515 1516 /* 1517 * We know that only the FE is busy here, this should 1518 * happen quickly (as the WAIT is only 200 cycles). If 1519 * we fail, just warn and continue. 1520 */ 1521 etnaviv_gpu_wait_idle(gpu, 100); 1522 } 1523 1524 return etnaviv_gpu_clk_disable(gpu); 1525 } 1526 1527 #ifdef CONFIG_PM 1528 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1529 { 1530 u32 clock; 1531 int ret; 1532 1533 ret = mutex_lock_killable(&gpu->lock); 1534 if (ret) 1535 return ret; 1536 1537 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 1538 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 1539 1540 etnaviv_gpu_load_clock(gpu, clock); 1541 etnaviv_gpu_hw_init(gpu); 1542 1543 gpu->switch_context = true; 1544 gpu->exec_state = -1; 1545 1546 mutex_unlock(&gpu->lock); 1547 1548 return 0; 1549 } 1550 #endif 1551 1552 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1553 void *data) 1554 { 1555 struct drm_device *drm = data; 1556 struct etnaviv_drm_private *priv = drm->dev_private; 1557 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1558 int ret; 1559 1560 #ifdef CONFIG_PM 1561 ret = pm_runtime_get_sync(gpu->dev); 1562 #else 1563 ret = etnaviv_gpu_clk_enable(gpu); 1564 #endif 1565 if (ret < 0) 1566 return ret; 1567 1568 gpu->drm = drm; 1569 gpu->fence_context = dma_fence_context_alloc(1); 1570 spin_lock_init(&gpu->fence_spinlock); 1571 1572 INIT_LIST_HEAD(&gpu->active_cmd_list); 1573 INIT_WORK(&gpu->retire_work, retire_worker); 1574 INIT_WORK(&gpu->recover_work, recover_worker); 1575 init_waitqueue_head(&gpu->fence_event); 1576 1577 setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, 1578 (unsigned long)gpu); 1579 1580 priv->gpu[priv->num_gpus++] = gpu; 1581 1582 pm_runtime_mark_last_busy(gpu->dev); 1583 pm_runtime_put_autosuspend(gpu->dev); 1584 1585 return 0; 1586 } 1587 1588 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1589 void *data) 1590 { 1591 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1592 1593 DBG("%s", dev_name(gpu->dev)); 1594 1595 hangcheck_disable(gpu); 1596 1597 #ifdef CONFIG_PM 1598 pm_runtime_get_sync(gpu->dev); 1599 pm_runtime_put_sync_suspend(gpu->dev); 1600 #else 1601 etnaviv_gpu_hw_suspend(gpu); 1602 #endif 1603 1604 if (gpu->buffer) { 1605 etnaviv_cmdbuf_free(gpu->buffer); 1606 gpu->buffer = NULL; 1607 } 1608 1609 if (gpu->cmdbuf_suballoc) { 1610 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); 1611 gpu->cmdbuf_suballoc = NULL; 1612 } 1613 1614 if (gpu->mmu) { 1615 etnaviv_iommu_destroy(gpu->mmu); 1616 gpu->mmu = NULL; 1617 } 1618 1619 gpu->drm = NULL; 1620 } 1621 1622 static const struct component_ops gpu_ops = { 1623 .bind = etnaviv_gpu_bind, 1624 .unbind = etnaviv_gpu_unbind, 1625 }; 1626 1627 static const struct of_device_id etnaviv_gpu_match[] = { 1628 { 1629 .compatible = "vivante,gc" 1630 }, 1631 { /* sentinel */ } 1632 }; 1633 1634 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1635 { 1636 struct device *dev = &pdev->dev; 1637 struct etnaviv_gpu *gpu; 1638 int err; 1639 1640 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1641 if (!gpu) 1642 return -ENOMEM; 1643 1644 gpu->dev = &pdev->dev; 1645 mutex_init(&gpu->lock); 1646 1647 /* Map registers: */ 1648 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); 1649 if (IS_ERR(gpu->mmio)) 1650 return PTR_ERR(gpu->mmio); 1651 1652 /* Get Interrupt: */ 1653 gpu->irq = platform_get_irq(pdev, 0); 1654 if (gpu->irq < 0) { 1655 dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1656 return gpu->irq; 1657 } 1658 1659 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1660 dev_name(gpu->dev), gpu); 1661 if (err) { 1662 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1663 return err; 1664 } 1665 1666 /* Get Clocks: */ 1667 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1668 DBG("clk_bus: %p", gpu->clk_bus); 1669 if (IS_ERR(gpu->clk_bus)) 1670 gpu->clk_bus = NULL; 1671 1672 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1673 DBG("clk_core: %p", gpu->clk_core); 1674 if (IS_ERR(gpu->clk_core)) 1675 gpu->clk_core = NULL; 1676 1677 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1678 DBG("clk_shader: %p", gpu->clk_shader); 1679 if (IS_ERR(gpu->clk_shader)) 1680 gpu->clk_shader = NULL; 1681 1682 /* TODO: figure out max mapped size */ 1683 dev_set_drvdata(dev, gpu); 1684 1685 /* 1686 * We treat the device as initially suspended. The runtime PM 1687 * autosuspend delay is rather arbitary: no measurements have 1688 * yet been performed to determine an appropriate value. 1689 */ 1690 pm_runtime_use_autosuspend(gpu->dev); 1691 pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1692 pm_runtime_enable(gpu->dev); 1693 1694 err = component_add(&pdev->dev, &gpu_ops); 1695 if (err < 0) { 1696 dev_err(&pdev->dev, "failed to register component: %d\n", err); 1697 return err; 1698 } 1699 1700 return 0; 1701 } 1702 1703 static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1704 { 1705 component_del(&pdev->dev, &gpu_ops); 1706 pm_runtime_disable(&pdev->dev); 1707 return 0; 1708 } 1709 1710 #ifdef CONFIG_PM 1711 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1712 { 1713 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1714 u32 idle, mask; 1715 1716 /* If we have outstanding fences, we're not idle */ 1717 if (gpu->completed_fence != gpu->active_fence) 1718 return -EBUSY; 1719 1720 /* Check whether the hardware (except FE) is idle */ 1721 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1722 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1723 if (idle != mask) 1724 return -EBUSY; 1725 1726 return etnaviv_gpu_hw_suspend(gpu); 1727 } 1728 1729 static int etnaviv_gpu_rpm_resume(struct device *dev) 1730 { 1731 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1732 int ret; 1733 1734 ret = etnaviv_gpu_clk_enable(gpu); 1735 if (ret) 1736 return ret; 1737 1738 /* Re-initialise the basic hardware state */ 1739 if (gpu->drm && gpu->buffer) { 1740 ret = etnaviv_gpu_hw_resume(gpu); 1741 if (ret) { 1742 etnaviv_gpu_clk_disable(gpu); 1743 return ret; 1744 } 1745 } 1746 1747 return 0; 1748 } 1749 #endif 1750 1751 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1752 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1753 NULL) 1754 }; 1755 1756 struct platform_driver etnaviv_gpu_driver = { 1757 .driver = { 1758 .name = "etnaviv-gpu", 1759 .owner = THIS_MODULE, 1760 .pm = &etnaviv_gpu_pm_ops, 1761 .of_match_table = etnaviv_gpu_match, 1762 }, 1763 .probe = etnaviv_gpu_platform_probe, 1764 .remove = etnaviv_gpu_platform_remove, 1765 .id_table = gpu_ids, 1766 }; 1767