1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2015-2018 Etnaviv Project
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17 
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29 
30 static const struct platform_device_id gpu_ids[] = {
31 	{ .name = "etnaviv-gpu,2d" },
32 	{ },
33 };
34 
35 /*
36  * Driver functions:
37  */
38 
39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40 {
41 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42 
43 	switch (param) {
44 	case ETNAVIV_PARAM_GPU_MODEL:
45 		*value = gpu->identity.model;
46 		break;
47 
48 	case ETNAVIV_PARAM_GPU_REVISION:
49 		*value = gpu->identity.revision;
50 		break;
51 
52 	case ETNAVIV_PARAM_GPU_FEATURES_0:
53 		*value = gpu->identity.features;
54 		break;
55 
56 	case ETNAVIV_PARAM_GPU_FEATURES_1:
57 		*value = gpu->identity.minor_features0;
58 		break;
59 
60 	case ETNAVIV_PARAM_GPU_FEATURES_2:
61 		*value = gpu->identity.minor_features1;
62 		break;
63 
64 	case ETNAVIV_PARAM_GPU_FEATURES_3:
65 		*value = gpu->identity.minor_features2;
66 		break;
67 
68 	case ETNAVIV_PARAM_GPU_FEATURES_4:
69 		*value = gpu->identity.minor_features3;
70 		break;
71 
72 	case ETNAVIV_PARAM_GPU_FEATURES_5:
73 		*value = gpu->identity.minor_features4;
74 		break;
75 
76 	case ETNAVIV_PARAM_GPU_FEATURES_6:
77 		*value = gpu->identity.minor_features5;
78 		break;
79 
80 	case ETNAVIV_PARAM_GPU_FEATURES_7:
81 		*value = gpu->identity.minor_features6;
82 		break;
83 
84 	case ETNAVIV_PARAM_GPU_FEATURES_8:
85 		*value = gpu->identity.minor_features7;
86 		break;
87 
88 	case ETNAVIV_PARAM_GPU_FEATURES_9:
89 		*value = gpu->identity.minor_features8;
90 		break;
91 
92 	case ETNAVIV_PARAM_GPU_FEATURES_10:
93 		*value = gpu->identity.minor_features9;
94 		break;
95 
96 	case ETNAVIV_PARAM_GPU_FEATURES_11:
97 		*value = gpu->identity.minor_features10;
98 		break;
99 
100 	case ETNAVIV_PARAM_GPU_FEATURES_12:
101 		*value = gpu->identity.minor_features11;
102 		break;
103 
104 	case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 		*value = gpu->identity.stream_count;
106 		break;
107 
108 	case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 		*value = gpu->identity.register_max;
110 		break;
111 
112 	case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 		*value = gpu->identity.thread_count;
114 		break;
115 
116 	case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 		*value = gpu->identity.vertex_cache_size;
118 		break;
119 
120 	case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 		*value = gpu->identity.shader_core_count;
122 		break;
123 
124 	case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 		*value = gpu->identity.pixel_pipes;
126 		break;
127 
128 	case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 		*value = gpu->identity.vertex_output_buffer_size;
130 		break;
131 
132 	case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 		*value = gpu->identity.buffer_size;
134 		break;
135 
136 	case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 		*value = gpu->identity.instruction_count;
138 		break;
139 
140 	case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 		*value = gpu->identity.num_constants;
142 		break;
143 
144 	case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 		*value = gpu->identity.varyings_count;
146 		break;
147 
148 	case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 		if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 			*value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 		else
152 			*value = ~0ULL;
153 		break;
154 
155 	case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 		*value = gpu->identity.product_id;
157 		break;
158 
159 	case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 		*value = gpu->identity.customer_id;
161 		break;
162 
163 	case ETNAVIV_PARAM_GPU_ECO_ID:
164 		*value = gpu->identity.eco_id;
165 		break;
166 
167 	default:
168 		DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 		return -EINVAL;
170 	}
171 
172 	return 0;
173 }
174 
175 
176 #define etnaviv_is_model_rev(gpu, mod, rev) \
177 	((gpu)->identity.model == chipModel_##mod && \
178 	 (gpu)->identity.revision == rev)
179 #define etnaviv_field(val, field) \
180 	(((val) & field##__MASK) >> field##__SHIFT)
181 
182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
183 {
184 	if (gpu->identity.minor_features0 &
185 	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
186 		u32 specs[4];
187 		unsigned int streams;
188 
189 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
190 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
191 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
192 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
193 
194 		gpu->identity.stream_count = etnaviv_field(specs[0],
195 					VIVS_HI_CHIP_SPECS_STREAM_COUNT);
196 		gpu->identity.register_max = etnaviv_field(specs[0],
197 					VIVS_HI_CHIP_SPECS_REGISTER_MAX);
198 		gpu->identity.thread_count = etnaviv_field(specs[0],
199 					VIVS_HI_CHIP_SPECS_THREAD_COUNT);
200 		gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
201 					VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
202 		gpu->identity.shader_core_count = etnaviv_field(specs[0],
203 					VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
204 		gpu->identity.pixel_pipes = etnaviv_field(specs[0],
205 					VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
206 		gpu->identity.vertex_output_buffer_size =
207 			etnaviv_field(specs[0],
208 				VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
209 
210 		gpu->identity.buffer_size = etnaviv_field(specs[1],
211 					VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
212 		gpu->identity.instruction_count = etnaviv_field(specs[1],
213 					VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
214 		gpu->identity.num_constants = etnaviv_field(specs[1],
215 					VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
216 
217 		gpu->identity.varyings_count = etnaviv_field(specs[2],
218 					VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
219 
220 		/* This overrides the value from older register if non-zero */
221 		streams = etnaviv_field(specs[3],
222 					VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
223 		if (streams)
224 			gpu->identity.stream_count = streams;
225 	}
226 
227 	/* Fill in the stream count if not specified */
228 	if (gpu->identity.stream_count == 0) {
229 		if (gpu->identity.model >= 0x1000)
230 			gpu->identity.stream_count = 4;
231 		else
232 			gpu->identity.stream_count = 1;
233 	}
234 
235 	/* Convert the register max value */
236 	if (gpu->identity.register_max)
237 		gpu->identity.register_max = 1 << gpu->identity.register_max;
238 	else if (gpu->identity.model == chipModel_GC400)
239 		gpu->identity.register_max = 32;
240 	else
241 		gpu->identity.register_max = 64;
242 
243 	/* Convert thread count */
244 	if (gpu->identity.thread_count)
245 		gpu->identity.thread_count = 1 << gpu->identity.thread_count;
246 	else if (gpu->identity.model == chipModel_GC400)
247 		gpu->identity.thread_count = 64;
248 	else if (gpu->identity.model == chipModel_GC500 ||
249 		 gpu->identity.model == chipModel_GC530)
250 		gpu->identity.thread_count = 128;
251 	else
252 		gpu->identity.thread_count = 256;
253 
254 	if (gpu->identity.vertex_cache_size == 0)
255 		gpu->identity.vertex_cache_size = 8;
256 
257 	if (gpu->identity.shader_core_count == 0) {
258 		if (gpu->identity.model >= 0x1000)
259 			gpu->identity.shader_core_count = 2;
260 		else
261 			gpu->identity.shader_core_count = 1;
262 	}
263 
264 	if (gpu->identity.pixel_pipes == 0)
265 		gpu->identity.pixel_pipes = 1;
266 
267 	/* Convert virtex buffer size */
268 	if (gpu->identity.vertex_output_buffer_size) {
269 		gpu->identity.vertex_output_buffer_size =
270 			1 << gpu->identity.vertex_output_buffer_size;
271 	} else if (gpu->identity.model == chipModel_GC400) {
272 		if (gpu->identity.revision < 0x4000)
273 			gpu->identity.vertex_output_buffer_size = 512;
274 		else if (gpu->identity.revision < 0x4200)
275 			gpu->identity.vertex_output_buffer_size = 256;
276 		else
277 			gpu->identity.vertex_output_buffer_size = 128;
278 	} else {
279 		gpu->identity.vertex_output_buffer_size = 512;
280 	}
281 
282 	switch (gpu->identity.instruction_count) {
283 	case 0:
284 		if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
285 		    gpu->identity.model == chipModel_GC880)
286 			gpu->identity.instruction_count = 512;
287 		else
288 			gpu->identity.instruction_count = 256;
289 		break;
290 
291 	case 1:
292 		gpu->identity.instruction_count = 1024;
293 		break;
294 
295 	case 2:
296 		gpu->identity.instruction_count = 2048;
297 		break;
298 
299 	default:
300 		gpu->identity.instruction_count = 256;
301 		break;
302 	}
303 
304 	if (gpu->identity.num_constants == 0)
305 		gpu->identity.num_constants = 168;
306 
307 	if (gpu->identity.varyings_count == 0) {
308 		if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
309 			gpu->identity.varyings_count = 12;
310 		else
311 			gpu->identity.varyings_count = 8;
312 	}
313 
314 	/*
315 	 * For some cores, two varyings are consumed for position, so the
316 	 * maximum varying count needs to be reduced by one.
317 	 */
318 	if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319 	    etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320 	    etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321 	    etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322 	    etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323 	    etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324 	    etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325 	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326 	    etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327 	    etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328 	    etnaviv_is_model_rev(gpu, GC880, 0x5106))
329 		gpu->identity.varyings_count -= 1;
330 }
331 
332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
333 {
334 	u32 chipIdentity;
335 
336 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
337 
338 	/* Special case for older graphic cores. */
339 	if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
340 		gpu->identity.model    = chipModel_GC500;
341 		gpu->identity.revision = etnaviv_field(chipIdentity,
342 					 VIVS_HI_CHIP_IDENTITY_REVISION);
343 	} else {
344 		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
345 
346 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
347 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
348 		gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
349 
350 		/*
351 		 * Reading these two registers on GC600 rev 0x19 result in a
352 		 * unhandled fault: external abort on non-linefetch
353 		 */
354 		if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
355 			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356 			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357 		}
358 
359 		/*
360 		 * !!!! HACK ALERT !!!!
361 		 * Because people change device IDs without letting software
362 		 * know about it - here is the hack to make it all look the
363 		 * same.  Only for GC400 family.
364 		 */
365 		if ((gpu->identity.model & 0xff00) == 0x0400 &&
366 		    gpu->identity.model != chipModel_GC420) {
367 			gpu->identity.model = gpu->identity.model & 0x0400;
368 		}
369 
370 		/* Another special case */
371 		if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
372 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373 
374 			if (chipDate == 0x20080814 && chipTime == 0x12051100) {
375 				/*
376 				 * This IP has an ECO; put the correct
377 				 * revision in it.
378 				 */
379 				gpu->identity.revision = 0x1051;
380 			}
381 		}
382 
383 		/*
384 		 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
385 		 * reality it's just a re-branded GC3000. We can identify this
386 		 * core by the upper half of the revision register being all 1.
387 		 * Fix model/rev here, so all other places can refer to this
388 		 * core by its real identity.
389 		 */
390 		if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
391 			gpu->identity.model = chipModel_GC3000;
392 			gpu->identity.revision &= 0xffff;
393 		}
394 
395 		if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
396 			gpu->identity.eco_id = 1;
397 
398 		if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
399 			gpu->identity.eco_id = 1;
400 	}
401 
402 	dev_info(gpu->dev, "model: GC%x, revision: %x\n",
403 		 gpu->identity.model, gpu->identity.revision);
404 
405 	gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
406 	/*
407 	 * If there is a match in the HWDB, we aren't interested in the
408 	 * remaining register values, as they might be wrong.
409 	 */
410 	if (etnaviv_fill_identity_from_hwdb(gpu))
411 		return;
412 
413 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
414 
415 	/* Disable fast clear on GC700. */
416 	if (gpu->identity.model == chipModel_GC700)
417 		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
418 
419 	/* These models/revisions don't have the 2D pipe bit */
420 	if ((gpu->identity.model == chipModel_GC500 &&
421 	     gpu->identity.revision <= 2) ||
422 	    gpu->identity.model == chipModel_GC300)
423 		gpu->identity.features |= chipFeatures_PIPE_2D;
424 
425 	if ((gpu->identity.model == chipModel_GC500 &&
426 	     gpu->identity.revision < 2) ||
427 	    (gpu->identity.model == chipModel_GC300 &&
428 	     gpu->identity.revision < 0x2000)) {
429 
430 		/*
431 		 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
432 		 * registers.
433 		 */
434 		gpu->identity.minor_features0 = 0;
435 		gpu->identity.minor_features1 = 0;
436 		gpu->identity.minor_features2 = 0;
437 		gpu->identity.minor_features3 = 0;
438 		gpu->identity.minor_features4 = 0;
439 		gpu->identity.minor_features5 = 0;
440 	} else
441 		gpu->identity.minor_features0 =
442 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
443 
444 	if (gpu->identity.minor_features0 &
445 	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
446 		gpu->identity.minor_features1 =
447 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
448 		gpu->identity.minor_features2 =
449 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
450 		gpu->identity.minor_features3 =
451 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
452 		gpu->identity.minor_features4 =
453 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
454 		gpu->identity.minor_features5 =
455 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
456 	}
457 
458 	/* GC600/300 idle register reports zero bits where modules aren't present */
459 	if (gpu->identity.model == chipModel_GC600 ||
460 	    gpu->identity.model == chipModel_GC300)
461 		gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
462 				 VIVS_HI_IDLE_STATE_RA |
463 				 VIVS_HI_IDLE_STATE_SE |
464 				 VIVS_HI_IDLE_STATE_PA |
465 				 VIVS_HI_IDLE_STATE_SH |
466 				 VIVS_HI_IDLE_STATE_PE |
467 				 VIVS_HI_IDLE_STATE_DE |
468 				 VIVS_HI_IDLE_STATE_FE;
469 
470 	etnaviv_hw_specs(gpu);
471 }
472 
473 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
474 {
475 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
476 		  VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
477 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
478 }
479 
480 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
481 {
482 	if (gpu->identity.minor_features2 &
483 	    chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
484 		clk_set_rate(gpu->clk_core,
485 			     gpu->base_rate_core >> gpu->freq_scale);
486 		clk_set_rate(gpu->clk_shader,
487 			     gpu->base_rate_shader >> gpu->freq_scale);
488 	} else {
489 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
490 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
491 
492 		clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
493 		clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
494 		etnaviv_gpu_load_clock(gpu, clock);
495 	}
496 }
497 
498 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
499 {
500 	u32 control, idle;
501 	unsigned long timeout;
502 	bool failed = true;
503 
504 	/* We hope that the GPU resets in under one second */
505 	timeout = jiffies + msecs_to_jiffies(1000);
506 
507 	while (time_is_after_jiffies(timeout)) {
508 		/* enable clock */
509 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
510 		control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
511 		etnaviv_gpu_load_clock(gpu, control);
512 
513 		/* isolate the GPU. */
514 		control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
515 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
516 
517 		if (gpu->sec_mode == ETNA_SEC_KERNEL) {
518 			gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
519 			          VIVS_MMUv2_AHB_CONTROL_RESET);
520 		} else {
521 			/* set soft reset. */
522 			control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
523 			gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
524 		}
525 
526 		/* wait for reset. */
527 		usleep_range(10, 20);
528 
529 		/* reset soft reset bit. */
530 		control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
531 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
532 
533 		/* reset GPU isolation. */
534 		control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
535 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
536 
537 		/* read idle register. */
538 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
539 
540 		/* try resetting again if FE is not idle */
541 		if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
542 			dev_dbg(gpu->dev, "FE is not idle\n");
543 			continue;
544 		}
545 
546 		/* read reset register. */
547 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
548 
549 		/* is the GPU idle? */
550 		if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
551 		    ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
552 			dev_dbg(gpu->dev, "GPU is not idle\n");
553 			continue;
554 		}
555 
556 		/* disable debug registers, as they are not normally needed */
557 		control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
558 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
559 
560 		failed = false;
561 		break;
562 	}
563 
564 	if (failed) {
565 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
566 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
567 
568 		dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
569 			idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
570 			control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
571 			control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
572 
573 		return -EBUSY;
574 	}
575 
576 	/* We rely on the GPU running, so program the clock */
577 	etnaviv_gpu_update_clock(gpu);
578 
579 	gpu->fe_running = false;
580 	gpu->exec_state = -1;
581 	if (gpu->mmu_context)
582 		etnaviv_iommu_context_put(gpu->mmu_context);
583 	gpu->mmu_context = NULL;
584 
585 	return 0;
586 }
587 
588 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
589 {
590 	u32 pmc, ppc;
591 
592 	/* enable clock gating */
593 	ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
594 	ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
595 
596 	/* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
597 	if (gpu->identity.revision == 0x4301 ||
598 	    gpu->identity.revision == 0x4302)
599 		ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
600 
601 	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
602 
603 	pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
604 
605 	/* Disable PA clock gating for GC400+ without bugfix except for GC420 */
606 	if (gpu->identity.model >= chipModel_GC400 &&
607 	    gpu->identity.model != chipModel_GC420 &&
608 	    !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
609 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
610 
611 	/*
612 	 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
613 	 * present without a bug fix.
614 	 */
615 	if (gpu->identity.revision < 0x5000 &&
616 	    gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
617 	    !(gpu->identity.minor_features1 &
618 	      chipMinorFeatures1_DISABLE_PE_GATING))
619 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
620 
621 	if (gpu->identity.revision < 0x5422)
622 		pmc |= BIT(15); /* Unknown bit */
623 
624 	/* Disable TX clock gating on affected core revisions. */
625 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
626 	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
627 	    etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
628 	    etnaviv_is_model_rev(gpu, GC2000, 0x6203))
629 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
630 
631 	/* Disable SE and RA clock gating on affected core revisions. */
632 	if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
633 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
634 		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
635 
636 	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
637 	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
638 
639 	gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
640 }
641 
642 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
643 {
644 	gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
645 	gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
646 		  VIVS_FE_COMMAND_CONTROL_ENABLE |
647 		  VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
648 
649 	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
650 		gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
651 			  VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
652 			  VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
653 	}
654 
655 	gpu->fe_running = true;
656 }
657 
658 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
659 					  struct etnaviv_iommu_context *context)
660 {
661 	u16 prefetch;
662 	u32 address;
663 
664 	/* setup the MMU */
665 	etnaviv_iommu_restore(gpu, context);
666 
667 	/* Start command processor */
668 	prefetch = etnaviv_buffer_init(gpu);
669 	address = etnaviv_cmdbuf_get_va(&gpu->buffer,
670 					&gpu->mmu_context->cmdbuf_mapping);
671 
672 	etnaviv_gpu_start_fe(gpu, address, prefetch);
673 }
674 
675 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
676 {
677 	/*
678 	 * Base value for VIVS_PM_PULSE_EATER register on models where it
679 	 * cannot be read, extracted from vivante kernel driver.
680 	 */
681 	u32 pulse_eater = 0x01590880;
682 
683 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
684 	    etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
685 		pulse_eater |= BIT(23);
686 
687 	}
688 
689 	if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
690 	    etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
691 		pulse_eater &= ~BIT(16);
692 		pulse_eater |= BIT(17);
693 	}
694 
695 	if ((gpu->identity.revision > 0x5420) &&
696 	    (gpu->identity.features & chipFeatures_PIPE_3D))
697 	{
698 		/* Performance fix: disable internal DFS */
699 		pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
700 		pulse_eater |= BIT(18);
701 	}
702 
703 	gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
704 }
705 
706 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
707 {
708 	if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
709 	     etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
710 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
711 		u32 mc_memory_debug;
712 
713 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
714 
715 		if (gpu->identity.revision == 0x5007)
716 			mc_memory_debug |= 0x0c;
717 		else
718 			mc_memory_debug |= 0x08;
719 
720 		gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
721 	}
722 
723 	/* enable module-level clock gating */
724 	etnaviv_gpu_enable_mlcg(gpu);
725 
726 	/*
727 	 * Update GPU AXI cache atttribute to "cacheable, no allocate".
728 	 * This is necessary to prevent the iMX6 SoC locking up.
729 	 */
730 	gpu_write(gpu, VIVS_HI_AXI_CONFIG,
731 		  VIVS_HI_AXI_CONFIG_AWCACHE(2) |
732 		  VIVS_HI_AXI_CONFIG_ARCACHE(2));
733 
734 	/* GC2000 rev 5108 needs a special bus config */
735 	if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
736 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
737 		bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
738 				VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
739 		bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
740 			      VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
741 		gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
742 	}
743 
744 	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
745 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
746 		val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
747 		gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
748 	}
749 
750 	/* setup the pulse eater */
751 	etnaviv_gpu_setup_pulse_eater(gpu);
752 
753 	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
754 }
755 
756 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
757 {
758 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
759 	dma_addr_t cmdbuf_paddr;
760 	int ret, i;
761 
762 	ret = pm_runtime_get_sync(gpu->dev);
763 	if (ret < 0) {
764 		dev_err(gpu->dev, "Failed to enable GPU power domain\n");
765 		goto pm_put;
766 	}
767 
768 	etnaviv_hw_identify(gpu);
769 
770 	if (gpu->identity.model == 0) {
771 		dev_err(gpu->dev, "Unknown GPU model\n");
772 		ret = -ENXIO;
773 		goto fail;
774 	}
775 
776 	/* Exclude VG cores with FE2.0 */
777 	if (gpu->identity.features & chipFeatures_PIPE_VG &&
778 	    gpu->identity.features & chipFeatures_FE20) {
779 		dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
780 		ret = -ENXIO;
781 		goto fail;
782 	}
783 
784 	/*
785 	 * On cores with security features supported, we claim control over the
786 	 * security states.
787 	 */
788 	if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
789 	    (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
790 		gpu->sec_mode = ETNA_SEC_KERNEL;
791 
792 	ret = etnaviv_hw_reset(gpu);
793 	if (ret) {
794 		dev_err(gpu->dev, "GPU reset failed\n");
795 		goto fail;
796 	}
797 
798 	ret = etnaviv_iommu_global_init(gpu);
799 	if (ret)
800 		goto fail;
801 
802 	/*
803 	 * If the GPU is part of a system with DMA addressing limitations,
804 	 * request pages for our SHM backend buffers from the DMA32 zone to
805 	 * hopefully avoid performance killing SWIOTLB bounce buffering.
806 	 */
807 	if (dma_addressing_limited(gpu->dev))
808 		priv->shm_gfp_mask |= GFP_DMA32;
809 
810 	/* Create buffer: */
811 	ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
812 				  PAGE_SIZE);
813 	if (ret) {
814 		dev_err(gpu->dev, "could not create command buffer\n");
815 		goto fail;
816 	}
817 
818 	/*
819 	 * Set the GPU linear window to cover the cmdbuf region, as the GPU
820 	 * won't be able to start execution otherwise. The alignment to 128M is
821 	 * chosen arbitrarily but helps in debugging, as the MMU offset
822 	 * calculations are much more straight forward this way.
823 	 *
824 	 * On MC1.0 cores the linear window offset is ignored by the TS engine,
825 	 * leading to inconsistent memory views. Avoid using the offset on those
826 	 * cores if possible, otherwise disable the TS feature.
827 	 */
828 	cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
829 
830 	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
831 	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
832 		if (cmdbuf_paddr >= SZ_2G)
833 			priv->mmu_global->memory_base = SZ_2G;
834 		else
835 			priv->mmu_global->memory_base = cmdbuf_paddr;
836 	} else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
837 		dev_info(gpu->dev,
838 			 "Need to move linear window on MC1.0, disabling TS\n");
839 		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
840 		priv->mmu_global->memory_base = SZ_2G;
841 	}
842 
843 	/* Setup event management */
844 	spin_lock_init(&gpu->event_spinlock);
845 	init_completion(&gpu->event_free);
846 	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
847 	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
848 		complete(&gpu->event_free);
849 
850 	/* Now program the hardware */
851 	mutex_lock(&gpu->lock);
852 	etnaviv_gpu_hw_init(gpu);
853 	mutex_unlock(&gpu->lock);
854 
855 	pm_runtime_mark_last_busy(gpu->dev);
856 	pm_runtime_put_autosuspend(gpu->dev);
857 
858 	gpu->initialized = true;
859 
860 	return 0;
861 
862 fail:
863 	pm_runtime_mark_last_busy(gpu->dev);
864 pm_put:
865 	pm_runtime_put_autosuspend(gpu->dev);
866 
867 	return ret;
868 }
869 
870 #ifdef CONFIG_DEBUG_FS
871 struct dma_debug {
872 	u32 address[2];
873 	u32 state[2];
874 };
875 
876 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
877 {
878 	u32 i;
879 
880 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
881 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
882 
883 	for (i = 0; i < 500; i++) {
884 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
885 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
886 
887 		if (debug->address[0] != debug->address[1])
888 			break;
889 
890 		if (debug->state[0] != debug->state[1])
891 			break;
892 	}
893 }
894 
895 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
896 {
897 	struct dma_debug debug;
898 	u32 dma_lo, dma_hi, axi, idle;
899 	int ret;
900 
901 	seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
902 
903 	ret = pm_runtime_get_sync(gpu->dev);
904 	if (ret < 0)
905 		goto pm_put;
906 
907 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
908 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
909 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
910 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
911 
912 	verify_dma(gpu, &debug);
913 
914 	seq_puts(m, "\tidentity\n");
915 	seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
916 	seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
917 	seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
918 	seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
919 	seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
920 
921 	seq_puts(m, "\tfeatures\n");
922 	seq_printf(m, "\t major_features: 0x%08x\n",
923 		   gpu->identity.features);
924 	seq_printf(m, "\t minor_features0: 0x%08x\n",
925 		   gpu->identity.minor_features0);
926 	seq_printf(m, "\t minor_features1: 0x%08x\n",
927 		   gpu->identity.minor_features1);
928 	seq_printf(m, "\t minor_features2: 0x%08x\n",
929 		   gpu->identity.minor_features2);
930 	seq_printf(m, "\t minor_features3: 0x%08x\n",
931 		   gpu->identity.minor_features3);
932 	seq_printf(m, "\t minor_features4: 0x%08x\n",
933 		   gpu->identity.minor_features4);
934 	seq_printf(m, "\t minor_features5: 0x%08x\n",
935 		   gpu->identity.minor_features5);
936 	seq_printf(m, "\t minor_features6: 0x%08x\n",
937 		   gpu->identity.minor_features6);
938 	seq_printf(m, "\t minor_features7: 0x%08x\n",
939 		   gpu->identity.minor_features7);
940 	seq_printf(m, "\t minor_features8: 0x%08x\n",
941 		   gpu->identity.minor_features8);
942 	seq_printf(m, "\t minor_features9: 0x%08x\n",
943 		   gpu->identity.minor_features9);
944 	seq_printf(m, "\t minor_features10: 0x%08x\n",
945 		   gpu->identity.minor_features10);
946 	seq_printf(m, "\t minor_features11: 0x%08x\n",
947 		   gpu->identity.minor_features11);
948 
949 	seq_puts(m, "\tspecs\n");
950 	seq_printf(m, "\t stream_count:  %d\n",
951 			gpu->identity.stream_count);
952 	seq_printf(m, "\t register_max: %d\n",
953 			gpu->identity.register_max);
954 	seq_printf(m, "\t thread_count: %d\n",
955 			gpu->identity.thread_count);
956 	seq_printf(m, "\t vertex_cache_size: %d\n",
957 			gpu->identity.vertex_cache_size);
958 	seq_printf(m, "\t shader_core_count: %d\n",
959 			gpu->identity.shader_core_count);
960 	seq_printf(m, "\t pixel_pipes: %d\n",
961 			gpu->identity.pixel_pipes);
962 	seq_printf(m, "\t vertex_output_buffer_size: %d\n",
963 			gpu->identity.vertex_output_buffer_size);
964 	seq_printf(m, "\t buffer_size: %d\n",
965 			gpu->identity.buffer_size);
966 	seq_printf(m, "\t instruction_count: %d\n",
967 			gpu->identity.instruction_count);
968 	seq_printf(m, "\t num_constants: %d\n",
969 			gpu->identity.num_constants);
970 	seq_printf(m, "\t varyings_count: %d\n",
971 			gpu->identity.varyings_count);
972 
973 	seq_printf(m, "\taxi: 0x%08x\n", axi);
974 	seq_printf(m, "\tidle: 0x%08x\n", idle);
975 	idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
976 	if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
977 		seq_puts(m, "\t FE is not idle\n");
978 	if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
979 		seq_puts(m, "\t DE is not idle\n");
980 	if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
981 		seq_puts(m, "\t PE is not idle\n");
982 	if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
983 		seq_puts(m, "\t SH is not idle\n");
984 	if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
985 		seq_puts(m, "\t PA is not idle\n");
986 	if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
987 		seq_puts(m, "\t SE is not idle\n");
988 	if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
989 		seq_puts(m, "\t RA is not idle\n");
990 	if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
991 		seq_puts(m, "\t TX is not idle\n");
992 	if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
993 		seq_puts(m, "\t VG is not idle\n");
994 	if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
995 		seq_puts(m, "\t IM is not idle\n");
996 	if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
997 		seq_puts(m, "\t FP is not idle\n");
998 	if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
999 		seq_puts(m, "\t TS is not idle\n");
1000 	if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1001 		seq_puts(m, "\t BL is not idle\n");
1002 	if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1003 		seq_puts(m, "\t ASYNCFE is not idle\n");
1004 	if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1005 		seq_puts(m, "\t MC is not idle\n");
1006 	if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1007 		seq_puts(m, "\t PPA is not idle\n");
1008 	if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1009 		seq_puts(m, "\t WD is not idle\n");
1010 	if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1011 		seq_puts(m, "\t NN is not idle\n");
1012 	if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1013 		seq_puts(m, "\t TP is not idle\n");
1014 	if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1015 		seq_puts(m, "\t AXI low power mode\n");
1016 
1017 	if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1018 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1019 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1020 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1021 
1022 		seq_puts(m, "\tMC\n");
1023 		seq_printf(m, "\t read0: 0x%08x\n", read0);
1024 		seq_printf(m, "\t read1: 0x%08x\n", read1);
1025 		seq_printf(m, "\t write: 0x%08x\n", write);
1026 	}
1027 
1028 	seq_puts(m, "\tDMA ");
1029 
1030 	if (debug.address[0] == debug.address[1] &&
1031 	    debug.state[0] == debug.state[1]) {
1032 		seq_puts(m, "seems to be stuck\n");
1033 	} else if (debug.address[0] == debug.address[1]) {
1034 		seq_puts(m, "address is constant\n");
1035 	} else {
1036 		seq_puts(m, "is running\n");
1037 	}
1038 
1039 	seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1040 	seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1041 	seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1042 	seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1043 	seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1044 		   dma_lo, dma_hi);
1045 
1046 	ret = 0;
1047 
1048 	pm_runtime_mark_last_busy(gpu->dev);
1049 pm_put:
1050 	pm_runtime_put_autosuspend(gpu->dev);
1051 
1052 	return ret;
1053 }
1054 #endif
1055 
1056 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1057 {
1058 	struct etnaviv_gpu *gpu = submit->gpu;
1059 	char *comm = NULL, *cmd = NULL;
1060 	struct task_struct *task;
1061 	unsigned int i;
1062 
1063 	dev_err(gpu->dev, "recover hung GPU!\n");
1064 
1065 	task = get_pid_task(submit->pid, PIDTYPE_PID);
1066 	if (task) {
1067 		comm = kstrdup(task->comm, GFP_KERNEL);
1068 		cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1069 		put_task_struct(task);
1070 	}
1071 
1072 	if (comm && cmd)
1073 		dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1074 
1075 	kfree(cmd);
1076 	kfree(comm);
1077 
1078 	if (pm_runtime_get_sync(gpu->dev) < 0)
1079 		goto pm_put;
1080 
1081 	mutex_lock(&gpu->lock);
1082 
1083 	etnaviv_hw_reset(gpu);
1084 
1085 	/* complete all events, the GPU won't do it after the reset */
1086 	spin_lock(&gpu->event_spinlock);
1087 	for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1088 		complete(&gpu->event_free);
1089 	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1090 	spin_unlock(&gpu->event_spinlock);
1091 
1092 	etnaviv_gpu_hw_init(gpu);
1093 
1094 	mutex_unlock(&gpu->lock);
1095 	pm_runtime_mark_last_busy(gpu->dev);
1096 pm_put:
1097 	pm_runtime_put_autosuspend(gpu->dev);
1098 }
1099 
1100 /* fence object management */
1101 struct etnaviv_fence {
1102 	struct etnaviv_gpu *gpu;
1103 	struct dma_fence base;
1104 };
1105 
1106 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1107 {
1108 	return container_of(fence, struct etnaviv_fence, base);
1109 }
1110 
1111 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1112 {
1113 	return "etnaviv";
1114 }
1115 
1116 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1117 {
1118 	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1119 
1120 	return dev_name(f->gpu->dev);
1121 }
1122 
1123 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1124 {
1125 	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1126 
1127 	return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1128 }
1129 
1130 static void etnaviv_fence_release(struct dma_fence *fence)
1131 {
1132 	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1133 
1134 	kfree_rcu(f, base.rcu);
1135 }
1136 
1137 static const struct dma_fence_ops etnaviv_fence_ops = {
1138 	.get_driver_name = etnaviv_fence_get_driver_name,
1139 	.get_timeline_name = etnaviv_fence_get_timeline_name,
1140 	.signaled = etnaviv_fence_signaled,
1141 	.release = etnaviv_fence_release,
1142 };
1143 
1144 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1145 {
1146 	struct etnaviv_fence *f;
1147 
1148 	/*
1149 	 * GPU lock must already be held, otherwise fence completion order might
1150 	 * not match the seqno order assigned here.
1151 	 */
1152 	lockdep_assert_held(&gpu->lock);
1153 
1154 	f = kzalloc(sizeof(*f), GFP_KERNEL);
1155 	if (!f)
1156 		return NULL;
1157 
1158 	f->gpu = gpu;
1159 
1160 	dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1161 		       gpu->fence_context, ++gpu->next_fence);
1162 
1163 	return &f->base;
1164 }
1165 
1166 /* returns true if fence a comes after fence b */
1167 static inline bool fence_after(u32 a, u32 b)
1168 {
1169 	return (s32)(a - b) > 0;
1170 }
1171 
1172 /*
1173  * event management:
1174  */
1175 
1176 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1177 	unsigned int *events)
1178 {
1179 	unsigned long timeout = msecs_to_jiffies(10 * 10000);
1180 	unsigned i, acquired = 0;
1181 
1182 	for (i = 0; i < nr_events; i++) {
1183 		unsigned long ret;
1184 
1185 		ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1186 
1187 		if (!ret) {
1188 			dev_err(gpu->dev, "wait_for_completion_timeout failed");
1189 			goto out;
1190 		}
1191 
1192 		acquired++;
1193 		timeout = ret;
1194 	}
1195 
1196 	spin_lock(&gpu->event_spinlock);
1197 
1198 	for (i = 0; i < nr_events; i++) {
1199 		int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1200 
1201 		events[i] = event;
1202 		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1203 		set_bit(event, gpu->event_bitmap);
1204 	}
1205 
1206 	spin_unlock(&gpu->event_spinlock);
1207 
1208 	return 0;
1209 
1210 out:
1211 	for (i = 0; i < acquired; i++)
1212 		complete(&gpu->event_free);
1213 
1214 	return -EBUSY;
1215 }
1216 
1217 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1218 {
1219 	if (!test_bit(event, gpu->event_bitmap)) {
1220 		dev_warn(gpu->dev, "event %u is already marked as free",
1221 			 event);
1222 	} else {
1223 		clear_bit(event, gpu->event_bitmap);
1224 		complete(&gpu->event_free);
1225 	}
1226 }
1227 
1228 /*
1229  * Cmdstream submission/retirement:
1230  */
1231 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1232 	u32 id, struct drm_etnaviv_timespec *timeout)
1233 {
1234 	struct dma_fence *fence;
1235 	int ret;
1236 
1237 	/*
1238 	 * Look up the fence and take a reference. We might still find a fence
1239 	 * whose refcount has already dropped to zero. dma_fence_get_rcu
1240 	 * pretends we didn't find a fence in that case.
1241 	 */
1242 	rcu_read_lock();
1243 	fence = idr_find(&gpu->fence_idr, id);
1244 	if (fence)
1245 		fence = dma_fence_get_rcu(fence);
1246 	rcu_read_unlock();
1247 
1248 	if (!fence)
1249 		return 0;
1250 
1251 	if (!timeout) {
1252 		/* No timeout was requested: just test for completion */
1253 		ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1254 	} else {
1255 		unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1256 
1257 		ret = dma_fence_wait_timeout(fence, true, remaining);
1258 		if (ret == 0)
1259 			ret = -ETIMEDOUT;
1260 		else if (ret != -ERESTARTSYS)
1261 			ret = 0;
1262 
1263 	}
1264 
1265 	dma_fence_put(fence);
1266 	return ret;
1267 }
1268 
1269 /*
1270  * Wait for an object to become inactive.  This, on it's own, is not race
1271  * free: the object is moved by the scheduler off the active list, and
1272  * then the iova is put.  Moreover, the object could be re-submitted just
1273  * after we notice that it's become inactive.
1274  *
1275  * Although the retirement happens under the gpu lock, we don't want to hold
1276  * that lock in this function while waiting.
1277  */
1278 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1279 	struct etnaviv_gem_object *etnaviv_obj,
1280 	struct drm_etnaviv_timespec *timeout)
1281 {
1282 	unsigned long remaining;
1283 	long ret;
1284 
1285 	if (!timeout)
1286 		return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1287 
1288 	remaining = etnaviv_timeout_to_jiffies(timeout);
1289 
1290 	ret = wait_event_interruptible_timeout(gpu->fence_event,
1291 					       !is_active(etnaviv_obj),
1292 					       remaining);
1293 	if (ret > 0)
1294 		return 0;
1295 	else if (ret == -ERESTARTSYS)
1296 		return -ERESTARTSYS;
1297 	else
1298 		return -ETIMEDOUT;
1299 }
1300 
1301 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1302 	struct etnaviv_event *event, unsigned int flags)
1303 {
1304 	const struct etnaviv_gem_submit *submit = event->submit;
1305 	unsigned int i;
1306 
1307 	for (i = 0; i < submit->nr_pmrs; i++) {
1308 		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1309 
1310 		if (pmr->flags == flags)
1311 			etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1312 	}
1313 }
1314 
1315 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1316 	struct etnaviv_event *event)
1317 {
1318 	u32 val;
1319 
1320 	/* disable clock gating */
1321 	val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1322 	val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1323 	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1324 
1325 	/* enable debug register */
1326 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1327 	val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1328 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1329 
1330 	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1331 }
1332 
1333 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1334 	struct etnaviv_event *event)
1335 {
1336 	const struct etnaviv_gem_submit *submit = event->submit;
1337 	unsigned int i;
1338 	u32 val;
1339 
1340 	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1341 
1342 	for (i = 0; i < submit->nr_pmrs; i++) {
1343 		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1344 
1345 		*pmr->bo_vma = pmr->sequence;
1346 	}
1347 
1348 	/* disable debug register */
1349 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1350 	val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1351 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1352 
1353 	/* enable clock gating */
1354 	val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1355 	val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1356 	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1357 }
1358 
1359 
1360 /* add bo's to gpu's ring, and kick gpu: */
1361 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1362 {
1363 	struct etnaviv_gpu *gpu = submit->gpu;
1364 	struct dma_fence *gpu_fence;
1365 	unsigned int i, nr_events = 1, event[3];
1366 	int ret;
1367 
1368 	if (!submit->runtime_resumed) {
1369 		ret = pm_runtime_get_sync(gpu->dev);
1370 		if (ret < 0) {
1371 			pm_runtime_put_noidle(gpu->dev);
1372 			return NULL;
1373 		}
1374 		submit->runtime_resumed = true;
1375 	}
1376 
1377 	/*
1378 	 * if there are performance monitor requests we need to have
1379 	 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1380 	 *   requests.
1381 	 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1382 	 *   and update the sequence number for userspace.
1383 	 */
1384 	if (submit->nr_pmrs)
1385 		nr_events = 3;
1386 
1387 	ret = event_alloc(gpu, nr_events, event);
1388 	if (ret) {
1389 		DRM_ERROR("no free events\n");
1390 		pm_runtime_put_noidle(gpu->dev);
1391 		return NULL;
1392 	}
1393 
1394 	mutex_lock(&gpu->lock);
1395 
1396 	gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1397 	if (!gpu_fence) {
1398 		for (i = 0; i < nr_events; i++)
1399 			event_free(gpu, event[i]);
1400 
1401 		goto out_unlock;
1402 	}
1403 
1404 	if (!gpu->fe_running)
1405 		etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1406 
1407 	if (submit->prev_mmu_context)
1408 		etnaviv_iommu_context_put(submit->prev_mmu_context);
1409 	submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1410 
1411 	if (submit->nr_pmrs) {
1412 		gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1413 		kref_get(&submit->refcount);
1414 		gpu->event[event[1]].submit = submit;
1415 		etnaviv_sync_point_queue(gpu, event[1]);
1416 	}
1417 
1418 	gpu->event[event[0]].fence = gpu_fence;
1419 	submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1420 	etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1421 			     event[0], &submit->cmdbuf);
1422 
1423 	if (submit->nr_pmrs) {
1424 		gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1425 		kref_get(&submit->refcount);
1426 		gpu->event[event[2]].submit = submit;
1427 		etnaviv_sync_point_queue(gpu, event[2]);
1428 	}
1429 
1430 out_unlock:
1431 	mutex_unlock(&gpu->lock);
1432 
1433 	return gpu_fence;
1434 }
1435 
1436 static void sync_point_worker(struct work_struct *work)
1437 {
1438 	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1439 					       sync_point_work);
1440 	struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1441 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1442 
1443 	event->sync_point(gpu, event);
1444 	etnaviv_submit_put(event->submit);
1445 	event_free(gpu, gpu->sync_point_event);
1446 
1447 	/* restart FE last to avoid GPU and IRQ racing against this worker */
1448 	etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1449 }
1450 
1451 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1452 {
1453 	u32 status_reg, status;
1454 	int i;
1455 
1456 	if (gpu->sec_mode == ETNA_SEC_NONE)
1457 		status_reg = VIVS_MMUv2_STATUS;
1458 	else
1459 		status_reg = VIVS_MMUv2_SEC_STATUS;
1460 
1461 	status = gpu_read(gpu, status_reg);
1462 	dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1463 
1464 	for (i = 0; i < 4; i++) {
1465 		u32 address_reg;
1466 
1467 		if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1468 			continue;
1469 
1470 		if (gpu->sec_mode == ETNA_SEC_NONE)
1471 			address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1472 		else
1473 			address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1474 
1475 		dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1476 				    gpu_read(gpu, address_reg));
1477 	}
1478 }
1479 
1480 static irqreturn_t irq_handler(int irq, void *data)
1481 {
1482 	struct etnaviv_gpu *gpu = data;
1483 	irqreturn_t ret = IRQ_NONE;
1484 
1485 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1486 
1487 	if (intr != 0) {
1488 		int event;
1489 
1490 		pm_runtime_mark_last_busy(gpu->dev);
1491 
1492 		dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1493 
1494 		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1495 			dev_err(gpu->dev, "AXI bus error\n");
1496 			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1497 		}
1498 
1499 		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1500 			dump_mmu_fault(gpu);
1501 			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1502 		}
1503 
1504 		while ((event = ffs(intr)) != 0) {
1505 			struct dma_fence *fence;
1506 
1507 			event -= 1;
1508 
1509 			intr &= ~(1 << event);
1510 
1511 			dev_dbg(gpu->dev, "event %u\n", event);
1512 
1513 			if (gpu->event[event].sync_point) {
1514 				gpu->sync_point_event = event;
1515 				queue_work(gpu->wq, &gpu->sync_point_work);
1516 			}
1517 
1518 			fence = gpu->event[event].fence;
1519 			if (!fence)
1520 				continue;
1521 
1522 			gpu->event[event].fence = NULL;
1523 
1524 			/*
1525 			 * Events can be processed out of order.  Eg,
1526 			 * - allocate and queue event 0
1527 			 * - allocate event 1
1528 			 * - event 0 completes, we process it
1529 			 * - allocate and queue event 0
1530 			 * - event 1 and event 0 complete
1531 			 * we can end up processing event 0 first, then 1.
1532 			 */
1533 			if (fence_after(fence->seqno, gpu->completed_fence))
1534 				gpu->completed_fence = fence->seqno;
1535 			dma_fence_signal(fence);
1536 
1537 			event_free(gpu, event);
1538 		}
1539 
1540 		ret = IRQ_HANDLED;
1541 	}
1542 
1543 	return ret;
1544 }
1545 
1546 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1547 {
1548 	int ret;
1549 
1550 	ret = clk_prepare_enable(gpu->clk_reg);
1551 	if (ret)
1552 		return ret;
1553 
1554 	ret = clk_prepare_enable(gpu->clk_bus);
1555 	if (ret)
1556 		goto disable_clk_reg;
1557 
1558 	ret = clk_prepare_enable(gpu->clk_core);
1559 	if (ret)
1560 		goto disable_clk_bus;
1561 
1562 	ret = clk_prepare_enable(gpu->clk_shader);
1563 	if (ret)
1564 		goto disable_clk_core;
1565 
1566 	return 0;
1567 
1568 disable_clk_core:
1569 	clk_disable_unprepare(gpu->clk_core);
1570 disable_clk_bus:
1571 	clk_disable_unprepare(gpu->clk_bus);
1572 disable_clk_reg:
1573 	clk_disable_unprepare(gpu->clk_reg);
1574 
1575 	return ret;
1576 }
1577 
1578 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1579 {
1580 	clk_disable_unprepare(gpu->clk_shader);
1581 	clk_disable_unprepare(gpu->clk_core);
1582 	clk_disable_unprepare(gpu->clk_bus);
1583 	clk_disable_unprepare(gpu->clk_reg);
1584 
1585 	return 0;
1586 }
1587 
1588 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1589 {
1590 	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1591 
1592 	do {
1593 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1594 
1595 		if ((idle & gpu->idle_mask) == gpu->idle_mask)
1596 			return 0;
1597 
1598 		if (time_is_before_jiffies(timeout)) {
1599 			dev_warn(gpu->dev,
1600 				 "timed out waiting for idle: idle=0x%x\n",
1601 				 idle);
1602 			return -ETIMEDOUT;
1603 		}
1604 
1605 		udelay(5);
1606 	} while (1);
1607 }
1608 
1609 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1610 {
1611 	if (gpu->initialized && gpu->fe_running) {
1612 		/* Replace the last WAIT with END */
1613 		mutex_lock(&gpu->lock);
1614 		etnaviv_buffer_end(gpu);
1615 		mutex_unlock(&gpu->lock);
1616 
1617 		/*
1618 		 * We know that only the FE is busy here, this should
1619 		 * happen quickly (as the WAIT is only 200 cycles).  If
1620 		 * we fail, just warn and continue.
1621 		 */
1622 		etnaviv_gpu_wait_idle(gpu, 100);
1623 
1624 		gpu->fe_running = false;
1625 	}
1626 
1627 	gpu->exec_state = -1;
1628 
1629 	return etnaviv_gpu_clk_disable(gpu);
1630 }
1631 
1632 #ifdef CONFIG_PM
1633 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1634 {
1635 	int ret;
1636 
1637 	ret = mutex_lock_killable(&gpu->lock);
1638 	if (ret)
1639 		return ret;
1640 
1641 	etnaviv_gpu_update_clock(gpu);
1642 	etnaviv_gpu_hw_init(gpu);
1643 
1644 	mutex_unlock(&gpu->lock);
1645 
1646 	return 0;
1647 }
1648 #endif
1649 
1650 static int
1651 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1652 				  unsigned long *state)
1653 {
1654 	*state = 6;
1655 
1656 	return 0;
1657 }
1658 
1659 static int
1660 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1661 				  unsigned long *state)
1662 {
1663 	struct etnaviv_gpu *gpu = cdev->devdata;
1664 
1665 	*state = gpu->freq_scale;
1666 
1667 	return 0;
1668 }
1669 
1670 static int
1671 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1672 				  unsigned long state)
1673 {
1674 	struct etnaviv_gpu *gpu = cdev->devdata;
1675 
1676 	mutex_lock(&gpu->lock);
1677 	gpu->freq_scale = state;
1678 	if (!pm_runtime_suspended(gpu->dev))
1679 		etnaviv_gpu_update_clock(gpu);
1680 	mutex_unlock(&gpu->lock);
1681 
1682 	return 0;
1683 }
1684 
1685 static const struct thermal_cooling_device_ops cooling_ops = {
1686 	.get_max_state = etnaviv_gpu_cooling_get_max_state,
1687 	.get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1688 	.set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1689 };
1690 
1691 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1692 	void *data)
1693 {
1694 	struct drm_device *drm = data;
1695 	struct etnaviv_drm_private *priv = drm->dev_private;
1696 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1697 	int ret;
1698 
1699 	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1700 		gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1701 				(char *)dev_name(dev), gpu, &cooling_ops);
1702 		if (IS_ERR(gpu->cooling))
1703 			return PTR_ERR(gpu->cooling);
1704 	}
1705 
1706 	gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1707 	if (!gpu->wq) {
1708 		ret = -ENOMEM;
1709 		goto out_thermal;
1710 	}
1711 
1712 	ret = etnaviv_sched_init(gpu);
1713 	if (ret)
1714 		goto out_workqueue;
1715 
1716 #ifdef CONFIG_PM
1717 	ret = pm_runtime_get_sync(gpu->dev);
1718 #else
1719 	ret = etnaviv_gpu_clk_enable(gpu);
1720 #endif
1721 	if (ret < 0)
1722 		goto out_sched;
1723 
1724 
1725 	gpu->drm = drm;
1726 	gpu->fence_context = dma_fence_context_alloc(1);
1727 	idr_init(&gpu->fence_idr);
1728 	spin_lock_init(&gpu->fence_spinlock);
1729 
1730 	INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1731 	init_waitqueue_head(&gpu->fence_event);
1732 
1733 	priv->gpu[priv->num_gpus++] = gpu;
1734 
1735 	pm_runtime_mark_last_busy(gpu->dev);
1736 	pm_runtime_put_autosuspend(gpu->dev);
1737 
1738 	return 0;
1739 
1740 out_sched:
1741 	etnaviv_sched_fini(gpu);
1742 
1743 out_workqueue:
1744 	destroy_workqueue(gpu->wq);
1745 
1746 out_thermal:
1747 	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1748 		thermal_cooling_device_unregister(gpu->cooling);
1749 
1750 	return ret;
1751 }
1752 
1753 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1754 	void *data)
1755 {
1756 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1757 
1758 	DBG("%s", dev_name(gpu->dev));
1759 
1760 	destroy_workqueue(gpu->wq);
1761 
1762 	etnaviv_sched_fini(gpu);
1763 
1764 #ifdef CONFIG_PM
1765 	pm_runtime_get_sync(gpu->dev);
1766 	pm_runtime_put_sync_suspend(gpu->dev);
1767 #else
1768 	etnaviv_gpu_hw_suspend(gpu);
1769 #endif
1770 
1771 	if (gpu->mmu_context)
1772 		etnaviv_iommu_context_put(gpu->mmu_context);
1773 
1774 	if (gpu->initialized) {
1775 		etnaviv_cmdbuf_free(&gpu->buffer);
1776 		etnaviv_iommu_global_fini(gpu);
1777 		gpu->initialized = false;
1778 	}
1779 
1780 	gpu->drm = NULL;
1781 	idr_destroy(&gpu->fence_idr);
1782 
1783 	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1784 		thermal_cooling_device_unregister(gpu->cooling);
1785 	gpu->cooling = NULL;
1786 }
1787 
1788 static const struct component_ops gpu_ops = {
1789 	.bind = etnaviv_gpu_bind,
1790 	.unbind = etnaviv_gpu_unbind,
1791 };
1792 
1793 static const struct of_device_id etnaviv_gpu_match[] = {
1794 	{
1795 		.compatible = "vivante,gc"
1796 	},
1797 	{ /* sentinel */ }
1798 };
1799 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1800 
1801 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1802 {
1803 	struct device *dev = &pdev->dev;
1804 	struct etnaviv_gpu *gpu;
1805 	int err;
1806 
1807 	gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1808 	if (!gpu)
1809 		return -ENOMEM;
1810 
1811 	gpu->dev = &pdev->dev;
1812 	mutex_init(&gpu->lock);
1813 	mutex_init(&gpu->fence_lock);
1814 
1815 	/* Map registers: */
1816 	gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1817 	if (IS_ERR(gpu->mmio))
1818 		return PTR_ERR(gpu->mmio);
1819 
1820 	/* Get Interrupt: */
1821 	gpu->irq = platform_get_irq(pdev, 0);
1822 	if (gpu->irq < 0)
1823 		return gpu->irq;
1824 
1825 	err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1826 			       dev_name(gpu->dev), gpu);
1827 	if (err) {
1828 		dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1829 		return err;
1830 	}
1831 
1832 	/* Get Clocks: */
1833 	gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1834 	DBG("clk_reg: %p", gpu->clk_reg);
1835 	if (IS_ERR(gpu->clk_reg))
1836 		return PTR_ERR(gpu->clk_reg);
1837 
1838 	gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1839 	DBG("clk_bus: %p", gpu->clk_bus);
1840 	if (IS_ERR(gpu->clk_bus))
1841 		return PTR_ERR(gpu->clk_bus);
1842 
1843 	gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1844 	DBG("clk_core: %p", gpu->clk_core);
1845 	if (IS_ERR(gpu->clk_core))
1846 		return PTR_ERR(gpu->clk_core);
1847 	gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1848 
1849 	gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1850 	DBG("clk_shader: %p", gpu->clk_shader);
1851 	if (IS_ERR(gpu->clk_shader))
1852 		return PTR_ERR(gpu->clk_shader);
1853 	gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1854 
1855 	/* TODO: figure out max mapped size */
1856 	dev_set_drvdata(dev, gpu);
1857 
1858 	/*
1859 	 * We treat the device as initially suspended.  The runtime PM
1860 	 * autosuspend delay is rather arbitary: no measurements have
1861 	 * yet been performed to determine an appropriate value.
1862 	 */
1863 	pm_runtime_use_autosuspend(gpu->dev);
1864 	pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1865 	pm_runtime_enable(gpu->dev);
1866 
1867 	err = component_add(&pdev->dev, &gpu_ops);
1868 	if (err < 0) {
1869 		dev_err(&pdev->dev, "failed to register component: %d\n", err);
1870 		return err;
1871 	}
1872 
1873 	return 0;
1874 }
1875 
1876 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1877 {
1878 	component_del(&pdev->dev, &gpu_ops);
1879 	pm_runtime_disable(&pdev->dev);
1880 	return 0;
1881 }
1882 
1883 #ifdef CONFIG_PM
1884 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1885 {
1886 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1887 	u32 idle, mask;
1888 
1889 	/* If there are any jobs in the HW queue, we're not idle */
1890 	if (atomic_read(&gpu->sched.hw_rq_count))
1891 		return -EBUSY;
1892 
1893 	/* Check whether the hardware (except FE and MC) is idle */
1894 	mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1895 				  VIVS_HI_IDLE_STATE_MC);
1896 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1897 	if (idle != mask) {
1898 		dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1899 				     idle);
1900 		return -EBUSY;
1901 	}
1902 
1903 	return etnaviv_gpu_hw_suspend(gpu);
1904 }
1905 
1906 static int etnaviv_gpu_rpm_resume(struct device *dev)
1907 {
1908 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1909 	int ret;
1910 
1911 	ret = etnaviv_gpu_clk_enable(gpu);
1912 	if (ret)
1913 		return ret;
1914 
1915 	/* Re-initialise the basic hardware state */
1916 	if (gpu->drm && gpu->initialized) {
1917 		ret = etnaviv_gpu_hw_resume(gpu);
1918 		if (ret) {
1919 			etnaviv_gpu_clk_disable(gpu);
1920 			return ret;
1921 		}
1922 	}
1923 
1924 	return 0;
1925 }
1926 #endif
1927 
1928 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1929 	SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1930 			   NULL)
1931 };
1932 
1933 struct platform_driver etnaviv_gpu_driver = {
1934 	.driver = {
1935 		.name = "etnaviv-gpu",
1936 		.owner = THIS_MODULE,
1937 		.pm = &etnaviv_gpu_pm_ops,
1938 		.of_match_table = etnaviv_gpu_match,
1939 	},
1940 	.probe = etnaviv_gpu_platform_probe,
1941 	.remove = etnaviv_gpu_platform_remove,
1942 	.id_table = gpu_ids,
1943 };
1944