1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/component.h> 18 #include <linux/dma-fence.h> 19 #include <linux/moduleparam.h> 20 #include <linux/of_device.h> 21 #include <linux/thermal.h> 22 23 #include "etnaviv_cmdbuf.h" 24 #include "etnaviv_dump.h" 25 #include "etnaviv_gpu.h" 26 #include "etnaviv_gem.h" 27 #include "etnaviv_mmu.h" 28 #include "etnaviv_perfmon.h" 29 #include "common.xml.h" 30 #include "state.xml.h" 31 #include "state_hi.xml.h" 32 #include "cmdstream.xml.h" 33 34 static const struct platform_device_id gpu_ids[] = { 35 { .name = "etnaviv-gpu,2d" }, 36 { }, 37 }; 38 39 static bool etnaviv_dump_core = true; 40 module_param_named(dump_core, etnaviv_dump_core, bool, 0600); 41 42 /* 43 * Driver functions: 44 */ 45 46 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 47 { 48 switch (param) { 49 case ETNAVIV_PARAM_GPU_MODEL: 50 *value = gpu->identity.model; 51 break; 52 53 case ETNAVIV_PARAM_GPU_REVISION: 54 *value = gpu->identity.revision; 55 break; 56 57 case ETNAVIV_PARAM_GPU_FEATURES_0: 58 *value = gpu->identity.features; 59 break; 60 61 case ETNAVIV_PARAM_GPU_FEATURES_1: 62 *value = gpu->identity.minor_features0; 63 break; 64 65 case ETNAVIV_PARAM_GPU_FEATURES_2: 66 *value = gpu->identity.minor_features1; 67 break; 68 69 case ETNAVIV_PARAM_GPU_FEATURES_3: 70 *value = gpu->identity.minor_features2; 71 break; 72 73 case ETNAVIV_PARAM_GPU_FEATURES_4: 74 *value = gpu->identity.minor_features3; 75 break; 76 77 case ETNAVIV_PARAM_GPU_FEATURES_5: 78 *value = gpu->identity.minor_features4; 79 break; 80 81 case ETNAVIV_PARAM_GPU_FEATURES_6: 82 *value = gpu->identity.minor_features5; 83 break; 84 85 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 86 *value = gpu->identity.stream_count; 87 break; 88 89 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 90 *value = gpu->identity.register_max; 91 break; 92 93 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 94 *value = gpu->identity.thread_count; 95 break; 96 97 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 98 *value = gpu->identity.vertex_cache_size; 99 break; 100 101 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 102 *value = gpu->identity.shader_core_count; 103 break; 104 105 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 106 *value = gpu->identity.pixel_pipes; 107 break; 108 109 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 110 *value = gpu->identity.vertex_output_buffer_size; 111 break; 112 113 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 114 *value = gpu->identity.buffer_size; 115 break; 116 117 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 118 *value = gpu->identity.instruction_count; 119 break; 120 121 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 122 *value = gpu->identity.num_constants; 123 break; 124 125 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 126 *value = gpu->identity.varyings_count; 127 break; 128 129 default: 130 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 131 return -EINVAL; 132 } 133 134 return 0; 135 } 136 137 138 #define etnaviv_is_model_rev(gpu, mod, rev) \ 139 ((gpu)->identity.model == chipModel_##mod && \ 140 (gpu)->identity.revision == rev) 141 #define etnaviv_field(val, field) \ 142 (((val) & field##__MASK) >> field##__SHIFT) 143 144 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 145 { 146 if (gpu->identity.minor_features0 & 147 chipMinorFeatures0_MORE_MINOR_FEATURES) { 148 u32 specs[4]; 149 unsigned int streams; 150 151 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 152 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 153 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 154 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 155 156 gpu->identity.stream_count = etnaviv_field(specs[0], 157 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 158 gpu->identity.register_max = etnaviv_field(specs[0], 159 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 160 gpu->identity.thread_count = etnaviv_field(specs[0], 161 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 162 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 163 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 164 gpu->identity.shader_core_count = etnaviv_field(specs[0], 165 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 166 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 167 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 168 gpu->identity.vertex_output_buffer_size = 169 etnaviv_field(specs[0], 170 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 171 172 gpu->identity.buffer_size = etnaviv_field(specs[1], 173 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 174 gpu->identity.instruction_count = etnaviv_field(specs[1], 175 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 176 gpu->identity.num_constants = etnaviv_field(specs[1], 177 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 178 179 gpu->identity.varyings_count = etnaviv_field(specs[2], 180 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 181 182 /* This overrides the value from older register if non-zero */ 183 streams = etnaviv_field(specs[3], 184 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 185 if (streams) 186 gpu->identity.stream_count = streams; 187 } 188 189 /* Fill in the stream count if not specified */ 190 if (gpu->identity.stream_count == 0) { 191 if (gpu->identity.model >= 0x1000) 192 gpu->identity.stream_count = 4; 193 else 194 gpu->identity.stream_count = 1; 195 } 196 197 /* Convert the register max value */ 198 if (gpu->identity.register_max) 199 gpu->identity.register_max = 1 << gpu->identity.register_max; 200 else if (gpu->identity.model == chipModel_GC400) 201 gpu->identity.register_max = 32; 202 else 203 gpu->identity.register_max = 64; 204 205 /* Convert thread count */ 206 if (gpu->identity.thread_count) 207 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 208 else if (gpu->identity.model == chipModel_GC400) 209 gpu->identity.thread_count = 64; 210 else if (gpu->identity.model == chipModel_GC500 || 211 gpu->identity.model == chipModel_GC530) 212 gpu->identity.thread_count = 128; 213 else 214 gpu->identity.thread_count = 256; 215 216 if (gpu->identity.vertex_cache_size == 0) 217 gpu->identity.vertex_cache_size = 8; 218 219 if (gpu->identity.shader_core_count == 0) { 220 if (gpu->identity.model >= 0x1000) 221 gpu->identity.shader_core_count = 2; 222 else 223 gpu->identity.shader_core_count = 1; 224 } 225 226 if (gpu->identity.pixel_pipes == 0) 227 gpu->identity.pixel_pipes = 1; 228 229 /* Convert virtex buffer size */ 230 if (gpu->identity.vertex_output_buffer_size) { 231 gpu->identity.vertex_output_buffer_size = 232 1 << gpu->identity.vertex_output_buffer_size; 233 } else if (gpu->identity.model == chipModel_GC400) { 234 if (gpu->identity.revision < 0x4000) 235 gpu->identity.vertex_output_buffer_size = 512; 236 else if (gpu->identity.revision < 0x4200) 237 gpu->identity.vertex_output_buffer_size = 256; 238 else 239 gpu->identity.vertex_output_buffer_size = 128; 240 } else { 241 gpu->identity.vertex_output_buffer_size = 512; 242 } 243 244 switch (gpu->identity.instruction_count) { 245 case 0: 246 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 247 gpu->identity.model == chipModel_GC880) 248 gpu->identity.instruction_count = 512; 249 else 250 gpu->identity.instruction_count = 256; 251 break; 252 253 case 1: 254 gpu->identity.instruction_count = 1024; 255 break; 256 257 case 2: 258 gpu->identity.instruction_count = 2048; 259 break; 260 261 default: 262 gpu->identity.instruction_count = 256; 263 break; 264 } 265 266 if (gpu->identity.num_constants == 0) 267 gpu->identity.num_constants = 168; 268 269 if (gpu->identity.varyings_count == 0) { 270 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 271 gpu->identity.varyings_count = 12; 272 else 273 gpu->identity.varyings_count = 8; 274 } 275 276 /* 277 * For some cores, two varyings are consumed for position, so the 278 * maximum varying count needs to be reduced by one. 279 */ 280 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 281 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 282 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 283 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 284 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 285 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 286 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 287 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 288 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 289 etnaviv_is_model_rev(gpu, GC880, 0x5107) || 290 etnaviv_is_model_rev(gpu, GC880, 0x5106)) 291 gpu->identity.varyings_count -= 1; 292 } 293 294 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 295 { 296 u32 chipIdentity; 297 298 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 299 300 /* Special case for older graphic cores. */ 301 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 302 gpu->identity.model = chipModel_GC500; 303 gpu->identity.revision = etnaviv_field(chipIdentity, 304 VIVS_HI_CHIP_IDENTITY_REVISION); 305 } else { 306 307 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 308 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 309 310 /* 311 * !!!! HACK ALERT !!!! 312 * Because people change device IDs without letting software 313 * know about it - here is the hack to make it all look the 314 * same. Only for GC400 family. 315 */ 316 if ((gpu->identity.model & 0xff00) == 0x0400 && 317 gpu->identity.model != chipModel_GC420) { 318 gpu->identity.model = gpu->identity.model & 0x0400; 319 } 320 321 /* Another special case */ 322 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 323 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 324 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 325 326 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 327 /* 328 * This IP has an ECO; put the correct 329 * revision in it. 330 */ 331 gpu->identity.revision = 0x1051; 332 } 333 } 334 335 /* 336 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 337 * reality it's just a re-branded GC3000. We can identify this 338 * core by the upper half of the revision register being all 1. 339 * Fix model/rev here, so all other places can refer to this 340 * core by its real identity. 341 */ 342 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 343 gpu->identity.model = chipModel_GC3000; 344 gpu->identity.revision &= 0xffff; 345 } 346 } 347 348 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 349 gpu->identity.model, gpu->identity.revision); 350 351 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 352 353 /* Disable fast clear on GC700. */ 354 if (gpu->identity.model == chipModel_GC700) 355 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 356 357 if ((gpu->identity.model == chipModel_GC500 && 358 gpu->identity.revision < 2) || 359 (gpu->identity.model == chipModel_GC300 && 360 gpu->identity.revision < 0x2000)) { 361 362 /* 363 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 364 * registers. 365 */ 366 gpu->identity.minor_features0 = 0; 367 gpu->identity.minor_features1 = 0; 368 gpu->identity.minor_features2 = 0; 369 gpu->identity.minor_features3 = 0; 370 gpu->identity.minor_features4 = 0; 371 gpu->identity.minor_features5 = 0; 372 } else 373 gpu->identity.minor_features0 = 374 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 375 376 if (gpu->identity.minor_features0 & 377 chipMinorFeatures0_MORE_MINOR_FEATURES) { 378 gpu->identity.minor_features1 = 379 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 380 gpu->identity.minor_features2 = 381 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 382 gpu->identity.minor_features3 = 383 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 384 gpu->identity.minor_features4 = 385 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 386 gpu->identity.minor_features5 = 387 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 388 } 389 390 /* GC600 idle register reports zero bits where modules aren't present */ 391 if (gpu->identity.model == chipModel_GC600) { 392 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 393 VIVS_HI_IDLE_STATE_RA | 394 VIVS_HI_IDLE_STATE_SE | 395 VIVS_HI_IDLE_STATE_PA | 396 VIVS_HI_IDLE_STATE_SH | 397 VIVS_HI_IDLE_STATE_PE | 398 VIVS_HI_IDLE_STATE_DE | 399 VIVS_HI_IDLE_STATE_FE; 400 } else { 401 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 402 } 403 404 etnaviv_hw_specs(gpu); 405 } 406 407 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 408 { 409 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 410 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 411 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 412 } 413 414 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 415 { 416 if (gpu->identity.minor_features2 & 417 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 418 clk_set_rate(gpu->clk_core, 419 gpu->base_rate_core >> gpu->freq_scale); 420 clk_set_rate(gpu->clk_shader, 421 gpu->base_rate_shader >> gpu->freq_scale); 422 } else { 423 unsigned int fscale = 1 << (6 - gpu->freq_scale); 424 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 425 426 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 427 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 428 etnaviv_gpu_load_clock(gpu, clock); 429 } 430 } 431 432 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 433 { 434 u32 control, idle; 435 unsigned long timeout; 436 bool failed = true; 437 438 /* TODO 439 * 440 * - clock gating 441 * - puls eater 442 * - what about VG? 443 */ 444 445 /* We hope that the GPU resets in under one second */ 446 timeout = jiffies + msecs_to_jiffies(1000); 447 448 while (time_is_after_jiffies(timeout)) { 449 /* enable clock */ 450 unsigned int fscale = 1 << (6 - gpu->freq_scale); 451 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 452 etnaviv_gpu_load_clock(gpu, control); 453 454 /* Wait for stable clock. Vivante's code waited for 1ms */ 455 usleep_range(1000, 10000); 456 457 /* isolate the GPU. */ 458 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 459 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 460 461 /* set soft reset. */ 462 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 463 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 464 465 /* wait for reset. */ 466 msleep(1); 467 468 /* reset soft reset bit. */ 469 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 470 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 471 472 /* reset GPU isolation. */ 473 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 474 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 475 476 /* read idle register. */ 477 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 478 479 /* try reseting again if FE it not idle */ 480 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 481 dev_dbg(gpu->dev, "FE is not idle\n"); 482 continue; 483 } 484 485 /* read reset register. */ 486 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 487 488 /* is the GPU idle? */ 489 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 490 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 491 dev_dbg(gpu->dev, "GPU is not idle\n"); 492 continue; 493 } 494 495 /* disable debug registers, as they are not normally needed */ 496 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 497 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 498 499 failed = false; 500 break; 501 } 502 503 if (failed) { 504 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 505 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 506 507 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 508 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 509 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 510 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 511 512 return -EBUSY; 513 } 514 515 /* We rely on the GPU running, so program the clock */ 516 etnaviv_gpu_update_clock(gpu); 517 518 return 0; 519 } 520 521 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 522 { 523 u32 pmc, ppc; 524 525 /* enable clock gating */ 526 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 527 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 528 529 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 530 if (gpu->identity.revision == 0x4301 || 531 gpu->identity.revision == 0x4302) 532 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 533 534 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 535 536 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 537 538 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 539 if (gpu->identity.model >= chipModel_GC400 && 540 gpu->identity.model != chipModel_GC420 && 541 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 542 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 543 544 /* 545 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 546 * present without a bug fix. 547 */ 548 if (gpu->identity.revision < 0x5000 && 549 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 550 !(gpu->identity.minor_features1 & 551 chipMinorFeatures1_DISABLE_PE_GATING)) 552 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 553 554 if (gpu->identity.revision < 0x5422) 555 pmc |= BIT(15); /* Unknown bit */ 556 557 /* Disable TX clock gating on affected core revisions. */ 558 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 559 etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 560 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 561 562 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 563 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 564 565 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 566 } 567 568 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 569 { 570 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 571 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 572 VIVS_FE_COMMAND_CONTROL_ENABLE | 573 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 574 } 575 576 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 577 { 578 /* 579 * Base value for VIVS_PM_PULSE_EATER register on models where it 580 * cannot be read, extracted from vivante kernel driver. 581 */ 582 u32 pulse_eater = 0x01590880; 583 584 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 585 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 586 pulse_eater |= BIT(23); 587 588 } 589 590 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 591 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 592 pulse_eater &= ~BIT(16); 593 pulse_eater |= BIT(17); 594 } 595 596 if ((gpu->identity.revision > 0x5420) && 597 (gpu->identity.features & chipFeatures_PIPE_3D)) 598 { 599 /* Performance fix: disable internal DFS */ 600 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 601 pulse_eater |= BIT(18); 602 } 603 604 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 605 } 606 607 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 608 { 609 u16 prefetch; 610 611 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 612 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 613 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 614 u32 mc_memory_debug; 615 616 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 617 618 if (gpu->identity.revision == 0x5007) 619 mc_memory_debug |= 0x0c; 620 else 621 mc_memory_debug |= 0x08; 622 623 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 624 } 625 626 /* enable module-level clock gating */ 627 etnaviv_gpu_enable_mlcg(gpu); 628 629 /* 630 * Update GPU AXI cache atttribute to "cacheable, no allocate". 631 * This is necessary to prevent the iMX6 SoC locking up. 632 */ 633 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 634 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 635 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 636 637 /* GC2000 rev 5108 needs a special bus config */ 638 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 639 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 640 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 641 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 642 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 643 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 644 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 645 } 646 647 /* setup the pulse eater */ 648 etnaviv_gpu_setup_pulse_eater(gpu); 649 650 /* setup the MMU */ 651 etnaviv_iommu_restore(gpu); 652 653 /* Start command processor */ 654 prefetch = etnaviv_buffer_init(gpu); 655 656 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 657 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer), 658 prefetch); 659 } 660 661 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 662 { 663 int ret, i; 664 665 ret = pm_runtime_get_sync(gpu->dev); 666 if (ret < 0) { 667 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 668 return ret; 669 } 670 671 etnaviv_hw_identify(gpu); 672 673 if (gpu->identity.model == 0) { 674 dev_err(gpu->dev, "Unknown GPU model\n"); 675 ret = -ENXIO; 676 goto fail; 677 } 678 679 /* Exclude VG cores with FE2.0 */ 680 if (gpu->identity.features & chipFeatures_PIPE_VG && 681 gpu->identity.features & chipFeatures_FE20) { 682 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 683 ret = -ENXIO; 684 goto fail; 685 } 686 687 /* 688 * Set the GPU linear window to be at the end of the DMA window, where 689 * the CMA area is likely to reside. This ensures that we are able to 690 * map the command buffers while having the linear window overlap as 691 * much RAM as possible, so we can optimize mappings for other buffers. 692 * 693 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 694 * to different views of the memory on the individual engines. 695 */ 696 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 697 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 698 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 699 if (dma_mask < PHYS_OFFSET + SZ_2G) 700 gpu->memory_base = PHYS_OFFSET; 701 else 702 gpu->memory_base = dma_mask - SZ_2G + 1; 703 } else if (PHYS_OFFSET >= SZ_2G) { 704 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 705 gpu->memory_base = PHYS_OFFSET; 706 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 707 } 708 709 ret = etnaviv_hw_reset(gpu); 710 if (ret) { 711 dev_err(gpu->dev, "GPU reset failed\n"); 712 goto fail; 713 } 714 715 gpu->mmu = etnaviv_iommu_new(gpu); 716 if (IS_ERR(gpu->mmu)) { 717 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 718 ret = PTR_ERR(gpu->mmu); 719 goto fail; 720 } 721 722 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu); 723 if (IS_ERR(gpu->cmdbuf_suballoc)) { 724 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); 725 ret = PTR_ERR(gpu->cmdbuf_suballoc); 726 goto fail; 727 } 728 729 /* Create buffer: */ 730 gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0, 0); 731 if (!gpu->buffer) { 732 ret = -ENOMEM; 733 dev_err(gpu->dev, "could not create command buffer\n"); 734 goto destroy_iommu; 735 } 736 737 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 738 etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) { 739 ret = -EINVAL; 740 dev_err(gpu->dev, 741 "command buffer outside valid memory window\n"); 742 goto free_buffer; 743 } 744 745 /* Setup event management */ 746 spin_lock_init(&gpu->event_spinlock); 747 init_completion(&gpu->event_free); 748 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 749 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 750 complete(&gpu->event_free); 751 752 /* Now program the hardware */ 753 mutex_lock(&gpu->lock); 754 etnaviv_gpu_hw_init(gpu); 755 gpu->exec_state = -1; 756 mutex_unlock(&gpu->lock); 757 758 pm_runtime_mark_last_busy(gpu->dev); 759 pm_runtime_put_autosuspend(gpu->dev); 760 761 return 0; 762 763 free_buffer: 764 etnaviv_cmdbuf_free(gpu->buffer); 765 gpu->buffer = NULL; 766 destroy_iommu: 767 etnaviv_iommu_destroy(gpu->mmu); 768 gpu->mmu = NULL; 769 fail: 770 pm_runtime_mark_last_busy(gpu->dev); 771 pm_runtime_put_autosuspend(gpu->dev); 772 773 return ret; 774 } 775 776 #ifdef CONFIG_DEBUG_FS 777 struct dma_debug { 778 u32 address[2]; 779 u32 state[2]; 780 }; 781 782 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 783 { 784 u32 i; 785 786 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 787 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 788 789 for (i = 0; i < 500; i++) { 790 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 791 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 792 793 if (debug->address[0] != debug->address[1]) 794 break; 795 796 if (debug->state[0] != debug->state[1]) 797 break; 798 } 799 } 800 801 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 802 { 803 struct dma_debug debug; 804 u32 dma_lo, dma_hi, axi, idle; 805 int ret; 806 807 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 808 809 ret = pm_runtime_get_sync(gpu->dev); 810 if (ret < 0) 811 return ret; 812 813 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 814 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 815 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 816 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 817 818 verify_dma(gpu, &debug); 819 820 seq_puts(m, "\tfeatures\n"); 821 seq_printf(m, "\t minor_features0: 0x%08x\n", 822 gpu->identity.minor_features0); 823 seq_printf(m, "\t minor_features1: 0x%08x\n", 824 gpu->identity.minor_features1); 825 seq_printf(m, "\t minor_features2: 0x%08x\n", 826 gpu->identity.minor_features2); 827 seq_printf(m, "\t minor_features3: 0x%08x\n", 828 gpu->identity.minor_features3); 829 seq_printf(m, "\t minor_features4: 0x%08x\n", 830 gpu->identity.minor_features4); 831 seq_printf(m, "\t minor_features5: 0x%08x\n", 832 gpu->identity.minor_features5); 833 834 seq_puts(m, "\tspecs\n"); 835 seq_printf(m, "\t stream_count: %d\n", 836 gpu->identity.stream_count); 837 seq_printf(m, "\t register_max: %d\n", 838 gpu->identity.register_max); 839 seq_printf(m, "\t thread_count: %d\n", 840 gpu->identity.thread_count); 841 seq_printf(m, "\t vertex_cache_size: %d\n", 842 gpu->identity.vertex_cache_size); 843 seq_printf(m, "\t shader_core_count: %d\n", 844 gpu->identity.shader_core_count); 845 seq_printf(m, "\t pixel_pipes: %d\n", 846 gpu->identity.pixel_pipes); 847 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 848 gpu->identity.vertex_output_buffer_size); 849 seq_printf(m, "\t buffer_size: %d\n", 850 gpu->identity.buffer_size); 851 seq_printf(m, "\t instruction_count: %d\n", 852 gpu->identity.instruction_count); 853 seq_printf(m, "\t num_constants: %d\n", 854 gpu->identity.num_constants); 855 seq_printf(m, "\t varyings_count: %d\n", 856 gpu->identity.varyings_count); 857 858 seq_printf(m, "\taxi: 0x%08x\n", axi); 859 seq_printf(m, "\tidle: 0x%08x\n", idle); 860 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 861 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 862 seq_puts(m, "\t FE is not idle\n"); 863 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 864 seq_puts(m, "\t DE is not idle\n"); 865 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 866 seq_puts(m, "\t PE is not idle\n"); 867 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 868 seq_puts(m, "\t SH is not idle\n"); 869 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 870 seq_puts(m, "\t PA is not idle\n"); 871 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 872 seq_puts(m, "\t SE is not idle\n"); 873 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 874 seq_puts(m, "\t RA is not idle\n"); 875 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 876 seq_puts(m, "\t TX is not idle\n"); 877 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 878 seq_puts(m, "\t VG is not idle\n"); 879 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 880 seq_puts(m, "\t IM is not idle\n"); 881 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 882 seq_puts(m, "\t FP is not idle\n"); 883 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 884 seq_puts(m, "\t TS is not idle\n"); 885 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 886 seq_puts(m, "\t AXI low power mode\n"); 887 888 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 889 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 890 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 891 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 892 893 seq_puts(m, "\tMC\n"); 894 seq_printf(m, "\t read0: 0x%08x\n", read0); 895 seq_printf(m, "\t read1: 0x%08x\n", read1); 896 seq_printf(m, "\t write: 0x%08x\n", write); 897 } 898 899 seq_puts(m, "\tDMA "); 900 901 if (debug.address[0] == debug.address[1] && 902 debug.state[0] == debug.state[1]) { 903 seq_puts(m, "seems to be stuck\n"); 904 } else if (debug.address[0] == debug.address[1]) { 905 seq_puts(m, "address is constant\n"); 906 } else { 907 seq_puts(m, "is running\n"); 908 } 909 910 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 911 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 912 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 913 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 914 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 915 dma_lo, dma_hi); 916 917 ret = 0; 918 919 pm_runtime_mark_last_busy(gpu->dev); 920 pm_runtime_put_autosuspend(gpu->dev); 921 922 return ret; 923 } 924 #endif 925 926 /* 927 * Hangcheck detection for locked gpu: 928 */ 929 static void recover_worker(struct work_struct *work) 930 { 931 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 932 recover_work); 933 unsigned long flags; 934 unsigned int i = 0; 935 936 dev_err(gpu->dev, "hangcheck recover!\n"); 937 938 if (pm_runtime_get_sync(gpu->dev) < 0) 939 return; 940 941 mutex_lock(&gpu->lock); 942 943 /* Only catch the first event, or when manually re-armed */ 944 if (etnaviv_dump_core) { 945 etnaviv_core_dump(gpu); 946 etnaviv_dump_core = false; 947 } 948 949 etnaviv_hw_reset(gpu); 950 951 /* complete all events, the GPU won't do it after the reset */ 952 spin_lock_irqsave(&gpu->event_spinlock, flags); 953 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) { 954 dma_fence_signal(gpu->event[i].fence); 955 gpu->event[i].fence = NULL; 956 complete(&gpu->event_free); 957 } 958 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 959 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 960 gpu->completed_fence = gpu->active_fence; 961 962 etnaviv_gpu_hw_init(gpu); 963 gpu->lastctx = NULL; 964 gpu->exec_state = -1; 965 966 mutex_unlock(&gpu->lock); 967 pm_runtime_mark_last_busy(gpu->dev); 968 pm_runtime_put_autosuspend(gpu->dev); 969 970 /* Retire the buffer objects in a work */ 971 etnaviv_queue_work(gpu->drm, &gpu->retire_work); 972 } 973 974 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) 975 { 976 DBG("%s", dev_name(gpu->dev)); 977 mod_timer(&gpu->hangcheck_timer, 978 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); 979 } 980 981 static void hangcheck_handler(unsigned long data) 982 { 983 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data; 984 u32 fence = gpu->completed_fence; 985 bool progress = false; 986 987 if (fence != gpu->hangcheck_fence) { 988 gpu->hangcheck_fence = fence; 989 progress = true; 990 } 991 992 if (!progress) { 993 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 994 int change = dma_addr - gpu->hangcheck_dma_addr; 995 996 if (change < 0 || change > 16) { 997 gpu->hangcheck_dma_addr = dma_addr; 998 progress = true; 999 } 1000 } 1001 1002 if (!progress && fence_after(gpu->active_fence, fence)) { 1003 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); 1004 dev_err(gpu->dev, " completed fence: %u\n", fence); 1005 dev_err(gpu->dev, " active fence: %u\n", 1006 gpu->active_fence); 1007 etnaviv_queue_work(gpu->drm, &gpu->recover_work); 1008 } 1009 1010 /* if still more pending work, reset the hangcheck timer: */ 1011 if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) 1012 hangcheck_timer_reset(gpu); 1013 } 1014 1015 static void hangcheck_disable(struct etnaviv_gpu *gpu) 1016 { 1017 del_timer_sync(&gpu->hangcheck_timer); 1018 cancel_work_sync(&gpu->recover_work); 1019 } 1020 1021 /* fence object management */ 1022 struct etnaviv_fence { 1023 struct etnaviv_gpu *gpu; 1024 struct dma_fence base; 1025 }; 1026 1027 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1028 { 1029 return container_of(fence, struct etnaviv_fence, base); 1030 } 1031 1032 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1033 { 1034 return "etnaviv"; 1035 } 1036 1037 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1038 { 1039 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1040 1041 return dev_name(f->gpu->dev); 1042 } 1043 1044 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence) 1045 { 1046 return true; 1047 } 1048 1049 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1050 { 1051 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1052 1053 return fence_completed(f->gpu, f->base.seqno); 1054 } 1055 1056 static void etnaviv_fence_release(struct dma_fence *fence) 1057 { 1058 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1059 1060 kfree_rcu(f, base.rcu); 1061 } 1062 1063 static const struct dma_fence_ops etnaviv_fence_ops = { 1064 .get_driver_name = etnaviv_fence_get_driver_name, 1065 .get_timeline_name = etnaviv_fence_get_timeline_name, 1066 .enable_signaling = etnaviv_fence_enable_signaling, 1067 .signaled = etnaviv_fence_signaled, 1068 .wait = dma_fence_default_wait, 1069 .release = etnaviv_fence_release, 1070 }; 1071 1072 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1073 { 1074 struct etnaviv_fence *f; 1075 1076 /* 1077 * GPU lock must already be held, otherwise fence completion order might 1078 * not match the seqno order assigned here. 1079 */ 1080 lockdep_assert_held(&gpu->lock); 1081 1082 f = kzalloc(sizeof(*f), GFP_KERNEL); 1083 if (!f) 1084 return NULL; 1085 1086 f->gpu = gpu; 1087 1088 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1089 gpu->fence_context, ++gpu->next_fence); 1090 1091 return &f->base; 1092 } 1093 1094 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 1095 unsigned int context, bool exclusive, bool explicit) 1096 { 1097 struct reservation_object *robj = etnaviv_obj->resv; 1098 struct reservation_object_list *fobj; 1099 struct dma_fence *fence; 1100 int i, ret; 1101 1102 if (!exclusive) { 1103 ret = reservation_object_reserve_shared(robj); 1104 if (ret) 1105 return ret; 1106 } 1107 1108 if (explicit) 1109 return 0; 1110 1111 /* 1112 * If we have any shared fences, then the exclusive fence 1113 * should be ignored as it will already have been signalled. 1114 */ 1115 fobj = reservation_object_get_list(robj); 1116 if (!fobj || fobj->shared_count == 0) { 1117 /* Wait on any existing exclusive fence which isn't our own */ 1118 fence = reservation_object_get_excl(robj); 1119 if (fence && fence->context != context) { 1120 ret = dma_fence_wait(fence, true); 1121 if (ret) 1122 return ret; 1123 } 1124 } 1125 1126 if (!exclusive || !fobj) 1127 return 0; 1128 1129 for (i = 0; i < fobj->shared_count; i++) { 1130 fence = rcu_dereference_protected(fobj->shared[i], 1131 reservation_object_held(robj)); 1132 if (fence->context != context) { 1133 ret = dma_fence_wait(fence, true); 1134 if (ret) 1135 return ret; 1136 } 1137 } 1138 1139 return 0; 1140 } 1141 1142 /* 1143 * event management: 1144 */ 1145 1146 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1147 unsigned int *events) 1148 { 1149 unsigned long flags, timeout = msecs_to_jiffies(10 * 10000); 1150 unsigned i, acquired = 0; 1151 1152 for (i = 0; i < nr_events; i++) { 1153 unsigned long ret; 1154 1155 ret = wait_for_completion_timeout(&gpu->event_free, timeout); 1156 1157 if (!ret) { 1158 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1159 goto out; 1160 } 1161 1162 acquired++; 1163 timeout = ret; 1164 } 1165 1166 spin_lock_irqsave(&gpu->event_spinlock, flags); 1167 1168 for (i = 0; i < nr_events; i++) { 1169 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1170 1171 events[i] = event; 1172 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1173 set_bit(event, gpu->event_bitmap); 1174 } 1175 1176 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1177 1178 return 0; 1179 1180 out: 1181 for (i = 0; i < acquired; i++) 1182 complete(&gpu->event_free); 1183 1184 return -EBUSY; 1185 } 1186 1187 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1188 { 1189 unsigned long flags; 1190 1191 spin_lock_irqsave(&gpu->event_spinlock, flags); 1192 1193 if (!test_bit(event, gpu->event_bitmap)) { 1194 dev_warn(gpu->dev, "event %u is already marked as free", 1195 event); 1196 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1197 } else { 1198 clear_bit(event, gpu->event_bitmap); 1199 spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1200 1201 complete(&gpu->event_free); 1202 } 1203 } 1204 1205 /* 1206 * Cmdstream submission/retirement: 1207 */ 1208 1209 static void retire_worker(struct work_struct *work) 1210 { 1211 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1212 retire_work); 1213 u32 fence = gpu->completed_fence; 1214 struct etnaviv_cmdbuf *cmdbuf, *tmp; 1215 unsigned int i; 1216 1217 mutex_lock(&gpu->lock); 1218 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { 1219 if (!dma_fence_is_signaled(cmdbuf->fence)) 1220 break; 1221 1222 list_del(&cmdbuf->node); 1223 dma_fence_put(cmdbuf->fence); 1224 1225 for (i = 0; i < cmdbuf->nr_bos; i++) { 1226 struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; 1227 struct etnaviv_gem_object *etnaviv_obj = mapping->object; 1228 1229 atomic_dec(&etnaviv_obj->gpu_active); 1230 /* drop the refcount taken in etnaviv_gpu_submit */ 1231 etnaviv_gem_mapping_unreference(mapping); 1232 } 1233 1234 etnaviv_cmdbuf_free(cmdbuf); 1235 /* 1236 * We need to balance the runtime PM count caused by 1237 * each submission. Upon submission, we increment 1238 * the runtime PM counter, and allocate one event. 1239 * So here, we put the runtime PM count for each 1240 * completed event. 1241 */ 1242 pm_runtime_put_autosuspend(gpu->dev); 1243 } 1244 1245 gpu->retired_fence = fence; 1246 1247 mutex_unlock(&gpu->lock); 1248 1249 wake_up_all(&gpu->fence_event); 1250 } 1251 1252 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1253 u32 fence, struct timespec *timeout) 1254 { 1255 int ret; 1256 1257 if (fence_after(fence, gpu->next_fence)) { 1258 DRM_ERROR("waiting on invalid fence: %u (of %u)\n", 1259 fence, gpu->next_fence); 1260 return -EINVAL; 1261 } 1262 1263 if (!timeout) { 1264 /* No timeout was requested: just test for completion */ 1265 ret = fence_completed(gpu, fence) ? 0 : -EBUSY; 1266 } else { 1267 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1268 1269 ret = wait_event_interruptible_timeout(gpu->fence_event, 1270 fence_completed(gpu, fence), 1271 remaining); 1272 if (ret == 0) { 1273 DBG("timeout waiting for fence: %u (retired: %u completed: %u)", 1274 fence, gpu->retired_fence, 1275 gpu->completed_fence); 1276 ret = -ETIMEDOUT; 1277 } else if (ret != -ERESTARTSYS) { 1278 ret = 0; 1279 } 1280 } 1281 1282 return ret; 1283 } 1284 1285 /* 1286 * Wait for an object to become inactive. This, on it's own, is not race 1287 * free: the object is moved by the retire worker off the active list, and 1288 * then the iova is put. Moreover, the object could be re-submitted just 1289 * after we notice that it's become inactive. 1290 * 1291 * Although the retirement happens under the gpu lock, we don't want to hold 1292 * that lock in this function while waiting. 1293 */ 1294 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1295 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1296 { 1297 unsigned long remaining; 1298 long ret; 1299 1300 if (!timeout) 1301 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1302 1303 remaining = etnaviv_timeout_to_jiffies(timeout); 1304 1305 ret = wait_event_interruptible_timeout(gpu->fence_event, 1306 !is_active(etnaviv_obj), 1307 remaining); 1308 if (ret > 0) { 1309 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 1310 1311 /* Synchronise with the retire worker */ 1312 flush_workqueue(priv->wq); 1313 return 0; 1314 } else if (ret == -ERESTARTSYS) { 1315 return -ERESTARTSYS; 1316 } else { 1317 return -ETIMEDOUT; 1318 } 1319 } 1320 1321 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) 1322 { 1323 return pm_runtime_get_sync(gpu->dev); 1324 } 1325 1326 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) 1327 { 1328 pm_runtime_mark_last_busy(gpu->dev); 1329 pm_runtime_put_autosuspend(gpu->dev); 1330 } 1331 1332 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1333 struct etnaviv_event *event, unsigned int flags) 1334 { 1335 const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf; 1336 unsigned int i; 1337 1338 for (i = 0; i < cmdbuf->nr_pmrs; i++) { 1339 const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i; 1340 1341 if (pmr->flags == flags) 1342 etnaviv_perfmon_process(gpu, pmr); 1343 } 1344 } 1345 1346 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1347 struct etnaviv_event *event) 1348 { 1349 u32 val; 1350 1351 /* disable clock gating */ 1352 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 1353 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1354 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 1355 1356 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1357 } 1358 1359 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1360 struct etnaviv_event *event) 1361 { 1362 const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf; 1363 unsigned int i; 1364 u32 val; 1365 1366 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1367 1368 for (i = 0; i < cmdbuf->nr_pmrs; i++) { 1369 const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i; 1370 1371 *pmr->bo_vma = pmr->sequence; 1372 } 1373 1374 /* enable clock gating */ 1375 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 1376 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1377 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 1378 } 1379 1380 1381 /* add bo's to gpu's ring, and kick gpu: */ 1382 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 1383 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) 1384 { 1385 struct dma_fence *fence; 1386 unsigned int i, nr_events = 1, event[3]; 1387 int ret; 1388 1389 ret = etnaviv_gpu_pm_get_sync(gpu); 1390 if (ret < 0) 1391 return ret; 1392 1393 /* 1394 * TODO 1395 * 1396 * - flush 1397 * - data endian 1398 * - prefetch 1399 * 1400 */ 1401 1402 /* 1403 * if there are performance monitor requests we need to have 1404 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1405 * requests. 1406 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1407 * and update the sequence number for userspace. 1408 */ 1409 if (cmdbuf->nr_pmrs) 1410 nr_events = 3; 1411 1412 ret = event_alloc(gpu, nr_events, event); 1413 if (ret) { 1414 DRM_ERROR("no free events\n"); 1415 goto out_pm_put; 1416 } 1417 1418 mutex_lock(&gpu->lock); 1419 1420 fence = etnaviv_gpu_fence_alloc(gpu); 1421 if (!fence) { 1422 for (i = 0; i < nr_events; i++) 1423 event_free(gpu, event[i]); 1424 1425 ret = -ENOMEM; 1426 goto out_unlock; 1427 } 1428 1429 gpu->event[event[0]].fence = fence; 1430 submit->fence = dma_fence_get(fence); 1431 gpu->active_fence = submit->fence->seqno; 1432 1433 if (gpu->lastctx != cmdbuf->ctx) { 1434 gpu->mmu->need_flush = true; 1435 gpu->switch_context = true; 1436 gpu->lastctx = cmdbuf->ctx; 1437 } 1438 1439 if (cmdbuf->nr_pmrs) { 1440 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1441 gpu->event[event[1]].cmdbuf = cmdbuf; 1442 etnaviv_sync_point_queue(gpu, event[1]); 1443 } 1444 1445 etnaviv_buffer_queue(gpu, event[0], cmdbuf); 1446 1447 if (cmdbuf->nr_pmrs) { 1448 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1449 gpu->event[event[2]].cmdbuf = cmdbuf; 1450 etnaviv_sync_point_queue(gpu, event[2]); 1451 } 1452 1453 cmdbuf->fence = fence; 1454 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); 1455 1456 /* We're committed to adding this command buffer, hold a PM reference */ 1457 pm_runtime_get_noresume(gpu->dev); 1458 1459 for (i = 0; i < submit->nr_bos; i++) { 1460 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; 1461 1462 /* Each cmdbuf takes a refcount on the mapping */ 1463 etnaviv_gem_mapping_reference(submit->bos[i].mapping); 1464 cmdbuf->bo_map[i] = submit->bos[i].mapping; 1465 atomic_inc(&etnaviv_obj->gpu_active); 1466 1467 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) 1468 reservation_object_add_excl_fence(etnaviv_obj->resv, 1469 fence); 1470 else 1471 reservation_object_add_shared_fence(etnaviv_obj->resv, 1472 fence); 1473 } 1474 cmdbuf->nr_bos = submit->nr_bos; 1475 hangcheck_timer_reset(gpu); 1476 ret = 0; 1477 1478 out_unlock: 1479 mutex_unlock(&gpu->lock); 1480 1481 out_pm_put: 1482 etnaviv_gpu_pm_put(gpu); 1483 1484 return ret; 1485 } 1486 1487 static void etnaviv_process_sync_point(struct etnaviv_gpu *gpu, 1488 struct etnaviv_event *event) 1489 { 1490 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1491 1492 event->sync_point(gpu, event); 1493 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1494 } 1495 1496 static void sync_point_worker(struct work_struct *work) 1497 { 1498 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1499 sync_point_work); 1500 1501 etnaviv_process_sync_point(gpu, &gpu->event[gpu->sync_point_event]); 1502 event_free(gpu, gpu->sync_point_event); 1503 } 1504 1505 /* 1506 * Init/Cleanup: 1507 */ 1508 static irqreturn_t irq_handler(int irq, void *data) 1509 { 1510 struct etnaviv_gpu *gpu = data; 1511 irqreturn_t ret = IRQ_NONE; 1512 1513 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1514 1515 if (intr != 0) { 1516 int event; 1517 1518 pm_runtime_mark_last_busy(gpu->dev); 1519 1520 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1521 1522 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1523 dev_err(gpu->dev, "AXI bus error\n"); 1524 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1525 } 1526 1527 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1528 int i; 1529 1530 dev_err_ratelimited(gpu->dev, 1531 "MMU fault status 0x%08x\n", 1532 gpu_read(gpu, VIVS_MMUv2_STATUS)); 1533 for (i = 0; i < 4; i++) { 1534 dev_err_ratelimited(gpu->dev, 1535 "MMU %d fault addr 0x%08x\n", 1536 i, gpu_read(gpu, 1537 VIVS_MMUv2_EXCEPTION_ADDR(i))); 1538 } 1539 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1540 } 1541 1542 while ((event = ffs(intr)) != 0) { 1543 struct dma_fence *fence; 1544 1545 event -= 1; 1546 1547 intr &= ~(1 << event); 1548 1549 dev_dbg(gpu->dev, "event %u\n", event); 1550 1551 if (gpu->event[event].sync_point) { 1552 gpu->sync_point_event = event; 1553 etnaviv_queue_work(gpu->drm, &gpu->sync_point_work); 1554 } 1555 1556 fence = gpu->event[event].fence; 1557 if (!fence) 1558 continue; 1559 1560 gpu->event[event].fence = NULL; 1561 dma_fence_signal(fence); 1562 1563 /* 1564 * Events can be processed out of order. Eg, 1565 * - allocate and queue event 0 1566 * - allocate event 1 1567 * - event 0 completes, we process it 1568 * - allocate and queue event 0 1569 * - event 1 and event 0 complete 1570 * we can end up processing event 0 first, then 1. 1571 */ 1572 if (fence_after(fence->seqno, gpu->completed_fence)) 1573 gpu->completed_fence = fence->seqno; 1574 1575 event_free(gpu, event); 1576 } 1577 1578 /* Retire the buffer objects in a work */ 1579 etnaviv_queue_work(gpu->drm, &gpu->retire_work); 1580 1581 ret = IRQ_HANDLED; 1582 } 1583 1584 return ret; 1585 } 1586 1587 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1588 { 1589 int ret; 1590 1591 if (gpu->clk_bus) { 1592 ret = clk_prepare_enable(gpu->clk_bus); 1593 if (ret) 1594 return ret; 1595 } 1596 1597 if (gpu->clk_core) { 1598 ret = clk_prepare_enable(gpu->clk_core); 1599 if (ret) 1600 goto disable_clk_bus; 1601 } 1602 1603 if (gpu->clk_shader) { 1604 ret = clk_prepare_enable(gpu->clk_shader); 1605 if (ret) 1606 goto disable_clk_core; 1607 } 1608 1609 return 0; 1610 1611 disable_clk_core: 1612 if (gpu->clk_core) 1613 clk_disable_unprepare(gpu->clk_core); 1614 disable_clk_bus: 1615 if (gpu->clk_bus) 1616 clk_disable_unprepare(gpu->clk_bus); 1617 1618 return ret; 1619 } 1620 1621 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1622 { 1623 if (gpu->clk_shader) 1624 clk_disable_unprepare(gpu->clk_shader); 1625 if (gpu->clk_core) 1626 clk_disable_unprepare(gpu->clk_core); 1627 if (gpu->clk_bus) 1628 clk_disable_unprepare(gpu->clk_bus); 1629 1630 return 0; 1631 } 1632 1633 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1634 { 1635 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1636 1637 do { 1638 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1639 1640 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1641 return 0; 1642 1643 if (time_is_before_jiffies(timeout)) { 1644 dev_warn(gpu->dev, 1645 "timed out waiting for idle: idle=0x%x\n", 1646 idle); 1647 return -ETIMEDOUT; 1648 } 1649 1650 udelay(5); 1651 } while (1); 1652 } 1653 1654 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1655 { 1656 if (gpu->buffer) { 1657 /* Replace the last WAIT with END */ 1658 etnaviv_buffer_end(gpu); 1659 1660 /* 1661 * We know that only the FE is busy here, this should 1662 * happen quickly (as the WAIT is only 200 cycles). If 1663 * we fail, just warn and continue. 1664 */ 1665 etnaviv_gpu_wait_idle(gpu, 100); 1666 } 1667 1668 return etnaviv_gpu_clk_disable(gpu); 1669 } 1670 1671 #ifdef CONFIG_PM 1672 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1673 { 1674 int ret; 1675 1676 ret = mutex_lock_killable(&gpu->lock); 1677 if (ret) 1678 return ret; 1679 1680 etnaviv_gpu_update_clock(gpu); 1681 etnaviv_gpu_hw_init(gpu); 1682 1683 gpu->switch_context = true; 1684 gpu->exec_state = -1; 1685 1686 mutex_unlock(&gpu->lock); 1687 1688 return 0; 1689 } 1690 #endif 1691 1692 static int 1693 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1694 unsigned long *state) 1695 { 1696 *state = 6; 1697 1698 return 0; 1699 } 1700 1701 static int 1702 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1703 unsigned long *state) 1704 { 1705 struct etnaviv_gpu *gpu = cdev->devdata; 1706 1707 *state = gpu->freq_scale; 1708 1709 return 0; 1710 } 1711 1712 static int 1713 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1714 unsigned long state) 1715 { 1716 struct etnaviv_gpu *gpu = cdev->devdata; 1717 1718 mutex_lock(&gpu->lock); 1719 gpu->freq_scale = state; 1720 if (!pm_runtime_suspended(gpu->dev)) 1721 etnaviv_gpu_update_clock(gpu); 1722 mutex_unlock(&gpu->lock); 1723 1724 return 0; 1725 } 1726 1727 static struct thermal_cooling_device_ops cooling_ops = { 1728 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1729 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1730 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1731 }; 1732 1733 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1734 void *data) 1735 { 1736 struct drm_device *drm = data; 1737 struct etnaviv_drm_private *priv = drm->dev_private; 1738 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1739 int ret; 1740 1741 if (IS_ENABLED(CONFIG_THERMAL)) { 1742 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1743 (char *)dev_name(dev), gpu, &cooling_ops); 1744 if (IS_ERR(gpu->cooling)) 1745 return PTR_ERR(gpu->cooling); 1746 } 1747 1748 #ifdef CONFIG_PM 1749 ret = pm_runtime_get_sync(gpu->dev); 1750 #else 1751 ret = etnaviv_gpu_clk_enable(gpu); 1752 #endif 1753 if (ret < 0) { 1754 thermal_cooling_device_unregister(gpu->cooling); 1755 return ret; 1756 } 1757 1758 gpu->drm = drm; 1759 gpu->fence_context = dma_fence_context_alloc(1); 1760 spin_lock_init(&gpu->fence_spinlock); 1761 1762 INIT_LIST_HEAD(&gpu->active_cmd_list); 1763 INIT_WORK(&gpu->retire_work, retire_worker); 1764 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1765 INIT_WORK(&gpu->recover_work, recover_worker); 1766 init_waitqueue_head(&gpu->fence_event); 1767 1768 setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, 1769 (unsigned long)gpu); 1770 1771 priv->gpu[priv->num_gpus++] = gpu; 1772 1773 pm_runtime_mark_last_busy(gpu->dev); 1774 pm_runtime_put_autosuspend(gpu->dev); 1775 1776 return 0; 1777 } 1778 1779 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1780 void *data) 1781 { 1782 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1783 1784 DBG("%s", dev_name(gpu->dev)); 1785 1786 hangcheck_disable(gpu); 1787 1788 #ifdef CONFIG_PM 1789 pm_runtime_get_sync(gpu->dev); 1790 pm_runtime_put_sync_suspend(gpu->dev); 1791 #else 1792 etnaviv_gpu_hw_suspend(gpu); 1793 #endif 1794 1795 if (gpu->buffer) { 1796 etnaviv_cmdbuf_free(gpu->buffer); 1797 gpu->buffer = NULL; 1798 } 1799 1800 if (gpu->cmdbuf_suballoc) { 1801 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); 1802 gpu->cmdbuf_suballoc = NULL; 1803 } 1804 1805 if (gpu->mmu) { 1806 etnaviv_iommu_destroy(gpu->mmu); 1807 gpu->mmu = NULL; 1808 } 1809 1810 gpu->drm = NULL; 1811 1812 thermal_cooling_device_unregister(gpu->cooling); 1813 gpu->cooling = NULL; 1814 } 1815 1816 static const struct component_ops gpu_ops = { 1817 .bind = etnaviv_gpu_bind, 1818 .unbind = etnaviv_gpu_unbind, 1819 }; 1820 1821 static const struct of_device_id etnaviv_gpu_match[] = { 1822 { 1823 .compatible = "vivante,gc" 1824 }, 1825 { /* sentinel */ } 1826 }; 1827 1828 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1829 { 1830 struct device *dev = &pdev->dev; 1831 struct etnaviv_gpu *gpu; 1832 int err; 1833 1834 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1835 if (!gpu) 1836 return -ENOMEM; 1837 1838 gpu->dev = &pdev->dev; 1839 mutex_init(&gpu->lock); 1840 1841 /* Map registers: */ 1842 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); 1843 if (IS_ERR(gpu->mmio)) 1844 return PTR_ERR(gpu->mmio); 1845 1846 /* Get Interrupt: */ 1847 gpu->irq = platform_get_irq(pdev, 0); 1848 if (gpu->irq < 0) { 1849 dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1850 return gpu->irq; 1851 } 1852 1853 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1854 dev_name(gpu->dev), gpu); 1855 if (err) { 1856 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1857 return err; 1858 } 1859 1860 /* Get Clocks: */ 1861 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1862 DBG("clk_bus: %p", gpu->clk_bus); 1863 if (IS_ERR(gpu->clk_bus)) 1864 gpu->clk_bus = NULL; 1865 1866 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1867 DBG("clk_core: %p", gpu->clk_core); 1868 if (IS_ERR(gpu->clk_core)) 1869 gpu->clk_core = NULL; 1870 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1871 1872 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1873 DBG("clk_shader: %p", gpu->clk_shader); 1874 if (IS_ERR(gpu->clk_shader)) 1875 gpu->clk_shader = NULL; 1876 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1877 1878 /* TODO: figure out max mapped size */ 1879 dev_set_drvdata(dev, gpu); 1880 1881 /* 1882 * We treat the device as initially suspended. The runtime PM 1883 * autosuspend delay is rather arbitary: no measurements have 1884 * yet been performed to determine an appropriate value. 1885 */ 1886 pm_runtime_use_autosuspend(gpu->dev); 1887 pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1888 pm_runtime_enable(gpu->dev); 1889 1890 err = component_add(&pdev->dev, &gpu_ops); 1891 if (err < 0) { 1892 dev_err(&pdev->dev, "failed to register component: %d\n", err); 1893 return err; 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1900 { 1901 component_del(&pdev->dev, &gpu_ops); 1902 pm_runtime_disable(&pdev->dev); 1903 return 0; 1904 } 1905 1906 #ifdef CONFIG_PM 1907 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1908 { 1909 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1910 u32 idle, mask; 1911 1912 /* If we have outstanding fences, we're not idle */ 1913 if (gpu->completed_fence != gpu->active_fence) 1914 return -EBUSY; 1915 1916 /* Check whether the hardware (except FE) is idle */ 1917 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1918 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1919 if (idle != mask) 1920 return -EBUSY; 1921 1922 return etnaviv_gpu_hw_suspend(gpu); 1923 } 1924 1925 static int etnaviv_gpu_rpm_resume(struct device *dev) 1926 { 1927 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1928 int ret; 1929 1930 ret = etnaviv_gpu_clk_enable(gpu); 1931 if (ret) 1932 return ret; 1933 1934 /* Re-initialise the basic hardware state */ 1935 if (gpu->drm && gpu->buffer) { 1936 ret = etnaviv_gpu_hw_resume(gpu); 1937 if (ret) { 1938 etnaviv_gpu_clk_disable(gpu); 1939 return ret; 1940 } 1941 } 1942 1943 return 0; 1944 } 1945 #endif 1946 1947 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1948 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1949 NULL) 1950 }; 1951 1952 struct platform_driver etnaviv_gpu_driver = { 1953 .driver = { 1954 .name = "etnaviv-gpu", 1955 .owner = THIS_MODULE, 1956 .pm = &etnaviv_gpu_pm_ops, 1957 .of_match_table = etnaviv_gpu_match, 1958 }, 1959 .probe = etnaviv_gpu_platform_probe, 1960 .remove = etnaviv_gpu_platform_remove, 1961 .id_table = gpu_ids, 1962 }; 1963