1a8c21a54SThe etnaviv authors /* 2a8c21a54SThe etnaviv authors * Copyright (C) 2015 Etnaviv Project 3a8c21a54SThe etnaviv authors * 4a8c21a54SThe etnaviv authors * This program is free software; you can redistribute it and/or modify it 5a8c21a54SThe etnaviv authors * under the terms of the GNU General Public License version 2 as published by 6a8c21a54SThe etnaviv authors * the Free Software Foundation. 7a8c21a54SThe etnaviv authors * 8a8c21a54SThe etnaviv authors * This program is distributed in the hope that it will be useful, but WITHOUT 9a8c21a54SThe etnaviv authors * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10a8c21a54SThe etnaviv authors * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11a8c21a54SThe etnaviv authors * more details. 12a8c21a54SThe etnaviv authors * 13a8c21a54SThe etnaviv authors * You should have received a copy of the GNU General Public License along with 14a8c21a54SThe etnaviv authors * this program. If not, see <http://www.gnu.org/licenses/>. 15a8c21a54SThe etnaviv authors */ 16a8c21a54SThe etnaviv authors 17a8c21a54SThe etnaviv authors #include <linux/component.h> 18f54d1867SChris Wilson #include <linux/dma-fence.h> 19a8c21a54SThe etnaviv authors #include <linux/moduleparam.h> 20a8c21a54SThe etnaviv authors #include <linux/of_device.h> 21bcdfb5e5SRussell King #include <linux/thermal.h> 22ea1f5729SLucas Stach 23ea1f5729SLucas Stach #include "etnaviv_cmdbuf.h" 24a8c21a54SThe etnaviv authors #include "etnaviv_dump.h" 25a8c21a54SThe etnaviv authors #include "etnaviv_gpu.h" 26a8c21a54SThe etnaviv authors #include "etnaviv_gem.h" 27a8c21a54SThe etnaviv authors #include "etnaviv_mmu.h" 28357713ceSChristian Gmeiner #include "etnaviv_perfmon.h" 29a8c21a54SThe etnaviv authors #include "common.xml.h" 30a8c21a54SThe etnaviv authors #include "state.xml.h" 31a8c21a54SThe etnaviv authors #include "state_hi.xml.h" 32a8c21a54SThe etnaviv authors #include "cmdstream.xml.h" 33a8c21a54SThe etnaviv authors 34a8c21a54SThe etnaviv authors static const struct platform_device_id gpu_ids[] = { 35a8c21a54SThe etnaviv authors { .name = "etnaviv-gpu,2d" }, 36a8c21a54SThe etnaviv authors { }, 37a8c21a54SThe etnaviv authors }; 38a8c21a54SThe etnaviv authors 39a8c21a54SThe etnaviv authors static bool etnaviv_dump_core = true; 40a8c21a54SThe etnaviv authors module_param_named(dump_core, etnaviv_dump_core, bool, 0600); 41a8c21a54SThe etnaviv authors 42a8c21a54SThe etnaviv authors /* 43a8c21a54SThe etnaviv authors * Driver functions: 44a8c21a54SThe etnaviv authors */ 45a8c21a54SThe etnaviv authors 46a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 47a8c21a54SThe etnaviv authors { 48a8c21a54SThe etnaviv authors switch (param) { 49a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_MODEL: 50a8c21a54SThe etnaviv authors *value = gpu->identity.model; 51a8c21a54SThe etnaviv authors break; 52a8c21a54SThe etnaviv authors 53a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REVISION: 54a8c21a54SThe etnaviv authors *value = gpu->identity.revision; 55a8c21a54SThe etnaviv authors break; 56a8c21a54SThe etnaviv authors 57a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_0: 58a8c21a54SThe etnaviv authors *value = gpu->identity.features; 59a8c21a54SThe etnaviv authors break; 60a8c21a54SThe etnaviv authors 61a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_1: 62a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features0; 63a8c21a54SThe etnaviv authors break; 64a8c21a54SThe etnaviv authors 65a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_2: 66a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features1; 67a8c21a54SThe etnaviv authors break; 68a8c21a54SThe etnaviv authors 69a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_3: 70a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features2; 71a8c21a54SThe etnaviv authors break; 72a8c21a54SThe etnaviv authors 73a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_4: 74a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features3; 75a8c21a54SThe etnaviv authors break; 76a8c21a54SThe etnaviv authors 77602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_5: 78602eb489SRussell King *value = gpu->identity.minor_features4; 79602eb489SRussell King break; 80602eb489SRussell King 81602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_6: 82602eb489SRussell King *value = gpu->identity.minor_features5; 83602eb489SRussell King break; 84602eb489SRussell King 85a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_STREAM_COUNT: 86a8c21a54SThe etnaviv authors *value = gpu->identity.stream_count; 87a8c21a54SThe etnaviv authors break; 88a8c21a54SThe etnaviv authors 89a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REGISTER_MAX: 90a8c21a54SThe etnaviv authors *value = gpu->identity.register_max; 91a8c21a54SThe etnaviv authors break; 92a8c21a54SThe etnaviv authors 93a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_THREAD_COUNT: 94a8c21a54SThe etnaviv authors *value = gpu->identity.thread_count; 95a8c21a54SThe etnaviv authors break; 96a8c21a54SThe etnaviv authors 97a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 98a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_cache_size; 99a8c21a54SThe etnaviv authors break; 100a8c21a54SThe etnaviv authors 101a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 102a8c21a54SThe etnaviv authors *value = gpu->identity.shader_core_count; 103a8c21a54SThe etnaviv authors break; 104a8c21a54SThe etnaviv authors 105a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 106a8c21a54SThe etnaviv authors *value = gpu->identity.pixel_pipes; 107a8c21a54SThe etnaviv authors break; 108a8c21a54SThe etnaviv authors 109a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 110a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_output_buffer_size; 111a8c21a54SThe etnaviv authors break; 112a8c21a54SThe etnaviv authors 113a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 114a8c21a54SThe etnaviv authors *value = gpu->identity.buffer_size; 115a8c21a54SThe etnaviv authors break; 116a8c21a54SThe etnaviv authors 117a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 118a8c21a54SThe etnaviv authors *value = gpu->identity.instruction_count; 119a8c21a54SThe etnaviv authors break; 120a8c21a54SThe etnaviv authors 121a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 122a8c21a54SThe etnaviv authors *value = gpu->identity.num_constants; 123a8c21a54SThe etnaviv authors break; 124a8c21a54SThe etnaviv authors 125602eb489SRussell King case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 126602eb489SRussell King *value = gpu->identity.varyings_count; 127602eb489SRussell King break; 128602eb489SRussell King 129a8c21a54SThe etnaviv authors default: 130a8c21a54SThe etnaviv authors DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 131a8c21a54SThe etnaviv authors return -EINVAL; 132a8c21a54SThe etnaviv authors } 133a8c21a54SThe etnaviv authors 134a8c21a54SThe etnaviv authors return 0; 135a8c21a54SThe etnaviv authors } 136a8c21a54SThe etnaviv authors 137472f79dcSRussell King 138472f79dcSRussell King #define etnaviv_is_model_rev(gpu, mod, rev) \ 139472f79dcSRussell King ((gpu)->identity.model == chipModel_##mod && \ 140472f79dcSRussell King (gpu)->identity.revision == rev) 14152f36ba1SRussell King #define etnaviv_field(val, field) \ 14252f36ba1SRussell King (((val) & field##__MASK) >> field##__SHIFT) 14352f36ba1SRussell King 144a8c21a54SThe etnaviv authors static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 145a8c21a54SThe etnaviv authors { 146a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 147a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 148602eb489SRussell King u32 specs[4]; 149602eb489SRussell King unsigned int streams; 150a8c21a54SThe etnaviv authors 151a8c21a54SThe etnaviv authors specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 152a8c21a54SThe etnaviv authors specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 153602eb489SRussell King specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 154602eb489SRussell King specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 155a8c21a54SThe etnaviv authors 15652f36ba1SRussell King gpu->identity.stream_count = etnaviv_field(specs[0], 15752f36ba1SRussell King VIVS_HI_CHIP_SPECS_STREAM_COUNT); 15852f36ba1SRussell King gpu->identity.register_max = etnaviv_field(specs[0], 15952f36ba1SRussell King VIVS_HI_CHIP_SPECS_REGISTER_MAX); 16052f36ba1SRussell King gpu->identity.thread_count = etnaviv_field(specs[0], 16152f36ba1SRussell King VIVS_HI_CHIP_SPECS_THREAD_COUNT); 16252f36ba1SRussell King gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 16352f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 16452f36ba1SRussell King gpu->identity.shader_core_count = etnaviv_field(specs[0], 16552f36ba1SRussell King VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 16652f36ba1SRussell King gpu->identity.pixel_pipes = etnaviv_field(specs[0], 16752f36ba1SRussell King VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 168a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 16952f36ba1SRussell King etnaviv_field(specs[0], 17052f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 171a8c21a54SThe etnaviv authors 17252f36ba1SRussell King gpu->identity.buffer_size = etnaviv_field(specs[1], 17352f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 17452f36ba1SRussell King gpu->identity.instruction_count = etnaviv_field(specs[1], 17552f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 17652f36ba1SRussell King gpu->identity.num_constants = etnaviv_field(specs[1], 17752f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 178602eb489SRussell King 179602eb489SRussell King gpu->identity.varyings_count = etnaviv_field(specs[2], 180602eb489SRussell King VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 181602eb489SRussell King 182602eb489SRussell King /* This overrides the value from older register if non-zero */ 183602eb489SRussell King streams = etnaviv_field(specs[3], 184602eb489SRussell King VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 185602eb489SRussell King if (streams) 186602eb489SRussell King gpu->identity.stream_count = streams; 187a8c21a54SThe etnaviv authors } 188a8c21a54SThe etnaviv authors 189a8c21a54SThe etnaviv authors /* Fill in the stream count if not specified */ 190a8c21a54SThe etnaviv authors if (gpu->identity.stream_count == 0) { 191a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 192a8c21a54SThe etnaviv authors gpu->identity.stream_count = 4; 193a8c21a54SThe etnaviv authors else 194a8c21a54SThe etnaviv authors gpu->identity.stream_count = 1; 195a8c21a54SThe etnaviv authors } 196a8c21a54SThe etnaviv authors 197a8c21a54SThe etnaviv authors /* Convert the register max value */ 198a8c21a54SThe etnaviv authors if (gpu->identity.register_max) 199a8c21a54SThe etnaviv authors gpu->identity.register_max = 1 << gpu->identity.register_max; 200507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 201a8c21a54SThe etnaviv authors gpu->identity.register_max = 32; 202a8c21a54SThe etnaviv authors else 203a8c21a54SThe etnaviv authors gpu->identity.register_max = 64; 204a8c21a54SThe etnaviv authors 205a8c21a54SThe etnaviv authors /* Convert thread count */ 206a8c21a54SThe etnaviv authors if (gpu->identity.thread_count) 207a8c21a54SThe etnaviv authors gpu->identity.thread_count = 1 << gpu->identity.thread_count; 208507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 209a8c21a54SThe etnaviv authors gpu->identity.thread_count = 64; 210507f8991SRussell King else if (gpu->identity.model == chipModel_GC500 || 211507f8991SRussell King gpu->identity.model == chipModel_GC530) 212a8c21a54SThe etnaviv authors gpu->identity.thread_count = 128; 213a8c21a54SThe etnaviv authors else 214a8c21a54SThe etnaviv authors gpu->identity.thread_count = 256; 215a8c21a54SThe etnaviv authors 216a8c21a54SThe etnaviv authors if (gpu->identity.vertex_cache_size == 0) 217a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size = 8; 218a8c21a54SThe etnaviv authors 219a8c21a54SThe etnaviv authors if (gpu->identity.shader_core_count == 0) { 220a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 221a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 2; 222a8c21a54SThe etnaviv authors else 223a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 1; 224a8c21a54SThe etnaviv authors } 225a8c21a54SThe etnaviv authors 226a8c21a54SThe etnaviv authors if (gpu->identity.pixel_pipes == 0) 227a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes = 1; 228a8c21a54SThe etnaviv authors 229a8c21a54SThe etnaviv authors /* Convert virtex buffer size */ 230a8c21a54SThe etnaviv authors if (gpu->identity.vertex_output_buffer_size) { 231a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 232a8c21a54SThe etnaviv authors 1 << gpu->identity.vertex_output_buffer_size; 233507f8991SRussell King } else if (gpu->identity.model == chipModel_GC400) { 234a8c21a54SThe etnaviv authors if (gpu->identity.revision < 0x4000) 235a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 236a8c21a54SThe etnaviv authors else if (gpu->identity.revision < 0x4200) 237a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 256; 238a8c21a54SThe etnaviv authors else 239a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 128; 240a8c21a54SThe etnaviv authors } else { 241a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 242a8c21a54SThe etnaviv authors } 243a8c21a54SThe etnaviv authors 244a8c21a54SThe etnaviv authors switch (gpu->identity.instruction_count) { 245a8c21a54SThe etnaviv authors case 0: 246472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 247507f8991SRussell King gpu->identity.model == chipModel_GC880) 248a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 512; 249a8c21a54SThe etnaviv authors else 250a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 251a8c21a54SThe etnaviv authors break; 252a8c21a54SThe etnaviv authors 253a8c21a54SThe etnaviv authors case 1: 254a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 1024; 255a8c21a54SThe etnaviv authors break; 256a8c21a54SThe etnaviv authors 257a8c21a54SThe etnaviv authors case 2: 258a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 2048; 259a8c21a54SThe etnaviv authors break; 260a8c21a54SThe etnaviv authors 261a8c21a54SThe etnaviv authors default: 262a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 263a8c21a54SThe etnaviv authors break; 264a8c21a54SThe etnaviv authors } 265a8c21a54SThe etnaviv authors 266a8c21a54SThe etnaviv authors if (gpu->identity.num_constants == 0) 267a8c21a54SThe etnaviv authors gpu->identity.num_constants = 168; 268602eb489SRussell King 269602eb489SRussell King if (gpu->identity.varyings_count == 0) { 270602eb489SRussell King if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 271602eb489SRussell King gpu->identity.varyings_count = 12; 272602eb489SRussell King else 273602eb489SRussell King gpu->identity.varyings_count = 8; 274602eb489SRussell King } 275602eb489SRussell King 276602eb489SRussell King /* 277602eb489SRussell King * For some cores, two varyings are consumed for position, so the 278602eb489SRussell King * maximum varying count needs to be reduced by one. 279602eb489SRussell King */ 280602eb489SRussell King if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 281602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 282602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 283602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 284602eb489SRussell King etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 285602eb489SRussell King etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 286602eb489SRussell King etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 287602eb489SRussell King etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 288602eb489SRussell King etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 289602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5107) || 290602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5106)) 291602eb489SRussell King gpu->identity.varyings_count -= 1; 292a8c21a54SThe etnaviv authors } 293a8c21a54SThe etnaviv authors 294a8c21a54SThe etnaviv authors static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 295a8c21a54SThe etnaviv authors { 296a8c21a54SThe etnaviv authors u32 chipIdentity; 297a8c21a54SThe etnaviv authors 298a8c21a54SThe etnaviv authors chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 299a8c21a54SThe etnaviv authors 300a8c21a54SThe etnaviv authors /* Special case for older graphic cores. */ 30152f36ba1SRussell King if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 302507f8991SRussell King gpu->identity.model = chipModel_GC500; 30352f36ba1SRussell King gpu->identity.revision = etnaviv_field(chipIdentity, 30452f36ba1SRussell King VIVS_HI_CHIP_IDENTITY_REVISION); 305a8c21a54SThe etnaviv authors } else { 306a8c21a54SThe etnaviv authors 307a8c21a54SThe etnaviv authors gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 308a8c21a54SThe etnaviv authors gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 309a8c21a54SThe etnaviv authors 310a8c21a54SThe etnaviv authors /* 311a8c21a54SThe etnaviv authors * !!!! HACK ALERT !!!! 312a8c21a54SThe etnaviv authors * Because people change device IDs without letting software 313a8c21a54SThe etnaviv authors * know about it - here is the hack to make it all look the 314a8c21a54SThe etnaviv authors * same. Only for GC400 family. 315a8c21a54SThe etnaviv authors */ 316a8c21a54SThe etnaviv authors if ((gpu->identity.model & 0xff00) == 0x0400 && 317507f8991SRussell King gpu->identity.model != chipModel_GC420) { 318a8c21a54SThe etnaviv authors gpu->identity.model = gpu->identity.model & 0x0400; 319a8c21a54SThe etnaviv authors } 320a8c21a54SThe etnaviv authors 321a8c21a54SThe etnaviv authors /* Another special case */ 322472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 323a8c21a54SThe etnaviv authors u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 324a8c21a54SThe etnaviv authors u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 325a8c21a54SThe etnaviv authors 326a8c21a54SThe etnaviv authors if (chipDate == 0x20080814 && chipTime == 0x12051100) { 327a8c21a54SThe etnaviv authors /* 328a8c21a54SThe etnaviv authors * This IP has an ECO; put the correct 329a8c21a54SThe etnaviv authors * revision in it. 330a8c21a54SThe etnaviv authors */ 331a8c21a54SThe etnaviv authors gpu->identity.revision = 0x1051; 332a8c21a54SThe etnaviv authors } 333a8c21a54SThe etnaviv authors } 33412ff4bdeSLucas Stach 33512ff4bdeSLucas Stach /* 33612ff4bdeSLucas Stach * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 33712ff4bdeSLucas Stach * reality it's just a re-branded GC3000. We can identify this 33812ff4bdeSLucas Stach * core by the upper half of the revision register being all 1. 33912ff4bdeSLucas Stach * Fix model/rev here, so all other places can refer to this 34012ff4bdeSLucas Stach * core by its real identity. 34112ff4bdeSLucas Stach */ 34212ff4bdeSLucas Stach if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 34312ff4bdeSLucas Stach gpu->identity.model = chipModel_GC3000; 34412ff4bdeSLucas Stach gpu->identity.revision &= 0xffff; 34512ff4bdeSLucas Stach } 346a8c21a54SThe etnaviv authors } 347a8c21a54SThe etnaviv authors 348a8c21a54SThe etnaviv authors dev_info(gpu->dev, "model: GC%x, revision: %x\n", 349a8c21a54SThe etnaviv authors gpu->identity.model, gpu->identity.revision); 350a8c21a54SThe etnaviv authors 351a8c21a54SThe etnaviv authors gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 352a8c21a54SThe etnaviv authors 353a8c21a54SThe etnaviv authors /* Disable fast clear on GC700. */ 354507f8991SRussell King if (gpu->identity.model == chipModel_GC700) 355a8c21a54SThe etnaviv authors gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 356a8c21a54SThe etnaviv authors 357507f8991SRussell King if ((gpu->identity.model == chipModel_GC500 && 358507f8991SRussell King gpu->identity.revision < 2) || 359507f8991SRussell King (gpu->identity.model == chipModel_GC300 && 360507f8991SRussell King gpu->identity.revision < 0x2000)) { 361a8c21a54SThe etnaviv authors 362a8c21a54SThe etnaviv authors /* 363a8c21a54SThe etnaviv authors * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 364a8c21a54SThe etnaviv authors * registers. 365a8c21a54SThe etnaviv authors */ 366a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 0; 367a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 0; 368a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 0; 369a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 0; 370602eb489SRussell King gpu->identity.minor_features4 = 0; 371602eb489SRussell King gpu->identity.minor_features5 = 0; 372a8c21a54SThe etnaviv authors } else 373a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 374a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 375a8c21a54SThe etnaviv authors 376a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 377a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 378a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 379a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 380a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 381a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 382a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 383a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 384602eb489SRussell King gpu->identity.minor_features4 = 385602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 386602eb489SRussell King gpu->identity.minor_features5 = 387602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 388a8c21a54SThe etnaviv authors } 389a8c21a54SThe etnaviv authors 390a8c21a54SThe etnaviv authors /* GC600 idle register reports zero bits where modules aren't present */ 391a8c21a54SThe etnaviv authors if (gpu->identity.model == chipModel_GC600) { 392a8c21a54SThe etnaviv authors gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 393a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_RA | 394a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SE | 395a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PA | 396a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SH | 397a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PE | 398a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_DE | 399a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_FE; 400a8c21a54SThe etnaviv authors } else { 401a8c21a54SThe etnaviv authors gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 402a8c21a54SThe etnaviv authors } 403a8c21a54SThe etnaviv authors 404a8c21a54SThe etnaviv authors etnaviv_hw_specs(gpu); 405a8c21a54SThe etnaviv authors } 406a8c21a54SThe etnaviv authors 407a8c21a54SThe etnaviv authors static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 408a8c21a54SThe etnaviv authors { 409a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 410a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 411a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 412a8c21a54SThe etnaviv authors } 413a8c21a54SThe etnaviv authors 414bcdfb5e5SRussell King static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 415bcdfb5e5SRussell King { 416d79fd1ccSLucas Stach if (gpu->identity.minor_features2 & 417d79fd1ccSLucas Stach chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 418d79fd1ccSLucas Stach clk_set_rate(gpu->clk_core, 419d79fd1ccSLucas Stach gpu->base_rate_core >> gpu->freq_scale); 420d79fd1ccSLucas Stach clk_set_rate(gpu->clk_shader, 421d79fd1ccSLucas Stach gpu->base_rate_shader >> gpu->freq_scale); 422d79fd1ccSLucas Stach } else { 423bcdfb5e5SRussell King unsigned int fscale = 1 << (6 - gpu->freq_scale); 4246eb3ecc3SLucas Stach u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 425bcdfb5e5SRussell King 4266eb3ecc3SLucas Stach clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 4276eb3ecc3SLucas Stach clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 428bcdfb5e5SRussell King etnaviv_gpu_load_clock(gpu, clock); 429bcdfb5e5SRussell King } 430d79fd1ccSLucas Stach } 431bcdfb5e5SRussell King 432a8c21a54SThe etnaviv authors static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 433a8c21a54SThe etnaviv authors { 434a8c21a54SThe etnaviv authors u32 control, idle; 435a8c21a54SThe etnaviv authors unsigned long timeout; 436a8c21a54SThe etnaviv authors bool failed = true; 437a8c21a54SThe etnaviv authors 438a8c21a54SThe etnaviv authors /* We hope that the GPU resets in under one second */ 439a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(1000); 440a8c21a54SThe etnaviv authors 441a8c21a54SThe etnaviv authors while (time_is_after_jiffies(timeout)) { 442a8c21a54SThe etnaviv authors /* enable clock */ 4436eb3ecc3SLucas Stach unsigned int fscale = 1 << (6 - gpu->freq_scale); 4446eb3ecc3SLucas Stach control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 4456eb3ecc3SLucas Stach etnaviv_gpu_load_clock(gpu, control); 446a8c21a54SThe etnaviv authors 447a8c21a54SThe etnaviv authors /* isolate the GPU. */ 448a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 449a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 450a8c21a54SThe etnaviv authors 451a8c21a54SThe etnaviv authors /* set soft reset. */ 452a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 453a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 454a8c21a54SThe etnaviv authors 455a8c21a54SThe etnaviv authors /* wait for reset. */ 45640462179SPhilipp Zabel usleep_range(10, 20); 457a8c21a54SThe etnaviv authors 458a8c21a54SThe etnaviv authors /* reset soft reset bit. */ 459a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 460a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 461a8c21a54SThe etnaviv authors 462a8c21a54SThe etnaviv authors /* reset GPU isolation. */ 463a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 464a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 465a8c21a54SThe etnaviv authors 466a8c21a54SThe etnaviv authors /* read idle register. */ 467a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 468a8c21a54SThe etnaviv authors 469a8c21a54SThe etnaviv authors /* try reseting again if FE it not idle */ 470a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 471a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "FE is not idle\n"); 472a8c21a54SThe etnaviv authors continue; 473a8c21a54SThe etnaviv authors } 474a8c21a54SThe etnaviv authors 475a8c21a54SThe etnaviv authors /* read reset register. */ 476a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 477a8c21a54SThe etnaviv authors 478a8c21a54SThe etnaviv authors /* is the GPU idle? */ 479a8c21a54SThe etnaviv authors if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 480a8c21a54SThe etnaviv authors ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 481a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "GPU is not idle\n"); 482a8c21a54SThe etnaviv authors continue; 483a8c21a54SThe etnaviv authors } 484a8c21a54SThe etnaviv authors 4856eb3ecc3SLucas Stach /* disable debug registers, as they are not normally needed */ 4866eb3ecc3SLucas Stach control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 4876eb3ecc3SLucas Stach gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 4886eb3ecc3SLucas Stach 489a8c21a54SThe etnaviv authors failed = false; 490a8c21a54SThe etnaviv authors break; 491a8c21a54SThe etnaviv authors } 492a8c21a54SThe etnaviv authors 493a8c21a54SThe etnaviv authors if (failed) { 494a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 495a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 496a8c21a54SThe etnaviv authors 497a8c21a54SThe etnaviv authors dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 498a8c21a54SThe etnaviv authors idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 499a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 500a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 501a8c21a54SThe etnaviv authors 502a8c21a54SThe etnaviv authors return -EBUSY; 503a8c21a54SThe etnaviv authors } 504a8c21a54SThe etnaviv authors 505a8c21a54SThe etnaviv authors /* We rely on the GPU running, so program the clock */ 506bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 507a8c21a54SThe etnaviv authors 508a8c21a54SThe etnaviv authors return 0; 509a8c21a54SThe etnaviv authors } 510a8c21a54SThe etnaviv authors 5117d0c6e71SRussell King static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 5127d0c6e71SRussell King { 5137d0c6e71SRussell King u32 pmc, ppc; 5147d0c6e71SRussell King 5157d0c6e71SRussell King /* enable clock gating */ 5167d0c6e71SRussell King ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 5177d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 5187d0c6e71SRussell King 5197d0c6e71SRussell King /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 5207d0c6e71SRussell King if (gpu->identity.revision == 0x4301 || 5217d0c6e71SRussell King gpu->identity.revision == 0x4302) 5227d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 5237d0c6e71SRussell King 5247d0c6e71SRussell King gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 5257d0c6e71SRussell King 5267d0c6e71SRussell King pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 5277d0c6e71SRussell King 5287cef6004SLucas Stach /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 5297d0c6e71SRussell King if (gpu->identity.model >= chipModel_GC400 && 5307cef6004SLucas Stach gpu->identity.model != chipModel_GC420 && 5317cef6004SLucas Stach !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 5327d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 5337d0c6e71SRussell King 5347d0c6e71SRussell King /* 5357d0c6e71SRussell King * Disable PE clock gating on revs < 5.0.0.0 when HZ is 5367d0c6e71SRussell King * present without a bug fix. 5377d0c6e71SRussell King */ 5387d0c6e71SRussell King if (gpu->identity.revision < 0x5000 && 5397d0c6e71SRussell King gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 5407d0c6e71SRussell King !(gpu->identity.minor_features1 & 5417d0c6e71SRussell King chipMinorFeatures1_DISABLE_PE_GATING)) 5427d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 5437d0c6e71SRussell King 5447d0c6e71SRussell King if (gpu->identity.revision < 0x5422) 5457d0c6e71SRussell King pmc |= BIT(15); /* Unknown bit */ 5467d0c6e71SRussell King 5477cef6004SLucas Stach /* Disable TX clock gating on affected core revisions. */ 5487cef6004SLucas Stach if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 5497cef6004SLucas Stach etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 5507cef6004SLucas Stach pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 5517cef6004SLucas Stach 5527d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 5537d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 5547d0c6e71SRussell King 5557d0c6e71SRussell King gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 5567d0c6e71SRussell King } 5577d0c6e71SRussell King 558229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 559229855b6SLucas Stach { 560229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 561229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 562229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_ENABLE | 563229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 564229855b6SLucas Stach } 565229855b6SLucas Stach 566e17a0dedSWladimir J. van der Laan static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 567e17a0dedSWladimir J. van der Laan { 568e17a0dedSWladimir J. van der Laan /* 569e17a0dedSWladimir J. van der Laan * Base value for VIVS_PM_PULSE_EATER register on models where it 570e17a0dedSWladimir J. van der Laan * cannot be read, extracted from vivante kernel driver. 571e17a0dedSWladimir J. van der Laan */ 572e17a0dedSWladimir J. van der Laan u32 pulse_eater = 0x01590880; 573e17a0dedSWladimir J. van der Laan 574e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 575e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 576e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(23); 577e17a0dedSWladimir J. van der Laan 578e17a0dedSWladimir J. van der Laan } 579e17a0dedSWladimir J. van der Laan 580e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 581e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 582e17a0dedSWladimir J. van der Laan pulse_eater &= ~BIT(16); 583e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(17); 584e17a0dedSWladimir J. van der Laan } 585e17a0dedSWladimir J. van der Laan 586e17a0dedSWladimir J. van der Laan if ((gpu->identity.revision > 0x5420) && 587e17a0dedSWladimir J. van der Laan (gpu->identity.features & chipFeatures_PIPE_3D)) 588e17a0dedSWladimir J. van der Laan { 589e17a0dedSWladimir J. van der Laan /* Performance fix: disable internal DFS */ 590e17a0dedSWladimir J. van der Laan pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 591e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(18); 592e17a0dedSWladimir J. van der Laan } 593e17a0dedSWladimir J. van der Laan 594e17a0dedSWladimir J. van der Laan gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 595e17a0dedSWladimir J. van der Laan } 596e17a0dedSWladimir J. van der Laan 597a8c21a54SThe etnaviv authors static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 598a8c21a54SThe etnaviv authors { 599a8c21a54SThe etnaviv authors u16 prefetch; 600a8c21a54SThe etnaviv authors 601472f79dcSRussell King if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 602472f79dcSRussell King etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 603472f79dcSRussell King gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 604a8c21a54SThe etnaviv authors u32 mc_memory_debug; 605a8c21a54SThe etnaviv authors 606a8c21a54SThe etnaviv authors mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 607a8c21a54SThe etnaviv authors 608a8c21a54SThe etnaviv authors if (gpu->identity.revision == 0x5007) 609a8c21a54SThe etnaviv authors mc_memory_debug |= 0x0c; 610a8c21a54SThe etnaviv authors else 611a8c21a54SThe etnaviv authors mc_memory_debug |= 0x08; 612a8c21a54SThe etnaviv authors 613a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 614a8c21a54SThe etnaviv authors } 615a8c21a54SThe etnaviv authors 6167d0c6e71SRussell King /* enable module-level clock gating */ 6177d0c6e71SRussell King etnaviv_gpu_enable_mlcg(gpu); 6187d0c6e71SRussell King 619a8c21a54SThe etnaviv authors /* 620a8c21a54SThe etnaviv authors * Update GPU AXI cache atttribute to "cacheable, no allocate". 621a8c21a54SThe etnaviv authors * This is necessary to prevent the iMX6 SoC locking up. 622a8c21a54SThe etnaviv authors */ 623a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_AXI_CONFIG, 624a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_AWCACHE(2) | 625a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_ARCACHE(2)); 626a8c21a54SThe etnaviv authors 627a8c21a54SThe etnaviv authors /* GC2000 rev 5108 needs a special bus config */ 628472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 629a8c21a54SThe etnaviv authors u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 630a8c21a54SThe etnaviv authors bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 631a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 632a8c21a54SThe etnaviv authors bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 633a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 634a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 635a8c21a54SThe etnaviv authors } 636a8c21a54SThe etnaviv authors 637e17a0dedSWladimir J. van der Laan /* setup the pulse eater */ 638e17a0dedSWladimir J. van der Laan etnaviv_gpu_setup_pulse_eater(gpu); 639e17a0dedSWladimir J. van der Laan 64099f861bcSLucas Stach /* setup the MMU */ 641e095c8feSLucas Stach etnaviv_iommu_restore(gpu); 642a8c21a54SThe etnaviv authors 643a8c21a54SThe etnaviv authors /* Start command processor */ 644a8c21a54SThe etnaviv authors prefetch = etnaviv_buffer_init(gpu); 645a8c21a54SThe etnaviv authors 646a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 647c3ef4b8cSLucas Stach etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer), 648229855b6SLucas Stach prefetch); 649a8c21a54SThe etnaviv authors } 650a8c21a54SThe etnaviv authors 651a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 652a8c21a54SThe etnaviv authors { 653a8c21a54SThe etnaviv authors int ret, i; 654a8c21a54SThe etnaviv authors 655a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 6561409df04SLucas Stach if (ret < 0) { 6571409df04SLucas Stach dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 658a8c21a54SThe etnaviv authors return ret; 6591409df04SLucas Stach } 660a8c21a54SThe etnaviv authors 661a8c21a54SThe etnaviv authors etnaviv_hw_identify(gpu); 662a8c21a54SThe etnaviv authors 663a8c21a54SThe etnaviv authors if (gpu->identity.model == 0) { 664a8c21a54SThe etnaviv authors dev_err(gpu->dev, "Unknown GPU model\n"); 665f6427760SRussell King ret = -ENXIO; 666f6427760SRussell King goto fail; 667a8c21a54SThe etnaviv authors } 668a8c21a54SThe etnaviv authors 669b98c6688SRussell King /* Exclude VG cores with FE2.0 */ 670b98c6688SRussell King if (gpu->identity.features & chipFeatures_PIPE_VG && 671b98c6688SRussell King gpu->identity.features & chipFeatures_FE20) { 672b98c6688SRussell King dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 673b98c6688SRussell King ret = -ENXIO; 674b98c6688SRussell King goto fail; 675b98c6688SRussell King } 676b98c6688SRussell King 6772144fff7SLucas Stach /* 6782144fff7SLucas Stach * Set the GPU linear window to be at the end of the DMA window, where 6792144fff7SLucas Stach * the CMA area is likely to reside. This ensures that we are able to 6802144fff7SLucas Stach * map the command buffers while having the linear window overlap as 6812144fff7SLucas Stach * much RAM as possible, so we can optimize mappings for other buffers. 6822144fff7SLucas Stach * 6832144fff7SLucas Stach * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 6842144fff7SLucas Stach * to different views of the memory on the individual engines. 6852144fff7SLucas Stach */ 6862144fff7SLucas Stach if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 6872144fff7SLucas Stach (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 6882144fff7SLucas Stach u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 6892144fff7SLucas Stach if (dma_mask < PHYS_OFFSET + SZ_2G) 6902144fff7SLucas Stach gpu->memory_base = PHYS_OFFSET; 6912144fff7SLucas Stach else 6922144fff7SLucas Stach gpu->memory_base = dma_mask - SZ_2G + 1; 6931db01279SLucas Stach } else if (PHYS_OFFSET >= SZ_2G) { 6941db01279SLucas Stach dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 6951db01279SLucas Stach gpu->memory_base = PHYS_OFFSET; 6961db01279SLucas Stach gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 6972144fff7SLucas Stach } 6982144fff7SLucas Stach 699a8c21a54SThe etnaviv authors ret = etnaviv_hw_reset(gpu); 7001409df04SLucas Stach if (ret) { 7011409df04SLucas Stach dev_err(gpu->dev, "GPU reset failed\n"); 702a8c21a54SThe etnaviv authors goto fail; 7031409df04SLucas Stach } 704a8c21a54SThe etnaviv authors 705dd34bb96SLucas Stach gpu->mmu = etnaviv_iommu_new(gpu); 706dd34bb96SLucas Stach if (IS_ERR(gpu->mmu)) { 7071409df04SLucas Stach dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 708dd34bb96SLucas Stach ret = PTR_ERR(gpu->mmu); 709a8c21a54SThe etnaviv authors goto fail; 710a8c21a54SThe etnaviv authors } 711a8c21a54SThe etnaviv authors 712e66774ddSLucas Stach gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu); 713e66774ddSLucas Stach if (IS_ERR(gpu->cmdbuf_suballoc)) { 714e66774ddSLucas Stach dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); 715e66774ddSLucas Stach ret = PTR_ERR(gpu->cmdbuf_suballoc); 716e66774ddSLucas Stach goto fail; 717e66774ddSLucas Stach } 718e66774ddSLucas Stach 719a8c21a54SThe etnaviv authors /* Create buffer: */ 7204fc3e66aSChristian Gmeiner gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0, 0); 721a8c21a54SThe etnaviv authors if (!gpu->buffer) { 722a8c21a54SThe etnaviv authors ret = -ENOMEM; 723a8c21a54SThe etnaviv authors dev_err(gpu->dev, "could not create command buffer\n"); 72445d16a6dSLucas Stach goto destroy_iommu; 725a8c21a54SThe etnaviv authors } 726acfee0ecSLucas Stach 727acfee0ecSLucas Stach if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 728c3ef4b8cSLucas Stach etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) { 729a8c21a54SThe etnaviv authors ret = -EINVAL; 730a8c21a54SThe etnaviv authors dev_err(gpu->dev, 731a8c21a54SThe etnaviv authors "command buffer outside valid memory window\n"); 732a8c21a54SThe etnaviv authors goto free_buffer; 733a8c21a54SThe etnaviv authors } 734a8c21a54SThe etnaviv authors 735a8c21a54SThe etnaviv authors /* Setup event management */ 736a8c21a54SThe etnaviv authors spin_lock_init(&gpu->event_spinlock); 737a8c21a54SThe etnaviv authors init_completion(&gpu->event_free); 738355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 739355502e0SChristian Gmeiner for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 740a8c21a54SThe etnaviv authors complete(&gpu->event_free); 741a8c21a54SThe etnaviv authors 742a8c21a54SThe etnaviv authors /* Now program the hardware */ 743a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 744a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 745f6086311SRussell King gpu->exec_state = -1; 746a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 747a8c21a54SThe etnaviv authors 748a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 749a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 750a8c21a54SThe etnaviv authors 751a8c21a54SThe etnaviv authors return 0; 752a8c21a54SThe etnaviv authors 753a8c21a54SThe etnaviv authors free_buffer: 754ea1f5729SLucas Stach etnaviv_cmdbuf_free(gpu->buffer); 755a8c21a54SThe etnaviv authors gpu->buffer = NULL; 75645d16a6dSLucas Stach destroy_iommu: 75745d16a6dSLucas Stach etnaviv_iommu_destroy(gpu->mmu); 75845d16a6dSLucas Stach gpu->mmu = NULL; 759a8c21a54SThe etnaviv authors fail: 760a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 761a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 762a8c21a54SThe etnaviv authors 763a8c21a54SThe etnaviv authors return ret; 764a8c21a54SThe etnaviv authors } 765a8c21a54SThe etnaviv authors 766a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 767a8c21a54SThe etnaviv authors struct dma_debug { 768a8c21a54SThe etnaviv authors u32 address[2]; 769a8c21a54SThe etnaviv authors u32 state[2]; 770a8c21a54SThe etnaviv authors }; 771a8c21a54SThe etnaviv authors 772a8c21a54SThe etnaviv authors static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 773a8c21a54SThe etnaviv authors { 774a8c21a54SThe etnaviv authors u32 i; 775a8c21a54SThe etnaviv authors 776a8c21a54SThe etnaviv authors debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 777a8c21a54SThe etnaviv authors debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 778a8c21a54SThe etnaviv authors 779a8c21a54SThe etnaviv authors for (i = 0; i < 500; i++) { 780a8c21a54SThe etnaviv authors debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 781a8c21a54SThe etnaviv authors debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 782a8c21a54SThe etnaviv authors 783a8c21a54SThe etnaviv authors if (debug->address[0] != debug->address[1]) 784a8c21a54SThe etnaviv authors break; 785a8c21a54SThe etnaviv authors 786a8c21a54SThe etnaviv authors if (debug->state[0] != debug->state[1]) 787a8c21a54SThe etnaviv authors break; 788a8c21a54SThe etnaviv authors } 789a8c21a54SThe etnaviv authors } 790a8c21a54SThe etnaviv authors 791a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 792a8c21a54SThe etnaviv authors { 793a8c21a54SThe etnaviv authors struct dma_debug debug; 794a8c21a54SThe etnaviv authors u32 dma_lo, dma_hi, axi, idle; 795a8c21a54SThe etnaviv authors int ret; 796a8c21a54SThe etnaviv authors 797a8c21a54SThe etnaviv authors seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 798a8c21a54SThe etnaviv authors 799a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 800a8c21a54SThe etnaviv authors if (ret < 0) 801a8c21a54SThe etnaviv authors return ret; 802a8c21a54SThe etnaviv authors 803a8c21a54SThe etnaviv authors dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 804a8c21a54SThe etnaviv authors dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 805a8c21a54SThe etnaviv authors axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 806a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 807a8c21a54SThe etnaviv authors 808a8c21a54SThe etnaviv authors verify_dma(gpu, &debug); 809a8c21a54SThe etnaviv authors 810a8c21a54SThe etnaviv authors seq_puts(m, "\tfeatures\n"); 811a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features0: 0x%08x\n", 812a8c21a54SThe etnaviv authors gpu->identity.minor_features0); 813a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features1: 0x%08x\n", 814a8c21a54SThe etnaviv authors gpu->identity.minor_features1); 815a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features2: 0x%08x\n", 816a8c21a54SThe etnaviv authors gpu->identity.minor_features2); 817a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features3: 0x%08x\n", 818a8c21a54SThe etnaviv authors gpu->identity.minor_features3); 819602eb489SRussell King seq_printf(m, "\t minor_features4: 0x%08x\n", 820602eb489SRussell King gpu->identity.minor_features4); 821602eb489SRussell King seq_printf(m, "\t minor_features5: 0x%08x\n", 822602eb489SRussell King gpu->identity.minor_features5); 823a8c21a54SThe etnaviv authors 824a8c21a54SThe etnaviv authors seq_puts(m, "\tspecs\n"); 825a8c21a54SThe etnaviv authors seq_printf(m, "\t stream_count: %d\n", 826a8c21a54SThe etnaviv authors gpu->identity.stream_count); 827a8c21a54SThe etnaviv authors seq_printf(m, "\t register_max: %d\n", 828a8c21a54SThe etnaviv authors gpu->identity.register_max); 829a8c21a54SThe etnaviv authors seq_printf(m, "\t thread_count: %d\n", 830a8c21a54SThe etnaviv authors gpu->identity.thread_count); 831a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_cache_size: %d\n", 832a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size); 833a8c21a54SThe etnaviv authors seq_printf(m, "\t shader_core_count: %d\n", 834a8c21a54SThe etnaviv authors gpu->identity.shader_core_count); 835a8c21a54SThe etnaviv authors seq_printf(m, "\t pixel_pipes: %d\n", 836a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes); 837a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_output_buffer_size: %d\n", 838a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size); 839a8c21a54SThe etnaviv authors seq_printf(m, "\t buffer_size: %d\n", 840a8c21a54SThe etnaviv authors gpu->identity.buffer_size); 841a8c21a54SThe etnaviv authors seq_printf(m, "\t instruction_count: %d\n", 842a8c21a54SThe etnaviv authors gpu->identity.instruction_count); 843a8c21a54SThe etnaviv authors seq_printf(m, "\t num_constants: %d\n", 844a8c21a54SThe etnaviv authors gpu->identity.num_constants); 845602eb489SRussell King seq_printf(m, "\t varyings_count: %d\n", 846602eb489SRussell King gpu->identity.varyings_count); 847a8c21a54SThe etnaviv authors 848a8c21a54SThe etnaviv authors seq_printf(m, "\taxi: 0x%08x\n", axi); 849a8c21a54SThe etnaviv authors seq_printf(m, "\tidle: 0x%08x\n", idle); 850a8c21a54SThe etnaviv authors idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 851a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 852a8c21a54SThe etnaviv authors seq_puts(m, "\t FE is not idle\n"); 853a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 854a8c21a54SThe etnaviv authors seq_puts(m, "\t DE is not idle\n"); 855a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 856a8c21a54SThe etnaviv authors seq_puts(m, "\t PE is not idle\n"); 857a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 858a8c21a54SThe etnaviv authors seq_puts(m, "\t SH is not idle\n"); 859a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 860a8c21a54SThe etnaviv authors seq_puts(m, "\t PA is not idle\n"); 861a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 862a8c21a54SThe etnaviv authors seq_puts(m, "\t SE is not idle\n"); 863a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 864a8c21a54SThe etnaviv authors seq_puts(m, "\t RA is not idle\n"); 865a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 866a8c21a54SThe etnaviv authors seq_puts(m, "\t TX is not idle\n"); 867a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 868a8c21a54SThe etnaviv authors seq_puts(m, "\t VG is not idle\n"); 869a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 870a8c21a54SThe etnaviv authors seq_puts(m, "\t IM is not idle\n"); 871a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 872a8c21a54SThe etnaviv authors seq_puts(m, "\t FP is not idle\n"); 873a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 874a8c21a54SThe etnaviv authors seq_puts(m, "\t TS is not idle\n"); 875a8c21a54SThe etnaviv authors if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 876a8c21a54SThe etnaviv authors seq_puts(m, "\t AXI low power mode\n"); 877a8c21a54SThe etnaviv authors 878a8c21a54SThe etnaviv authors if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 879a8c21a54SThe etnaviv authors u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 880a8c21a54SThe etnaviv authors u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 881a8c21a54SThe etnaviv authors u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 882a8c21a54SThe etnaviv authors 883a8c21a54SThe etnaviv authors seq_puts(m, "\tMC\n"); 884a8c21a54SThe etnaviv authors seq_printf(m, "\t read0: 0x%08x\n", read0); 885a8c21a54SThe etnaviv authors seq_printf(m, "\t read1: 0x%08x\n", read1); 886a8c21a54SThe etnaviv authors seq_printf(m, "\t write: 0x%08x\n", write); 887a8c21a54SThe etnaviv authors } 888a8c21a54SThe etnaviv authors 889a8c21a54SThe etnaviv authors seq_puts(m, "\tDMA "); 890a8c21a54SThe etnaviv authors 891a8c21a54SThe etnaviv authors if (debug.address[0] == debug.address[1] && 892a8c21a54SThe etnaviv authors debug.state[0] == debug.state[1]) { 893a8c21a54SThe etnaviv authors seq_puts(m, "seems to be stuck\n"); 894a8c21a54SThe etnaviv authors } else if (debug.address[0] == debug.address[1]) { 895c01e0159SMasanari Iida seq_puts(m, "address is constant\n"); 896a8c21a54SThe etnaviv authors } else { 897c01e0159SMasanari Iida seq_puts(m, "is running\n"); 898a8c21a54SThe etnaviv authors } 899a8c21a54SThe etnaviv authors 900a8c21a54SThe etnaviv authors seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 901a8c21a54SThe etnaviv authors seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 902a8c21a54SThe etnaviv authors seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 903a8c21a54SThe etnaviv authors seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 904a8c21a54SThe etnaviv authors seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 905a8c21a54SThe etnaviv authors dma_lo, dma_hi); 906a8c21a54SThe etnaviv authors 907a8c21a54SThe etnaviv authors ret = 0; 908a8c21a54SThe etnaviv authors 909a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 910a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 911a8c21a54SThe etnaviv authors 912a8c21a54SThe etnaviv authors return ret; 913a8c21a54SThe etnaviv authors } 914a8c21a54SThe etnaviv authors #endif 915a8c21a54SThe etnaviv authors 916a8c21a54SThe etnaviv authors /* 917a8c21a54SThe etnaviv authors * Hangcheck detection for locked gpu: 918a8c21a54SThe etnaviv authors */ 919a8c21a54SThe etnaviv authors static void recover_worker(struct work_struct *work) 920a8c21a54SThe etnaviv authors { 921a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 922a8c21a54SThe etnaviv authors recover_work); 923a8c21a54SThe etnaviv authors unsigned long flags; 924355502e0SChristian Gmeiner unsigned int i = 0; 925a8c21a54SThe etnaviv authors 926a8c21a54SThe etnaviv authors dev_err(gpu->dev, "hangcheck recover!\n"); 927a8c21a54SThe etnaviv authors 928a8c21a54SThe etnaviv authors if (pm_runtime_get_sync(gpu->dev) < 0) 929a8c21a54SThe etnaviv authors return; 930a8c21a54SThe etnaviv authors 931a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 932a8c21a54SThe etnaviv authors 933a8c21a54SThe etnaviv authors /* Only catch the first event, or when manually re-armed */ 934a8c21a54SThe etnaviv authors if (etnaviv_dump_core) { 935a8c21a54SThe etnaviv authors etnaviv_core_dump(gpu); 936a8c21a54SThe etnaviv authors etnaviv_dump_core = false; 937a8c21a54SThe etnaviv authors } 938a8c21a54SThe etnaviv authors 939a8c21a54SThe etnaviv authors etnaviv_hw_reset(gpu); 940a8c21a54SThe etnaviv authors 941a8c21a54SThe etnaviv authors /* complete all events, the GPU won't do it after the reset */ 942a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 943355502e0SChristian Gmeiner for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) { 944f54d1867SChris Wilson dma_fence_signal(gpu->event[i].fence); 945a8c21a54SThe etnaviv authors gpu->event[i].fence = NULL; 946a8c21a54SThe etnaviv authors complete(&gpu->event_free); 947a8c21a54SThe etnaviv authors } 948355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 949a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 950a8c21a54SThe etnaviv authors gpu->completed_fence = gpu->active_fence; 951a8c21a54SThe etnaviv authors 952a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 9531b94a9b7SLucas Stach gpu->lastctx = NULL; 954f6086311SRussell King gpu->exec_state = -1; 955a8c21a54SThe etnaviv authors 956a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 957a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 958a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 959a8c21a54SThe etnaviv authors 960a8c21a54SThe etnaviv authors /* Retire the buffer objects in a work */ 961a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->retire_work); 962a8c21a54SThe etnaviv authors } 963a8c21a54SThe etnaviv authors 964a8c21a54SThe etnaviv authors static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) 965a8c21a54SThe etnaviv authors { 966a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 967a8c21a54SThe etnaviv authors mod_timer(&gpu->hangcheck_timer, 968a8c21a54SThe etnaviv authors round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); 969a8c21a54SThe etnaviv authors } 970a8c21a54SThe etnaviv authors 97143b70524SKees Cook static void hangcheck_handler(struct timer_list *t) 972a8c21a54SThe etnaviv authors { 97343b70524SKees Cook struct etnaviv_gpu *gpu = from_timer(gpu, t, hangcheck_timer); 974a8c21a54SThe etnaviv authors u32 fence = gpu->completed_fence; 975a8c21a54SThe etnaviv authors bool progress = false; 976a8c21a54SThe etnaviv authors 977a8c21a54SThe etnaviv authors if (fence != gpu->hangcheck_fence) { 978a8c21a54SThe etnaviv authors gpu->hangcheck_fence = fence; 979a8c21a54SThe etnaviv authors progress = true; 980a8c21a54SThe etnaviv authors } 981a8c21a54SThe etnaviv authors 982a8c21a54SThe etnaviv authors if (!progress) { 983a8c21a54SThe etnaviv authors u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 984a8c21a54SThe etnaviv authors int change = dma_addr - gpu->hangcheck_dma_addr; 985a8c21a54SThe etnaviv authors 986a8c21a54SThe etnaviv authors if (change < 0 || change > 16) { 987a8c21a54SThe etnaviv authors gpu->hangcheck_dma_addr = dma_addr; 988a8c21a54SThe etnaviv authors progress = true; 989a8c21a54SThe etnaviv authors } 990a8c21a54SThe etnaviv authors } 991a8c21a54SThe etnaviv authors 992a8c21a54SThe etnaviv authors if (!progress && fence_after(gpu->active_fence, fence)) { 993a8c21a54SThe etnaviv authors dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); 994a8c21a54SThe etnaviv authors dev_err(gpu->dev, " completed fence: %u\n", fence); 995a8c21a54SThe etnaviv authors dev_err(gpu->dev, " active fence: %u\n", 996a8c21a54SThe etnaviv authors gpu->active_fence); 997a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->recover_work); 998a8c21a54SThe etnaviv authors } 999a8c21a54SThe etnaviv authors 1000a8c21a54SThe etnaviv authors /* if still more pending work, reset the hangcheck timer: */ 1001a8c21a54SThe etnaviv authors if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) 1002a8c21a54SThe etnaviv authors hangcheck_timer_reset(gpu); 1003a8c21a54SThe etnaviv authors } 1004a8c21a54SThe etnaviv authors 1005a8c21a54SThe etnaviv authors static void hangcheck_disable(struct etnaviv_gpu *gpu) 1006a8c21a54SThe etnaviv authors { 1007a8c21a54SThe etnaviv authors del_timer_sync(&gpu->hangcheck_timer); 1008a8c21a54SThe etnaviv authors cancel_work_sync(&gpu->recover_work); 1009a8c21a54SThe etnaviv authors } 1010a8c21a54SThe etnaviv authors 1011a8c21a54SThe etnaviv authors /* fence object management */ 1012a8c21a54SThe etnaviv authors struct etnaviv_fence { 1013a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1014f54d1867SChris Wilson struct dma_fence base; 1015a8c21a54SThe etnaviv authors }; 1016a8c21a54SThe etnaviv authors 1017f54d1867SChris Wilson static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1018a8c21a54SThe etnaviv authors { 1019a8c21a54SThe etnaviv authors return container_of(fence, struct etnaviv_fence, base); 1020a8c21a54SThe etnaviv authors } 1021a8c21a54SThe etnaviv authors 1022f54d1867SChris Wilson static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1023a8c21a54SThe etnaviv authors { 1024a8c21a54SThe etnaviv authors return "etnaviv"; 1025a8c21a54SThe etnaviv authors } 1026a8c21a54SThe etnaviv authors 1027f54d1867SChris Wilson static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1028a8c21a54SThe etnaviv authors { 1029a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1030a8c21a54SThe etnaviv authors 1031a8c21a54SThe etnaviv authors return dev_name(f->gpu->dev); 1032a8c21a54SThe etnaviv authors } 1033a8c21a54SThe etnaviv authors 1034f54d1867SChris Wilson static bool etnaviv_fence_enable_signaling(struct dma_fence *fence) 1035a8c21a54SThe etnaviv authors { 1036a8c21a54SThe etnaviv authors return true; 1037a8c21a54SThe etnaviv authors } 1038a8c21a54SThe etnaviv authors 1039f54d1867SChris Wilson static bool etnaviv_fence_signaled(struct dma_fence *fence) 1040a8c21a54SThe etnaviv authors { 1041a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1042a8c21a54SThe etnaviv authors 1043a8c21a54SThe etnaviv authors return fence_completed(f->gpu, f->base.seqno); 1044a8c21a54SThe etnaviv authors } 1045a8c21a54SThe etnaviv authors 1046f54d1867SChris Wilson static void etnaviv_fence_release(struct dma_fence *fence) 1047a8c21a54SThe etnaviv authors { 1048a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1049a8c21a54SThe etnaviv authors 1050a8c21a54SThe etnaviv authors kfree_rcu(f, base.rcu); 1051a8c21a54SThe etnaviv authors } 1052a8c21a54SThe etnaviv authors 1053f54d1867SChris Wilson static const struct dma_fence_ops etnaviv_fence_ops = { 1054a8c21a54SThe etnaviv authors .get_driver_name = etnaviv_fence_get_driver_name, 1055a8c21a54SThe etnaviv authors .get_timeline_name = etnaviv_fence_get_timeline_name, 1056a8c21a54SThe etnaviv authors .enable_signaling = etnaviv_fence_enable_signaling, 1057a8c21a54SThe etnaviv authors .signaled = etnaviv_fence_signaled, 1058f54d1867SChris Wilson .wait = dma_fence_default_wait, 1059a8c21a54SThe etnaviv authors .release = etnaviv_fence_release, 1060a8c21a54SThe etnaviv authors }; 1061a8c21a54SThe etnaviv authors 1062f54d1867SChris Wilson static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1063a8c21a54SThe etnaviv authors { 1064a8c21a54SThe etnaviv authors struct etnaviv_fence *f; 1065a8c21a54SThe etnaviv authors 1066b27734c2SLucas Stach /* 1067b27734c2SLucas Stach * GPU lock must already be held, otherwise fence completion order might 1068b27734c2SLucas Stach * not match the seqno order assigned here. 1069b27734c2SLucas Stach */ 1070b27734c2SLucas Stach lockdep_assert_held(&gpu->lock); 1071b27734c2SLucas Stach 1072a8c21a54SThe etnaviv authors f = kzalloc(sizeof(*f), GFP_KERNEL); 1073a8c21a54SThe etnaviv authors if (!f) 1074a8c21a54SThe etnaviv authors return NULL; 1075a8c21a54SThe etnaviv authors 1076a8c21a54SThe etnaviv authors f->gpu = gpu; 1077a8c21a54SThe etnaviv authors 1078f54d1867SChris Wilson dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1079a8c21a54SThe etnaviv authors gpu->fence_context, ++gpu->next_fence); 1080a8c21a54SThe etnaviv authors 1081a8c21a54SThe etnaviv authors return &f->base; 1082a8c21a54SThe etnaviv authors } 1083a8c21a54SThe etnaviv authors 1084a8c21a54SThe etnaviv authors int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 10859ad59feaSPhilipp Zabel unsigned int context, bool exclusive, bool explicit) 1086a8c21a54SThe etnaviv authors { 1087a8c21a54SThe etnaviv authors struct reservation_object *robj = etnaviv_obj->resv; 1088a8c21a54SThe etnaviv authors struct reservation_object_list *fobj; 1089f54d1867SChris Wilson struct dma_fence *fence; 1090a8c21a54SThe etnaviv authors int i, ret; 1091a8c21a54SThe etnaviv authors 1092a8c21a54SThe etnaviv authors if (!exclusive) { 1093a8c21a54SThe etnaviv authors ret = reservation_object_reserve_shared(robj); 1094a8c21a54SThe etnaviv authors if (ret) 1095a8c21a54SThe etnaviv authors return ret; 1096a8c21a54SThe etnaviv authors } 1097a8c21a54SThe etnaviv authors 10989ad59feaSPhilipp Zabel if (explicit) 10999ad59feaSPhilipp Zabel return 0; 11009ad59feaSPhilipp Zabel 1101a8c21a54SThe etnaviv authors /* 1102a8c21a54SThe etnaviv authors * If we have any shared fences, then the exclusive fence 1103a8c21a54SThe etnaviv authors * should be ignored as it will already have been signalled. 1104a8c21a54SThe etnaviv authors */ 1105a8c21a54SThe etnaviv authors fobj = reservation_object_get_list(robj); 1106a8c21a54SThe etnaviv authors if (!fobj || fobj->shared_count == 0) { 1107a8c21a54SThe etnaviv authors /* Wait on any existing exclusive fence which isn't our own */ 1108a8c21a54SThe etnaviv authors fence = reservation_object_get_excl(robj); 1109a8c21a54SThe etnaviv authors if (fence && fence->context != context) { 1110f54d1867SChris Wilson ret = dma_fence_wait(fence, true); 1111a8c21a54SThe etnaviv authors if (ret) 1112a8c21a54SThe etnaviv authors return ret; 1113a8c21a54SThe etnaviv authors } 1114a8c21a54SThe etnaviv authors } 1115a8c21a54SThe etnaviv authors 1116a8c21a54SThe etnaviv authors if (!exclusive || !fobj) 1117a8c21a54SThe etnaviv authors return 0; 1118a8c21a54SThe etnaviv authors 1119a8c21a54SThe etnaviv authors for (i = 0; i < fobj->shared_count; i++) { 1120a8c21a54SThe etnaviv authors fence = rcu_dereference_protected(fobj->shared[i], 1121a8c21a54SThe etnaviv authors reservation_object_held(robj)); 1122a8c21a54SThe etnaviv authors if (fence->context != context) { 1123f54d1867SChris Wilson ret = dma_fence_wait(fence, true); 1124a8c21a54SThe etnaviv authors if (ret) 1125a8c21a54SThe etnaviv authors return ret; 1126a8c21a54SThe etnaviv authors } 1127a8c21a54SThe etnaviv authors } 1128a8c21a54SThe etnaviv authors 1129a8c21a54SThe etnaviv authors return 0; 1130a8c21a54SThe etnaviv authors } 1131a8c21a54SThe etnaviv authors 1132a8c21a54SThe etnaviv authors /* 1133a8c21a54SThe etnaviv authors * event management: 1134a8c21a54SThe etnaviv authors */ 1135a8c21a54SThe etnaviv authors 113695a428c1SChristian Gmeiner static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 113795a428c1SChristian Gmeiner unsigned int *events) 1138a8c21a54SThe etnaviv authors { 113995a428c1SChristian Gmeiner unsigned long flags, timeout = msecs_to_jiffies(10 * 10000); 114095a428c1SChristian Gmeiner unsigned i, acquired = 0; 1141a8c21a54SThe etnaviv authors 114295a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 114395a428c1SChristian Gmeiner unsigned long ret; 114495a428c1SChristian Gmeiner 114595a428c1SChristian Gmeiner ret = wait_for_completion_timeout(&gpu->event_free, timeout); 114695a428c1SChristian Gmeiner 114795a428c1SChristian Gmeiner if (!ret) { 1148a8c21a54SThe etnaviv authors dev_err(gpu->dev, "wait_for_completion_timeout failed"); 114995a428c1SChristian Gmeiner goto out; 115095a428c1SChristian Gmeiner } 115195a428c1SChristian Gmeiner 115295a428c1SChristian Gmeiner acquired++; 115395a428c1SChristian Gmeiner timeout = ret; 115495a428c1SChristian Gmeiner } 1155a8c21a54SThe etnaviv authors 1156a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1157a8c21a54SThe etnaviv authors 115895a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 115995a428c1SChristian Gmeiner int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 116095a428c1SChristian Gmeiner 116195a428c1SChristian Gmeiner events[i] = event; 1162547d340dSChristian Gmeiner memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1163355502e0SChristian Gmeiner set_bit(event, gpu->event_bitmap); 1164a8c21a54SThe etnaviv authors } 1165a8c21a54SThe etnaviv authors 1166a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1167a8c21a54SThe etnaviv authors 116895a428c1SChristian Gmeiner return 0; 116995a428c1SChristian Gmeiner 117095a428c1SChristian Gmeiner out: 117195a428c1SChristian Gmeiner for (i = 0; i < acquired; i++) 117295a428c1SChristian Gmeiner complete(&gpu->event_free); 117395a428c1SChristian Gmeiner 117495a428c1SChristian Gmeiner return -EBUSY; 1175a8c21a54SThe etnaviv authors } 1176a8c21a54SThe etnaviv authors 1177a8c21a54SThe etnaviv authors static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1178a8c21a54SThe etnaviv authors { 1179a8c21a54SThe etnaviv authors unsigned long flags; 1180a8c21a54SThe etnaviv authors 1181a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1182a8c21a54SThe etnaviv authors 1183355502e0SChristian Gmeiner if (!test_bit(event, gpu->event_bitmap)) { 1184a8c21a54SThe etnaviv authors dev_warn(gpu->dev, "event %u is already marked as free", 1185a8c21a54SThe etnaviv authors event); 1186a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1187a8c21a54SThe etnaviv authors } else { 1188355502e0SChristian Gmeiner clear_bit(event, gpu->event_bitmap); 1189a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1190a8c21a54SThe etnaviv authors 1191a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1192a8c21a54SThe etnaviv authors } 1193a8c21a54SThe etnaviv authors } 1194a8c21a54SThe etnaviv authors 1195a8c21a54SThe etnaviv authors /* 1196a8c21a54SThe etnaviv authors * Cmdstream submission/retirement: 1197a8c21a54SThe etnaviv authors */ 1198a8c21a54SThe etnaviv authors 1199a8c21a54SThe etnaviv authors static void retire_worker(struct work_struct *work) 1200a8c21a54SThe etnaviv authors { 1201a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1202a8c21a54SThe etnaviv authors retire_work); 1203a8c21a54SThe etnaviv authors u32 fence = gpu->completed_fence; 1204a8c21a54SThe etnaviv authors struct etnaviv_cmdbuf *cmdbuf, *tmp; 1205a8c21a54SThe etnaviv authors unsigned int i; 1206a8c21a54SThe etnaviv authors 1207a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 1208a8c21a54SThe etnaviv authors list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { 1209f54d1867SChris Wilson if (!dma_fence_is_signaled(cmdbuf->fence)) 1210a8c21a54SThe etnaviv authors break; 1211a8c21a54SThe etnaviv authors 1212a8c21a54SThe etnaviv authors list_del(&cmdbuf->node); 1213f54d1867SChris Wilson dma_fence_put(cmdbuf->fence); 1214a8c21a54SThe etnaviv authors 1215a8c21a54SThe etnaviv authors for (i = 0; i < cmdbuf->nr_bos; i++) { 1216b6325f40SRussell King struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; 1217b6325f40SRussell King struct etnaviv_gem_object *etnaviv_obj = mapping->object; 1218a8c21a54SThe etnaviv authors 1219a8c21a54SThe etnaviv authors atomic_dec(&etnaviv_obj->gpu_active); 1220a8c21a54SThe etnaviv authors /* drop the refcount taken in etnaviv_gpu_submit */ 1221b6325f40SRussell King etnaviv_gem_mapping_unreference(mapping); 1222a8c21a54SThe etnaviv authors } 1223a8c21a54SThe etnaviv authors 1224ea1f5729SLucas Stach etnaviv_cmdbuf_free(cmdbuf); 1225d9fd0c7dSLucas Stach /* 1226d9fd0c7dSLucas Stach * We need to balance the runtime PM count caused by 1227d9fd0c7dSLucas Stach * each submission. Upon submission, we increment 1228d9fd0c7dSLucas Stach * the runtime PM counter, and allocate one event. 1229d9fd0c7dSLucas Stach * So here, we put the runtime PM count for each 1230d9fd0c7dSLucas Stach * completed event. 1231d9fd0c7dSLucas Stach */ 1232d9fd0c7dSLucas Stach pm_runtime_put_autosuspend(gpu->dev); 1233a8c21a54SThe etnaviv authors } 1234a8c21a54SThe etnaviv authors 1235a8c21a54SThe etnaviv authors gpu->retired_fence = fence; 1236a8c21a54SThe etnaviv authors 1237a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1238a8c21a54SThe etnaviv authors 1239a8c21a54SThe etnaviv authors wake_up_all(&gpu->fence_event); 1240a8c21a54SThe etnaviv authors } 1241a8c21a54SThe etnaviv authors 1242a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1243a8c21a54SThe etnaviv authors u32 fence, struct timespec *timeout) 1244a8c21a54SThe etnaviv authors { 1245a8c21a54SThe etnaviv authors int ret; 1246a8c21a54SThe etnaviv authors 1247a8c21a54SThe etnaviv authors if (fence_after(fence, gpu->next_fence)) { 1248a8c21a54SThe etnaviv authors DRM_ERROR("waiting on invalid fence: %u (of %u)\n", 1249a8c21a54SThe etnaviv authors fence, gpu->next_fence); 1250a8c21a54SThe etnaviv authors return -EINVAL; 1251a8c21a54SThe etnaviv authors } 1252a8c21a54SThe etnaviv authors 1253a8c21a54SThe etnaviv authors if (!timeout) { 1254a8c21a54SThe etnaviv authors /* No timeout was requested: just test for completion */ 1255a8c21a54SThe etnaviv authors ret = fence_completed(gpu, fence) ? 0 : -EBUSY; 1256a8c21a54SThe etnaviv authors } else { 1257a8c21a54SThe etnaviv authors unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1258a8c21a54SThe etnaviv authors 1259a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1260a8c21a54SThe etnaviv authors fence_completed(gpu, fence), 1261a8c21a54SThe etnaviv authors remaining); 1262a8c21a54SThe etnaviv authors if (ret == 0) { 1263a8c21a54SThe etnaviv authors DBG("timeout waiting for fence: %u (retired: %u completed: %u)", 1264a8c21a54SThe etnaviv authors fence, gpu->retired_fence, 1265a8c21a54SThe etnaviv authors gpu->completed_fence); 1266a8c21a54SThe etnaviv authors ret = -ETIMEDOUT; 1267a8c21a54SThe etnaviv authors } else if (ret != -ERESTARTSYS) { 1268a8c21a54SThe etnaviv authors ret = 0; 1269a8c21a54SThe etnaviv authors } 1270a8c21a54SThe etnaviv authors } 1271a8c21a54SThe etnaviv authors 1272a8c21a54SThe etnaviv authors return ret; 1273a8c21a54SThe etnaviv authors } 1274a8c21a54SThe etnaviv authors 1275a8c21a54SThe etnaviv authors /* 1276a8c21a54SThe etnaviv authors * Wait for an object to become inactive. This, on it's own, is not race 1277a8c21a54SThe etnaviv authors * free: the object is moved by the retire worker off the active list, and 1278a8c21a54SThe etnaviv authors * then the iova is put. Moreover, the object could be re-submitted just 1279a8c21a54SThe etnaviv authors * after we notice that it's become inactive. 1280a8c21a54SThe etnaviv authors * 1281a8c21a54SThe etnaviv authors * Although the retirement happens under the gpu lock, we don't want to hold 1282a8c21a54SThe etnaviv authors * that lock in this function while waiting. 1283a8c21a54SThe etnaviv authors */ 1284a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1285a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1286a8c21a54SThe etnaviv authors { 1287a8c21a54SThe etnaviv authors unsigned long remaining; 1288a8c21a54SThe etnaviv authors long ret; 1289a8c21a54SThe etnaviv authors 1290a8c21a54SThe etnaviv authors if (!timeout) 1291a8c21a54SThe etnaviv authors return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1292a8c21a54SThe etnaviv authors 1293a8c21a54SThe etnaviv authors remaining = etnaviv_timeout_to_jiffies(timeout); 1294a8c21a54SThe etnaviv authors 1295a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1296a8c21a54SThe etnaviv authors !is_active(etnaviv_obj), 1297a8c21a54SThe etnaviv authors remaining); 1298fa67ac84SLucas Stach if (ret > 0) 1299a8c21a54SThe etnaviv authors return 0; 1300fa67ac84SLucas Stach else if (ret == -ERESTARTSYS) 1301a8c21a54SThe etnaviv authors return -ERESTARTSYS; 1302fa67ac84SLucas Stach else 1303a8c21a54SThe etnaviv authors return -ETIMEDOUT; 1304a8c21a54SThe etnaviv authors } 1305a8c21a54SThe etnaviv authors 1306a8c21a54SThe etnaviv authors int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) 1307a8c21a54SThe etnaviv authors { 1308a8c21a54SThe etnaviv authors return pm_runtime_get_sync(gpu->dev); 1309a8c21a54SThe etnaviv authors } 1310a8c21a54SThe etnaviv authors 1311a8c21a54SThe etnaviv authors void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) 1312a8c21a54SThe etnaviv authors { 1313a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1314a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1315a8c21a54SThe etnaviv authors } 1316a8c21a54SThe etnaviv authors 131768dc0b29SChristian Gmeiner static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 131868dc0b29SChristian Gmeiner struct etnaviv_event *event, unsigned int flags) 131968dc0b29SChristian Gmeiner { 132068dc0b29SChristian Gmeiner const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf; 132168dc0b29SChristian Gmeiner unsigned int i; 132268dc0b29SChristian Gmeiner 132368dc0b29SChristian Gmeiner for (i = 0; i < cmdbuf->nr_pmrs; i++) { 132468dc0b29SChristian Gmeiner const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i; 132568dc0b29SChristian Gmeiner 132668dc0b29SChristian Gmeiner if (pmr->flags == flags) 132768dc0b29SChristian Gmeiner etnaviv_perfmon_process(gpu, pmr); 132868dc0b29SChristian Gmeiner } 132968dc0b29SChristian Gmeiner } 133068dc0b29SChristian Gmeiner 133168dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 133268dc0b29SChristian Gmeiner struct etnaviv_event *event) 133368dc0b29SChristian Gmeiner { 13342c8b0c5aSChristian Gmeiner u32 val; 13352c8b0c5aSChristian Gmeiner 13362c8b0c5aSChristian Gmeiner /* disable clock gating */ 13372c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 13382c8b0c5aSChristian Gmeiner val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 13392c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 13402c8b0c5aSChristian Gmeiner 134104a7d18dSChristian Gmeiner /* enable debug register */ 134204a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 134304a7d18dSChristian Gmeiner val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 134404a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 134504a7d18dSChristian Gmeiner 134668dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 134768dc0b29SChristian Gmeiner } 134868dc0b29SChristian Gmeiner 134968dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 135068dc0b29SChristian Gmeiner struct etnaviv_event *event) 135168dc0b29SChristian Gmeiner { 135268dc0b29SChristian Gmeiner const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf; 135368dc0b29SChristian Gmeiner unsigned int i; 13542c8b0c5aSChristian Gmeiner u32 val; 135568dc0b29SChristian Gmeiner 135668dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 135768dc0b29SChristian Gmeiner 135868dc0b29SChristian Gmeiner for (i = 0; i < cmdbuf->nr_pmrs; i++) { 135968dc0b29SChristian Gmeiner const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i; 136068dc0b29SChristian Gmeiner 136168dc0b29SChristian Gmeiner *pmr->bo_vma = pmr->sequence; 136268dc0b29SChristian Gmeiner } 13632c8b0c5aSChristian Gmeiner 136404a7d18dSChristian Gmeiner /* disable debug register */ 136504a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 136604a7d18dSChristian Gmeiner val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 136704a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 136804a7d18dSChristian Gmeiner 13692c8b0c5aSChristian Gmeiner /* enable clock gating */ 13702c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 13712c8b0c5aSChristian Gmeiner val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 13722c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 137368dc0b29SChristian Gmeiner } 137468dc0b29SChristian Gmeiner 137568dc0b29SChristian Gmeiner 1376a8c21a54SThe etnaviv authors /* add bo's to gpu's ring, and kick gpu: */ 1377a8c21a54SThe etnaviv authors int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 1378a8c21a54SThe etnaviv authors struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) 1379a8c21a54SThe etnaviv authors { 1380f54d1867SChris Wilson struct dma_fence *fence; 138168dc0b29SChristian Gmeiner unsigned int i, nr_events = 1, event[3]; 1382a8c21a54SThe etnaviv authors int ret; 1383a8c21a54SThe etnaviv authors 1384a8c21a54SThe etnaviv authors ret = etnaviv_gpu_pm_get_sync(gpu); 1385a8c21a54SThe etnaviv authors if (ret < 0) 1386a8c21a54SThe etnaviv authors return ret; 1387a8c21a54SThe etnaviv authors 1388a8c21a54SThe etnaviv authors /* 138968dc0b29SChristian Gmeiner * if there are performance monitor requests we need to have 139068dc0b29SChristian Gmeiner * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 139168dc0b29SChristian Gmeiner * requests. 139268dc0b29SChristian Gmeiner * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 139368dc0b29SChristian Gmeiner * and update the sequence number for userspace. 139468dc0b29SChristian Gmeiner */ 139568dc0b29SChristian Gmeiner if (cmdbuf->nr_pmrs) 139668dc0b29SChristian Gmeiner nr_events = 3; 139768dc0b29SChristian Gmeiner 139868dc0b29SChristian Gmeiner ret = event_alloc(gpu, nr_events, event); 139995a428c1SChristian Gmeiner if (ret) { 140068dc0b29SChristian Gmeiner DRM_ERROR("no free events\n"); 1401d9853490SLucas Stach goto out_pm_put; 1402a8c21a54SThe etnaviv authors } 1403a8c21a54SThe etnaviv authors 1404f3cd1b06SLucas Stach mutex_lock(&gpu->lock); 1405f3cd1b06SLucas Stach 1406a8c21a54SThe etnaviv authors fence = etnaviv_gpu_fence_alloc(gpu); 1407a8c21a54SThe etnaviv authors if (!fence) { 140868dc0b29SChristian Gmeiner for (i = 0; i < nr_events; i++) 140968dc0b29SChristian Gmeiner event_free(gpu, event[i]); 141068dc0b29SChristian Gmeiner 1411a8c21a54SThe etnaviv authors ret = -ENOMEM; 141245abdf35SWei Yongjun goto out_unlock; 1413a8c21a54SThe etnaviv authors } 1414a8c21a54SThe etnaviv authors 141568dc0b29SChristian Gmeiner gpu->event[event[0]].fence = fence; 14166e2b98cfSLucas Stach submit->fence = dma_fence_get(fence); 14176e2b98cfSLucas Stach gpu->active_fence = submit->fence->seqno; 1418a8c21a54SThe etnaviv authors 1419a8c21a54SThe etnaviv authors if (gpu->lastctx != cmdbuf->ctx) { 1420a8c21a54SThe etnaviv authors gpu->mmu->need_flush = true; 1421a8c21a54SThe etnaviv authors gpu->switch_context = true; 1422a8c21a54SThe etnaviv authors gpu->lastctx = cmdbuf->ctx; 1423a8c21a54SThe etnaviv authors } 1424a8c21a54SThe etnaviv authors 142568dc0b29SChristian Gmeiner if (cmdbuf->nr_pmrs) { 142668dc0b29SChristian Gmeiner gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 142768dc0b29SChristian Gmeiner gpu->event[event[1]].cmdbuf = cmdbuf; 142868dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[1]); 142968dc0b29SChristian Gmeiner } 143068dc0b29SChristian Gmeiner 143168dc0b29SChristian Gmeiner etnaviv_buffer_queue(gpu, event[0], cmdbuf); 143268dc0b29SChristian Gmeiner 143368dc0b29SChristian Gmeiner if (cmdbuf->nr_pmrs) { 143468dc0b29SChristian Gmeiner gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 143568dc0b29SChristian Gmeiner gpu->event[event[2]].cmdbuf = cmdbuf; 143668dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[2]); 143768dc0b29SChristian Gmeiner } 1438a8c21a54SThe etnaviv authors 1439a8c21a54SThe etnaviv authors cmdbuf->fence = fence; 1440a8c21a54SThe etnaviv authors list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); 1441a8c21a54SThe etnaviv authors 1442a8c21a54SThe etnaviv authors /* We're committed to adding this command buffer, hold a PM reference */ 1443a8c21a54SThe etnaviv authors pm_runtime_get_noresume(gpu->dev); 1444a8c21a54SThe etnaviv authors 1445a8c21a54SThe etnaviv authors for (i = 0; i < submit->nr_bos; i++) { 1446a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; 1447a8c21a54SThe etnaviv authors 1448b6325f40SRussell King /* Each cmdbuf takes a refcount on the mapping */ 1449b6325f40SRussell King etnaviv_gem_mapping_reference(submit->bos[i].mapping); 1450b6325f40SRussell King cmdbuf->bo_map[i] = submit->bos[i].mapping; 1451a8c21a54SThe etnaviv authors atomic_inc(&etnaviv_obj->gpu_active); 1452a8c21a54SThe etnaviv authors 1453a8c21a54SThe etnaviv authors if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) 1454a8c21a54SThe etnaviv authors reservation_object_add_excl_fence(etnaviv_obj->resv, 1455a8c21a54SThe etnaviv authors fence); 1456a8c21a54SThe etnaviv authors else 1457a8c21a54SThe etnaviv authors reservation_object_add_shared_fence(etnaviv_obj->resv, 1458a8c21a54SThe etnaviv authors fence); 1459a8c21a54SThe etnaviv authors } 1460a8c21a54SThe etnaviv authors cmdbuf->nr_bos = submit->nr_bos; 1461a8c21a54SThe etnaviv authors hangcheck_timer_reset(gpu); 1462a8c21a54SThe etnaviv authors ret = 0; 1463a8c21a54SThe etnaviv authors 146445abdf35SWei Yongjun out_unlock: 1465a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1466a8c21a54SThe etnaviv authors 1467d9853490SLucas Stach out_pm_put: 1468a8c21a54SThe etnaviv authors etnaviv_gpu_pm_put(gpu); 1469a8c21a54SThe etnaviv authors 1470a8c21a54SThe etnaviv authors return ret; 1471a8c21a54SThe etnaviv authors } 1472a8c21a54SThe etnaviv authors 1473357713ceSChristian Gmeiner static void sync_point_worker(struct work_struct *work) 1474357713ceSChristian Gmeiner { 1475357713ceSChristian Gmeiner struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1476357713ceSChristian Gmeiner sync_point_work); 1477b9a48aa7SLucas Stach struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1478b9a48aa7SLucas Stach u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1479357713ceSChristian Gmeiner 1480b9a48aa7SLucas Stach event->sync_point(gpu, event); 1481357713ceSChristian Gmeiner event_free(gpu, gpu->sync_point_event); 1482b9a48aa7SLucas Stach 1483b9a48aa7SLucas Stach /* restart FE last to avoid GPU and IRQ racing against this worker */ 1484b9a48aa7SLucas Stach etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1485357713ceSChristian Gmeiner } 1486357713ceSChristian Gmeiner 1487a8c21a54SThe etnaviv authors /* 1488a8c21a54SThe etnaviv authors * Init/Cleanup: 1489a8c21a54SThe etnaviv authors */ 1490a8c21a54SThe etnaviv authors static irqreturn_t irq_handler(int irq, void *data) 1491a8c21a54SThe etnaviv authors { 1492a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = data; 1493a8c21a54SThe etnaviv authors irqreturn_t ret = IRQ_NONE; 1494a8c21a54SThe etnaviv authors 1495a8c21a54SThe etnaviv authors u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1496a8c21a54SThe etnaviv authors 1497a8c21a54SThe etnaviv authors if (intr != 0) { 1498a8c21a54SThe etnaviv authors int event; 1499a8c21a54SThe etnaviv authors 1500a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1501a8c21a54SThe etnaviv authors 1502a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1503a8c21a54SThe etnaviv authors 1504a8c21a54SThe etnaviv authors if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1505a8c21a54SThe etnaviv authors dev_err(gpu->dev, "AXI bus error\n"); 1506a8c21a54SThe etnaviv authors intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1507a8c21a54SThe etnaviv authors } 1508a8c21a54SThe etnaviv authors 1509128a9b1dSLucas Stach if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1510128a9b1dSLucas Stach int i; 1511128a9b1dSLucas Stach 1512128a9b1dSLucas Stach dev_err_ratelimited(gpu->dev, 1513128a9b1dSLucas Stach "MMU fault status 0x%08x\n", 1514128a9b1dSLucas Stach gpu_read(gpu, VIVS_MMUv2_STATUS)); 1515128a9b1dSLucas Stach for (i = 0; i < 4; i++) { 1516128a9b1dSLucas Stach dev_err_ratelimited(gpu->dev, 1517128a9b1dSLucas Stach "MMU %d fault addr 0x%08x\n", 1518128a9b1dSLucas Stach i, gpu_read(gpu, 1519128a9b1dSLucas Stach VIVS_MMUv2_EXCEPTION_ADDR(i))); 1520128a9b1dSLucas Stach } 1521128a9b1dSLucas Stach intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1522128a9b1dSLucas Stach } 1523128a9b1dSLucas Stach 1524a8c21a54SThe etnaviv authors while ((event = ffs(intr)) != 0) { 1525f54d1867SChris Wilson struct dma_fence *fence; 1526a8c21a54SThe etnaviv authors 1527a8c21a54SThe etnaviv authors event -= 1; 1528a8c21a54SThe etnaviv authors 1529a8c21a54SThe etnaviv authors intr &= ~(1 << event); 1530a8c21a54SThe etnaviv authors 1531a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "event %u\n", event); 1532a8c21a54SThe etnaviv authors 1533357713ceSChristian Gmeiner if (gpu->event[event].sync_point) { 1534357713ceSChristian Gmeiner gpu->sync_point_event = event; 1535357713ceSChristian Gmeiner etnaviv_queue_work(gpu->drm, &gpu->sync_point_work); 1536357713ceSChristian Gmeiner } 1537357713ceSChristian Gmeiner 1538a8c21a54SThe etnaviv authors fence = gpu->event[event].fence; 153968dc0b29SChristian Gmeiner if (!fence) 154068dc0b29SChristian Gmeiner continue; 154168dc0b29SChristian Gmeiner 1542a8c21a54SThe etnaviv authors gpu->event[event].fence = NULL; 1543f54d1867SChris Wilson dma_fence_signal(fence); 1544a8c21a54SThe etnaviv authors 1545a8c21a54SThe etnaviv authors /* 1546a8c21a54SThe etnaviv authors * Events can be processed out of order. Eg, 1547a8c21a54SThe etnaviv authors * - allocate and queue event 0 1548a8c21a54SThe etnaviv authors * - allocate event 1 1549a8c21a54SThe etnaviv authors * - event 0 completes, we process it 1550a8c21a54SThe etnaviv authors * - allocate and queue event 0 1551a8c21a54SThe etnaviv authors * - event 1 and event 0 complete 1552a8c21a54SThe etnaviv authors * we can end up processing event 0 first, then 1. 1553a8c21a54SThe etnaviv authors */ 1554a8c21a54SThe etnaviv authors if (fence_after(fence->seqno, gpu->completed_fence)) 1555a8c21a54SThe etnaviv authors gpu->completed_fence = fence->seqno; 1556a8c21a54SThe etnaviv authors 1557a8c21a54SThe etnaviv authors event_free(gpu, event); 1558a8c21a54SThe etnaviv authors } 1559a8c21a54SThe etnaviv authors 1560a8c21a54SThe etnaviv authors /* Retire the buffer objects in a work */ 1561a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->retire_work); 1562a8c21a54SThe etnaviv authors 1563a8c21a54SThe etnaviv authors ret = IRQ_HANDLED; 1564a8c21a54SThe etnaviv authors } 1565a8c21a54SThe etnaviv authors 1566a8c21a54SThe etnaviv authors return ret; 1567a8c21a54SThe etnaviv authors } 1568a8c21a54SThe etnaviv authors 1569a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1570a8c21a54SThe etnaviv authors { 1571a8c21a54SThe etnaviv authors int ret; 1572a8c21a54SThe etnaviv authors 15739c7310c0SLucas Stach if (gpu->clk_bus) { 15749c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_bus); 1575a8c21a54SThe etnaviv authors if (ret) 1576a8c21a54SThe etnaviv authors return ret; 1577a8c21a54SThe etnaviv authors } 1578a8c21a54SThe etnaviv authors 15799c7310c0SLucas Stach if (gpu->clk_core) { 15809c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_core); 15819c7310c0SLucas Stach if (ret) 15829c7310c0SLucas Stach goto disable_clk_bus; 15839c7310c0SLucas Stach } 15849c7310c0SLucas Stach 15859c7310c0SLucas Stach if (gpu->clk_shader) { 15869c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_shader); 15879c7310c0SLucas Stach if (ret) 15889c7310c0SLucas Stach goto disable_clk_core; 15899c7310c0SLucas Stach } 15909c7310c0SLucas Stach 1591a8c21a54SThe etnaviv authors return 0; 15929c7310c0SLucas Stach 15939c7310c0SLucas Stach disable_clk_core: 15949c7310c0SLucas Stach if (gpu->clk_core) 15959c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 15969c7310c0SLucas Stach disable_clk_bus: 15979c7310c0SLucas Stach if (gpu->clk_bus) 15989c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 15999c7310c0SLucas Stach 16009c7310c0SLucas Stach return ret; 1601a8c21a54SThe etnaviv authors } 1602a8c21a54SThe etnaviv authors 1603a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1604a8c21a54SThe etnaviv authors { 16059c7310c0SLucas Stach if (gpu->clk_shader) 16069c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_shader); 16079c7310c0SLucas Stach if (gpu->clk_core) 16089c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 16099c7310c0SLucas Stach if (gpu->clk_bus) 16109c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 1611a8c21a54SThe etnaviv authors 1612a8c21a54SThe etnaviv authors return 0; 1613a8c21a54SThe etnaviv authors } 1614a8c21a54SThe etnaviv authors 1615b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1616b88163e3SLucas Stach { 1617b88163e3SLucas Stach unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1618b88163e3SLucas Stach 1619b88163e3SLucas Stach do { 1620b88163e3SLucas Stach u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1621b88163e3SLucas Stach 1622b88163e3SLucas Stach if ((idle & gpu->idle_mask) == gpu->idle_mask) 1623b88163e3SLucas Stach return 0; 1624b88163e3SLucas Stach 1625b88163e3SLucas Stach if (time_is_before_jiffies(timeout)) { 1626b88163e3SLucas Stach dev_warn(gpu->dev, 1627b88163e3SLucas Stach "timed out waiting for idle: idle=0x%x\n", 1628b88163e3SLucas Stach idle); 1629b88163e3SLucas Stach return -ETIMEDOUT; 1630b88163e3SLucas Stach } 1631b88163e3SLucas Stach 1632b88163e3SLucas Stach udelay(5); 1633b88163e3SLucas Stach } while (1); 1634b88163e3SLucas Stach } 1635b88163e3SLucas Stach 1636a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1637a8c21a54SThe etnaviv authors { 1638a8c21a54SThe etnaviv authors if (gpu->buffer) { 1639a8c21a54SThe etnaviv authors /* Replace the last WAIT with END */ 1640a8c21a54SThe etnaviv authors etnaviv_buffer_end(gpu); 1641a8c21a54SThe etnaviv authors 1642a8c21a54SThe etnaviv authors /* 1643a8c21a54SThe etnaviv authors * We know that only the FE is busy here, this should 1644a8c21a54SThe etnaviv authors * happen quickly (as the WAIT is only 200 cycles). If 1645a8c21a54SThe etnaviv authors * we fail, just warn and continue. 1646a8c21a54SThe etnaviv authors */ 1647b88163e3SLucas Stach etnaviv_gpu_wait_idle(gpu, 100); 1648a8c21a54SThe etnaviv authors } 1649a8c21a54SThe etnaviv authors 1650a8c21a54SThe etnaviv authors return etnaviv_gpu_clk_disable(gpu); 1651a8c21a54SThe etnaviv authors } 1652a8c21a54SThe etnaviv authors 1653a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1654a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1655a8c21a54SThe etnaviv authors { 1656a8c21a54SThe etnaviv authors int ret; 1657a8c21a54SThe etnaviv authors 1658a8c21a54SThe etnaviv authors ret = mutex_lock_killable(&gpu->lock); 1659a8c21a54SThe etnaviv authors if (ret) 1660a8c21a54SThe etnaviv authors return ret; 1661a8c21a54SThe etnaviv authors 1662bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1663a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1664a8c21a54SThe etnaviv authors 1665a8c21a54SThe etnaviv authors gpu->switch_context = true; 1666f6086311SRussell King gpu->exec_state = -1; 1667a8c21a54SThe etnaviv authors 1668a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1669a8c21a54SThe etnaviv authors 1670a8c21a54SThe etnaviv authors return 0; 1671a8c21a54SThe etnaviv authors } 1672a8c21a54SThe etnaviv authors #endif 1673a8c21a54SThe etnaviv authors 1674bcdfb5e5SRussell King static int 1675bcdfb5e5SRussell King etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1676bcdfb5e5SRussell King unsigned long *state) 1677bcdfb5e5SRussell King { 1678bcdfb5e5SRussell King *state = 6; 1679bcdfb5e5SRussell King 1680bcdfb5e5SRussell King return 0; 1681bcdfb5e5SRussell King } 1682bcdfb5e5SRussell King 1683bcdfb5e5SRussell King static int 1684bcdfb5e5SRussell King etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1685bcdfb5e5SRussell King unsigned long *state) 1686bcdfb5e5SRussell King { 1687bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1688bcdfb5e5SRussell King 1689bcdfb5e5SRussell King *state = gpu->freq_scale; 1690bcdfb5e5SRussell King 1691bcdfb5e5SRussell King return 0; 1692bcdfb5e5SRussell King } 1693bcdfb5e5SRussell King 1694bcdfb5e5SRussell King static int 1695bcdfb5e5SRussell King etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1696bcdfb5e5SRussell King unsigned long state) 1697bcdfb5e5SRussell King { 1698bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1699bcdfb5e5SRussell King 1700bcdfb5e5SRussell King mutex_lock(&gpu->lock); 1701bcdfb5e5SRussell King gpu->freq_scale = state; 1702bcdfb5e5SRussell King if (!pm_runtime_suspended(gpu->dev)) 1703bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1704bcdfb5e5SRussell King mutex_unlock(&gpu->lock); 1705bcdfb5e5SRussell King 1706bcdfb5e5SRussell King return 0; 1707bcdfb5e5SRussell King } 1708bcdfb5e5SRussell King 1709bcdfb5e5SRussell King static struct thermal_cooling_device_ops cooling_ops = { 1710bcdfb5e5SRussell King .get_max_state = etnaviv_gpu_cooling_get_max_state, 1711bcdfb5e5SRussell King .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1712bcdfb5e5SRussell King .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1713bcdfb5e5SRussell King }; 1714bcdfb5e5SRussell King 1715a8c21a54SThe etnaviv authors static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1716a8c21a54SThe etnaviv authors void *data) 1717a8c21a54SThe etnaviv authors { 1718a8c21a54SThe etnaviv authors struct drm_device *drm = data; 1719a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = drm->dev_private; 1720a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1721a8c21a54SThe etnaviv authors int ret; 1722a8c21a54SThe etnaviv authors 172349b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1724bcdfb5e5SRussell King gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1725bcdfb5e5SRussell King (char *)dev_name(dev), gpu, &cooling_ops); 1726bcdfb5e5SRussell King if (IS_ERR(gpu->cooling)) 1727bcdfb5e5SRussell King return PTR_ERR(gpu->cooling); 17285247e2aaSLucas Stach } 1729bcdfb5e5SRussell King 1730a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1731a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 1732a8c21a54SThe etnaviv authors #else 1733a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1734a8c21a54SThe etnaviv authors #endif 1735bcdfb5e5SRussell King if (ret < 0) { 173649b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1737bcdfb5e5SRussell King thermal_cooling_device_unregister(gpu->cooling); 1738a8c21a54SThe etnaviv authors return ret; 1739bcdfb5e5SRussell King } 1740a8c21a54SThe etnaviv authors 1741a8c21a54SThe etnaviv authors gpu->drm = drm; 1742f54d1867SChris Wilson gpu->fence_context = dma_fence_context_alloc(1); 1743a8c21a54SThe etnaviv authors spin_lock_init(&gpu->fence_spinlock); 1744a8c21a54SThe etnaviv authors 1745a8c21a54SThe etnaviv authors INIT_LIST_HEAD(&gpu->active_cmd_list); 1746a8c21a54SThe etnaviv authors INIT_WORK(&gpu->retire_work, retire_worker); 1747357713ceSChristian Gmeiner INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1748a8c21a54SThe etnaviv authors INIT_WORK(&gpu->recover_work, recover_worker); 1749a8c21a54SThe etnaviv authors init_waitqueue_head(&gpu->fence_event); 1750a8c21a54SThe etnaviv authors 175143b70524SKees Cook timer_setup(&gpu->hangcheck_timer, hangcheck_handler, TIMER_DEFERRABLE); 1752a8c21a54SThe etnaviv authors 1753a8c21a54SThe etnaviv authors priv->gpu[priv->num_gpus++] = gpu; 1754a8c21a54SThe etnaviv authors 1755a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1756a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1757a8c21a54SThe etnaviv authors 1758a8c21a54SThe etnaviv authors return 0; 1759a8c21a54SThe etnaviv authors } 1760a8c21a54SThe etnaviv authors 1761a8c21a54SThe etnaviv authors static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1762a8c21a54SThe etnaviv authors void *data) 1763a8c21a54SThe etnaviv authors { 1764a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1765a8c21a54SThe etnaviv authors 1766a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 1767a8c21a54SThe etnaviv authors 1768a8c21a54SThe etnaviv authors hangcheck_disable(gpu); 1769a8c21a54SThe etnaviv authors 1770a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1771a8c21a54SThe etnaviv authors pm_runtime_get_sync(gpu->dev); 1772a8c21a54SThe etnaviv authors pm_runtime_put_sync_suspend(gpu->dev); 1773a8c21a54SThe etnaviv authors #else 1774a8c21a54SThe etnaviv authors etnaviv_gpu_hw_suspend(gpu); 1775a8c21a54SThe etnaviv authors #endif 1776a8c21a54SThe etnaviv authors 1777a8c21a54SThe etnaviv authors if (gpu->buffer) { 1778ea1f5729SLucas Stach etnaviv_cmdbuf_free(gpu->buffer); 1779a8c21a54SThe etnaviv authors gpu->buffer = NULL; 1780a8c21a54SThe etnaviv authors } 1781a8c21a54SThe etnaviv authors 1782e66774ddSLucas Stach if (gpu->cmdbuf_suballoc) { 1783e66774ddSLucas Stach etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); 1784e66774ddSLucas Stach gpu->cmdbuf_suballoc = NULL; 1785e66774ddSLucas Stach } 1786e66774ddSLucas Stach 1787a8c21a54SThe etnaviv authors if (gpu->mmu) { 1788a8c21a54SThe etnaviv authors etnaviv_iommu_destroy(gpu->mmu); 1789a8c21a54SThe etnaviv authors gpu->mmu = NULL; 1790a8c21a54SThe etnaviv authors } 1791a8c21a54SThe etnaviv authors 1792a8c21a54SThe etnaviv authors gpu->drm = NULL; 1793bcdfb5e5SRussell King 179449b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1795bcdfb5e5SRussell King thermal_cooling_device_unregister(gpu->cooling); 1796bcdfb5e5SRussell King gpu->cooling = NULL; 1797a8c21a54SThe etnaviv authors } 1798a8c21a54SThe etnaviv authors 1799a8c21a54SThe etnaviv authors static const struct component_ops gpu_ops = { 1800a8c21a54SThe etnaviv authors .bind = etnaviv_gpu_bind, 1801a8c21a54SThe etnaviv authors .unbind = etnaviv_gpu_unbind, 1802a8c21a54SThe etnaviv authors }; 1803a8c21a54SThe etnaviv authors 1804a8c21a54SThe etnaviv authors static const struct of_device_id etnaviv_gpu_match[] = { 1805a8c21a54SThe etnaviv authors { 1806a8c21a54SThe etnaviv authors .compatible = "vivante,gc" 1807a8c21a54SThe etnaviv authors }, 1808a8c21a54SThe etnaviv authors { /* sentinel */ } 1809a8c21a54SThe etnaviv authors }; 1810a8c21a54SThe etnaviv authors 1811a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1812a8c21a54SThe etnaviv authors { 1813a8c21a54SThe etnaviv authors struct device *dev = &pdev->dev; 1814a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1815dc227890SFabio Estevam int err; 1816a8c21a54SThe etnaviv authors 1817a8c21a54SThe etnaviv authors gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1818a8c21a54SThe etnaviv authors if (!gpu) 1819a8c21a54SThe etnaviv authors return -ENOMEM; 1820a8c21a54SThe etnaviv authors 1821a8c21a54SThe etnaviv authors gpu->dev = &pdev->dev; 1822a8c21a54SThe etnaviv authors mutex_init(&gpu->lock); 1823a8c21a54SThe etnaviv authors 1824a8c21a54SThe etnaviv authors /* Map registers: */ 1825a8c21a54SThe etnaviv authors gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); 1826a8c21a54SThe etnaviv authors if (IS_ERR(gpu->mmio)) 1827a8c21a54SThe etnaviv authors return PTR_ERR(gpu->mmio); 1828a8c21a54SThe etnaviv authors 1829a8c21a54SThe etnaviv authors /* Get Interrupt: */ 1830a8c21a54SThe etnaviv authors gpu->irq = platform_get_irq(pdev, 0); 1831a8c21a54SThe etnaviv authors if (gpu->irq < 0) { 1832db60eda3SFabio Estevam dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1833db60eda3SFabio Estevam return gpu->irq; 1834a8c21a54SThe etnaviv authors } 1835a8c21a54SThe etnaviv authors 1836a8c21a54SThe etnaviv authors err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1837a8c21a54SThe etnaviv authors dev_name(gpu->dev), gpu); 1838a8c21a54SThe etnaviv authors if (err) { 1839a8c21a54SThe etnaviv authors dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1840db60eda3SFabio Estevam return err; 1841a8c21a54SThe etnaviv authors } 1842a8c21a54SThe etnaviv authors 1843a8c21a54SThe etnaviv authors /* Get Clocks: */ 1844a8c21a54SThe etnaviv authors gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1845a8c21a54SThe etnaviv authors DBG("clk_bus: %p", gpu->clk_bus); 1846a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_bus)) 1847a8c21a54SThe etnaviv authors gpu->clk_bus = NULL; 1848a8c21a54SThe etnaviv authors 1849a8c21a54SThe etnaviv authors gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1850a8c21a54SThe etnaviv authors DBG("clk_core: %p", gpu->clk_core); 1851a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_core)) 1852a8c21a54SThe etnaviv authors gpu->clk_core = NULL; 1853d79fd1ccSLucas Stach gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1854a8c21a54SThe etnaviv authors 1855a8c21a54SThe etnaviv authors gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1856a8c21a54SThe etnaviv authors DBG("clk_shader: %p", gpu->clk_shader); 1857a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_shader)) 1858a8c21a54SThe etnaviv authors gpu->clk_shader = NULL; 1859d79fd1ccSLucas Stach gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1860a8c21a54SThe etnaviv authors 1861a8c21a54SThe etnaviv authors /* TODO: figure out max mapped size */ 1862a8c21a54SThe etnaviv authors dev_set_drvdata(dev, gpu); 1863a8c21a54SThe etnaviv authors 1864a8c21a54SThe etnaviv authors /* 1865a8c21a54SThe etnaviv authors * We treat the device as initially suspended. The runtime PM 1866a8c21a54SThe etnaviv authors * autosuspend delay is rather arbitary: no measurements have 1867a8c21a54SThe etnaviv authors * yet been performed to determine an appropriate value. 1868a8c21a54SThe etnaviv authors */ 1869a8c21a54SThe etnaviv authors pm_runtime_use_autosuspend(gpu->dev); 1870a8c21a54SThe etnaviv authors pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1871a8c21a54SThe etnaviv authors pm_runtime_enable(gpu->dev); 1872a8c21a54SThe etnaviv authors 1873a8c21a54SThe etnaviv authors err = component_add(&pdev->dev, &gpu_ops); 1874a8c21a54SThe etnaviv authors if (err < 0) { 1875a8c21a54SThe etnaviv authors dev_err(&pdev->dev, "failed to register component: %d\n", err); 1876db60eda3SFabio Estevam return err; 1877a8c21a54SThe etnaviv authors } 1878a8c21a54SThe etnaviv authors 1879a8c21a54SThe etnaviv authors return 0; 1880a8c21a54SThe etnaviv authors } 1881a8c21a54SThe etnaviv authors 1882a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1883a8c21a54SThe etnaviv authors { 1884a8c21a54SThe etnaviv authors component_del(&pdev->dev, &gpu_ops); 1885a8c21a54SThe etnaviv authors pm_runtime_disable(&pdev->dev); 1886a8c21a54SThe etnaviv authors return 0; 1887a8c21a54SThe etnaviv authors } 1888a8c21a54SThe etnaviv authors 1889a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1890a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_suspend(struct device *dev) 1891a8c21a54SThe etnaviv authors { 1892a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1893a8c21a54SThe etnaviv authors u32 idle, mask; 1894a8c21a54SThe etnaviv authors 1895a8c21a54SThe etnaviv authors /* If we have outstanding fences, we're not idle */ 1896a8c21a54SThe etnaviv authors if (gpu->completed_fence != gpu->active_fence) 1897a8c21a54SThe etnaviv authors return -EBUSY; 1898a8c21a54SThe etnaviv authors 1899a8c21a54SThe etnaviv authors /* Check whether the hardware (except FE) is idle */ 1900a8c21a54SThe etnaviv authors mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1901a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1902a8c21a54SThe etnaviv authors if (idle != mask) 1903a8c21a54SThe etnaviv authors return -EBUSY; 1904a8c21a54SThe etnaviv authors 1905a8c21a54SThe etnaviv authors return etnaviv_gpu_hw_suspend(gpu); 1906a8c21a54SThe etnaviv authors } 1907a8c21a54SThe etnaviv authors 1908a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_resume(struct device *dev) 1909a8c21a54SThe etnaviv authors { 1910a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1911a8c21a54SThe etnaviv authors int ret; 1912a8c21a54SThe etnaviv authors 1913a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1914a8c21a54SThe etnaviv authors if (ret) 1915a8c21a54SThe etnaviv authors return ret; 1916a8c21a54SThe etnaviv authors 1917a8c21a54SThe etnaviv authors /* Re-initialise the basic hardware state */ 1918a8c21a54SThe etnaviv authors if (gpu->drm && gpu->buffer) { 1919a8c21a54SThe etnaviv authors ret = etnaviv_gpu_hw_resume(gpu); 1920a8c21a54SThe etnaviv authors if (ret) { 1921a8c21a54SThe etnaviv authors etnaviv_gpu_clk_disable(gpu); 1922a8c21a54SThe etnaviv authors return ret; 1923a8c21a54SThe etnaviv authors } 1924a8c21a54SThe etnaviv authors } 1925a8c21a54SThe etnaviv authors 1926a8c21a54SThe etnaviv authors return 0; 1927a8c21a54SThe etnaviv authors } 1928a8c21a54SThe etnaviv authors #endif 1929a8c21a54SThe etnaviv authors 1930a8c21a54SThe etnaviv authors static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1931a8c21a54SThe etnaviv authors SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1932a8c21a54SThe etnaviv authors NULL) 1933a8c21a54SThe etnaviv authors }; 1934a8c21a54SThe etnaviv authors 1935a8c21a54SThe etnaviv authors struct platform_driver etnaviv_gpu_driver = { 1936a8c21a54SThe etnaviv authors .driver = { 1937a8c21a54SThe etnaviv authors .name = "etnaviv-gpu", 1938a8c21a54SThe etnaviv authors .owner = THIS_MODULE, 1939a8c21a54SThe etnaviv authors .pm = &etnaviv_gpu_pm_ops, 1940a8c21a54SThe etnaviv authors .of_match_table = etnaviv_gpu_match, 1941a8c21a54SThe etnaviv authors }, 1942a8c21a54SThe etnaviv authors .probe = etnaviv_gpu_platform_probe, 1943a8c21a54SThe etnaviv authors .remove = etnaviv_gpu_platform_remove, 1944a8c21a54SThe etnaviv authors .id_table = gpu_ids, 1945a8c21a54SThe etnaviv authors }; 1946