1a8c21a54SThe etnaviv authors /* 2a8c21a54SThe etnaviv authors * Copyright (C) 2015 Etnaviv Project 3a8c21a54SThe etnaviv authors * 4a8c21a54SThe etnaviv authors * This program is free software; you can redistribute it and/or modify it 5a8c21a54SThe etnaviv authors * under the terms of the GNU General Public License version 2 as published by 6a8c21a54SThe etnaviv authors * the Free Software Foundation. 7a8c21a54SThe etnaviv authors * 8a8c21a54SThe etnaviv authors * This program is distributed in the hope that it will be useful, but WITHOUT 9a8c21a54SThe etnaviv authors * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10a8c21a54SThe etnaviv authors * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11a8c21a54SThe etnaviv authors * more details. 12a8c21a54SThe etnaviv authors * 13a8c21a54SThe etnaviv authors * You should have received a copy of the GNU General Public License along with 14a8c21a54SThe etnaviv authors * this program. If not, see <http://www.gnu.org/licenses/>. 15a8c21a54SThe etnaviv authors */ 16a8c21a54SThe etnaviv authors 17a8c21a54SThe etnaviv authors #include <linux/component.h> 18a8c21a54SThe etnaviv authors #include <linux/fence.h> 19a8c21a54SThe etnaviv authors #include <linux/moduleparam.h> 20a8c21a54SThe etnaviv authors #include <linux/of_device.h> 21a8c21a54SThe etnaviv authors #include "etnaviv_dump.h" 22a8c21a54SThe etnaviv authors #include "etnaviv_gpu.h" 23a8c21a54SThe etnaviv authors #include "etnaviv_gem.h" 24a8c21a54SThe etnaviv authors #include "etnaviv_mmu.h" 25a8c21a54SThe etnaviv authors #include "common.xml.h" 26a8c21a54SThe etnaviv authors #include "state.xml.h" 27a8c21a54SThe etnaviv authors #include "state_hi.xml.h" 28a8c21a54SThe etnaviv authors #include "cmdstream.xml.h" 29a8c21a54SThe etnaviv authors 30a8c21a54SThe etnaviv authors static const struct platform_device_id gpu_ids[] = { 31a8c21a54SThe etnaviv authors { .name = "etnaviv-gpu,2d" }, 32a8c21a54SThe etnaviv authors { }, 33a8c21a54SThe etnaviv authors }; 34a8c21a54SThe etnaviv authors 35a8c21a54SThe etnaviv authors static bool etnaviv_dump_core = true; 36a8c21a54SThe etnaviv authors module_param_named(dump_core, etnaviv_dump_core, bool, 0600); 37a8c21a54SThe etnaviv authors 38a8c21a54SThe etnaviv authors /* 39a8c21a54SThe etnaviv authors * Driver functions: 40a8c21a54SThe etnaviv authors */ 41a8c21a54SThe etnaviv authors 42a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 43a8c21a54SThe etnaviv authors { 44a8c21a54SThe etnaviv authors switch (param) { 45a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_MODEL: 46a8c21a54SThe etnaviv authors *value = gpu->identity.model; 47a8c21a54SThe etnaviv authors break; 48a8c21a54SThe etnaviv authors 49a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REVISION: 50a8c21a54SThe etnaviv authors *value = gpu->identity.revision; 51a8c21a54SThe etnaviv authors break; 52a8c21a54SThe etnaviv authors 53a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_0: 54a8c21a54SThe etnaviv authors *value = gpu->identity.features; 55a8c21a54SThe etnaviv authors break; 56a8c21a54SThe etnaviv authors 57a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_1: 58a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features0; 59a8c21a54SThe etnaviv authors break; 60a8c21a54SThe etnaviv authors 61a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_2: 62a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features1; 63a8c21a54SThe etnaviv authors break; 64a8c21a54SThe etnaviv authors 65a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_3: 66a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features2; 67a8c21a54SThe etnaviv authors break; 68a8c21a54SThe etnaviv authors 69a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_4: 70a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features3; 71a8c21a54SThe etnaviv authors break; 72a8c21a54SThe etnaviv authors 73602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_5: 74602eb489SRussell King *value = gpu->identity.minor_features4; 75602eb489SRussell King break; 76602eb489SRussell King 77602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_6: 78602eb489SRussell King *value = gpu->identity.minor_features5; 79602eb489SRussell King break; 80602eb489SRussell King 81a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_STREAM_COUNT: 82a8c21a54SThe etnaviv authors *value = gpu->identity.stream_count; 83a8c21a54SThe etnaviv authors break; 84a8c21a54SThe etnaviv authors 85a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REGISTER_MAX: 86a8c21a54SThe etnaviv authors *value = gpu->identity.register_max; 87a8c21a54SThe etnaviv authors break; 88a8c21a54SThe etnaviv authors 89a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_THREAD_COUNT: 90a8c21a54SThe etnaviv authors *value = gpu->identity.thread_count; 91a8c21a54SThe etnaviv authors break; 92a8c21a54SThe etnaviv authors 93a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 94a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_cache_size; 95a8c21a54SThe etnaviv authors break; 96a8c21a54SThe etnaviv authors 97a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 98a8c21a54SThe etnaviv authors *value = gpu->identity.shader_core_count; 99a8c21a54SThe etnaviv authors break; 100a8c21a54SThe etnaviv authors 101a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 102a8c21a54SThe etnaviv authors *value = gpu->identity.pixel_pipes; 103a8c21a54SThe etnaviv authors break; 104a8c21a54SThe etnaviv authors 105a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 106a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_output_buffer_size; 107a8c21a54SThe etnaviv authors break; 108a8c21a54SThe etnaviv authors 109a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 110a8c21a54SThe etnaviv authors *value = gpu->identity.buffer_size; 111a8c21a54SThe etnaviv authors break; 112a8c21a54SThe etnaviv authors 113a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 114a8c21a54SThe etnaviv authors *value = gpu->identity.instruction_count; 115a8c21a54SThe etnaviv authors break; 116a8c21a54SThe etnaviv authors 117a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 118a8c21a54SThe etnaviv authors *value = gpu->identity.num_constants; 119a8c21a54SThe etnaviv authors break; 120a8c21a54SThe etnaviv authors 121602eb489SRussell King case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 122602eb489SRussell King *value = gpu->identity.varyings_count; 123602eb489SRussell King break; 124602eb489SRussell King 125a8c21a54SThe etnaviv authors default: 126a8c21a54SThe etnaviv authors DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 127a8c21a54SThe etnaviv authors return -EINVAL; 128a8c21a54SThe etnaviv authors } 129a8c21a54SThe etnaviv authors 130a8c21a54SThe etnaviv authors return 0; 131a8c21a54SThe etnaviv authors } 132a8c21a54SThe etnaviv authors 133472f79dcSRussell King 134472f79dcSRussell King #define etnaviv_is_model_rev(gpu, mod, rev) \ 135472f79dcSRussell King ((gpu)->identity.model == chipModel_##mod && \ 136472f79dcSRussell King (gpu)->identity.revision == rev) 13752f36ba1SRussell King #define etnaviv_field(val, field) \ 13852f36ba1SRussell King (((val) & field##__MASK) >> field##__SHIFT) 13952f36ba1SRussell King 140a8c21a54SThe etnaviv authors static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 141a8c21a54SThe etnaviv authors { 142a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 143a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 144602eb489SRussell King u32 specs[4]; 145602eb489SRussell King unsigned int streams; 146a8c21a54SThe etnaviv authors 147a8c21a54SThe etnaviv authors specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 148a8c21a54SThe etnaviv authors specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 149602eb489SRussell King specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 150602eb489SRussell King specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 151a8c21a54SThe etnaviv authors 15252f36ba1SRussell King gpu->identity.stream_count = etnaviv_field(specs[0], 15352f36ba1SRussell King VIVS_HI_CHIP_SPECS_STREAM_COUNT); 15452f36ba1SRussell King gpu->identity.register_max = etnaviv_field(specs[0], 15552f36ba1SRussell King VIVS_HI_CHIP_SPECS_REGISTER_MAX); 15652f36ba1SRussell King gpu->identity.thread_count = etnaviv_field(specs[0], 15752f36ba1SRussell King VIVS_HI_CHIP_SPECS_THREAD_COUNT); 15852f36ba1SRussell King gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 15952f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 16052f36ba1SRussell King gpu->identity.shader_core_count = etnaviv_field(specs[0], 16152f36ba1SRussell King VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 16252f36ba1SRussell King gpu->identity.pixel_pipes = etnaviv_field(specs[0], 16352f36ba1SRussell King VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 164a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 16552f36ba1SRussell King etnaviv_field(specs[0], 16652f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 167a8c21a54SThe etnaviv authors 16852f36ba1SRussell King gpu->identity.buffer_size = etnaviv_field(specs[1], 16952f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 17052f36ba1SRussell King gpu->identity.instruction_count = etnaviv_field(specs[1], 17152f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 17252f36ba1SRussell King gpu->identity.num_constants = etnaviv_field(specs[1], 17352f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 174602eb489SRussell King 175602eb489SRussell King gpu->identity.varyings_count = etnaviv_field(specs[2], 176602eb489SRussell King VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 177602eb489SRussell King 178602eb489SRussell King /* This overrides the value from older register if non-zero */ 179602eb489SRussell King streams = etnaviv_field(specs[3], 180602eb489SRussell King VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 181602eb489SRussell King if (streams) 182602eb489SRussell King gpu->identity.stream_count = streams; 183a8c21a54SThe etnaviv authors } 184a8c21a54SThe etnaviv authors 185a8c21a54SThe etnaviv authors /* Fill in the stream count if not specified */ 186a8c21a54SThe etnaviv authors if (gpu->identity.stream_count == 0) { 187a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 188a8c21a54SThe etnaviv authors gpu->identity.stream_count = 4; 189a8c21a54SThe etnaviv authors else 190a8c21a54SThe etnaviv authors gpu->identity.stream_count = 1; 191a8c21a54SThe etnaviv authors } 192a8c21a54SThe etnaviv authors 193a8c21a54SThe etnaviv authors /* Convert the register max value */ 194a8c21a54SThe etnaviv authors if (gpu->identity.register_max) 195a8c21a54SThe etnaviv authors gpu->identity.register_max = 1 << gpu->identity.register_max; 196507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 197a8c21a54SThe etnaviv authors gpu->identity.register_max = 32; 198a8c21a54SThe etnaviv authors else 199a8c21a54SThe etnaviv authors gpu->identity.register_max = 64; 200a8c21a54SThe etnaviv authors 201a8c21a54SThe etnaviv authors /* Convert thread count */ 202a8c21a54SThe etnaviv authors if (gpu->identity.thread_count) 203a8c21a54SThe etnaviv authors gpu->identity.thread_count = 1 << gpu->identity.thread_count; 204507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 205a8c21a54SThe etnaviv authors gpu->identity.thread_count = 64; 206507f8991SRussell King else if (gpu->identity.model == chipModel_GC500 || 207507f8991SRussell King gpu->identity.model == chipModel_GC530) 208a8c21a54SThe etnaviv authors gpu->identity.thread_count = 128; 209a8c21a54SThe etnaviv authors else 210a8c21a54SThe etnaviv authors gpu->identity.thread_count = 256; 211a8c21a54SThe etnaviv authors 212a8c21a54SThe etnaviv authors if (gpu->identity.vertex_cache_size == 0) 213a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size = 8; 214a8c21a54SThe etnaviv authors 215a8c21a54SThe etnaviv authors if (gpu->identity.shader_core_count == 0) { 216a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 217a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 2; 218a8c21a54SThe etnaviv authors else 219a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 1; 220a8c21a54SThe etnaviv authors } 221a8c21a54SThe etnaviv authors 222a8c21a54SThe etnaviv authors if (gpu->identity.pixel_pipes == 0) 223a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes = 1; 224a8c21a54SThe etnaviv authors 225a8c21a54SThe etnaviv authors /* Convert virtex buffer size */ 226a8c21a54SThe etnaviv authors if (gpu->identity.vertex_output_buffer_size) { 227a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 228a8c21a54SThe etnaviv authors 1 << gpu->identity.vertex_output_buffer_size; 229507f8991SRussell King } else if (gpu->identity.model == chipModel_GC400) { 230a8c21a54SThe etnaviv authors if (gpu->identity.revision < 0x4000) 231a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 232a8c21a54SThe etnaviv authors else if (gpu->identity.revision < 0x4200) 233a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 256; 234a8c21a54SThe etnaviv authors else 235a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 128; 236a8c21a54SThe etnaviv authors } else { 237a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 238a8c21a54SThe etnaviv authors } 239a8c21a54SThe etnaviv authors 240a8c21a54SThe etnaviv authors switch (gpu->identity.instruction_count) { 241a8c21a54SThe etnaviv authors case 0: 242472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 243507f8991SRussell King gpu->identity.model == chipModel_GC880) 244a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 512; 245a8c21a54SThe etnaviv authors else 246a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 247a8c21a54SThe etnaviv authors break; 248a8c21a54SThe etnaviv authors 249a8c21a54SThe etnaviv authors case 1: 250a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 1024; 251a8c21a54SThe etnaviv authors break; 252a8c21a54SThe etnaviv authors 253a8c21a54SThe etnaviv authors case 2: 254a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 2048; 255a8c21a54SThe etnaviv authors break; 256a8c21a54SThe etnaviv authors 257a8c21a54SThe etnaviv authors default: 258a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 259a8c21a54SThe etnaviv authors break; 260a8c21a54SThe etnaviv authors } 261a8c21a54SThe etnaviv authors 262a8c21a54SThe etnaviv authors if (gpu->identity.num_constants == 0) 263a8c21a54SThe etnaviv authors gpu->identity.num_constants = 168; 264602eb489SRussell King 265602eb489SRussell King if (gpu->identity.varyings_count == 0) { 266602eb489SRussell King if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 267602eb489SRussell King gpu->identity.varyings_count = 12; 268602eb489SRussell King else 269602eb489SRussell King gpu->identity.varyings_count = 8; 270602eb489SRussell King } 271602eb489SRussell King 272602eb489SRussell King /* 273602eb489SRussell King * For some cores, two varyings are consumed for position, so the 274602eb489SRussell King * maximum varying count needs to be reduced by one. 275602eb489SRussell King */ 276602eb489SRussell King if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 277602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 278602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 279602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 280602eb489SRussell King etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 281602eb489SRussell King etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 282602eb489SRussell King etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 283602eb489SRussell King etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 284602eb489SRussell King etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 285602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5107) || 286602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5106)) 287602eb489SRussell King gpu->identity.varyings_count -= 1; 288a8c21a54SThe etnaviv authors } 289a8c21a54SThe etnaviv authors 290a8c21a54SThe etnaviv authors static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 291a8c21a54SThe etnaviv authors { 292a8c21a54SThe etnaviv authors u32 chipIdentity; 293a8c21a54SThe etnaviv authors 294a8c21a54SThe etnaviv authors chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 295a8c21a54SThe etnaviv authors 296a8c21a54SThe etnaviv authors /* Special case for older graphic cores. */ 29752f36ba1SRussell King if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 298507f8991SRussell King gpu->identity.model = chipModel_GC500; 29952f36ba1SRussell King gpu->identity.revision = etnaviv_field(chipIdentity, 30052f36ba1SRussell King VIVS_HI_CHIP_IDENTITY_REVISION); 301a8c21a54SThe etnaviv authors } else { 302a8c21a54SThe etnaviv authors 303a8c21a54SThe etnaviv authors gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 304a8c21a54SThe etnaviv authors gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 305a8c21a54SThe etnaviv authors 306a8c21a54SThe etnaviv authors /* 307a8c21a54SThe etnaviv authors * !!!! HACK ALERT !!!! 308a8c21a54SThe etnaviv authors * Because people change device IDs without letting software 309a8c21a54SThe etnaviv authors * know about it - here is the hack to make it all look the 310a8c21a54SThe etnaviv authors * same. Only for GC400 family. 311a8c21a54SThe etnaviv authors */ 312a8c21a54SThe etnaviv authors if ((gpu->identity.model & 0xff00) == 0x0400 && 313507f8991SRussell King gpu->identity.model != chipModel_GC420) { 314a8c21a54SThe etnaviv authors gpu->identity.model = gpu->identity.model & 0x0400; 315a8c21a54SThe etnaviv authors } 316a8c21a54SThe etnaviv authors 317a8c21a54SThe etnaviv authors /* Another special case */ 318472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 319a8c21a54SThe etnaviv authors u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 320a8c21a54SThe etnaviv authors u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 321a8c21a54SThe etnaviv authors 322a8c21a54SThe etnaviv authors if (chipDate == 0x20080814 && chipTime == 0x12051100) { 323a8c21a54SThe etnaviv authors /* 324a8c21a54SThe etnaviv authors * This IP has an ECO; put the correct 325a8c21a54SThe etnaviv authors * revision in it. 326a8c21a54SThe etnaviv authors */ 327a8c21a54SThe etnaviv authors gpu->identity.revision = 0x1051; 328a8c21a54SThe etnaviv authors } 329a8c21a54SThe etnaviv authors } 330a8c21a54SThe etnaviv authors } 331a8c21a54SThe etnaviv authors 332a8c21a54SThe etnaviv authors dev_info(gpu->dev, "model: GC%x, revision: %x\n", 333a8c21a54SThe etnaviv authors gpu->identity.model, gpu->identity.revision); 334a8c21a54SThe etnaviv authors 335a8c21a54SThe etnaviv authors gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 336a8c21a54SThe etnaviv authors 337a8c21a54SThe etnaviv authors /* Disable fast clear on GC700. */ 338507f8991SRussell King if (gpu->identity.model == chipModel_GC700) 339a8c21a54SThe etnaviv authors gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 340a8c21a54SThe etnaviv authors 341507f8991SRussell King if ((gpu->identity.model == chipModel_GC500 && 342507f8991SRussell King gpu->identity.revision < 2) || 343507f8991SRussell King (gpu->identity.model == chipModel_GC300 && 344507f8991SRussell King gpu->identity.revision < 0x2000)) { 345a8c21a54SThe etnaviv authors 346a8c21a54SThe etnaviv authors /* 347a8c21a54SThe etnaviv authors * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 348a8c21a54SThe etnaviv authors * registers. 349a8c21a54SThe etnaviv authors */ 350a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 0; 351a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 0; 352a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 0; 353a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 0; 354602eb489SRussell King gpu->identity.minor_features4 = 0; 355602eb489SRussell King gpu->identity.minor_features5 = 0; 356a8c21a54SThe etnaviv authors } else 357a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 358a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 359a8c21a54SThe etnaviv authors 360a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 361a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 362a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 363a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 364a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 365a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 366a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 367a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 368602eb489SRussell King gpu->identity.minor_features4 = 369602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 370602eb489SRussell King gpu->identity.minor_features5 = 371602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 372a8c21a54SThe etnaviv authors } 373a8c21a54SThe etnaviv authors 374a8c21a54SThe etnaviv authors /* GC600 idle register reports zero bits where modules aren't present */ 375a8c21a54SThe etnaviv authors if (gpu->identity.model == chipModel_GC600) { 376a8c21a54SThe etnaviv authors gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 377a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_RA | 378a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SE | 379a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PA | 380a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SH | 381a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PE | 382a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_DE | 383a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_FE; 384a8c21a54SThe etnaviv authors } else { 385a8c21a54SThe etnaviv authors gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 386a8c21a54SThe etnaviv authors } 387a8c21a54SThe etnaviv authors 388a8c21a54SThe etnaviv authors etnaviv_hw_specs(gpu); 389a8c21a54SThe etnaviv authors } 390a8c21a54SThe etnaviv authors 391a8c21a54SThe etnaviv authors static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 392a8c21a54SThe etnaviv authors { 393a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 394a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 395a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 396a8c21a54SThe etnaviv authors } 397a8c21a54SThe etnaviv authors 398a8c21a54SThe etnaviv authors static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 399a8c21a54SThe etnaviv authors { 400a8c21a54SThe etnaviv authors u32 control, idle; 401a8c21a54SThe etnaviv authors unsigned long timeout; 402a8c21a54SThe etnaviv authors bool failed = true; 403a8c21a54SThe etnaviv authors 404a8c21a54SThe etnaviv authors /* TODO 405a8c21a54SThe etnaviv authors * 406a8c21a54SThe etnaviv authors * - clock gating 407a8c21a54SThe etnaviv authors * - puls eater 408a8c21a54SThe etnaviv authors * - what about VG? 409a8c21a54SThe etnaviv authors */ 410a8c21a54SThe etnaviv authors 411a8c21a54SThe etnaviv authors /* We hope that the GPU resets in under one second */ 412a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(1000); 413a8c21a54SThe etnaviv authors 414a8c21a54SThe etnaviv authors while (time_is_after_jiffies(timeout)) { 415a8c21a54SThe etnaviv authors control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 416a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 417a8c21a54SThe etnaviv authors 418a8c21a54SThe etnaviv authors /* enable clock */ 419a8c21a54SThe etnaviv authors etnaviv_gpu_load_clock(gpu, control); 420a8c21a54SThe etnaviv authors 421a8c21a54SThe etnaviv authors /* Wait for stable clock. Vivante's code waited for 1ms */ 422a8c21a54SThe etnaviv authors usleep_range(1000, 10000); 423a8c21a54SThe etnaviv authors 424a8c21a54SThe etnaviv authors /* isolate the GPU. */ 425a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 426a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 427a8c21a54SThe etnaviv authors 428a8c21a54SThe etnaviv authors /* set soft reset. */ 429a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 430a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 431a8c21a54SThe etnaviv authors 432a8c21a54SThe etnaviv authors /* wait for reset. */ 433a8c21a54SThe etnaviv authors msleep(1); 434a8c21a54SThe etnaviv authors 435a8c21a54SThe etnaviv authors /* reset soft reset bit. */ 436a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 437a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 438a8c21a54SThe etnaviv authors 439a8c21a54SThe etnaviv authors /* reset GPU isolation. */ 440a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 441a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 442a8c21a54SThe etnaviv authors 443a8c21a54SThe etnaviv authors /* read idle register. */ 444a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 445a8c21a54SThe etnaviv authors 446a8c21a54SThe etnaviv authors /* try reseting again if FE it not idle */ 447a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 448a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "FE is not idle\n"); 449a8c21a54SThe etnaviv authors continue; 450a8c21a54SThe etnaviv authors } 451a8c21a54SThe etnaviv authors 452a8c21a54SThe etnaviv authors /* read reset register. */ 453a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 454a8c21a54SThe etnaviv authors 455a8c21a54SThe etnaviv authors /* is the GPU idle? */ 456a8c21a54SThe etnaviv authors if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 457a8c21a54SThe etnaviv authors ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 458a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "GPU is not idle\n"); 459a8c21a54SThe etnaviv authors continue; 460a8c21a54SThe etnaviv authors } 461a8c21a54SThe etnaviv authors 462a8c21a54SThe etnaviv authors failed = false; 463a8c21a54SThe etnaviv authors break; 464a8c21a54SThe etnaviv authors } 465a8c21a54SThe etnaviv authors 466a8c21a54SThe etnaviv authors if (failed) { 467a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 468a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 469a8c21a54SThe etnaviv authors 470a8c21a54SThe etnaviv authors dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 471a8c21a54SThe etnaviv authors idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 472a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 473a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 474a8c21a54SThe etnaviv authors 475a8c21a54SThe etnaviv authors return -EBUSY; 476a8c21a54SThe etnaviv authors } 477a8c21a54SThe etnaviv authors 478a8c21a54SThe etnaviv authors /* We rely on the GPU running, so program the clock */ 479a8c21a54SThe etnaviv authors control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 480a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 481a8c21a54SThe etnaviv authors 482a8c21a54SThe etnaviv authors /* enable clock */ 483a8c21a54SThe etnaviv authors etnaviv_gpu_load_clock(gpu, control); 484a8c21a54SThe etnaviv authors 485a8c21a54SThe etnaviv authors return 0; 486a8c21a54SThe etnaviv authors } 487a8c21a54SThe etnaviv authors 4887d0c6e71SRussell King static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 4897d0c6e71SRussell King { 4907d0c6e71SRussell King u32 pmc, ppc; 4917d0c6e71SRussell King 4927d0c6e71SRussell King /* enable clock gating */ 4937d0c6e71SRussell King ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 4947d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 4957d0c6e71SRussell King 4967d0c6e71SRussell King /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 4977d0c6e71SRussell King if (gpu->identity.revision == 0x4301 || 4987d0c6e71SRussell King gpu->identity.revision == 0x4302) 4997d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 5007d0c6e71SRussell King 5017d0c6e71SRussell King gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 5027d0c6e71SRussell King 5037d0c6e71SRussell King pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 5047d0c6e71SRussell King 5057d0c6e71SRussell King /* Disable PA clock gating for GC400+ except for GC420 */ 5067d0c6e71SRussell King if (gpu->identity.model >= chipModel_GC400 && 5077d0c6e71SRussell King gpu->identity.model != chipModel_GC420) 5087d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 5097d0c6e71SRussell King 5107d0c6e71SRussell King /* 5117d0c6e71SRussell King * Disable PE clock gating on revs < 5.0.0.0 when HZ is 5127d0c6e71SRussell King * present without a bug fix. 5137d0c6e71SRussell King */ 5147d0c6e71SRussell King if (gpu->identity.revision < 0x5000 && 5157d0c6e71SRussell King gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 5167d0c6e71SRussell King !(gpu->identity.minor_features1 & 5177d0c6e71SRussell King chipMinorFeatures1_DISABLE_PE_GATING)) 5187d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 5197d0c6e71SRussell King 5207d0c6e71SRussell King if (gpu->identity.revision < 0x5422) 5217d0c6e71SRussell King pmc |= BIT(15); /* Unknown bit */ 5227d0c6e71SRussell King 5237d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 5247d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 5257d0c6e71SRussell King 5267d0c6e71SRussell King gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 5277d0c6e71SRussell King } 5287d0c6e71SRussell King 529a8c21a54SThe etnaviv authors static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 530a8c21a54SThe etnaviv authors { 531a8c21a54SThe etnaviv authors u16 prefetch; 532a8c21a54SThe etnaviv authors 533472f79dcSRussell King if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 534472f79dcSRussell King etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 535472f79dcSRussell King gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 536a8c21a54SThe etnaviv authors u32 mc_memory_debug; 537a8c21a54SThe etnaviv authors 538a8c21a54SThe etnaviv authors mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 539a8c21a54SThe etnaviv authors 540a8c21a54SThe etnaviv authors if (gpu->identity.revision == 0x5007) 541a8c21a54SThe etnaviv authors mc_memory_debug |= 0x0c; 542a8c21a54SThe etnaviv authors else 543a8c21a54SThe etnaviv authors mc_memory_debug |= 0x08; 544a8c21a54SThe etnaviv authors 545a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 546a8c21a54SThe etnaviv authors } 547a8c21a54SThe etnaviv authors 5487d0c6e71SRussell King /* enable module-level clock gating */ 5497d0c6e71SRussell King etnaviv_gpu_enable_mlcg(gpu); 5507d0c6e71SRussell King 551a8c21a54SThe etnaviv authors /* 552a8c21a54SThe etnaviv authors * Update GPU AXI cache atttribute to "cacheable, no allocate". 553a8c21a54SThe etnaviv authors * This is necessary to prevent the iMX6 SoC locking up. 554a8c21a54SThe etnaviv authors */ 555a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_AXI_CONFIG, 556a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_AWCACHE(2) | 557a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_ARCACHE(2)); 558a8c21a54SThe etnaviv authors 559a8c21a54SThe etnaviv authors /* GC2000 rev 5108 needs a special bus config */ 560472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 561a8c21a54SThe etnaviv authors u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 562a8c21a54SThe etnaviv authors bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 563a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 564a8c21a54SThe etnaviv authors bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 565a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 566a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 567a8c21a54SThe etnaviv authors } 568a8c21a54SThe etnaviv authors 56999f861bcSLucas Stach /* setup the MMU */ 570e095c8feSLucas Stach etnaviv_iommu_restore(gpu); 571a8c21a54SThe etnaviv authors 572a8c21a54SThe etnaviv authors /* Start command processor */ 573a8c21a54SThe etnaviv authors prefetch = etnaviv_buffer_init(gpu); 574a8c21a54SThe etnaviv authors 575a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 576a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, 577a8c21a54SThe etnaviv authors gpu->buffer->paddr - gpu->memory_base); 578a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 579a8c21a54SThe etnaviv authors VIVS_FE_COMMAND_CONTROL_ENABLE | 580a8c21a54SThe etnaviv authors VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 581a8c21a54SThe etnaviv authors } 582a8c21a54SThe etnaviv authors 583a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 584a8c21a54SThe etnaviv authors { 585a8c21a54SThe etnaviv authors int ret, i; 586a8c21a54SThe etnaviv authors 587a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 5881409df04SLucas Stach if (ret < 0) { 5891409df04SLucas Stach dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 590a8c21a54SThe etnaviv authors return ret; 5911409df04SLucas Stach } 592a8c21a54SThe etnaviv authors 593a8c21a54SThe etnaviv authors etnaviv_hw_identify(gpu); 594a8c21a54SThe etnaviv authors 595a8c21a54SThe etnaviv authors if (gpu->identity.model == 0) { 596a8c21a54SThe etnaviv authors dev_err(gpu->dev, "Unknown GPU model\n"); 597f6427760SRussell King ret = -ENXIO; 598f6427760SRussell King goto fail; 599a8c21a54SThe etnaviv authors } 600a8c21a54SThe etnaviv authors 601b98c6688SRussell King /* Exclude VG cores with FE2.0 */ 602b98c6688SRussell King if (gpu->identity.features & chipFeatures_PIPE_VG && 603b98c6688SRussell King gpu->identity.features & chipFeatures_FE20) { 604b98c6688SRussell King dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 605b98c6688SRussell King ret = -ENXIO; 606b98c6688SRussell King goto fail; 607b98c6688SRussell King } 608b98c6688SRussell King 6092144fff7SLucas Stach /* 6102144fff7SLucas Stach * Set the GPU linear window to be at the end of the DMA window, where 6112144fff7SLucas Stach * the CMA area is likely to reside. This ensures that we are able to 6122144fff7SLucas Stach * map the command buffers while having the linear window overlap as 6132144fff7SLucas Stach * much RAM as possible, so we can optimize mappings for other buffers. 6142144fff7SLucas Stach * 6152144fff7SLucas Stach * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 6162144fff7SLucas Stach * to different views of the memory on the individual engines. 6172144fff7SLucas Stach */ 6182144fff7SLucas Stach if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 6192144fff7SLucas Stach (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 6202144fff7SLucas Stach u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 6212144fff7SLucas Stach if (dma_mask < PHYS_OFFSET + SZ_2G) 6222144fff7SLucas Stach gpu->memory_base = PHYS_OFFSET; 6232144fff7SLucas Stach else 6242144fff7SLucas Stach gpu->memory_base = dma_mask - SZ_2G + 1; 6252144fff7SLucas Stach } 6262144fff7SLucas Stach 627a8c21a54SThe etnaviv authors ret = etnaviv_hw_reset(gpu); 6281409df04SLucas Stach if (ret) { 6291409df04SLucas Stach dev_err(gpu->dev, "GPU reset failed\n"); 630a8c21a54SThe etnaviv authors goto fail; 6311409df04SLucas Stach } 632a8c21a54SThe etnaviv authors 633dd34bb96SLucas Stach gpu->mmu = etnaviv_iommu_new(gpu); 634dd34bb96SLucas Stach if (IS_ERR(gpu->mmu)) { 6351409df04SLucas Stach dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 636dd34bb96SLucas Stach ret = PTR_ERR(gpu->mmu); 637a8c21a54SThe etnaviv authors goto fail; 638a8c21a54SThe etnaviv authors } 639a8c21a54SThe etnaviv authors 640a8c21a54SThe etnaviv authors /* Create buffer: */ 641a8c21a54SThe etnaviv authors gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0); 642a8c21a54SThe etnaviv authors if (!gpu->buffer) { 643a8c21a54SThe etnaviv authors ret = -ENOMEM; 644a8c21a54SThe etnaviv authors dev_err(gpu->dev, "could not create command buffer\n"); 64545d16a6dSLucas Stach goto destroy_iommu; 646a8c21a54SThe etnaviv authors } 647acfee0ecSLucas Stach 648acfee0ecSLucas Stach if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 649acfee0ecSLucas Stach gpu->buffer->paddr - gpu->memory_base > 0x80000000) { 650a8c21a54SThe etnaviv authors ret = -EINVAL; 651a8c21a54SThe etnaviv authors dev_err(gpu->dev, 652a8c21a54SThe etnaviv authors "command buffer outside valid memory window\n"); 653a8c21a54SThe etnaviv authors goto free_buffer; 654a8c21a54SThe etnaviv authors } 655a8c21a54SThe etnaviv authors 656a8c21a54SThe etnaviv authors /* Setup event management */ 657a8c21a54SThe etnaviv authors spin_lock_init(&gpu->event_spinlock); 658a8c21a54SThe etnaviv authors init_completion(&gpu->event_free); 659a8c21a54SThe etnaviv authors for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 660a8c21a54SThe etnaviv authors gpu->event[i].used = false; 661a8c21a54SThe etnaviv authors complete(&gpu->event_free); 662a8c21a54SThe etnaviv authors } 663a8c21a54SThe etnaviv authors 664a8c21a54SThe etnaviv authors /* Now program the hardware */ 665a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 666a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 667f6086311SRussell King gpu->exec_state = -1; 668a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 669a8c21a54SThe etnaviv authors 670a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 671a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 672a8c21a54SThe etnaviv authors 673a8c21a54SThe etnaviv authors return 0; 674a8c21a54SThe etnaviv authors 675a8c21a54SThe etnaviv authors free_buffer: 676a8c21a54SThe etnaviv authors etnaviv_gpu_cmdbuf_free(gpu->buffer); 677a8c21a54SThe etnaviv authors gpu->buffer = NULL; 67845d16a6dSLucas Stach destroy_iommu: 67945d16a6dSLucas Stach etnaviv_iommu_destroy(gpu->mmu); 68045d16a6dSLucas Stach gpu->mmu = NULL; 681a8c21a54SThe etnaviv authors fail: 682a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 683a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 684a8c21a54SThe etnaviv authors 685a8c21a54SThe etnaviv authors return ret; 686a8c21a54SThe etnaviv authors } 687a8c21a54SThe etnaviv authors 688a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 689a8c21a54SThe etnaviv authors struct dma_debug { 690a8c21a54SThe etnaviv authors u32 address[2]; 691a8c21a54SThe etnaviv authors u32 state[2]; 692a8c21a54SThe etnaviv authors }; 693a8c21a54SThe etnaviv authors 694a8c21a54SThe etnaviv authors static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 695a8c21a54SThe etnaviv authors { 696a8c21a54SThe etnaviv authors u32 i; 697a8c21a54SThe etnaviv authors 698a8c21a54SThe etnaviv authors debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 699a8c21a54SThe etnaviv authors debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 700a8c21a54SThe etnaviv authors 701a8c21a54SThe etnaviv authors for (i = 0; i < 500; i++) { 702a8c21a54SThe etnaviv authors debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 703a8c21a54SThe etnaviv authors debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 704a8c21a54SThe etnaviv authors 705a8c21a54SThe etnaviv authors if (debug->address[0] != debug->address[1]) 706a8c21a54SThe etnaviv authors break; 707a8c21a54SThe etnaviv authors 708a8c21a54SThe etnaviv authors if (debug->state[0] != debug->state[1]) 709a8c21a54SThe etnaviv authors break; 710a8c21a54SThe etnaviv authors } 711a8c21a54SThe etnaviv authors } 712a8c21a54SThe etnaviv authors 713a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 714a8c21a54SThe etnaviv authors { 715a8c21a54SThe etnaviv authors struct dma_debug debug; 716a8c21a54SThe etnaviv authors u32 dma_lo, dma_hi, axi, idle; 717a8c21a54SThe etnaviv authors int ret; 718a8c21a54SThe etnaviv authors 719a8c21a54SThe etnaviv authors seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 720a8c21a54SThe etnaviv authors 721a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 722a8c21a54SThe etnaviv authors if (ret < 0) 723a8c21a54SThe etnaviv authors return ret; 724a8c21a54SThe etnaviv authors 725a8c21a54SThe etnaviv authors dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 726a8c21a54SThe etnaviv authors dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 727a8c21a54SThe etnaviv authors axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 728a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 729a8c21a54SThe etnaviv authors 730a8c21a54SThe etnaviv authors verify_dma(gpu, &debug); 731a8c21a54SThe etnaviv authors 732a8c21a54SThe etnaviv authors seq_puts(m, "\tfeatures\n"); 733a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features0: 0x%08x\n", 734a8c21a54SThe etnaviv authors gpu->identity.minor_features0); 735a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features1: 0x%08x\n", 736a8c21a54SThe etnaviv authors gpu->identity.minor_features1); 737a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features2: 0x%08x\n", 738a8c21a54SThe etnaviv authors gpu->identity.minor_features2); 739a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features3: 0x%08x\n", 740a8c21a54SThe etnaviv authors gpu->identity.minor_features3); 741602eb489SRussell King seq_printf(m, "\t minor_features4: 0x%08x\n", 742602eb489SRussell King gpu->identity.minor_features4); 743602eb489SRussell King seq_printf(m, "\t minor_features5: 0x%08x\n", 744602eb489SRussell King gpu->identity.minor_features5); 745a8c21a54SThe etnaviv authors 746a8c21a54SThe etnaviv authors seq_puts(m, "\tspecs\n"); 747a8c21a54SThe etnaviv authors seq_printf(m, "\t stream_count: %d\n", 748a8c21a54SThe etnaviv authors gpu->identity.stream_count); 749a8c21a54SThe etnaviv authors seq_printf(m, "\t register_max: %d\n", 750a8c21a54SThe etnaviv authors gpu->identity.register_max); 751a8c21a54SThe etnaviv authors seq_printf(m, "\t thread_count: %d\n", 752a8c21a54SThe etnaviv authors gpu->identity.thread_count); 753a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_cache_size: %d\n", 754a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size); 755a8c21a54SThe etnaviv authors seq_printf(m, "\t shader_core_count: %d\n", 756a8c21a54SThe etnaviv authors gpu->identity.shader_core_count); 757a8c21a54SThe etnaviv authors seq_printf(m, "\t pixel_pipes: %d\n", 758a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes); 759a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_output_buffer_size: %d\n", 760a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size); 761a8c21a54SThe etnaviv authors seq_printf(m, "\t buffer_size: %d\n", 762a8c21a54SThe etnaviv authors gpu->identity.buffer_size); 763a8c21a54SThe etnaviv authors seq_printf(m, "\t instruction_count: %d\n", 764a8c21a54SThe etnaviv authors gpu->identity.instruction_count); 765a8c21a54SThe etnaviv authors seq_printf(m, "\t num_constants: %d\n", 766a8c21a54SThe etnaviv authors gpu->identity.num_constants); 767602eb489SRussell King seq_printf(m, "\t varyings_count: %d\n", 768602eb489SRussell King gpu->identity.varyings_count); 769a8c21a54SThe etnaviv authors 770a8c21a54SThe etnaviv authors seq_printf(m, "\taxi: 0x%08x\n", axi); 771a8c21a54SThe etnaviv authors seq_printf(m, "\tidle: 0x%08x\n", idle); 772a8c21a54SThe etnaviv authors idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 773a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 774a8c21a54SThe etnaviv authors seq_puts(m, "\t FE is not idle\n"); 775a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 776a8c21a54SThe etnaviv authors seq_puts(m, "\t DE is not idle\n"); 777a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 778a8c21a54SThe etnaviv authors seq_puts(m, "\t PE is not idle\n"); 779a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 780a8c21a54SThe etnaviv authors seq_puts(m, "\t SH is not idle\n"); 781a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 782a8c21a54SThe etnaviv authors seq_puts(m, "\t PA is not idle\n"); 783a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 784a8c21a54SThe etnaviv authors seq_puts(m, "\t SE is not idle\n"); 785a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 786a8c21a54SThe etnaviv authors seq_puts(m, "\t RA is not idle\n"); 787a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 788a8c21a54SThe etnaviv authors seq_puts(m, "\t TX is not idle\n"); 789a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 790a8c21a54SThe etnaviv authors seq_puts(m, "\t VG is not idle\n"); 791a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 792a8c21a54SThe etnaviv authors seq_puts(m, "\t IM is not idle\n"); 793a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 794a8c21a54SThe etnaviv authors seq_puts(m, "\t FP is not idle\n"); 795a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 796a8c21a54SThe etnaviv authors seq_puts(m, "\t TS is not idle\n"); 797a8c21a54SThe etnaviv authors if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 798a8c21a54SThe etnaviv authors seq_puts(m, "\t AXI low power mode\n"); 799a8c21a54SThe etnaviv authors 800a8c21a54SThe etnaviv authors if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 801a8c21a54SThe etnaviv authors u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 802a8c21a54SThe etnaviv authors u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 803a8c21a54SThe etnaviv authors u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 804a8c21a54SThe etnaviv authors 805a8c21a54SThe etnaviv authors seq_puts(m, "\tMC\n"); 806a8c21a54SThe etnaviv authors seq_printf(m, "\t read0: 0x%08x\n", read0); 807a8c21a54SThe etnaviv authors seq_printf(m, "\t read1: 0x%08x\n", read1); 808a8c21a54SThe etnaviv authors seq_printf(m, "\t write: 0x%08x\n", write); 809a8c21a54SThe etnaviv authors } 810a8c21a54SThe etnaviv authors 811a8c21a54SThe etnaviv authors seq_puts(m, "\tDMA "); 812a8c21a54SThe etnaviv authors 813a8c21a54SThe etnaviv authors if (debug.address[0] == debug.address[1] && 814a8c21a54SThe etnaviv authors debug.state[0] == debug.state[1]) { 815a8c21a54SThe etnaviv authors seq_puts(m, "seems to be stuck\n"); 816a8c21a54SThe etnaviv authors } else if (debug.address[0] == debug.address[1]) { 817c01e0159SMasanari Iida seq_puts(m, "address is constant\n"); 818a8c21a54SThe etnaviv authors } else { 819c01e0159SMasanari Iida seq_puts(m, "is running\n"); 820a8c21a54SThe etnaviv authors } 821a8c21a54SThe etnaviv authors 822a8c21a54SThe etnaviv authors seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 823a8c21a54SThe etnaviv authors seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 824a8c21a54SThe etnaviv authors seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 825a8c21a54SThe etnaviv authors seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 826a8c21a54SThe etnaviv authors seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 827a8c21a54SThe etnaviv authors dma_lo, dma_hi); 828a8c21a54SThe etnaviv authors 829a8c21a54SThe etnaviv authors ret = 0; 830a8c21a54SThe etnaviv authors 831a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 832a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 833a8c21a54SThe etnaviv authors 834a8c21a54SThe etnaviv authors return ret; 835a8c21a54SThe etnaviv authors } 836a8c21a54SThe etnaviv authors #endif 837a8c21a54SThe etnaviv authors 838a8c21a54SThe etnaviv authors /* 839a8c21a54SThe etnaviv authors * Hangcheck detection for locked gpu: 840a8c21a54SThe etnaviv authors */ 841a8c21a54SThe etnaviv authors static void recover_worker(struct work_struct *work) 842a8c21a54SThe etnaviv authors { 843a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 844a8c21a54SThe etnaviv authors recover_work); 845a8c21a54SThe etnaviv authors unsigned long flags; 846a8c21a54SThe etnaviv authors unsigned int i; 847a8c21a54SThe etnaviv authors 848a8c21a54SThe etnaviv authors dev_err(gpu->dev, "hangcheck recover!\n"); 849a8c21a54SThe etnaviv authors 850a8c21a54SThe etnaviv authors if (pm_runtime_get_sync(gpu->dev) < 0) 851a8c21a54SThe etnaviv authors return; 852a8c21a54SThe etnaviv authors 853a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 854a8c21a54SThe etnaviv authors 855a8c21a54SThe etnaviv authors /* Only catch the first event, or when manually re-armed */ 856a8c21a54SThe etnaviv authors if (etnaviv_dump_core) { 857a8c21a54SThe etnaviv authors etnaviv_core_dump(gpu); 858a8c21a54SThe etnaviv authors etnaviv_dump_core = false; 859a8c21a54SThe etnaviv authors } 860a8c21a54SThe etnaviv authors 861a8c21a54SThe etnaviv authors etnaviv_hw_reset(gpu); 862a8c21a54SThe etnaviv authors 863a8c21a54SThe etnaviv authors /* complete all events, the GPU won't do it after the reset */ 864a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 865a8c21a54SThe etnaviv authors for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 866a8c21a54SThe etnaviv authors if (!gpu->event[i].used) 867a8c21a54SThe etnaviv authors continue; 868a8c21a54SThe etnaviv authors fence_signal(gpu->event[i].fence); 869a8c21a54SThe etnaviv authors gpu->event[i].fence = NULL; 870a8c21a54SThe etnaviv authors gpu->event[i].used = false; 871a8c21a54SThe etnaviv authors complete(&gpu->event_free); 872a8c21a54SThe etnaviv authors } 873a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 874a8c21a54SThe etnaviv authors gpu->completed_fence = gpu->active_fence; 875a8c21a54SThe etnaviv authors 876a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 877a8c21a54SThe etnaviv authors gpu->switch_context = true; 878f6086311SRussell King gpu->exec_state = -1; 879a8c21a54SThe etnaviv authors 880a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 881a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 882a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 883a8c21a54SThe etnaviv authors 884a8c21a54SThe etnaviv authors /* Retire the buffer objects in a work */ 885a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->retire_work); 886a8c21a54SThe etnaviv authors } 887a8c21a54SThe etnaviv authors 888a8c21a54SThe etnaviv authors static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) 889a8c21a54SThe etnaviv authors { 890a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 891a8c21a54SThe etnaviv authors mod_timer(&gpu->hangcheck_timer, 892a8c21a54SThe etnaviv authors round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); 893a8c21a54SThe etnaviv authors } 894a8c21a54SThe etnaviv authors 895a8c21a54SThe etnaviv authors static void hangcheck_handler(unsigned long data) 896a8c21a54SThe etnaviv authors { 897a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data; 898a8c21a54SThe etnaviv authors u32 fence = gpu->completed_fence; 899a8c21a54SThe etnaviv authors bool progress = false; 900a8c21a54SThe etnaviv authors 901a8c21a54SThe etnaviv authors if (fence != gpu->hangcheck_fence) { 902a8c21a54SThe etnaviv authors gpu->hangcheck_fence = fence; 903a8c21a54SThe etnaviv authors progress = true; 904a8c21a54SThe etnaviv authors } 905a8c21a54SThe etnaviv authors 906a8c21a54SThe etnaviv authors if (!progress) { 907a8c21a54SThe etnaviv authors u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 908a8c21a54SThe etnaviv authors int change = dma_addr - gpu->hangcheck_dma_addr; 909a8c21a54SThe etnaviv authors 910a8c21a54SThe etnaviv authors if (change < 0 || change > 16) { 911a8c21a54SThe etnaviv authors gpu->hangcheck_dma_addr = dma_addr; 912a8c21a54SThe etnaviv authors progress = true; 913a8c21a54SThe etnaviv authors } 914a8c21a54SThe etnaviv authors } 915a8c21a54SThe etnaviv authors 916a8c21a54SThe etnaviv authors if (!progress && fence_after(gpu->active_fence, fence)) { 917a8c21a54SThe etnaviv authors dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); 918a8c21a54SThe etnaviv authors dev_err(gpu->dev, " completed fence: %u\n", fence); 919a8c21a54SThe etnaviv authors dev_err(gpu->dev, " active fence: %u\n", 920a8c21a54SThe etnaviv authors gpu->active_fence); 921a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->recover_work); 922a8c21a54SThe etnaviv authors } 923a8c21a54SThe etnaviv authors 924a8c21a54SThe etnaviv authors /* if still more pending work, reset the hangcheck timer: */ 925a8c21a54SThe etnaviv authors if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) 926a8c21a54SThe etnaviv authors hangcheck_timer_reset(gpu); 927a8c21a54SThe etnaviv authors } 928a8c21a54SThe etnaviv authors 929a8c21a54SThe etnaviv authors static void hangcheck_disable(struct etnaviv_gpu *gpu) 930a8c21a54SThe etnaviv authors { 931a8c21a54SThe etnaviv authors del_timer_sync(&gpu->hangcheck_timer); 932a8c21a54SThe etnaviv authors cancel_work_sync(&gpu->recover_work); 933a8c21a54SThe etnaviv authors } 934a8c21a54SThe etnaviv authors 935a8c21a54SThe etnaviv authors /* fence object management */ 936a8c21a54SThe etnaviv authors struct etnaviv_fence { 937a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 938a8c21a54SThe etnaviv authors struct fence base; 939a8c21a54SThe etnaviv authors }; 940a8c21a54SThe etnaviv authors 941a8c21a54SThe etnaviv authors static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence) 942a8c21a54SThe etnaviv authors { 943a8c21a54SThe etnaviv authors return container_of(fence, struct etnaviv_fence, base); 944a8c21a54SThe etnaviv authors } 945a8c21a54SThe etnaviv authors 946a8c21a54SThe etnaviv authors static const char *etnaviv_fence_get_driver_name(struct fence *fence) 947a8c21a54SThe etnaviv authors { 948a8c21a54SThe etnaviv authors return "etnaviv"; 949a8c21a54SThe etnaviv authors } 950a8c21a54SThe etnaviv authors 951a8c21a54SThe etnaviv authors static const char *etnaviv_fence_get_timeline_name(struct fence *fence) 952a8c21a54SThe etnaviv authors { 953a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 954a8c21a54SThe etnaviv authors 955a8c21a54SThe etnaviv authors return dev_name(f->gpu->dev); 956a8c21a54SThe etnaviv authors } 957a8c21a54SThe etnaviv authors 958a8c21a54SThe etnaviv authors static bool etnaviv_fence_enable_signaling(struct fence *fence) 959a8c21a54SThe etnaviv authors { 960a8c21a54SThe etnaviv authors return true; 961a8c21a54SThe etnaviv authors } 962a8c21a54SThe etnaviv authors 963a8c21a54SThe etnaviv authors static bool etnaviv_fence_signaled(struct fence *fence) 964a8c21a54SThe etnaviv authors { 965a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 966a8c21a54SThe etnaviv authors 967a8c21a54SThe etnaviv authors return fence_completed(f->gpu, f->base.seqno); 968a8c21a54SThe etnaviv authors } 969a8c21a54SThe etnaviv authors 970a8c21a54SThe etnaviv authors static void etnaviv_fence_release(struct fence *fence) 971a8c21a54SThe etnaviv authors { 972a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 973a8c21a54SThe etnaviv authors 974a8c21a54SThe etnaviv authors kfree_rcu(f, base.rcu); 975a8c21a54SThe etnaviv authors } 976a8c21a54SThe etnaviv authors 977a8c21a54SThe etnaviv authors static const struct fence_ops etnaviv_fence_ops = { 978a8c21a54SThe etnaviv authors .get_driver_name = etnaviv_fence_get_driver_name, 979a8c21a54SThe etnaviv authors .get_timeline_name = etnaviv_fence_get_timeline_name, 980a8c21a54SThe etnaviv authors .enable_signaling = etnaviv_fence_enable_signaling, 981a8c21a54SThe etnaviv authors .signaled = etnaviv_fence_signaled, 982a8c21a54SThe etnaviv authors .wait = fence_default_wait, 983a8c21a54SThe etnaviv authors .release = etnaviv_fence_release, 984a8c21a54SThe etnaviv authors }; 985a8c21a54SThe etnaviv authors 986a8c21a54SThe etnaviv authors static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 987a8c21a54SThe etnaviv authors { 988a8c21a54SThe etnaviv authors struct etnaviv_fence *f; 989a8c21a54SThe etnaviv authors 990a8c21a54SThe etnaviv authors f = kzalloc(sizeof(*f), GFP_KERNEL); 991a8c21a54SThe etnaviv authors if (!f) 992a8c21a54SThe etnaviv authors return NULL; 993a8c21a54SThe etnaviv authors 994a8c21a54SThe etnaviv authors f->gpu = gpu; 995a8c21a54SThe etnaviv authors 996a8c21a54SThe etnaviv authors fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 997a8c21a54SThe etnaviv authors gpu->fence_context, ++gpu->next_fence); 998a8c21a54SThe etnaviv authors 999a8c21a54SThe etnaviv authors return &f->base; 1000a8c21a54SThe etnaviv authors } 1001a8c21a54SThe etnaviv authors 1002a8c21a54SThe etnaviv authors int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 1003a8c21a54SThe etnaviv authors unsigned int context, bool exclusive) 1004a8c21a54SThe etnaviv authors { 1005a8c21a54SThe etnaviv authors struct reservation_object *robj = etnaviv_obj->resv; 1006a8c21a54SThe etnaviv authors struct reservation_object_list *fobj; 1007a8c21a54SThe etnaviv authors struct fence *fence; 1008a8c21a54SThe etnaviv authors int i, ret; 1009a8c21a54SThe etnaviv authors 1010a8c21a54SThe etnaviv authors if (!exclusive) { 1011a8c21a54SThe etnaviv authors ret = reservation_object_reserve_shared(robj); 1012a8c21a54SThe etnaviv authors if (ret) 1013a8c21a54SThe etnaviv authors return ret; 1014a8c21a54SThe etnaviv authors } 1015a8c21a54SThe etnaviv authors 1016a8c21a54SThe etnaviv authors /* 1017a8c21a54SThe etnaviv authors * If we have any shared fences, then the exclusive fence 1018a8c21a54SThe etnaviv authors * should be ignored as it will already have been signalled. 1019a8c21a54SThe etnaviv authors */ 1020a8c21a54SThe etnaviv authors fobj = reservation_object_get_list(robj); 1021a8c21a54SThe etnaviv authors if (!fobj || fobj->shared_count == 0) { 1022a8c21a54SThe etnaviv authors /* Wait on any existing exclusive fence which isn't our own */ 1023a8c21a54SThe etnaviv authors fence = reservation_object_get_excl(robj); 1024a8c21a54SThe etnaviv authors if (fence && fence->context != context) { 1025a8c21a54SThe etnaviv authors ret = fence_wait(fence, true); 1026a8c21a54SThe etnaviv authors if (ret) 1027a8c21a54SThe etnaviv authors return ret; 1028a8c21a54SThe etnaviv authors } 1029a8c21a54SThe etnaviv authors } 1030a8c21a54SThe etnaviv authors 1031a8c21a54SThe etnaviv authors if (!exclusive || !fobj) 1032a8c21a54SThe etnaviv authors return 0; 1033a8c21a54SThe etnaviv authors 1034a8c21a54SThe etnaviv authors for (i = 0; i < fobj->shared_count; i++) { 1035a8c21a54SThe etnaviv authors fence = rcu_dereference_protected(fobj->shared[i], 1036a8c21a54SThe etnaviv authors reservation_object_held(robj)); 1037a8c21a54SThe etnaviv authors if (fence->context != context) { 1038a8c21a54SThe etnaviv authors ret = fence_wait(fence, true); 1039a8c21a54SThe etnaviv authors if (ret) 1040a8c21a54SThe etnaviv authors return ret; 1041a8c21a54SThe etnaviv authors } 1042a8c21a54SThe etnaviv authors } 1043a8c21a54SThe etnaviv authors 1044a8c21a54SThe etnaviv authors return 0; 1045a8c21a54SThe etnaviv authors } 1046a8c21a54SThe etnaviv authors 1047a8c21a54SThe etnaviv authors /* 1048a8c21a54SThe etnaviv authors * event management: 1049a8c21a54SThe etnaviv authors */ 1050a8c21a54SThe etnaviv authors 1051a8c21a54SThe etnaviv authors static unsigned int event_alloc(struct etnaviv_gpu *gpu) 1052a8c21a54SThe etnaviv authors { 1053a8c21a54SThe etnaviv authors unsigned long ret, flags; 1054a8c21a54SThe etnaviv authors unsigned int i, event = ~0U; 1055a8c21a54SThe etnaviv authors 1056a8c21a54SThe etnaviv authors ret = wait_for_completion_timeout(&gpu->event_free, 1057a8c21a54SThe etnaviv authors msecs_to_jiffies(10 * 10000)); 1058a8c21a54SThe etnaviv authors if (!ret) 1059a8c21a54SThe etnaviv authors dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1060a8c21a54SThe etnaviv authors 1061a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1062a8c21a54SThe etnaviv authors 1063a8c21a54SThe etnaviv authors /* find first free event */ 1064a8c21a54SThe etnaviv authors for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 1065a8c21a54SThe etnaviv authors if (gpu->event[i].used == false) { 1066a8c21a54SThe etnaviv authors gpu->event[i].used = true; 1067a8c21a54SThe etnaviv authors event = i; 1068a8c21a54SThe etnaviv authors break; 1069a8c21a54SThe etnaviv authors } 1070a8c21a54SThe etnaviv authors } 1071a8c21a54SThe etnaviv authors 1072a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1073a8c21a54SThe etnaviv authors 1074a8c21a54SThe etnaviv authors return event; 1075a8c21a54SThe etnaviv authors } 1076a8c21a54SThe etnaviv authors 1077a8c21a54SThe etnaviv authors static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1078a8c21a54SThe etnaviv authors { 1079a8c21a54SThe etnaviv authors unsigned long flags; 1080a8c21a54SThe etnaviv authors 1081a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1082a8c21a54SThe etnaviv authors 1083a8c21a54SThe etnaviv authors if (gpu->event[event].used == false) { 1084a8c21a54SThe etnaviv authors dev_warn(gpu->dev, "event %u is already marked as free", 1085a8c21a54SThe etnaviv authors event); 1086a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1087a8c21a54SThe etnaviv authors } else { 1088a8c21a54SThe etnaviv authors gpu->event[event].used = false; 1089a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1090a8c21a54SThe etnaviv authors 1091a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1092a8c21a54SThe etnaviv authors } 1093a8c21a54SThe etnaviv authors } 1094a8c21a54SThe etnaviv authors 1095a8c21a54SThe etnaviv authors /* 1096a8c21a54SThe etnaviv authors * Cmdstream submission/retirement: 1097a8c21a54SThe etnaviv authors */ 1098a8c21a54SThe etnaviv authors 1099a8c21a54SThe etnaviv authors struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size, 1100a8c21a54SThe etnaviv authors size_t nr_bos) 1101a8c21a54SThe etnaviv authors { 1102a8c21a54SThe etnaviv authors struct etnaviv_cmdbuf *cmdbuf; 1103b6325f40SRussell King size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]), 1104a8c21a54SThe etnaviv authors sizeof(*cmdbuf)); 1105a8c21a54SThe etnaviv authors 1106a8c21a54SThe etnaviv authors cmdbuf = kzalloc(sz, GFP_KERNEL); 1107a8c21a54SThe etnaviv authors if (!cmdbuf) 1108a8c21a54SThe etnaviv authors return NULL; 1109a8c21a54SThe etnaviv authors 1110f6e45661SLuis R. Rodriguez cmdbuf->vaddr = dma_alloc_wc(gpu->dev, size, &cmdbuf->paddr, 1111a8c21a54SThe etnaviv authors GFP_KERNEL); 1112a8c21a54SThe etnaviv authors if (!cmdbuf->vaddr) { 1113a8c21a54SThe etnaviv authors kfree(cmdbuf); 1114a8c21a54SThe etnaviv authors return NULL; 1115a8c21a54SThe etnaviv authors } 1116a8c21a54SThe etnaviv authors 1117a8c21a54SThe etnaviv authors cmdbuf->gpu = gpu; 1118a8c21a54SThe etnaviv authors cmdbuf->size = size; 1119a8c21a54SThe etnaviv authors 1120a8c21a54SThe etnaviv authors return cmdbuf; 1121a8c21a54SThe etnaviv authors } 1122a8c21a54SThe etnaviv authors 1123a8c21a54SThe etnaviv authors void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf) 1124a8c21a54SThe etnaviv authors { 1125f6e45661SLuis R. Rodriguez dma_free_wc(cmdbuf->gpu->dev, cmdbuf->size, cmdbuf->vaddr, 1126f6e45661SLuis R. Rodriguez cmdbuf->paddr); 1127a8c21a54SThe etnaviv authors kfree(cmdbuf); 1128a8c21a54SThe etnaviv authors } 1129a8c21a54SThe etnaviv authors 1130a8c21a54SThe etnaviv authors static void retire_worker(struct work_struct *work) 1131a8c21a54SThe etnaviv authors { 1132a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1133a8c21a54SThe etnaviv authors retire_work); 1134a8c21a54SThe etnaviv authors u32 fence = gpu->completed_fence; 1135a8c21a54SThe etnaviv authors struct etnaviv_cmdbuf *cmdbuf, *tmp; 1136a8c21a54SThe etnaviv authors unsigned int i; 1137a8c21a54SThe etnaviv authors 1138a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 1139a8c21a54SThe etnaviv authors list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { 1140a8c21a54SThe etnaviv authors if (!fence_is_signaled(cmdbuf->fence)) 1141a8c21a54SThe etnaviv authors break; 1142a8c21a54SThe etnaviv authors 1143a8c21a54SThe etnaviv authors list_del(&cmdbuf->node); 1144a8c21a54SThe etnaviv authors fence_put(cmdbuf->fence); 1145a8c21a54SThe etnaviv authors 1146a8c21a54SThe etnaviv authors for (i = 0; i < cmdbuf->nr_bos; i++) { 1147b6325f40SRussell King struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; 1148b6325f40SRussell King struct etnaviv_gem_object *etnaviv_obj = mapping->object; 1149a8c21a54SThe etnaviv authors 1150a8c21a54SThe etnaviv authors atomic_dec(&etnaviv_obj->gpu_active); 1151a8c21a54SThe etnaviv authors /* drop the refcount taken in etnaviv_gpu_submit */ 1152b6325f40SRussell King etnaviv_gem_mapping_unreference(mapping); 1153a8c21a54SThe etnaviv authors } 1154a8c21a54SThe etnaviv authors 1155a8c21a54SThe etnaviv authors etnaviv_gpu_cmdbuf_free(cmdbuf); 1156d9fd0c7dSLucas Stach /* 1157d9fd0c7dSLucas Stach * We need to balance the runtime PM count caused by 1158d9fd0c7dSLucas Stach * each submission. Upon submission, we increment 1159d9fd0c7dSLucas Stach * the runtime PM counter, and allocate one event. 1160d9fd0c7dSLucas Stach * So here, we put the runtime PM count for each 1161d9fd0c7dSLucas Stach * completed event. 1162d9fd0c7dSLucas Stach */ 1163d9fd0c7dSLucas Stach pm_runtime_put_autosuspend(gpu->dev); 1164a8c21a54SThe etnaviv authors } 1165a8c21a54SThe etnaviv authors 1166a8c21a54SThe etnaviv authors gpu->retired_fence = fence; 1167a8c21a54SThe etnaviv authors 1168a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1169a8c21a54SThe etnaviv authors 1170a8c21a54SThe etnaviv authors wake_up_all(&gpu->fence_event); 1171a8c21a54SThe etnaviv authors } 1172a8c21a54SThe etnaviv authors 1173a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1174a8c21a54SThe etnaviv authors u32 fence, struct timespec *timeout) 1175a8c21a54SThe etnaviv authors { 1176a8c21a54SThe etnaviv authors int ret; 1177a8c21a54SThe etnaviv authors 1178a8c21a54SThe etnaviv authors if (fence_after(fence, gpu->next_fence)) { 1179a8c21a54SThe etnaviv authors DRM_ERROR("waiting on invalid fence: %u (of %u)\n", 1180a8c21a54SThe etnaviv authors fence, gpu->next_fence); 1181a8c21a54SThe etnaviv authors return -EINVAL; 1182a8c21a54SThe etnaviv authors } 1183a8c21a54SThe etnaviv authors 1184a8c21a54SThe etnaviv authors if (!timeout) { 1185a8c21a54SThe etnaviv authors /* No timeout was requested: just test for completion */ 1186a8c21a54SThe etnaviv authors ret = fence_completed(gpu, fence) ? 0 : -EBUSY; 1187a8c21a54SThe etnaviv authors } else { 1188a8c21a54SThe etnaviv authors unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1189a8c21a54SThe etnaviv authors 1190a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1191a8c21a54SThe etnaviv authors fence_completed(gpu, fence), 1192a8c21a54SThe etnaviv authors remaining); 1193a8c21a54SThe etnaviv authors if (ret == 0) { 1194a8c21a54SThe etnaviv authors DBG("timeout waiting for fence: %u (retired: %u completed: %u)", 1195a8c21a54SThe etnaviv authors fence, gpu->retired_fence, 1196a8c21a54SThe etnaviv authors gpu->completed_fence); 1197a8c21a54SThe etnaviv authors ret = -ETIMEDOUT; 1198a8c21a54SThe etnaviv authors } else if (ret != -ERESTARTSYS) { 1199a8c21a54SThe etnaviv authors ret = 0; 1200a8c21a54SThe etnaviv authors } 1201a8c21a54SThe etnaviv authors } 1202a8c21a54SThe etnaviv authors 1203a8c21a54SThe etnaviv authors return ret; 1204a8c21a54SThe etnaviv authors } 1205a8c21a54SThe etnaviv authors 1206a8c21a54SThe etnaviv authors /* 1207a8c21a54SThe etnaviv authors * Wait for an object to become inactive. This, on it's own, is not race 1208a8c21a54SThe etnaviv authors * free: the object is moved by the retire worker off the active list, and 1209a8c21a54SThe etnaviv authors * then the iova is put. Moreover, the object could be re-submitted just 1210a8c21a54SThe etnaviv authors * after we notice that it's become inactive. 1211a8c21a54SThe etnaviv authors * 1212a8c21a54SThe etnaviv authors * Although the retirement happens under the gpu lock, we don't want to hold 1213a8c21a54SThe etnaviv authors * that lock in this function while waiting. 1214a8c21a54SThe etnaviv authors */ 1215a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1216a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1217a8c21a54SThe etnaviv authors { 1218a8c21a54SThe etnaviv authors unsigned long remaining; 1219a8c21a54SThe etnaviv authors long ret; 1220a8c21a54SThe etnaviv authors 1221a8c21a54SThe etnaviv authors if (!timeout) 1222a8c21a54SThe etnaviv authors return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1223a8c21a54SThe etnaviv authors 1224a8c21a54SThe etnaviv authors remaining = etnaviv_timeout_to_jiffies(timeout); 1225a8c21a54SThe etnaviv authors 1226a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1227a8c21a54SThe etnaviv authors !is_active(etnaviv_obj), 1228a8c21a54SThe etnaviv authors remaining); 1229a8c21a54SThe etnaviv authors if (ret > 0) { 1230a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = gpu->drm->dev_private; 1231a8c21a54SThe etnaviv authors 1232a8c21a54SThe etnaviv authors /* Synchronise with the retire worker */ 1233a8c21a54SThe etnaviv authors flush_workqueue(priv->wq); 1234a8c21a54SThe etnaviv authors return 0; 1235a8c21a54SThe etnaviv authors } else if (ret == -ERESTARTSYS) { 1236a8c21a54SThe etnaviv authors return -ERESTARTSYS; 1237a8c21a54SThe etnaviv authors } else { 1238a8c21a54SThe etnaviv authors return -ETIMEDOUT; 1239a8c21a54SThe etnaviv authors } 1240a8c21a54SThe etnaviv authors } 1241a8c21a54SThe etnaviv authors 1242a8c21a54SThe etnaviv authors int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) 1243a8c21a54SThe etnaviv authors { 1244a8c21a54SThe etnaviv authors return pm_runtime_get_sync(gpu->dev); 1245a8c21a54SThe etnaviv authors } 1246a8c21a54SThe etnaviv authors 1247a8c21a54SThe etnaviv authors void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) 1248a8c21a54SThe etnaviv authors { 1249a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1250a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1251a8c21a54SThe etnaviv authors } 1252a8c21a54SThe etnaviv authors 1253a8c21a54SThe etnaviv authors /* add bo's to gpu's ring, and kick gpu: */ 1254a8c21a54SThe etnaviv authors int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 1255a8c21a54SThe etnaviv authors struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) 1256a8c21a54SThe etnaviv authors { 1257a8c21a54SThe etnaviv authors struct fence *fence; 1258a8c21a54SThe etnaviv authors unsigned int event, i; 1259a8c21a54SThe etnaviv authors int ret; 1260a8c21a54SThe etnaviv authors 1261a8c21a54SThe etnaviv authors ret = etnaviv_gpu_pm_get_sync(gpu); 1262a8c21a54SThe etnaviv authors if (ret < 0) 1263a8c21a54SThe etnaviv authors return ret; 1264a8c21a54SThe etnaviv authors 1265a8c21a54SThe etnaviv authors /* 1266a8c21a54SThe etnaviv authors * TODO 1267a8c21a54SThe etnaviv authors * 1268a8c21a54SThe etnaviv authors * - flush 1269a8c21a54SThe etnaviv authors * - data endian 1270a8c21a54SThe etnaviv authors * - prefetch 1271a8c21a54SThe etnaviv authors * 1272a8c21a54SThe etnaviv authors */ 1273a8c21a54SThe etnaviv authors 1274a8c21a54SThe etnaviv authors event = event_alloc(gpu); 1275a8c21a54SThe etnaviv authors if (unlikely(event == ~0U)) { 1276a8c21a54SThe etnaviv authors DRM_ERROR("no free event\n"); 1277a8c21a54SThe etnaviv authors ret = -EBUSY; 1278d9853490SLucas Stach goto out_pm_put; 1279a8c21a54SThe etnaviv authors } 1280a8c21a54SThe etnaviv authors 1281a8c21a54SThe etnaviv authors fence = etnaviv_gpu_fence_alloc(gpu); 1282a8c21a54SThe etnaviv authors if (!fence) { 1283a8c21a54SThe etnaviv authors event_free(gpu, event); 1284a8c21a54SThe etnaviv authors ret = -ENOMEM; 1285d9853490SLucas Stach goto out_pm_put; 1286a8c21a54SThe etnaviv authors } 1287a8c21a54SThe etnaviv authors 1288d9853490SLucas Stach mutex_lock(&gpu->lock); 1289d9853490SLucas Stach 1290a8c21a54SThe etnaviv authors gpu->event[event].fence = fence; 1291a8c21a54SThe etnaviv authors submit->fence = fence->seqno; 1292a8c21a54SThe etnaviv authors gpu->active_fence = submit->fence; 1293a8c21a54SThe etnaviv authors 1294a8c21a54SThe etnaviv authors if (gpu->lastctx != cmdbuf->ctx) { 1295a8c21a54SThe etnaviv authors gpu->mmu->need_flush = true; 1296a8c21a54SThe etnaviv authors gpu->switch_context = true; 1297a8c21a54SThe etnaviv authors gpu->lastctx = cmdbuf->ctx; 1298a8c21a54SThe etnaviv authors } 1299a8c21a54SThe etnaviv authors 1300a8c21a54SThe etnaviv authors etnaviv_buffer_queue(gpu, event, cmdbuf); 1301a8c21a54SThe etnaviv authors 1302a8c21a54SThe etnaviv authors cmdbuf->fence = fence; 1303a8c21a54SThe etnaviv authors list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); 1304a8c21a54SThe etnaviv authors 1305a8c21a54SThe etnaviv authors /* We're committed to adding this command buffer, hold a PM reference */ 1306a8c21a54SThe etnaviv authors pm_runtime_get_noresume(gpu->dev); 1307a8c21a54SThe etnaviv authors 1308a8c21a54SThe etnaviv authors for (i = 0; i < submit->nr_bos; i++) { 1309a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; 1310a8c21a54SThe etnaviv authors 1311b6325f40SRussell King /* Each cmdbuf takes a refcount on the mapping */ 1312b6325f40SRussell King etnaviv_gem_mapping_reference(submit->bos[i].mapping); 1313b6325f40SRussell King cmdbuf->bo_map[i] = submit->bos[i].mapping; 1314a8c21a54SThe etnaviv authors atomic_inc(&etnaviv_obj->gpu_active); 1315a8c21a54SThe etnaviv authors 1316a8c21a54SThe etnaviv authors if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) 1317a8c21a54SThe etnaviv authors reservation_object_add_excl_fence(etnaviv_obj->resv, 1318a8c21a54SThe etnaviv authors fence); 1319a8c21a54SThe etnaviv authors else 1320a8c21a54SThe etnaviv authors reservation_object_add_shared_fence(etnaviv_obj->resv, 1321a8c21a54SThe etnaviv authors fence); 1322a8c21a54SThe etnaviv authors } 1323a8c21a54SThe etnaviv authors cmdbuf->nr_bos = submit->nr_bos; 1324a8c21a54SThe etnaviv authors hangcheck_timer_reset(gpu); 1325a8c21a54SThe etnaviv authors ret = 0; 1326a8c21a54SThe etnaviv authors 1327a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1328a8c21a54SThe etnaviv authors 1329d9853490SLucas Stach out_pm_put: 1330a8c21a54SThe etnaviv authors etnaviv_gpu_pm_put(gpu); 1331a8c21a54SThe etnaviv authors 1332a8c21a54SThe etnaviv authors return ret; 1333a8c21a54SThe etnaviv authors } 1334a8c21a54SThe etnaviv authors 1335a8c21a54SThe etnaviv authors /* 1336a8c21a54SThe etnaviv authors * Init/Cleanup: 1337a8c21a54SThe etnaviv authors */ 1338a8c21a54SThe etnaviv authors static irqreturn_t irq_handler(int irq, void *data) 1339a8c21a54SThe etnaviv authors { 1340a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = data; 1341a8c21a54SThe etnaviv authors irqreturn_t ret = IRQ_NONE; 1342a8c21a54SThe etnaviv authors 1343a8c21a54SThe etnaviv authors u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1344a8c21a54SThe etnaviv authors 1345a8c21a54SThe etnaviv authors if (intr != 0) { 1346a8c21a54SThe etnaviv authors int event; 1347a8c21a54SThe etnaviv authors 1348a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1349a8c21a54SThe etnaviv authors 1350a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1351a8c21a54SThe etnaviv authors 1352a8c21a54SThe etnaviv authors if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1353a8c21a54SThe etnaviv authors dev_err(gpu->dev, "AXI bus error\n"); 1354a8c21a54SThe etnaviv authors intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1355a8c21a54SThe etnaviv authors } 1356a8c21a54SThe etnaviv authors 1357a8c21a54SThe etnaviv authors while ((event = ffs(intr)) != 0) { 1358a8c21a54SThe etnaviv authors struct fence *fence; 1359a8c21a54SThe etnaviv authors 1360a8c21a54SThe etnaviv authors event -= 1; 1361a8c21a54SThe etnaviv authors 1362a8c21a54SThe etnaviv authors intr &= ~(1 << event); 1363a8c21a54SThe etnaviv authors 1364a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "event %u\n", event); 1365a8c21a54SThe etnaviv authors 1366a8c21a54SThe etnaviv authors fence = gpu->event[event].fence; 1367a8c21a54SThe etnaviv authors gpu->event[event].fence = NULL; 1368a8c21a54SThe etnaviv authors fence_signal(fence); 1369a8c21a54SThe etnaviv authors 1370a8c21a54SThe etnaviv authors /* 1371a8c21a54SThe etnaviv authors * Events can be processed out of order. Eg, 1372a8c21a54SThe etnaviv authors * - allocate and queue event 0 1373a8c21a54SThe etnaviv authors * - allocate event 1 1374a8c21a54SThe etnaviv authors * - event 0 completes, we process it 1375a8c21a54SThe etnaviv authors * - allocate and queue event 0 1376a8c21a54SThe etnaviv authors * - event 1 and event 0 complete 1377a8c21a54SThe etnaviv authors * we can end up processing event 0 first, then 1. 1378a8c21a54SThe etnaviv authors */ 1379a8c21a54SThe etnaviv authors if (fence_after(fence->seqno, gpu->completed_fence)) 1380a8c21a54SThe etnaviv authors gpu->completed_fence = fence->seqno; 1381a8c21a54SThe etnaviv authors 1382a8c21a54SThe etnaviv authors event_free(gpu, event); 1383a8c21a54SThe etnaviv authors } 1384a8c21a54SThe etnaviv authors 1385a8c21a54SThe etnaviv authors /* Retire the buffer objects in a work */ 1386a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->retire_work); 1387a8c21a54SThe etnaviv authors 1388a8c21a54SThe etnaviv authors ret = IRQ_HANDLED; 1389a8c21a54SThe etnaviv authors } 1390a8c21a54SThe etnaviv authors 1391a8c21a54SThe etnaviv authors return ret; 1392a8c21a54SThe etnaviv authors } 1393a8c21a54SThe etnaviv authors 1394a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1395a8c21a54SThe etnaviv authors { 1396a8c21a54SThe etnaviv authors int ret; 1397a8c21a54SThe etnaviv authors 13989c7310c0SLucas Stach if (gpu->clk_bus) { 13999c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_bus); 1400a8c21a54SThe etnaviv authors if (ret) 1401a8c21a54SThe etnaviv authors return ret; 1402a8c21a54SThe etnaviv authors } 1403a8c21a54SThe etnaviv authors 14049c7310c0SLucas Stach if (gpu->clk_core) { 14059c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_core); 14069c7310c0SLucas Stach if (ret) 14079c7310c0SLucas Stach goto disable_clk_bus; 14089c7310c0SLucas Stach } 14099c7310c0SLucas Stach 14109c7310c0SLucas Stach if (gpu->clk_shader) { 14119c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_shader); 14129c7310c0SLucas Stach if (ret) 14139c7310c0SLucas Stach goto disable_clk_core; 14149c7310c0SLucas Stach } 14159c7310c0SLucas Stach 1416a8c21a54SThe etnaviv authors return 0; 14179c7310c0SLucas Stach 14189c7310c0SLucas Stach disable_clk_core: 14199c7310c0SLucas Stach if (gpu->clk_core) 14209c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 14219c7310c0SLucas Stach disable_clk_bus: 14229c7310c0SLucas Stach if (gpu->clk_bus) 14239c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 14249c7310c0SLucas Stach 14259c7310c0SLucas Stach return ret; 1426a8c21a54SThe etnaviv authors } 1427a8c21a54SThe etnaviv authors 1428a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1429a8c21a54SThe etnaviv authors { 14309c7310c0SLucas Stach if (gpu->clk_shader) 14319c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_shader); 14329c7310c0SLucas Stach if (gpu->clk_core) 14339c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 14349c7310c0SLucas Stach if (gpu->clk_bus) 14359c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 1436a8c21a54SThe etnaviv authors 1437a8c21a54SThe etnaviv authors return 0; 1438a8c21a54SThe etnaviv authors } 1439a8c21a54SThe etnaviv authors 1440a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1441a8c21a54SThe etnaviv authors { 1442a8c21a54SThe etnaviv authors if (gpu->buffer) { 1443a8c21a54SThe etnaviv authors unsigned long timeout; 1444a8c21a54SThe etnaviv authors 1445a8c21a54SThe etnaviv authors /* Replace the last WAIT with END */ 1446a8c21a54SThe etnaviv authors etnaviv_buffer_end(gpu); 1447a8c21a54SThe etnaviv authors 1448a8c21a54SThe etnaviv authors /* 1449a8c21a54SThe etnaviv authors * We know that only the FE is busy here, this should 1450a8c21a54SThe etnaviv authors * happen quickly (as the WAIT is only 200 cycles). If 1451a8c21a54SThe etnaviv authors * we fail, just warn and continue. 1452a8c21a54SThe etnaviv authors */ 1453a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(100); 1454a8c21a54SThe etnaviv authors do { 1455a8c21a54SThe etnaviv authors u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1456a8c21a54SThe etnaviv authors 1457a8c21a54SThe etnaviv authors if ((idle & gpu->idle_mask) == gpu->idle_mask) 1458a8c21a54SThe etnaviv authors break; 1459a8c21a54SThe etnaviv authors 1460a8c21a54SThe etnaviv authors if (time_is_before_jiffies(timeout)) { 1461a8c21a54SThe etnaviv authors dev_warn(gpu->dev, 1462a8c21a54SThe etnaviv authors "timed out waiting for idle: idle=0x%x\n", 1463a8c21a54SThe etnaviv authors idle); 1464a8c21a54SThe etnaviv authors break; 1465a8c21a54SThe etnaviv authors } 1466a8c21a54SThe etnaviv authors 1467a8c21a54SThe etnaviv authors udelay(5); 1468a8c21a54SThe etnaviv authors } while (1); 1469a8c21a54SThe etnaviv authors } 1470a8c21a54SThe etnaviv authors 1471a8c21a54SThe etnaviv authors return etnaviv_gpu_clk_disable(gpu); 1472a8c21a54SThe etnaviv authors } 1473a8c21a54SThe etnaviv authors 1474a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1475a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1476a8c21a54SThe etnaviv authors { 1477a8c21a54SThe etnaviv authors u32 clock; 1478a8c21a54SThe etnaviv authors int ret; 1479a8c21a54SThe etnaviv authors 1480a8c21a54SThe etnaviv authors ret = mutex_lock_killable(&gpu->lock); 1481a8c21a54SThe etnaviv authors if (ret) 1482a8c21a54SThe etnaviv authors return ret; 1483a8c21a54SThe etnaviv authors 1484a8c21a54SThe etnaviv authors clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 1485a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 1486a8c21a54SThe etnaviv authors 1487a8c21a54SThe etnaviv authors etnaviv_gpu_load_clock(gpu, clock); 1488a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1489a8c21a54SThe etnaviv authors 1490a8c21a54SThe etnaviv authors gpu->switch_context = true; 1491f6086311SRussell King gpu->exec_state = -1; 1492a8c21a54SThe etnaviv authors 1493a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1494a8c21a54SThe etnaviv authors 1495a8c21a54SThe etnaviv authors return 0; 1496a8c21a54SThe etnaviv authors } 1497a8c21a54SThe etnaviv authors #endif 1498a8c21a54SThe etnaviv authors 1499a8c21a54SThe etnaviv authors static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1500a8c21a54SThe etnaviv authors void *data) 1501a8c21a54SThe etnaviv authors { 1502a8c21a54SThe etnaviv authors struct drm_device *drm = data; 1503a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = drm->dev_private; 1504a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1505a8c21a54SThe etnaviv authors int ret; 1506a8c21a54SThe etnaviv authors 1507a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1508a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 1509a8c21a54SThe etnaviv authors #else 1510a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1511a8c21a54SThe etnaviv authors #endif 1512a8c21a54SThe etnaviv authors if (ret < 0) 1513a8c21a54SThe etnaviv authors return ret; 1514a8c21a54SThe etnaviv authors 1515a8c21a54SThe etnaviv authors gpu->drm = drm; 1516a8c21a54SThe etnaviv authors gpu->fence_context = fence_context_alloc(1); 1517a8c21a54SThe etnaviv authors spin_lock_init(&gpu->fence_spinlock); 1518a8c21a54SThe etnaviv authors 1519a8c21a54SThe etnaviv authors INIT_LIST_HEAD(&gpu->active_cmd_list); 1520a8c21a54SThe etnaviv authors INIT_WORK(&gpu->retire_work, retire_worker); 1521a8c21a54SThe etnaviv authors INIT_WORK(&gpu->recover_work, recover_worker); 1522a8c21a54SThe etnaviv authors init_waitqueue_head(&gpu->fence_event); 1523a8c21a54SThe etnaviv authors 1524946dd8d5SLucas Stach setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, 1525a8c21a54SThe etnaviv authors (unsigned long)gpu); 1526a8c21a54SThe etnaviv authors 1527a8c21a54SThe etnaviv authors priv->gpu[priv->num_gpus++] = gpu; 1528a8c21a54SThe etnaviv authors 1529a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1530a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1531a8c21a54SThe etnaviv authors 1532a8c21a54SThe etnaviv authors return 0; 1533a8c21a54SThe etnaviv authors } 1534a8c21a54SThe etnaviv authors 1535a8c21a54SThe etnaviv authors static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1536a8c21a54SThe etnaviv authors void *data) 1537a8c21a54SThe etnaviv authors { 1538a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1539a8c21a54SThe etnaviv authors 1540a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 1541a8c21a54SThe etnaviv authors 1542a8c21a54SThe etnaviv authors hangcheck_disable(gpu); 1543a8c21a54SThe etnaviv authors 1544a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1545a8c21a54SThe etnaviv authors pm_runtime_get_sync(gpu->dev); 1546a8c21a54SThe etnaviv authors pm_runtime_put_sync_suspend(gpu->dev); 1547a8c21a54SThe etnaviv authors #else 1548a8c21a54SThe etnaviv authors etnaviv_gpu_hw_suspend(gpu); 1549a8c21a54SThe etnaviv authors #endif 1550a8c21a54SThe etnaviv authors 1551a8c21a54SThe etnaviv authors if (gpu->buffer) { 1552a8c21a54SThe etnaviv authors etnaviv_gpu_cmdbuf_free(gpu->buffer); 1553a8c21a54SThe etnaviv authors gpu->buffer = NULL; 1554a8c21a54SThe etnaviv authors } 1555a8c21a54SThe etnaviv authors 1556a8c21a54SThe etnaviv authors if (gpu->mmu) { 1557a8c21a54SThe etnaviv authors etnaviv_iommu_destroy(gpu->mmu); 1558a8c21a54SThe etnaviv authors gpu->mmu = NULL; 1559a8c21a54SThe etnaviv authors } 1560a8c21a54SThe etnaviv authors 1561a8c21a54SThe etnaviv authors gpu->drm = NULL; 1562a8c21a54SThe etnaviv authors } 1563a8c21a54SThe etnaviv authors 1564a8c21a54SThe etnaviv authors static const struct component_ops gpu_ops = { 1565a8c21a54SThe etnaviv authors .bind = etnaviv_gpu_bind, 1566a8c21a54SThe etnaviv authors .unbind = etnaviv_gpu_unbind, 1567a8c21a54SThe etnaviv authors }; 1568a8c21a54SThe etnaviv authors 1569a8c21a54SThe etnaviv authors static const struct of_device_id etnaviv_gpu_match[] = { 1570a8c21a54SThe etnaviv authors { 1571a8c21a54SThe etnaviv authors .compatible = "vivante,gc" 1572a8c21a54SThe etnaviv authors }, 1573a8c21a54SThe etnaviv authors { /* sentinel */ } 1574a8c21a54SThe etnaviv authors }; 1575a8c21a54SThe etnaviv authors 1576a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1577a8c21a54SThe etnaviv authors { 1578a8c21a54SThe etnaviv authors struct device *dev = &pdev->dev; 1579a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1580dc227890SFabio Estevam int err; 1581a8c21a54SThe etnaviv authors 1582a8c21a54SThe etnaviv authors gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1583a8c21a54SThe etnaviv authors if (!gpu) 1584a8c21a54SThe etnaviv authors return -ENOMEM; 1585a8c21a54SThe etnaviv authors 1586a8c21a54SThe etnaviv authors gpu->dev = &pdev->dev; 1587a8c21a54SThe etnaviv authors mutex_init(&gpu->lock); 1588a8c21a54SThe etnaviv authors 1589a8c21a54SThe etnaviv authors /* Map registers: */ 1590a8c21a54SThe etnaviv authors gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); 1591a8c21a54SThe etnaviv authors if (IS_ERR(gpu->mmio)) 1592a8c21a54SThe etnaviv authors return PTR_ERR(gpu->mmio); 1593a8c21a54SThe etnaviv authors 1594a8c21a54SThe etnaviv authors /* Get Interrupt: */ 1595a8c21a54SThe etnaviv authors gpu->irq = platform_get_irq(pdev, 0); 1596a8c21a54SThe etnaviv authors if (gpu->irq < 0) { 1597db60eda3SFabio Estevam dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1598db60eda3SFabio Estevam return gpu->irq; 1599a8c21a54SThe etnaviv authors } 1600a8c21a54SThe etnaviv authors 1601a8c21a54SThe etnaviv authors err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1602a8c21a54SThe etnaviv authors dev_name(gpu->dev), gpu); 1603a8c21a54SThe etnaviv authors if (err) { 1604a8c21a54SThe etnaviv authors dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1605db60eda3SFabio Estevam return err; 1606a8c21a54SThe etnaviv authors } 1607a8c21a54SThe etnaviv authors 1608a8c21a54SThe etnaviv authors /* Get Clocks: */ 1609a8c21a54SThe etnaviv authors gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1610a8c21a54SThe etnaviv authors DBG("clk_bus: %p", gpu->clk_bus); 1611a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_bus)) 1612a8c21a54SThe etnaviv authors gpu->clk_bus = NULL; 1613a8c21a54SThe etnaviv authors 1614a8c21a54SThe etnaviv authors gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1615a8c21a54SThe etnaviv authors DBG("clk_core: %p", gpu->clk_core); 1616a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_core)) 1617a8c21a54SThe etnaviv authors gpu->clk_core = NULL; 1618a8c21a54SThe etnaviv authors 1619a8c21a54SThe etnaviv authors gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1620a8c21a54SThe etnaviv authors DBG("clk_shader: %p", gpu->clk_shader); 1621a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_shader)) 1622a8c21a54SThe etnaviv authors gpu->clk_shader = NULL; 1623a8c21a54SThe etnaviv authors 1624a8c21a54SThe etnaviv authors /* TODO: figure out max mapped size */ 1625a8c21a54SThe etnaviv authors dev_set_drvdata(dev, gpu); 1626a8c21a54SThe etnaviv authors 1627a8c21a54SThe etnaviv authors /* 1628a8c21a54SThe etnaviv authors * We treat the device as initially suspended. The runtime PM 1629a8c21a54SThe etnaviv authors * autosuspend delay is rather arbitary: no measurements have 1630a8c21a54SThe etnaviv authors * yet been performed to determine an appropriate value. 1631a8c21a54SThe etnaviv authors */ 1632a8c21a54SThe etnaviv authors pm_runtime_use_autosuspend(gpu->dev); 1633a8c21a54SThe etnaviv authors pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1634a8c21a54SThe etnaviv authors pm_runtime_enable(gpu->dev); 1635a8c21a54SThe etnaviv authors 1636a8c21a54SThe etnaviv authors err = component_add(&pdev->dev, &gpu_ops); 1637a8c21a54SThe etnaviv authors if (err < 0) { 1638a8c21a54SThe etnaviv authors dev_err(&pdev->dev, "failed to register component: %d\n", err); 1639db60eda3SFabio Estevam return err; 1640a8c21a54SThe etnaviv authors } 1641a8c21a54SThe etnaviv authors 1642a8c21a54SThe etnaviv authors return 0; 1643a8c21a54SThe etnaviv authors } 1644a8c21a54SThe etnaviv authors 1645a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1646a8c21a54SThe etnaviv authors { 1647a8c21a54SThe etnaviv authors component_del(&pdev->dev, &gpu_ops); 1648a8c21a54SThe etnaviv authors pm_runtime_disable(&pdev->dev); 1649a8c21a54SThe etnaviv authors return 0; 1650a8c21a54SThe etnaviv authors } 1651a8c21a54SThe etnaviv authors 1652a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1653a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_suspend(struct device *dev) 1654a8c21a54SThe etnaviv authors { 1655a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1656a8c21a54SThe etnaviv authors u32 idle, mask; 1657a8c21a54SThe etnaviv authors 1658a8c21a54SThe etnaviv authors /* If we have outstanding fences, we're not idle */ 1659a8c21a54SThe etnaviv authors if (gpu->completed_fence != gpu->active_fence) 1660a8c21a54SThe etnaviv authors return -EBUSY; 1661a8c21a54SThe etnaviv authors 1662a8c21a54SThe etnaviv authors /* Check whether the hardware (except FE) is idle */ 1663a8c21a54SThe etnaviv authors mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1664a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1665a8c21a54SThe etnaviv authors if (idle != mask) 1666a8c21a54SThe etnaviv authors return -EBUSY; 1667a8c21a54SThe etnaviv authors 1668a8c21a54SThe etnaviv authors return etnaviv_gpu_hw_suspend(gpu); 1669a8c21a54SThe etnaviv authors } 1670a8c21a54SThe etnaviv authors 1671a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_resume(struct device *dev) 1672a8c21a54SThe etnaviv authors { 1673a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1674a8c21a54SThe etnaviv authors int ret; 1675a8c21a54SThe etnaviv authors 1676a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1677a8c21a54SThe etnaviv authors if (ret) 1678a8c21a54SThe etnaviv authors return ret; 1679a8c21a54SThe etnaviv authors 1680a8c21a54SThe etnaviv authors /* Re-initialise the basic hardware state */ 1681a8c21a54SThe etnaviv authors if (gpu->drm && gpu->buffer) { 1682a8c21a54SThe etnaviv authors ret = etnaviv_gpu_hw_resume(gpu); 1683a8c21a54SThe etnaviv authors if (ret) { 1684a8c21a54SThe etnaviv authors etnaviv_gpu_clk_disable(gpu); 1685a8c21a54SThe etnaviv authors return ret; 1686a8c21a54SThe etnaviv authors } 1687a8c21a54SThe etnaviv authors } 1688a8c21a54SThe etnaviv authors 1689a8c21a54SThe etnaviv authors return 0; 1690a8c21a54SThe etnaviv authors } 1691a8c21a54SThe etnaviv authors #endif 1692a8c21a54SThe etnaviv authors 1693a8c21a54SThe etnaviv authors static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1694a8c21a54SThe etnaviv authors SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1695a8c21a54SThe etnaviv authors NULL) 1696a8c21a54SThe etnaviv authors }; 1697a8c21a54SThe etnaviv authors 1698a8c21a54SThe etnaviv authors struct platform_driver etnaviv_gpu_driver = { 1699a8c21a54SThe etnaviv authors .driver = { 1700a8c21a54SThe etnaviv authors .name = "etnaviv-gpu", 1701a8c21a54SThe etnaviv authors .owner = THIS_MODULE, 1702a8c21a54SThe etnaviv authors .pm = &etnaviv_gpu_pm_ops, 1703a8c21a54SThe etnaviv authors .of_match_table = etnaviv_gpu_match, 1704a8c21a54SThe etnaviv authors }, 1705a8c21a54SThe etnaviv authors .probe = etnaviv_gpu_platform_probe, 1706a8c21a54SThe etnaviv authors .remove = etnaviv_gpu_platform_remove, 1707a8c21a54SThe etnaviv authors .id_table = gpu_ids, 1708a8c21a54SThe etnaviv authors }; 1709