1f6ffbd4fSLucas Stach // SPDX-License-Identifier: GPL-2.0 2a8c21a54SThe etnaviv authors /* 3f6ffbd4fSLucas Stach * Copyright (C) 2015-2018 Etnaviv Project 4a8c21a54SThe etnaviv authors */ 5a8c21a54SThe etnaviv authors 6f9d255f4SLucas Stach #include <linux/clk.h> 7a8c21a54SThe etnaviv authors #include <linux/component.h> 86eae41feSSam Ravnborg #include <linux/delay.h> 9f54d1867SChris Wilson #include <linux/dma-fence.h> 106eae41feSSam Ravnborg #include <linux/dma-mapping.h> 112e737e52SLucas Stach #include <linux/module.h> 12a8c21a54SThe etnaviv authors #include <linux/of_device.h> 132e737e52SLucas Stach #include <linux/platform_device.h> 142e737e52SLucas Stach #include <linux/pm_runtime.h> 15f9d255f4SLucas Stach #include <linux/regulator/consumer.h> 16bcdfb5e5SRussell King #include <linux/thermal.h> 17ea1f5729SLucas Stach 18ea1f5729SLucas Stach #include "etnaviv_cmdbuf.h" 19a8c21a54SThe etnaviv authors #include "etnaviv_dump.h" 20a8c21a54SThe etnaviv authors #include "etnaviv_gpu.h" 21a8c21a54SThe etnaviv authors #include "etnaviv_gem.h" 22a8c21a54SThe etnaviv authors #include "etnaviv_mmu.h" 23357713ceSChristian Gmeiner #include "etnaviv_perfmon.h" 24e93b6deeSLucas Stach #include "etnaviv_sched.h" 25a8c21a54SThe etnaviv authors #include "common.xml.h" 26a8c21a54SThe etnaviv authors #include "state.xml.h" 27a8c21a54SThe etnaviv authors #include "state_hi.xml.h" 28a8c21a54SThe etnaviv authors #include "cmdstream.xml.h" 29a8c21a54SThe etnaviv authors 30a8c21a54SThe etnaviv authors static const struct platform_device_id gpu_ids[] = { 31a8c21a54SThe etnaviv authors { .name = "etnaviv-gpu,2d" }, 32a8c21a54SThe etnaviv authors { }, 33a8c21a54SThe etnaviv authors }; 34a8c21a54SThe etnaviv authors 35a8c21a54SThe etnaviv authors /* 36a8c21a54SThe etnaviv authors * Driver functions: 37a8c21a54SThe etnaviv authors */ 38a8c21a54SThe etnaviv authors 39a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 40a8c21a54SThe etnaviv authors { 41088880ddSLucas Stach struct etnaviv_drm_private *priv = gpu->drm->dev_private; 42088880ddSLucas Stach 43a8c21a54SThe etnaviv authors switch (param) { 44a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_MODEL: 45a8c21a54SThe etnaviv authors *value = gpu->identity.model; 46a8c21a54SThe etnaviv authors break; 47a8c21a54SThe etnaviv authors 48a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REVISION: 49a8c21a54SThe etnaviv authors *value = gpu->identity.revision; 50a8c21a54SThe etnaviv authors break; 51a8c21a54SThe etnaviv authors 52a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_0: 53a8c21a54SThe etnaviv authors *value = gpu->identity.features; 54a8c21a54SThe etnaviv authors break; 55a8c21a54SThe etnaviv authors 56a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_1: 57a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features0; 58a8c21a54SThe etnaviv authors break; 59a8c21a54SThe etnaviv authors 60a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_2: 61a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features1; 62a8c21a54SThe etnaviv authors break; 63a8c21a54SThe etnaviv authors 64a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_3: 65a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features2; 66a8c21a54SThe etnaviv authors break; 67a8c21a54SThe etnaviv authors 68a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_4: 69a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features3; 70a8c21a54SThe etnaviv authors break; 71a8c21a54SThe etnaviv authors 72602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_5: 73602eb489SRussell King *value = gpu->identity.minor_features4; 74602eb489SRussell King break; 75602eb489SRussell King 76602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_6: 77602eb489SRussell King *value = gpu->identity.minor_features5; 78602eb489SRussell King break; 79602eb489SRussell King 800538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_7: 810538aaf9SLucas Stach *value = gpu->identity.minor_features6; 820538aaf9SLucas Stach break; 830538aaf9SLucas Stach 840538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_8: 850538aaf9SLucas Stach *value = gpu->identity.minor_features7; 860538aaf9SLucas Stach break; 870538aaf9SLucas Stach 880538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_9: 890538aaf9SLucas Stach *value = gpu->identity.minor_features8; 900538aaf9SLucas Stach break; 910538aaf9SLucas Stach 920538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_10: 930538aaf9SLucas Stach *value = gpu->identity.minor_features9; 940538aaf9SLucas Stach break; 950538aaf9SLucas Stach 960538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_11: 970538aaf9SLucas Stach *value = gpu->identity.minor_features10; 980538aaf9SLucas Stach break; 990538aaf9SLucas Stach 1000538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_12: 1010538aaf9SLucas Stach *value = gpu->identity.minor_features11; 1020538aaf9SLucas Stach break; 1030538aaf9SLucas Stach 104a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_STREAM_COUNT: 105a8c21a54SThe etnaviv authors *value = gpu->identity.stream_count; 106a8c21a54SThe etnaviv authors break; 107a8c21a54SThe etnaviv authors 108a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REGISTER_MAX: 109a8c21a54SThe etnaviv authors *value = gpu->identity.register_max; 110a8c21a54SThe etnaviv authors break; 111a8c21a54SThe etnaviv authors 112a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_THREAD_COUNT: 113a8c21a54SThe etnaviv authors *value = gpu->identity.thread_count; 114a8c21a54SThe etnaviv authors break; 115a8c21a54SThe etnaviv authors 116a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 117a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_cache_size; 118a8c21a54SThe etnaviv authors break; 119a8c21a54SThe etnaviv authors 120a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 121a8c21a54SThe etnaviv authors *value = gpu->identity.shader_core_count; 122a8c21a54SThe etnaviv authors break; 123a8c21a54SThe etnaviv authors 124a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 125a8c21a54SThe etnaviv authors *value = gpu->identity.pixel_pipes; 126a8c21a54SThe etnaviv authors break; 127a8c21a54SThe etnaviv authors 128a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 129a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_output_buffer_size; 130a8c21a54SThe etnaviv authors break; 131a8c21a54SThe etnaviv authors 132a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 133a8c21a54SThe etnaviv authors *value = gpu->identity.buffer_size; 134a8c21a54SThe etnaviv authors break; 135a8c21a54SThe etnaviv authors 136a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 137a8c21a54SThe etnaviv authors *value = gpu->identity.instruction_count; 138a8c21a54SThe etnaviv authors break; 139a8c21a54SThe etnaviv authors 140a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 141a8c21a54SThe etnaviv authors *value = gpu->identity.num_constants; 142a8c21a54SThe etnaviv authors break; 143a8c21a54SThe etnaviv authors 144602eb489SRussell King case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 145602eb489SRussell King *value = gpu->identity.varyings_count; 146602eb489SRussell King break; 147602eb489SRussell King 148088880ddSLucas Stach case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 149088880ddSLucas Stach if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 150088880ddSLucas Stach *value = ETNAVIV_SOFTPIN_START_ADDRESS; 151088880ddSLucas Stach else 152088880ddSLucas Stach *value = ~0ULL; 153088880ddSLucas Stach break; 154088880ddSLucas Stach 1551ff79a4aSChristian Gmeiner case ETNAVIV_PARAM_GPU_PRODUCT_ID: 1561ff79a4aSChristian Gmeiner *value = gpu->identity.product_id; 1571ff79a4aSChristian Gmeiner break; 1581ff79a4aSChristian Gmeiner 1591ff79a4aSChristian Gmeiner case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 1601ff79a4aSChristian Gmeiner *value = gpu->identity.customer_id; 1611ff79a4aSChristian Gmeiner break; 1621ff79a4aSChristian Gmeiner 1631ff79a4aSChristian Gmeiner case ETNAVIV_PARAM_GPU_ECO_ID: 1641ff79a4aSChristian Gmeiner *value = gpu->identity.eco_id; 1651ff79a4aSChristian Gmeiner break; 1661ff79a4aSChristian Gmeiner 167a8c21a54SThe etnaviv authors default: 168a8c21a54SThe etnaviv authors DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 169a8c21a54SThe etnaviv authors return -EINVAL; 170a8c21a54SThe etnaviv authors } 171a8c21a54SThe etnaviv authors 172a8c21a54SThe etnaviv authors return 0; 173a8c21a54SThe etnaviv authors } 174a8c21a54SThe etnaviv authors 175472f79dcSRussell King 176472f79dcSRussell King #define etnaviv_is_model_rev(gpu, mod, rev) \ 177472f79dcSRussell King ((gpu)->identity.model == chipModel_##mod && \ 178472f79dcSRussell King (gpu)->identity.revision == rev) 17952f36ba1SRussell King #define etnaviv_field(val, field) \ 18052f36ba1SRussell King (((val) & field##__MASK) >> field##__SHIFT) 18152f36ba1SRussell King 182a8c21a54SThe etnaviv authors static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 183a8c21a54SThe etnaviv authors { 184a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 185a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 186602eb489SRussell King u32 specs[4]; 187602eb489SRussell King unsigned int streams; 188a8c21a54SThe etnaviv authors 189a8c21a54SThe etnaviv authors specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 190a8c21a54SThe etnaviv authors specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 191602eb489SRussell King specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 192602eb489SRussell King specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 193a8c21a54SThe etnaviv authors 19452f36ba1SRussell King gpu->identity.stream_count = etnaviv_field(specs[0], 19552f36ba1SRussell King VIVS_HI_CHIP_SPECS_STREAM_COUNT); 19652f36ba1SRussell King gpu->identity.register_max = etnaviv_field(specs[0], 19752f36ba1SRussell King VIVS_HI_CHIP_SPECS_REGISTER_MAX); 19852f36ba1SRussell King gpu->identity.thread_count = etnaviv_field(specs[0], 19952f36ba1SRussell King VIVS_HI_CHIP_SPECS_THREAD_COUNT); 20052f36ba1SRussell King gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 20152f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 20252f36ba1SRussell King gpu->identity.shader_core_count = etnaviv_field(specs[0], 20352f36ba1SRussell King VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 20452f36ba1SRussell King gpu->identity.pixel_pipes = etnaviv_field(specs[0], 20552f36ba1SRussell King VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 206a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 20752f36ba1SRussell King etnaviv_field(specs[0], 20852f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 209a8c21a54SThe etnaviv authors 21052f36ba1SRussell King gpu->identity.buffer_size = etnaviv_field(specs[1], 21152f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 21252f36ba1SRussell King gpu->identity.instruction_count = etnaviv_field(specs[1], 21352f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 21452f36ba1SRussell King gpu->identity.num_constants = etnaviv_field(specs[1], 21552f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 216602eb489SRussell King 217602eb489SRussell King gpu->identity.varyings_count = etnaviv_field(specs[2], 218602eb489SRussell King VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 219602eb489SRussell King 220602eb489SRussell King /* This overrides the value from older register if non-zero */ 221602eb489SRussell King streams = etnaviv_field(specs[3], 222602eb489SRussell King VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 223602eb489SRussell King if (streams) 224602eb489SRussell King gpu->identity.stream_count = streams; 225a8c21a54SThe etnaviv authors } 226a8c21a54SThe etnaviv authors 227a8c21a54SThe etnaviv authors /* Fill in the stream count if not specified */ 228a8c21a54SThe etnaviv authors if (gpu->identity.stream_count == 0) { 229a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 230a8c21a54SThe etnaviv authors gpu->identity.stream_count = 4; 231a8c21a54SThe etnaviv authors else 232a8c21a54SThe etnaviv authors gpu->identity.stream_count = 1; 233a8c21a54SThe etnaviv authors } 234a8c21a54SThe etnaviv authors 235a8c21a54SThe etnaviv authors /* Convert the register max value */ 236a8c21a54SThe etnaviv authors if (gpu->identity.register_max) 237a8c21a54SThe etnaviv authors gpu->identity.register_max = 1 << gpu->identity.register_max; 238507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 239a8c21a54SThe etnaviv authors gpu->identity.register_max = 32; 240a8c21a54SThe etnaviv authors else 241a8c21a54SThe etnaviv authors gpu->identity.register_max = 64; 242a8c21a54SThe etnaviv authors 243a8c21a54SThe etnaviv authors /* Convert thread count */ 244a8c21a54SThe etnaviv authors if (gpu->identity.thread_count) 245a8c21a54SThe etnaviv authors gpu->identity.thread_count = 1 << gpu->identity.thread_count; 246507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 247a8c21a54SThe etnaviv authors gpu->identity.thread_count = 64; 248507f8991SRussell King else if (gpu->identity.model == chipModel_GC500 || 249507f8991SRussell King gpu->identity.model == chipModel_GC530) 250a8c21a54SThe etnaviv authors gpu->identity.thread_count = 128; 251a8c21a54SThe etnaviv authors else 252a8c21a54SThe etnaviv authors gpu->identity.thread_count = 256; 253a8c21a54SThe etnaviv authors 254a8c21a54SThe etnaviv authors if (gpu->identity.vertex_cache_size == 0) 255a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size = 8; 256a8c21a54SThe etnaviv authors 257a8c21a54SThe etnaviv authors if (gpu->identity.shader_core_count == 0) { 258a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 259a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 2; 260a8c21a54SThe etnaviv authors else 261a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 1; 262a8c21a54SThe etnaviv authors } 263a8c21a54SThe etnaviv authors 264a8c21a54SThe etnaviv authors if (gpu->identity.pixel_pipes == 0) 265a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes = 1; 266a8c21a54SThe etnaviv authors 267a8c21a54SThe etnaviv authors /* Convert virtex buffer size */ 268a8c21a54SThe etnaviv authors if (gpu->identity.vertex_output_buffer_size) { 269a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 270a8c21a54SThe etnaviv authors 1 << gpu->identity.vertex_output_buffer_size; 271507f8991SRussell King } else if (gpu->identity.model == chipModel_GC400) { 272a8c21a54SThe etnaviv authors if (gpu->identity.revision < 0x4000) 273a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 274a8c21a54SThe etnaviv authors else if (gpu->identity.revision < 0x4200) 275a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 256; 276a8c21a54SThe etnaviv authors else 277a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 128; 278a8c21a54SThe etnaviv authors } else { 279a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 280a8c21a54SThe etnaviv authors } 281a8c21a54SThe etnaviv authors 282a8c21a54SThe etnaviv authors switch (gpu->identity.instruction_count) { 283a8c21a54SThe etnaviv authors case 0: 284472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 285507f8991SRussell King gpu->identity.model == chipModel_GC880) 286a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 512; 287a8c21a54SThe etnaviv authors else 288a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 289a8c21a54SThe etnaviv authors break; 290a8c21a54SThe etnaviv authors 291a8c21a54SThe etnaviv authors case 1: 292a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 1024; 293a8c21a54SThe etnaviv authors break; 294a8c21a54SThe etnaviv authors 295a8c21a54SThe etnaviv authors case 2: 296a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 2048; 297a8c21a54SThe etnaviv authors break; 298a8c21a54SThe etnaviv authors 299a8c21a54SThe etnaviv authors default: 300a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 301a8c21a54SThe etnaviv authors break; 302a8c21a54SThe etnaviv authors } 303a8c21a54SThe etnaviv authors 304a8c21a54SThe etnaviv authors if (gpu->identity.num_constants == 0) 305a8c21a54SThe etnaviv authors gpu->identity.num_constants = 168; 306602eb489SRussell King 307602eb489SRussell King if (gpu->identity.varyings_count == 0) { 308602eb489SRussell King if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 309602eb489SRussell King gpu->identity.varyings_count = 12; 310602eb489SRussell King else 311602eb489SRussell King gpu->identity.varyings_count = 8; 312602eb489SRussell King } 313602eb489SRussell King 314602eb489SRussell King /* 315602eb489SRussell King * For some cores, two varyings are consumed for position, so the 316602eb489SRussell King * maximum varying count needs to be reduced by one. 317602eb489SRussell King */ 318602eb489SRussell King if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 319602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 320602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 321602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 322602eb489SRussell King etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 323602eb489SRussell King etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 324602eb489SRussell King etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 325602eb489SRussell King etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 326602eb489SRussell King etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 327602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5107) || 328602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5106)) 329602eb489SRussell King gpu->identity.varyings_count -= 1; 330a8c21a54SThe etnaviv authors } 331a8c21a54SThe etnaviv authors 332a8c21a54SThe etnaviv authors static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 333a8c21a54SThe etnaviv authors { 334a8c21a54SThe etnaviv authors u32 chipIdentity; 335a8c21a54SThe etnaviv authors 336a8c21a54SThe etnaviv authors chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 337a8c21a54SThe etnaviv authors 338a8c21a54SThe etnaviv authors /* Special case for older graphic cores. */ 33952f36ba1SRussell King if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 340507f8991SRussell King gpu->identity.model = chipModel_GC500; 34152f36ba1SRussell King gpu->identity.revision = etnaviv_field(chipIdentity, 34252f36ba1SRussell King VIVS_HI_CHIP_IDENTITY_REVISION); 343a8c21a54SThe etnaviv authors } else { 344815e45bbSChristian Gmeiner u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 345a8c21a54SThe etnaviv authors 346a8c21a54SThe etnaviv authors gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 347a8c21a54SThe etnaviv authors gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 348815e45bbSChristian Gmeiner gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 3492c5bf028SChristian Gmeiner 3502c5bf028SChristian Gmeiner /* 3512c5bf028SChristian Gmeiner * Reading these two registers on GC600 rev 0x19 result in a 3522c5bf028SChristian Gmeiner * unhandled fault: external abort on non-linefetch 3532c5bf028SChristian Gmeiner */ 3542c5bf028SChristian Gmeiner if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { 3552c5bf028SChristian Gmeiner gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 356815e45bbSChristian Gmeiner gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 3572c5bf028SChristian Gmeiner } 358a8c21a54SThe etnaviv authors 359a8c21a54SThe etnaviv authors /* 360a8c21a54SThe etnaviv authors * !!!! HACK ALERT !!!! 361a8c21a54SThe etnaviv authors * Because people change device IDs without letting software 362a8c21a54SThe etnaviv authors * know about it - here is the hack to make it all look the 363a8c21a54SThe etnaviv authors * same. Only for GC400 family. 364a8c21a54SThe etnaviv authors */ 365a8c21a54SThe etnaviv authors if ((gpu->identity.model & 0xff00) == 0x0400 && 366507f8991SRussell King gpu->identity.model != chipModel_GC420) { 367a8c21a54SThe etnaviv authors gpu->identity.model = gpu->identity.model & 0x0400; 368a8c21a54SThe etnaviv authors } 369a8c21a54SThe etnaviv authors 370a8c21a54SThe etnaviv authors /* Another special case */ 371472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 372a8c21a54SThe etnaviv authors u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 373a8c21a54SThe etnaviv authors 374a8c21a54SThe etnaviv authors if (chipDate == 0x20080814 && chipTime == 0x12051100) { 375a8c21a54SThe etnaviv authors /* 376a8c21a54SThe etnaviv authors * This IP has an ECO; put the correct 377a8c21a54SThe etnaviv authors * revision in it. 378a8c21a54SThe etnaviv authors */ 379a8c21a54SThe etnaviv authors gpu->identity.revision = 0x1051; 380a8c21a54SThe etnaviv authors } 381a8c21a54SThe etnaviv authors } 38212ff4bdeSLucas Stach 38312ff4bdeSLucas Stach /* 38412ff4bdeSLucas Stach * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 38512ff4bdeSLucas Stach * reality it's just a re-branded GC3000. We can identify this 38612ff4bdeSLucas Stach * core by the upper half of the revision register being all 1. 38712ff4bdeSLucas Stach * Fix model/rev here, so all other places can refer to this 38812ff4bdeSLucas Stach * core by its real identity. 38912ff4bdeSLucas Stach */ 39012ff4bdeSLucas Stach if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 39112ff4bdeSLucas Stach gpu->identity.model = chipModel_GC3000; 39212ff4bdeSLucas Stach gpu->identity.revision &= 0xffff; 39312ff4bdeSLucas Stach } 394815e45bbSChristian Gmeiner 395815e45bbSChristian Gmeiner if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) 396815e45bbSChristian Gmeiner gpu->identity.eco_id = 1; 397815e45bbSChristian Gmeiner 398815e45bbSChristian Gmeiner if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) 399815e45bbSChristian Gmeiner gpu->identity.eco_id = 1; 400a8c21a54SThe etnaviv authors } 401a8c21a54SThe etnaviv authors 402a8c21a54SThe etnaviv authors dev_info(gpu->dev, "model: GC%x, revision: %x\n", 403a8c21a54SThe etnaviv authors gpu->identity.model, gpu->identity.revision); 404a8c21a54SThe etnaviv authors 4052b76f5beSLucas Stach gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 406681c19c8SLucas Stach /* 407681c19c8SLucas Stach * If there is a match in the HWDB, we aren't interested in the 408681c19c8SLucas Stach * remaining register values, as they might be wrong. 409681c19c8SLucas Stach */ 410681c19c8SLucas Stach if (etnaviv_fill_identity_from_hwdb(gpu)) 411681c19c8SLucas Stach return; 412681c19c8SLucas Stach 413a8c21a54SThe etnaviv authors gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 414a8c21a54SThe etnaviv authors 415a8c21a54SThe etnaviv authors /* Disable fast clear on GC700. */ 416507f8991SRussell King if (gpu->identity.model == chipModel_GC700) 417a8c21a54SThe etnaviv authors gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 418a8c21a54SThe etnaviv authors 419*cc7d3fb4SDoug Brown /* These models/revisions don't have the 2D pipe bit */ 420*cc7d3fb4SDoug Brown if ((gpu->identity.model == chipModel_GC500 && 421*cc7d3fb4SDoug Brown gpu->identity.revision <= 2) || 422*cc7d3fb4SDoug Brown gpu->identity.model == chipModel_GC300) 423*cc7d3fb4SDoug Brown gpu->identity.features |= chipFeatures_PIPE_2D; 424*cc7d3fb4SDoug Brown 425507f8991SRussell King if ((gpu->identity.model == chipModel_GC500 && 426507f8991SRussell King gpu->identity.revision < 2) || 427507f8991SRussell King (gpu->identity.model == chipModel_GC300 && 428507f8991SRussell King gpu->identity.revision < 0x2000)) { 429a8c21a54SThe etnaviv authors 430a8c21a54SThe etnaviv authors /* 431a8c21a54SThe etnaviv authors * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 432a8c21a54SThe etnaviv authors * registers. 433a8c21a54SThe etnaviv authors */ 434a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 0; 435a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 0; 436a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 0; 437a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 0; 438602eb489SRussell King gpu->identity.minor_features4 = 0; 439602eb489SRussell King gpu->identity.minor_features5 = 0; 440a8c21a54SThe etnaviv authors } else 441a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 442a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 443a8c21a54SThe etnaviv authors 444a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 445a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 446a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 447a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 448a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 449a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 450a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 451a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 452602eb489SRussell King gpu->identity.minor_features4 = 453602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 454602eb489SRussell King gpu->identity.minor_features5 = 455602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 456a8c21a54SThe etnaviv authors } 457a8c21a54SThe etnaviv authors 458*cc7d3fb4SDoug Brown /* GC600/300 idle register reports zero bits where modules aren't present */ 459*cc7d3fb4SDoug Brown if (gpu->identity.model == chipModel_GC600 || 460*cc7d3fb4SDoug Brown gpu->identity.model == chipModel_GC300) 461a8c21a54SThe etnaviv authors gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 462a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_RA | 463a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SE | 464a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PA | 465a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SH | 466a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PE | 467a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_DE | 468a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_FE; 469a8c21a54SThe etnaviv authors 470a8c21a54SThe etnaviv authors etnaviv_hw_specs(gpu); 471a8c21a54SThe etnaviv authors } 472a8c21a54SThe etnaviv authors 473a8c21a54SThe etnaviv authors static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 474a8c21a54SThe etnaviv authors { 475a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 476a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 477a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 478a8c21a54SThe etnaviv authors } 479a8c21a54SThe etnaviv authors 480bcdfb5e5SRussell King static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 481bcdfb5e5SRussell King { 482d79fd1ccSLucas Stach if (gpu->identity.minor_features2 & 483d79fd1ccSLucas Stach chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 484d79fd1ccSLucas Stach clk_set_rate(gpu->clk_core, 485d79fd1ccSLucas Stach gpu->base_rate_core >> gpu->freq_scale); 486d79fd1ccSLucas Stach clk_set_rate(gpu->clk_shader, 487d79fd1ccSLucas Stach gpu->base_rate_shader >> gpu->freq_scale); 488d79fd1ccSLucas Stach } else { 489bcdfb5e5SRussell King unsigned int fscale = 1 << (6 - gpu->freq_scale); 4906eb3ecc3SLucas Stach u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 491bcdfb5e5SRussell King 4926eb3ecc3SLucas Stach clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 4936eb3ecc3SLucas Stach clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 494bcdfb5e5SRussell King etnaviv_gpu_load_clock(gpu, clock); 495bcdfb5e5SRussell King } 496d79fd1ccSLucas Stach } 497bcdfb5e5SRussell King 498a8c21a54SThe etnaviv authors static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 499a8c21a54SThe etnaviv authors { 500a8c21a54SThe etnaviv authors u32 control, idle; 501a8c21a54SThe etnaviv authors unsigned long timeout; 502a8c21a54SThe etnaviv authors bool failed = true; 503a8c21a54SThe etnaviv authors 504a8c21a54SThe etnaviv authors /* We hope that the GPU resets in under one second */ 505a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(1000); 506a8c21a54SThe etnaviv authors 507a8c21a54SThe etnaviv authors while (time_is_after_jiffies(timeout)) { 508a8c21a54SThe etnaviv authors /* enable clock */ 5096eb3ecc3SLucas Stach unsigned int fscale = 1 << (6 - gpu->freq_scale); 5106eb3ecc3SLucas Stach control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 5116eb3ecc3SLucas Stach etnaviv_gpu_load_clock(gpu, control); 512a8c21a54SThe etnaviv authors 513a8c21a54SThe etnaviv authors /* isolate the GPU. */ 514a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 515a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 516a8c21a54SThe etnaviv authors 517c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 518c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 519c997c3dfSLucas Stach VIVS_MMUv2_AHB_CONTROL_RESET); 520c997c3dfSLucas Stach } else { 521a8c21a54SThe etnaviv authors /* set soft reset. */ 522a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 523a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 524c997c3dfSLucas Stach } 525a8c21a54SThe etnaviv authors 526a8c21a54SThe etnaviv authors /* wait for reset. */ 52740462179SPhilipp Zabel usleep_range(10, 20); 528a8c21a54SThe etnaviv authors 529a8c21a54SThe etnaviv authors /* reset soft reset bit. */ 530a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 531a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 532a8c21a54SThe etnaviv authors 533a8c21a54SThe etnaviv authors /* reset GPU isolation. */ 534a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 535a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 536a8c21a54SThe etnaviv authors 537a8c21a54SThe etnaviv authors /* read idle register. */ 538a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 539a8c21a54SThe etnaviv authors 540ea4ed4a5SGuido Günther /* try resetting again if FE is not idle */ 541a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 542a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "FE is not idle\n"); 543a8c21a54SThe etnaviv authors continue; 544a8c21a54SThe etnaviv authors } 545a8c21a54SThe etnaviv authors 546a8c21a54SThe etnaviv authors /* read reset register. */ 547a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 548a8c21a54SThe etnaviv authors 549a8c21a54SThe etnaviv authors /* is the GPU idle? */ 550a8c21a54SThe etnaviv authors if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 551a8c21a54SThe etnaviv authors ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 552a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "GPU is not idle\n"); 553a8c21a54SThe etnaviv authors continue; 554a8c21a54SThe etnaviv authors } 555a8c21a54SThe etnaviv authors 5566eb3ecc3SLucas Stach /* disable debug registers, as they are not normally needed */ 5576eb3ecc3SLucas Stach control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 5586eb3ecc3SLucas Stach gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 5596eb3ecc3SLucas Stach 560a8c21a54SThe etnaviv authors failed = false; 561a8c21a54SThe etnaviv authors break; 562a8c21a54SThe etnaviv authors } 563a8c21a54SThe etnaviv authors 564a8c21a54SThe etnaviv authors if (failed) { 565a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 566a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 567a8c21a54SThe etnaviv authors 568a8c21a54SThe etnaviv authors dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 569a8c21a54SThe etnaviv authors idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 570a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 571a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 572a8c21a54SThe etnaviv authors 573a8c21a54SThe etnaviv authors return -EBUSY; 574a8c21a54SThe etnaviv authors } 575a8c21a54SThe etnaviv authors 576a8c21a54SThe etnaviv authors /* We rely on the GPU running, so program the clock */ 577bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 578a8c21a54SThe etnaviv authors 57923e0f5a5SLucas Stach gpu->fe_running = false; 580725cbc78SLucas Stach gpu->exec_state = -1; 581f978a530SLucas Stach if (gpu->mmu_context) 582f978a530SLucas Stach etnaviv_iommu_context_put(gpu->mmu_context); 583725cbc78SLucas Stach gpu->mmu_context = NULL; 58423e0f5a5SLucas Stach 585a8c21a54SThe etnaviv authors return 0; 586a8c21a54SThe etnaviv authors } 587a8c21a54SThe etnaviv authors 5887d0c6e71SRussell King static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 5897d0c6e71SRussell King { 5907d0c6e71SRussell King u32 pmc, ppc; 5917d0c6e71SRussell King 5927d0c6e71SRussell King /* enable clock gating */ 5937d0c6e71SRussell King ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 5947d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 5957d0c6e71SRussell King 5967d0c6e71SRussell King /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 5977d0c6e71SRussell King if (gpu->identity.revision == 0x4301 || 5987d0c6e71SRussell King gpu->identity.revision == 0x4302) 5997d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 6007d0c6e71SRussell King 6017d0c6e71SRussell King gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 6027d0c6e71SRussell King 6037d0c6e71SRussell King pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 6047d0c6e71SRussell King 6057cef6004SLucas Stach /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 6067d0c6e71SRussell King if (gpu->identity.model >= chipModel_GC400 && 6077cef6004SLucas Stach gpu->identity.model != chipModel_GC420 && 6087cef6004SLucas Stach !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 6097d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 6107d0c6e71SRussell King 6117d0c6e71SRussell King /* 6127d0c6e71SRussell King * Disable PE clock gating on revs < 5.0.0.0 when HZ is 6137d0c6e71SRussell King * present without a bug fix. 6147d0c6e71SRussell King */ 6157d0c6e71SRussell King if (gpu->identity.revision < 0x5000 && 6167d0c6e71SRussell King gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 6177d0c6e71SRussell King !(gpu->identity.minor_features1 & 6187d0c6e71SRussell King chipMinorFeatures1_DISABLE_PE_GATING)) 6197d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 6207d0c6e71SRussell King 6217d0c6e71SRussell King if (gpu->identity.revision < 0x5422) 6227d0c6e71SRussell King pmc |= BIT(15); /* Unknown bit */ 6237d0c6e71SRussell King 6247cef6004SLucas Stach /* Disable TX clock gating on affected core revisions. */ 6257cef6004SLucas Stach if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 6267cef6004SLucas Stach etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 6277cef6004SLucas Stach pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 6287cef6004SLucas Stach 629432f51e7SMichael Walle /* Disable SE, RA and TX clock gating on affected core revisions. */ 630432f51e7SMichael Walle if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) 631432f51e7SMichael Walle pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 632432f51e7SMichael Walle VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA | 633432f51e7SMichael Walle VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 634432f51e7SMichael Walle 6357d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 6367d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 6377d0c6e71SRussell King 6387d0c6e71SRussell King gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 6397d0c6e71SRussell King } 6407d0c6e71SRussell King 641229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 642229855b6SLucas Stach { 643229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 644229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 645229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_ENABLE | 646229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 647c997c3dfSLucas Stach 648c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 649c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 650c997c3dfSLucas Stach VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 651c997c3dfSLucas Stach VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 652c997c3dfSLucas Stach } 65323e0f5a5SLucas Stach 65423e0f5a5SLucas Stach gpu->fe_running = true; 655229855b6SLucas Stach } 656229855b6SLucas Stach 657d6408538SLucas Stach static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, 658d6408538SLucas Stach struct etnaviv_iommu_context *context) 659d80d842aSLucas Stach { 660d80d842aSLucas Stach u16 prefetch; 661d6408538SLucas Stach u32 address; 662d80d842aSLucas Stach 663d80d842aSLucas Stach /* setup the MMU */ 664d6408538SLucas Stach etnaviv_iommu_restore(gpu, context); 665d80d842aSLucas Stach 666d80d842aSLucas Stach /* Start command processor */ 667d80d842aSLucas Stach prefetch = etnaviv_buffer_init(gpu); 668d6408538SLucas Stach address = etnaviv_cmdbuf_get_va(&gpu->buffer, 669d6408538SLucas Stach &gpu->mmu_context->cmdbuf_mapping); 670d80d842aSLucas Stach 671d80d842aSLucas Stach etnaviv_gpu_start_fe(gpu, address, prefetch); 672d80d842aSLucas Stach } 673d80d842aSLucas Stach 674e17a0dedSWladimir J. van der Laan static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 675e17a0dedSWladimir J. van der Laan { 676e17a0dedSWladimir J. van der Laan /* 677e17a0dedSWladimir J. van der Laan * Base value for VIVS_PM_PULSE_EATER register on models where it 678e17a0dedSWladimir J. van der Laan * cannot be read, extracted from vivante kernel driver. 679e17a0dedSWladimir J. van der Laan */ 680e17a0dedSWladimir J. van der Laan u32 pulse_eater = 0x01590880; 681e17a0dedSWladimir J. van der Laan 682e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 683e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 684e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(23); 685e17a0dedSWladimir J. van der Laan 686e17a0dedSWladimir J. van der Laan } 687e17a0dedSWladimir J. van der Laan 688e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 689e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 690e17a0dedSWladimir J. van der Laan pulse_eater &= ~BIT(16); 691e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(17); 692e17a0dedSWladimir J. van der Laan } 693e17a0dedSWladimir J. van der Laan 694e17a0dedSWladimir J. van der Laan if ((gpu->identity.revision > 0x5420) && 695e17a0dedSWladimir J. van der Laan (gpu->identity.features & chipFeatures_PIPE_3D)) 696e17a0dedSWladimir J. van der Laan { 697e17a0dedSWladimir J. van der Laan /* Performance fix: disable internal DFS */ 698e17a0dedSWladimir J. van der Laan pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 699e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(18); 700e17a0dedSWladimir J. van der Laan } 701e17a0dedSWladimir J. van der Laan 702e17a0dedSWladimir J. van der Laan gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 703e17a0dedSWladimir J. van der Laan } 704e17a0dedSWladimir J. van der Laan 705a8c21a54SThe etnaviv authors static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 706a8c21a54SThe etnaviv authors { 707472f79dcSRussell King if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 708472f79dcSRussell King etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 709472f79dcSRussell King gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 710a8c21a54SThe etnaviv authors u32 mc_memory_debug; 711a8c21a54SThe etnaviv authors 712a8c21a54SThe etnaviv authors mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 713a8c21a54SThe etnaviv authors 714a8c21a54SThe etnaviv authors if (gpu->identity.revision == 0x5007) 715a8c21a54SThe etnaviv authors mc_memory_debug |= 0x0c; 716a8c21a54SThe etnaviv authors else 717a8c21a54SThe etnaviv authors mc_memory_debug |= 0x08; 718a8c21a54SThe etnaviv authors 719a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 720a8c21a54SThe etnaviv authors } 721a8c21a54SThe etnaviv authors 7227d0c6e71SRussell King /* enable module-level clock gating */ 7237d0c6e71SRussell King etnaviv_gpu_enable_mlcg(gpu); 7247d0c6e71SRussell King 725a8c21a54SThe etnaviv authors /* 726a8c21a54SThe etnaviv authors * Update GPU AXI cache atttribute to "cacheable, no allocate". 727a8c21a54SThe etnaviv authors * This is necessary to prevent the iMX6 SoC locking up. 728a8c21a54SThe etnaviv authors */ 729a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_AXI_CONFIG, 730a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_AWCACHE(2) | 731a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_ARCACHE(2)); 732a8c21a54SThe etnaviv authors 733a8c21a54SThe etnaviv authors /* GC2000 rev 5108 needs a special bus config */ 734472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 735a8c21a54SThe etnaviv authors u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 736a8c21a54SThe etnaviv authors bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 737a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 738a8c21a54SThe etnaviv authors bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 739a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 740a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 741a8c21a54SThe etnaviv authors } 742a8c21a54SThe etnaviv authors 743c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 744c997c3dfSLucas Stach u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 745c997c3dfSLucas Stach val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 746c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 747c997c3dfSLucas Stach } 748c997c3dfSLucas Stach 749e17a0dedSWladimir J. van der Laan /* setup the pulse eater */ 750e17a0dedSWladimir J. van der Laan etnaviv_gpu_setup_pulse_eater(gpu); 751e17a0dedSWladimir J. van der Laan 752a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 753a8c21a54SThe etnaviv authors } 754a8c21a54SThe etnaviv authors 755a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 756a8c21a54SThe etnaviv authors { 757bffe5db8SLucas Stach struct etnaviv_drm_private *priv = gpu->drm->dev_private; 7584bfdd2aaSLucas Stach dma_addr_t cmdbuf_paddr; 759a8c21a54SThe etnaviv authors int ret, i; 760a8c21a54SThe etnaviv authors 761a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 7621409df04SLucas Stach if (ret < 0) { 7631409df04SLucas Stach dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 764c5d5a32eSNavid Emamdoost goto pm_put; 7651409df04SLucas Stach } 766a8c21a54SThe etnaviv authors 767a8c21a54SThe etnaviv authors etnaviv_hw_identify(gpu); 768a8c21a54SThe etnaviv authors 769a8c21a54SThe etnaviv authors if (gpu->identity.model == 0) { 770a8c21a54SThe etnaviv authors dev_err(gpu->dev, "Unknown GPU model\n"); 771f6427760SRussell King ret = -ENXIO; 772f6427760SRussell King goto fail; 773a8c21a54SThe etnaviv authors } 774a8c21a54SThe etnaviv authors 775b98c6688SRussell King /* Exclude VG cores with FE2.0 */ 776b98c6688SRussell King if (gpu->identity.features & chipFeatures_PIPE_VG && 777b98c6688SRussell King gpu->identity.features & chipFeatures_FE20) { 778b98c6688SRussell King dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 779b98c6688SRussell King ret = -ENXIO; 780b98c6688SRussell King goto fail; 781b98c6688SRussell King } 782b98c6688SRussell King 7832144fff7SLucas Stach /* 784c997c3dfSLucas Stach * On cores with security features supported, we claim control over the 785c997c3dfSLucas Stach * security states. 786c997c3dfSLucas Stach */ 787c997c3dfSLucas Stach if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 788c997c3dfSLucas Stach (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 789c997c3dfSLucas Stach gpu->sec_mode = ETNA_SEC_KERNEL; 790c997c3dfSLucas Stach 791a8c21a54SThe etnaviv authors ret = etnaviv_hw_reset(gpu); 7921409df04SLucas Stach if (ret) { 7931409df04SLucas Stach dev_err(gpu->dev, "GPU reset failed\n"); 794a8c21a54SThe etnaviv authors goto fail; 7951409df04SLucas Stach } 796a8c21a54SThe etnaviv authors 79727b67278SLucas Stach ret = etnaviv_iommu_global_init(gpu); 79827b67278SLucas Stach if (ret) 799a8c21a54SThe etnaviv authors goto fail; 80027b67278SLucas Stach 80117e4660aSLucas Stach /* 802b72af445SLucas Stach * If the GPU is part of a system with DMA addressing limitations, 803b72af445SLucas Stach * request pages for our SHM backend buffers from the DMA32 zone to 804b72af445SLucas Stach * hopefully avoid performance killing SWIOTLB bounce buffering. 805b72af445SLucas Stach */ 806b72af445SLucas Stach if (dma_addressing_limited(gpu->dev)) 807b72af445SLucas Stach priv->shm_gfp_mask |= GFP_DMA32; 808b72af445SLucas Stach 809a8c21a54SThe etnaviv authors /* Create buffer: */ 810bffe5db8SLucas Stach ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, 8112f9225dbSLucas Stach PAGE_SIZE); 8122f9225dbSLucas Stach if (ret) { 813a8c21a54SThe etnaviv authors dev_err(gpu->dev, "could not create command buffer\n"); 81417e4660aSLucas Stach goto fail; 815a8c21a54SThe etnaviv authors } 816a8c21a54SThe etnaviv authors 8174bfdd2aaSLucas Stach /* 8184bfdd2aaSLucas Stach * Set the GPU linear window to cover the cmdbuf region, as the GPU 8194bfdd2aaSLucas Stach * won't be able to start execution otherwise. The alignment to 128M is 8204bfdd2aaSLucas Stach * chosen arbitrarily but helps in debugging, as the MMU offset 8214bfdd2aaSLucas Stach * calculations are much more straight forward this way. 8224bfdd2aaSLucas Stach * 8234bfdd2aaSLucas Stach * On MC1.0 cores the linear window offset is ignored by the TS engine, 8244bfdd2aaSLucas Stach * leading to inconsistent memory views. Avoid using the offset on those 8254bfdd2aaSLucas Stach * cores if possible, otherwise disable the TS feature. 8264bfdd2aaSLucas Stach */ 8274bfdd2aaSLucas Stach cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 8284bfdd2aaSLucas Stach 8294bfdd2aaSLucas Stach if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 8304bfdd2aaSLucas Stach (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 8314bfdd2aaSLucas Stach if (cmdbuf_paddr >= SZ_2G) 8324bfdd2aaSLucas Stach priv->mmu_global->memory_base = SZ_2G; 8334bfdd2aaSLucas Stach else 8344bfdd2aaSLucas Stach priv->mmu_global->memory_base = cmdbuf_paddr; 8354bfdd2aaSLucas Stach } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 8364bfdd2aaSLucas Stach dev_info(gpu->dev, 8374bfdd2aaSLucas Stach "Need to move linear window on MC1.0, disabling TS\n"); 8384bfdd2aaSLucas Stach gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 8394bfdd2aaSLucas Stach priv->mmu_global->memory_base = SZ_2G; 8404bfdd2aaSLucas Stach } 8414bfdd2aaSLucas Stach 842a8c21a54SThe etnaviv authors /* Setup event management */ 843a8c21a54SThe etnaviv authors spin_lock_init(&gpu->event_spinlock); 844a8c21a54SThe etnaviv authors init_completion(&gpu->event_free); 845355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 846355502e0SChristian Gmeiner for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 847a8c21a54SThe etnaviv authors complete(&gpu->event_free); 848a8c21a54SThe etnaviv authors 849a8c21a54SThe etnaviv authors /* Now program the hardware */ 850a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 851a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 852a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 853a8c21a54SThe etnaviv authors 854a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 855a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 856a8c21a54SThe etnaviv authors 857db41fe7dSLucas Stach gpu->initialized = true; 858db41fe7dSLucas Stach 859a8c21a54SThe etnaviv authors return 0; 860a8c21a54SThe etnaviv authors 861a8c21a54SThe etnaviv authors fail: 862a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 863c5d5a32eSNavid Emamdoost pm_put: 864a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 865a8c21a54SThe etnaviv authors 866a8c21a54SThe etnaviv authors return ret; 867a8c21a54SThe etnaviv authors } 868a8c21a54SThe etnaviv authors 869a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 870a8c21a54SThe etnaviv authors struct dma_debug { 871a8c21a54SThe etnaviv authors u32 address[2]; 872a8c21a54SThe etnaviv authors u32 state[2]; 873a8c21a54SThe etnaviv authors }; 874a8c21a54SThe etnaviv authors 875a8c21a54SThe etnaviv authors static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 876a8c21a54SThe etnaviv authors { 877a8c21a54SThe etnaviv authors u32 i; 878a8c21a54SThe etnaviv authors 879a8c21a54SThe etnaviv authors debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 880a8c21a54SThe etnaviv authors debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 881a8c21a54SThe etnaviv authors 882a8c21a54SThe etnaviv authors for (i = 0; i < 500; i++) { 883a8c21a54SThe etnaviv authors debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 884a8c21a54SThe etnaviv authors debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 885a8c21a54SThe etnaviv authors 886a8c21a54SThe etnaviv authors if (debug->address[0] != debug->address[1]) 887a8c21a54SThe etnaviv authors break; 888a8c21a54SThe etnaviv authors 889a8c21a54SThe etnaviv authors if (debug->state[0] != debug->state[1]) 890a8c21a54SThe etnaviv authors break; 891a8c21a54SThe etnaviv authors } 892a8c21a54SThe etnaviv authors } 893a8c21a54SThe etnaviv authors 894a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 895a8c21a54SThe etnaviv authors { 896a8c21a54SThe etnaviv authors struct dma_debug debug; 897a8c21a54SThe etnaviv authors u32 dma_lo, dma_hi, axi, idle; 898a8c21a54SThe etnaviv authors int ret; 899a8c21a54SThe etnaviv authors 900a8c21a54SThe etnaviv authors seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 901a8c21a54SThe etnaviv authors 902a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 903a8c21a54SThe etnaviv authors if (ret < 0) 904c5d5a32eSNavid Emamdoost goto pm_put; 905a8c21a54SThe etnaviv authors 906a8c21a54SThe etnaviv authors dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 907a8c21a54SThe etnaviv authors dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 908a8c21a54SThe etnaviv authors axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 909a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 910a8c21a54SThe etnaviv authors 911a8c21a54SThe etnaviv authors verify_dma(gpu, &debug); 912a8c21a54SThe etnaviv authors 91300080663SChristian Gmeiner seq_puts(m, "\tidentity\n"); 91400080663SChristian Gmeiner seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 91500080663SChristian Gmeiner seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 91600080663SChristian Gmeiner seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 91700080663SChristian Gmeiner seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 91800080663SChristian Gmeiner seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 91900080663SChristian Gmeiner 920a8c21a54SThe etnaviv authors seq_puts(m, "\tfeatures\n"); 9213d9fc642SLucas Stach seq_printf(m, "\t major_features: 0x%08x\n", 9223d9fc642SLucas Stach gpu->identity.features); 923a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features0: 0x%08x\n", 924a8c21a54SThe etnaviv authors gpu->identity.minor_features0); 925a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features1: 0x%08x\n", 926a8c21a54SThe etnaviv authors gpu->identity.minor_features1); 927a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features2: 0x%08x\n", 928a8c21a54SThe etnaviv authors gpu->identity.minor_features2); 929a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features3: 0x%08x\n", 930a8c21a54SThe etnaviv authors gpu->identity.minor_features3); 931602eb489SRussell King seq_printf(m, "\t minor_features4: 0x%08x\n", 932602eb489SRussell King gpu->identity.minor_features4); 933602eb489SRussell King seq_printf(m, "\t minor_features5: 0x%08x\n", 934602eb489SRussell King gpu->identity.minor_features5); 9350538aaf9SLucas Stach seq_printf(m, "\t minor_features6: 0x%08x\n", 9360538aaf9SLucas Stach gpu->identity.minor_features6); 9370538aaf9SLucas Stach seq_printf(m, "\t minor_features7: 0x%08x\n", 9380538aaf9SLucas Stach gpu->identity.minor_features7); 9390538aaf9SLucas Stach seq_printf(m, "\t minor_features8: 0x%08x\n", 9400538aaf9SLucas Stach gpu->identity.minor_features8); 9410538aaf9SLucas Stach seq_printf(m, "\t minor_features9: 0x%08x\n", 9420538aaf9SLucas Stach gpu->identity.minor_features9); 9430538aaf9SLucas Stach seq_printf(m, "\t minor_features10: 0x%08x\n", 9440538aaf9SLucas Stach gpu->identity.minor_features10); 9450538aaf9SLucas Stach seq_printf(m, "\t minor_features11: 0x%08x\n", 9460538aaf9SLucas Stach gpu->identity.minor_features11); 947a8c21a54SThe etnaviv authors 948a8c21a54SThe etnaviv authors seq_puts(m, "\tspecs\n"); 949a8c21a54SThe etnaviv authors seq_printf(m, "\t stream_count: %d\n", 950a8c21a54SThe etnaviv authors gpu->identity.stream_count); 951a8c21a54SThe etnaviv authors seq_printf(m, "\t register_max: %d\n", 952a8c21a54SThe etnaviv authors gpu->identity.register_max); 953a8c21a54SThe etnaviv authors seq_printf(m, "\t thread_count: %d\n", 954a8c21a54SThe etnaviv authors gpu->identity.thread_count); 955a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_cache_size: %d\n", 956a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size); 957a8c21a54SThe etnaviv authors seq_printf(m, "\t shader_core_count: %d\n", 958a8c21a54SThe etnaviv authors gpu->identity.shader_core_count); 959a8c21a54SThe etnaviv authors seq_printf(m, "\t pixel_pipes: %d\n", 960a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes); 961a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_output_buffer_size: %d\n", 962a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size); 963a8c21a54SThe etnaviv authors seq_printf(m, "\t buffer_size: %d\n", 964a8c21a54SThe etnaviv authors gpu->identity.buffer_size); 965a8c21a54SThe etnaviv authors seq_printf(m, "\t instruction_count: %d\n", 966a8c21a54SThe etnaviv authors gpu->identity.instruction_count); 967a8c21a54SThe etnaviv authors seq_printf(m, "\t num_constants: %d\n", 968a8c21a54SThe etnaviv authors gpu->identity.num_constants); 969602eb489SRussell King seq_printf(m, "\t varyings_count: %d\n", 970602eb489SRussell King gpu->identity.varyings_count); 971a8c21a54SThe etnaviv authors 972a8c21a54SThe etnaviv authors seq_printf(m, "\taxi: 0x%08x\n", axi); 973a8c21a54SThe etnaviv authors seq_printf(m, "\tidle: 0x%08x\n", idle); 974a8c21a54SThe etnaviv authors idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 975a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 976a8c21a54SThe etnaviv authors seq_puts(m, "\t FE is not idle\n"); 977a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 978a8c21a54SThe etnaviv authors seq_puts(m, "\t DE is not idle\n"); 979a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 980a8c21a54SThe etnaviv authors seq_puts(m, "\t PE is not idle\n"); 981a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 982a8c21a54SThe etnaviv authors seq_puts(m, "\t SH is not idle\n"); 983a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 984a8c21a54SThe etnaviv authors seq_puts(m, "\t PA is not idle\n"); 985a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 986a8c21a54SThe etnaviv authors seq_puts(m, "\t SE is not idle\n"); 987a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 988a8c21a54SThe etnaviv authors seq_puts(m, "\t RA is not idle\n"); 989a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 990a8c21a54SThe etnaviv authors seq_puts(m, "\t TX is not idle\n"); 991a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 992a8c21a54SThe etnaviv authors seq_puts(m, "\t VG is not idle\n"); 993a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 994a8c21a54SThe etnaviv authors seq_puts(m, "\t IM is not idle\n"); 995a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 996a8c21a54SThe etnaviv authors seq_puts(m, "\t FP is not idle\n"); 997a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 998a8c21a54SThe etnaviv authors seq_puts(m, "\t TS is not idle\n"); 999b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 1000b1704551SGuido Günther seq_puts(m, "\t BL is not idle\n"); 1001b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 1002b1704551SGuido Günther seq_puts(m, "\t ASYNCFE is not idle\n"); 1003b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 1004b1704551SGuido Günther seq_puts(m, "\t MC is not idle\n"); 1005b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 1006b1704551SGuido Günther seq_puts(m, "\t PPA is not idle\n"); 1007b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 1008b1704551SGuido Günther seq_puts(m, "\t WD is not idle\n"); 1009b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 1010b1704551SGuido Günther seq_puts(m, "\t NN is not idle\n"); 1011b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 1012b1704551SGuido Günther seq_puts(m, "\t TP is not idle\n"); 1013a8c21a54SThe etnaviv authors if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 1014a8c21a54SThe etnaviv authors seq_puts(m, "\t AXI low power mode\n"); 1015a8c21a54SThe etnaviv authors 1016a8c21a54SThe etnaviv authors if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1017a8c21a54SThe etnaviv authors u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1018a8c21a54SThe etnaviv authors u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1019a8c21a54SThe etnaviv authors u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1020a8c21a54SThe etnaviv authors 1021a8c21a54SThe etnaviv authors seq_puts(m, "\tMC\n"); 1022a8c21a54SThe etnaviv authors seq_printf(m, "\t read0: 0x%08x\n", read0); 1023a8c21a54SThe etnaviv authors seq_printf(m, "\t read1: 0x%08x\n", read1); 1024a8c21a54SThe etnaviv authors seq_printf(m, "\t write: 0x%08x\n", write); 1025a8c21a54SThe etnaviv authors } 1026a8c21a54SThe etnaviv authors 1027a8c21a54SThe etnaviv authors seq_puts(m, "\tDMA "); 1028a8c21a54SThe etnaviv authors 1029a8c21a54SThe etnaviv authors if (debug.address[0] == debug.address[1] && 1030a8c21a54SThe etnaviv authors debug.state[0] == debug.state[1]) { 1031a8c21a54SThe etnaviv authors seq_puts(m, "seems to be stuck\n"); 1032a8c21a54SThe etnaviv authors } else if (debug.address[0] == debug.address[1]) { 1033c01e0159SMasanari Iida seq_puts(m, "address is constant\n"); 1034a8c21a54SThe etnaviv authors } else { 1035c01e0159SMasanari Iida seq_puts(m, "is running\n"); 1036a8c21a54SThe etnaviv authors } 1037a8c21a54SThe etnaviv authors 1038a8c21a54SThe etnaviv authors seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1039a8c21a54SThe etnaviv authors seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1040a8c21a54SThe etnaviv authors seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1041a8c21a54SThe etnaviv authors seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1042a8c21a54SThe etnaviv authors seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1043a8c21a54SThe etnaviv authors dma_lo, dma_hi); 1044a8c21a54SThe etnaviv authors 1045a8c21a54SThe etnaviv authors ret = 0; 1046a8c21a54SThe etnaviv authors 1047a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1048c5d5a32eSNavid Emamdoost pm_put: 1049a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1050a8c21a54SThe etnaviv authors 1051a8c21a54SThe etnaviv authors return ret; 1052a8c21a54SThe etnaviv authors } 1053a8c21a54SThe etnaviv authors #endif 1054a8c21a54SThe etnaviv authors 1055f51d753fSChristian Gmeiner void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit) 1056a8c21a54SThe etnaviv authors { 1057f51d753fSChristian Gmeiner struct etnaviv_gpu *gpu = submit->gpu; 1058f51d753fSChristian Gmeiner char *comm = NULL, *cmd = NULL; 1059f51d753fSChristian Gmeiner struct task_struct *task; 1060749443deSYury Norov unsigned int i; 1061a8c21a54SThe etnaviv authors 10626d7a20c0SLucas Stach dev_err(gpu->dev, "recover hung GPU!\n"); 1063a8c21a54SThe etnaviv authors 1064f51d753fSChristian Gmeiner task = get_pid_task(submit->pid, PIDTYPE_PID); 1065f51d753fSChristian Gmeiner if (task) { 1066f51d753fSChristian Gmeiner comm = kstrdup(task->comm, GFP_KERNEL); 1067f51d753fSChristian Gmeiner cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 1068f51d753fSChristian Gmeiner put_task_struct(task); 1069f51d753fSChristian Gmeiner } 1070f51d753fSChristian Gmeiner 1071f51d753fSChristian Gmeiner if (comm && cmd) 1072f51d753fSChristian Gmeiner dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); 1073f51d753fSChristian Gmeiner 1074f51d753fSChristian Gmeiner kfree(cmd); 1075f51d753fSChristian Gmeiner kfree(comm); 1076f51d753fSChristian Gmeiner 1077a8c21a54SThe etnaviv authors if (pm_runtime_get_sync(gpu->dev) < 0) 1078c5d5a32eSNavid Emamdoost goto pm_put; 1079a8c21a54SThe etnaviv authors 1080a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 1081a8c21a54SThe etnaviv authors 1082a8c21a54SThe etnaviv authors etnaviv_hw_reset(gpu); 1083a8c21a54SThe etnaviv authors 1084a8c21a54SThe etnaviv authors /* complete all events, the GPU won't do it after the reset */ 10855a23144cSLucas Stach spin_lock(&gpu->event_spinlock); 1086749443deSYury Norov for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1087a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1088355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 10895a23144cSLucas Stach spin_unlock(&gpu->event_spinlock); 1090a8c21a54SThe etnaviv authors 1091a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1092a8c21a54SThe etnaviv authors 1093a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1094a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1095c5d5a32eSNavid Emamdoost pm_put: 1096a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1097a8c21a54SThe etnaviv authors } 1098a8c21a54SThe etnaviv authors 1099a8c21a54SThe etnaviv authors /* fence object management */ 1100a8c21a54SThe etnaviv authors struct etnaviv_fence { 1101a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1102f54d1867SChris Wilson struct dma_fence base; 1103a8c21a54SThe etnaviv authors }; 1104a8c21a54SThe etnaviv authors 1105f54d1867SChris Wilson static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1106a8c21a54SThe etnaviv authors { 1107a8c21a54SThe etnaviv authors return container_of(fence, struct etnaviv_fence, base); 1108a8c21a54SThe etnaviv authors } 1109a8c21a54SThe etnaviv authors 1110f54d1867SChris Wilson static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1111a8c21a54SThe etnaviv authors { 1112a8c21a54SThe etnaviv authors return "etnaviv"; 1113a8c21a54SThe etnaviv authors } 1114a8c21a54SThe etnaviv authors 1115f54d1867SChris Wilson static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1116a8c21a54SThe etnaviv authors { 1117a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1118a8c21a54SThe etnaviv authors 1119a8c21a54SThe etnaviv authors return dev_name(f->gpu->dev); 1120a8c21a54SThe etnaviv authors } 1121a8c21a54SThe etnaviv authors 1122f54d1867SChris Wilson static bool etnaviv_fence_signaled(struct dma_fence *fence) 1123a8c21a54SThe etnaviv authors { 1124a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1125a8c21a54SThe etnaviv authors 11263283ee77SLucas Stach return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1127a8c21a54SThe etnaviv authors } 1128a8c21a54SThe etnaviv authors 1129f54d1867SChris Wilson static void etnaviv_fence_release(struct dma_fence *fence) 1130a8c21a54SThe etnaviv authors { 1131a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1132a8c21a54SThe etnaviv authors 1133a8c21a54SThe etnaviv authors kfree_rcu(f, base.rcu); 1134a8c21a54SThe etnaviv authors } 1135a8c21a54SThe etnaviv authors 1136f54d1867SChris Wilson static const struct dma_fence_ops etnaviv_fence_ops = { 1137a8c21a54SThe etnaviv authors .get_driver_name = etnaviv_fence_get_driver_name, 1138a8c21a54SThe etnaviv authors .get_timeline_name = etnaviv_fence_get_timeline_name, 1139a8c21a54SThe etnaviv authors .signaled = etnaviv_fence_signaled, 1140a8c21a54SThe etnaviv authors .release = etnaviv_fence_release, 1141a8c21a54SThe etnaviv authors }; 1142a8c21a54SThe etnaviv authors 1143f54d1867SChris Wilson static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1144a8c21a54SThe etnaviv authors { 1145a8c21a54SThe etnaviv authors struct etnaviv_fence *f; 1146a8c21a54SThe etnaviv authors 1147b27734c2SLucas Stach /* 1148b27734c2SLucas Stach * GPU lock must already be held, otherwise fence completion order might 1149b27734c2SLucas Stach * not match the seqno order assigned here. 1150b27734c2SLucas Stach */ 1151b27734c2SLucas Stach lockdep_assert_held(&gpu->lock); 1152b27734c2SLucas Stach 1153a8c21a54SThe etnaviv authors f = kzalloc(sizeof(*f), GFP_KERNEL); 1154a8c21a54SThe etnaviv authors if (!f) 1155a8c21a54SThe etnaviv authors return NULL; 1156a8c21a54SThe etnaviv authors 1157a8c21a54SThe etnaviv authors f->gpu = gpu; 1158a8c21a54SThe etnaviv authors 1159f54d1867SChris Wilson dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1160a8c21a54SThe etnaviv authors gpu->fence_context, ++gpu->next_fence); 1161a8c21a54SThe etnaviv authors 1162a8c21a54SThe etnaviv authors return &f->base; 1163a8c21a54SThe etnaviv authors } 1164a8c21a54SThe etnaviv authors 11653283ee77SLucas Stach /* returns true if fence a comes after fence b */ 11663283ee77SLucas Stach static inline bool fence_after(u32 a, u32 b) 11673283ee77SLucas Stach { 11683283ee77SLucas Stach return (s32)(a - b) > 0; 11693283ee77SLucas Stach } 11703283ee77SLucas Stach 1171a8c21a54SThe etnaviv authors /* 1172a8c21a54SThe etnaviv authors * event management: 1173a8c21a54SThe etnaviv authors */ 1174a8c21a54SThe etnaviv authors 117595a428c1SChristian Gmeiner static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 117695a428c1SChristian Gmeiner unsigned int *events) 1177a8c21a54SThe etnaviv authors { 11785a23144cSLucas Stach unsigned long timeout = msecs_to_jiffies(10 * 10000); 117995a428c1SChristian Gmeiner unsigned i, acquired = 0; 1180a8c21a54SThe etnaviv authors 118195a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 118295a428c1SChristian Gmeiner unsigned long ret; 118395a428c1SChristian Gmeiner 118495a428c1SChristian Gmeiner ret = wait_for_completion_timeout(&gpu->event_free, timeout); 118595a428c1SChristian Gmeiner 118695a428c1SChristian Gmeiner if (!ret) { 1187a8c21a54SThe etnaviv authors dev_err(gpu->dev, "wait_for_completion_timeout failed"); 118895a428c1SChristian Gmeiner goto out; 118995a428c1SChristian Gmeiner } 119095a428c1SChristian Gmeiner 119195a428c1SChristian Gmeiner acquired++; 119295a428c1SChristian Gmeiner timeout = ret; 119395a428c1SChristian Gmeiner } 1194a8c21a54SThe etnaviv authors 11955a23144cSLucas Stach spin_lock(&gpu->event_spinlock); 1196a8c21a54SThe etnaviv authors 119795a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 119895a428c1SChristian Gmeiner int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 119995a428c1SChristian Gmeiner 120095a428c1SChristian Gmeiner events[i] = event; 1201547d340dSChristian Gmeiner memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1202355502e0SChristian Gmeiner set_bit(event, gpu->event_bitmap); 1203a8c21a54SThe etnaviv authors } 1204a8c21a54SThe etnaviv authors 12055a23144cSLucas Stach spin_unlock(&gpu->event_spinlock); 1206a8c21a54SThe etnaviv authors 120795a428c1SChristian Gmeiner return 0; 120895a428c1SChristian Gmeiner 120995a428c1SChristian Gmeiner out: 121095a428c1SChristian Gmeiner for (i = 0; i < acquired; i++) 121195a428c1SChristian Gmeiner complete(&gpu->event_free); 121295a428c1SChristian Gmeiner 121395a428c1SChristian Gmeiner return -EBUSY; 1214a8c21a54SThe etnaviv authors } 1215a8c21a54SThe etnaviv authors 1216a8c21a54SThe etnaviv authors static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1217a8c21a54SThe etnaviv authors { 1218355502e0SChristian Gmeiner if (!test_bit(event, gpu->event_bitmap)) { 1219a8c21a54SThe etnaviv authors dev_warn(gpu->dev, "event %u is already marked as free", 1220a8c21a54SThe etnaviv authors event); 1221a8c21a54SThe etnaviv authors } else { 1222355502e0SChristian Gmeiner clear_bit(event, gpu->event_bitmap); 1223a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1224a8c21a54SThe etnaviv authors } 1225a8c21a54SThe etnaviv authors } 1226a8c21a54SThe etnaviv authors 1227a8c21a54SThe etnaviv authors /* 1228a8c21a54SThe etnaviv authors * Cmdstream submission/retirement: 1229a8c21a54SThe etnaviv authors */ 1230a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 123138c4a4cfSArnd Bergmann u32 id, struct drm_etnaviv_timespec *timeout) 1232a8c21a54SThe etnaviv authors { 12338bc4d885SLucas Stach struct dma_fence *fence; 1234a8c21a54SThe etnaviv authors int ret; 1235a8c21a54SThe etnaviv authors 12368bc4d885SLucas Stach /* 1237e93b6deeSLucas Stach * Look up the fence and take a reference. We might still find a fence 12388bc4d885SLucas Stach * whose refcount has already dropped to zero. dma_fence_get_rcu 12398bc4d885SLucas Stach * pretends we didn't find a fence in that case. 12408bc4d885SLucas Stach */ 1241e93b6deeSLucas Stach rcu_read_lock(); 12428bc4d885SLucas Stach fence = idr_find(&gpu->fence_idr, id); 12438bc4d885SLucas Stach if (fence) 12448bc4d885SLucas Stach fence = dma_fence_get_rcu(fence); 1245e93b6deeSLucas Stach rcu_read_unlock(); 12468bc4d885SLucas Stach 12478bc4d885SLucas Stach if (!fence) 12488bc4d885SLucas Stach return 0; 1249a8c21a54SThe etnaviv authors 1250a8c21a54SThe etnaviv authors if (!timeout) { 1251a8c21a54SThe etnaviv authors /* No timeout was requested: just test for completion */ 12528bc4d885SLucas Stach ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1253a8c21a54SThe etnaviv authors } else { 1254a8c21a54SThe etnaviv authors unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1255a8c21a54SThe etnaviv authors 12568bc4d885SLucas Stach ret = dma_fence_wait_timeout(fence, true, remaining); 12578bc4d885SLucas Stach if (ret == 0) 1258a8c21a54SThe etnaviv authors ret = -ETIMEDOUT; 12598bc4d885SLucas Stach else if (ret != -ERESTARTSYS) 1260a8c21a54SThe etnaviv authors ret = 0; 12618bc4d885SLucas Stach 1262a8c21a54SThe etnaviv authors } 1263a8c21a54SThe etnaviv authors 12648bc4d885SLucas Stach dma_fence_put(fence); 1265a8c21a54SThe etnaviv authors return ret; 1266a8c21a54SThe etnaviv authors } 1267a8c21a54SThe etnaviv authors 1268a8c21a54SThe etnaviv authors /* 1269a8c21a54SThe etnaviv authors * Wait for an object to become inactive. This, on it's own, is not race 1270e93b6deeSLucas Stach * free: the object is moved by the scheduler off the active list, and 1271a8c21a54SThe etnaviv authors * then the iova is put. Moreover, the object could be re-submitted just 1272a8c21a54SThe etnaviv authors * after we notice that it's become inactive. 1273a8c21a54SThe etnaviv authors * 1274a8c21a54SThe etnaviv authors * Although the retirement happens under the gpu lock, we don't want to hold 1275a8c21a54SThe etnaviv authors * that lock in this function while waiting. 1276a8c21a54SThe etnaviv authors */ 1277a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 127838c4a4cfSArnd Bergmann struct etnaviv_gem_object *etnaviv_obj, 127938c4a4cfSArnd Bergmann struct drm_etnaviv_timespec *timeout) 1280a8c21a54SThe etnaviv authors { 1281a8c21a54SThe etnaviv authors unsigned long remaining; 1282a8c21a54SThe etnaviv authors long ret; 1283a8c21a54SThe etnaviv authors 1284a8c21a54SThe etnaviv authors if (!timeout) 1285a8c21a54SThe etnaviv authors return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1286a8c21a54SThe etnaviv authors 1287a8c21a54SThe etnaviv authors remaining = etnaviv_timeout_to_jiffies(timeout); 1288a8c21a54SThe etnaviv authors 1289a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1290a8c21a54SThe etnaviv authors !is_active(etnaviv_obj), 1291a8c21a54SThe etnaviv authors remaining); 1292fa67ac84SLucas Stach if (ret > 0) 1293a8c21a54SThe etnaviv authors return 0; 1294fa67ac84SLucas Stach else if (ret == -ERESTARTSYS) 1295a8c21a54SThe etnaviv authors return -ERESTARTSYS; 1296fa67ac84SLucas Stach else 1297a8c21a54SThe etnaviv authors return -ETIMEDOUT; 1298a8c21a54SThe etnaviv authors } 1299a8c21a54SThe etnaviv authors 130068dc0b29SChristian Gmeiner static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 130168dc0b29SChristian Gmeiner struct etnaviv_event *event, unsigned int flags) 130268dc0b29SChristian Gmeiner { 1303ef146c00SLucas Stach const struct etnaviv_gem_submit *submit = event->submit; 130468dc0b29SChristian Gmeiner unsigned int i; 130568dc0b29SChristian Gmeiner 1306ef146c00SLucas Stach for (i = 0; i < submit->nr_pmrs; i++) { 1307ef146c00SLucas Stach const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 130868dc0b29SChristian Gmeiner 130968dc0b29SChristian Gmeiner if (pmr->flags == flags) 13107a9c0fe2SLucas Stach etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 131168dc0b29SChristian Gmeiner } 131268dc0b29SChristian Gmeiner } 131368dc0b29SChristian Gmeiner 131468dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 131568dc0b29SChristian Gmeiner struct etnaviv_event *event) 131668dc0b29SChristian Gmeiner { 13172c8b0c5aSChristian Gmeiner u32 val; 13182c8b0c5aSChristian Gmeiner 13192c8b0c5aSChristian Gmeiner /* disable clock gating */ 13202c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 13212c8b0c5aSChristian Gmeiner val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 13222c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 13232c8b0c5aSChristian Gmeiner 132404a7d18dSChristian Gmeiner /* enable debug register */ 132504a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 132604a7d18dSChristian Gmeiner val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 132704a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 132804a7d18dSChristian Gmeiner 132968dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 133068dc0b29SChristian Gmeiner } 133168dc0b29SChristian Gmeiner 133268dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 133368dc0b29SChristian Gmeiner struct etnaviv_event *event) 133468dc0b29SChristian Gmeiner { 1335ef146c00SLucas Stach const struct etnaviv_gem_submit *submit = event->submit; 133668dc0b29SChristian Gmeiner unsigned int i; 13372c8b0c5aSChristian Gmeiner u32 val; 133868dc0b29SChristian Gmeiner 133968dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 134068dc0b29SChristian Gmeiner 1341ef146c00SLucas Stach for (i = 0; i < submit->nr_pmrs; i++) { 1342ef146c00SLucas Stach const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 134368dc0b29SChristian Gmeiner 134468dc0b29SChristian Gmeiner *pmr->bo_vma = pmr->sequence; 134568dc0b29SChristian Gmeiner } 13462c8b0c5aSChristian Gmeiner 134704a7d18dSChristian Gmeiner /* disable debug register */ 134804a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 134904a7d18dSChristian Gmeiner val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 135004a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 135104a7d18dSChristian Gmeiner 13522c8b0c5aSChristian Gmeiner /* enable clock gating */ 13532c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 13542c8b0c5aSChristian Gmeiner val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 13552c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 135668dc0b29SChristian Gmeiner } 135768dc0b29SChristian Gmeiner 135868dc0b29SChristian Gmeiner 1359a8c21a54SThe etnaviv authors /* add bo's to gpu's ring, and kick gpu: */ 1360e93b6deeSLucas Stach struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1361a8c21a54SThe etnaviv authors { 1362e93b6deeSLucas Stach struct etnaviv_gpu *gpu = submit->gpu; 1363e93b6deeSLucas Stach struct dma_fence *gpu_fence; 136468dc0b29SChristian Gmeiner unsigned int i, nr_events = 1, event[3]; 1365a8c21a54SThe etnaviv authors int ret; 1366a8c21a54SThe etnaviv authors 13676d7a20c0SLucas Stach if (!submit->runtime_resumed) { 13688bda1516SLucas Stach ret = pm_runtime_get_sync(gpu->dev); 1369c5d5a32eSNavid Emamdoost if (ret < 0) { 1370c5d5a32eSNavid Emamdoost pm_runtime_put_noidle(gpu->dev); 1371e93b6deeSLucas Stach return NULL; 1372c5d5a32eSNavid Emamdoost } 13738bda1516SLucas Stach submit->runtime_resumed = true; 13746d7a20c0SLucas Stach } 1375a8c21a54SThe etnaviv authors 1376a8c21a54SThe etnaviv authors /* 137768dc0b29SChristian Gmeiner * if there are performance monitor requests we need to have 137868dc0b29SChristian Gmeiner * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 137968dc0b29SChristian Gmeiner * requests. 138068dc0b29SChristian Gmeiner * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 138168dc0b29SChristian Gmeiner * and update the sequence number for userspace. 138268dc0b29SChristian Gmeiner */ 1383ef146c00SLucas Stach if (submit->nr_pmrs) 138468dc0b29SChristian Gmeiner nr_events = 3; 138568dc0b29SChristian Gmeiner 138668dc0b29SChristian Gmeiner ret = event_alloc(gpu, nr_events, event); 138795a428c1SChristian Gmeiner if (ret) { 138868dc0b29SChristian Gmeiner DRM_ERROR("no free events\n"); 1389c5d5a32eSNavid Emamdoost pm_runtime_put_noidle(gpu->dev); 1390e93b6deeSLucas Stach return NULL; 1391a8c21a54SThe etnaviv authors } 1392a8c21a54SThe etnaviv authors 1393f3cd1b06SLucas Stach mutex_lock(&gpu->lock); 1394f3cd1b06SLucas Stach 1395e93b6deeSLucas Stach gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1396e93b6deeSLucas Stach if (!gpu_fence) { 139768dc0b29SChristian Gmeiner for (i = 0; i < nr_events; i++) 139868dc0b29SChristian Gmeiner event_free(gpu, event[i]); 139968dc0b29SChristian Gmeiner 140045abdf35SWei Yongjun goto out_unlock; 1401a8c21a54SThe etnaviv authors } 1402a8c21a54SThe etnaviv authors 1403d6408538SLucas Stach if (!gpu->fe_running) 1404d6408538SLucas Stach etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); 1405d6408538SLucas Stach 1406cda75329SLucas Stach if (submit->prev_mmu_context) 1407cda75329SLucas Stach etnaviv_iommu_context_put(submit->prev_mmu_context); 140878edefc0SLucas Stach submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); 140917e4660aSLucas Stach 1410ef146c00SLucas Stach if (submit->nr_pmrs) { 141168dc0b29SChristian Gmeiner gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1412ef146c00SLucas Stach kref_get(&submit->refcount); 1413ef146c00SLucas Stach gpu->event[event[1]].submit = submit; 141468dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[1]); 141568dc0b29SChristian Gmeiner } 141668dc0b29SChristian Gmeiner 1417e93b6deeSLucas Stach gpu->event[event[0]].fence = gpu_fence; 14186d7a20c0SLucas Stach submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 141917e4660aSLucas Stach etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 142017e4660aSLucas Stach event[0], &submit->cmdbuf); 142168dc0b29SChristian Gmeiner 1422ef146c00SLucas Stach if (submit->nr_pmrs) { 142368dc0b29SChristian Gmeiner gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1424ef146c00SLucas Stach kref_get(&submit->refcount); 1425ef146c00SLucas Stach gpu->event[event[2]].submit = submit; 142668dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[2]); 142768dc0b29SChristian Gmeiner } 1428a8c21a54SThe etnaviv authors 142945abdf35SWei Yongjun out_unlock: 1430a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1431a8c21a54SThe etnaviv authors 1432e93b6deeSLucas Stach return gpu_fence; 1433a8c21a54SThe etnaviv authors } 1434a8c21a54SThe etnaviv authors 1435357713ceSChristian Gmeiner static void sync_point_worker(struct work_struct *work) 1436357713ceSChristian Gmeiner { 1437357713ceSChristian Gmeiner struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1438357713ceSChristian Gmeiner sync_point_work); 1439b9a48aa7SLucas Stach struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1440b9a48aa7SLucas Stach u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1441357713ceSChristian Gmeiner 1442b9a48aa7SLucas Stach event->sync_point(gpu, event); 1443ef146c00SLucas Stach etnaviv_submit_put(event->submit); 1444357713ceSChristian Gmeiner event_free(gpu, gpu->sync_point_event); 1445b9a48aa7SLucas Stach 1446b9a48aa7SLucas Stach /* restart FE last to avoid GPU and IRQ racing against this worker */ 1447b9a48aa7SLucas Stach etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1448357713ceSChristian Gmeiner } 1449357713ceSChristian Gmeiner 14504df3000eSLucas Stach static void dump_mmu_fault(struct etnaviv_gpu *gpu) 14514df3000eSLucas Stach { 1452c997c3dfSLucas Stach u32 status_reg, status; 14534df3000eSLucas Stach int i; 14544df3000eSLucas Stach 1455c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_NONE) 1456c997c3dfSLucas Stach status_reg = VIVS_MMUv2_STATUS; 1457c997c3dfSLucas Stach else 1458c997c3dfSLucas Stach status_reg = VIVS_MMUv2_SEC_STATUS; 1459c997c3dfSLucas Stach 1460c997c3dfSLucas Stach status = gpu_read(gpu, status_reg); 14614df3000eSLucas Stach dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 14624df3000eSLucas Stach 14634df3000eSLucas Stach for (i = 0; i < 4; i++) { 1464c997c3dfSLucas Stach u32 address_reg; 1465c997c3dfSLucas Stach 14664df3000eSLucas Stach if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4)))) 14674df3000eSLucas Stach continue; 14684df3000eSLucas Stach 1469c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_NONE) 1470c997c3dfSLucas Stach address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1471c997c3dfSLucas Stach else 1472c997c3dfSLucas Stach address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1473c997c3dfSLucas Stach 14744df3000eSLucas Stach dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, 1475c997c3dfSLucas Stach gpu_read(gpu, address_reg)); 14764df3000eSLucas Stach } 14774df3000eSLucas Stach } 14784df3000eSLucas Stach 1479a8c21a54SThe etnaviv authors static irqreturn_t irq_handler(int irq, void *data) 1480a8c21a54SThe etnaviv authors { 1481a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = data; 1482a8c21a54SThe etnaviv authors irqreturn_t ret = IRQ_NONE; 1483a8c21a54SThe etnaviv authors 1484a8c21a54SThe etnaviv authors u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1485a8c21a54SThe etnaviv authors 1486a8c21a54SThe etnaviv authors if (intr != 0) { 1487a8c21a54SThe etnaviv authors int event; 1488a8c21a54SThe etnaviv authors 1489a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1490a8c21a54SThe etnaviv authors 1491a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1492a8c21a54SThe etnaviv authors 1493a8c21a54SThe etnaviv authors if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1494a8c21a54SThe etnaviv authors dev_err(gpu->dev, "AXI bus error\n"); 1495a8c21a54SThe etnaviv authors intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1496a8c21a54SThe etnaviv authors } 1497a8c21a54SThe etnaviv authors 1498128a9b1dSLucas Stach if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 14994df3000eSLucas Stach dump_mmu_fault(gpu); 1500128a9b1dSLucas Stach intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1501128a9b1dSLucas Stach } 1502128a9b1dSLucas Stach 1503a8c21a54SThe etnaviv authors while ((event = ffs(intr)) != 0) { 1504f54d1867SChris Wilson struct dma_fence *fence; 1505a8c21a54SThe etnaviv authors 1506a8c21a54SThe etnaviv authors event -= 1; 1507a8c21a54SThe etnaviv authors 1508a8c21a54SThe etnaviv authors intr &= ~(1 << event); 1509a8c21a54SThe etnaviv authors 1510a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "event %u\n", event); 1511a8c21a54SThe etnaviv authors 1512357713ceSChristian Gmeiner if (gpu->event[event].sync_point) { 1513357713ceSChristian Gmeiner gpu->sync_point_event = event; 1514a7790d78SLucas Stach queue_work(gpu->wq, &gpu->sync_point_work); 1515357713ceSChristian Gmeiner } 1516357713ceSChristian Gmeiner 1517a8c21a54SThe etnaviv authors fence = gpu->event[event].fence; 151868dc0b29SChristian Gmeiner if (!fence) 151968dc0b29SChristian Gmeiner continue; 152068dc0b29SChristian Gmeiner 1521a8c21a54SThe etnaviv authors gpu->event[event].fence = NULL; 1522a8c21a54SThe etnaviv authors 1523a8c21a54SThe etnaviv authors /* 1524a8c21a54SThe etnaviv authors * Events can be processed out of order. Eg, 1525a8c21a54SThe etnaviv authors * - allocate and queue event 0 1526a8c21a54SThe etnaviv authors * - allocate event 1 1527a8c21a54SThe etnaviv authors * - event 0 completes, we process it 1528a8c21a54SThe etnaviv authors * - allocate and queue event 0 1529a8c21a54SThe etnaviv authors * - event 1 and event 0 complete 1530a8c21a54SThe etnaviv authors * we can end up processing event 0 first, then 1. 1531a8c21a54SThe etnaviv authors */ 1532a8c21a54SThe etnaviv authors if (fence_after(fence->seqno, gpu->completed_fence)) 1533a8c21a54SThe etnaviv authors gpu->completed_fence = fence->seqno; 15348bc4d885SLucas Stach dma_fence_signal(fence); 1535a8c21a54SThe etnaviv authors 1536a8c21a54SThe etnaviv authors event_free(gpu, event); 1537a8c21a54SThe etnaviv authors } 1538a8c21a54SThe etnaviv authors 1539a8c21a54SThe etnaviv authors ret = IRQ_HANDLED; 1540a8c21a54SThe etnaviv authors } 1541a8c21a54SThe etnaviv authors 1542a8c21a54SThe etnaviv authors return ret; 1543a8c21a54SThe etnaviv authors } 1544a8c21a54SThe etnaviv authors 1545a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1546a8c21a54SThe etnaviv authors { 1547a8c21a54SThe etnaviv authors int ret; 1548a8c21a54SThe etnaviv authors 154965f037e8SLucas Stach ret = clk_prepare_enable(gpu->clk_reg); 155065f037e8SLucas Stach if (ret) 155165f037e8SLucas Stach return ret; 155265f037e8SLucas Stach 15539c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_bus); 1554a8c21a54SThe etnaviv authors if (ret) 1555f8794feaSLubomir Rintel goto disable_clk_reg; 1556a8c21a54SThe etnaviv authors 15579c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_core); 15589c7310c0SLucas Stach if (ret) 15599c7310c0SLucas Stach goto disable_clk_bus; 15609c7310c0SLucas Stach 15619c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_shader); 15629c7310c0SLucas Stach if (ret) 15639c7310c0SLucas Stach goto disable_clk_core; 15649c7310c0SLucas Stach 1565a8c21a54SThe etnaviv authors return 0; 15669c7310c0SLucas Stach 15679c7310c0SLucas Stach disable_clk_core: 15689c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 15699c7310c0SLucas Stach disable_clk_bus: 15709c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 1571f8794feaSLubomir Rintel disable_clk_reg: 1572f8794feaSLubomir Rintel clk_disable_unprepare(gpu->clk_reg); 15739c7310c0SLucas Stach 15749c7310c0SLucas Stach return ret; 1575a8c21a54SThe etnaviv authors } 1576a8c21a54SThe etnaviv authors 1577a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1578a8c21a54SThe etnaviv authors { 15799c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_shader); 15809c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 15819c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 158265f037e8SLucas Stach clk_disable_unprepare(gpu->clk_reg); 1583a8c21a54SThe etnaviv authors 1584a8c21a54SThe etnaviv authors return 0; 1585a8c21a54SThe etnaviv authors } 1586a8c21a54SThe etnaviv authors 1587b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1588b88163e3SLucas Stach { 1589b88163e3SLucas Stach unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1590b88163e3SLucas Stach 1591b88163e3SLucas Stach do { 1592b88163e3SLucas Stach u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1593b88163e3SLucas Stach 1594b88163e3SLucas Stach if ((idle & gpu->idle_mask) == gpu->idle_mask) 1595b88163e3SLucas Stach return 0; 1596b88163e3SLucas Stach 1597b88163e3SLucas Stach if (time_is_before_jiffies(timeout)) { 1598b88163e3SLucas Stach dev_warn(gpu->dev, 1599b88163e3SLucas Stach "timed out waiting for idle: idle=0x%x\n", 1600b88163e3SLucas Stach idle); 1601b88163e3SLucas Stach return -ETIMEDOUT; 1602b88163e3SLucas Stach } 1603b88163e3SLucas Stach 1604b88163e3SLucas Stach udelay(5); 1605b88163e3SLucas Stach } while (1); 1606b88163e3SLucas Stach } 1607b88163e3SLucas Stach 1608a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1609a8c21a54SThe etnaviv authors { 161023e0f5a5SLucas Stach if (gpu->initialized && gpu->fe_running) { 1611a8c21a54SThe etnaviv authors /* Replace the last WAIT with END */ 161240c27bdeSLucas Stach mutex_lock(&gpu->lock); 1613a8c21a54SThe etnaviv authors etnaviv_buffer_end(gpu); 161440c27bdeSLucas Stach mutex_unlock(&gpu->lock); 1615a8c21a54SThe etnaviv authors 1616a8c21a54SThe etnaviv authors /* 1617a8c21a54SThe etnaviv authors * We know that only the FE is busy here, this should 1618a8c21a54SThe etnaviv authors * happen quickly (as the WAIT is only 200 cycles). If 1619a8c21a54SThe etnaviv authors * we fail, just warn and continue. 1620a8c21a54SThe etnaviv authors */ 1621b88163e3SLucas Stach etnaviv_gpu_wait_idle(gpu, 100); 162217e4660aSLucas Stach 162323e0f5a5SLucas Stach gpu->fe_running = false; 1624a8c21a54SThe etnaviv authors } 1625a8c21a54SThe etnaviv authors 162617e4660aSLucas Stach gpu->exec_state = -1; 162717e4660aSLucas Stach 1628a8c21a54SThe etnaviv authors return etnaviv_gpu_clk_disable(gpu); 1629a8c21a54SThe etnaviv authors } 1630a8c21a54SThe etnaviv authors 1631a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1632a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1633a8c21a54SThe etnaviv authors { 1634a8c21a54SThe etnaviv authors int ret; 1635a8c21a54SThe etnaviv authors 1636a8c21a54SThe etnaviv authors ret = mutex_lock_killable(&gpu->lock); 1637a8c21a54SThe etnaviv authors if (ret) 1638a8c21a54SThe etnaviv authors return ret; 1639a8c21a54SThe etnaviv authors 1640bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1641a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1642a8c21a54SThe etnaviv authors 1643a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1644a8c21a54SThe etnaviv authors 1645a8c21a54SThe etnaviv authors return 0; 1646a8c21a54SThe etnaviv authors } 1647a8c21a54SThe etnaviv authors #endif 1648a8c21a54SThe etnaviv authors 1649bcdfb5e5SRussell King static int 1650bcdfb5e5SRussell King etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1651bcdfb5e5SRussell King unsigned long *state) 1652bcdfb5e5SRussell King { 1653bcdfb5e5SRussell King *state = 6; 1654bcdfb5e5SRussell King 1655bcdfb5e5SRussell King return 0; 1656bcdfb5e5SRussell King } 1657bcdfb5e5SRussell King 1658bcdfb5e5SRussell King static int 1659bcdfb5e5SRussell King etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1660bcdfb5e5SRussell King unsigned long *state) 1661bcdfb5e5SRussell King { 1662bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1663bcdfb5e5SRussell King 1664bcdfb5e5SRussell King *state = gpu->freq_scale; 1665bcdfb5e5SRussell King 1666bcdfb5e5SRussell King return 0; 1667bcdfb5e5SRussell King } 1668bcdfb5e5SRussell King 1669bcdfb5e5SRussell King static int 1670bcdfb5e5SRussell King etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1671bcdfb5e5SRussell King unsigned long state) 1672bcdfb5e5SRussell King { 1673bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1674bcdfb5e5SRussell King 1675bcdfb5e5SRussell King mutex_lock(&gpu->lock); 1676bcdfb5e5SRussell King gpu->freq_scale = state; 1677bcdfb5e5SRussell King if (!pm_runtime_suspended(gpu->dev)) 1678bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1679bcdfb5e5SRussell King mutex_unlock(&gpu->lock); 1680bcdfb5e5SRussell King 1681bcdfb5e5SRussell King return 0; 1682bcdfb5e5SRussell King } 1683bcdfb5e5SRussell King 168496894b79SRikard Falkeborn static const struct thermal_cooling_device_ops cooling_ops = { 1685bcdfb5e5SRussell King .get_max_state = etnaviv_gpu_cooling_get_max_state, 1686bcdfb5e5SRussell King .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1687bcdfb5e5SRussell King .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1688bcdfb5e5SRussell King }; 1689bcdfb5e5SRussell King 1690a8c21a54SThe etnaviv authors static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1691a8c21a54SThe etnaviv authors void *data) 1692a8c21a54SThe etnaviv authors { 1693a8c21a54SThe etnaviv authors struct drm_device *drm = data; 1694a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = drm->dev_private; 1695a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1696a8c21a54SThe etnaviv authors int ret; 1697a8c21a54SThe etnaviv authors 169849b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1699bcdfb5e5SRussell King gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1700bcdfb5e5SRussell King (char *)dev_name(dev), gpu, &cooling_ops); 1701bcdfb5e5SRussell King if (IS_ERR(gpu->cooling)) 1702bcdfb5e5SRussell King return PTR_ERR(gpu->cooling); 17035247e2aaSLucas Stach } 1704bcdfb5e5SRussell King 1705a7790d78SLucas Stach gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1706a7790d78SLucas Stach if (!gpu->wq) { 1707e93b6deeSLucas Stach ret = -ENOMEM; 1708e93b6deeSLucas Stach goto out_thermal; 1709a7790d78SLucas Stach } 1710a7790d78SLucas Stach 1711e93b6deeSLucas Stach ret = etnaviv_sched_init(gpu); 1712e93b6deeSLucas Stach if (ret) 1713e93b6deeSLucas Stach goto out_workqueue; 1714e93b6deeSLucas Stach 1715a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1716a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 1717a8c21a54SThe etnaviv authors #else 1718a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1719a8c21a54SThe etnaviv authors #endif 1720e93b6deeSLucas Stach if (ret < 0) 1721e93b6deeSLucas Stach goto out_sched; 1722e93b6deeSLucas Stach 1723a8c21a54SThe etnaviv authors 1724a8c21a54SThe etnaviv authors gpu->drm = drm; 1725f54d1867SChris Wilson gpu->fence_context = dma_fence_context_alloc(1); 17268bc4d885SLucas Stach idr_init(&gpu->fence_idr); 1727a8c21a54SThe etnaviv authors spin_lock_init(&gpu->fence_spinlock); 1728a8c21a54SThe etnaviv authors 1729357713ceSChristian Gmeiner INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1730a8c21a54SThe etnaviv authors init_waitqueue_head(&gpu->fence_event); 1731a8c21a54SThe etnaviv authors 1732a8c21a54SThe etnaviv authors priv->gpu[priv->num_gpus++] = gpu; 1733a8c21a54SThe etnaviv authors 1734a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1735a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1736a8c21a54SThe etnaviv authors 1737a8c21a54SThe etnaviv authors return 0; 1738e93b6deeSLucas Stach 1739e93b6deeSLucas Stach out_sched: 1740e93b6deeSLucas Stach etnaviv_sched_fini(gpu); 1741e93b6deeSLucas Stach 1742e93b6deeSLucas Stach out_workqueue: 1743e93b6deeSLucas Stach destroy_workqueue(gpu->wq); 1744e93b6deeSLucas Stach 1745e93b6deeSLucas Stach out_thermal: 1746e93b6deeSLucas Stach if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1747e93b6deeSLucas Stach thermal_cooling_device_unregister(gpu->cooling); 1748e93b6deeSLucas Stach 1749e93b6deeSLucas Stach return ret; 1750a8c21a54SThe etnaviv authors } 1751a8c21a54SThe etnaviv authors 1752a8c21a54SThe etnaviv authors static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1753a8c21a54SThe etnaviv authors void *data) 1754a8c21a54SThe etnaviv authors { 1755a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1756a8c21a54SThe etnaviv authors 1757a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 1758a8c21a54SThe etnaviv authors 1759a7790d78SLucas Stach destroy_workqueue(gpu->wq); 1760a7790d78SLucas Stach 1761e93b6deeSLucas Stach etnaviv_sched_fini(gpu); 1762e93b6deeSLucas Stach 1763a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1764a8c21a54SThe etnaviv authors pm_runtime_get_sync(gpu->dev); 1765a8c21a54SThe etnaviv authors pm_runtime_put_sync_suspend(gpu->dev); 1766a8c21a54SThe etnaviv authors #else 1767a8c21a54SThe etnaviv authors etnaviv_gpu_hw_suspend(gpu); 1768a8c21a54SThe etnaviv authors #endif 1769a8c21a54SThe etnaviv authors 17708f3eea9dSLucas Stach if (gpu->mmu_context) 17718f3eea9dSLucas Stach etnaviv_iommu_context_put(gpu->mmu_context); 17728f3eea9dSLucas Stach 1773db41fe7dSLucas Stach if (gpu->initialized) { 17742f9225dbSLucas Stach etnaviv_cmdbuf_free(&gpu->buffer); 177527b67278SLucas Stach etnaviv_iommu_global_fini(gpu); 1776db41fe7dSLucas Stach gpu->initialized = false; 1777a8c21a54SThe etnaviv authors } 1778a8c21a54SThe etnaviv authors 1779a8c21a54SThe etnaviv authors gpu->drm = NULL; 17808bc4d885SLucas Stach idr_destroy(&gpu->fence_idr); 1781bcdfb5e5SRussell King 178249b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1783bcdfb5e5SRussell King thermal_cooling_device_unregister(gpu->cooling); 1784bcdfb5e5SRussell King gpu->cooling = NULL; 1785a8c21a54SThe etnaviv authors } 1786a8c21a54SThe etnaviv authors 1787a8c21a54SThe etnaviv authors static const struct component_ops gpu_ops = { 1788a8c21a54SThe etnaviv authors .bind = etnaviv_gpu_bind, 1789a8c21a54SThe etnaviv authors .unbind = etnaviv_gpu_unbind, 1790a8c21a54SThe etnaviv authors }; 1791a8c21a54SThe etnaviv authors 1792a8c21a54SThe etnaviv authors static const struct of_device_id etnaviv_gpu_match[] = { 1793a8c21a54SThe etnaviv authors { 1794a8c21a54SThe etnaviv authors .compatible = "vivante,gc" 1795a8c21a54SThe etnaviv authors }, 1796a8c21a54SThe etnaviv authors { /* sentinel */ } 1797a8c21a54SThe etnaviv authors }; 1798246774d1SLucas Stach MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1799a8c21a54SThe etnaviv authors 1800a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1801a8c21a54SThe etnaviv authors { 1802a8c21a54SThe etnaviv authors struct device *dev = &pdev->dev; 1803a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1804dc227890SFabio Estevam int err; 1805a8c21a54SThe etnaviv authors 1806a8c21a54SThe etnaviv authors gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1807a8c21a54SThe etnaviv authors if (!gpu) 1808a8c21a54SThe etnaviv authors return -ENOMEM; 1809a8c21a54SThe etnaviv authors 1810a8c21a54SThe etnaviv authors gpu->dev = &pdev->dev; 1811a8c21a54SThe etnaviv authors mutex_init(&gpu->lock); 1812a0780bb1SLucas Stach mutex_init(&gpu->fence_lock); 1813a8c21a54SThe etnaviv authors 1814a8c21a54SThe etnaviv authors /* Map registers: */ 1815facb180dSFabio Estevam gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1816a8c21a54SThe etnaviv authors if (IS_ERR(gpu->mmio)) 1817a8c21a54SThe etnaviv authors return PTR_ERR(gpu->mmio); 1818a8c21a54SThe etnaviv authors 1819a8c21a54SThe etnaviv authors /* Get Interrupt: */ 1820a8c21a54SThe etnaviv authors gpu->irq = platform_get_irq(pdev, 0); 18210e63302dSTian Tao if (gpu->irq < 0) 1822db60eda3SFabio Estevam return gpu->irq; 1823a8c21a54SThe etnaviv authors 1824a8c21a54SThe etnaviv authors err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1825a8c21a54SThe etnaviv authors dev_name(gpu->dev), gpu); 1826a8c21a54SThe etnaviv authors if (err) { 1827a8c21a54SThe etnaviv authors dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1828db60eda3SFabio Estevam return err; 1829a8c21a54SThe etnaviv authors } 1830a8c21a54SThe etnaviv authors 1831a8c21a54SThe etnaviv authors /* Get Clocks: */ 1832f76fc5ffSLubomir Rintel gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 183365f037e8SLucas Stach DBG("clk_reg: %p", gpu->clk_reg); 183465f037e8SLucas Stach if (IS_ERR(gpu->clk_reg)) 1835f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_reg); 183665f037e8SLucas Stach 1837f76fc5ffSLubomir Rintel gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1838a8c21a54SThe etnaviv authors DBG("clk_bus: %p", gpu->clk_bus); 1839a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_bus)) 1840f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_bus); 1841a8c21a54SThe etnaviv authors 1842a59052d2SLubomir Rintel gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1843a8c21a54SThe etnaviv authors DBG("clk_core: %p", gpu->clk_core); 1844a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_core)) 1845f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_core); 1846d79fd1ccSLucas Stach gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1847a8c21a54SThe etnaviv authors 1848f76fc5ffSLubomir Rintel gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1849a8c21a54SThe etnaviv authors DBG("clk_shader: %p", gpu->clk_shader); 1850a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_shader)) 1851f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_shader); 1852d79fd1ccSLucas Stach gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1853a8c21a54SThe etnaviv authors 1854a8c21a54SThe etnaviv authors /* TODO: figure out max mapped size */ 1855a8c21a54SThe etnaviv authors dev_set_drvdata(dev, gpu); 1856a8c21a54SThe etnaviv authors 1857a8c21a54SThe etnaviv authors /* 1858a8c21a54SThe etnaviv authors * We treat the device as initially suspended. The runtime PM 1859a8c21a54SThe etnaviv authors * autosuspend delay is rather arbitary: no measurements have 1860a8c21a54SThe etnaviv authors * yet been performed to determine an appropriate value. 1861a8c21a54SThe etnaviv authors */ 1862a8c21a54SThe etnaviv authors pm_runtime_use_autosuspend(gpu->dev); 1863a8c21a54SThe etnaviv authors pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1864a8c21a54SThe etnaviv authors pm_runtime_enable(gpu->dev); 1865a8c21a54SThe etnaviv authors 1866a8c21a54SThe etnaviv authors err = component_add(&pdev->dev, &gpu_ops); 1867a8c21a54SThe etnaviv authors if (err < 0) { 1868a8c21a54SThe etnaviv authors dev_err(&pdev->dev, "failed to register component: %d\n", err); 1869db60eda3SFabio Estevam return err; 1870a8c21a54SThe etnaviv authors } 1871a8c21a54SThe etnaviv authors 1872a8c21a54SThe etnaviv authors return 0; 1873a8c21a54SThe etnaviv authors } 1874a8c21a54SThe etnaviv authors 1875a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1876a8c21a54SThe etnaviv authors { 1877a8c21a54SThe etnaviv authors component_del(&pdev->dev, &gpu_ops); 1878a8c21a54SThe etnaviv authors pm_runtime_disable(&pdev->dev); 1879a8c21a54SThe etnaviv authors return 0; 1880a8c21a54SThe etnaviv authors } 1881a8c21a54SThe etnaviv authors 1882a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1883a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_suspend(struct device *dev) 1884a8c21a54SThe etnaviv authors { 1885a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1886a8c21a54SThe etnaviv authors u32 idle, mask; 1887a8c21a54SThe etnaviv authors 1888f4163814SLucas Stach /* If there are any jobs in the HW queue, we're not idle */ 1889f4163814SLucas Stach if (atomic_read(&gpu->sched.hw_rq_count)) 1890a8c21a54SThe etnaviv authors return -EBUSY; 1891a8c21a54SThe etnaviv authors 18921a910c11SGuido Günther /* Check whether the hardware (except FE and MC) is idle */ 18931a910c11SGuido Günther mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 18941a910c11SGuido Günther VIVS_HI_IDLE_STATE_MC); 1895a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 189678f2bfa3SGuido Günther if (idle != mask) { 189778f2bfa3SGuido Günther dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 189878f2bfa3SGuido Günther idle); 1899a8c21a54SThe etnaviv authors return -EBUSY; 190078f2bfa3SGuido Günther } 1901a8c21a54SThe etnaviv authors 1902a8c21a54SThe etnaviv authors return etnaviv_gpu_hw_suspend(gpu); 1903a8c21a54SThe etnaviv authors } 1904a8c21a54SThe etnaviv authors 1905a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_resume(struct device *dev) 1906a8c21a54SThe etnaviv authors { 1907a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1908a8c21a54SThe etnaviv authors int ret; 1909a8c21a54SThe etnaviv authors 1910a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1911a8c21a54SThe etnaviv authors if (ret) 1912a8c21a54SThe etnaviv authors return ret; 1913a8c21a54SThe etnaviv authors 1914a8c21a54SThe etnaviv authors /* Re-initialise the basic hardware state */ 1915db41fe7dSLucas Stach if (gpu->drm && gpu->initialized) { 1916a8c21a54SThe etnaviv authors ret = etnaviv_gpu_hw_resume(gpu); 1917a8c21a54SThe etnaviv authors if (ret) { 1918a8c21a54SThe etnaviv authors etnaviv_gpu_clk_disable(gpu); 1919a8c21a54SThe etnaviv authors return ret; 1920a8c21a54SThe etnaviv authors } 1921a8c21a54SThe etnaviv authors } 1922a8c21a54SThe etnaviv authors 1923a8c21a54SThe etnaviv authors return 0; 1924a8c21a54SThe etnaviv authors } 1925a8c21a54SThe etnaviv authors #endif 1926a8c21a54SThe etnaviv authors 1927a8c21a54SThe etnaviv authors static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1928a8c21a54SThe etnaviv authors SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1929a8c21a54SThe etnaviv authors NULL) 1930a8c21a54SThe etnaviv authors }; 1931a8c21a54SThe etnaviv authors 1932a8c21a54SThe etnaviv authors struct platform_driver etnaviv_gpu_driver = { 1933a8c21a54SThe etnaviv authors .driver = { 1934a8c21a54SThe etnaviv authors .name = "etnaviv-gpu", 1935a8c21a54SThe etnaviv authors .owner = THIS_MODULE, 1936a8c21a54SThe etnaviv authors .pm = &etnaviv_gpu_pm_ops, 1937a8c21a54SThe etnaviv authors .of_match_table = etnaviv_gpu_match, 1938a8c21a54SThe etnaviv authors }, 1939a8c21a54SThe etnaviv authors .probe = etnaviv_gpu_platform_probe, 1940a8c21a54SThe etnaviv authors .remove = etnaviv_gpu_platform_remove, 1941a8c21a54SThe etnaviv authors .id_table = gpu_ids, 1942a8c21a54SThe etnaviv authors }; 1943