1a8c21a54SThe etnaviv authors /* 2a8c21a54SThe etnaviv authors * Copyright (C) 2015 Etnaviv Project 3a8c21a54SThe etnaviv authors * 4a8c21a54SThe etnaviv authors * This program is free software; you can redistribute it and/or modify it 5a8c21a54SThe etnaviv authors * under the terms of the GNU General Public License version 2 as published by 6a8c21a54SThe etnaviv authors * the Free Software Foundation. 7a8c21a54SThe etnaviv authors * 8a8c21a54SThe etnaviv authors * This program is distributed in the hope that it will be useful, but WITHOUT 9a8c21a54SThe etnaviv authors * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10a8c21a54SThe etnaviv authors * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11a8c21a54SThe etnaviv authors * more details. 12a8c21a54SThe etnaviv authors * 13a8c21a54SThe etnaviv authors * You should have received a copy of the GNU General Public License along with 14a8c21a54SThe etnaviv authors * this program. If not, see <http://www.gnu.org/licenses/>. 15a8c21a54SThe etnaviv authors */ 16a8c21a54SThe etnaviv authors 17a8c21a54SThe etnaviv authors #include <linux/component.h> 18f54d1867SChris Wilson #include <linux/dma-fence.h> 19a8c21a54SThe etnaviv authors #include <linux/moduleparam.h> 20a8c21a54SThe etnaviv authors #include <linux/of_device.h> 21ea1f5729SLucas Stach 22ea1f5729SLucas Stach #include "etnaviv_cmdbuf.h" 23a8c21a54SThe etnaviv authors #include "etnaviv_dump.h" 24a8c21a54SThe etnaviv authors #include "etnaviv_gpu.h" 25a8c21a54SThe etnaviv authors #include "etnaviv_gem.h" 26a8c21a54SThe etnaviv authors #include "etnaviv_mmu.h" 27a8c21a54SThe etnaviv authors #include "common.xml.h" 28a8c21a54SThe etnaviv authors #include "state.xml.h" 29a8c21a54SThe etnaviv authors #include "state_hi.xml.h" 30a8c21a54SThe etnaviv authors #include "cmdstream.xml.h" 31a8c21a54SThe etnaviv authors 32a8c21a54SThe etnaviv authors static const struct platform_device_id gpu_ids[] = { 33a8c21a54SThe etnaviv authors { .name = "etnaviv-gpu,2d" }, 34a8c21a54SThe etnaviv authors { }, 35a8c21a54SThe etnaviv authors }; 36a8c21a54SThe etnaviv authors 37a8c21a54SThe etnaviv authors static bool etnaviv_dump_core = true; 38a8c21a54SThe etnaviv authors module_param_named(dump_core, etnaviv_dump_core, bool, 0600); 39a8c21a54SThe etnaviv authors 40a8c21a54SThe etnaviv authors /* 41a8c21a54SThe etnaviv authors * Driver functions: 42a8c21a54SThe etnaviv authors */ 43a8c21a54SThe etnaviv authors 44a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 45a8c21a54SThe etnaviv authors { 46a8c21a54SThe etnaviv authors switch (param) { 47a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_MODEL: 48a8c21a54SThe etnaviv authors *value = gpu->identity.model; 49a8c21a54SThe etnaviv authors break; 50a8c21a54SThe etnaviv authors 51a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REVISION: 52a8c21a54SThe etnaviv authors *value = gpu->identity.revision; 53a8c21a54SThe etnaviv authors break; 54a8c21a54SThe etnaviv authors 55a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_0: 56a8c21a54SThe etnaviv authors *value = gpu->identity.features; 57a8c21a54SThe etnaviv authors break; 58a8c21a54SThe etnaviv authors 59a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_1: 60a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features0; 61a8c21a54SThe etnaviv authors break; 62a8c21a54SThe etnaviv authors 63a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_2: 64a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features1; 65a8c21a54SThe etnaviv authors break; 66a8c21a54SThe etnaviv authors 67a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_3: 68a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features2; 69a8c21a54SThe etnaviv authors break; 70a8c21a54SThe etnaviv authors 71a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_4: 72a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features3; 73a8c21a54SThe etnaviv authors break; 74a8c21a54SThe etnaviv authors 75602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_5: 76602eb489SRussell King *value = gpu->identity.minor_features4; 77602eb489SRussell King break; 78602eb489SRussell King 79602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_6: 80602eb489SRussell King *value = gpu->identity.minor_features5; 81602eb489SRussell King break; 82602eb489SRussell King 83a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_STREAM_COUNT: 84a8c21a54SThe etnaviv authors *value = gpu->identity.stream_count; 85a8c21a54SThe etnaviv authors break; 86a8c21a54SThe etnaviv authors 87a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REGISTER_MAX: 88a8c21a54SThe etnaviv authors *value = gpu->identity.register_max; 89a8c21a54SThe etnaviv authors break; 90a8c21a54SThe etnaviv authors 91a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_THREAD_COUNT: 92a8c21a54SThe etnaviv authors *value = gpu->identity.thread_count; 93a8c21a54SThe etnaviv authors break; 94a8c21a54SThe etnaviv authors 95a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 96a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_cache_size; 97a8c21a54SThe etnaviv authors break; 98a8c21a54SThe etnaviv authors 99a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 100a8c21a54SThe etnaviv authors *value = gpu->identity.shader_core_count; 101a8c21a54SThe etnaviv authors break; 102a8c21a54SThe etnaviv authors 103a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 104a8c21a54SThe etnaviv authors *value = gpu->identity.pixel_pipes; 105a8c21a54SThe etnaviv authors break; 106a8c21a54SThe etnaviv authors 107a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 108a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_output_buffer_size; 109a8c21a54SThe etnaviv authors break; 110a8c21a54SThe etnaviv authors 111a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 112a8c21a54SThe etnaviv authors *value = gpu->identity.buffer_size; 113a8c21a54SThe etnaviv authors break; 114a8c21a54SThe etnaviv authors 115a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 116a8c21a54SThe etnaviv authors *value = gpu->identity.instruction_count; 117a8c21a54SThe etnaviv authors break; 118a8c21a54SThe etnaviv authors 119a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 120a8c21a54SThe etnaviv authors *value = gpu->identity.num_constants; 121a8c21a54SThe etnaviv authors break; 122a8c21a54SThe etnaviv authors 123602eb489SRussell King case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 124602eb489SRussell King *value = gpu->identity.varyings_count; 125602eb489SRussell King break; 126602eb489SRussell King 127a8c21a54SThe etnaviv authors default: 128a8c21a54SThe etnaviv authors DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 129a8c21a54SThe etnaviv authors return -EINVAL; 130a8c21a54SThe etnaviv authors } 131a8c21a54SThe etnaviv authors 132a8c21a54SThe etnaviv authors return 0; 133a8c21a54SThe etnaviv authors } 134a8c21a54SThe etnaviv authors 135472f79dcSRussell King 136472f79dcSRussell King #define etnaviv_is_model_rev(gpu, mod, rev) \ 137472f79dcSRussell King ((gpu)->identity.model == chipModel_##mod && \ 138472f79dcSRussell King (gpu)->identity.revision == rev) 13952f36ba1SRussell King #define etnaviv_field(val, field) \ 14052f36ba1SRussell King (((val) & field##__MASK) >> field##__SHIFT) 14152f36ba1SRussell King 142a8c21a54SThe etnaviv authors static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 143a8c21a54SThe etnaviv authors { 144a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 145a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 146602eb489SRussell King u32 specs[4]; 147602eb489SRussell King unsigned int streams; 148a8c21a54SThe etnaviv authors 149a8c21a54SThe etnaviv authors specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 150a8c21a54SThe etnaviv authors specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 151602eb489SRussell King specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 152602eb489SRussell King specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 153a8c21a54SThe etnaviv authors 15452f36ba1SRussell King gpu->identity.stream_count = etnaviv_field(specs[0], 15552f36ba1SRussell King VIVS_HI_CHIP_SPECS_STREAM_COUNT); 15652f36ba1SRussell King gpu->identity.register_max = etnaviv_field(specs[0], 15752f36ba1SRussell King VIVS_HI_CHIP_SPECS_REGISTER_MAX); 15852f36ba1SRussell King gpu->identity.thread_count = etnaviv_field(specs[0], 15952f36ba1SRussell King VIVS_HI_CHIP_SPECS_THREAD_COUNT); 16052f36ba1SRussell King gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 16152f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 16252f36ba1SRussell King gpu->identity.shader_core_count = etnaviv_field(specs[0], 16352f36ba1SRussell King VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 16452f36ba1SRussell King gpu->identity.pixel_pipes = etnaviv_field(specs[0], 16552f36ba1SRussell King VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 166a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 16752f36ba1SRussell King etnaviv_field(specs[0], 16852f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 169a8c21a54SThe etnaviv authors 17052f36ba1SRussell King gpu->identity.buffer_size = etnaviv_field(specs[1], 17152f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 17252f36ba1SRussell King gpu->identity.instruction_count = etnaviv_field(specs[1], 17352f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 17452f36ba1SRussell King gpu->identity.num_constants = etnaviv_field(specs[1], 17552f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 176602eb489SRussell King 177602eb489SRussell King gpu->identity.varyings_count = etnaviv_field(specs[2], 178602eb489SRussell King VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 179602eb489SRussell King 180602eb489SRussell King /* This overrides the value from older register if non-zero */ 181602eb489SRussell King streams = etnaviv_field(specs[3], 182602eb489SRussell King VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 183602eb489SRussell King if (streams) 184602eb489SRussell King gpu->identity.stream_count = streams; 185a8c21a54SThe etnaviv authors } 186a8c21a54SThe etnaviv authors 187a8c21a54SThe etnaviv authors /* Fill in the stream count if not specified */ 188a8c21a54SThe etnaviv authors if (gpu->identity.stream_count == 0) { 189a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 190a8c21a54SThe etnaviv authors gpu->identity.stream_count = 4; 191a8c21a54SThe etnaviv authors else 192a8c21a54SThe etnaviv authors gpu->identity.stream_count = 1; 193a8c21a54SThe etnaviv authors } 194a8c21a54SThe etnaviv authors 195a8c21a54SThe etnaviv authors /* Convert the register max value */ 196a8c21a54SThe etnaviv authors if (gpu->identity.register_max) 197a8c21a54SThe etnaviv authors gpu->identity.register_max = 1 << gpu->identity.register_max; 198507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 199a8c21a54SThe etnaviv authors gpu->identity.register_max = 32; 200a8c21a54SThe etnaviv authors else 201a8c21a54SThe etnaviv authors gpu->identity.register_max = 64; 202a8c21a54SThe etnaviv authors 203a8c21a54SThe etnaviv authors /* Convert thread count */ 204a8c21a54SThe etnaviv authors if (gpu->identity.thread_count) 205a8c21a54SThe etnaviv authors gpu->identity.thread_count = 1 << gpu->identity.thread_count; 206507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 207a8c21a54SThe etnaviv authors gpu->identity.thread_count = 64; 208507f8991SRussell King else if (gpu->identity.model == chipModel_GC500 || 209507f8991SRussell King gpu->identity.model == chipModel_GC530) 210a8c21a54SThe etnaviv authors gpu->identity.thread_count = 128; 211a8c21a54SThe etnaviv authors else 212a8c21a54SThe etnaviv authors gpu->identity.thread_count = 256; 213a8c21a54SThe etnaviv authors 214a8c21a54SThe etnaviv authors if (gpu->identity.vertex_cache_size == 0) 215a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size = 8; 216a8c21a54SThe etnaviv authors 217a8c21a54SThe etnaviv authors if (gpu->identity.shader_core_count == 0) { 218a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 219a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 2; 220a8c21a54SThe etnaviv authors else 221a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 1; 222a8c21a54SThe etnaviv authors } 223a8c21a54SThe etnaviv authors 224a8c21a54SThe etnaviv authors if (gpu->identity.pixel_pipes == 0) 225a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes = 1; 226a8c21a54SThe etnaviv authors 227a8c21a54SThe etnaviv authors /* Convert virtex buffer size */ 228a8c21a54SThe etnaviv authors if (gpu->identity.vertex_output_buffer_size) { 229a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 230a8c21a54SThe etnaviv authors 1 << gpu->identity.vertex_output_buffer_size; 231507f8991SRussell King } else if (gpu->identity.model == chipModel_GC400) { 232a8c21a54SThe etnaviv authors if (gpu->identity.revision < 0x4000) 233a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 234a8c21a54SThe etnaviv authors else if (gpu->identity.revision < 0x4200) 235a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 256; 236a8c21a54SThe etnaviv authors else 237a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 128; 238a8c21a54SThe etnaviv authors } else { 239a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 240a8c21a54SThe etnaviv authors } 241a8c21a54SThe etnaviv authors 242a8c21a54SThe etnaviv authors switch (gpu->identity.instruction_count) { 243a8c21a54SThe etnaviv authors case 0: 244472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 245507f8991SRussell King gpu->identity.model == chipModel_GC880) 246a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 512; 247a8c21a54SThe etnaviv authors else 248a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 249a8c21a54SThe etnaviv authors break; 250a8c21a54SThe etnaviv authors 251a8c21a54SThe etnaviv authors case 1: 252a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 1024; 253a8c21a54SThe etnaviv authors break; 254a8c21a54SThe etnaviv authors 255a8c21a54SThe etnaviv authors case 2: 256a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 2048; 257a8c21a54SThe etnaviv authors break; 258a8c21a54SThe etnaviv authors 259a8c21a54SThe etnaviv authors default: 260a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 261a8c21a54SThe etnaviv authors break; 262a8c21a54SThe etnaviv authors } 263a8c21a54SThe etnaviv authors 264a8c21a54SThe etnaviv authors if (gpu->identity.num_constants == 0) 265a8c21a54SThe etnaviv authors gpu->identity.num_constants = 168; 266602eb489SRussell King 267602eb489SRussell King if (gpu->identity.varyings_count == 0) { 268602eb489SRussell King if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 269602eb489SRussell King gpu->identity.varyings_count = 12; 270602eb489SRussell King else 271602eb489SRussell King gpu->identity.varyings_count = 8; 272602eb489SRussell King } 273602eb489SRussell King 274602eb489SRussell King /* 275602eb489SRussell King * For some cores, two varyings are consumed for position, so the 276602eb489SRussell King * maximum varying count needs to be reduced by one. 277602eb489SRussell King */ 278602eb489SRussell King if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 279602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 280602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 281602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 282602eb489SRussell King etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 283602eb489SRussell King etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 284602eb489SRussell King etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 285602eb489SRussell King etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 286602eb489SRussell King etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 287602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5107) || 288602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5106)) 289602eb489SRussell King gpu->identity.varyings_count -= 1; 290a8c21a54SThe etnaviv authors } 291a8c21a54SThe etnaviv authors 292a8c21a54SThe etnaviv authors static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 293a8c21a54SThe etnaviv authors { 294a8c21a54SThe etnaviv authors u32 chipIdentity; 295a8c21a54SThe etnaviv authors 296a8c21a54SThe etnaviv authors chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 297a8c21a54SThe etnaviv authors 298a8c21a54SThe etnaviv authors /* Special case for older graphic cores. */ 29952f36ba1SRussell King if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 300507f8991SRussell King gpu->identity.model = chipModel_GC500; 30152f36ba1SRussell King gpu->identity.revision = etnaviv_field(chipIdentity, 30252f36ba1SRussell King VIVS_HI_CHIP_IDENTITY_REVISION); 303a8c21a54SThe etnaviv authors } else { 304a8c21a54SThe etnaviv authors 305a8c21a54SThe etnaviv authors gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 306a8c21a54SThe etnaviv authors gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 307a8c21a54SThe etnaviv authors 308a8c21a54SThe etnaviv authors /* 309a8c21a54SThe etnaviv authors * !!!! HACK ALERT !!!! 310a8c21a54SThe etnaviv authors * Because people change device IDs without letting software 311a8c21a54SThe etnaviv authors * know about it - here is the hack to make it all look the 312a8c21a54SThe etnaviv authors * same. Only for GC400 family. 313a8c21a54SThe etnaviv authors */ 314a8c21a54SThe etnaviv authors if ((gpu->identity.model & 0xff00) == 0x0400 && 315507f8991SRussell King gpu->identity.model != chipModel_GC420) { 316a8c21a54SThe etnaviv authors gpu->identity.model = gpu->identity.model & 0x0400; 317a8c21a54SThe etnaviv authors } 318a8c21a54SThe etnaviv authors 319a8c21a54SThe etnaviv authors /* Another special case */ 320472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 321a8c21a54SThe etnaviv authors u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 322a8c21a54SThe etnaviv authors u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 323a8c21a54SThe etnaviv authors 324a8c21a54SThe etnaviv authors if (chipDate == 0x20080814 && chipTime == 0x12051100) { 325a8c21a54SThe etnaviv authors /* 326a8c21a54SThe etnaviv authors * This IP has an ECO; put the correct 327a8c21a54SThe etnaviv authors * revision in it. 328a8c21a54SThe etnaviv authors */ 329a8c21a54SThe etnaviv authors gpu->identity.revision = 0x1051; 330a8c21a54SThe etnaviv authors } 331a8c21a54SThe etnaviv authors } 33212ff4bdeSLucas Stach 33312ff4bdeSLucas Stach /* 33412ff4bdeSLucas Stach * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 33512ff4bdeSLucas Stach * reality it's just a re-branded GC3000. We can identify this 33612ff4bdeSLucas Stach * core by the upper half of the revision register being all 1. 33712ff4bdeSLucas Stach * Fix model/rev here, so all other places can refer to this 33812ff4bdeSLucas Stach * core by its real identity. 33912ff4bdeSLucas Stach */ 34012ff4bdeSLucas Stach if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 34112ff4bdeSLucas Stach gpu->identity.model = chipModel_GC3000; 34212ff4bdeSLucas Stach gpu->identity.revision &= 0xffff; 34312ff4bdeSLucas Stach } 344a8c21a54SThe etnaviv authors } 345a8c21a54SThe etnaviv authors 346a8c21a54SThe etnaviv authors dev_info(gpu->dev, "model: GC%x, revision: %x\n", 347a8c21a54SThe etnaviv authors gpu->identity.model, gpu->identity.revision); 348a8c21a54SThe etnaviv authors 349a8c21a54SThe etnaviv authors gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 350a8c21a54SThe etnaviv authors 351a8c21a54SThe etnaviv authors /* Disable fast clear on GC700. */ 352507f8991SRussell King if (gpu->identity.model == chipModel_GC700) 353a8c21a54SThe etnaviv authors gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 354a8c21a54SThe etnaviv authors 355507f8991SRussell King if ((gpu->identity.model == chipModel_GC500 && 356507f8991SRussell King gpu->identity.revision < 2) || 357507f8991SRussell King (gpu->identity.model == chipModel_GC300 && 358507f8991SRussell King gpu->identity.revision < 0x2000)) { 359a8c21a54SThe etnaviv authors 360a8c21a54SThe etnaviv authors /* 361a8c21a54SThe etnaviv authors * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 362a8c21a54SThe etnaviv authors * registers. 363a8c21a54SThe etnaviv authors */ 364a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 0; 365a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 0; 366a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 0; 367a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 0; 368602eb489SRussell King gpu->identity.minor_features4 = 0; 369602eb489SRussell King gpu->identity.minor_features5 = 0; 370a8c21a54SThe etnaviv authors } else 371a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 372a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 373a8c21a54SThe etnaviv authors 374a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 375a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 376a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 377a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 378a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 379a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 380a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 381a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 382602eb489SRussell King gpu->identity.minor_features4 = 383602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 384602eb489SRussell King gpu->identity.minor_features5 = 385602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 386a8c21a54SThe etnaviv authors } 387a8c21a54SThe etnaviv authors 388a8c21a54SThe etnaviv authors /* GC600 idle register reports zero bits where modules aren't present */ 389a8c21a54SThe etnaviv authors if (gpu->identity.model == chipModel_GC600) { 390a8c21a54SThe etnaviv authors gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 391a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_RA | 392a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SE | 393a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PA | 394a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SH | 395a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PE | 396a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_DE | 397a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_FE; 398a8c21a54SThe etnaviv authors } else { 399a8c21a54SThe etnaviv authors gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 400a8c21a54SThe etnaviv authors } 401a8c21a54SThe etnaviv authors 402a8c21a54SThe etnaviv authors etnaviv_hw_specs(gpu); 403a8c21a54SThe etnaviv authors } 404a8c21a54SThe etnaviv authors 405a8c21a54SThe etnaviv authors static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 406a8c21a54SThe etnaviv authors { 407a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 408a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 409a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 410a8c21a54SThe etnaviv authors } 411a8c21a54SThe etnaviv authors 412a8c21a54SThe etnaviv authors static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 413a8c21a54SThe etnaviv authors { 414a8c21a54SThe etnaviv authors u32 control, idle; 415a8c21a54SThe etnaviv authors unsigned long timeout; 416a8c21a54SThe etnaviv authors bool failed = true; 417a8c21a54SThe etnaviv authors 418a8c21a54SThe etnaviv authors /* TODO 419a8c21a54SThe etnaviv authors * 420a8c21a54SThe etnaviv authors * - clock gating 421a8c21a54SThe etnaviv authors * - puls eater 422a8c21a54SThe etnaviv authors * - what about VG? 423a8c21a54SThe etnaviv authors */ 424a8c21a54SThe etnaviv authors 425a8c21a54SThe etnaviv authors /* We hope that the GPU resets in under one second */ 426a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(1000); 427a8c21a54SThe etnaviv authors 428a8c21a54SThe etnaviv authors while (time_is_after_jiffies(timeout)) { 429a8c21a54SThe etnaviv authors control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 430a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 431a8c21a54SThe etnaviv authors 432a8c21a54SThe etnaviv authors /* enable clock */ 433a8c21a54SThe etnaviv authors etnaviv_gpu_load_clock(gpu, control); 434a8c21a54SThe etnaviv authors 435a8c21a54SThe etnaviv authors /* Wait for stable clock. Vivante's code waited for 1ms */ 436a8c21a54SThe etnaviv authors usleep_range(1000, 10000); 437a8c21a54SThe etnaviv authors 438a8c21a54SThe etnaviv authors /* isolate the GPU. */ 439a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 440a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 441a8c21a54SThe etnaviv authors 442a8c21a54SThe etnaviv authors /* set soft reset. */ 443a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 444a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 445a8c21a54SThe etnaviv authors 446a8c21a54SThe etnaviv authors /* wait for reset. */ 447a8c21a54SThe etnaviv authors msleep(1); 448a8c21a54SThe etnaviv authors 449a8c21a54SThe etnaviv authors /* reset soft reset bit. */ 450a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 451a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 452a8c21a54SThe etnaviv authors 453a8c21a54SThe etnaviv authors /* reset GPU isolation. */ 454a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 455a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 456a8c21a54SThe etnaviv authors 457a8c21a54SThe etnaviv authors /* read idle register. */ 458a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 459a8c21a54SThe etnaviv authors 460a8c21a54SThe etnaviv authors /* try reseting again if FE it not idle */ 461a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 462a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "FE is not idle\n"); 463a8c21a54SThe etnaviv authors continue; 464a8c21a54SThe etnaviv authors } 465a8c21a54SThe etnaviv authors 466a8c21a54SThe etnaviv authors /* read reset register. */ 467a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 468a8c21a54SThe etnaviv authors 469a8c21a54SThe etnaviv authors /* is the GPU idle? */ 470a8c21a54SThe etnaviv authors if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 471a8c21a54SThe etnaviv authors ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 472a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "GPU is not idle\n"); 473a8c21a54SThe etnaviv authors continue; 474a8c21a54SThe etnaviv authors } 475a8c21a54SThe etnaviv authors 476a8c21a54SThe etnaviv authors failed = false; 477a8c21a54SThe etnaviv authors break; 478a8c21a54SThe etnaviv authors } 479a8c21a54SThe etnaviv authors 480a8c21a54SThe etnaviv authors if (failed) { 481a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 482a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 483a8c21a54SThe etnaviv authors 484a8c21a54SThe etnaviv authors dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 485a8c21a54SThe etnaviv authors idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 486a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 487a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 488a8c21a54SThe etnaviv authors 489a8c21a54SThe etnaviv authors return -EBUSY; 490a8c21a54SThe etnaviv authors } 491a8c21a54SThe etnaviv authors 492a8c21a54SThe etnaviv authors /* We rely on the GPU running, so program the clock */ 493a8c21a54SThe etnaviv authors control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 494a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 495a8c21a54SThe etnaviv authors 496a8c21a54SThe etnaviv authors /* enable clock */ 497a8c21a54SThe etnaviv authors etnaviv_gpu_load_clock(gpu, control); 498a8c21a54SThe etnaviv authors 499a8c21a54SThe etnaviv authors return 0; 500a8c21a54SThe etnaviv authors } 501a8c21a54SThe etnaviv authors 5027d0c6e71SRussell King static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 5037d0c6e71SRussell King { 5047d0c6e71SRussell King u32 pmc, ppc; 5057d0c6e71SRussell King 5067d0c6e71SRussell King /* enable clock gating */ 5077d0c6e71SRussell King ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 5087d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 5097d0c6e71SRussell King 5107d0c6e71SRussell King /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 5117d0c6e71SRussell King if (gpu->identity.revision == 0x4301 || 5127d0c6e71SRussell King gpu->identity.revision == 0x4302) 5137d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 5147d0c6e71SRussell King 5157d0c6e71SRussell King gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 5167d0c6e71SRussell King 5177d0c6e71SRussell King pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 5187d0c6e71SRussell King 5197d0c6e71SRussell King /* Disable PA clock gating for GC400+ except for GC420 */ 5207d0c6e71SRussell King if (gpu->identity.model >= chipModel_GC400 && 5217d0c6e71SRussell King gpu->identity.model != chipModel_GC420) 5227d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 5237d0c6e71SRussell King 5247d0c6e71SRussell King /* 5257d0c6e71SRussell King * Disable PE clock gating on revs < 5.0.0.0 when HZ is 5267d0c6e71SRussell King * present without a bug fix. 5277d0c6e71SRussell King */ 5287d0c6e71SRussell King if (gpu->identity.revision < 0x5000 && 5297d0c6e71SRussell King gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 5307d0c6e71SRussell King !(gpu->identity.minor_features1 & 5317d0c6e71SRussell King chipMinorFeatures1_DISABLE_PE_GATING)) 5327d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 5337d0c6e71SRussell King 5347d0c6e71SRussell King if (gpu->identity.revision < 0x5422) 5357d0c6e71SRussell King pmc |= BIT(15); /* Unknown bit */ 5367d0c6e71SRussell King 5377d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 5387d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 5397d0c6e71SRussell King 5407d0c6e71SRussell King gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 5417d0c6e71SRussell King } 5427d0c6e71SRussell King 543229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 544229855b6SLucas Stach { 545229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 546229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 547229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_ENABLE | 548229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 549229855b6SLucas Stach } 550229855b6SLucas Stach 551e17a0dedSWladimir J. van der Laan static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 552e17a0dedSWladimir J. van der Laan { 553e17a0dedSWladimir J. van der Laan /* 554e17a0dedSWladimir J. van der Laan * Base value for VIVS_PM_PULSE_EATER register on models where it 555e17a0dedSWladimir J. van der Laan * cannot be read, extracted from vivante kernel driver. 556e17a0dedSWladimir J. van der Laan */ 557e17a0dedSWladimir J. van der Laan u32 pulse_eater = 0x01590880; 558e17a0dedSWladimir J. van der Laan 559e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 560e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 561e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(23); 562e17a0dedSWladimir J. van der Laan 563e17a0dedSWladimir J. van der Laan } 564e17a0dedSWladimir J. van der Laan 565e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 566e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 567e17a0dedSWladimir J. van der Laan pulse_eater &= ~BIT(16); 568e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(17); 569e17a0dedSWladimir J. van der Laan } 570e17a0dedSWladimir J. van der Laan 571e17a0dedSWladimir J. van der Laan if ((gpu->identity.revision > 0x5420) && 572e17a0dedSWladimir J. van der Laan (gpu->identity.features & chipFeatures_PIPE_3D)) 573e17a0dedSWladimir J. van der Laan { 574e17a0dedSWladimir J. van der Laan /* Performance fix: disable internal DFS */ 575e17a0dedSWladimir J. van der Laan pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 576e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(18); 577e17a0dedSWladimir J. van der Laan } 578e17a0dedSWladimir J. van der Laan 579e17a0dedSWladimir J. van der Laan gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 580e17a0dedSWladimir J. van der Laan } 581e17a0dedSWladimir J. van der Laan 582a8c21a54SThe etnaviv authors static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 583a8c21a54SThe etnaviv authors { 584a8c21a54SThe etnaviv authors u16 prefetch; 585a8c21a54SThe etnaviv authors 586472f79dcSRussell King if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 587472f79dcSRussell King etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 588472f79dcSRussell King gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 589a8c21a54SThe etnaviv authors u32 mc_memory_debug; 590a8c21a54SThe etnaviv authors 591a8c21a54SThe etnaviv authors mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 592a8c21a54SThe etnaviv authors 593a8c21a54SThe etnaviv authors if (gpu->identity.revision == 0x5007) 594a8c21a54SThe etnaviv authors mc_memory_debug |= 0x0c; 595a8c21a54SThe etnaviv authors else 596a8c21a54SThe etnaviv authors mc_memory_debug |= 0x08; 597a8c21a54SThe etnaviv authors 598a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 599a8c21a54SThe etnaviv authors } 600a8c21a54SThe etnaviv authors 6017d0c6e71SRussell King /* enable module-level clock gating */ 6027d0c6e71SRussell King etnaviv_gpu_enable_mlcg(gpu); 6037d0c6e71SRussell King 604a8c21a54SThe etnaviv authors /* 605a8c21a54SThe etnaviv authors * Update GPU AXI cache atttribute to "cacheable, no allocate". 606a8c21a54SThe etnaviv authors * This is necessary to prevent the iMX6 SoC locking up. 607a8c21a54SThe etnaviv authors */ 608a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_AXI_CONFIG, 609a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_AWCACHE(2) | 610a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_ARCACHE(2)); 611a8c21a54SThe etnaviv authors 612a8c21a54SThe etnaviv authors /* GC2000 rev 5108 needs a special bus config */ 613472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 614a8c21a54SThe etnaviv authors u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 615a8c21a54SThe etnaviv authors bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 616a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 617a8c21a54SThe etnaviv authors bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 618a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 619a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 620a8c21a54SThe etnaviv authors } 621a8c21a54SThe etnaviv authors 622e17a0dedSWladimir J. van der Laan /* setup the pulse eater */ 623e17a0dedSWladimir J. van der Laan etnaviv_gpu_setup_pulse_eater(gpu); 624e17a0dedSWladimir J. van der Laan 62599f861bcSLucas Stach /* setup the MMU */ 626e095c8feSLucas Stach etnaviv_iommu_restore(gpu); 627a8c21a54SThe etnaviv authors 628a8c21a54SThe etnaviv authors /* Start command processor */ 629a8c21a54SThe etnaviv authors prefetch = etnaviv_buffer_init(gpu); 630a8c21a54SThe etnaviv authors 631a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 632c3ef4b8cSLucas Stach etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer), 633229855b6SLucas Stach prefetch); 634a8c21a54SThe etnaviv authors } 635a8c21a54SThe etnaviv authors 636a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 637a8c21a54SThe etnaviv authors { 638a8c21a54SThe etnaviv authors int ret, i; 639a8c21a54SThe etnaviv authors 640a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 6411409df04SLucas Stach if (ret < 0) { 6421409df04SLucas Stach dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 643a8c21a54SThe etnaviv authors return ret; 6441409df04SLucas Stach } 645a8c21a54SThe etnaviv authors 646a8c21a54SThe etnaviv authors etnaviv_hw_identify(gpu); 647a8c21a54SThe etnaviv authors 648a8c21a54SThe etnaviv authors if (gpu->identity.model == 0) { 649a8c21a54SThe etnaviv authors dev_err(gpu->dev, "Unknown GPU model\n"); 650f6427760SRussell King ret = -ENXIO; 651f6427760SRussell King goto fail; 652a8c21a54SThe etnaviv authors } 653a8c21a54SThe etnaviv authors 654b98c6688SRussell King /* Exclude VG cores with FE2.0 */ 655b98c6688SRussell King if (gpu->identity.features & chipFeatures_PIPE_VG && 656b98c6688SRussell King gpu->identity.features & chipFeatures_FE20) { 657b98c6688SRussell King dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 658b98c6688SRussell King ret = -ENXIO; 659b98c6688SRussell King goto fail; 660b98c6688SRussell King } 661b98c6688SRussell King 6622144fff7SLucas Stach /* 6632144fff7SLucas Stach * Set the GPU linear window to be at the end of the DMA window, where 6642144fff7SLucas Stach * the CMA area is likely to reside. This ensures that we are able to 6652144fff7SLucas Stach * map the command buffers while having the linear window overlap as 6662144fff7SLucas Stach * much RAM as possible, so we can optimize mappings for other buffers. 6672144fff7SLucas Stach * 6682144fff7SLucas Stach * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 6692144fff7SLucas Stach * to different views of the memory on the individual engines. 6702144fff7SLucas Stach */ 6712144fff7SLucas Stach if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 6722144fff7SLucas Stach (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 6732144fff7SLucas Stach u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 6742144fff7SLucas Stach if (dma_mask < PHYS_OFFSET + SZ_2G) 6752144fff7SLucas Stach gpu->memory_base = PHYS_OFFSET; 6762144fff7SLucas Stach else 6772144fff7SLucas Stach gpu->memory_base = dma_mask - SZ_2G + 1; 6781db01279SLucas Stach } else if (PHYS_OFFSET >= SZ_2G) { 6791db01279SLucas Stach dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 6801db01279SLucas Stach gpu->memory_base = PHYS_OFFSET; 6811db01279SLucas Stach gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 6822144fff7SLucas Stach } 6832144fff7SLucas Stach 684a8c21a54SThe etnaviv authors ret = etnaviv_hw_reset(gpu); 6851409df04SLucas Stach if (ret) { 6861409df04SLucas Stach dev_err(gpu->dev, "GPU reset failed\n"); 687a8c21a54SThe etnaviv authors goto fail; 6881409df04SLucas Stach } 689a8c21a54SThe etnaviv authors 690dd34bb96SLucas Stach gpu->mmu = etnaviv_iommu_new(gpu); 691dd34bb96SLucas Stach if (IS_ERR(gpu->mmu)) { 6921409df04SLucas Stach dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 693dd34bb96SLucas Stach ret = PTR_ERR(gpu->mmu); 694a8c21a54SThe etnaviv authors goto fail; 695a8c21a54SThe etnaviv authors } 696a8c21a54SThe etnaviv authors 697a8c21a54SThe etnaviv authors /* Create buffer: */ 698ea1f5729SLucas Stach gpu->buffer = etnaviv_cmdbuf_new(gpu, PAGE_SIZE, 0); 699a8c21a54SThe etnaviv authors if (!gpu->buffer) { 700a8c21a54SThe etnaviv authors ret = -ENOMEM; 701a8c21a54SThe etnaviv authors dev_err(gpu->dev, "could not create command buffer\n"); 70245d16a6dSLucas Stach goto destroy_iommu; 703a8c21a54SThe etnaviv authors } 704acfee0ecSLucas Stach 705acfee0ecSLucas Stach if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 706c3ef4b8cSLucas Stach etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) { 707a8c21a54SThe etnaviv authors ret = -EINVAL; 708a8c21a54SThe etnaviv authors dev_err(gpu->dev, 709a8c21a54SThe etnaviv authors "command buffer outside valid memory window\n"); 710a8c21a54SThe etnaviv authors goto free_buffer; 711a8c21a54SThe etnaviv authors } 712a8c21a54SThe etnaviv authors 713a8c21a54SThe etnaviv authors /* Setup event management */ 714a8c21a54SThe etnaviv authors spin_lock_init(&gpu->event_spinlock); 715a8c21a54SThe etnaviv authors init_completion(&gpu->event_free); 716a8c21a54SThe etnaviv authors for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 717a8c21a54SThe etnaviv authors gpu->event[i].used = false; 718a8c21a54SThe etnaviv authors complete(&gpu->event_free); 719a8c21a54SThe etnaviv authors } 720a8c21a54SThe etnaviv authors 721a8c21a54SThe etnaviv authors /* Now program the hardware */ 722a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 723a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 724f6086311SRussell King gpu->exec_state = -1; 725a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 726a8c21a54SThe etnaviv authors 727a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 728a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 729a8c21a54SThe etnaviv authors 730a8c21a54SThe etnaviv authors return 0; 731a8c21a54SThe etnaviv authors 732a8c21a54SThe etnaviv authors free_buffer: 733ea1f5729SLucas Stach etnaviv_cmdbuf_free(gpu->buffer); 734a8c21a54SThe etnaviv authors gpu->buffer = NULL; 73545d16a6dSLucas Stach destroy_iommu: 73645d16a6dSLucas Stach etnaviv_iommu_destroy(gpu->mmu); 73745d16a6dSLucas Stach gpu->mmu = NULL; 738a8c21a54SThe etnaviv authors fail: 739a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 740a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 741a8c21a54SThe etnaviv authors 742a8c21a54SThe etnaviv authors return ret; 743a8c21a54SThe etnaviv authors } 744a8c21a54SThe etnaviv authors 745a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 746a8c21a54SThe etnaviv authors struct dma_debug { 747a8c21a54SThe etnaviv authors u32 address[2]; 748a8c21a54SThe etnaviv authors u32 state[2]; 749a8c21a54SThe etnaviv authors }; 750a8c21a54SThe etnaviv authors 751a8c21a54SThe etnaviv authors static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 752a8c21a54SThe etnaviv authors { 753a8c21a54SThe etnaviv authors u32 i; 754a8c21a54SThe etnaviv authors 755a8c21a54SThe etnaviv authors debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 756a8c21a54SThe etnaviv authors debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 757a8c21a54SThe etnaviv authors 758a8c21a54SThe etnaviv authors for (i = 0; i < 500; i++) { 759a8c21a54SThe etnaviv authors debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 760a8c21a54SThe etnaviv authors debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 761a8c21a54SThe etnaviv authors 762a8c21a54SThe etnaviv authors if (debug->address[0] != debug->address[1]) 763a8c21a54SThe etnaviv authors break; 764a8c21a54SThe etnaviv authors 765a8c21a54SThe etnaviv authors if (debug->state[0] != debug->state[1]) 766a8c21a54SThe etnaviv authors break; 767a8c21a54SThe etnaviv authors } 768a8c21a54SThe etnaviv authors } 769a8c21a54SThe etnaviv authors 770a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 771a8c21a54SThe etnaviv authors { 772a8c21a54SThe etnaviv authors struct dma_debug debug; 773a8c21a54SThe etnaviv authors u32 dma_lo, dma_hi, axi, idle; 774a8c21a54SThe etnaviv authors int ret; 775a8c21a54SThe etnaviv authors 776a8c21a54SThe etnaviv authors seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 777a8c21a54SThe etnaviv authors 778a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 779a8c21a54SThe etnaviv authors if (ret < 0) 780a8c21a54SThe etnaviv authors return ret; 781a8c21a54SThe etnaviv authors 782a8c21a54SThe etnaviv authors dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 783a8c21a54SThe etnaviv authors dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 784a8c21a54SThe etnaviv authors axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 785a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 786a8c21a54SThe etnaviv authors 787a8c21a54SThe etnaviv authors verify_dma(gpu, &debug); 788a8c21a54SThe etnaviv authors 789a8c21a54SThe etnaviv authors seq_puts(m, "\tfeatures\n"); 790a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features0: 0x%08x\n", 791a8c21a54SThe etnaviv authors gpu->identity.minor_features0); 792a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features1: 0x%08x\n", 793a8c21a54SThe etnaviv authors gpu->identity.minor_features1); 794a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features2: 0x%08x\n", 795a8c21a54SThe etnaviv authors gpu->identity.minor_features2); 796a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features3: 0x%08x\n", 797a8c21a54SThe etnaviv authors gpu->identity.minor_features3); 798602eb489SRussell King seq_printf(m, "\t minor_features4: 0x%08x\n", 799602eb489SRussell King gpu->identity.minor_features4); 800602eb489SRussell King seq_printf(m, "\t minor_features5: 0x%08x\n", 801602eb489SRussell King gpu->identity.minor_features5); 802a8c21a54SThe etnaviv authors 803a8c21a54SThe etnaviv authors seq_puts(m, "\tspecs\n"); 804a8c21a54SThe etnaviv authors seq_printf(m, "\t stream_count: %d\n", 805a8c21a54SThe etnaviv authors gpu->identity.stream_count); 806a8c21a54SThe etnaviv authors seq_printf(m, "\t register_max: %d\n", 807a8c21a54SThe etnaviv authors gpu->identity.register_max); 808a8c21a54SThe etnaviv authors seq_printf(m, "\t thread_count: %d\n", 809a8c21a54SThe etnaviv authors gpu->identity.thread_count); 810a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_cache_size: %d\n", 811a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size); 812a8c21a54SThe etnaviv authors seq_printf(m, "\t shader_core_count: %d\n", 813a8c21a54SThe etnaviv authors gpu->identity.shader_core_count); 814a8c21a54SThe etnaviv authors seq_printf(m, "\t pixel_pipes: %d\n", 815a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes); 816a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_output_buffer_size: %d\n", 817a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size); 818a8c21a54SThe etnaviv authors seq_printf(m, "\t buffer_size: %d\n", 819a8c21a54SThe etnaviv authors gpu->identity.buffer_size); 820a8c21a54SThe etnaviv authors seq_printf(m, "\t instruction_count: %d\n", 821a8c21a54SThe etnaviv authors gpu->identity.instruction_count); 822a8c21a54SThe etnaviv authors seq_printf(m, "\t num_constants: %d\n", 823a8c21a54SThe etnaviv authors gpu->identity.num_constants); 824602eb489SRussell King seq_printf(m, "\t varyings_count: %d\n", 825602eb489SRussell King gpu->identity.varyings_count); 826a8c21a54SThe etnaviv authors 827a8c21a54SThe etnaviv authors seq_printf(m, "\taxi: 0x%08x\n", axi); 828a8c21a54SThe etnaviv authors seq_printf(m, "\tidle: 0x%08x\n", idle); 829a8c21a54SThe etnaviv authors idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 830a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 831a8c21a54SThe etnaviv authors seq_puts(m, "\t FE is not idle\n"); 832a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 833a8c21a54SThe etnaviv authors seq_puts(m, "\t DE is not idle\n"); 834a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 835a8c21a54SThe etnaviv authors seq_puts(m, "\t PE is not idle\n"); 836a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 837a8c21a54SThe etnaviv authors seq_puts(m, "\t SH is not idle\n"); 838a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 839a8c21a54SThe etnaviv authors seq_puts(m, "\t PA is not idle\n"); 840a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 841a8c21a54SThe etnaviv authors seq_puts(m, "\t SE is not idle\n"); 842a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 843a8c21a54SThe etnaviv authors seq_puts(m, "\t RA is not idle\n"); 844a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 845a8c21a54SThe etnaviv authors seq_puts(m, "\t TX is not idle\n"); 846a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 847a8c21a54SThe etnaviv authors seq_puts(m, "\t VG is not idle\n"); 848a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 849a8c21a54SThe etnaviv authors seq_puts(m, "\t IM is not idle\n"); 850a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 851a8c21a54SThe etnaviv authors seq_puts(m, "\t FP is not idle\n"); 852a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 853a8c21a54SThe etnaviv authors seq_puts(m, "\t TS is not idle\n"); 854a8c21a54SThe etnaviv authors if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 855a8c21a54SThe etnaviv authors seq_puts(m, "\t AXI low power mode\n"); 856a8c21a54SThe etnaviv authors 857a8c21a54SThe etnaviv authors if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 858a8c21a54SThe etnaviv authors u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 859a8c21a54SThe etnaviv authors u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 860a8c21a54SThe etnaviv authors u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 861a8c21a54SThe etnaviv authors 862a8c21a54SThe etnaviv authors seq_puts(m, "\tMC\n"); 863a8c21a54SThe etnaviv authors seq_printf(m, "\t read0: 0x%08x\n", read0); 864a8c21a54SThe etnaviv authors seq_printf(m, "\t read1: 0x%08x\n", read1); 865a8c21a54SThe etnaviv authors seq_printf(m, "\t write: 0x%08x\n", write); 866a8c21a54SThe etnaviv authors } 867a8c21a54SThe etnaviv authors 868a8c21a54SThe etnaviv authors seq_puts(m, "\tDMA "); 869a8c21a54SThe etnaviv authors 870a8c21a54SThe etnaviv authors if (debug.address[0] == debug.address[1] && 871a8c21a54SThe etnaviv authors debug.state[0] == debug.state[1]) { 872a8c21a54SThe etnaviv authors seq_puts(m, "seems to be stuck\n"); 873a8c21a54SThe etnaviv authors } else if (debug.address[0] == debug.address[1]) { 874c01e0159SMasanari Iida seq_puts(m, "address is constant\n"); 875a8c21a54SThe etnaviv authors } else { 876c01e0159SMasanari Iida seq_puts(m, "is running\n"); 877a8c21a54SThe etnaviv authors } 878a8c21a54SThe etnaviv authors 879a8c21a54SThe etnaviv authors seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 880a8c21a54SThe etnaviv authors seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 881a8c21a54SThe etnaviv authors seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 882a8c21a54SThe etnaviv authors seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 883a8c21a54SThe etnaviv authors seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 884a8c21a54SThe etnaviv authors dma_lo, dma_hi); 885a8c21a54SThe etnaviv authors 886a8c21a54SThe etnaviv authors ret = 0; 887a8c21a54SThe etnaviv authors 888a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 889a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 890a8c21a54SThe etnaviv authors 891a8c21a54SThe etnaviv authors return ret; 892a8c21a54SThe etnaviv authors } 893a8c21a54SThe etnaviv authors #endif 894a8c21a54SThe etnaviv authors 895a8c21a54SThe etnaviv authors /* 896a8c21a54SThe etnaviv authors * Hangcheck detection for locked gpu: 897a8c21a54SThe etnaviv authors */ 898a8c21a54SThe etnaviv authors static void recover_worker(struct work_struct *work) 899a8c21a54SThe etnaviv authors { 900a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 901a8c21a54SThe etnaviv authors recover_work); 902a8c21a54SThe etnaviv authors unsigned long flags; 903a8c21a54SThe etnaviv authors unsigned int i; 904a8c21a54SThe etnaviv authors 905a8c21a54SThe etnaviv authors dev_err(gpu->dev, "hangcheck recover!\n"); 906a8c21a54SThe etnaviv authors 907a8c21a54SThe etnaviv authors if (pm_runtime_get_sync(gpu->dev) < 0) 908a8c21a54SThe etnaviv authors return; 909a8c21a54SThe etnaviv authors 910a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 911a8c21a54SThe etnaviv authors 912a8c21a54SThe etnaviv authors /* Only catch the first event, or when manually re-armed */ 913a8c21a54SThe etnaviv authors if (etnaviv_dump_core) { 914a8c21a54SThe etnaviv authors etnaviv_core_dump(gpu); 915a8c21a54SThe etnaviv authors etnaviv_dump_core = false; 916a8c21a54SThe etnaviv authors } 917a8c21a54SThe etnaviv authors 918a8c21a54SThe etnaviv authors etnaviv_hw_reset(gpu); 919a8c21a54SThe etnaviv authors 920a8c21a54SThe etnaviv authors /* complete all events, the GPU won't do it after the reset */ 921a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 922a8c21a54SThe etnaviv authors for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 923a8c21a54SThe etnaviv authors if (!gpu->event[i].used) 924a8c21a54SThe etnaviv authors continue; 925f54d1867SChris Wilson dma_fence_signal(gpu->event[i].fence); 926a8c21a54SThe etnaviv authors gpu->event[i].fence = NULL; 927a8c21a54SThe etnaviv authors gpu->event[i].used = false; 928a8c21a54SThe etnaviv authors complete(&gpu->event_free); 929a8c21a54SThe etnaviv authors } 930a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 931a8c21a54SThe etnaviv authors gpu->completed_fence = gpu->active_fence; 932a8c21a54SThe etnaviv authors 933a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 9341b94a9b7SLucas Stach gpu->lastctx = NULL; 935f6086311SRussell King gpu->exec_state = -1; 936a8c21a54SThe etnaviv authors 937a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 938a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 939a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 940a8c21a54SThe etnaviv authors 941a8c21a54SThe etnaviv authors /* Retire the buffer objects in a work */ 942a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->retire_work); 943a8c21a54SThe etnaviv authors } 944a8c21a54SThe etnaviv authors 945a8c21a54SThe etnaviv authors static void hangcheck_timer_reset(struct etnaviv_gpu *gpu) 946a8c21a54SThe etnaviv authors { 947a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 948a8c21a54SThe etnaviv authors mod_timer(&gpu->hangcheck_timer, 949a8c21a54SThe etnaviv authors round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES)); 950a8c21a54SThe etnaviv authors } 951a8c21a54SThe etnaviv authors 952a8c21a54SThe etnaviv authors static void hangcheck_handler(unsigned long data) 953a8c21a54SThe etnaviv authors { 954a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data; 955a8c21a54SThe etnaviv authors u32 fence = gpu->completed_fence; 956a8c21a54SThe etnaviv authors bool progress = false; 957a8c21a54SThe etnaviv authors 958a8c21a54SThe etnaviv authors if (fence != gpu->hangcheck_fence) { 959a8c21a54SThe etnaviv authors gpu->hangcheck_fence = fence; 960a8c21a54SThe etnaviv authors progress = true; 961a8c21a54SThe etnaviv authors } 962a8c21a54SThe etnaviv authors 963a8c21a54SThe etnaviv authors if (!progress) { 964a8c21a54SThe etnaviv authors u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 965a8c21a54SThe etnaviv authors int change = dma_addr - gpu->hangcheck_dma_addr; 966a8c21a54SThe etnaviv authors 967a8c21a54SThe etnaviv authors if (change < 0 || change > 16) { 968a8c21a54SThe etnaviv authors gpu->hangcheck_dma_addr = dma_addr; 969a8c21a54SThe etnaviv authors progress = true; 970a8c21a54SThe etnaviv authors } 971a8c21a54SThe etnaviv authors } 972a8c21a54SThe etnaviv authors 973a8c21a54SThe etnaviv authors if (!progress && fence_after(gpu->active_fence, fence)) { 974a8c21a54SThe etnaviv authors dev_err(gpu->dev, "hangcheck detected gpu lockup!\n"); 975a8c21a54SThe etnaviv authors dev_err(gpu->dev, " completed fence: %u\n", fence); 976a8c21a54SThe etnaviv authors dev_err(gpu->dev, " active fence: %u\n", 977a8c21a54SThe etnaviv authors gpu->active_fence); 978a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->recover_work); 979a8c21a54SThe etnaviv authors } 980a8c21a54SThe etnaviv authors 981a8c21a54SThe etnaviv authors /* if still more pending work, reset the hangcheck timer: */ 982a8c21a54SThe etnaviv authors if (fence_after(gpu->active_fence, gpu->hangcheck_fence)) 983a8c21a54SThe etnaviv authors hangcheck_timer_reset(gpu); 984a8c21a54SThe etnaviv authors } 985a8c21a54SThe etnaviv authors 986a8c21a54SThe etnaviv authors static void hangcheck_disable(struct etnaviv_gpu *gpu) 987a8c21a54SThe etnaviv authors { 988a8c21a54SThe etnaviv authors del_timer_sync(&gpu->hangcheck_timer); 989a8c21a54SThe etnaviv authors cancel_work_sync(&gpu->recover_work); 990a8c21a54SThe etnaviv authors } 991a8c21a54SThe etnaviv authors 992a8c21a54SThe etnaviv authors /* fence object management */ 993a8c21a54SThe etnaviv authors struct etnaviv_fence { 994a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 995f54d1867SChris Wilson struct dma_fence base; 996a8c21a54SThe etnaviv authors }; 997a8c21a54SThe etnaviv authors 998f54d1867SChris Wilson static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 999a8c21a54SThe etnaviv authors { 1000a8c21a54SThe etnaviv authors return container_of(fence, struct etnaviv_fence, base); 1001a8c21a54SThe etnaviv authors } 1002a8c21a54SThe etnaviv authors 1003f54d1867SChris Wilson static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1004a8c21a54SThe etnaviv authors { 1005a8c21a54SThe etnaviv authors return "etnaviv"; 1006a8c21a54SThe etnaviv authors } 1007a8c21a54SThe etnaviv authors 1008f54d1867SChris Wilson static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1009a8c21a54SThe etnaviv authors { 1010a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1011a8c21a54SThe etnaviv authors 1012a8c21a54SThe etnaviv authors return dev_name(f->gpu->dev); 1013a8c21a54SThe etnaviv authors } 1014a8c21a54SThe etnaviv authors 1015f54d1867SChris Wilson static bool etnaviv_fence_enable_signaling(struct dma_fence *fence) 1016a8c21a54SThe etnaviv authors { 1017a8c21a54SThe etnaviv authors return true; 1018a8c21a54SThe etnaviv authors } 1019a8c21a54SThe etnaviv authors 1020f54d1867SChris Wilson static bool etnaviv_fence_signaled(struct dma_fence *fence) 1021a8c21a54SThe etnaviv authors { 1022a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1023a8c21a54SThe etnaviv authors 1024a8c21a54SThe etnaviv authors return fence_completed(f->gpu, f->base.seqno); 1025a8c21a54SThe etnaviv authors } 1026a8c21a54SThe etnaviv authors 1027f54d1867SChris Wilson static void etnaviv_fence_release(struct dma_fence *fence) 1028a8c21a54SThe etnaviv authors { 1029a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1030a8c21a54SThe etnaviv authors 1031a8c21a54SThe etnaviv authors kfree_rcu(f, base.rcu); 1032a8c21a54SThe etnaviv authors } 1033a8c21a54SThe etnaviv authors 1034f54d1867SChris Wilson static const struct dma_fence_ops etnaviv_fence_ops = { 1035a8c21a54SThe etnaviv authors .get_driver_name = etnaviv_fence_get_driver_name, 1036a8c21a54SThe etnaviv authors .get_timeline_name = etnaviv_fence_get_timeline_name, 1037a8c21a54SThe etnaviv authors .enable_signaling = etnaviv_fence_enable_signaling, 1038a8c21a54SThe etnaviv authors .signaled = etnaviv_fence_signaled, 1039f54d1867SChris Wilson .wait = dma_fence_default_wait, 1040a8c21a54SThe etnaviv authors .release = etnaviv_fence_release, 1041a8c21a54SThe etnaviv authors }; 1042a8c21a54SThe etnaviv authors 1043f54d1867SChris Wilson static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1044a8c21a54SThe etnaviv authors { 1045a8c21a54SThe etnaviv authors struct etnaviv_fence *f; 1046a8c21a54SThe etnaviv authors 1047a8c21a54SThe etnaviv authors f = kzalloc(sizeof(*f), GFP_KERNEL); 1048a8c21a54SThe etnaviv authors if (!f) 1049a8c21a54SThe etnaviv authors return NULL; 1050a8c21a54SThe etnaviv authors 1051a8c21a54SThe etnaviv authors f->gpu = gpu; 1052a8c21a54SThe etnaviv authors 1053f54d1867SChris Wilson dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1054a8c21a54SThe etnaviv authors gpu->fence_context, ++gpu->next_fence); 1055a8c21a54SThe etnaviv authors 1056a8c21a54SThe etnaviv authors return &f->base; 1057a8c21a54SThe etnaviv authors } 1058a8c21a54SThe etnaviv authors 1059a8c21a54SThe etnaviv authors int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 1060a8c21a54SThe etnaviv authors unsigned int context, bool exclusive) 1061a8c21a54SThe etnaviv authors { 1062a8c21a54SThe etnaviv authors struct reservation_object *robj = etnaviv_obj->resv; 1063a8c21a54SThe etnaviv authors struct reservation_object_list *fobj; 1064f54d1867SChris Wilson struct dma_fence *fence; 1065a8c21a54SThe etnaviv authors int i, ret; 1066a8c21a54SThe etnaviv authors 1067a8c21a54SThe etnaviv authors if (!exclusive) { 1068a8c21a54SThe etnaviv authors ret = reservation_object_reserve_shared(robj); 1069a8c21a54SThe etnaviv authors if (ret) 1070a8c21a54SThe etnaviv authors return ret; 1071a8c21a54SThe etnaviv authors } 1072a8c21a54SThe etnaviv authors 1073a8c21a54SThe etnaviv authors /* 1074a8c21a54SThe etnaviv authors * If we have any shared fences, then the exclusive fence 1075a8c21a54SThe etnaviv authors * should be ignored as it will already have been signalled. 1076a8c21a54SThe etnaviv authors */ 1077a8c21a54SThe etnaviv authors fobj = reservation_object_get_list(robj); 1078a8c21a54SThe etnaviv authors if (!fobj || fobj->shared_count == 0) { 1079a8c21a54SThe etnaviv authors /* Wait on any existing exclusive fence which isn't our own */ 1080a8c21a54SThe etnaviv authors fence = reservation_object_get_excl(robj); 1081a8c21a54SThe etnaviv authors if (fence && fence->context != context) { 1082f54d1867SChris Wilson ret = dma_fence_wait(fence, true); 1083a8c21a54SThe etnaviv authors if (ret) 1084a8c21a54SThe etnaviv authors return ret; 1085a8c21a54SThe etnaviv authors } 1086a8c21a54SThe etnaviv authors } 1087a8c21a54SThe etnaviv authors 1088a8c21a54SThe etnaviv authors if (!exclusive || !fobj) 1089a8c21a54SThe etnaviv authors return 0; 1090a8c21a54SThe etnaviv authors 1091a8c21a54SThe etnaviv authors for (i = 0; i < fobj->shared_count; i++) { 1092a8c21a54SThe etnaviv authors fence = rcu_dereference_protected(fobj->shared[i], 1093a8c21a54SThe etnaviv authors reservation_object_held(robj)); 1094a8c21a54SThe etnaviv authors if (fence->context != context) { 1095f54d1867SChris Wilson ret = dma_fence_wait(fence, true); 1096a8c21a54SThe etnaviv authors if (ret) 1097a8c21a54SThe etnaviv authors return ret; 1098a8c21a54SThe etnaviv authors } 1099a8c21a54SThe etnaviv authors } 1100a8c21a54SThe etnaviv authors 1101a8c21a54SThe etnaviv authors return 0; 1102a8c21a54SThe etnaviv authors } 1103a8c21a54SThe etnaviv authors 1104a8c21a54SThe etnaviv authors /* 1105a8c21a54SThe etnaviv authors * event management: 1106a8c21a54SThe etnaviv authors */ 1107a8c21a54SThe etnaviv authors 1108a8c21a54SThe etnaviv authors static unsigned int event_alloc(struct etnaviv_gpu *gpu) 1109a8c21a54SThe etnaviv authors { 1110a8c21a54SThe etnaviv authors unsigned long ret, flags; 1111a8c21a54SThe etnaviv authors unsigned int i, event = ~0U; 1112a8c21a54SThe etnaviv authors 1113a8c21a54SThe etnaviv authors ret = wait_for_completion_timeout(&gpu->event_free, 1114a8c21a54SThe etnaviv authors msecs_to_jiffies(10 * 10000)); 1115a8c21a54SThe etnaviv authors if (!ret) 1116a8c21a54SThe etnaviv authors dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1117a8c21a54SThe etnaviv authors 1118a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1119a8c21a54SThe etnaviv authors 1120a8c21a54SThe etnaviv authors /* find first free event */ 1121a8c21a54SThe etnaviv authors for (i = 0; i < ARRAY_SIZE(gpu->event); i++) { 1122a8c21a54SThe etnaviv authors if (gpu->event[i].used == false) { 1123a8c21a54SThe etnaviv authors gpu->event[i].used = true; 1124a8c21a54SThe etnaviv authors event = i; 1125a8c21a54SThe etnaviv authors break; 1126a8c21a54SThe etnaviv authors } 1127a8c21a54SThe etnaviv authors } 1128a8c21a54SThe etnaviv authors 1129a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1130a8c21a54SThe etnaviv authors 1131a8c21a54SThe etnaviv authors return event; 1132a8c21a54SThe etnaviv authors } 1133a8c21a54SThe etnaviv authors 1134a8c21a54SThe etnaviv authors static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1135a8c21a54SThe etnaviv authors { 1136a8c21a54SThe etnaviv authors unsigned long flags; 1137a8c21a54SThe etnaviv authors 1138a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1139a8c21a54SThe etnaviv authors 1140a8c21a54SThe etnaviv authors if (gpu->event[event].used == false) { 1141a8c21a54SThe etnaviv authors dev_warn(gpu->dev, "event %u is already marked as free", 1142a8c21a54SThe etnaviv authors event); 1143a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1144a8c21a54SThe etnaviv authors } else { 1145a8c21a54SThe etnaviv authors gpu->event[event].used = false; 1146a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1147a8c21a54SThe etnaviv authors 1148a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1149a8c21a54SThe etnaviv authors } 1150a8c21a54SThe etnaviv authors } 1151a8c21a54SThe etnaviv authors 1152a8c21a54SThe etnaviv authors /* 1153a8c21a54SThe etnaviv authors * Cmdstream submission/retirement: 1154a8c21a54SThe etnaviv authors */ 1155a8c21a54SThe etnaviv authors 1156a8c21a54SThe etnaviv authors static void retire_worker(struct work_struct *work) 1157a8c21a54SThe etnaviv authors { 1158a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1159a8c21a54SThe etnaviv authors retire_work); 1160a8c21a54SThe etnaviv authors u32 fence = gpu->completed_fence; 1161a8c21a54SThe etnaviv authors struct etnaviv_cmdbuf *cmdbuf, *tmp; 1162a8c21a54SThe etnaviv authors unsigned int i; 1163a8c21a54SThe etnaviv authors 1164a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 1165a8c21a54SThe etnaviv authors list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) { 1166f54d1867SChris Wilson if (!dma_fence_is_signaled(cmdbuf->fence)) 1167a8c21a54SThe etnaviv authors break; 1168a8c21a54SThe etnaviv authors 1169a8c21a54SThe etnaviv authors list_del(&cmdbuf->node); 1170f54d1867SChris Wilson dma_fence_put(cmdbuf->fence); 1171a8c21a54SThe etnaviv authors 1172a8c21a54SThe etnaviv authors for (i = 0; i < cmdbuf->nr_bos; i++) { 1173b6325f40SRussell King struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i]; 1174b6325f40SRussell King struct etnaviv_gem_object *etnaviv_obj = mapping->object; 1175a8c21a54SThe etnaviv authors 1176a8c21a54SThe etnaviv authors atomic_dec(&etnaviv_obj->gpu_active); 1177a8c21a54SThe etnaviv authors /* drop the refcount taken in etnaviv_gpu_submit */ 1178b6325f40SRussell King etnaviv_gem_mapping_unreference(mapping); 1179a8c21a54SThe etnaviv authors } 1180a8c21a54SThe etnaviv authors 1181ea1f5729SLucas Stach etnaviv_cmdbuf_free(cmdbuf); 1182d9fd0c7dSLucas Stach /* 1183d9fd0c7dSLucas Stach * We need to balance the runtime PM count caused by 1184d9fd0c7dSLucas Stach * each submission. Upon submission, we increment 1185d9fd0c7dSLucas Stach * the runtime PM counter, and allocate one event. 1186d9fd0c7dSLucas Stach * So here, we put the runtime PM count for each 1187d9fd0c7dSLucas Stach * completed event. 1188d9fd0c7dSLucas Stach */ 1189d9fd0c7dSLucas Stach pm_runtime_put_autosuspend(gpu->dev); 1190a8c21a54SThe etnaviv authors } 1191a8c21a54SThe etnaviv authors 1192a8c21a54SThe etnaviv authors gpu->retired_fence = fence; 1193a8c21a54SThe etnaviv authors 1194a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1195a8c21a54SThe etnaviv authors 1196a8c21a54SThe etnaviv authors wake_up_all(&gpu->fence_event); 1197a8c21a54SThe etnaviv authors } 1198a8c21a54SThe etnaviv authors 1199a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1200a8c21a54SThe etnaviv authors u32 fence, struct timespec *timeout) 1201a8c21a54SThe etnaviv authors { 1202a8c21a54SThe etnaviv authors int ret; 1203a8c21a54SThe etnaviv authors 1204a8c21a54SThe etnaviv authors if (fence_after(fence, gpu->next_fence)) { 1205a8c21a54SThe etnaviv authors DRM_ERROR("waiting on invalid fence: %u (of %u)\n", 1206a8c21a54SThe etnaviv authors fence, gpu->next_fence); 1207a8c21a54SThe etnaviv authors return -EINVAL; 1208a8c21a54SThe etnaviv authors } 1209a8c21a54SThe etnaviv authors 1210a8c21a54SThe etnaviv authors if (!timeout) { 1211a8c21a54SThe etnaviv authors /* No timeout was requested: just test for completion */ 1212a8c21a54SThe etnaviv authors ret = fence_completed(gpu, fence) ? 0 : -EBUSY; 1213a8c21a54SThe etnaviv authors } else { 1214a8c21a54SThe etnaviv authors unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1215a8c21a54SThe etnaviv authors 1216a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1217a8c21a54SThe etnaviv authors fence_completed(gpu, fence), 1218a8c21a54SThe etnaviv authors remaining); 1219a8c21a54SThe etnaviv authors if (ret == 0) { 1220a8c21a54SThe etnaviv authors DBG("timeout waiting for fence: %u (retired: %u completed: %u)", 1221a8c21a54SThe etnaviv authors fence, gpu->retired_fence, 1222a8c21a54SThe etnaviv authors gpu->completed_fence); 1223a8c21a54SThe etnaviv authors ret = -ETIMEDOUT; 1224a8c21a54SThe etnaviv authors } else if (ret != -ERESTARTSYS) { 1225a8c21a54SThe etnaviv authors ret = 0; 1226a8c21a54SThe etnaviv authors } 1227a8c21a54SThe etnaviv authors } 1228a8c21a54SThe etnaviv authors 1229a8c21a54SThe etnaviv authors return ret; 1230a8c21a54SThe etnaviv authors } 1231a8c21a54SThe etnaviv authors 1232a8c21a54SThe etnaviv authors /* 1233a8c21a54SThe etnaviv authors * Wait for an object to become inactive. This, on it's own, is not race 1234a8c21a54SThe etnaviv authors * free: the object is moved by the retire worker off the active list, and 1235a8c21a54SThe etnaviv authors * then the iova is put. Moreover, the object could be re-submitted just 1236a8c21a54SThe etnaviv authors * after we notice that it's become inactive. 1237a8c21a54SThe etnaviv authors * 1238a8c21a54SThe etnaviv authors * Although the retirement happens under the gpu lock, we don't want to hold 1239a8c21a54SThe etnaviv authors * that lock in this function while waiting. 1240a8c21a54SThe etnaviv authors */ 1241a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1242a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1243a8c21a54SThe etnaviv authors { 1244a8c21a54SThe etnaviv authors unsigned long remaining; 1245a8c21a54SThe etnaviv authors long ret; 1246a8c21a54SThe etnaviv authors 1247a8c21a54SThe etnaviv authors if (!timeout) 1248a8c21a54SThe etnaviv authors return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1249a8c21a54SThe etnaviv authors 1250a8c21a54SThe etnaviv authors remaining = etnaviv_timeout_to_jiffies(timeout); 1251a8c21a54SThe etnaviv authors 1252a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1253a8c21a54SThe etnaviv authors !is_active(etnaviv_obj), 1254a8c21a54SThe etnaviv authors remaining); 1255a8c21a54SThe etnaviv authors if (ret > 0) { 1256a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = gpu->drm->dev_private; 1257a8c21a54SThe etnaviv authors 1258a8c21a54SThe etnaviv authors /* Synchronise with the retire worker */ 1259a8c21a54SThe etnaviv authors flush_workqueue(priv->wq); 1260a8c21a54SThe etnaviv authors return 0; 1261a8c21a54SThe etnaviv authors } else if (ret == -ERESTARTSYS) { 1262a8c21a54SThe etnaviv authors return -ERESTARTSYS; 1263a8c21a54SThe etnaviv authors } else { 1264a8c21a54SThe etnaviv authors return -ETIMEDOUT; 1265a8c21a54SThe etnaviv authors } 1266a8c21a54SThe etnaviv authors } 1267a8c21a54SThe etnaviv authors 1268a8c21a54SThe etnaviv authors int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu) 1269a8c21a54SThe etnaviv authors { 1270a8c21a54SThe etnaviv authors return pm_runtime_get_sync(gpu->dev); 1271a8c21a54SThe etnaviv authors } 1272a8c21a54SThe etnaviv authors 1273a8c21a54SThe etnaviv authors void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) 1274a8c21a54SThe etnaviv authors { 1275a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1276a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1277a8c21a54SThe etnaviv authors } 1278a8c21a54SThe etnaviv authors 1279a8c21a54SThe etnaviv authors /* add bo's to gpu's ring, and kick gpu: */ 1280a8c21a54SThe etnaviv authors int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 1281a8c21a54SThe etnaviv authors struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) 1282a8c21a54SThe etnaviv authors { 1283f54d1867SChris Wilson struct dma_fence *fence; 1284a8c21a54SThe etnaviv authors unsigned int event, i; 1285a8c21a54SThe etnaviv authors int ret; 1286a8c21a54SThe etnaviv authors 1287a8c21a54SThe etnaviv authors ret = etnaviv_gpu_pm_get_sync(gpu); 1288a8c21a54SThe etnaviv authors if (ret < 0) 1289a8c21a54SThe etnaviv authors return ret; 1290a8c21a54SThe etnaviv authors 1291a8c21a54SThe etnaviv authors /* 1292a8c21a54SThe etnaviv authors * TODO 1293a8c21a54SThe etnaviv authors * 1294a8c21a54SThe etnaviv authors * - flush 1295a8c21a54SThe etnaviv authors * - data endian 1296a8c21a54SThe etnaviv authors * - prefetch 1297a8c21a54SThe etnaviv authors * 1298a8c21a54SThe etnaviv authors */ 1299a8c21a54SThe etnaviv authors 1300a8c21a54SThe etnaviv authors event = event_alloc(gpu); 1301a8c21a54SThe etnaviv authors if (unlikely(event == ~0U)) { 1302a8c21a54SThe etnaviv authors DRM_ERROR("no free event\n"); 1303a8c21a54SThe etnaviv authors ret = -EBUSY; 1304d9853490SLucas Stach goto out_pm_put; 1305a8c21a54SThe etnaviv authors } 1306a8c21a54SThe etnaviv authors 1307a8c21a54SThe etnaviv authors fence = etnaviv_gpu_fence_alloc(gpu); 1308a8c21a54SThe etnaviv authors if (!fence) { 1309a8c21a54SThe etnaviv authors event_free(gpu, event); 1310a8c21a54SThe etnaviv authors ret = -ENOMEM; 1311d9853490SLucas Stach goto out_pm_put; 1312a8c21a54SThe etnaviv authors } 1313a8c21a54SThe etnaviv authors 1314d9853490SLucas Stach mutex_lock(&gpu->lock); 1315d9853490SLucas Stach 1316a8c21a54SThe etnaviv authors gpu->event[event].fence = fence; 1317a8c21a54SThe etnaviv authors submit->fence = fence->seqno; 1318a8c21a54SThe etnaviv authors gpu->active_fence = submit->fence; 1319a8c21a54SThe etnaviv authors 1320a8c21a54SThe etnaviv authors if (gpu->lastctx != cmdbuf->ctx) { 1321a8c21a54SThe etnaviv authors gpu->mmu->need_flush = true; 1322a8c21a54SThe etnaviv authors gpu->switch_context = true; 1323a8c21a54SThe etnaviv authors gpu->lastctx = cmdbuf->ctx; 1324a8c21a54SThe etnaviv authors } 1325a8c21a54SThe etnaviv authors 1326a8c21a54SThe etnaviv authors etnaviv_buffer_queue(gpu, event, cmdbuf); 1327a8c21a54SThe etnaviv authors 1328a8c21a54SThe etnaviv authors cmdbuf->fence = fence; 1329a8c21a54SThe etnaviv authors list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); 1330a8c21a54SThe etnaviv authors 1331a8c21a54SThe etnaviv authors /* We're committed to adding this command buffer, hold a PM reference */ 1332a8c21a54SThe etnaviv authors pm_runtime_get_noresume(gpu->dev); 1333a8c21a54SThe etnaviv authors 1334a8c21a54SThe etnaviv authors for (i = 0; i < submit->nr_bos; i++) { 1335a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; 1336a8c21a54SThe etnaviv authors 1337b6325f40SRussell King /* Each cmdbuf takes a refcount on the mapping */ 1338b6325f40SRussell King etnaviv_gem_mapping_reference(submit->bos[i].mapping); 1339b6325f40SRussell King cmdbuf->bo_map[i] = submit->bos[i].mapping; 1340a8c21a54SThe etnaviv authors atomic_inc(&etnaviv_obj->gpu_active); 1341a8c21a54SThe etnaviv authors 1342a8c21a54SThe etnaviv authors if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE) 1343a8c21a54SThe etnaviv authors reservation_object_add_excl_fence(etnaviv_obj->resv, 1344a8c21a54SThe etnaviv authors fence); 1345a8c21a54SThe etnaviv authors else 1346a8c21a54SThe etnaviv authors reservation_object_add_shared_fence(etnaviv_obj->resv, 1347a8c21a54SThe etnaviv authors fence); 1348a8c21a54SThe etnaviv authors } 1349a8c21a54SThe etnaviv authors cmdbuf->nr_bos = submit->nr_bos; 1350a8c21a54SThe etnaviv authors hangcheck_timer_reset(gpu); 1351a8c21a54SThe etnaviv authors ret = 0; 1352a8c21a54SThe etnaviv authors 1353a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1354a8c21a54SThe etnaviv authors 1355d9853490SLucas Stach out_pm_put: 1356a8c21a54SThe etnaviv authors etnaviv_gpu_pm_put(gpu); 1357a8c21a54SThe etnaviv authors 1358a8c21a54SThe etnaviv authors return ret; 1359a8c21a54SThe etnaviv authors } 1360a8c21a54SThe etnaviv authors 1361a8c21a54SThe etnaviv authors /* 1362a8c21a54SThe etnaviv authors * Init/Cleanup: 1363a8c21a54SThe etnaviv authors */ 1364a8c21a54SThe etnaviv authors static irqreturn_t irq_handler(int irq, void *data) 1365a8c21a54SThe etnaviv authors { 1366a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = data; 1367a8c21a54SThe etnaviv authors irqreturn_t ret = IRQ_NONE; 1368a8c21a54SThe etnaviv authors 1369a8c21a54SThe etnaviv authors u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1370a8c21a54SThe etnaviv authors 1371a8c21a54SThe etnaviv authors if (intr != 0) { 1372a8c21a54SThe etnaviv authors int event; 1373a8c21a54SThe etnaviv authors 1374a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1375a8c21a54SThe etnaviv authors 1376a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1377a8c21a54SThe etnaviv authors 1378a8c21a54SThe etnaviv authors if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1379a8c21a54SThe etnaviv authors dev_err(gpu->dev, "AXI bus error\n"); 1380a8c21a54SThe etnaviv authors intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1381a8c21a54SThe etnaviv authors } 1382a8c21a54SThe etnaviv authors 1383128a9b1dSLucas Stach if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1384128a9b1dSLucas Stach int i; 1385128a9b1dSLucas Stach 1386128a9b1dSLucas Stach dev_err_ratelimited(gpu->dev, 1387128a9b1dSLucas Stach "MMU fault status 0x%08x\n", 1388128a9b1dSLucas Stach gpu_read(gpu, VIVS_MMUv2_STATUS)); 1389128a9b1dSLucas Stach for (i = 0; i < 4; i++) { 1390128a9b1dSLucas Stach dev_err_ratelimited(gpu->dev, 1391128a9b1dSLucas Stach "MMU %d fault addr 0x%08x\n", 1392128a9b1dSLucas Stach i, gpu_read(gpu, 1393128a9b1dSLucas Stach VIVS_MMUv2_EXCEPTION_ADDR(i))); 1394128a9b1dSLucas Stach } 1395128a9b1dSLucas Stach intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1396128a9b1dSLucas Stach } 1397128a9b1dSLucas Stach 1398a8c21a54SThe etnaviv authors while ((event = ffs(intr)) != 0) { 1399f54d1867SChris Wilson struct dma_fence *fence; 1400a8c21a54SThe etnaviv authors 1401a8c21a54SThe etnaviv authors event -= 1; 1402a8c21a54SThe etnaviv authors 1403a8c21a54SThe etnaviv authors intr &= ~(1 << event); 1404a8c21a54SThe etnaviv authors 1405a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "event %u\n", event); 1406a8c21a54SThe etnaviv authors 1407a8c21a54SThe etnaviv authors fence = gpu->event[event].fence; 1408a8c21a54SThe etnaviv authors gpu->event[event].fence = NULL; 1409f54d1867SChris Wilson dma_fence_signal(fence); 1410a8c21a54SThe etnaviv authors 1411a8c21a54SThe etnaviv authors /* 1412a8c21a54SThe etnaviv authors * Events can be processed out of order. Eg, 1413a8c21a54SThe etnaviv authors * - allocate and queue event 0 1414a8c21a54SThe etnaviv authors * - allocate event 1 1415a8c21a54SThe etnaviv authors * - event 0 completes, we process it 1416a8c21a54SThe etnaviv authors * - allocate and queue event 0 1417a8c21a54SThe etnaviv authors * - event 1 and event 0 complete 1418a8c21a54SThe etnaviv authors * we can end up processing event 0 first, then 1. 1419a8c21a54SThe etnaviv authors */ 1420a8c21a54SThe etnaviv authors if (fence_after(fence->seqno, gpu->completed_fence)) 1421a8c21a54SThe etnaviv authors gpu->completed_fence = fence->seqno; 1422a8c21a54SThe etnaviv authors 1423a8c21a54SThe etnaviv authors event_free(gpu, event); 1424a8c21a54SThe etnaviv authors } 1425a8c21a54SThe etnaviv authors 1426a8c21a54SThe etnaviv authors /* Retire the buffer objects in a work */ 1427a8c21a54SThe etnaviv authors etnaviv_queue_work(gpu->drm, &gpu->retire_work); 1428a8c21a54SThe etnaviv authors 1429a8c21a54SThe etnaviv authors ret = IRQ_HANDLED; 1430a8c21a54SThe etnaviv authors } 1431a8c21a54SThe etnaviv authors 1432a8c21a54SThe etnaviv authors return ret; 1433a8c21a54SThe etnaviv authors } 1434a8c21a54SThe etnaviv authors 1435a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1436a8c21a54SThe etnaviv authors { 1437a8c21a54SThe etnaviv authors int ret; 1438a8c21a54SThe etnaviv authors 14399c7310c0SLucas Stach if (gpu->clk_bus) { 14409c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_bus); 1441a8c21a54SThe etnaviv authors if (ret) 1442a8c21a54SThe etnaviv authors return ret; 1443a8c21a54SThe etnaviv authors } 1444a8c21a54SThe etnaviv authors 14459c7310c0SLucas Stach if (gpu->clk_core) { 14469c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_core); 14479c7310c0SLucas Stach if (ret) 14489c7310c0SLucas Stach goto disable_clk_bus; 14499c7310c0SLucas Stach } 14509c7310c0SLucas Stach 14519c7310c0SLucas Stach if (gpu->clk_shader) { 14529c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_shader); 14539c7310c0SLucas Stach if (ret) 14549c7310c0SLucas Stach goto disable_clk_core; 14559c7310c0SLucas Stach } 14569c7310c0SLucas Stach 1457a8c21a54SThe etnaviv authors return 0; 14589c7310c0SLucas Stach 14599c7310c0SLucas Stach disable_clk_core: 14609c7310c0SLucas Stach if (gpu->clk_core) 14619c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 14629c7310c0SLucas Stach disable_clk_bus: 14639c7310c0SLucas Stach if (gpu->clk_bus) 14649c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 14659c7310c0SLucas Stach 14669c7310c0SLucas Stach return ret; 1467a8c21a54SThe etnaviv authors } 1468a8c21a54SThe etnaviv authors 1469a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1470a8c21a54SThe etnaviv authors { 14719c7310c0SLucas Stach if (gpu->clk_shader) 14729c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_shader); 14739c7310c0SLucas Stach if (gpu->clk_core) 14749c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 14759c7310c0SLucas Stach if (gpu->clk_bus) 14769c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 1477a8c21a54SThe etnaviv authors 1478a8c21a54SThe etnaviv authors return 0; 1479a8c21a54SThe etnaviv authors } 1480a8c21a54SThe etnaviv authors 1481b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1482b88163e3SLucas Stach { 1483b88163e3SLucas Stach unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1484b88163e3SLucas Stach 1485b88163e3SLucas Stach do { 1486b88163e3SLucas Stach u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1487b88163e3SLucas Stach 1488b88163e3SLucas Stach if ((idle & gpu->idle_mask) == gpu->idle_mask) 1489b88163e3SLucas Stach return 0; 1490b88163e3SLucas Stach 1491b88163e3SLucas Stach if (time_is_before_jiffies(timeout)) { 1492b88163e3SLucas Stach dev_warn(gpu->dev, 1493b88163e3SLucas Stach "timed out waiting for idle: idle=0x%x\n", 1494b88163e3SLucas Stach idle); 1495b88163e3SLucas Stach return -ETIMEDOUT; 1496b88163e3SLucas Stach } 1497b88163e3SLucas Stach 1498b88163e3SLucas Stach udelay(5); 1499b88163e3SLucas Stach } while (1); 1500b88163e3SLucas Stach } 1501b88163e3SLucas Stach 1502a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1503a8c21a54SThe etnaviv authors { 1504a8c21a54SThe etnaviv authors if (gpu->buffer) { 1505a8c21a54SThe etnaviv authors /* Replace the last WAIT with END */ 1506a8c21a54SThe etnaviv authors etnaviv_buffer_end(gpu); 1507a8c21a54SThe etnaviv authors 1508a8c21a54SThe etnaviv authors /* 1509a8c21a54SThe etnaviv authors * We know that only the FE is busy here, this should 1510a8c21a54SThe etnaviv authors * happen quickly (as the WAIT is only 200 cycles). If 1511a8c21a54SThe etnaviv authors * we fail, just warn and continue. 1512a8c21a54SThe etnaviv authors */ 1513b88163e3SLucas Stach etnaviv_gpu_wait_idle(gpu, 100); 1514a8c21a54SThe etnaviv authors } 1515a8c21a54SThe etnaviv authors 1516a8c21a54SThe etnaviv authors return etnaviv_gpu_clk_disable(gpu); 1517a8c21a54SThe etnaviv authors } 1518a8c21a54SThe etnaviv authors 1519a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1520a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1521a8c21a54SThe etnaviv authors { 1522a8c21a54SThe etnaviv authors u32 clock; 1523a8c21a54SThe etnaviv authors int ret; 1524a8c21a54SThe etnaviv authors 1525a8c21a54SThe etnaviv authors ret = mutex_lock_killable(&gpu->lock); 1526a8c21a54SThe etnaviv authors if (ret) 1527a8c21a54SThe etnaviv authors return ret; 1528a8c21a54SThe etnaviv authors 1529a8c21a54SThe etnaviv authors clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | 1530a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40); 1531a8c21a54SThe etnaviv authors 1532a8c21a54SThe etnaviv authors etnaviv_gpu_load_clock(gpu, clock); 1533a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1534a8c21a54SThe etnaviv authors 1535a8c21a54SThe etnaviv authors gpu->switch_context = true; 1536f6086311SRussell King gpu->exec_state = -1; 1537a8c21a54SThe etnaviv authors 1538a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1539a8c21a54SThe etnaviv authors 1540a8c21a54SThe etnaviv authors return 0; 1541a8c21a54SThe etnaviv authors } 1542a8c21a54SThe etnaviv authors #endif 1543a8c21a54SThe etnaviv authors 1544a8c21a54SThe etnaviv authors static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1545a8c21a54SThe etnaviv authors void *data) 1546a8c21a54SThe etnaviv authors { 1547a8c21a54SThe etnaviv authors struct drm_device *drm = data; 1548a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = drm->dev_private; 1549a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1550a8c21a54SThe etnaviv authors int ret; 1551a8c21a54SThe etnaviv authors 1552a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1553a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 1554a8c21a54SThe etnaviv authors #else 1555a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1556a8c21a54SThe etnaviv authors #endif 1557a8c21a54SThe etnaviv authors if (ret < 0) 1558a8c21a54SThe etnaviv authors return ret; 1559a8c21a54SThe etnaviv authors 1560a8c21a54SThe etnaviv authors gpu->drm = drm; 1561f54d1867SChris Wilson gpu->fence_context = dma_fence_context_alloc(1); 1562a8c21a54SThe etnaviv authors spin_lock_init(&gpu->fence_spinlock); 1563a8c21a54SThe etnaviv authors 1564a8c21a54SThe etnaviv authors INIT_LIST_HEAD(&gpu->active_cmd_list); 1565a8c21a54SThe etnaviv authors INIT_WORK(&gpu->retire_work, retire_worker); 1566a8c21a54SThe etnaviv authors INIT_WORK(&gpu->recover_work, recover_worker); 1567a8c21a54SThe etnaviv authors init_waitqueue_head(&gpu->fence_event); 1568a8c21a54SThe etnaviv authors 1569946dd8d5SLucas Stach setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler, 1570a8c21a54SThe etnaviv authors (unsigned long)gpu); 1571a8c21a54SThe etnaviv authors 1572a8c21a54SThe etnaviv authors priv->gpu[priv->num_gpus++] = gpu; 1573a8c21a54SThe etnaviv authors 1574a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1575a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1576a8c21a54SThe etnaviv authors 1577a8c21a54SThe etnaviv authors return 0; 1578a8c21a54SThe etnaviv authors } 1579a8c21a54SThe etnaviv authors 1580a8c21a54SThe etnaviv authors static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1581a8c21a54SThe etnaviv authors void *data) 1582a8c21a54SThe etnaviv authors { 1583a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1584a8c21a54SThe etnaviv authors 1585a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 1586a8c21a54SThe etnaviv authors 1587a8c21a54SThe etnaviv authors hangcheck_disable(gpu); 1588a8c21a54SThe etnaviv authors 1589a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1590a8c21a54SThe etnaviv authors pm_runtime_get_sync(gpu->dev); 1591a8c21a54SThe etnaviv authors pm_runtime_put_sync_suspend(gpu->dev); 1592a8c21a54SThe etnaviv authors #else 1593a8c21a54SThe etnaviv authors etnaviv_gpu_hw_suspend(gpu); 1594a8c21a54SThe etnaviv authors #endif 1595a8c21a54SThe etnaviv authors 1596a8c21a54SThe etnaviv authors if (gpu->buffer) { 1597ea1f5729SLucas Stach etnaviv_cmdbuf_free(gpu->buffer); 1598a8c21a54SThe etnaviv authors gpu->buffer = NULL; 1599a8c21a54SThe etnaviv authors } 1600a8c21a54SThe etnaviv authors 1601a8c21a54SThe etnaviv authors if (gpu->mmu) { 1602a8c21a54SThe etnaviv authors etnaviv_iommu_destroy(gpu->mmu); 1603a8c21a54SThe etnaviv authors gpu->mmu = NULL; 1604a8c21a54SThe etnaviv authors } 1605a8c21a54SThe etnaviv authors 1606a8c21a54SThe etnaviv authors gpu->drm = NULL; 1607a8c21a54SThe etnaviv authors } 1608a8c21a54SThe etnaviv authors 1609a8c21a54SThe etnaviv authors static const struct component_ops gpu_ops = { 1610a8c21a54SThe etnaviv authors .bind = etnaviv_gpu_bind, 1611a8c21a54SThe etnaviv authors .unbind = etnaviv_gpu_unbind, 1612a8c21a54SThe etnaviv authors }; 1613a8c21a54SThe etnaviv authors 1614a8c21a54SThe etnaviv authors static const struct of_device_id etnaviv_gpu_match[] = { 1615a8c21a54SThe etnaviv authors { 1616a8c21a54SThe etnaviv authors .compatible = "vivante,gc" 1617a8c21a54SThe etnaviv authors }, 1618a8c21a54SThe etnaviv authors { /* sentinel */ } 1619a8c21a54SThe etnaviv authors }; 1620a8c21a54SThe etnaviv authors 1621a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1622a8c21a54SThe etnaviv authors { 1623a8c21a54SThe etnaviv authors struct device *dev = &pdev->dev; 1624a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1625dc227890SFabio Estevam int err; 1626a8c21a54SThe etnaviv authors 1627a8c21a54SThe etnaviv authors gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1628a8c21a54SThe etnaviv authors if (!gpu) 1629a8c21a54SThe etnaviv authors return -ENOMEM; 1630a8c21a54SThe etnaviv authors 1631a8c21a54SThe etnaviv authors gpu->dev = &pdev->dev; 1632a8c21a54SThe etnaviv authors mutex_init(&gpu->lock); 1633a8c21a54SThe etnaviv authors 1634a8c21a54SThe etnaviv authors /* Map registers: */ 1635a8c21a54SThe etnaviv authors gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev)); 1636a8c21a54SThe etnaviv authors if (IS_ERR(gpu->mmio)) 1637a8c21a54SThe etnaviv authors return PTR_ERR(gpu->mmio); 1638a8c21a54SThe etnaviv authors 1639a8c21a54SThe etnaviv authors /* Get Interrupt: */ 1640a8c21a54SThe etnaviv authors gpu->irq = platform_get_irq(pdev, 0); 1641a8c21a54SThe etnaviv authors if (gpu->irq < 0) { 1642db60eda3SFabio Estevam dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1643db60eda3SFabio Estevam return gpu->irq; 1644a8c21a54SThe etnaviv authors } 1645a8c21a54SThe etnaviv authors 1646a8c21a54SThe etnaviv authors err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1647a8c21a54SThe etnaviv authors dev_name(gpu->dev), gpu); 1648a8c21a54SThe etnaviv authors if (err) { 1649a8c21a54SThe etnaviv authors dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1650db60eda3SFabio Estevam return err; 1651a8c21a54SThe etnaviv authors } 1652a8c21a54SThe etnaviv authors 1653a8c21a54SThe etnaviv authors /* Get Clocks: */ 1654a8c21a54SThe etnaviv authors gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1655a8c21a54SThe etnaviv authors DBG("clk_bus: %p", gpu->clk_bus); 1656a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_bus)) 1657a8c21a54SThe etnaviv authors gpu->clk_bus = NULL; 1658a8c21a54SThe etnaviv authors 1659a8c21a54SThe etnaviv authors gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1660a8c21a54SThe etnaviv authors DBG("clk_core: %p", gpu->clk_core); 1661a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_core)) 1662a8c21a54SThe etnaviv authors gpu->clk_core = NULL; 1663a8c21a54SThe etnaviv authors 1664a8c21a54SThe etnaviv authors gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1665a8c21a54SThe etnaviv authors DBG("clk_shader: %p", gpu->clk_shader); 1666a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_shader)) 1667a8c21a54SThe etnaviv authors gpu->clk_shader = NULL; 1668a8c21a54SThe etnaviv authors 1669a8c21a54SThe etnaviv authors /* TODO: figure out max mapped size */ 1670a8c21a54SThe etnaviv authors dev_set_drvdata(dev, gpu); 1671a8c21a54SThe etnaviv authors 1672a8c21a54SThe etnaviv authors /* 1673a8c21a54SThe etnaviv authors * We treat the device as initially suspended. The runtime PM 1674a8c21a54SThe etnaviv authors * autosuspend delay is rather arbitary: no measurements have 1675a8c21a54SThe etnaviv authors * yet been performed to determine an appropriate value. 1676a8c21a54SThe etnaviv authors */ 1677a8c21a54SThe etnaviv authors pm_runtime_use_autosuspend(gpu->dev); 1678a8c21a54SThe etnaviv authors pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1679a8c21a54SThe etnaviv authors pm_runtime_enable(gpu->dev); 1680a8c21a54SThe etnaviv authors 1681a8c21a54SThe etnaviv authors err = component_add(&pdev->dev, &gpu_ops); 1682a8c21a54SThe etnaviv authors if (err < 0) { 1683a8c21a54SThe etnaviv authors dev_err(&pdev->dev, "failed to register component: %d\n", err); 1684db60eda3SFabio Estevam return err; 1685a8c21a54SThe etnaviv authors } 1686a8c21a54SThe etnaviv authors 1687a8c21a54SThe etnaviv authors return 0; 1688a8c21a54SThe etnaviv authors } 1689a8c21a54SThe etnaviv authors 1690a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1691a8c21a54SThe etnaviv authors { 1692a8c21a54SThe etnaviv authors component_del(&pdev->dev, &gpu_ops); 1693a8c21a54SThe etnaviv authors pm_runtime_disable(&pdev->dev); 1694a8c21a54SThe etnaviv authors return 0; 1695a8c21a54SThe etnaviv authors } 1696a8c21a54SThe etnaviv authors 1697a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1698a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_suspend(struct device *dev) 1699a8c21a54SThe etnaviv authors { 1700a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1701a8c21a54SThe etnaviv authors u32 idle, mask; 1702a8c21a54SThe etnaviv authors 1703a8c21a54SThe etnaviv authors /* If we have outstanding fences, we're not idle */ 1704a8c21a54SThe etnaviv authors if (gpu->completed_fence != gpu->active_fence) 1705a8c21a54SThe etnaviv authors return -EBUSY; 1706a8c21a54SThe etnaviv authors 1707a8c21a54SThe etnaviv authors /* Check whether the hardware (except FE) is idle */ 1708a8c21a54SThe etnaviv authors mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1709a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1710a8c21a54SThe etnaviv authors if (idle != mask) 1711a8c21a54SThe etnaviv authors return -EBUSY; 1712a8c21a54SThe etnaviv authors 1713a8c21a54SThe etnaviv authors return etnaviv_gpu_hw_suspend(gpu); 1714a8c21a54SThe etnaviv authors } 1715a8c21a54SThe etnaviv authors 1716a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_resume(struct device *dev) 1717a8c21a54SThe etnaviv authors { 1718a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1719a8c21a54SThe etnaviv authors int ret; 1720a8c21a54SThe etnaviv authors 1721a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1722a8c21a54SThe etnaviv authors if (ret) 1723a8c21a54SThe etnaviv authors return ret; 1724a8c21a54SThe etnaviv authors 1725a8c21a54SThe etnaviv authors /* Re-initialise the basic hardware state */ 1726a8c21a54SThe etnaviv authors if (gpu->drm && gpu->buffer) { 1727a8c21a54SThe etnaviv authors ret = etnaviv_gpu_hw_resume(gpu); 1728a8c21a54SThe etnaviv authors if (ret) { 1729a8c21a54SThe etnaviv authors etnaviv_gpu_clk_disable(gpu); 1730a8c21a54SThe etnaviv authors return ret; 1731a8c21a54SThe etnaviv authors } 1732a8c21a54SThe etnaviv authors } 1733a8c21a54SThe etnaviv authors 1734a8c21a54SThe etnaviv authors return 0; 1735a8c21a54SThe etnaviv authors } 1736a8c21a54SThe etnaviv authors #endif 1737a8c21a54SThe etnaviv authors 1738a8c21a54SThe etnaviv authors static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1739a8c21a54SThe etnaviv authors SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1740a8c21a54SThe etnaviv authors NULL) 1741a8c21a54SThe etnaviv authors }; 1742a8c21a54SThe etnaviv authors 1743a8c21a54SThe etnaviv authors struct platform_driver etnaviv_gpu_driver = { 1744a8c21a54SThe etnaviv authors .driver = { 1745a8c21a54SThe etnaviv authors .name = "etnaviv-gpu", 1746a8c21a54SThe etnaviv authors .owner = THIS_MODULE, 1747a8c21a54SThe etnaviv authors .pm = &etnaviv_gpu_pm_ops, 1748a8c21a54SThe etnaviv authors .of_match_table = etnaviv_gpu_match, 1749a8c21a54SThe etnaviv authors }, 1750a8c21a54SThe etnaviv authors .probe = etnaviv_gpu_platform_probe, 1751a8c21a54SThe etnaviv authors .remove = etnaviv_gpu_platform_remove, 1752a8c21a54SThe etnaviv authors .id_table = gpu_ids, 1753a8c21a54SThe etnaviv authors }; 1754