1f6ffbd4fSLucas Stach // SPDX-License-Identifier: GPL-2.0 2a8c21a54SThe etnaviv authors /* 3f6ffbd4fSLucas Stach * Copyright (C) 2015-2018 Etnaviv Project 4a8c21a54SThe etnaviv authors */ 5a8c21a54SThe etnaviv authors 6f9d255f4SLucas Stach #include <linux/clk.h> 7a8c21a54SThe etnaviv authors #include <linux/component.h> 86eae41feSSam Ravnborg #include <linux/delay.h> 9f54d1867SChris Wilson #include <linux/dma-fence.h> 106eae41feSSam Ravnborg #include <linux/dma-mapping.h> 112e737e52SLucas Stach #include <linux/module.h> 12a8c21a54SThe etnaviv authors #include <linux/of_device.h> 132e737e52SLucas Stach #include <linux/platform_device.h> 142e737e52SLucas Stach #include <linux/pm_runtime.h> 15f9d255f4SLucas Stach #include <linux/regulator/consumer.h> 16bcdfb5e5SRussell King #include <linux/thermal.h> 17ea1f5729SLucas Stach 18ea1f5729SLucas Stach #include "etnaviv_cmdbuf.h" 19a8c21a54SThe etnaviv authors #include "etnaviv_dump.h" 20a8c21a54SThe etnaviv authors #include "etnaviv_gpu.h" 21a8c21a54SThe etnaviv authors #include "etnaviv_gem.h" 22a8c21a54SThe etnaviv authors #include "etnaviv_mmu.h" 23357713ceSChristian Gmeiner #include "etnaviv_perfmon.h" 24e93b6deeSLucas Stach #include "etnaviv_sched.h" 25a8c21a54SThe etnaviv authors #include "common.xml.h" 26a8c21a54SThe etnaviv authors #include "state.xml.h" 27a8c21a54SThe etnaviv authors #include "state_hi.xml.h" 28a8c21a54SThe etnaviv authors #include "cmdstream.xml.h" 29a8c21a54SThe etnaviv authors 30a8c21a54SThe etnaviv authors static const struct platform_device_id gpu_ids[] = { 31a8c21a54SThe etnaviv authors { .name = "etnaviv-gpu,2d" }, 32a8c21a54SThe etnaviv authors { }, 33a8c21a54SThe etnaviv authors }; 34a8c21a54SThe etnaviv authors 35a8c21a54SThe etnaviv authors /* 36a8c21a54SThe etnaviv authors * Driver functions: 37a8c21a54SThe etnaviv authors */ 38a8c21a54SThe etnaviv authors 39a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 40a8c21a54SThe etnaviv authors { 41088880ddSLucas Stach struct etnaviv_drm_private *priv = gpu->drm->dev_private; 42088880ddSLucas Stach 43a8c21a54SThe etnaviv authors switch (param) { 44a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_MODEL: 45a8c21a54SThe etnaviv authors *value = gpu->identity.model; 46a8c21a54SThe etnaviv authors break; 47a8c21a54SThe etnaviv authors 48a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REVISION: 49a8c21a54SThe etnaviv authors *value = gpu->identity.revision; 50a8c21a54SThe etnaviv authors break; 51a8c21a54SThe etnaviv authors 52a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_0: 53a8c21a54SThe etnaviv authors *value = gpu->identity.features; 54a8c21a54SThe etnaviv authors break; 55a8c21a54SThe etnaviv authors 56a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_1: 57a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features0; 58a8c21a54SThe etnaviv authors break; 59a8c21a54SThe etnaviv authors 60a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_2: 61a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features1; 62a8c21a54SThe etnaviv authors break; 63a8c21a54SThe etnaviv authors 64a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_3: 65a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features2; 66a8c21a54SThe etnaviv authors break; 67a8c21a54SThe etnaviv authors 68a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_4: 69a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features3; 70a8c21a54SThe etnaviv authors break; 71a8c21a54SThe etnaviv authors 72602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_5: 73602eb489SRussell King *value = gpu->identity.minor_features4; 74602eb489SRussell King break; 75602eb489SRussell King 76602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_6: 77602eb489SRussell King *value = gpu->identity.minor_features5; 78602eb489SRussell King break; 79602eb489SRussell King 800538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_7: 810538aaf9SLucas Stach *value = gpu->identity.minor_features6; 820538aaf9SLucas Stach break; 830538aaf9SLucas Stach 840538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_8: 850538aaf9SLucas Stach *value = gpu->identity.minor_features7; 860538aaf9SLucas Stach break; 870538aaf9SLucas Stach 880538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_9: 890538aaf9SLucas Stach *value = gpu->identity.minor_features8; 900538aaf9SLucas Stach break; 910538aaf9SLucas Stach 920538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_10: 930538aaf9SLucas Stach *value = gpu->identity.minor_features9; 940538aaf9SLucas Stach break; 950538aaf9SLucas Stach 960538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_11: 970538aaf9SLucas Stach *value = gpu->identity.minor_features10; 980538aaf9SLucas Stach break; 990538aaf9SLucas Stach 1000538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_12: 1010538aaf9SLucas Stach *value = gpu->identity.minor_features11; 1020538aaf9SLucas Stach break; 1030538aaf9SLucas Stach 104a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_STREAM_COUNT: 105a8c21a54SThe etnaviv authors *value = gpu->identity.stream_count; 106a8c21a54SThe etnaviv authors break; 107a8c21a54SThe etnaviv authors 108a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REGISTER_MAX: 109a8c21a54SThe etnaviv authors *value = gpu->identity.register_max; 110a8c21a54SThe etnaviv authors break; 111a8c21a54SThe etnaviv authors 112a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_THREAD_COUNT: 113a8c21a54SThe etnaviv authors *value = gpu->identity.thread_count; 114a8c21a54SThe etnaviv authors break; 115a8c21a54SThe etnaviv authors 116a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 117a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_cache_size; 118a8c21a54SThe etnaviv authors break; 119a8c21a54SThe etnaviv authors 120a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 121a8c21a54SThe etnaviv authors *value = gpu->identity.shader_core_count; 122a8c21a54SThe etnaviv authors break; 123a8c21a54SThe etnaviv authors 124a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 125a8c21a54SThe etnaviv authors *value = gpu->identity.pixel_pipes; 126a8c21a54SThe etnaviv authors break; 127a8c21a54SThe etnaviv authors 128a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 129a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_output_buffer_size; 130a8c21a54SThe etnaviv authors break; 131a8c21a54SThe etnaviv authors 132a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 133a8c21a54SThe etnaviv authors *value = gpu->identity.buffer_size; 134a8c21a54SThe etnaviv authors break; 135a8c21a54SThe etnaviv authors 136a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 137a8c21a54SThe etnaviv authors *value = gpu->identity.instruction_count; 138a8c21a54SThe etnaviv authors break; 139a8c21a54SThe etnaviv authors 140a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 141a8c21a54SThe etnaviv authors *value = gpu->identity.num_constants; 142a8c21a54SThe etnaviv authors break; 143a8c21a54SThe etnaviv authors 144602eb489SRussell King case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 145602eb489SRussell King *value = gpu->identity.varyings_count; 146602eb489SRussell King break; 147602eb489SRussell King 148088880ddSLucas Stach case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 149088880ddSLucas Stach if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 150088880ddSLucas Stach *value = ETNAVIV_SOFTPIN_START_ADDRESS; 151088880ddSLucas Stach else 152088880ddSLucas Stach *value = ~0ULL; 153088880ddSLucas Stach break; 154088880ddSLucas Stach 1551ff79a4aSChristian Gmeiner case ETNAVIV_PARAM_GPU_PRODUCT_ID: 1561ff79a4aSChristian Gmeiner *value = gpu->identity.product_id; 1571ff79a4aSChristian Gmeiner break; 1581ff79a4aSChristian Gmeiner 1591ff79a4aSChristian Gmeiner case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 1601ff79a4aSChristian Gmeiner *value = gpu->identity.customer_id; 1611ff79a4aSChristian Gmeiner break; 1621ff79a4aSChristian Gmeiner 1631ff79a4aSChristian Gmeiner case ETNAVIV_PARAM_GPU_ECO_ID: 1641ff79a4aSChristian Gmeiner *value = gpu->identity.eco_id; 1651ff79a4aSChristian Gmeiner break; 1661ff79a4aSChristian Gmeiner 167a8c21a54SThe etnaviv authors default: 168a8c21a54SThe etnaviv authors DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 169a8c21a54SThe etnaviv authors return -EINVAL; 170a8c21a54SThe etnaviv authors } 171a8c21a54SThe etnaviv authors 172a8c21a54SThe etnaviv authors return 0; 173a8c21a54SThe etnaviv authors } 174a8c21a54SThe etnaviv authors 175472f79dcSRussell King 176472f79dcSRussell King #define etnaviv_is_model_rev(gpu, mod, rev) \ 177472f79dcSRussell King ((gpu)->identity.model == chipModel_##mod && \ 178472f79dcSRussell King (gpu)->identity.revision == rev) 17952f36ba1SRussell King #define etnaviv_field(val, field) \ 18052f36ba1SRussell King (((val) & field##__MASK) >> field##__SHIFT) 18152f36ba1SRussell King 182a8c21a54SThe etnaviv authors static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 183a8c21a54SThe etnaviv authors { 184a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 185a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 186602eb489SRussell King u32 specs[4]; 187602eb489SRussell King unsigned int streams; 188a8c21a54SThe etnaviv authors 189a8c21a54SThe etnaviv authors specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 190a8c21a54SThe etnaviv authors specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 191602eb489SRussell King specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 192602eb489SRussell King specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 193a8c21a54SThe etnaviv authors 19452f36ba1SRussell King gpu->identity.stream_count = etnaviv_field(specs[0], 19552f36ba1SRussell King VIVS_HI_CHIP_SPECS_STREAM_COUNT); 19652f36ba1SRussell King gpu->identity.register_max = etnaviv_field(specs[0], 19752f36ba1SRussell King VIVS_HI_CHIP_SPECS_REGISTER_MAX); 19852f36ba1SRussell King gpu->identity.thread_count = etnaviv_field(specs[0], 19952f36ba1SRussell King VIVS_HI_CHIP_SPECS_THREAD_COUNT); 20052f36ba1SRussell King gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 20152f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 20252f36ba1SRussell King gpu->identity.shader_core_count = etnaviv_field(specs[0], 20352f36ba1SRussell King VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 20452f36ba1SRussell King gpu->identity.pixel_pipes = etnaviv_field(specs[0], 20552f36ba1SRussell King VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 206a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 20752f36ba1SRussell King etnaviv_field(specs[0], 20852f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 209a8c21a54SThe etnaviv authors 21052f36ba1SRussell King gpu->identity.buffer_size = etnaviv_field(specs[1], 21152f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 21252f36ba1SRussell King gpu->identity.instruction_count = etnaviv_field(specs[1], 21352f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 21452f36ba1SRussell King gpu->identity.num_constants = etnaviv_field(specs[1], 21552f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 216602eb489SRussell King 217602eb489SRussell King gpu->identity.varyings_count = etnaviv_field(specs[2], 218602eb489SRussell King VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 219602eb489SRussell King 220602eb489SRussell King /* This overrides the value from older register if non-zero */ 221602eb489SRussell King streams = etnaviv_field(specs[3], 222602eb489SRussell King VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 223602eb489SRussell King if (streams) 224602eb489SRussell King gpu->identity.stream_count = streams; 225a8c21a54SThe etnaviv authors } 226a8c21a54SThe etnaviv authors 227a8c21a54SThe etnaviv authors /* Fill in the stream count if not specified */ 228a8c21a54SThe etnaviv authors if (gpu->identity.stream_count == 0) { 229a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 230a8c21a54SThe etnaviv authors gpu->identity.stream_count = 4; 231a8c21a54SThe etnaviv authors else 232a8c21a54SThe etnaviv authors gpu->identity.stream_count = 1; 233a8c21a54SThe etnaviv authors } 234a8c21a54SThe etnaviv authors 235a8c21a54SThe etnaviv authors /* Convert the register max value */ 236a8c21a54SThe etnaviv authors if (gpu->identity.register_max) 237a8c21a54SThe etnaviv authors gpu->identity.register_max = 1 << gpu->identity.register_max; 238507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 239a8c21a54SThe etnaviv authors gpu->identity.register_max = 32; 240a8c21a54SThe etnaviv authors else 241a8c21a54SThe etnaviv authors gpu->identity.register_max = 64; 242a8c21a54SThe etnaviv authors 243a8c21a54SThe etnaviv authors /* Convert thread count */ 244a8c21a54SThe etnaviv authors if (gpu->identity.thread_count) 245a8c21a54SThe etnaviv authors gpu->identity.thread_count = 1 << gpu->identity.thread_count; 246507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 247a8c21a54SThe etnaviv authors gpu->identity.thread_count = 64; 248507f8991SRussell King else if (gpu->identity.model == chipModel_GC500 || 249507f8991SRussell King gpu->identity.model == chipModel_GC530) 250a8c21a54SThe etnaviv authors gpu->identity.thread_count = 128; 251a8c21a54SThe etnaviv authors else 252a8c21a54SThe etnaviv authors gpu->identity.thread_count = 256; 253a8c21a54SThe etnaviv authors 254a8c21a54SThe etnaviv authors if (gpu->identity.vertex_cache_size == 0) 255a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size = 8; 256a8c21a54SThe etnaviv authors 257a8c21a54SThe etnaviv authors if (gpu->identity.shader_core_count == 0) { 258a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 259a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 2; 260a8c21a54SThe etnaviv authors else 261a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 1; 262a8c21a54SThe etnaviv authors } 263a8c21a54SThe etnaviv authors 264a8c21a54SThe etnaviv authors if (gpu->identity.pixel_pipes == 0) 265a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes = 1; 266a8c21a54SThe etnaviv authors 267a8c21a54SThe etnaviv authors /* Convert virtex buffer size */ 268a8c21a54SThe etnaviv authors if (gpu->identity.vertex_output_buffer_size) { 269a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 270a8c21a54SThe etnaviv authors 1 << gpu->identity.vertex_output_buffer_size; 271507f8991SRussell King } else if (gpu->identity.model == chipModel_GC400) { 272a8c21a54SThe etnaviv authors if (gpu->identity.revision < 0x4000) 273a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 274a8c21a54SThe etnaviv authors else if (gpu->identity.revision < 0x4200) 275a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 256; 276a8c21a54SThe etnaviv authors else 277a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 128; 278a8c21a54SThe etnaviv authors } else { 279a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 280a8c21a54SThe etnaviv authors } 281a8c21a54SThe etnaviv authors 282a8c21a54SThe etnaviv authors switch (gpu->identity.instruction_count) { 283a8c21a54SThe etnaviv authors case 0: 284472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 285507f8991SRussell King gpu->identity.model == chipModel_GC880) 286a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 512; 287a8c21a54SThe etnaviv authors else 288a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 289a8c21a54SThe etnaviv authors break; 290a8c21a54SThe etnaviv authors 291a8c21a54SThe etnaviv authors case 1: 292a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 1024; 293a8c21a54SThe etnaviv authors break; 294a8c21a54SThe etnaviv authors 295a8c21a54SThe etnaviv authors case 2: 296a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 2048; 297a8c21a54SThe etnaviv authors break; 298a8c21a54SThe etnaviv authors 299a8c21a54SThe etnaviv authors default: 300a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 301a8c21a54SThe etnaviv authors break; 302a8c21a54SThe etnaviv authors } 303a8c21a54SThe etnaviv authors 304a8c21a54SThe etnaviv authors if (gpu->identity.num_constants == 0) 305a8c21a54SThe etnaviv authors gpu->identity.num_constants = 168; 306602eb489SRussell King 307602eb489SRussell King if (gpu->identity.varyings_count == 0) { 308602eb489SRussell King if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 309602eb489SRussell King gpu->identity.varyings_count = 12; 310602eb489SRussell King else 311602eb489SRussell King gpu->identity.varyings_count = 8; 312602eb489SRussell King } 313602eb489SRussell King 314602eb489SRussell King /* 315602eb489SRussell King * For some cores, two varyings are consumed for position, so the 316602eb489SRussell King * maximum varying count needs to be reduced by one. 317602eb489SRussell King */ 318602eb489SRussell King if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 319602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 320602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 321602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 322602eb489SRussell King etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 323602eb489SRussell King etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 324602eb489SRussell King etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 325602eb489SRussell King etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 326602eb489SRussell King etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 327602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5107) || 328602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5106)) 329602eb489SRussell King gpu->identity.varyings_count -= 1; 330a8c21a54SThe etnaviv authors } 331a8c21a54SThe etnaviv authors 332a8c21a54SThe etnaviv authors static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 333a8c21a54SThe etnaviv authors { 334a8c21a54SThe etnaviv authors u32 chipIdentity; 335a8c21a54SThe etnaviv authors 336a8c21a54SThe etnaviv authors chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 337a8c21a54SThe etnaviv authors 338a8c21a54SThe etnaviv authors /* Special case for older graphic cores. */ 33952f36ba1SRussell King if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 340507f8991SRussell King gpu->identity.model = chipModel_GC500; 34152f36ba1SRussell King gpu->identity.revision = etnaviv_field(chipIdentity, 34252f36ba1SRussell King VIVS_HI_CHIP_IDENTITY_REVISION); 343a8c21a54SThe etnaviv authors } else { 344815e45bbSChristian Gmeiner u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 345a8c21a54SThe etnaviv authors 346a8c21a54SThe etnaviv authors gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 347a8c21a54SThe etnaviv authors gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 348815e45bbSChristian Gmeiner gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 3492c5bf028SChristian Gmeiner 3502c5bf028SChristian Gmeiner /* 3512c5bf028SChristian Gmeiner * Reading these two registers on GC600 rev 0x19 result in a 3522c5bf028SChristian Gmeiner * unhandled fault: external abort on non-linefetch 3532c5bf028SChristian Gmeiner */ 3542c5bf028SChristian Gmeiner if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { 3552c5bf028SChristian Gmeiner gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 356815e45bbSChristian Gmeiner gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 3572c5bf028SChristian Gmeiner } 358a8c21a54SThe etnaviv authors 359a8c21a54SThe etnaviv authors /* 360a8c21a54SThe etnaviv authors * !!!! HACK ALERT !!!! 361a8c21a54SThe etnaviv authors * Because people change device IDs without letting software 362a8c21a54SThe etnaviv authors * know about it - here is the hack to make it all look the 363a8c21a54SThe etnaviv authors * same. Only for GC400 family. 364a8c21a54SThe etnaviv authors */ 365a8c21a54SThe etnaviv authors if ((gpu->identity.model & 0xff00) == 0x0400 && 366507f8991SRussell King gpu->identity.model != chipModel_GC420) { 367a8c21a54SThe etnaviv authors gpu->identity.model = gpu->identity.model & 0x0400; 368a8c21a54SThe etnaviv authors } 369a8c21a54SThe etnaviv authors 370a8c21a54SThe etnaviv authors /* Another special case */ 371472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 372a8c21a54SThe etnaviv authors u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 373a8c21a54SThe etnaviv authors 374a8c21a54SThe etnaviv authors if (chipDate == 0x20080814 && chipTime == 0x12051100) { 375a8c21a54SThe etnaviv authors /* 376a8c21a54SThe etnaviv authors * This IP has an ECO; put the correct 377a8c21a54SThe etnaviv authors * revision in it. 378a8c21a54SThe etnaviv authors */ 379a8c21a54SThe etnaviv authors gpu->identity.revision = 0x1051; 380a8c21a54SThe etnaviv authors } 381a8c21a54SThe etnaviv authors } 38212ff4bdeSLucas Stach 38312ff4bdeSLucas Stach /* 38412ff4bdeSLucas Stach * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 38512ff4bdeSLucas Stach * reality it's just a re-branded GC3000. We can identify this 38612ff4bdeSLucas Stach * core by the upper half of the revision register being all 1. 38712ff4bdeSLucas Stach * Fix model/rev here, so all other places can refer to this 38812ff4bdeSLucas Stach * core by its real identity. 38912ff4bdeSLucas Stach */ 39012ff4bdeSLucas Stach if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 39112ff4bdeSLucas Stach gpu->identity.model = chipModel_GC3000; 39212ff4bdeSLucas Stach gpu->identity.revision &= 0xffff; 39312ff4bdeSLucas Stach } 394815e45bbSChristian Gmeiner 395815e45bbSChristian Gmeiner if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) 396815e45bbSChristian Gmeiner gpu->identity.eco_id = 1; 397815e45bbSChristian Gmeiner 398815e45bbSChristian Gmeiner if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) 399815e45bbSChristian Gmeiner gpu->identity.eco_id = 1; 400a8c21a54SThe etnaviv authors } 401a8c21a54SThe etnaviv authors 402a8c21a54SThe etnaviv authors dev_info(gpu->dev, "model: GC%x, revision: %x\n", 403a8c21a54SThe etnaviv authors gpu->identity.model, gpu->identity.revision); 404a8c21a54SThe etnaviv authors 4052b76f5beSLucas Stach gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 406681c19c8SLucas Stach /* 407681c19c8SLucas Stach * If there is a match in the HWDB, we aren't interested in the 408681c19c8SLucas Stach * remaining register values, as they might be wrong. 409681c19c8SLucas Stach */ 410681c19c8SLucas Stach if (etnaviv_fill_identity_from_hwdb(gpu)) 411681c19c8SLucas Stach return; 412681c19c8SLucas Stach 413a8c21a54SThe etnaviv authors gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 414a8c21a54SThe etnaviv authors 415a8c21a54SThe etnaviv authors /* Disable fast clear on GC700. */ 416507f8991SRussell King if (gpu->identity.model == chipModel_GC700) 417a8c21a54SThe etnaviv authors gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 418a8c21a54SThe etnaviv authors 419507f8991SRussell King if ((gpu->identity.model == chipModel_GC500 && 420507f8991SRussell King gpu->identity.revision < 2) || 421507f8991SRussell King (gpu->identity.model == chipModel_GC300 && 422507f8991SRussell King gpu->identity.revision < 0x2000)) { 423a8c21a54SThe etnaviv authors 424a8c21a54SThe etnaviv authors /* 425a8c21a54SThe etnaviv authors * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 426a8c21a54SThe etnaviv authors * registers. 427a8c21a54SThe etnaviv authors */ 428a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 0; 429a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 0; 430a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 0; 431a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 0; 432602eb489SRussell King gpu->identity.minor_features4 = 0; 433602eb489SRussell King gpu->identity.minor_features5 = 0; 434a8c21a54SThe etnaviv authors } else 435a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 436a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 437a8c21a54SThe etnaviv authors 438a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 439a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 440a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 441a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 442a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 443a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 444a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 445a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 446602eb489SRussell King gpu->identity.minor_features4 = 447602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 448602eb489SRussell King gpu->identity.minor_features5 = 449602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 450a8c21a54SThe etnaviv authors } 451a8c21a54SThe etnaviv authors 452a8c21a54SThe etnaviv authors /* GC600 idle register reports zero bits where modules aren't present */ 4532b76f5beSLucas Stach if (gpu->identity.model == chipModel_GC600) 454a8c21a54SThe etnaviv authors gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 455a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_RA | 456a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SE | 457a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PA | 458a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SH | 459a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PE | 460a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_DE | 461a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_FE; 462a8c21a54SThe etnaviv authors 463a8c21a54SThe etnaviv authors etnaviv_hw_specs(gpu); 464a8c21a54SThe etnaviv authors } 465a8c21a54SThe etnaviv authors 466a8c21a54SThe etnaviv authors static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 467a8c21a54SThe etnaviv authors { 468a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 469a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 470a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 471a8c21a54SThe etnaviv authors } 472a8c21a54SThe etnaviv authors 473bcdfb5e5SRussell King static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 474bcdfb5e5SRussell King { 475d79fd1ccSLucas Stach if (gpu->identity.minor_features2 & 476d79fd1ccSLucas Stach chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 477d79fd1ccSLucas Stach clk_set_rate(gpu->clk_core, 478d79fd1ccSLucas Stach gpu->base_rate_core >> gpu->freq_scale); 479d79fd1ccSLucas Stach clk_set_rate(gpu->clk_shader, 480d79fd1ccSLucas Stach gpu->base_rate_shader >> gpu->freq_scale); 481d79fd1ccSLucas Stach } else { 482bcdfb5e5SRussell King unsigned int fscale = 1 << (6 - gpu->freq_scale); 4836eb3ecc3SLucas Stach u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 484bcdfb5e5SRussell King 4856eb3ecc3SLucas Stach clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 4866eb3ecc3SLucas Stach clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 487bcdfb5e5SRussell King etnaviv_gpu_load_clock(gpu, clock); 488bcdfb5e5SRussell King } 489d79fd1ccSLucas Stach } 490bcdfb5e5SRussell King 491a8c21a54SThe etnaviv authors static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 492a8c21a54SThe etnaviv authors { 493a8c21a54SThe etnaviv authors u32 control, idle; 494a8c21a54SThe etnaviv authors unsigned long timeout; 495a8c21a54SThe etnaviv authors bool failed = true; 496a8c21a54SThe etnaviv authors 497a8c21a54SThe etnaviv authors /* We hope that the GPU resets in under one second */ 498a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(1000); 499a8c21a54SThe etnaviv authors 500a8c21a54SThe etnaviv authors while (time_is_after_jiffies(timeout)) { 501a8c21a54SThe etnaviv authors /* enable clock */ 5026eb3ecc3SLucas Stach unsigned int fscale = 1 << (6 - gpu->freq_scale); 5036eb3ecc3SLucas Stach control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 5046eb3ecc3SLucas Stach etnaviv_gpu_load_clock(gpu, control); 505a8c21a54SThe etnaviv authors 506a8c21a54SThe etnaviv authors /* isolate the GPU. */ 507a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 508a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 509a8c21a54SThe etnaviv authors 510c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 511c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 512c997c3dfSLucas Stach VIVS_MMUv2_AHB_CONTROL_RESET); 513c997c3dfSLucas Stach } else { 514a8c21a54SThe etnaviv authors /* set soft reset. */ 515a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 516a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 517c997c3dfSLucas Stach } 518a8c21a54SThe etnaviv authors 519a8c21a54SThe etnaviv authors /* wait for reset. */ 52040462179SPhilipp Zabel usleep_range(10, 20); 521a8c21a54SThe etnaviv authors 522a8c21a54SThe etnaviv authors /* reset soft reset bit. */ 523a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 524a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 525a8c21a54SThe etnaviv authors 526a8c21a54SThe etnaviv authors /* reset GPU isolation. */ 527a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 528a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 529a8c21a54SThe etnaviv authors 530a8c21a54SThe etnaviv authors /* read idle register. */ 531a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 532a8c21a54SThe etnaviv authors 533ea4ed4a5SGuido Günther /* try resetting again if FE is not idle */ 534a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 535a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "FE is not idle\n"); 536a8c21a54SThe etnaviv authors continue; 537a8c21a54SThe etnaviv authors } 538a8c21a54SThe etnaviv authors 539a8c21a54SThe etnaviv authors /* read reset register. */ 540a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 541a8c21a54SThe etnaviv authors 542a8c21a54SThe etnaviv authors /* is the GPU idle? */ 543a8c21a54SThe etnaviv authors if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 544a8c21a54SThe etnaviv authors ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 545a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "GPU is not idle\n"); 546a8c21a54SThe etnaviv authors continue; 547a8c21a54SThe etnaviv authors } 548a8c21a54SThe etnaviv authors 5496eb3ecc3SLucas Stach /* disable debug registers, as they are not normally needed */ 5506eb3ecc3SLucas Stach control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 5516eb3ecc3SLucas Stach gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 5526eb3ecc3SLucas Stach 553a8c21a54SThe etnaviv authors failed = false; 554a8c21a54SThe etnaviv authors break; 555a8c21a54SThe etnaviv authors } 556a8c21a54SThe etnaviv authors 557a8c21a54SThe etnaviv authors if (failed) { 558a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 559a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 560a8c21a54SThe etnaviv authors 561a8c21a54SThe etnaviv authors dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 562a8c21a54SThe etnaviv authors idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 563a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 564a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 565a8c21a54SThe etnaviv authors 566a8c21a54SThe etnaviv authors return -EBUSY; 567a8c21a54SThe etnaviv authors } 568a8c21a54SThe etnaviv authors 569a8c21a54SThe etnaviv authors /* We rely on the GPU running, so program the clock */ 570bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 571a8c21a54SThe etnaviv authors 57223e0f5a5SLucas Stach gpu->fe_running = false; 573725cbc78SLucas Stach gpu->exec_state = -1; 574f978a530SLucas Stach if (gpu->mmu_context) 575f978a530SLucas Stach etnaviv_iommu_context_put(gpu->mmu_context); 576725cbc78SLucas Stach gpu->mmu_context = NULL; 57723e0f5a5SLucas Stach 578a8c21a54SThe etnaviv authors return 0; 579a8c21a54SThe etnaviv authors } 580a8c21a54SThe etnaviv authors 5817d0c6e71SRussell King static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 5827d0c6e71SRussell King { 5837d0c6e71SRussell King u32 pmc, ppc; 5847d0c6e71SRussell King 5857d0c6e71SRussell King /* enable clock gating */ 5867d0c6e71SRussell King ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 5877d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 5887d0c6e71SRussell King 5897d0c6e71SRussell King /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 5907d0c6e71SRussell King if (gpu->identity.revision == 0x4301 || 5917d0c6e71SRussell King gpu->identity.revision == 0x4302) 5927d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 5937d0c6e71SRussell King 5947d0c6e71SRussell King gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 5957d0c6e71SRussell King 5967d0c6e71SRussell King pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 5977d0c6e71SRussell King 5987cef6004SLucas Stach /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 5997d0c6e71SRussell King if (gpu->identity.model >= chipModel_GC400 && 6007cef6004SLucas Stach gpu->identity.model != chipModel_GC420 && 6017cef6004SLucas Stach !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 6027d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 6037d0c6e71SRussell King 6047d0c6e71SRussell King /* 6057d0c6e71SRussell King * Disable PE clock gating on revs < 5.0.0.0 when HZ is 6067d0c6e71SRussell King * present without a bug fix. 6077d0c6e71SRussell King */ 6087d0c6e71SRussell King if (gpu->identity.revision < 0x5000 && 6097d0c6e71SRussell King gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 6107d0c6e71SRussell King !(gpu->identity.minor_features1 & 6117d0c6e71SRussell King chipMinorFeatures1_DISABLE_PE_GATING)) 6127d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 6137d0c6e71SRussell King 6147d0c6e71SRussell King if (gpu->identity.revision < 0x5422) 6157d0c6e71SRussell King pmc |= BIT(15); /* Unknown bit */ 6167d0c6e71SRussell King 6177cef6004SLucas Stach /* Disable TX clock gating on affected core revisions. */ 6187cef6004SLucas Stach if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 6197cef6004SLucas Stach etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 6207cef6004SLucas Stach pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 6217cef6004SLucas Stach 622432f51e7SMichael Walle /* Disable SE, RA and TX clock gating on affected core revisions. */ 623432f51e7SMichael Walle if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) 624432f51e7SMichael Walle pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 625432f51e7SMichael Walle VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA | 626432f51e7SMichael Walle VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 627432f51e7SMichael Walle 6287d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 6297d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 6307d0c6e71SRussell King 6317d0c6e71SRussell King gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 6327d0c6e71SRussell King } 6337d0c6e71SRussell King 634229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 635229855b6SLucas Stach { 636229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 637229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 638229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_ENABLE | 639229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 640c997c3dfSLucas Stach 641c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 642c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 643c997c3dfSLucas Stach VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 644c997c3dfSLucas Stach VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 645c997c3dfSLucas Stach } 64623e0f5a5SLucas Stach 64723e0f5a5SLucas Stach gpu->fe_running = true; 648229855b6SLucas Stach } 649229855b6SLucas Stach 650d6408538SLucas Stach static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, 651d6408538SLucas Stach struct etnaviv_iommu_context *context) 652d80d842aSLucas Stach { 653d80d842aSLucas Stach u16 prefetch; 654d6408538SLucas Stach u32 address; 655d80d842aSLucas Stach 656d80d842aSLucas Stach /* setup the MMU */ 657d6408538SLucas Stach etnaviv_iommu_restore(gpu, context); 658d80d842aSLucas Stach 659d80d842aSLucas Stach /* Start command processor */ 660d80d842aSLucas Stach prefetch = etnaviv_buffer_init(gpu); 661d6408538SLucas Stach address = etnaviv_cmdbuf_get_va(&gpu->buffer, 662d6408538SLucas Stach &gpu->mmu_context->cmdbuf_mapping); 663d80d842aSLucas Stach 664d80d842aSLucas Stach etnaviv_gpu_start_fe(gpu, address, prefetch); 665d80d842aSLucas Stach } 666d80d842aSLucas Stach 667e17a0dedSWladimir J. van der Laan static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 668e17a0dedSWladimir J. van der Laan { 669e17a0dedSWladimir J. van der Laan /* 670e17a0dedSWladimir J. van der Laan * Base value for VIVS_PM_PULSE_EATER register on models where it 671e17a0dedSWladimir J. van der Laan * cannot be read, extracted from vivante kernel driver. 672e17a0dedSWladimir J. van der Laan */ 673e17a0dedSWladimir J. van der Laan u32 pulse_eater = 0x01590880; 674e17a0dedSWladimir J. van der Laan 675e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 676e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 677e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(23); 678e17a0dedSWladimir J. van der Laan 679e17a0dedSWladimir J. van der Laan } 680e17a0dedSWladimir J. van der Laan 681e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 682e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 683e17a0dedSWladimir J. van der Laan pulse_eater &= ~BIT(16); 684e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(17); 685e17a0dedSWladimir J. van der Laan } 686e17a0dedSWladimir J. van der Laan 687e17a0dedSWladimir J. van der Laan if ((gpu->identity.revision > 0x5420) && 688e17a0dedSWladimir J. van der Laan (gpu->identity.features & chipFeatures_PIPE_3D)) 689e17a0dedSWladimir J. van der Laan { 690e17a0dedSWladimir J. van der Laan /* Performance fix: disable internal DFS */ 691e17a0dedSWladimir J. van der Laan pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 692e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(18); 693e17a0dedSWladimir J. van der Laan } 694e17a0dedSWladimir J. van der Laan 695e17a0dedSWladimir J. van der Laan gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 696e17a0dedSWladimir J. van der Laan } 697e17a0dedSWladimir J. van der Laan 698a8c21a54SThe etnaviv authors static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 699a8c21a54SThe etnaviv authors { 700472f79dcSRussell King if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 701472f79dcSRussell King etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 702472f79dcSRussell King gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 703a8c21a54SThe etnaviv authors u32 mc_memory_debug; 704a8c21a54SThe etnaviv authors 705a8c21a54SThe etnaviv authors mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 706a8c21a54SThe etnaviv authors 707a8c21a54SThe etnaviv authors if (gpu->identity.revision == 0x5007) 708a8c21a54SThe etnaviv authors mc_memory_debug |= 0x0c; 709a8c21a54SThe etnaviv authors else 710a8c21a54SThe etnaviv authors mc_memory_debug |= 0x08; 711a8c21a54SThe etnaviv authors 712a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 713a8c21a54SThe etnaviv authors } 714a8c21a54SThe etnaviv authors 7157d0c6e71SRussell King /* enable module-level clock gating */ 7167d0c6e71SRussell King etnaviv_gpu_enable_mlcg(gpu); 7177d0c6e71SRussell King 718a8c21a54SThe etnaviv authors /* 719a8c21a54SThe etnaviv authors * Update GPU AXI cache atttribute to "cacheable, no allocate". 720a8c21a54SThe etnaviv authors * This is necessary to prevent the iMX6 SoC locking up. 721a8c21a54SThe etnaviv authors */ 722a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_AXI_CONFIG, 723a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_AWCACHE(2) | 724a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_ARCACHE(2)); 725a8c21a54SThe etnaviv authors 726a8c21a54SThe etnaviv authors /* GC2000 rev 5108 needs a special bus config */ 727472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 728a8c21a54SThe etnaviv authors u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 729a8c21a54SThe etnaviv authors bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 730a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 731a8c21a54SThe etnaviv authors bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 732a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 733a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 734a8c21a54SThe etnaviv authors } 735a8c21a54SThe etnaviv authors 736c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 737c997c3dfSLucas Stach u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 738c997c3dfSLucas Stach val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 739c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 740c997c3dfSLucas Stach } 741c997c3dfSLucas Stach 742e17a0dedSWladimir J. van der Laan /* setup the pulse eater */ 743e17a0dedSWladimir J. van der Laan etnaviv_gpu_setup_pulse_eater(gpu); 744e17a0dedSWladimir J. van der Laan 745a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 746a8c21a54SThe etnaviv authors } 747a8c21a54SThe etnaviv authors 748a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 749a8c21a54SThe etnaviv authors { 750bffe5db8SLucas Stach struct etnaviv_drm_private *priv = gpu->drm->dev_private; 7514bfdd2aaSLucas Stach dma_addr_t cmdbuf_paddr; 752a8c21a54SThe etnaviv authors int ret, i; 753a8c21a54SThe etnaviv authors 754a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 7551409df04SLucas Stach if (ret < 0) { 7561409df04SLucas Stach dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 757c5d5a32eSNavid Emamdoost goto pm_put; 7581409df04SLucas Stach } 759a8c21a54SThe etnaviv authors 760a8c21a54SThe etnaviv authors etnaviv_hw_identify(gpu); 761a8c21a54SThe etnaviv authors 762a8c21a54SThe etnaviv authors if (gpu->identity.model == 0) { 763a8c21a54SThe etnaviv authors dev_err(gpu->dev, "Unknown GPU model\n"); 764f6427760SRussell King ret = -ENXIO; 765f6427760SRussell King goto fail; 766a8c21a54SThe etnaviv authors } 767a8c21a54SThe etnaviv authors 768b98c6688SRussell King /* Exclude VG cores with FE2.0 */ 769b98c6688SRussell King if (gpu->identity.features & chipFeatures_PIPE_VG && 770b98c6688SRussell King gpu->identity.features & chipFeatures_FE20) { 771b98c6688SRussell King dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 772b98c6688SRussell King ret = -ENXIO; 773b98c6688SRussell King goto fail; 774b98c6688SRussell King } 775b98c6688SRussell King 7762144fff7SLucas Stach /* 777c997c3dfSLucas Stach * On cores with security features supported, we claim control over the 778c997c3dfSLucas Stach * security states. 779c997c3dfSLucas Stach */ 780c997c3dfSLucas Stach if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 781c997c3dfSLucas Stach (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 782c997c3dfSLucas Stach gpu->sec_mode = ETNA_SEC_KERNEL; 783c997c3dfSLucas Stach 784a8c21a54SThe etnaviv authors ret = etnaviv_hw_reset(gpu); 7851409df04SLucas Stach if (ret) { 7861409df04SLucas Stach dev_err(gpu->dev, "GPU reset failed\n"); 787a8c21a54SThe etnaviv authors goto fail; 7881409df04SLucas Stach } 789a8c21a54SThe etnaviv authors 79027b67278SLucas Stach ret = etnaviv_iommu_global_init(gpu); 79127b67278SLucas Stach if (ret) 792a8c21a54SThe etnaviv authors goto fail; 79327b67278SLucas Stach 79417e4660aSLucas Stach /* 795b72af445SLucas Stach * If the GPU is part of a system with DMA addressing limitations, 796b72af445SLucas Stach * request pages for our SHM backend buffers from the DMA32 zone to 797b72af445SLucas Stach * hopefully avoid performance killing SWIOTLB bounce buffering. 798b72af445SLucas Stach */ 799b72af445SLucas Stach if (dma_addressing_limited(gpu->dev)) 800b72af445SLucas Stach priv->shm_gfp_mask |= GFP_DMA32; 801b72af445SLucas Stach 802a8c21a54SThe etnaviv authors /* Create buffer: */ 803bffe5db8SLucas Stach ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, 8042f9225dbSLucas Stach PAGE_SIZE); 8052f9225dbSLucas Stach if (ret) { 806a8c21a54SThe etnaviv authors dev_err(gpu->dev, "could not create command buffer\n"); 80717e4660aSLucas Stach goto fail; 808a8c21a54SThe etnaviv authors } 809a8c21a54SThe etnaviv authors 8104bfdd2aaSLucas Stach /* 8114bfdd2aaSLucas Stach * Set the GPU linear window to cover the cmdbuf region, as the GPU 8124bfdd2aaSLucas Stach * won't be able to start execution otherwise. The alignment to 128M is 8134bfdd2aaSLucas Stach * chosen arbitrarily but helps in debugging, as the MMU offset 8144bfdd2aaSLucas Stach * calculations are much more straight forward this way. 8154bfdd2aaSLucas Stach * 8164bfdd2aaSLucas Stach * On MC1.0 cores the linear window offset is ignored by the TS engine, 8174bfdd2aaSLucas Stach * leading to inconsistent memory views. Avoid using the offset on those 8184bfdd2aaSLucas Stach * cores if possible, otherwise disable the TS feature. 8194bfdd2aaSLucas Stach */ 8204bfdd2aaSLucas Stach cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 8214bfdd2aaSLucas Stach 8224bfdd2aaSLucas Stach if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 8234bfdd2aaSLucas Stach (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 8244bfdd2aaSLucas Stach if (cmdbuf_paddr >= SZ_2G) 8254bfdd2aaSLucas Stach priv->mmu_global->memory_base = SZ_2G; 8264bfdd2aaSLucas Stach else 8274bfdd2aaSLucas Stach priv->mmu_global->memory_base = cmdbuf_paddr; 8284bfdd2aaSLucas Stach } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 8294bfdd2aaSLucas Stach dev_info(gpu->dev, 8304bfdd2aaSLucas Stach "Need to move linear window on MC1.0, disabling TS\n"); 8314bfdd2aaSLucas Stach gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 8324bfdd2aaSLucas Stach priv->mmu_global->memory_base = SZ_2G; 8334bfdd2aaSLucas Stach } 8344bfdd2aaSLucas Stach 835a8c21a54SThe etnaviv authors /* Setup event management */ 836a8c21a54SThe etnaviv authors spin_lock_init(&gpu->event_spinlock); 837a8c21a54SThe etnaviv authors init_completion(&gpu->event_free); 838355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 839355502e0SChristian Gmeiner for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 840a8c21a54SThe etnaviv authors complete(&gpu->event_free); 841a8c21a54SThe etnaviv authors 842a8c21a54SThe etnaviv authors /* Now program the hardware */ 843a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 844a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 845a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 846a8c21a54SThe etnaviv authors 847a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 848a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 849a8c21a54SThe etnaviv authors 850db41fe7dSLucas Stach gpu->initialized = true; 851db41fe7dSLucas Stach 852a8c21a54SThe etnaviv authors return 0; 853a8c21a54SThe etnaviv authors 854a8c21a54SThe etnaviv authors fail: 855a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 856c5d5a32eSNavid Emamdoost pm_put: 857a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 858a8c21a54SThe etnaviv authors 859a8c21a54SThe etnaviv authors return ret; 860a8c21a54SThe etnaviv authors } 861a8c21a54SThe etnaviv authors 862a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 863a8c21a54SThe etnaviv authors struct dma_debug { 864a8c21a54SThe etnaviv authors u32 address[2]; 865a8c21a54SThe etnaviv authors u32 state[2]; 866a8c21a54SThe etnaviv authors }; 867a8c21a54SThe etnaviv authors 868a8c21a54SThe etnaviv authors static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 869a8c21a54SThe etnaviv authors { 870a8c21a54SThe etnaviv authors u32 i; 871a8c21a54SThe etnaviv authors 872a8c21a54SThe etnaviv authors debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 873a8c21a54SThe etnaviv authors debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 874a8c21a54SThe etnaviv authors 875a8c21a54SThe etnaviv authors for (i = 0; i < 500; i++) { 876a8c21a54SThe etnaviv authors debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 877a8c21a54SThe etnaviv authors debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 878a8c21a54SThe etnaviv authors 879a8c21a54SThe etnaviv authors if (debug->address[0] != debug->address[1]) 880a8c21a54SThe etnaviv authors break; 881a8c21a54SThe etnaviv authors 882a8c21a54SThe etnaviv authors if (debug->state[0] != debug->state[1]) 883a8c21a54SThe etnaviv authors break; 884a8c21a54SThe etnaviv authors } 885a8c21a54SThe etnaviv authors } 886a8c21a54SThe etnaviv authors 887a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 888a8c21a54SThe etnaviv authors { 889a8c21a54SThe etnaviv authors struct dma_debug debug; 890a8c21a54SThe etnaviv authors u32 dma_lo, dma_hi, axi, idle; 891a8c21a54SThe etnaviv authors int ret; 892a8c21a54SThe etnaviv authors 893a8c21a54SThe etnaviv authors seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 894a8c21a54SThe etnaviv authors 895a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 896a8c21a54SThe etnaviv authors if (ret < 0) 897c5d5a32eSNavid Emamdoost goto pm_put; 898a8c21a54SThe etnaviv authors 899a8c21a54SThe etnaviv authors dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 900a8c21a54SThe etnaviv authors dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 901a8c21a54SThe etnaviv authors axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 902a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 903a8c21a54SThe etnaviv authors 904a8c21a54SThe etnaviv authors verify_dma(gpu, &debug); 905a8c21a54SThe etnaviv authors 90600080663SChristian Gmeiner seq_puts(m, "\tidentity\n"); 90700080663SChristian Gmeiner seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 90800080663SChristian Gmeiner seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 90900080663SChristian Gmeiner seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 91000080663SChristian Gmeiner seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 91100080663SChristian Gmeiner seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 91200080663SChristian Gmeiner 913a8c21a54SThe etnaviv authors seq_puts(m, "\tfeatures\n"); 9143d9fc642SLucas Stach seq_printf(m, "\t major_features: 0x%08x\n", 9153d9fc642SLucas Stach gpu->identity.features); 916a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features0: 0x%08x\n", 917a8c21a54SThe etnaviv authors gpu->identity.minor_features0); 918a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features1: 0x%08x\n", 919a8c21a54SThe etnaviv authors gpu->identity.minor_features1); 920a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features2: 0x%08x\n", 921a8c21a54SThe etnaviv authors gpu->identity.minor_features2); 922a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features3: 0x%08x\n", 923a8c21a54SThe etnaviv authors gpu->identity.minor_features3); 924602eb489SRussell King seq_printf(m, "\t minor_features4: 0x%08x\n", 925602eb489SRussell King gpu->identity.minor_features4); 926602eb489SRussell King seq_printf(m, "\t minor_features5: 0x%08x\n", 927602eb489SRussell King gpu->identity.minor_features5); 9280538aaf9SLucas Stach seq_printf(m, "\t minor_features6: 0x%08x\n", 9290538aaf9SLucas Stach gpu->identity.minor_features6); 9300538aaf9SLucas Stach seq_printf(m, "\t minor_features7: 0x%08x\n", 9310538aaf9SLucas Stach gpu->identity.minor_features7); 9320538aaf9SLucas Stach seq_printf(m, "\t minor_features8: 0x%08x\n", 9330538aaf9SLucas Stach gpu->identity.minor_features8); 9340538aaf9SLucas Stach seq_printf(m, "\t minor_features9: 0x%08x\n", 9350538aaf9SLucas Stach gpu->identity.minor_features9); 9360538aaf9SLucas Stach seq_printf(m, "\t minor_features10: 0x%08x\n", 9370538aaf9SLucas Stach gpu->identity.minor_features10); 9380538aaf9SLucas Stach seq_printf(m, "\t minor_features11: 0x%08x\n", 9390538aaf9SLucas Stach gpu->identity.minor_features11); 940a8c21a54SThe etnaviv authors 941a8c21a54SThe etnaviv authors seq_puts(m, "\tspecs\n"); 942a8c21a54SThe etnaviv authors seq_printf(m, "\t stream_count: %d\n", 943a8c21a54SThe etnaviv authors gpu->identity.stream_count); 944a8c21a54SThe etnaviv authors seq_printf(m, "\t register_max: %d\n", 945a8c21a54SThe etnaviv authors gpu->identity.register_max); 946a8c21a54SThe etnaviv authors seq_printf(m, "\t thread_count: %d\n", 947a8c21a54SThe etnaviv authors gpu->identity.thread_count); 948a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_cache_size: %d\n", 949a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size); 950a8c21a54SThe etnaviv authors seq_printf(m, "\t shader_core_count: %d\n", 951a8c21a54SThe etnaviv authors gpu->identity.shader_core_count); 952a8c21a54SThe etnaviv authors seq_printf(m, "\t pixel_pipes: %d\n", 953a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes); 954a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_output_buffer_size: %d\n", 955a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size); 956a8c21a54SThe etnaviv authors seq_printf(m, "\t buffer_size: %d\n", 957a8c21a54SThe etnaviv authors gpu->identity.buffer_size); 958a8c21a54SThe etnaviv authors seq_printf(m, "\t instruction_count: %d\n", 959a8c21a54SThe etnaviv authors gpu->identity.instruction_count); 960a8c21a54SThe etnaviv authors seq_printf(m, "\t num_constants: %d\n", 961a8c21a54SThe etnaviv authors gpu->identity.num_constants); 962602eb489SRussell King seq_printf(m, "\t varyings_count: %d\n", 963602eb489SRussell King gpu->identity.varyings_count); 964a8c21a54SThe etnaviv authors 965a8c21a54SThe etnaviv authors seq_printf(m, "\taxi: 0x%08x\n", axi); 966a8c21a54SThe etnaviv authors seq_printf(m, "\tidle: 0x%08x\n", idle); 967a8c21a54SThe etnaviv authors idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 968a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 969a8c21a54SThe etnaviv authors seq_puts(m, "\t FE is not idle\n"); 970a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 971a8c21a54SThe etnaviv authors seq_puts(m, "\t DE is not idle\n"); 972a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 973a8c21a54SThe etnaviv authors seq_puts(m, "\t PE is not idle\n"); 974a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 975a8c21a54SThe etnaviv authors seq_puts(m, "\t SH is not idle\n"); 976a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 977a8c21a54SThe etnaviv authors seq_puts(m, "\t PA is not idle\n"); 978a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 979a8c21a54SThe etnaviv authors seq_puts(m, "\t SE is not idle\n"); 980a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 981a8c21a54SThe etnaviv authors seq_puts(m, "\t RA is not idle\n"); 982a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 983a8c21a54SThe etnaviv authors seq_puts(m, "\t TX is not idle\n"); 984a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 985a8c21a54SThe etnaviv authors seq_puts(m, "\t VG is not idle\n"); 986a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 987a8c21a54SThe etnaviv authors seq_puts(m, "\t IM is not idle\n"); 988a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 989a8c21a54SThe etnaviv authors seq_puts(m, "\t FP is not idle\n"); 990a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 991a8c21a54SThe etnaviv authors seq_puts(m, "\t TS is not idle\n"); 992b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 993b1704551SGuido Günther seq_puts(m, "\t BL is not idle\n"); 994b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 995b1704551SGuido Günther seq_puts(m, "\t ASYNCFE is not idle\n"); 996b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 997b1704551SGuido Günther seq_puts(m, "\t MC is not idle\n"); 998b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 999b1704551SGuido Günther seq_puts(m, "\t PPA is not idle\n"); 1000b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 1001b1704551SGuido Günther seq_puts(m, "\t WD is not idle\n"); 1002b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 1003b1704551SGuido Günther seq_puts(m, "\t NN is not idle\n"); 1004b1704551SGuido Günther if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 1005b1704551SGuido Günther seq_puts(m, "\t TP is not idle\n"); 1006a8c21a54SThe etnaviv authors if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 1007a8c21a54SThe etnaviv authors seq_puts(m, "\t AXI low power mode\n"); 1008a8c21a54SThe etnaviv authors 1009a8c21a54SThe etnaviv authors if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1010a8c21a54SThe etnaviv authors u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1011a8c21a54SThe etnaviv authors u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1012a8c21a54SThe etnaviv authors u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1013a8c21a54SThe etnaviv authors 1014a8c21a54SThe etnaviv authors seq_puts(m, "\tMC\n"); 1015a8c21a54SThe etnaviv authors seq_printf(m, "\t read0: 0x%08x\n", read0); 1016a8c21a54SThe etnaviv authors seq_printf(m, "\t read1: 0x%08x\n", read1); 1017a8c21a54SThe etnaviv authors seq_printf(m, "\t write: 0x%08x\n", write); 1018a8c21a54SThe etnaviv authors } 1019a8c21a54SThe etnaviv authors 1020a8c21a54SThe etnaviv authors seq_puts(m, "\tDMA "); 1021a8c21a54SThe etnaviv authors 1022a8c21a54SThe etnaviv authors if (debug.address[0] == debug.address[1] && 1023a8c21a54SThe etnaviv authors debug.state[0] == debug.state[1]) { 1024a8c21a54SThe etnaviv authors seq_puts(m, "seems to be stuck\n"); 1025a8c21a54SThe etnaviv authors } else if (debug.address[0] == debug.address[1]) { 1026c01e0159SMasanari Iida seq_puts(m, "address is constant\n"); 1027a8c21a54SThe etnaviv authors } else { 1028c01e0159SMasanari Iida seq_puts(m, "is running\n"); 1029a8c21a54SThe etnaviv authors } 1030a8c21a54SThe etnaviv authors 1031a8c21a54SThe etnaviv authors seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1032a8c21a54SThe etnaviv authors seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1033a8c21a54SThe etnaviv authors seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1034a8c21a54SThe etnaviv authors seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1035a8c21a54SThe etnaviv authors seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1036a8c21a54SThe etnaviv authors dma_lo, dma_hi); 1037a8c21a54SThe etnaviv authors 1038a8c21a54SThe etnaviv authors ret = 0; 1039a8c21a54SThe etnaviv authors 1040a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1041c5d5a32eSNavid Emamdoost pm_put: 1042a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1043a8c21a54SThe etnaviv authors 1044a8c21a54SThe etnaviv authors return ret; 1045a8c21a54SThe etnaviv authors } 1046a8c21a54SThe etnaviv authors #endif 1047a8c21a54SThe etnaviv authors 10486d7a20c0SLucas Stach void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) 1049a8c21a54SThe etnaviv authors { 1050*749443deSYury Norov unsigned int i; 1051a8c21a54SThe etnaviv authors 10526d7a20c0SLucas Stach dev_err(gpu->dev, "recover hung GPU!\n"); 1053a8c21a54SThe etnaviv authors 1054a8c21a54SThe etnaviv authors if (pm_runtime_get_sync(gpu->dev) < 0) 1055c5d5a32eSNavid Emamdoost goto pm_put; 1056a8c21a54SThe etnaviv authors 1057a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 1058a8c21a54SThe etnaviv authors 1059a8c21a54SThe etnaviv authors etnaviv_hw_reset(gpu); 1060a8c21a54SThe etnaviv authors 1061a8c21a54SThe etnaviv authors /* complete all events, the GPU won't do it after the reset */ 10625a23144cSLucas Stach spin_lock(&gpu->event_spinlock); 1063*749443deSYury Norov for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1064a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1065355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 10665a23144cSLucas Stach spin_unlock(&gpu->event_spinlock); 1067a8c21a54SThe etnaviv authors 1068a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1069a8c21a54SThe etnaviv authors 1070a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1071a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1072c5d5a32eSNavid Emamdoost pm_put: 1073a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1074a8c21a54SThe etnaviv authors } 1075a8c21a54SThe etnaviv authors 1076a8c21a54SThe etnaviv authors /* fence object management */ 1077a8c21a54SThe etnaviv authors struct etnaviv_fence { 1078a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1079f54d1867SChris Wilson struct dma_fence base; 1080a8c21a54SThe etnaviv authors }; 1081a8c21a54SThe etnaviv authors 1082f54d1867SChris Wilson static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1083a8c21a54SThe etnaviv authors { 1084a8c21a54SThe etnaviv authors return container_of(fence, struct etnaviv_fence, base); 1085a8c21a54SThe etnaviv authors } 1086a8c21a54SThe etnaviv authors 1087f54d1867SChris Wilson static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1088a8c21a54SThe etnaviv authors { 1089a8c21a54SThe etnaviv authors return "etnaviv"; 1090a8c21a54SThe etnaviv authors } 1091a8c21a54SThe etnaviv authors 1092f54d1867SChris Wilson static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1093a8c21a54SThe etnaviv authors { 1094a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1095a8c21a54SThe etnaviv authors 1096a8c21a54SThe etnaviv authors return dev_name(f->gpu->dev); 1097a8c21a54SThe etnaviv authors } 1098a8c21a54SThe etnaviv authors 1099f54d1867SChris Wilson static bool etnaviv_fence_signaled(struct dma_fence *fence) 1100a8c21a54SThe etnaviv authors { 1101a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1102a8c21a54SThe etnaviv authors 11033283ee77SLucas Stach return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1104a8c21a54SThe etnaviv authors } 1105a8c21a54SThe etnaviv authors 1106f54d1867SChris Wilson static void etnaviv_fence_release(struct dma_fence *fence) 1107a8c21a54SThe etnaviv authors { 1108a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1109a8c21a54SThe etnaviv authors 1110a8c21a54SThe etnaviv authors kfree_rcu(f, base.rcu); 1111a8c21a54SThe etnaviv authors } 1112a8c21a54SThe etnaviv authors 1113f54d1867SChris Wilson static const struct dma_fence_ops etnaviv_fence_ops = { 1114a8c21a54SThe etnaviv authors .get_driver_name = etnaviv_fence_get_driver_name, 1115a8c21a54SThe etnaviv authors .get_timeline_name = etnaviv_fence_get_timeline_name, 1116a8c21a54SThe etnaviv authors .signaled = etnaviv_fence_signaled, 1117a8c21a54SThe etnaviv authors .release = etnaviv_fence_release, 1118a8c21a54SThe etnaviv authors }; 1119a8c21a54SThe etnaviv authors 1120f54d1867SChris Wilson static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1121a8c21a54SThe etnaviv authors { 1122a8c21a54SThe etnaviv authors struct etnaviv_fence *f; 1123a8c21a54SThe etnaviv authors 1124b27734c2SLucas Stach /* 1125b27734c2SLucas Stach * GPU lock must already be held, otherwise fence completion order might 1126b27734c2SLucas Stach * not match the seqno order assigned here. 1127b27734c2SLucas Stach */ 1128b27734c2SLucas Stach lockdep_assert_held(&gpu->lock); 1129b27734c2SLucas Stach 1130a8c21a54SThe etnaviv authors f = kzalloc(sizeof(*f), GFP_KERNEL); 1131a8c21a54SThe etnaviv authors if (!f) 1132a8c21a54SThe etnaviv authors return NULL; 1133a8c21a54SThe etnaviv authors 1134a8c21a54SThe etnaviv authors f->gpu = gpu; 1135a8c21a54SThe etnaviv authors 1136f54d1867SChris Wilson dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1137a8c21a54SThe etnaviv authors gpu->fence_context, ++gpu->next_fence); 1138a8c21a54SThe etnaviv authors 1139a8c21a54SThe etnaviv authors return &f->base; 1140a8c21a54SThe etnaviv authors } 1141a8c21a54SThe etnaviv authors 11423283ee77SLucas Stach /* returns true if fence a comes after fence b */ 11433283ee77SLucas Stach static inline bool fence_after(u32 a, u32 b) 11443283ee77SLucas Stach { 11453283ee77SLucas Stach return (s32)(a - b) > 0; 11463283ee77SLucas Stach } 11473283ee77SLucas Stach 1148a8c21a54SThe etnaviv authors /* 1149a8c21a54SThe etnaviv authors * event management: 1150a8c21a54SThe etnaviv authors */ 1151a8c21a54SThe etnaviv authors 115295a428c1SChristian Gmeiner static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 115395a428c1SChristian Gmeiner unsigned int *events) 1154a8c21a54SThe etnaviv authors { 11555a23144cSLucas Stach unsigned long timeout = msecs_to_jiffies(10 * 10000); 115695a428c1SChristian Gmeiner unsigned i, acquired = 0; 1157a8c21a54SThe etnaviv authors 115895a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 115995a428c1SChristian Gmeiner unsigned long ret; 116095a428c1SChristian Gmeiner 116195a428c1SChristian Gmeiner ret = wait_for_completion_timeout(&gpu->event_free, timeout); 116295a428c1SChristian Gmeiner 116395a428c1SChristian Gmeiner if (!ret) { 1164a8c21a54SThe etnaviv authors dev_err(gpu->dev, "wait_for_completion_timeout failed"); 116595a428c1SChristian Gmeiner goto out; 116695a428c1SChristian Gmeiner } 116795a428c1SChristian Gmeiner 116895a428c1SChristian Gmeiner acquired++; 116995a428c1SChristian Gmeiner timeout = ret; 117095a428c1SChristian Gmeiner } 1171a8c21a54SThe etnaviv authors 11725a23144cSLucas Stach spin_lock(&gpu->event_spinlock); 1173a8c21a54SThe etnaviv authors 117495a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 117595a428c1SChristian Gmeiner int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 117695a428c1SChristian Gmeiner 117795a428c1SChristian Gmeiner events[i] = event; 1178547d340dSChristian Gmeiner memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1179355502e0SChristian Gmeiner set_bit(event, gpu->event_bitmap); 1180a8c21a54SThe etnaviv authors } 1181a8c21a54SThe etnaviv authors 11825a23144cSLucas Stach spin_unlock(&gpu->event_spinlock); 1183a8c21a54SThe etnaviv authors 118495a428c1SChristian Gmeiner return 0; 118595a428c1SChristian Gmeiner 118695a428c1SChristian Gmeiner out: 118795a428c1SChristian Gmeiner for (i = 0; i < acquired; i++) 118895a428c1SChristian Gmeiner complete(&gpu->event_free); 118995a428c1SChristian Gmeiner 119095a428c1SChristian Gmeiner return -EBUSY; 1191a8c21a54SThe etnaviv authors } 1192a8c21a54SThe etnaviv authors 1193a8c21a54SThe etnaviv authors static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1194a8c21a54SThe etnaviv authors { 1195355502e0SChristian Gmeiner if (!test_bit(event, gpu->event_bitmap)) { 1196a8c21a54SThe etnaviv authors dev_warn(gpu->dev, "event %u is already marked as free", 1197a8c21a54SThe etnaviv authors event); 1198a8c21a54SThe etnaviv authors } else { 1199355502e0SChristian Gmeiner clear_bit(event, gpu->event_bitmap); 1200a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1201a8c21a54SThe etnaviv authors } 1202a8c21a54SThe etnaviv authors } 1203a8c21a54SThe etnaviv authors 1204a8c21a54SThe etnaviv authors /* 1205a8c21a54SThe etnaviv authors * Cmdstream submission/retirement: 1206a8c21a54SThe etnaviv authors */ 1207a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 120838c4a4cfSArnd Bergmann u32 id, struct drm_etnaviv_timespec *timeout) 1209a8c21a54SThe etnaviv authors { 12108bc4d885SLucas Stach struct dma_fence *fence; 1211a8c21a54SThe etnaviv authors int ret; 1212a8c21a54SThe etnaviv authors 12138bc4d885SLucas Stach /* 1214e93b6deeSLucas Stach * Look up the fence and take a reference. We might still find a fence 12158bc4d885SLucas Stach * whose refcount has already dropped to zero. dma_fence_get_rcu 12168bc4d885SLucas Stach * pretends we didn't find a fence in that case. 12178bc4d885SLucas Stach */ 1218e93b6deeSLucas Stach rcu_read_lock(); 12198bc4d885SLucas Stach fence = idr_find(&gpu->fence_idr, id); 12208bc4d885SLucas Stach if (fence) 12218bc4d885SLucas Stach fence = dma_fence_get_rcu(fence); 1222e93b6deeSLucas Stach rcu_read_unlock(); 12238bc4d885SLucas Stach 12248bc4d885SLucas Stach if (!fence) 12258bc4d885SLucas Stach return 0; 1226a8c21a54SThe etnaviv authors 1227a8c21a54SThe etnaviv authors if (!timeout) { 1228a8c21a54SThe etnaviv authors /* No timeout was requested: just test for completion */ 12298bc4d885SLucas Stach ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1230a8c21a54SThe etnaviv authors } else { 1231a8c21a54SThe etnaviv authors unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1232a8c21a54SThe etnaviv authors 12338bc4d885SLucas Stach ret = dma_fence_wait_timeout(fence, true, remaining); 12348bc4d885SLucas Stach if (ret == 0) 1235a8c21a54SThe etnaviv authors ret = -ETIMEDOUT; 12368bc4d885SLucas Stach else if (ret != -ERESTARTSYS) 1237a8c21a54SThe etnaviv authors ret = 0; 12388bc4d885SLucas Stach 1239a8c21a54SThe etnaviv authors } 1240a8c21a54SThe etnaviv authors 12418bc4d885SLucas Stach dma_fence_put(fence); 1242a8c21a54SThe etnaviv authors return ret; 1243a8c21a54SThe etnaviv authors } 1244a8c21a54SThe etnaviv authors 1245a8c21a54SThe etnaviv authors /* 1246a8c21a54SThe etnaviv authors * Wait for an object to become inactive. This, on it's own, is not race 1247e93b6deeSLucas Stach * free: the object is moved by the scheduler off the active list, and 1248a8c21a54SThe etnaviv authors * then the iova is put. Moreover, the object could be re-submitted just 1249a8c21a54SThe etnaviv authors * after we notice that it's become inactive. 1250a8c21a54SThe etnaviv authors * 1251a8c21a54SThe etnaviv authors * Although the retirement happens under the gpu lock, we don't want to hold 1252a8c21a54SThe etnaviv authors * that lock in this function while waiting. 1253a8c21a54SThe etnaviv authors */ 1254a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 125538c4a4cfSArnd Bergmann struct etnaviv_gem_object *etnaviv_obj, 125638c4a4cfSArnd Bergmann struct drm_etnaviv_timespec *timeout) 1257a8c21a54SThe etnaviv authors { 1258a8c21a54SThe etnaviv authors unsigned long remaining; 1259a8c21a54SThe etnaviv authors long ret; 1260a8c21a54SThe etnaviv authors 1261a8c21a54SThe etnaviv authors if (!timeout) 1262a8c21a54SThe etnaviv authors return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1263a8c21a54SThe etnaviv authors 1264a8c21a54SThe etnaviv authors remaining = etnaviv_timeout_to_jiffies(timeout); 1265a8c21a54SThe etnaviv authors 1266a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1267a8c21a54SThe etnaviv authors !is_active(etnaviv_obj), 1268a8c21a54SThe etnaviv authors remaining); 1269fa67ac84SLucas Stach if (ret > 0) 1270a8c21a54SThe etnaviv authors return 0; 1271fa67ac84SLucas Stach else if (ret == -ERESTARTSYS) 1272a8c21a54SThe etnaviv authors return -ERESTARTSYS; 1273fa67ac84SLucas Stach else 1274a8c21a54SThe etnaviv authors return -ETIMEDOUT; 1275a8c21a54SThe etnaviv authors } 1276a8c21a54SThe etnaviv authors 127768dc0b29SChristian Gmeiner static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 127868dc0b29SChristian Gmeiner struct etnaviv_event *event, unsigned int flags) 127968dc0b29SChristian Gmeiner { 1280ef146c00SLucas Stach const struct etnaviv_gem_submit *submit = event->submit; 128168dc0b29SChristian Gmeiner unsigned int i; 128268dc0b29SChristian Gmeiner 1283ef146c00SLucas Stach for (i = 0; i < submit->nr_pmrs; i++) { 1284ef146c00SLucas Stach const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 128568dc0b29SChristian Gmeiner 128668dc0b29SChristian Gmeiner if (pmr->flags == flags) 12877a9c0fe2SLucas Stach etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 128868dc0b29SChristian Gmeiner } 128968dc0b29SChristian Gmeiner } 129068dc0b29SChristian Gmeiner 129168dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 129268dc0b29SChristian Gmeiner struct etnaviv_event *event) 129368dc0b29SChristian Gmeiner { 12942c8b0c5aSChristian Gmeiner u32 val; 12952c8b0c5aSChristian Gmeiner 12962c8b0c5aSChristian Gmeiner /* disable clock gating */ 12972c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 12982c8b0c5aSChristian Gmeiner val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 12992c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 13002c8b0c5aSChristian Gmeiner 130104a7d18dSChristian Gmeiner /* enable debug register */ 130204a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 130304a7d18dSChristian Gmeiner val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 130404a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 130504a7d18dSChristian Gmeiner 130668dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 130768dc0b29SChristian Gmeiner } 130868dc0b29SChristian Gmeiner 130968dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 131068dc0b29SChristian Gmeiner struct etnaviv_event *event) 131168dc0b29SChristian Gmeiner { 1312ef146c00SLucas Stach const struct etnaviv_gem_submit *submit = event->submit; 131368dc0b29SChristian Gmeiner unsigned int i; 13142c8b0c5aSChristian Gmeiner u32 val; 131568dc0b29SChristian Gmeiner 131668dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 131768dc0b29SChristian Gmeiner 1318ef146c00SLucas Stach for (i = 0; i < submit->nr_pmrs; i++) { 1319ef146c00SLucas Stach const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 132068dc0b29SChristian Gmeiner 132168dc0b29SChristian Gmeiner *pmr->bo_vma = pmr->sequence; 132268dc0b29SChristian Gmeiner } 13232c8b0c5aSChristian Gmeiner 132404a7d18dSChristian Gmeiner /* disable debug register */ 132504a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 132604a7d18dSChristian Gmeiner val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 132704a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 132804a7d18dSChristian Gmeiner 13292c8b0c5aSChristian Gmeiner /* enable clock gating */ 13302c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 13312c8b0c5aSChristian Gmeiner val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 13322c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 133368dc0b29SChristian Gmeiner } 133468dc0b29SChristian Gmeiner 133568dc0b29SChristian Gmeiner 1336a8c21a54SThe etnaviv authors /* add bo's to gpu's ring, and kick gpu: */ 1337e93b6deeSLucas Stach struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1338a8c21a54SThe etnaviv authors { 1339e93b6deeSLucas Stach struct etnaviv_gpu *gpu = submit->gpu; 1340e93b6deeSLucas Stach struct dma_fence *gpu_fence; 134168dc0b29SChristian Gmeiner unsigned int i, nr_events = 1, event[3]; 1342a8c21a54SThe etnaviv authors int ret; 1343a8c21a54SThe etnaviv authors 13446d7a20c0SLucas Stach if (!submit->runtime_resumed) { 13458bda1516SLucas Stach ret = pm_runtime_get_sync(gpu->dev); 1346c5d5a32eSNavid Emamdoost if (ret < 0) { 1347c5d5a32eSNavid Emamdoost pm_runtime_put_noidle(gpu->dev); 1348e93b6deeSLucas Stach return NULL; 1349c5d5a32eSNavid Emamdoost } 13508bda1516SLucas Stach submit->runtime_resumed = true; 13516d7a20c0SLucas Stach } 1352a8c21a54SThe etnaviv authors 1353a8c21a54SThe etnaviv authors /* 135468dc0b29SChristian Gmeiner * if there are performance monitor requests we need to have 135568dc0b29SChristian Gmeiner * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 135668dc0b29SChristian Gmeiner * requests. 135768dc0b29SChristian Gmeiner * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 135868dc0b29SChristian Gmeiner * and update the sequence number for userspace. 135968dc0b29SChristian Gmeiner */ 1360ef146c00SLucas Stach if (submit->nr_pmrs) 136168dc0b29SChristian Gmeiner nr_events = 3; 136268dc0b29SChristian Gmeiner 136368dc0b29SChristian Gmeiner ret = event_alloc(gpu, nr_events, event); 136495a428c1SChristian Gmeiner if (ret) { 136568dc0b29SChristian Gmeiner DRM_ERROR("no free events\n"); 1366c5d5a32eSNavid Emamdoost pm_runtime_put_noidle(gpu->dev); 1367e93b6deeSLucas Stach return NULL; 1368a8c21a54SThe etnaviv authors } 1369a8c21a54SThe etnaviv authors 1370f3cd1b06SLucas Stach mutex_lock(&gpu->lock); 1371f3cd1b06SLucas Stach 1372e93b6deeSLucas Stach gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1373e93b6deeSLucas Stach if (!gpu_fence) { 137468dc0b29SChristian Gmeiner for (i = 0; i < nr_events; i++) 137568dc0b29SChristian Gmeiner event_free(gpu, event[i]); 137668dc0b29SChristian Gmeiner 137745abdf35SWei Yongjun goto out_unlock; 1378a8c21a54SThe etnaviv authors } 1379a8c21a54SThe etnaviv authors 1380d6408538SLucas Stach if (!gpu->fe_running) 1381d6408538SLucas Stach etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); 1382d6408538SLucas Stach 1383cda75329SLucas Stach if (submit->prev_mmu_context) 1384cda75329SLucas Stach etnaviv_iommu_context_put(submit->prev_mmu_context); 138578edefc0SLucas Stach submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); 138617e4660aSLucas Stach 1387ef146c00SLucas Stach if (submit->nr_pmrs) { 138868dc0b29SChristian Gmeiner gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1389ef146c00SLucas Stach kref_get(&submit->refcount); 1390ef146c00SLucas Stach gpu->event[event[1]].submit = submit; 139168dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[1]); 139268dc0b29SChristian Gmeiner } 139368dc0b29SChristian Gmeiner 1394e93b6deeSLucas Stach gpu->event[event[0]].fence = gpu_fence; 13956d7a20c0SLucas Stach submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 139617e4660aSLucas Stach etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 139717e4660aSLucas Stach event[0], &submit->cmdbuf); 139868dc0b29SChristian Gmeiner 1399ef146c00SLucas Stach if (submit->nr_pmrs) { 140068dc0b29SChristian Gmeiner gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1401ef146c00SLucas Stach kref_get(&submit->refcount); 1402ef146c00SLucas Stach gpu->event[event[2]].submit = submit; 140368dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[2]); 140468dc0b29SChristian Gmeiner } 1405a8c21a54SThe etnaviv authors 140645abdf35SWei Yongjun out_unlock: 1407a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1408a8c21a54SThe etnaviv authors 1409e93b6deeSLucas Stach return gpu_fence; 1410a8c21a54SThe etnaviv authors } 1411a8c21a54SThe etnaviv authors 1412357713ceSChristian Gmeiner static void sync_point_worker(struct work_struct *work) 1413357713ceSChristian Gmeiner { 1414357713ceSChristian Gmeiner struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1415357713ceSChristian Gmeiner sync_point_work); 1416b9a48aa7SLucas Stach struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1417b9a48aa7SLucas Stach u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1418357713ceSChristian Gmeiner 1419b9a48aa7SLucas Stach event->sync_point(gpu, event); 1420ef146c00SLucas Stach etnaviv_submit_put(event->submit); 1421357713ceSChristian Gmeiner event_free(gpu, gpu->sync_point_event); 1422b9a48aa7SLucas Stach 1423b9a48aa7SLucas Stach /* restart FE last to avoid GPU and IRQ racing against this worker */ 1424b9a48aa7SLucas Stach etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1425357713ceSChristian Gmeiner } 1426357713ceSChristian Gmeiner 14274df3000eSLucas Stach static void dump_mmu_fault(struct etnaviv_gpu *gpu) 14284df3000eSLucas Stach { 1429c997c3dfSLucas Stach u32 status_reg, status; 14304df3000eSLucas Stach int i; 14314df3000eSLucas Stach 1432c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_NONE) 1433c997c3dfSLucas Stach status_reg = VIVS_MMUv2_STATUS; 1434c997c3dfSLucas Stach else 1435c997c3dfSLucas Stach status_reg = VIVS_MMUv2_SEC_STATUS; 1436c997c3dfSLucas Stach 1437c997c3dfSLucas Stach status = gpu_read(gpu, status_reg); 14384df3000eSLucas Stach dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 14394df3000eSLucas Stach 14404df3000eSLucas Stach for (i = 0; i < 4; i++) { 1441c997c3dfSLucas Stach u32 address_reg; 1442c997c3dfSLucas Stach 14434df3000eSLucas Stach if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4)))) 14444df3000eSLucas Stach continue; 14454df3000eSLucas Stach 1446c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_NONE) 1447c997c3dfSLucas Stach address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1448c997c3dfSLucas Stach else 1449c997c3dfSLucas Stach address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1450c997c3dfSLucas Stach 14514df3000eSLucas Stach dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, 1452c997c3dfSLucas Stach gpu_read(gpu, address_reg)); 14534df3000eSLucas Stach } 14544df3000eSLucas Stach } 14554df3000eSLucas Stach 1456a8c21a54SThe etnaviv authors static irqreturn_t irq_handler(int irq, void *data) 1457a8c21a54SThe etnaviv authors { 1458a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = data; 1459a8c21a54SThe etnaviv authors irqreturn_t ret = IRQ_NONE; 1460a8c21a54SThe etnaviv authors 1461a8c21a54SThe etnaviv authors u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1462a8c21a54SThe etnaviv authors 1463a8c21a54SThe etnaviv authors if (intr != 0) { 1464a8c21a54SThe etnaviv authors int event; 1465a8c21a54SThe etnaviv authors 1466a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1467a8c21a54SThe etnaviv authors 1468a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1469a8c21a54SThe etnaviv authors 1470a8c21a54SThe etnaviv authors if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1471a8c21a54SThe etnaviv authors dev_err(gpu->dev, "AXI bus error\n"); 1472a8c21a54SThe etnaviv authors intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1473a8c21a54SThe etnaviv authors } 1474a8c21a54SThe etnaviv authors 1475128a9b1dSLucas Stach if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 14764df3000eSLucas Stach dump_mmu_fault(gpu); 1477128a9b1dSLucas Stach intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1478128a9b1dSLucas Stach } 1479128a9b1dSLucas Stach 1480a8c21a54SThe etnaviv authors while ((event = ffs(intr)) != 0) { 1481f54d1867SChris Wilson struct dma_fence *fence; 1482a8c21a54SThe etnaviv authors 1483a8c21a54SThe etnaviv authors event -= 1; 1484a8c21a54SThe etnaviv authors 1485a8c21a54SThe etnaviv authors intr &= ~(1 << event); 1486a8c21a54SThe etnaviv authors 1487a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "event %u\n", event); 1488a8c21a54SThe etnaviv authors 1489357713ceSChristian Gmeiner if (gpu->event[event].sync_point) { 1490357713ceSChristian Gmeiner gpu->sync_point_event = event; 1491a7790d78SLucas Stach queue_work(gpu->wq, &gpu->sync_point_work); 1492357713ceSChristian Gmeiner } 1493357713ceSChristian Gmeiner 1494a8c21a54SThe etnaviv authors fence = gpu->event[event].fence; 149568dc0b29SChristian Gmeiner if (!fence) 149668dc0b29SChristian Gmeiner continue; 149768dc0b29SChristian Gmeiner 1498a8c21a54SThe etnaviv authors gpu->event[event].fence = NULL; 1499a8c21a54SThe etnaviv authors 1500a8c21a54SThe etnaviv authors /* 1501a8c21a54SThe etnaviv authors * Events can be processed out of order. Eg, 1502a8c21a54SThe etnaviv authors * - allocate and queue event 0 1503a8c21a54SThe etnaviv authors * - allocate event 1 1504a8c21a54SThe etnaviv authors * - event 0 completes, we process it 1505a8c21a54SThe etnaviv authors * - allocate and queue event 0 1506a8c21a54SThe etnaviv authors * - event 1 and event 0 complete 1507a8c21a54SThe etnaviv authors * we can end up processing event 0 first, then 1. 1508a8c21a54SThe etnaviv authors */ 1509a8c21a54SThe etnaviv authors if (fence_after(fence->seqno, gpu->completed_fence)) 1510a8c21a54SThe etnaviv authors gpu->completed_fence = fence->seqno; 15118bc4d885SLucas Stach dma_fence_signal(fence); 1512a8c21a54SThe etnaviv authors 1513a8c21a54SThe etnaviv authors event_free(gpu, event); 1514a8c21a54SThe etnaviv authors } 1515a8c21a54SThe etnaviv authors 1516a8c21a54SThe etnaviv authors ret = IRQ_HANDLED; 1517a8c21a54SThe etnaviv authors } 1518a8c21a54SThe etnaviv authors 1519a8c21a54SThe etnaviv authors return ret; 1520a8c21a54SThe etnaviv authors } 1521a8c21a54SThe etnaviv authors 1522a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1523a8c21a54SThe etnaviv authors { 1524a8c21a54SThe etnaviv authors int ret; 1525a8c21a54SThe etnaviv authors 152665f037e8SLucas Stach ret = clk_prepare_enable(gpu->clk_reg); 152765f037e8SLucas Stach if (ret) 152865f037e8SLucas Stach return ret; 152965f037e8SLucas Stach 15309c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_bus); 1531a8c21a54SThe etnaviv authors if (ret) 1532f8794feaSLubomir Rintel goto disable_clk_reg; 1533a8c21a54SThe etnaviv authors 15349c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_core); 15359c7310c0SLucas Stach if (ret) 15369c7310c0SLucas Stach goto disable_clk_bus; 15379c7310c0SLucas Stach 15389c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_shader); 15399c7310c0SLucas Stach if (ret) 15409c7310c0SLucas Stach goto disable_clk_core; 15419c7310c0SLucas Stach 1542a8c21a54SThe etnaviv authors return 0; 15439c7310c0SLucas Stach 15449c7310c0SLucas Stach disable_clk_core: 15459c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 15469c7310c0SLucas Stach disable_clk_bus: 15479c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 1548f8794feaSLubomir Rintel disable_clk_reg: 1549f8794feaSLubomir Rintel clk_disable_unprepare(gpu->clk_reg); 15509c7310c0SLucas Stach 15519c7310c0SLucas Stach return ret; 1552a8c21a54SThe etnaviv authors } 1553a8c21a54SThe etnaviv authors 1554a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1555a8c21a54SThe etnaviv authors { 15569c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_shader); 15579c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 15589c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 155965f037e8SLucas Stach clk_disable_unprepare(gpu->clk_reg); 1560a8c21a54SThe etnaviv authors 1561a8c21a54SThe etnaviv authors return 0; 1562a8c21a54SThe etnaviv authors } 1563a8c21a54SThe etnaviv authors 1564b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1565b88163e3SLucas Stach { 1566b88163e3SLucas Stach unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1567b88163e3SLucas Stach 1568b88163e3SLucas Stach do { 1569b88163e3SLucas Stach u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1570b88163e3SLucas Stach 1571b88163e3SLucas Stach if ((idle & gpu->idle_mask) == gpu->idle_mask) 1572b88163e3SLucas Stach return 0; 1573b88163e3SLucas Stach 1574b88163e3SLucas Stach if (time_is_before_jiffies(timeout)) { 1575b88163e3SLucas Stach dev_warn(gpu->dev, 1576b88163e3SLucas Stach "timed out waiting for idle: idle=0x%x\n", 1577b88163e3SLucas Stach idle); 1578b88163e3SLucas Stach return -ETIMEDOUT; 1579b88163e3SLucas Stach } 1580b88163e3SLucas Stach 1581b88163e3SLucas Stach udelay(5); 1582b88163e3SLucas Stach } while (1); 1583b88163e3SLucas Stach } 1584b88163e3SLucas Stach 1585a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1586a8c21a54SThe etnaviv authors { 158723e0f5a5SLucas Stach if (gpu->initialized && gpu->fe_running) { 1588a8c21a54SThe etnaviv authors /* Replace the last WAIT with END */ 158940c27bdeSLucas Stach mutex_lock(&gpu->lock); 1590a8c21a54SThe etnaviv authors etnaviv_buffer_end(gpu); 159140c27bdeSLucas Stach mutex_unlock(&gpu->lock); 1592a8c21a54SThe etnaviv authors 1593a8c21a54SThe etnaviv authors /* 1594a8c21a54SThe etnaviv authors * We know that only the FE is busy here, this should 1595a8c21a54SThe etnaviv authors * happen quickly (as the WAIT is only 200 cycles). If 1596a8c21a54SThe etnaviv authors * we fail, just warn and continue. 1597a8c21a54SThe etnaviv authors */ 1598b88163e3SLucas Stach etnaviv_gpu_wait_idle(gpu, 100); 159917e4660aSLucas Stach 160023e0f5a5SLucas Stach gpu->fe_running = false; 1601a8c21a54SThe etnaviv authors } 1602a8c21a54SThe etnaviv authors 160317e4660aSLucas Stach gpu->exec_state = -1; 160417e4660aSLucas Stach 1605a8c21a54SThe etnaviv authors return etnaviv_gpu_clk_disable(gpu); 1606a8c21a54SThe etnaviv authors } 1607a8c21a54SThe etnaviv authors 1608a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1609a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1610a8c21a54SThe etnaviv authors { 1611a8c21a54SThe etnaviv authors int ret; 1612a8c21a54SThe etnaviv authors 1613a8c21a54SThe etnaviv authors ret = mutex_lock_killable(&gpu->lock); 1614a8c21a54SThe etnaviv authors if (ret) 1615a8c21a54SThe etnaviv authors return ret; 1616a8c21a54SThe etnaviv authors 1617bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1618a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1619a8c21a54SThe etnaviv authors 1620a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1621a8c21a54SThe etnaviv authors 1622a8c21a54SThe etnaviv authors return 0; 1623a8c21a54SThe etnaviv authors } 1624a8c21a54SThe etnaviv authors #endif 1625a8c21a54SThe etnaviv authors 1626bcdfb5e5SRussell King static int 1627bcdfb5e5SRussell King etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1628bcdfb5e5SRussell King unsigned long *state) 1629bcdfb5e5SRussell King { 1630bcdfb5e5SRussell King *state = 6; 1631bcdfb5e5SRussell King 1632bcdfb5e5SRussell King return 0; 1633bcdfb5e5SRussell King } 1634bcdfb5e5SRussell King 1635bcdfb5e5SRussell King static int 1636bcdfb5e5SRussell King etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1637bcdfb5e5SRussell King unsigned long *state) 1638bcdfb5e5SRussell King { 1639bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1640bcdfb5e5SRussell King 1641bcdfb5e5SRussell King *state = gpu->freq_scale; 1642bcdfb5e5SRussell King 1643bcdfb5e5SRussell King return 0; 1644bcdfb5e5SRussell King } 1645bcdfb5e5SRussell King 1646bcdfb5e5SRussell King static int 1647bcdfb5e5SRussell King etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1648bcdfb5e5SRussell King unsigned long state) 1649bcdfb5e5SRussell King { 1650bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1651bcdfb5e5SRussell King 1652bcdfb5e5SRussell King mutex_lock(&gpu->lock); 1653bcdfb5e5SRussell King gpu->freq_scale = state; 1654bcdfb5e5SRussell King if (!pm_runtime_suspended(gpu->dev)) 1655bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1656bcdfb5e5SRussell King mutex_unlock(&gpu->lock); 1657bcdfb5e5SRussell King 1658bcdfb5e5SRussell King return 0; 1659bcdfb5e5SRussell King } 1660bcdfb5e5SRussell King 1661bcdfb5e5SRussell King static struct thermal_cooling_device_ops cooling_ops = { 1662bcdfb5e5SRussell King .get_max_state = etnaviv_gpu_cooling_get_max_state, 1663bcdfb5e5SRussell King .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1664bcdfb5e5SRussell King .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1665bcdfb5e5SRussell King }; 1666bcdfb5e5SRussell King 1667a8c21a54SThe etnaviv authors static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1668a8c21a54SThe etnaviv authors void *data) 1669a8c21a54SThe etnaviv authors { 1670a8c21a54SThe etnaviv authors struct drm_device *drm = data; 1671a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = drm->dev_private; 1672a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1673a8c21a54SThe etnaviv authors int ret; 1674a8c21a54SThe etnaviv authors 167549b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1676bcdfb5e5SRussell King gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1677bcdfb5e5SRussell King (char *)dev_name(dev), gpu, &cooling_ops); 1678bcdfb5e5SRussell King if (IS_ERR(gpu->cooling)) 1679bcdfb5e5SRussell King return PTR_ERR(gpu->cooling); 16805247e2aaSLucas Stach } 1681bcdfb5e5SRussell King 1682a7790d78SLucas Stach gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1683a7790d78SLucas Stach if (!gpu->wq) { 1684e93b6deeSLucas Stach ret = -ENOMEM; 1685e93b6deeSLucas Stach goto out_thermal; 1686a7790d78SLucas Stach } 1687a7790d78SLucas Stach 1688e93b6deeSLucas Stach ret = etnaviv_sched_init(gpu); 1689e93b6deeSLucas Stach if (ret) 1690e93b6deeSLucas Stach goto out_workqueue; 1691e93b6deeSLucas Stach 1692a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1693a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 1694a8c21a54SThe etnaviv authors #else 1695a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1696a8c21a54SThe etnaviv authors #endif 1697e93b6deeSLucas Stach if (ret < 0) 1698e93b6deeSLucas Stach goto out_sched; 1699e93b6deeSLucas Stach 1700a8c21a54SThe etnaviv authors 1701a8c21a54SThe etnaviv authors gpu->drm = drm; 1702f54d1867SChris Wilson gpu->fence_context = dma_fence_context_alloc(1); 17038bc4d885SLucas Stach idr_init(&gpu->fence_idr); 1704a8c21a54SThe etnaviv authors spin_lock_init(&gpu->fence_spinlock); 1705a8c21a54SThe etnaviv authors 1706357713ceSChristian Gmeiner INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1707a8c21a54SThe etnaviv authors init_waitqueue_head(&gpu->fence_event); 1708a8c21a54SThe etnaviv authors 1709a8c21a54SThe etnaviv authors priv->gpu[priv->num_gpus++] = gpu; 1710a8c21a54SThe etnaviv authors 1711a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1712a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1713a8c21a54SThe etnaviv authors 1714a8c21a54SThe etnaviv authors return 0; 1715e93b6deeSLucas Stach 1716e93b6deeSLucas Stach out_sched: 1717e93b6deeSLucas Stach etnaviv_sched_fini(gpu); 1718e93b6deeSLucas Stach 1719e93b6deeSLucas Stach out_workqueue: 1720e93b6deeSLucas Stach destroy_workqueue(gpu->wq); 1721e93b6deeSLucas Stach 1722e93b6deeSLucas Stach out_thermal: 1723e93b6deeSLucas Stach if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1724e93b6deeSLucas Stach thermal_cooling_device_unregister(gpu->cooling); 1725e93b6deeSLucas Stach 1726e93b6deeSLucas Stach return ret; 1727a8c21a54SThe etnaviv authors } 1728a8c21a54SThe etnaviv authors 1729a8c21a54SThe etnaviv authors static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1730a8c21a54SThe etnaviv authors void *data) 1731a8c21a54SThe etnaviv authors { 1732a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1733a8c21a54SThe etnaviv authors 1734a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 1735a8c21a54SThe etnaviv authors 1736a7790d78SLucas Stach destroy_workqueue(gpu->wq); 1737a7790d78SLucas Stach 1738e93b6deeSLucas Stach etnaviv_sched_fini(gpu); 1739e93b6deeSLucas Stach 1740a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1741a8c21a54SThe etnaviv authors pm_runtime_get_sync(gpu->dev); 1742a8c21a54SThe etnaviv authors pm_runtime_put_sync_suspend(gpu->dev); 1743a8c21a54SThe etnaviv authors #else 1744a8c21a54SThe etnaviv authors etnaviv_gpu_hw_suspend(gpu); 1745a8c21a54SThe etnaviv authors #endif 1746a8c21a54SThe etnaviv authors 17478f3eea9dSLucas Stach if (gpu->mmu_context) 17488f3eea9dSLucas Stach etnaviv_iommu_context_put(gpu->mmu_context); 17498f3eea9dSLucas Stach 1750db41fe7dSLucas Stach if (gpu->initialized) { 17512f9225dbSLucas Stach etnaviv_cmdbuf_free(&gpu->buffer); 175227b67278SLucas Stach etnaviv_iommu_global_fini(gpu); 1753db41fe7dSLucas Stach gpu->initialized = false; 1754a8c21a54SThe etnaviv authors } 1755a8c21a54SThe etnaviv authors 1756a8c21a54SThe etnaviv authors gpu->drm = NULL; 17578bc4d885SLucas Stach idr_destroy(&gpu->fence_idr); 1758bcdfb5e5SRussell King 175949b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1760bcdfb5e5SRussell King thermal_cooling_device_unregister(gpu->cooling); 1761bcdfb5e5SRussell King gpu->cooling = NULL; 1762a8c21a54SThe etnaviv authors } 1763a8c21a54SThe etnaviv authors 1764a8c21a54SThe etnaviv authors static const struct component_ops gpu_ops = { 1765a8c21a54SThe etnaviv authors .bind = etnaviv_gpu_bind, 1766a8c21a54SThe etnaviv authors .unbind = etnaviv_gpu_unbind, 1767a8c21a54SThe etnaviv authors }; 1768a8c21a54SThe etnaviv authors 1769a8c21a54SThe etnaviv authors static const struct of_device_id etnaviv_gpu_match[] = { 1770a8c21a54SThe etnaviv authors { 1771a8c21a54SThe etnaviv authors .compatible = "vivante,gc" 1772a8c21a54SThe etnaviv authors }, 1773a8c21a54SThe etnaviv authors { /* sentinel */ } 1774a8c21a54SThe etnaviv authors }; 1775246774d1SLucas Stach MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1776a8c21a54SThe etnaviv authors 1777a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1778a8c21a54SThe etnaviv authors { 1779a8c21a54SThe etnaviv authors struct device *dev = &pdev->dev; 1780a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1781dc227890SFabio Estevam int err; 1782a8c21a54SThe etnaviv authors 1783a8c21a54SThe etnaviv authors gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1784a8c21a54SThe etnaviv authors if (!gpu) 1785a8c21a54SThe etnaviv authors return -ENOMEM; 1786a8c21a54SThe etnaviv authors 1787a8c21a54SThe etnaviv authors gpu->dev = &pdev->dev; 1788a8c21a54SThe etnaviv authors mutex_init(&gpu->lock); 1789a0780bb1SLucas Stach mutex_init(&gpu->fence_lock); 1790a8c21a54SThe etnaviv authors 1791a8c21a54SThe etnaviv authors /* Map registers: */ 1792facb180dSFabio Estevam gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1793a8c21a54SThe etnaviv authors if (IS_ERR(gpu->mmio)) 1794a8c21a54SThe etnaviv authors return PTR_ERR(gpu->mmio); 1795a8c21a54SThe etnaviv authors 1796a8c21a54SThe etnaviv authors /* Get Interrupt: */ 1797a8c21a54SThe etnaviv authors gpu->irq = platform_get_irq(pdev, 0); 17980e63302dSTian Tao if (gpu->irq < 0) 1799db60eda3SFabio Estevam return gpu->irq; 1800a8c21a54SThe etnaviv authors 1801a8c21a54SThe etnaviv authors err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1802a8c21a54SThe etnaviv authors dev_name(gpu->dev), gpu); 1803a8c21a54SThe etnaviv authors if (err) { 1804a8c21a54SThe etnaviv authors dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1805db60eda3SFabio Estevam return err; 1806a8c21a54SThe etnaviv authors } 1807a8c21a54SThe etnaviv authors 1808a8c21a54SThe etnaviv authors /* Get Clocks: */ 1809f76fc5ffSLubomir Rintel gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 181065f037e8SLucas Stach DBG("clk_reg: %p", gpu->clk_reg); 181165f037e8SLucas Stach if (IS_ERR(gpu->clk_reg)) 1812f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_reg); 181365f037e8SLucas Stach 1814f76fc5ffSLubomir Rintel gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1815a8c21a54SThe etnaviv authors DBG("clk_bus: %p", gpu->clk_bus); 1816a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_bus)) 1817f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_bus); 1818a8c21a54SThe etnaviv authors 1819a59052d2SLubomir Rintel gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1820a8c21a54SThe etnaviv authors DBG("clk_core: %p", gpu->clk_core); 1821a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_core)) 1822f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_core); 1823d79fd1ccSLucas Stach gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1824a8c21a54SThe etnaviv authors 1825f76fc5ffSLubomir Rintel gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1826a8c21a54SThe etnaviv authors DBG("clk_shader: %p", gpu->clk_shader); 1827a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_shader)) 1828f76fc5ffSLubomir Rintel return PTR_ERR(gpu->clk_shader); 1829d79fd1ccSLucas Stach gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1830a8c21a54SThe etnaviv authors 1831a8c21a54SThe etnaviv authors /* TODO: figure out max mapped size */ 1832a8c21a54SThe etnaviv authors dev_set_drvdata(dev, gpu); 1833a8c21a54SThe etnaviv authors 1834a8c21a54SThe etnaviv authors /* 1835a8c21a54SThe etnaviv authors * We treat the device as initially suspended. The runtime PM 1836a8c21a54SThe etnaviv authors * autosuspend delay is rather arbitary: no measurements have 1837a8c21a54SThe etnaviv authors * yet been performed to determine an appropriate value. 1838a8c21a54SThe etnaviv authors */ 1839a8c21a54SThe etnaviv authors pm_runtime_use_autosuspend(gpu->dev); 1840a8c21a54SThe etnaviv authors pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1841a8c21a54SThe etnaviv authors pm_runtime_enable(gpu->dev); 1842a8c21a54SThe etnaviv authors 1843a8c21a54SThe etnaviv authors err = component_add(&pdev->dev, &gpu_ops); 1844a8c21a54SThe etnaviv authors if (err < 0) { 1845a8c21a54SThe etnaviv authors dev_err(&pdev->dev, "failed to register component: %d\n", err); 1846db60eda3SFabio Estevam return err; 1847a8c21a54SThe etnaviv authors } 1848a8c21a54SThe etnaviv authors 1849a8c21a54SThe etnaviv authors return 0; 1850a8c21a54SThe etnaviv authors } 1851a8c21a54SThe etnaviv authors 1852a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1853a8c21a54SThe etnaviv authors { 1854a8c21a54SThe etnaviv authors component_del(&pdev->dev, &gpu_ops); 1855a8c21a54SThe etnaviv authors pm_runtime_disable(&pdev->dev); 1856a8c21a54SThe etnaviv authors return 0; 1857a8c21a54SThe etnaviv authors } 1858a8c21a54SThe etnaviv authors 1859a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1860a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_suspend(struct device *dev) 1861a8c21a54SThe etnaviv authors { 1862a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1863a8c21a54SThe etnaviv authors u32 idle, mask; 1864a8c21a54SThe etnaviv authors 1865f4163814SLucas Stach /* If there are any jobs in the HW queue, we're not idle */ 1866f4163814SLucas Stach if (atomic_read(&gpu->sched.hw_rq_count)) 1867a8c21a54SThe etnaviv authors return -EBUSY; 1868a8c21a54SThe etnaviv authors 18691a910c11SGuido Günther /* Check whether the hardware (except FE and MC) is idle */ 18701a910c11SGuido Günther mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 18711a910c11SGuido Günther VIVS_HI_IDLE_STATE_MC); 1872a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 187378f2bfa3SGuido Günther if (idle != mask) { 187478f2bfa3SGuido Günther dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 187578f2bfa3SGuido Günther idle); 1876a8c21a54SThe etnaviv authors return -EBUSY; 187778f2bfa3SGuido Günther } 1878a8c21a54SThe etnaviv authors 1879a8c21a54SThe etnaviv authors return etnaviv_gpu_hw_suspend(gpu); 1880a8c21a54SThe etnaviv authors } 1881a8c21a54SThe etnaviv authors 1882a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_resume(struct device *dev) 1883a8c21a54SThe etnaviv authors { 1884a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1885a8c21a54SThe etnaviv authors int ret; 1886a8c21a54SThe etnaviv authors 1887a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1888a8c21a54SThe etnaviv authors if (ret) 1889a8c21a54SThe etnaviv authors return ret; 1890a8c21a54SThe etnaviv authors 1891a8c21a54SThe etnaviv authors /* Re-initialise the basic hardware state */ 1892db41fe7dSLucas Stach if (gpu->drm && gpu->initialized) { 1893a8c21a54SThe etnaviv authors ret = etnaviv_gpu_hw_resume(gpu); 1894a8c21a54SThe etnaviv authors if (ret) { 1895a8c21a54SThe etnaviv authors etnaviv_gpu_clk_disable(gpu); 1896a8c21a54SThe etnaviv authors return ret; 1897a8c21a54SThe etnaviv authors } 1898a8c21a54SThe etnaviv authors } 1899a8c21a54SThe etnaviv authors 1900a8c21a54SThe etnaviv authors return 0; 1901a8c21a54SThe etnaviv authors } 1902a8c21a54SThe etnaviv authors #endif 1903a8c21a54SThe etnaviv authors 1904a8c21a54SThe etnaviv authors static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1905a8c21a54SThe etnaviv authors SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1906a8c21a54SThe etnaviv authors NULL) 1907a8c21a54SThe etnaviv authors }; 1908a8c21a54SThe etnaviv authors 1909a8c21a54SThe etnaviv authors struct platform_driver etnaviv_gpu_driver = { 1910a8c21a54SThe etnaviv authors .driver = { 1911a8c21a54SThe etnaviv authors .name = "etnaviv-gpu", 1912a8c21a54SThe etnaviv authors .owner = THIS_MODULE, 1913a8c21a54SThe etnaviv authors .pm = &etnaviv_gpu_pm_ops, 1914a8c21a54SThe etnaviv authors .of_match_table = etnaviv_gpu_match, 1915a8c21a54SThe etnaviv authors }, 1916a8c21a54SThe etnaviv authors .probe = etnaviv_gpu_platform_probe, 1917a8c21a54SThe etnaviv authors .remove = etnaviv_gpu_platform_remove, 1918a8c21a54SThe etnaviv authors .id_table = gpu_ids, 1919a8c21a54SThe etnaviv authors }; 1920