1f6ffbd4fSLucas Stach // SPDX-License-Identifier: GPL-2.0 2a8c21a54SThe etnaviv authors /* 3f6ffbd4fSLucas Stach * Copyright (C) 2015-2018 Etnaviv Project 4a8c21a54SThe etnaviv authors */ 5a8c21a54SThe etnaviv authors 6a8c21a54SThe etnaviv authors #include <linux/component.h> 7f54d1867SChris Wilson #include <linux/dma-fence.h> 8a8c21a54SThe etnaviv authors #include <linux/moduleparam.h> 9a8c21a54SThe etnaviv authors #include <linux/of_device.h> 10bcdfb5e5SRussell King #include <linux/thermal.h> 11ea1f5729SLucas Stach 12ea1f5729SLucas Stach #include "etnaviv_cmdbuf.h" 13a8c21a54SThe etnaviv authors #include "etnaviv_dump.h" 14a8c21a54SThe etnaviv authors #include "etnaviv_gpu.h" 15a8c21a54SThe etnaviv authors #include "etnaviv_gem.h" 16a8c21a54SThe etnaviv authors #include "etnaviv_mmu.h" 17357713ceSChristian Gmeiner #include "etnaviv_perfmon.h" 18e93b6deeSLucas Stach #include "etnaviv_sched.h" 19a8c21a54SThe etnaviv authors #include "common.xml.h" 20a8c21a54SThe etnaviv authors #include "state.xml.h" 21a8c21a54SThe etnaviv authors #include "state_hi.xml.h" 22a8c21a54SThe etnaviv authors #include "cmdstream.xml.h" 23a8c21a54SThe etnaviv authors 24c09d7f79SLucas Stach #ifndef PHYS_OFFSET 25c09d7f79SLucas Stach #define PHYS_OFFSET 0 26c09d7f79SLucas Stach #endif 27c09d7f79SLucas Stach 28a8c21a54SThe etnaviv authors static const struct platform_device_id gpu_ids[] = { 29a8c21a54SThe etnaviv authors { .name = "etnaviv-gpu,2d" }, 30a8c21a54SThe etnaviv authors { }, 31a8c21a54SThe etnaviv authors }; 32a8c21a54SThe etnaviv authors 33a8c21a54SThe etnaviv authors /* 34a8c21a54SThe etnaviv authors * Driver functions: 35a8c21a54SThe etnaviv authors */ 36a8c21a54SThe etnaviv authors 37a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 38a8c21a54SThe etnaviv authors { 39a8c21a54SThe etnaviv authors switch (param) { 40a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_MODEL: 41a8c21a54SThe etnaviv authors *value = gpu->identity.model; 42a8c21a54SThe etnaviv authors break; 43a8c21a54SThe etnaviv authors 44a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REVISION: 45a8c21a54SThe etnaviv authors *value = gpu->identity.revision; 46a8c21a54SThe etnaviv authors break; 47a8c21a54SThe etnaviv authors 48a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_0: 49a8c21a54SThe etnaviv authors *value = gpu->identity.features; 50a8c21a54SThe etnaviv authors break; 51a8c21a54SThe etnaviv authors 52a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_1: 53a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features0; 54a8c21a54SThe etnaviv authors break; 55a8c21a54SThe etnaviv authors 56a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_2: 57a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features1; 58a8c21a54SThe etnaviv authors break; 59a8c21a54SThe etnaviv authors 60a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_3: 61a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features2; 62a8c21a54SThe etnaviv authors break; 63a8c21a54SThe etnaviv authors 64a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_FEATURES_4: 65a8c21a54SThe etnaviv authors *value = gpu->identity.minor_features3; 66a8c21a54SThe etnaviv authors break; 67a8c21a54SThe etnaviv authors 68602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_5: 69602eb489SRussell King *value = gpu->identity.minor_features4; 70602eb489SRussell King break; 71602eb489SRussell King 72602eb489SRussell King case ETNAVIV_PARAM_GPU_FEATURES_6: 73602eb489SRussell King *value = gpu->identity.minor_features5; 74602eb489SRussell King break; 75602eb489SRussell King 760538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_7: 770538aaf9SLucas Stach *value = gpu->identity.minor_features6; 780538aaf9SLucas Stach break; 790538aaf9SLucas Stach 800538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_8: 810538aaf9SLucas Stach *value = gpu->identity.minor_features7; 820538aaf9SLucas Stach break; 830538aaf9SLucas Stach 840538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_9: 850538aaf9SLucas Stach *value = gpu->identity.minor_features8; 860538aaf9SLucas Stach break; 870538aaf9SLucas Stach 880538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_10: 890538aaf9SLucas Stach *value = gpu->identity.minor_features9; 900538aaf9SLucas Stach break; 910538aaf9SLucas Stach 920538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_11: 930538aaf9SLucas Stach *value = gpu->identity.minor_features10; 940538aaf9SLucas Stach break; 950538aaf9SLucas Stach 960538aaf9SLucas Stach case ETNAVIV_PARAM_GPU_FEATURES_12: 970538aaf9SLucas Stach *value = gpu->identity.minor_features11; 980538aaf9SLucas Stach break; 990538aaf9SLucas Stach 100a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_STREAM_COUNT: 101a8c21a54SThe etnaviv authors *value = gpu->identity.stream_count; 102a8c21a54SThe etnaviv authors break; 103a8c21a54SThe etnaviv authors 104a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_REGISTER_MAX: 105a8c21a54SThe etnaviv authors *value = gpu->identity.register_max; 106a8c21a54SThe etnaviv authors break; 107a8c21a54SThe etnaviv authors 108a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_THREAD_COUNT: 109a8c21a54SThe etnaviv authors *value = gpu->identity.thread_count; 110a8c21a54SThe etnaviv authors break; 111a8c21a54SThe etnaviv authors 112a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 113a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_cache_size; 114a8c21a54SThe etnaviv authors break; 115a8c21a54SThe etnaviv authors 116a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 117a8c21a54SThe etnaviv authors *value = gpu->identity.shader_core_count; 118a8c21a54SThe etnaviv authors break; 119a8c21a54SThe etnaviv authors 120a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 121a8c21a54SThe etnaviv authors *value = gpu->identity.pixel_pipes; 122a8c21a54SThe etnaviv authors break; 123a8c21a54SThe etnaviv authors 124a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 125a8c21a54SThe etnaviv authors *value = gpu->identity.vertex_output_buffer_size; 126a8c21a54SThe etnaviv authors break; 127a8c21a54SThe etnaviv authors 128a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 129a8c21a54SThe etnaviv authors *value = gpu->identity.buffer_size; 130a8c21a54SThe etnaviv authors break; 131a8c21a54SThe etnaviv authors 132a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 133a8c21a54SThe etnaviv authors *value = gpu->identity.instruction_count; 134a8c21a54SThe etnaviv authors break; 135a8c21a54SThe etnaviv authors 136a8c21a54SThe etnaviv authors case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 137a8c21a54SThe etnaviv authors *value = gpu->identity.num_constants; 138a8c21a54SThe etnaviv authors break; 139a8c21a54SThe etnaviv authors 140602eb489SRussell King case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 141602eb489SRussell King *value = gpu->identity.varyings_count; 142602eb489SRussell King break; 143602eb489SRussell King 144a8c21a54SThe etnaviv authors default: 145a8c21a54SThe etnaviv authors DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 146a8c21a54SThe etnaviv authors return -EINVAL; 147a8c21a54SThe etnaviv authors } 148a8c21a54SThe etnaviv authors 149a8c21a54SThe etnaviv authors return 0; 150a8c21a54SThe etnaviv authors } 151a8c21a54SThe etnaviv authors 152472f79dcSRussell King 153472f79dcSRussell King #define etnaviv_is_model_rev(gpu, mod, rev) \ 154472f79dcSRussell King ((gpu)->identity.model == chipModel_##mod && \ 155472f79dcSRussell King (gpu)->identity.revision == rev) 15652f36ba1SRussell King #define etnaviv_field(val, field) \ 15752f36ba1SRussell King (((val) & field##__MASK) >> field##__SHIFT) 15852f36ba1SRussell King 159a8c21a54SThe etnaviv authors static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 160a8c21a54SThe etnaviv authors { 161a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 162a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 163602eb489SRussell King u32 specs[4]; 164602eb489SRussell King unsigned int streams; 165a8c21a54SThe etnaviv authors 166a8c21a54SThe etnaviv authors specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 167a8c21a54SThe etnaviv authors specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 168602eb489SRussell King specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 169602eb489SRussell King specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 170a8c21a54SThe etnaviv authors 17152f36ba1SRussell King gpu->identity.stream_count = etnaviv_field(specs[0], 17252f36ba1SRussell King VIVS_HI_CHIP_SPECS_STREAM_COUNT); 17352f36ba1SRussell King gpu->identity.register_max = etnaviv_field(specs[0], 17452f36ba1SRussell King VIVS_HI_CHIP_SPECS_REGISTER_MAX); 17552f36ba1SRussell King gpu->identity.thread_count = etnaviv_field(specs[0], 17652f36ba1SRussell King VIVS_HI_CHIP_SPECS_THREAD_COUNT); 17752f36ba1SRussell King gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 17852f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 17952f36ba1SRussell King gpu->identity.shader_core_count = etnaviv_field(specs[0], 18052f36ba1SRussell King VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 18152f36ba1SRussell King gpu->identity.pixel_pipes = etnaviv_field(specs[0], 18252f36ba1SRussell King VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 183a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 18452f36ba1SRussell King etnaviv_field(specs[0], 18552f36ba1SRussell King VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 186a8c21a54SThe etnaviv authors 18752f36ba1SRussell King gpu->identity.buffer_size = etnaviv_field(specs[1], 18852f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 18952f36ba1SRussell King gpu->identity.instruction_count = etnaviv_field(specs[1], 19052f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 19152f36ba1SRussell King gpu->identity.num_constants = etnaviv_field(specs[1], 19252f36ba1SRussell King VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 193602eb489SRussell King 194602eb489SRussell King gpu->identity.varyings_count = etnaviv_field(specs[2], 195602eb489SRussell King VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 196602eb489SRussell King 197602eb489SRussell King /* This overrides the value from older register if non-zero */ 198602eb489SRussell King streams = etnaviv_field(specs[3], 199602eb489SRussell King VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 200602eb489SRussell King if (streams) 201602eb489SRussell King gpu->identity.stream_count = streams; 202a8c21a54SThe etnaviv authors } 203a8c21a54SThe etnaviv authors 204a8c21a54SThe etnaviv authors /* Fill in the stream count if not specified */ 205a8c21a54SThe etnaviv authors if (gpu->identity.stream_count == 0) { 206a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 207a8c21a54SThe etnaviv authors gpu->identity.stream_count = 4; 208a8c21a54SThe etnaviv authors else 209a8c21a54SThe etnaviv authors gpu->identity.stream_count = 1; 210a8c21a54SThe etnaviv authors } 211a8c21a54SThe etnaviv authors 212a8c21a54SThe etnaviv authors /* Convert the register max value */ 213a8c21a54SThe etnaviv authors if (gpu->identity.register_max) 214a8c21a54SThe etnaviv authors gpu->identity.register_max = 1 << gpu->identity.register_max; 215507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 216a8c21a54SThe etnaviv authors gpu->identity.register_max = 32; 217a8c21a54SThe etnaviv authors else 218a8c21a54SThe etnaviv authors gpu->identity.register_max = 64; 219a8c21a54SThe etnaviv authors 220a8c21a54SThe etnaviv authors /* Convert thread count */ 221a8c21a54SThe etnaviv authors if (gpu->identity.thread_count) 222a8c21a54SThe etnaviv authors gpu->identity.thread_count = 1 << gpu->identity.thread_count; 223507f8991SRussell King else if (gpu->identity.model == chipModel_GC400) 224a8c21a54SThe etnaviv authors gpu->identity.thread_count = 64; 225507f8991SRussell King else if (gpu->identity.model == chipModel_GC500 || 226507f8991SRussell King gpu->identity.model == chipModel_GC530) 227a8c21a54SThe etnaviv authors gpu->identity.thread_count = 128; 228a8c21a54SThe etnaviv authors else 229a8c21a54SThe etnaviv authors gpu->identity.thread_count = 256; 230a8c21a54SThe etnaviv authors 231a8c21a54SThe etnaviv authors if (gpu->identity.vertex_cache_size == 0) 232a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size = 8; 233a8c21a54SThe etnaviv authors 234a8c21a54SThe etnaviv authors if (gpu->identity.shader_core_count == 0) { 235a8c21a54SThe etnaviv authors if (gpu->identity.model >= 0x1000) 236a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 2; 237a8c21a54SThe etnaviv authors else 238a8c21a54SThe etnaviv authors gpu->identity.shader_core_count = 1; 239a8c21a54SThe etnaviv authors } 240a8c21a54SThe etnaviv authors 241a8c21a54SThe etnaviv authors if (gpu->identity.pixel_pipes == 0) 242a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes = 1; 243a8c21a54SThe etnaviv authors 244a8c21a54SThe etnaviv authors /* Convert virtex buffer size */ 245a8c21a54SThe etnaviv authors if (gpu->identity.vertex_output_buffer_size) { 246a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 247a8c21a54SThe etnaviv authors 1 << gpu->identity.vertex_output_buffer_size; 248507f8991SRussell King } else if (gpu->identity.model == chipModel_GC400) { 249a8c21a54SThe etnaviv authors if (gpu->identity.revision < 0x4000) 250a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 251a8c21a54SThe etnaviv authors else if (gpu->identity.revision < 0x4200) 252a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 256; 253a8c21a54SThe etnaviv authors else 254a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 128; 255a8c21a54SThe etnaviv authors } else { 256a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size = 512; 257a8c21a54SThe etnaviv authors } 258a8c21a54SThe etnaviv authors 259a8c21a54SThe etnaviv authors switch (gpu->identity.instruction_count) { 260a8c21a54SThe etnaviv authors case 0: 261472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 262507f8991SRussell King gpu->identity.model == chipModel_GC880) 263a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 512; 264a8c21a54SThe etnaviv authors else 265a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 266a8c21a54SThe etnaviv authors break; 267a8c21a54SThe etnaviv authors 268a8c21a54SThe etnaviv authors case 1: 269a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 1024; 270a8c21a54SThe etnaviv authors break; 271a8c21a54SThe etnaviv authors 272a8c21a54SThe etnaviv authors case 2: 273a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 2048; 274a8c21a54SThe etnaviv authors break; 275a8c21a54SThe etnaviv authors 276a8c21a54SThe etnaviv authors default: 277a8c21a54SThe etnaviv authors gpu->identity.instruction_count = 256; 278a8c21a54SThe etnaviv authors break; 279a8c21a54SThe etnaviv authors } 280a8c21a54SThe etnaviv authors 281a8c21a54SThe etnaviv authors if (gpu->identity.num_constants == 0) 282a8c21a54SThe etnaviv authors gpu->identity.num_constants = 168; 283602eb489SRussell King 284602eb489SRussell King if (gpu->identity.varyings_count == 0) { 285602eb489SRussell King if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 286602eb489SRussell King gpu->identity.varyings_count = 12; 287602eb489SRussell King else 288602eb489SRussell King gpu->identity.varyings_count = 8; 289602eb489SRussell King } 290602eb489SRussell King 291602eb489SRussell King /* 292602eb489SRussell King * For some cores, two varyings are consumed for position, so the 293602eb489SRussell King * maximum varying count needs to be reduced by one. 294602eb489SRussell King */ 295602eb489SRussell King if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 296602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 297602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 298602eb489SRussell King etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 299602eb489SRussell King etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 300602eb489SRussell King etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 301602eb489SRussell King etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 302602eb489SRussell King etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 303602eb489SRussell King etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 304602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5107) || 305602eb489SRussell King etnaviv_is_model_rev(gpu, GC880, 0x5106)) 306602eb489SRussell King gpu->identity.varyings_count -= 1; 307a8c21a54SThe etnaviv authors } 308a8c21a54SThe etnaviv authors 309a8c21a54SThe etnaviv authors static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 310a8c21a54SThe etnaviv authors { 311a8c21a54SThe etnaviv authors u32 chipIdentity; 312a8c21a54SThe etnaviv authors 313a8c21a54SThe etnaviv authors chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 314a8c21a54SThe etnaviv authors 315a8c21a54SThe etnaviv authors /* Special case for older graphic cores. */ 31652f36ba1SRussell King if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 317507f8991SRussell King gpu->identity.model = chipModel_GC500; 31852f36ba1SRussell King gpu->identity.revision = etnaviv_field(chipIdentity, 31952f36ba1SRussell King VIVS_HI_CHIP_IDENTITY_REVISION); 320a8c21a54SThe etnaviv authors } else { 321a8c21a54SThe etnaviv authors 322a8c21a54SThe etnaviv authors gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 323a8c21a54SThe etnaviv authors gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 324a8c21a54SThe etnaviv authors 325a8c21a54SThe etnaviv authors /* 326a8c21a54SThe etnaviv authors * !!!! HACK ALERT !!!! 327a8c21a54SThe etnaviv authors * Because people change device IDs without letting software 328a8c21a54SThe etnaviv authors * know about it - here is the hack to make it all look the 329a8c21a54SThe etnaviv authors * same. Only for GC400 family. 330a8c21a54SThe etnaviv authors */ 331a8c21a54SThe etnaviv authors if ((gpu->identity.model & 0xff00) == 0x0400 && 332507f8991SRussell King gpu->identity.model != chipModel_GC420) { 333a8c21a54SThe etnaviv authors gpu->identity.model = gpu->identity.model & 0x0400; 334a8c21a54SThe etnaviv authors } 335a8c21a54SThe etnaviv authors 336a8c21a54SThe etnaviv authors /* Another special case */ 337472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 338a8c21a54SThe etnaviv authors u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 339a8c21a54SThe etnaviv authors u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 340a8c21a54SThe etnaviv authors 341a8c21a54SThe etnaviv authors if (chipDate == 0x20080814 && chipTime == 0x12051100) { 342a8c21a54SThe etnaviv authors /* 343a8c21a54SThe etnaviv authors * This IP has an ECO; put the correct 344a8c21a54SThe etnaviv authors * revision in it. 345a8c21a54SThe etnaviv authors */ 346a8c21a54SThe etnaviv authors gpu->identity.revision = 0x1051; 347a8c21a54SThe etnaviv authors } 348a8c21a54SThe etnaviv authors } 34912ff4bdeSLucas Stach 35012ff4bdeSLucas Stach /* 35112ff4bdeSLucas Stach * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 35212ff4bdeSLucas Stach * reality it's just a re-branded GC3000. We can identify this 35312ff4bdeSLucas Stach * core by the upper half of the revision register being all 1. 35412ff4bdeSLucas Stach * Fix model/rev here, so all other places can refer to this 35512ff4bdeSLucas Stach * core by its real identity. 35612ff4bdeSLucas Stach */ 35712ff4bdeSLucas Stach if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 35812ff4bdeSLucas Stach gpu->identity.model = chipModel_GC3000; 35912ff4bdeSLucas Stach gpu->identity.revision &= 0xffff; 36012ff4bdeSLucas Stach } 361a8c21a54SThe etnaviv authors } 362a8c21a54SThe etnaviv authors 363a8c21a54SThe etnaviv authors dev_info(gpu->dev, "model: GC%x, revision: %x\n", 364a8c21a54SThe etnaviv authors gpu->identity.model, gpu->identity.revision); 365a8c21a54SThe etnaviv authors 366681c19c8SLucas Stach /* 367681c19c8SLucas Stach * If there is a match in the HWDB, we aren't interested in the 368681c19c8SLucas Stach * remaining register values, as they might be wrong. 369681c19c8SLucas Stach */ 370681c19c8SLucas Stach if (etnaviv_fill_identity_from_hwdb(gpu)) 371681c19c8SLucas Stach return; 372681c19c8SLucas Stach 373a8c21a54SThe etnaviv authors gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 374a8c21a54SThe etnaviv authors 375a8c21a54SThe etnaviv authors /* Disable fast clear on GC700. */ 376507f8991SRussell King if (gpu->identity.model == chipModel_GC700) 377a8c21a54SThe etnaviv authors gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 378a8c21a54SThe etnaviv authors 379507f8991SRussell King if ((gpu->identity.model == chipModel_GC500 && 380507f8991SRussell King gpu->identity.revision < 2) || 381507f8991SRussell King (gpu->identity.model == chipModel_GC300 && 382507f8991SRussell King gpu->identity.revision < 0x2000)) { 383a8c21a54SThe etnaviv authors 384a8c21a54SThe etnaviv authors /* 385a8c21a54SThe etnaviv authors * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 386a8c21a54SThe etnaviv authors * registers. 387a8c21a54SThe etnaviv authors */ 388a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 0; 389a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 0; 390a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 0; 391a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 0; 392602eb489SRussell King gpu->identity.minor_features4 = 0; 393602eb489SRussell King gpu->identity.minor_features5 = 0; 394a8c21a54SThe etnaviv authors } else 395a8c21a54SThe etnaviv authors gpu->identity.minor_features0 = 396a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 397a8c21a54SThe etnaviv authors 398a8c21a54SThe etnaviv authors if (gpu->identity.minor_features0 & 399a8c21a54SThe etnaviv authors chipMinorFeatures0_MORE_MINOR_FEATURES) { 400a8c21a54SThe etnaviv authors gpu->identity.minor_features1 = 401a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 402a8c21a54SThe etnaviv authors gpu->identity.minor_features2 = 403a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 404a8c21a54SThe etnaviv authors gpu->identity.minor_features3 = 405a8c21a54SThe etnaviv authors gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 406602eb489SRussell King gpu->identity.minor_features4 = 407602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 408602eb489SRussell King gpu->identity.minor_features5 = 409602eb489SRussell King gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 410a8c21a54SThe etnaviv authors } 411a8c21a54SThe etnaviv authors 412a8c21a54SThe etnaviv authors /* GC600 idle register reports zero bits where modules aren't present */ 413a8c21a54SThe etnaviv authors if (gpu->identity.model == chipModel_GC600) { 414a8c21a54SThe etnaviv authors gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 415a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_RA | 416a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SE | 417a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PA | 418a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_SH | 419a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_PE | 420a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_DE | 421a8c21a54SThe etnaviv authors VIVS_HI_IDLE_STATE_FE; 422a8c21a54SThe etnaviv authors } else { 423a8c21a54SThe etnaviv authors gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 424a8c21a54SThe etnaviv authors } 425a8c21a54SThe etnaviv authors 426a8c21a54SThe etnaviv authors etnaviv_hw_specs(gpu); 427a8c21a54SThe etnaviv authors } 428a8c21a54SThe etnaviv authors 429a8c21a54SThe etnaviv authors static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 430a8c21a54SThe etnaviv authors { 431a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 432a8c21a54SThe etnaviv authors VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 433a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 434a8c21a54SThe etnaviv authors } 435a8c21a54SThe etnaviv authors 436bcdfb5e5SRussell King static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 437bcdfb5e5SRussell King { 438d79fd1ccSLucas Stach if (gpu->identity.minor_features2 & 439d79fd1ccSLucas Stach chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 440d79fd1ccSLucas Stach clk_set_rate(gpu->clk_core, 441d79fd1ccSLucas Stach gpu->base_rate_core >> gpu->freq_scale); 442d79fd1ccSLucas Stach clk_set_rate(gpu->clk_shader, 443d79fd1ccSLucas Stach gpu->base_rate_shader >> gpu->freq_scale); 444d79fd1ccSLucas Stach } else { 445bcdfb5e5SRussell King unsigned int fscale = 1 << (6 - gpu->freq_scale); 4466eb3ecc3SLucas Stach u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 447bcdfb5e5SRussell King 4486eb3ecc3SLucas Stach clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 4496eb3ecc3SLucas Stach clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 450bcdfb5e5SRussell King etnaviv_gpu_load_clock(gpu, clock); 451bcdfb5e5SRussell King } 452d79fd1ccSLucas Stach } 453bcdfb5e5SRussell King 454a8c21a54SThe etnaviv authors static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 455a8c21a54SThe etnaviv authors { 456a8c21a54SThe etnaviv authors u32 control, idle; 457a8c21a54SThe etnaviv authors unsigned long timeout; 458a8c21a54SThe etnaviv authors bool failed = true; 459a8c21a54SThe etnaviv authors 460a8c21a54SThe etnaviv authors /* We hope that the GPU resets in under one second */ 461a8c21a54SThe etnaviv authors timeout = jiffies + msecs_to_jiffies(1000); 462a8c21a54SThe etnaviv authors 463a8c21a54SThe etnaviv authors while (time_is_after_jiffies(timeout)) { 464a8c21a54SThe etnaviv authors /* enable clock */ 4656eb3ecc3SLucas Stach unsigned int fscale = 1 << (6 - gpu->freq_scale); 4666eb3ecc3SLucas Stach control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 4676eb3ecc3SLucas Stach etnaviv_gpu_load_clock(gpu, control); 468a8c21a54SThe etnaviv authors 469a8c21a54SThe etnaviv authors /* isolate the GPU. */ 470a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 471a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 472a8c21a54SThe etnaviv authors 473c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 474c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 475c997c3dfSLucas Stach VIVS_MMUv2_AHB_CONTROL_RESET); 476c997c3dfSLucas Stach } else { 477a8c21a54SThe etnaviv authors /* set soft reset. */ 478a8c21a54SThe etnaviv authors control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 479a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 480c997c3dfSLucas Stach } 481a8c21a54SThe etnaviv authors 482a8c21a54SThe etnaviv authors /* wait for reset. */ 48340462179SPhilipp Zabel usleep_range(10, 20); 484a8c21a54SThe etnaviv authors 485a8c21a54SThe etnaviv authors /* reset soft reset bit. */ 486a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 487a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 488a8c21a54SThe etnaviv authors 489a8c21a54SThe etnaviv authors /* reset GPU isolation. */ 490a8c21a54SThe etnaviv authors control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 491a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 492a8c21a54SThe etnaviv authors 493a8c21a54SThe etnaviv authors /* read idle register. */ 494a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 495a8c21a54SThe etnaviv authors 496a8c21a54SThe etnaviv authors /* try reseting again if FE it not idle */ 497a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 498a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "FE is not idle\n"); 499a8c21a54SThe etnaviv authors continue; 500a8c21a54SThe etnaviv authors } 501a8c21a54SThe etnaviv authors 502a8c21a54SThe etnaviv authors /* read reset register. */ 503a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 504a8c21a54SThe etnaviv authors 505a8c21a54SThe etnaviv authors /* is the GPU idle? */ 506a8c21a54SThe etnaviv authors if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 507a8c21a54SThe etnaviv authors ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 508a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "GPU is not idle\n"); 509a8c21a54SThe etnaviv authors continue; 510a8c21a54SThe etnaviv authors } 511a8c21a54SThe etnaviv authors 5126eb3ecc3SLucas Stach /* disable debug registers, as they are not normally needed */ 5136eb3ecc3SLucas Stach control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 5146eb3ecc3SLucas Stach gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 5156eb3ecc3SLucas Stach 516a8c21a54SThe etnaviv authors failed = false; 517a8c21a54SThe etnaviv authors break; 518a8c21a54SThe etnaviv authors } 519a8c21a54SThe etnaviv authors 520a8c21a54SThe etnaviv authors if (failed) { 521a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 522a8c21a54SThe etnaviv authors control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 523a8c21a54SThe etnaviv authors 524a8c21a54SThe etnaviv authors dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 525a8c21a54SThe etnaviv authors idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 526a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 527a8c21a54SThe etnaviv authors control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 528a8c21a54SThe etnaviv authors 529a8c21a54SThe etnaviv authors return -EBUSY; 530a8c21a54SThe etnaviv authors } 531a8c21a54SThe etnaviv authors 532a8c21a54SThe etnaviv authors /* We rely on the GPU running, so program the clock */ 533bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 534a8c21a54SThe etnaviv authors 535a8c21a54SThe etnaviv authors return 0; 536a8c21a54SThe etnaviv authors } 537a8c21a54SThe etnaviv authors 5387d0c6e71SRussell King static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 5397d0c6e71SRussell King { 5407d0c6e71SRussell King u32 pmc, ppc; 5417d0c6e71SRussell King 5427d0c6e71SRussell King /* enable clock gating */ 5437d0c6e71SRussell King ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 5447d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 5457d0c6e71SRussell King 5467d0c6e71SRussell King /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 5477d0c6e71SRussell King if (gpu->identity.revision == 0x4301 || 5487d0c6e71SRussell King gpu->identity.revision == 0x4302) 5497d0c6e71SRussell King ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 5507d0c6e71SRussell King 5517d0c6e71SRussell King gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 5527d0c6e71SRussell King 5537d0c6e71SRussell King pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 5547d0c6e71SRussell King 5557cef6004SLucas Stach /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 5567d0c6e71SRussell King if (gpu->identity.model >= chipModel_GC400 && 5577cef6004SLucas Stach gpu->identity.model != chipModel_GC420 && 5587cef6004SLucas Stach !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 5597d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 5607d0c6e71SRussell King 5617d0c6e71SRussell King /* 5627d0c6e71SRussell King * Disable PE clock gating on revs < 5.0.0.0 when HZ is 5637d0c6e71SRussell King * present without a bug fix. 5647d0c6e71SRussell King */ 5657d0c6e71SRussell King if (gpu->identity.revision < 0x5000 && 5667d0c6e71SRussell King gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 5677d0c6e71SRussell King !(gpu->identity.minor_features1 & 5687d0c6e71SRussell King chipMinorFeatures1_DISABLE_PE_GATING)) 5697d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 5707d0c6e71SRussell King 5717d0c6e71SRussell King if (gpu->identity.revision < 0x5422) 5727d0c6e71SRussell King pmc |= BIT(15); /* Unknown bit */ 5737d0c6e71SRussell King 5747cef6004SLucas Stach /* Disable TX clock gating on affected core revisions. */ 5757cef6004SLucas Stach if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 5767cef6004SLucas Stach etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 5777cef6004SLucas Stach pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 5787cef6004SLucas Stach 5797d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 5807d0c6e71SRussell King pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 5817d0c6e71SRussell King 5827d0c6e71SRussell King gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 5837d0c6e71SRussell King } 5847d0c6e71SRussell King 585229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 586229855b6SLucas Stach { 587229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 588229855b6SLucas Stach gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 589229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_ENABLE | 590229855b6SLucas Stach VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 591c997c3dfSLucas Stach 592c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 593c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 594c997c3dfSLucas Stach VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 595c997c3dfSLucas Stach VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 596c997c3dfSLucas Stach } 597229855b6SLucas Stach } 598229855b6SLucas Stach 599e17a0dedSWladimir J. van der Laan static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 600e17a0dedSWladimir J. van der Laan { 601e17a0dedSWladimir J. van der Laan /* 602e17a0dedSWladimir J. van der Laan * Base value for VIVS_PM_PULSE_EATER register on models where it 603e17a0dedSWladimir J. van der Laan * cannot be read, extracted from vivante kernel driver. 604e17a0dedSWladimir J. van der Laan */ 605e17a0dedSWladimir J. van der Laan u32 pulse_eater = 0x01590880; 606e17a0dedSWladimir J. van der Laan 607e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 608e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 609e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(23); 610e17a0dedSWladimir J. van der Laan 611e17a0dedSWladimir J. van der Laan } 612e17a0dedSWladimir J. van der Laan 613e17a0dedSWladimir J. van der Laan if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 614e17a0dedSWladimir J. van der Laan etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 615e17a0dedSWladimir J. van der Laan pulse_eater &= ~BIT(16); 616e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(17); 617e17a0dedSWladimir J. van der Laan } 618e17a0dedSWladimir J. van der Laan 619e17a0dedSWladimir J. van der Laan if ((gpu->identity.revision > 0x5420) && 620e17a0dedSWladimir J. van der Laan (gpu->identity.features & chipFeatures_PIPE_3D)) 621e17a0dedSWladimir J. van der Laan { 622e17a0dedSWladimir J. van der Laan /* Performance fix: disable internal DFS */ 623e17a0dedSWladimir J. van der Laan pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 624e17a0dedSWladimir J. van der Laan pulse_eater |= BIT(18); 625e17a0dedSWladimir J. van der Laan } 626e17a0dedSWladimir J. van der Laan 627e17a0dedSWladimir J. van der Laan gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 628e17a0dedSWladimir J. van der Laan } 629e17a0dedSWladimir J. van der Laan 630a8c21a54SThe etnaviv authors static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 631a8c21a54SThe etnaviv authors { 632a8c21a54SThe etnaviv authors u16 prefetch; 633a8c21a54SThe etnaviv authors 634472f79dcSRussell King if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 635472f79dcSRussell King etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 636472f79dcSRussell King gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 637a8c21a54SThe etnaviv authors u32 mc_memory_debug; 638a8c21a54SThe etnaviv authors 639a8c21a54SThe etnaviv authors mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 640a8c21a54SThe etnaviv authors 641a8c21a54SThe etnaviv authors if (gpu->identity.revision == 0x5007) 642a8c21a54SThe etnaviv authors mc_memory_debug |= 0x0c; 643a8c21a54SThe etnaviv authors else 644a8c21a54SThe etnaviv authors mc_memory_debug |= 0x08; 645a8c21a54SThe etnaviv authors 646a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 647a8c21a54SThe etnaviv authors } 648a8c21a54SThe etnaviv authors 6497d0c6e71SRussell King /* enable module-level clock gating */ 6507d0c6e71SRussell King etnaviv_gpu_enable_mlcg(gpu); 6517d0c6e71SRussell King 652a8c21a54SThe etnaviv authors /* 653a8c21a54SThe etnaviv authors * Update GPU AXI cache atttribute to "cacheable, no allocate". 654a8c21a54SThe etnaviv authors * This is necessary to prevent the iMX6 SoC locking up. 655a8c21a54SThe etnaviv authors */ 656a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_AXI_CONFIG, 657a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_AWCACHE(2) | 658a8c21a54SThe etnaviv authors VIVS_HI_AXI_CONFIG_ARCACHE(2)); 659a8c21a54SThe etnaviv authors 660a8c21a54SThe etnaviv authors /* GC2000 rev 5108 needs a special bus config */ 661472f79dcSRussell King if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 662a8c21a54SThe etnaviv authors u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 663a8c21a54SThe etnaviv authors bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 664a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 665a8c21a54SThe etnaviv authors bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 666a8c21a54SThe etnaviv authors VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 667a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 668a8c21a54SThe etnaviv authors } 669a8c21a54SThe etnaviv authors 670c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_KERNEL) { 671c997c3dfSLucas Stach u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 672c997c3dfSLucas Stach val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 673c997c3dfSLucas Stach gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 674c997c3dfSLucas Stach } 675c997c3dfSLucas Stach 676e17a0dedSWladimir J. van der Laan /* setup the pulse eater */ 677e17a0dedSWladimir J. van der Laan etnaviv_gpu_setup_pulse_eater(gpu); 678e17a0dedSWladimir J. van der Laan 67999f861bcSLucas Stach /* setup the MMU */ 680e095c8feSLucas Stach etnaviv_iommu_restore(gpu); 681a8c21a54SThe etnaviv authors 682a8c21a54SThe etnaviv authors /* Start command processor */ 683a8c21a54SThe etnaviv authors prefetch = etnaviv_buffer_init(gpu); 684a8c21a54SThe etnaviv authors 685a8c21a54SThe etnaviv authors gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 6862f9225dbSLucas Stach etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer), 687229855b6SLucas Stach prefetch); 688a8c21a54SThe etnaviv authors } 689a8c21a54SThe etnaviv authors 690a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 691a8c21a54SThe etnaviv authors { 692a8c21a54SThe etnaviv authors int ret, i; 693a8c21a54SThe etnaviv authors 694a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 6951409df04SLucas Stach if (ret < 0) { 6961409df04SLucas Stach dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 697a8c21a54SThe etnaviv authors return ret; 6981409df04SLucas Stach } 699a8c21a54SThe etnaviv authors 700a8c21a54SThe etnaviv authors etnaviv_hw_identify(gpu); 701a8c21a54SThe etnaviv authors 702a8c21a54SThe etnaviv authors if (gpu->identity.model == 0) { 703a8c21a54SThe etnaviv authors dev_err(gpu->dev, "Unknown GPU model\n"); 704f6427760SRussell King ret = -ENXIO; 705f6427760SRussell King goto fail; 706a8c21a54SThe etnaviv authors } 707a8c21a54SThe etnaviv authors 708b98c6688SRussell King /* Exclude VG cores with FE2.0 */ 709b98c6688SRussell King if (gpu->identity.features & chipFeatures_PIPE_VG && 710b98c6688SRussell King gpu->identity.features & chipFeatures_FE20) { 711b98c6688SRussell King dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 712b98c6688SRussell King ret = -ENXIO; 713b98c6688SRussell King goto fail; 714b98c6688SRussell King } 715b98c6688SRussell King 7162144fff7SLucas Stach /* 7172144fff7SLucas Stach * Set the GPU linear window to be at the end of the DMA window, where 7182144fff7SLucas Stach * the CMA area is likely to reside. This ensures that we are able to 7192144fff7SLucas Stach * map the command buffers while having the linear window overlap as 7202144fff7SLucas Stach * much RAM as possible, so we can optimize mappings for other buffers. 7212144fff7SLucas Stach * 7222144fff7SLucas Stach * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads 7232144fff7SLucas Stach * to different views of the memory on the individual engines. 7242144fff7SLucas Stach */ 7252144fff7SLucas Stach if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 7262144fff7SLucas Stach (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 7272144fff7SLucas Stach u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); 7282144fff7SLucas Stach if (dma_mask < PHYS_OFFSET + SZ_2G) 7292144fff7SLucas Stach gpu->memory_base = PHYS_OFFSET; 7302144fff7SLucas Stach else 7312144fff7SLucas Stach gpu->memory_base = dma_mask - SZ_2G + 1; 7321db01279SLucas Stach } else if (PHYS_OFFSET >= SZ_2G) { 7331db01279SLucas Stach dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); 7341db01279SLucas Stach gpu->memory_base = PHYS_OFFSET; 7351db01279SLucas Stach gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 7362144fff7SLucas Stach } 7372144fff7SLucas Stach 738c997c3dfSLucas Stach /* 739c997c3dfSLucas Stach * On cores with security features supported, we claim control over the 740c997c3dfSLucas Stach * security states. 741c997c3dfSLucas Stach */ 742c997c3dfSLucas Stach if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 743c997c3dfSLucas Stach (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 744c997c3dfSLucas Stach gpu->sec_mode = ETNA_SEC_KERNEL; 745c997c3dfSLucas Stach 746a8c21a54SThe etnaviv authors ret = etnaviv_hw_reset(gpu); 7471409df04SLucas Stach if (ret) { 7481409df04SLucas Stach dev_err(gpu->dev, "GPU reset failed\n"); 749a8c21a54SThe etnaviv authors goto fail; 7501409df04SLucas Stach } 751a8c21a54SThe etnaviv authors 752dd34bb96SLucas Stach gpu->mmu = etnaviv_iommu_new(gpu); 753dd34bb96SLucas Stach if (IS_ERR(gpu->mmu)) { 7541409df04SLucas Stach dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); 755dd34bb96SLucas Stach ret = PTR_ERR(gpu->mmu); 756a8c21a54SThe etnaviv authors goto fail; 757a8c21a54SThe etnaviv authors } 758a8c21a54SThe etnaviv authors 759e66774ddSLucas Stach gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu); 760e66774ddSLucas Stach if (IS_ERR(gpu->cmdbuf_suballoc)) { 761e66774ddSLucas Stach dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); 762e66774ddSLucas Stach ret = PTR_ERR(gpu->cmdbuf_suballoc); 763e66774ddSLucas Stach goto fail; 764e66774ddSLucas Stach } 765e66774ddSLucas Stach 766a8c21a54SThe etnaviv authors /* Create buffer: */ 7672f9225dbSLucas Stach ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer, 7682f9225dbSLucas Stach PAGE_SIZE); 7692f9225dbSLucas Stach if (ret) { 770a8c21a54SThe etnaviv authors dev_err(gpu->dev, "could not create command buffer\n"); 77145d16a6dSLucas Stach goto destroy_iommu; 772a8c21a54SThe etnaviv authors } 773acfee0ecSLucas Stach 774acfee0ecSLucas Stach if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && 7752f9225dbSLucas Stach etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) { 776a8c21a54SThe etnaviv authors ret = -EINVAL; 777a8c21a54SThe etnaviv authors dev_err(gpu->dev, 778a8c21a54SThe etnaviv authors "command buffer outside valid memory window\n"); 779a8c21a54SThe etnaviv authors goto free_buffer; 780a8c21a54SThe etnaviv authors } 781a8c21a54SThe etnaviv authors 782a8c21a54SThe etnaviv authors /* Setup event management */ 783a8c21a54SThe etnaviv authors spin_lock_init(&gpu->event_spinlock); 784a8c21a54SThe etnaviv authors init_completion(&gpu->event_free); 785355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 786355502e0SChristian Gmeiner for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 787a8c21a54SThe etnaviv authors complete(&gpu->event_free); 788a8c21a54SThe etnaviv authors 789a8c21a54SThe etnaviv authors /* Now program the hardware */ 790a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 791a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 792f6086311SRussell King gpu->exec_state = -1; 793a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 794a8c21a54SThe etnaviv authors 795a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 796a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 797a8c21a54SThe etnaviv authors 798a8c21a54SThe etnaviv authors return 0; 799a8c21a54SThe etnaviv authors 800a8c21a54SThe etnaviv authors free_buffer: 8012f9225dbSLucas Stach etnaviv_cmdbuf_free(&gpu->buffer); 8025b147465SLucas Stach gpu->buffer.suballoc = NULL; 80345d16a6dSLucas Stach destroy_iommu: 80445d16a6dSLucas Stach etnaviv_iommu_destroy(gpu->mmu); 80545d16a6dSLucas Stach gpu->mmu = NULL; 806a8c21a54SThe etnaviv authors fail: 807a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 808a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 809a8c21a54SThe etnaviv authors 810a8c21a54SThe etnaviv authors return ret; 811a8c21a54SThe etnaviv authors } 812a8c21a54SThe etnaviv authors 813a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 814a8c21a54SThe etnaviv authors struct dma_debug { 815a8c21a54SThe etnaviv authors u32 address[2]; 816a8c21a54SThe etnaviv authors u32 state[2]; 817a8c21a54SThe etnaviv authors }; 818a8c21a54SThe etnaviv authors 819a8c21a54SThe etnaviv authors static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 820a8c21a54SThe etnaviv authors { 821a8c21a54SThe etnaviv authors u32 i; 822a8c21a54SThe etnaviv authors 823a8c21a54SThe etnaviv authors debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 824a8c21a54SThe etnaviv authors debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 825a8c21a54SThe etnaviv authors 826a8c21a54SThe etnaviv authors for (i = 0; i < 500; i++) { 827a8c21a54SThe etnaviv authors debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 828a8c21a54SThe etnaviv authors debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 829a8c21a54SThe etnaviv authors 830a8c21a54SThe etnaviv authors if (debug->address[0] != debug->address[1]) 831a8c21a54SThe etnaviv authors break; 832a8c21a54SThe etnaviv authors 833a8c21a54SThe etnaviv authors if (debug->state[0] != debug->state[1]) 834a8c21a54SThe etnaviv authors break; 835a8c21a54SThe etnaviv authors } 836a8c21a54SThe etnaviv authors } 837a8c21a54SThe etnaviv authors 838a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 839a8c21a54SThe etnaviv authors { 840a8c21a54SThe etnaviv authors struct dma_debug debug; 841a8c21a54SThe etnaviv authors u32 dma_lo, dma_hi, axi, idle; 842a8c21a54SThe etnaviv authors int ret; 843a8c21a54SThe etnaviv authors 844a8c21a54SThe etnaviv authors seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 845a8c21a54SThe etnaviv authors 846a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 847a8c21a54SThe etnaviv authors if (ret < 0) 848a8c21a54SThe etnaviv authors return ret; 849a8c21a54SThe etnaviv authors 850a8c21a54SThe etnaviv authors dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 851a8c21a54SThe etnaviv authors dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 852a8c21a54SThe etnaviv authors axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 853a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 854a8c21a54SThe etnaviv authors 855a8c21a54SThe etnaviv authors verify_dma(gpu, &debug); 856a8c21a54SThe etnaviv authors 857a8c21a54SThe etnaviv authors seq_puts(m, "\tfeatures\n"); 8583d9fc642SLucas Stach seq_printf(m, "\t major_features: 0x%08x\n", 8593d9fc642SLucas Stach gpu->identity.features); 860a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features0: 0x%08x\n", 861a8c21a54SThe etnaviv authors gpu->identity.minor_features0); 862a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features1: 0x%08x\n", 863a8c21a54SThe etnaviv authors gpu->identity.minor_features1); 864a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features2: 0x%08x\n", 865a8c21a54SThe etnaviv authors gpu->identity.minor_features2); 866a8c21a54SThe etnaviv authors seq_printf(m, "\t minor_features3: 0x%08x\n", 867a8c21a54SThe etnaviv authors gpu->identity.minor_features3); 868602eb489SRussell King seq_printf(m, "\t minor_features4: 0x%08x\n", 869602eb489SRussell King gpu->identity.minor_features4); 870602eb489SRussell King seq_printf(m, "\t minor_features5: 0x%08x\n", 871602eb489SRussell King gpu->identity.minor_features5); 8720538aaf9SLucas Stach seq_printf(m, "\t minor_features6: 0x%08x\n", 8730538aaf9SLucas Stach gpu->identity.minor_features6); 8740538aaf9SLucas Stach seq_printf(m, "\t minor_features7: 0x%08x\n", 8750538aaf9SLucas Stach gpu->identity.minor_features7); 8760538aaf9SLucas Stach seq_printf(m, "\t minor_features8: 0x%08x\n", 8770538aaf9SLucas Stach gpu->identity.minor_features8); 8780538aaf9SLucas Stach seq_printf(m, "\t minor_features9: 0x%08x\n", 8790538aaf9SLucas Stach gpu->identity.minor_features9); 8800538aaf9SLucas Stach seq_printf(m, "\t minor_features10: 0x%08x\n", 8810538aaf9SLucas Stach gpu->identity.minor_features10); 8820538aaf9SLucas Stach seq_printf(m, "\t minor_features11: 0x%08x\n", 8830538aaf9SLucas Stach gpu->identity.minor_features11); 884a8c21a54SThe etnaviv authors 885a8c21a54SThe etnaviv authors seq_puts(m, "\tspecs\n"); 886a8c21a54SThe etnaviv authors seq_printf(m, "\t stream_count: %d\n", 887a8c21a54SThe etnaviv authors gpu->identity.stream_count); 888a8c21a54SThe etnaviv authors seq_printf(m, "\t register_max: %d\n", 889a8c21a54SThe etnaviv authors gpu->identity.register_max); 890a8c21a54SThe etnaviv authors seq_printf(m, "\t thread_count: %d\n", 891a8c21a54SThe etnaviv authors gpu->identity.thread_count); 892a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_cache_size: %d\n", 893a8c21a54SThe etnaviv authors gpu->identity.vertex_cache_size); 894a8c21a54SThe etnaviv authors seq_printf(m, "\t shader_core_count: %d\n", 895a8c21a54SThe etnaviv authors gpu->identity.shader_core_count); 896a8c21a54SThe etnaviv authors seq_printf(m, "\t pixel_pipes: %d\n", 897a8c21a54SThe etnaviv authors gpu->identity.pixel_pipes); 898a8c21a54SThe etnaviv authors seq_printf(m, "\t vertex_output_buffer_size: %d\n", 899a8c21a54SThe etnaviv authors gpu->identity.vertex_output_buffer_size); 900a8c21a54SThe etnaviv authors seq_printf(m, "\t buffer_size: %d\n", 901a8c21a54SThe etnaviv authors gpu->identity.buffer_size); 902a8c21a54SThe etnaviv authors seq_printf(m, "\t instruction_count: %d\n", 903a8c21a54SThe etnaviv authors gpu->identity.instruction_count); 904a8c21a54SThe etnaviv authors seq_printf(m, "\t num_constants: %d\n", 905a8c21a54SThe etnaviv authors gpu->identity.num_constants); 906602eb489SRussell King seq_printf(m, "\t varyings_count: %d\n", 907602eb489SRussell King gpu->identity.varyings_count); 908a8c21a54SThe etnaviv authors 909a8c21a54SThe etnaviv authors seq_printf(m, "\taxi: 0x%08x\n", axi); 910a8c21a54SThe etnaviv authors seq_printf(m, "\tidle: 0x%08x\n", idle); 911a8c21a54SThe etnaviv authors idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 912a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 913a8c21a54SThe etnaviv authors seq_puts(m, "\t FE is not idle\n"); 914a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 915a8c21a54SThe etnaviv authors seq_puts(m, "\t DE is not idle\n"); 916a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 917a8c21a54SThe etnaviv authors seq_puts(m, "\t PE is not idle\n"); 918a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 919a8c21a54SThe etnaviv authors seq_puts(m, "\t SH is not idle\n"); 920a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 921a8c21a54SThe etnaviv authors seq_puts(m, "\t PA is not idle\n"); 922a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 923a8c21a54SThe etnaviv authors seq_puts(m, "\t SE is not idle\n"); 924a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 925a8c21a54SThe etnaviv authors seq_puts(m, "\t RA is not idle\n"); 926a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 927a8c21a54SThe etnaviv authors seq_puts(m, "\t TX is not idle\n"); 928a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 929a8c21a54SThe etnaviv authors seq_puts(m, "\t VG is not idle\n"); 930a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 931a8c21a54SThe etnaviv authors seq_puts(m, "\t IM is not idle\n"); 932a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 933a8c21a54SThe etnaviv authors seq_puts(m, "\t FP is not idle\n"); 934a8c21a54SThe etnaviv authors if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 935a8c21a54SThe etnaviv authors seq_puts(m, "\t TS is not idle\n"); 936a8c21a54SThe etnaviv authors if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 937a8c21a54SThe etnaviv authors seq_puts(m, "\t AXI low power mode\n"); 938a8c21a54SThe etnaviv authors 939a8c21a54SThe etnaviv authors if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 940a8c21a54SThe etnaviv authors u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 941a8c21a54SThe etnaviv authors u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 942a8c21a54SThe etnaviv authors u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 943a8c21a54SThe etnaviv authors 944a8c21a54SThe etnaviv authors seq_puts(m, "\tMC\n"); 945a8c21a54SThe etnaviv authors seq_printf(m, "\t read0: 0x%08x\n", read0); 946a8c21a54SThe etnaviv authors seq_printf(m, "\t read1: 0x%08x\n", read1); 947a8c21a54SThe etnaviv authors seq_printf(m, "\t write: 0x%08x\n", write); 948a8c21a54SThe etnaviv authors } 949a8c21a54SThe etnaviv authors 950a8c21a54SThe etnaviv authors seq_puts(m, "\tDMA "); 951a8c21a54SThe etnaviv authors 952a8c21a54SThe etnaviv authors if (debug.address[0] == debug.address[1] && 953a8c21a54SThe etnaviv authors debug.state[0] == debug.state[1]) { 954a8c21a54SThe etnaviv authors seq_puts(m, "seems to be stuck\n"); 955a8c21a54SThe etnaviv authors } else if (debug.address[0] == debug.address[1]) { 956c01e0159SMasanari Iida seq_puts(m, "address is constant\n"); 957a8c21a54SThe etnaviv authors } else { 958c01e0159SMasanari Iida seq_puts(m, "is running\n"); 959a8c21a54SThe etnaviv authors } 960a8c21a54SThe etnaviv authors 961a8c21a54SThe etnaviv authors seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 962a8c21a54SThe etnaviv authors seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 963a8c21a54SThe etnaviv authors seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 964a8c21a54SThe etnaviv authors seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 965a8c21a54SThe etnaviv authors seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 966a8c21a54SThe etnaviv authors dma_lo, dma_hi); 967a8c21a54SThe etnaviv authors 968a8c21a54SThe etnaviv authors ret = 0; 969a8c21a54SThe etnaviv authors 970a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 971a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 972a8c21a54SThe etnaviv authors 973a8c21a54SThe etnaviv authors return ret; 974a8c21a54SThe etnaviv authors } 975a8c21a54SThe etnaviv authors #endif 976a8c21a54SThe etnaviv authors 9776d7a20c0SLucas Stach void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) 978a8c21a54SThe etnaviv authors { 979a8c21a54SThe etnaviv authors unsigned long flags; 980355502e0SChristian Gmeiner unsigned int i = 0; 981a8c21a54SThe etnaviv authors 9826d7a20c0SLucas Stach dev_err(gpu->dev, "recover hung GPU!\n"); 983a8c21a54SThe etnaviv authors 984a8c21a54SThe etnaviv authors if (pm_runtime_get_sync(gpu->dev) < 0) 985a8c21a54SThe etnaviv authors return; 986a8c21a54SThe etnaviv authors 987a8c21a54SThe etnaviv authors mutex_lock(&gpu->lock); 988a8c21a54SThe etnaviv authors 989a8c21a54SThe etnaviv authors etnaviv_hw_reset(gpu); 990a8c21a54SThe etnaviv authors 991a8c21a54SThe etnaviv authors /* complete all events, the GPU won't do it after the reset */ 992a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 9936d7a20c0SLucas Stach for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) 994a8c21a54SThe etnaviv authors complete(&gpu->event_free); 995355502e0SChristian Gmeiner bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 996a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 997a8c21a54SThe etnaviv authors gpu->completed_fence = gpu->active_fence; 998a8c21a54SThe etnaviv authors 999a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 10001b94a9b7SLucas Stach gpu->lastctx = NULL; 1001f6086311SRussell King gpu->exec_state = -1; 1002a8c21a54SThe etnaviv authors 1003a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1004a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1005a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1006a8c21a54SThe etnaviv authors } 1007a8c21a54SThe etnaviv authors 1008a8c21a54SThe etnaviv authors /* fence object management */ 1009a8c21a54SThe etnaviv authors struct etnaviv_fence { 1010a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1011f54d1867SChris Wilson struct dma_fence base; 1012a8c21a54SThe etnaviv authors }; 1013a8c21a54SThe etnaviv authors 1014f54d1867SChris Wilson static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1015a8c21a54SThe etnaviv authors { 1016a8c21a54SThe etnaviv authors return container_of(fence, struct etnaviv_fence, base); 1017a8c21a54SThe etnaviv authors } 1018a8c21a54SThe etnaviv authors 1019f54d1867SChris Wilson static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1020a8c21a54SThe etnaviv authors { 1021a8c21a54SThe etnaviv authors return "etnaviv"; 1022a8c21a54SThe etnaviv authors } 1023a8c21a54SThe etnaviv authors 1024f54d1867SChris Wilson static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1025a8c21a54SThe etnaviv authors { 1026a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1027a8c21a54SThe etnaviv authors 1028a8c21a54SThe etnaviv authors return dev_name(f->gpu->dev); 1029a8c21a54SThe etnaviv authors } 1030a8c21a54SThe etnaviv authors 1031f54d1867SChris Wilson static bool etnaviv_fence_enable_signaling(struct dma_fence *fence) 1032a8c21a54SThe etnaviv authors { 1033a8c21a54SThe etnaviv authors return true; 1034a8c21a54SThe etnaviv authors } 1035a8c21a54SThe etnaviv authors 1036f54d1867SChris Wilson static bool etnaviv_fence_signaled(struct dma_fence *fence) 1037a8c21a54SThe etnaviv authors { 1038a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1039a8c21a54SThe etnaviv authors 1040a8c21a54SThe etnaviv authors return fence_completed(f->gpu, f->base.seqno); 1041a8c21a54SThe etnaviv authors } 1042a8c21a54SThe etnaviv authors 1043f54d1867SChris Wilson static void etnaviv_fence_release(struct dma_fence *fence) 1044a8c21a54SThe etnaviv authors { 1045a8c21a54SThe etnaviv authors struct etnaviv_fence *f = to_etnaviv_fence(fence); 1046a8c21a54SThe etnaviv authors 1047a8c21a54SThe etnaviv authors kfree_rcu(f, base.rcu); 1048a8c21a54SThe etnaviv authors } 1049a8c21a54SThe etnaviv authors 1050f54d1867SChris Wilson static const struct dma_fence_ops etnaviv_fence_ops = { 1051a8c21a54SThe etnaviv authors .get_driver_name = etnaviv_fence_get_driver_name, 1052a8c21a54SThe etnaviv authors .get_timeline_name = etnaviv_fence_get_timeline_name, 1053a8c21a54SThe etnaviv authors .enable_signaling = etnaviv_fence_enable_signaling, 1054a8c21a54SThe etnaviv authors .signaled = etnaviv_fence_signaled, 1055f54d1867SChris Wilson .wait = dma_fence_default_wait, 1056a8c21a54SThe etnaviv authors .release = etnaviv_fence_release, 1057a8c21a54SThe etnaviv authors }; 1058a8c21a54SThe etnaviv authors 1059f54d1867SChris Wilson static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1060a8c21a54SThe etnaviv authors { 1061a8c21a54SThe etnaviv authors struct etnaviv_fence *f; 1062a8c21a54SThe etnaviv authors 1063b27734c2SLucas Stach /* 1064b27734c2SLucas Stach * GPU lock must already be held, otherwise fence completion order might 1065b27734c2SLucas Stach * not match the seqno order assigned here. 1066b27734c2SLucas Stach */ 1067b27734c2SLucas Stach lockdep_assert_held(&gpu->lock); 1068b27734c2SLucas Stach 1069a8c21a54SThe etnaviv authors f = kzalloc(sizeof(*f), GFP_KERNEL); 1070a8c21a54SThe etnaviv authors if (!f) 1071a8c21a54SThe etnaviv authors return NULL; 1072a8c21a54SThe etnaviv authors 1073a8c21a54SThe etnaviv authors f->gpu = gpu; 1074a8c21a54SThe etnaviv authors 1075f54d1867SChris Wilson dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1076a8c21a54SThe etnaviv authors gpu->fence_context, ++gpu->next_fence); 1077a8c21a54SThe etnaviv authors 1078a8c21a54SThe etnaviv authors return &f->base; 1079a8c21a54SThe etnaviv authors } 1080a8c21a54SThe etnaviv authors 1081a8c21a54SThe etnaviv authors /* 1082a8c21a54SThe etnaviv authors * event management: 1083a8c21a54SThe etnaviv authors */ 1084a8c21a54SThe etnaviv authors 108595a428c1SChristian Gmeiner static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 108695a428c1SChristian Gmeiner unsigned int *events) 1087a8c21a54SThe etnaviv authors { 108895a428c1SChristian Gmeiner unsigned long flags, timeout = msecs_to_jiffies(10 * 10000); 108995a428c1SChristian Gmeiner unsigned i, acquired = 0; 1090a8c21a54SThe etnaviv authors 109195a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 109295a428c1SChristian Gmeiner unsigned long ret; 109395a428c1SChristian Gmeiner 109495a428c1SChristian Gmeiner ret = wait_for_completion_timeout(&gpu->event_free, timeout); 109595a428c1SChristian Gmeiner 109695a428c1SChristian Gmeiner if (!ret) { 1097a8c21a54SThe etnaviv authors dev_err(gpu->dev, "wait_for_completion_timeout failed"); 109895a428c1SChristian Gmeiner goto out; 109995a428c1SChristian Gmeiner } 110095a428c1SChristian Gmeiner 110195a428c1SChristian Gmeiner acquired++; 110295a428c1SChristian Gmeiner timeout = ret; 110395a428c1SChristian Gmeiner } 1104a8c21a54SThe etnaviv authors 1105a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1106a8c21a54SThe etnaviv authors 110795a428c1SChristian Gmeiner for (i = 0; i < nr_events; i++) { 110895a428c1SChristian Gmeiner int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 110995a428c1SChristian Gmeiner 111095a428c1SChristian Gmeiner events[i] = event; 1111547d340dSChristian Gmeiner memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1112355502e0SChristian Gmeiner set_bit(event, gpu->event_bitmap); 1113a8c21a54SThe etnaviv authors } 1114a8c21a54SThe etnaviv authors 1115a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1116a8c21a54SThe etnaviv authors 111795a428c1SChristian Gmeiner return 0; 111895a428c1SChristian Gmeiner 111995a428c1SChristian Gmeiner out: 112095a428c1SChristian Gmeiner for (i = 0; i < acquired; i++) 112195a428c1SChristian Gmeiner complete(&gpu->event_free); 112295a428c1SChristian Gmeiner 112395a428c1SChristian Gmeiner return -EBUSY; 1124a8c21a54SThe etnaviv authors } 1125a8c21a54SThe etnaviv authors 1126a8c21a54SThe etnaviv authors static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1127a8c21a54SThe etnaviv authors { 1128a8c21a54SThe etnaviv authors unsigned long flags; 1129a8c21a54SThe etnaviv authors 1130a8c21a54SThe etnaviv authors spin_lock_irqsave(&gpu->event_spinlock, flags); 1131a8c21a54SThe etnaviv authors 1132355502e0SChristian Gmeiner if (!test_bit(event, gpu->event_bitmap)) { 1133a8c21a54SThe etnaviv authors dev_warn(gpu->dev, "event %u is already marked as free", 1134a8c21a54SThe etnaviv authors event); 1135a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1136a8c21a54SThe etnaviv authors } else { 1137355502e0SChristian Gmeiner clear_bit(event, gpu->event_bitmap); 1138a8c21a54SThe etnaviv authors spin_unlock_irqrestore(&gpu->event_spinlock, flags); 1139a8c21a54SThe etnaviv authors 1140a8c21a54SThe etnaviv authors complete(&gpu->event_free); 1141a8c21a54SThe etnaviv authors } 1142a8c21a54SThe etnaviv authors } 1143a8c21a54SThe etnaviv authors 1144a8c21a54SThe etnaviv authors /* 1145a8c21a54SThe etnaviv authors * Cmdstream submission/retirement: 1146a8c21a54SThe etnaviv authors */ 1147a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 11488bc4d885SLucas Stach u32 id, struct timespec *timeout) 1149a8c21a54SThe etnaviv authors { 11508bc4d885SLucas Stach struct dma_fence *fence; 1151a8c21a54SThe etnaviv authors int ret; 1152a8c21a54SThe etnaviv authors 11538bc4d885SLucas Stach /* 1154e93b6deeSLucas Stach * Look up the fence and take a reference. We might still find a fence 11558bc4d885SLucas Stach * whose refcount has already dropped to zero. dma_fence_get_rcu 11568bc4d885SLucas Stach * pretends we didn't find a fence in that case. 11578bc4d885SLucas Stach */ 1158e93b6deeSLucas Stach rcu_read_lock(); 11598bc4d885SLucas Stach fence = idr_find(&gpu->fence_idr, id); 11608bc4d885SLucas Stach if (fence) 11618bc4d885SLucas Stach fence = dma_fence_get_rcu(fence); 1162e93b6deeSLucas Stach rcu_read_unlock(); 11638bc4d885SLucas Stach 11648bc4d885SLucas Stach if (!fence) 11658bc4d885SLucas Stach return 0; 1166a8c21a54SThe etnaviv authors 1167a8c21a54SThe etnaviv authors if (!timeout) { 1168a8c21a54SThe etnaviv authors /* No timeout was requested: just test for completion */ 11698bc4d885SLucas Stach ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1170a8c21a54SThe etnaviv authors } else { 1171a8c21a54SThe etnaviv authors unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1172a8c21a54SThe etnaviv authors 11738bc4d885SLucas Stach ret = dma_fence_wait_timeout(fence, true, remaining); 11748bc4d885SLucas Stach if (ret == 0) 1175a8c21a54SThe etnaviv authors ret = -ETIMEDOUT; 11768bc4d885SLucas Stach else if (ret != -ERESTARTSYS) 1177a8c21a54SThe etnaviv authors ret = 0; 11788bc4d885SLucas Stach 1179a8c21a54SThe etnaviv authors } 1180a8c21a54SThe etnaviv authors 11818bc4d885SLucas Stach dma_fence_put(fence); 1182a8c21a54SThe etnaviv authors return ret; 1183a8c21a54SThe etnaviv authors } 1184a8c21a54SThe etnaviv authors 1185a8c21a54SThe etnaviv authors /* 1186a8c21a54SThe etnaviv authors * Wait for an object to become inactive. This, on it's own, is not race 1187e93b6deeSLucas Stach * free: the object is moved by the scheduler off the active list, and 1188a8c21a54SThe etnaviv authors * then the iova is put. Moreover, the object could be re-submitted just 1189a8c21a54SThe etnaviv authors * after we notice that it's become inactive. 1190a8c21a54SThe etnaviv authors * 1191a8c21a54SThe etnaviv authors * Although the retirement happens under the gpu lock, we don't want to hold 1192a8c21a54SThe etnaviv authors * that lock in this function while waiting. 1193a8c21a54SThe etnaviv authors */ 1194a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1195a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) 1196a8c21a54SThe etnaviv authors { 1197a8c21a54SThe etnaviv authors unsigned long remaining; 1198a8c21a54SThe etnaviv authors long ret; 1199a8c21a54SThe etnaviv authors 1200a8c21a54SThe etnaviv authors if (!timeout) 1201a8c21a54SThe etnaviv authors return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1202a8c21a54SThe etnaviv authors 1203a8c21a54SThe etnaviv authors remaining = etnaviv_timeout_to_jiffies(timeout); 1204a8c21a54SThe etnaviv authors 1205a8c21a54SThe etnaviv authors ret = wait_event_interruptible_timeout(gpu->fence_event, 1206a8c21a54SThe etnaviv authors !is_active(etnaviv_obj), 1207a8c21a54SThe etnaviv authors remaining); 1208fa67ac84SLucas Stach if (ret > 0) 1209a8c21a54SThe etnaviv authors return 0; 1210fa67ac84SLucas Stach else if (ret == -ERESTARTSYS) 1211a8c21a54SThe etnaviv authors return -ERESTARTSYS; 1212fa67ac84SLucas Stach else 1213a8c21a54SThe etnaviv authors return -ETIMEDOUT; 1214a8c21a54SThe etnaviv authors } 1215a8c21a54SThe etnaviv authors 121668dc0b29SChristian Gmeiner static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 121768dc0b29SChristian Gmeiner struct etnaviv_event *event, unsigned int flags) 121868dc0b29SChristian Gmeiner { 1219ef146c00SLucas Stach const struct etnaviv_gem_submit *submit = event->submit; 122068dc0b29SChristian Gmeiner unsigned int i; 122168dc0b29SChristian Gmeiner 1222ef146c00SLucas Stach for (i = 0; i < submit->nr_pmrs; i++) { 1223ef146c00SLucas Stach const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 122468dc0b29SChristian Gmeiner 122568dc0b29SChristian Gmeiner if (pmr->flags == flags) 12267a9c0fe2SLucas Stach etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 122768dc0b29SChristian Gmeiner } 122868dc0b29SChristian Gmeiner } 122968dc0b29SChristian Gmeiner 123068dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 123168dc0b29SChristian Gmeiner struct etnaviv_event *event) 123268dc0b29SChristian Gmeiner { 12332c8b0c5aSChristian Gmeiner u32 val; 12342c8b0c5aSChristian Gmeiner 12352c8b0c5aSChristian Gmeiner /* disable clock gating */ 12362c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 12372c8b0c5aSChristian Gmeiner val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 12382c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 12392c8b0c5aSChristian Gmeiner 124004a7d18dSChristian Gmeiner /* enable debug register */ 124104a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 124204a7d18dSChristian Gmeiner val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 124304a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 124404a7d18dSChristian Gmeiner 124568dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 124668dc0b29SChristian Gmeiner } 124768dc0b29SChristian Gmeiner 124868dc0b29SChristian Gmeiner static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 124968dc0b29SChristian Gmeiner struct etnaviv_event *event) 125068dc0b29SChristian Gmeiner { 1251ef146c00SLucas Stach const struct etnaviv_gem_submit *submit = event->submit; 125268dc0b29SChristian Gmeiner unsigned int i; 12532c8b0c5aSChristian Gmeiner u32 val; 125468dc0b29SChristian Gmeiner 125568dc0b29SChristian Gmeiner sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 125668dc0b29SChristian Gmeiner 1257ef146c00SLucas Stach for (i = 0; i < submit->nr_pmrs; i++) { 1258ef146c00SLucas Stach const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 125968dc0b29SChristian Gmeiner 126068dc0b29SChristian Gmeiner *pmr->bo_vma = pmr->sequence; 126168dc0b29SChristian Gmeiner } 12622c8b0c5aSChristian Gmeiner 126304a7d18dSChristian Gmeiner /* disable debug register */ 126404a7d18dSChristian Gmeiner val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 126504a7d18dSChristian Gmeiner val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 126604a7d18dSChristian Gmeiner gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 126704a7d18dSChristian Gmeiner 12682c8b0c5aSChristian Gmeiner /* enable clock gating */ 12692c8b0c5aSChristian Gmeiner val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 12702c8b0c5aSChristian Gmeiner val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 12712c8b0c5aSChristian Gmeiner gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 127268dc0b29SChristian Gmeiner } 127368dc0b29SChristian Gmeiner 127468dc0b29SChristian Gmeiner 1275a8c21a54SThe etnaviv authors /* add bo's to gpu's ring, and kick gpu: */ 1276e93b6deeSLucas Stach struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1277a8c21a54SThe etnaviv authors { 1278e93b6deeSLucas Stach struct etnaviv_gpu *gpu = submit->gpu; 1279e93b6deeSLucas Stach struct dma_fence *gpu_fence; 128068dc0b29SChristian Gmeiner unsigned int i, nr_events = 1, event[3]; 1281a8c21a54SThe etnaviv authors int ret; 1282a8c21a54SThe etnaviv authors 12836d7a20c0SLucas Stach if (!submit->runtime_resumed) { 12848bda1516SLucas Stach ret = pm_runtime_get_sync(gpu->dev); 1285a8c21a54SThe etnaviv authors if (ret < 0) 1286e93b6deeSLucas Stach return NULL; 12878bda1516SLucas Stach submit->runtime_resumed = true; 12886d7a20c0SLucas Stach } 1289a8c21a54SThe etnaviv authors 1290a8c21a54SThe etnaviv authors /* 129168dc0b29SChristian Gmeiner * if there are performance monitor requests we need to have 129268dc0b29SChristian Gmeiner * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 129368dc0b29SChristian Gmeiner * requests. 129468dc0b29SChristian Gmeiner * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 129568dc0b29SChristian Gmeiner * and update the sequence number for userspace. 129668dc0b29SChristian Gmeiner */ 1297ef146c00SLucas Stach if (submit->nr_pmrs) 129868dc0b29SChristian Gmeiner nr_events = 3; 129968dc0b29SChristian Gmeiner 130068dc0b29SChristian Gmeiner ret = event_alloc(gpu, nr_events, event); 130195a428c1SChristian Gmeiner if (ret) { 130268dc0b29SChristian Gmeiner DRM_ERROR("no free events\n"); 1303e93b6deeSLucas Stach return NULL; 1304a8c21a54SThe etnaviv authors } 1305a8c21a54SThe etnaviv authors 1306f3cd1b06SLucas Stach mutex_lock(&gpu->lock); 1307f3cd1b06SLucas Stach 1308e93b6deeSLucas Stach gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1309e93b6deeSLucas Stach if (!gpu_fence) { 131068dc0b29SChristian Gmeiner for (i = 0; i < nr_events; i++) 131168dc0b29SChristian Gmeiner event_free(gpu, event[i]); 131268dc0b29SChristian Gmeiner 131345abdf35SWei Yongjun goto out_unlock; 1314a8c21a54SThe etnaviv authors } 1315a8c21a54SThe etnaviv authors 1316e93b6deeSLucas Stach gpu->active_fence = gpu_fence->seqno; 1317a8c21a54SThe etnaviv authors 1318ef146c00SLucas Stach if (submit->nr_pmrs) { 131968dc0b29SChristian Gmeiner gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1320ef146c00SLucas Stach kref_get(&submit->refcount); 1321ef146c00SLucas Stach gpu->event[event[1]].submit = submit; 132268dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[1]); 132368dc0b29SChristian Gmeiner } 132468dc0b29SChristian Gmeiner 1325e93b6deeSLucas Stach gpu->event[event[0]].fence = gpu_fence; 13266d7a20c0SLucas Stach submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 13272f9225dbSLucas Stach etnaviv_buffer_queue(gpu, submit->exec_state, event[0], 13282f9225dbSLucas Stach &submit->cmdbuf); 132968dc0b29SChristian Gmeiner 1330ef146c00SLucas Stach if (submit->nr_pmrs) { 133168dc0b29SChristian Gmeiner gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1332ef146c00SLucas Stach kref_get(&submit->refcount); 1333ef146c00SLucas Stach gpu->event[event[2]].submit = submit; 133468dc0b29SChristian Gmeiner etnaviv_sync_point_queue(gpu, event[2]); 133568dc0b29SChristian Gmeiner } 1336a8c21a54SThe etnaviv authors 133745abdf35SWei Yongjun out_unlock: 1338a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1339a8c21a54SThe etnaviv authors 1340e93b6deeSLucas Stach return gpu_fence; 1341a8c21a54SThe etnaviv authors } 1342a8c21a54SThe etnaviv authors 1343357713ceSChristian Gmeiner static void sync_point_worker(struct work_struct *work) 1344357713ceSChristian Gmeiner { 1345357713ceSChristian Gmeiner struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1346357713ceSChristian Gmeiner sync_point_work); 1347b9a48aa7SLucas Stach struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1348b9a48aa7SLucas Stach u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1349357713ceSChristian Gmeiner 1350b9a48aa7SLucas Stach event->sync_point(gpu, event); 1351ef146c00SLucas Stach etnaviv_submit_put(event->submit); 1352357713ceSChristian Gmeiner event_free(gpu, gpu->sync_point_event); 1353b9a48aa7SLucas Stach 1354b9a48aa7SLucas Stach /* restart FE last to avoid GPU and IRQ racing against this worker */ 1355b9a48aa7SLucas Stach etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1356357713ceSChristian Gmeiner } 1357357713ceSChristian Gmeiner 13584df3000eSLucas Stach static void dump_mmu_fault(struct etnaviv_gpu *gpu) 13594df3000eSLucas Stach { 1360c997c3dfSLucas Stach u32 status_reg, status; 13614df3000eSLucas Stach int i; 13624df3000eSLucas Stach 1363c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_NONE) 1364c997c3dfSLucas Stach status_reg = VIVS_MMUv2_STATUS; 1365c997c3dfSLucas Stach else 1366c997c3dfSLucas Stach status_reg = VIVS_MMUv2_SEC_STATUS; 1367c997c3dfSLucas Stach 1368c997c3dfSLucas Stach status = gpu_read(gpu, status_reg); 13694df3000eSLucas Stach dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 13704df3000eSLucas Stach 13714df3000eSLucas Stach for (i = 0; i < 4; i++) { 1372c997c3dfSLucas Stach u32 address_reg; 1373c997c3dfSLucas Stach 13744df3000eSLucas Stach if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4)))) 13754df3000eSLucas Stach continue; 13764df3000eSLucas Stach 1377c997c3dfSLucas Stach if (gpu->sec_mode == ETNA_SEC_NONE) 1378c997c3dfSLucas Stach address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1379c997c3dfSLucas Stach else 1380c997c3dfSLucas Stach address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1381c997c3dfSLucas Stach 13824df3000eSLucas Stach dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, 1383c997c3dfSLucas Stach gpu_read(gpu, address_reg)); 13844df3000eSLucas Stach } 13854df3000eSLucas Stach } 13864df3000eSLucas Stach 1387a8c21a54SThe etnaviv authors static irqreturn_t irq_handler(int irq, void *data) 1388a8c21a54SThe etnaviv authors { 1389a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = data; 1390a8c21a54SThe etnaviv authors irqreturn_t ret = IRQ_NONE; 1391a8c21a54SThe etnaviv authors 1392a8c21a54SThe etnaviv authors u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1393a8c21a54SThe etnaviv authors 1394a8c21a54SThe etnaviv authors if (intr != 0) { 1395a8c21a54SThe etnaviv authors int event; 1396a8c21a54SThe etnaviv authors 1397a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1398a8c21a54SThe etnaviv authors 1399a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1400a8c21a54SThe etnaviv authors 1401a8c21a54SThe etnaviv authors if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1402a8c21a54SThe etnaviv authors dev_err(gpu->dev, "AXI bus error\n"); 1403a8c21a54SThe etnaviv authors intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1404a8c21a54SThe etnaviv authors } 1405a8c21a54SThe etnaviv authors 1406128a9b1dSLucas Stach if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 14074df3000eSLucas Stach dump_mmu_fault(gpu); 1408128a9b1dSLucas Stach intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1409128a9b1dSLucas Stach } 1410128a9b1dSLucas Stach 1411a8c21a54SThe etnaviv authors while ((event = ffs(intr)) != 0) { 1412f54d1867SChris Wilson struct dma_fence *fence; 1413a8c21a54SThe etnaviv authors 1414a8c21a54SThe etnaviv authors event -= 1; 1415a8c21a54SThe etnaviv authors 1416a8c21a54SThe etnaviv authors intr &= ~(1 << event); 1417a8c21a54SThe etnaviv authors 1418a8c21a54SThe etnaviv authors dev_dbg(gpu->dev, "event %u\n", event); 1419a8c21a54SThe etnaviv authors 1420357713ceSChristian Gmeiner if (gpu->event[event].sync_point) { 1421357713ceSChristian Gmeiner gpu->sync_point_event = event; 1422a7790d78SLucas Stach queue_work(gpu->wq, &gpu->sync_point_work); 1423357713ceSChristian Gmeiner } 1424357713ceSChristian Gmeiner 1425a8c21a54SThe etnaviv authors fence = gpu->event[event].fence; 142668dc0b29SChristian Gmeiner if (!fence) 142768dc0b29SChristian Gmeiner continue; 142868dc0b29SChristian Gmeiner 1429a8c21a54SThe etnaviv authors gpu->event[event].fence = NULL; 1430a8c21a54SThe etnaviv authors 1431a8c21a54SThe etnaviv authors /* 1432a8c21a54SThe etnaviv authors * Events can be processed out of order. Eg, 1433a8c21a54SThe etnaviv authors * - allocate and queue event 0 1434a8c21a54SThe etnaviv authors * - allocate event 1 1435a8c21a54SThe etnaviv authors * - event 0 completes, we process it 1436a8c21a54SThe etnaviv authors * - allocate and queue event 0 1437a8c21a54SThe etnaviv authors * - event 1 and event 0 complete 1438a8c21a54SThe etnaviv authors * we can end up processing event 0 first, then 1. 1439a8c21a54SThe etnaviv authors */ 1440a8c21a54SThe etnaviv authors if (fence_after(fence->seqno, gpu->completed_fence)) 1441a8c21a54SThe etnaviv authors gpu->completed_fence = fence->seqno; 14428bc4d885SLucas Stach dma_fence_signal(fence); 1443a8c21a54SThe etnaviv authors 1444a8c21a54SThe etnaviv authors event_free(gpu, event); 1445a8c21a54SThe etnaviv authors } 1446a8c21a54SThe etnaviv authors 1447a8c21a54SThe etnaviv authors ret = IRQ_HANDLED; 1448a8c21a54SThe etnaviv authors } 1449a8c21a54SThe etnaviv authors 1450a8c21a54SThe etnaviv authors return ret; 1451a8c21a54SThe etnaviv authors } 1452a8c21a54SThe etnaviv authors 1453a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1454a8c21a54SThe etnaviv authors { 1455a8c21a54SThe etnaviv authors int ret; 1456a8c21a54SThe etnaviv authors 145765f037e8SLucas Stach if (gpu->clk_reg) { 145865f037e8SLucas Stach ret = clk_prepare_enable(gpu->clk_reg); 145965f037e8SLucas Stach if (ret) 146065f037e8SLucas Stach return ret; 146165f037e8SLucas Stach } 146265f037e8SLucas Stach 14639c7310c0SLucas Stach if (gpu->clk_bus) { 14649c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_bus); 1465a8c21a54SThe etnaviv authors if (ret) 1466a8c21a54SThe etnaviv authors return ret; 1467a8c21a54SThe etnaviv authors } 1468a8c21a54SThe etnaviv authors 14699c7310c0SLucas Stach if (gpu->clk_core) { 14709c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_core); 14719c7310c0SLucas Stach if (ret) 14729c7310c0SLucas Stach goto disable_clk_bus; 14739c7310c0SLucas Stach } 14749c7310c0SLucas Stach 14759c7310c0SLucas Stach if (gpu->clk_shader) { 14769c7310c0SLucas Stach ret = clk_prepare_enable(gpu->clk_shader); 14779c7310c0SLucas Stach if (ret) 14789c7310c0SLucas Stach goto disable_clk_core; 14799c7310c0SLucas Stach } 14809c7310c0SLucas Stach 1481a8c21a54SThe etnaviv authors return 0; 14829c7310c0SLucas Stach 14839c7310c0SLucas Stach disable_clk_core: 14849c7310c0SLucas Stach if (gpu->clk_core) 14859c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 14869c7310c0SLucas Stach disable_clk_bus: 14879c7310c0SLucas Stach if (gpu->clk_bus) 14889c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 14899c7310c0SLucas Stach 14909c7310c0SLucas Stach return ret; 1491a8c21a54SThe etnaviv authors } 1492a8c21a54SThe etnaviv authors 1493a8c21a54SThe etnaviv authors static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1494a8c21a54SThe etnaviv authors { 14959c7310c0SLucas Stach if (gpu->clk_shader) 14969c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_shader); 14979c7310c0SLucas Stach if (gpu->clk_core) 14989c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_core); 14999c7310c0SLucas Stach if (gpu->clk_bus) 15009c7310c0SLucas Stach clk_disable_unprepare(gpu->clk_bus); 150165f037e8SLucas Stach if (gpu->clk_reg) 150265f037e8SLucas Stach clk_disable_unprepare(gpu->clk_reg); 1503a8c21a54SThe etnaviv authors 1504a8c21a54SThe etnaviv authors return 0; 1505a8c21a54SThe etnaviv authors } 1506a8c21a54SThe etnaviv authors 1507b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1508b88163e3SLucas Stach { 1509b88163e3SLucas Stach unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1510b88163e3SLucas Stach 1511b88163e3SLucas Stach do { 1512b88163e3SLucas Stach u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1513b88163e3SLucas Stach 1514b88163e3SLucas Stach if ((idle & gpu->idle_mask) == gpu->idle_mask) 1515b88163e3SLucas Stach return 0; 1516b88163e3SLucas Stach 1517b88163e3SLucas Stach if (time_is_before_jiffies(timeout)) { 1518b88163e3SLucas Stach dev_warn(gpu->dev, 1519b88163e3SLucas Stach "timed out waiting for idle: idle=0x%x\n", 1520b88163e3SLucas Stach idle); 1521b88163e3SLucas Stach return -ETIMEDOUT; 1522b88163e3SLucas Stach } 1523b88163e3SLucas Stach 1524b88163e3SLucas Stach udelay(5); 1525b88163e3SLucas Stach } while (1); 1526b88163e3SLucas Stach } 1527b88163e3SLucas Stach 1528a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1529a8c21a54SThe etnaviv authors { 15302f9225dbSLucas Stach if (gpu->buffer.suballoc) { 1531a8c21a54SThe etnaviv authors /* Replace the last WAIT with END */ 153240c27bdeSLucas Stach mutex_lock(&gpu->lock); 1533a8c21a54SThe etnaviv authors etnaviv_buffer_end(gpu); 153440c27bdeSLucas Stach mutex_unlock(&gpu->lock); 1535a8c21a54SThe etnaviv authors 1536a8c21a54SThe etnaviv authors /* 1537a8c21a54SThe etnaviv authors * We know that only the FE is busy here, this should 1538a8c21a54SThe etnaviv authors * happen quickly (as the WAIT is only 200 cycles). If 1539a8c21a54SThe etnaviv authors * we fail, just warn and continue. 1540a8c21a54SThe etnaviv authors */ 1541b88163e3SLucas Stach etnaviv_gpu_wait_idle(gpu, 100); 1542a8c21a54SThe etnaviv authors } 1543a8c21a54SThe etnaviv authors 1544a8c21a54SThe etnaviv authors return etnaviv_gpu_clk_disable(gpu); 1545a8c21a54SThe etnaviv authors } 1546a8c21a54SThe etnaviv authors 1547a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1548a8c21a54SThe etnaviv authors static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1549a8c21a54SThe etnaviv authors { 1550a8c21a54SThe etnaviv authors int ret; 1551a8c21a54SThe etnaviv authors 1552a8c21a54SThe etnaviv authors ret = mutex_lock_killable(&gpu->lock); 1553a8c21a54SThe etnaviv authors if (ret) 1554a8c21a54SThe etnaviv authors return ret; 1555a8c21a54SThe etnaviv authors 1556bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1557a8c21a54SThe etnaviv authors etnaviv_gpu_hw_init(gpu); 1558a8c21a54SThe etnaviv authors 15594375ffffSLucas Stach gpu->lastctx = NULL; 1560f6086311SRussell King gpu->exec_state = -1; 1561a8c21a54SThe etnaviv authors 1562a8c21a54SThe etnaviv authors mutex_unlock(&gpu->lock); 1563a8c21a54SThe etnaviv authors 1564a8c21a54SThe etnaviv authors return 0; 1565a8c21a54SThe etnaviv authors } 1566a8c21a54SThe etnaviv authors #endif 1567a8c21a54SThe etnaviv authors 1568bcdfb5e5SRussell King static int 1569bcdfb5e5SRussell King etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1570bcdfb5e5SRussell King unsigned long *state) 1571bcdfb5e5SRussell King { 1572bcdfb5e5SRussell King *state = 6; 1573bcdfb5e5SRussell King 1574bcdfb5e5SRussell King return 0; 1575bcdfb5e5SRussell King } 1576bcdfb5e5SRussell King 1577bcdfb5e5SRussell King static int 1578bcdfb5e5SRussell King etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1579bcdfb5e5SRussell King unsigned long *state) 1580bcdfb5e5SRussell King { 1581bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1582bcdfb5e5SRussell King 1583bcdfb5e5SRussell King *state = gpu->freq_scale; 1584bcdfb5e5SRussell King 1585bcdfb5e5SRussell King return 0; 1586bcdfb5e5SRussell King } 1587bcdfb5e5SRussell King 1588bcdfb5e5SRussell King static int 1589bcdfb5e5SRussell King etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1590bcdfb5e5SRussell King unsigned long state) 1591bcdfb5e5SRussell King { 1592bcdfb5e5SRussell King struct etnaviv_gpu *gpu = cdev->devdata; 1593bcdfb5e5SRussell King 1594bcdfb5e5SRussell King mutex_lock(&gpu->lock); 1595bcdfb5e5SRussell King gpu->freq_scale = state; 1596bcdfb5e5SRussell King if (!pm_runtime_suspended(gpu->dev)) 1597bcdfb5e5SRussell King etnaviv_gpu_update_clock(gpu); 1598bcdfb5e5SRussell King mutex_unlock(&gpu->lock); 1599bcdfb5e5SRussell King 1600bcdfb5e5SRussell King return 0; 1601bcdfb5e5SRussell King } 1602bcdfb5e5SRussell King 1603bcdfb5e5SRussell King static struct thermal_cooling_device_ops cooling_ops = { 1604bcdfb5e5SRussell King .get_max_state = etnaviv_gpu_cooling_get_max_state, 1605bcdfb5e5SRussell King .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1606bcdfb5e5SRussell King .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1607bcdfb5e5SRussell King }; 1608bcdfb5e5SRussell King 1609a8c21a54SThe etnaviv authors static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1610a8c21a54SThe etnaviv authors void *data) 1611a8c21a54SThe etnaviv authors { 1612a8c21a54SThe etnaviv authors struct drm_device *drm = data; 1613a8c21a54SThe etnaviv authors struct etnaviv_drm_private *priv = drm->dev_private; 1614a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1615a8c21a54SThe etnaviv authors int ret; 1616a8c21a54SThe etnaviv authors 161749b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1618bcdfb5e5SRussell King gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1619bcdfb5e5SRussell King (char *)dev_name(dev), gpu, &cooling_ops); 1620bcdfb5e5SRussell King if (IS_ERR(gpu->cooling)) 1621bcdfb5e5SRussell King return PTR_ERR(gpu->cooling); 16225247e2aaSLucas Stach } 1623bcdfb5e5SRussell King 1624a7790d78SLucas Stach gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1625a7790d78SLucas Stach if (!gpu->wq) { 1626e93b6deeSLucas Stach ret = -ENOMEM; 1627e93b6deeSLucas Stach goto out_thermal; 1628a7790d78SLucas Stach } 1629a7790d78SLucas Stach 1630e93b6deeSLucas Stach ret = etnaviv_sched_init(gpu); 1631e93b6deeSLucas Stach if (ret) 1632e93b6deeSLucas Stach goto out_workqueue; 1633e93b6deeSLucas Stach 1634a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1635a8c21a54SThe etnaviv authors ret = pm_runtime_get_sync(gpu->dev); 1636a8c21a54SThe etnaviv authors #else 1637a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1638a8c21a54SThe etnaviv authors #endif 1639e93b6deeSLucas Stach if (ret < 0) 1640e93b6deeSLucas Stach goto out_sched; 1641e93b6deeSLucas Stach 1642a8c21a54SThe etnaviv authors 1643a8c21a54SThe etnaviv authors gpu->drm = drm; 1644f54d1867SChris Wilson gpu->fence_context = dma_fence_context_alloc(1); 16458bc4d885SLucas Stach idr_init(&gpu->fence_idr); 1646a8c21a54SThe etnaviv authors spin_lock_init(&gpu->fence_spinlock); 1647a8c21a54SThe etnaviv authors 1648357713ceSChristian Gmeiner INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1649a8c21a54SThe etnaviv authors init_waitqueue_head(&gpu->fence_event); 1650a8c21a54SThe etnaviv authors 1651a8c21a54SThe etnaviv authors priv->gpu[priv->num_gpus++] = gpu; 1652a8c21a54SThe etnaviv authors 1653a8c21a54SThe etnaviv authors pm_runtime_mark_last_busy(gpu->dev); 1654a8c21a54SThe etnaviv authors pm_runtime_put_autosuspend(gpu->dev); 1655a8c21a54SThe etnaviv authors 1656a8c21a54SThe etnaviv authors return 0; 1657e93b6deeSLucas Stach 1658e93b6deeSLucas Stach out_sched: 1659e93b6deeSLucas Stach etnaviv_sched_fini(gpu); 1660e93b6deeSLucas Stach 1661e93b6deeSLucas Stach out_workqueue: 1662e93b6deeSLucas Stach destroy_workqueue(gpu->wq); 1663e93b6deeSLucas Stach 1664e93b6deeSLucas Stach out_thermal: 1665e93b6deeSLucas Stach if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1666e93b6deeSLucas Stach thermal_cooling_device_unregister(gpu->cooling); 1667e93b6deeSLucas Stach 1668e93b6deeSLucas Stach return ret; 1669a8c21a54SThe etnaviv authors } 1670a8c21a54SThe etnaviv authors 1671a8c21a54SThe etnaviv authors static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1672a8c21a54SThe etnaviv authors void *data) 1673a8c21a54SThe etnaviv authors { 1674a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1675a8c21a54SThe etnaviv authors 1676a8c21a54SThe etnaviv authors DBG("%s", dev_name(gpu->dev)); 1677a8c21a54SThe etnaviv authors 1678a7790d78SLucas Stach flush_workqueue(gpu->wq); 1679a7790d78SLucas Stach destroy_workqueue(gpu->wq); 1680a7790d78SLucas Stach 1681e93b6deeSLucas Stach etnaviv_sched_fini(gpu); 1682e93b6deeSLucas Stach 1683a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1684a8c21a54SThe etnaviv authors pm_runtime_get_sync(gpu->dev); 1685a8c21a54SThe etnaviv authors pm_runtime_put_sync_suspend(gpu->dev); 1686a8c21a54SThe etnaviv authors #else 1687a8c21a54SThe etnaviv authors etnaviv_gpu_hw_suspend(gpu); 1688a8c21a54SThe etnaviv authors #endif 1689a8c21a54SThe etnaviv authors 16902f9225dbSLucas Stach if (gpu->buffer.suballoc) 16912f9225dbSLucas Stach etnaviv_cmdbuf_free(&gpu->buffer); 1692a8c21a54SThe etnaviv authors 1693e66774ddSLucas Stach if (gpu->cmdbuf_suballoc) { 1694e66774ddSLucas Stach etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); 1695e66774ddSLucas Stach gpu->cmdbuf_suballoc = NULL; 1696e66774ddSLucas Stach } 1697e66774ddSLucas Stach 1698a8c21a54SThe etnaviv authors if (gpu->mmu) { 1699a8c21a54SThe etnaviv authors etnaviv_iommu_destroy(gpu->mmu); 1700a8c21a54SThe etnaviv authors gpu->mmu = NULL; 1701a8c21a54SThe etnaviv authors } 1702a8c21a54SThe etnaviv authors 1703a8c21a54SThe etnaviv authors gpu->drm = NULL; 17048bc4d885SLucas Stach idr_destroy(&gpu->fence_idr); 1705bcdfb5e5SRussell King 170649b82c38SPhilipp Zabel if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1707bcdfb5e5SRussell King thermal_cooling_device_unregister(gpu->cooling); 1708bcdfb5e5SRussell King gpu->cooling = NULL; 1709a8c21a54SThe etnaviv authors } 1710a8c21a54SThe etnaviv authors 1711a8c21a54SThe etnaviv authors static const struct component_ops gpu_ops = { 1712a8c21a54SThe etnaviv authors .bind = etnaviv_gpu_bind, 1713a8c21a54SThe etnaviv authors .unbind = etnaviv_gpu_unbind, 1714a8c21a54SThe etnaviv authors }; 1715a8c21a54SThe etnaviv authors 1716a8c21a54SThe etnaviv authors static const struct of_device_id etnaviv_gpu_match[] = { 1717a8c21a54SThe etnaviv authors { 1718a8c21a54SThe etnaviv authors .compatible = "vivante,gc" 1719a8c21a54SThe etnaviv authors }, 1720a8c21a54SThe etnaviv authors { /* sentinel */ } 1721a8c21a54SThe etnaviv authors }; 1722246774d1SLucas Stach MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1723a8c21a54SThe etnaviv authors 1724a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1725a8c21a54SThe etnaviv authors { 1726a8c21a54SThe etnaviv authors struct device *dev = &pdev->dev; 1727a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu; 1728a98b1e78SLucas Stach struct resource *res; 1729dc227890SFabio Estevam int err; 1730a8c21a54SThe etnaviv authors 1731a8c21a54SThe etnaviv authors gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1732a8c21a54SThe etnaviv authors if (!gpu) 1733a8c21a54SThe etnaviv authors return -ENOMEM; 1734a8c21a54SThe etnaviv authors 1735a8c21a54SThe etnaviv authors gpu->dev = &pdev->dev; 1736a8c21a54SThe etnaviv authors mutex_init(&gpu->lock); 1737a0780bb1SLucas Stach mutex_init(&gpu->fence_lock); 1738a8c21a54SThe etnaviv authors 1739a8c21a54SThe etnaviv authors /* Map registers: */ 1740a98b1e78SLucas Stach res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1741a98b1e78SLucas Stach gpu->mmio = devm_ioremap_resource(&pdev->dev, res); 1742a8c21a54SThe etnaviv authors if (IS_ERR(gpu->mmio)) 1743a8c21a54SThe etnaviv authors return PTR_ERR(gpu->mmio); 1744a8c21a54SThe etnaviv authors 1745a8c21a54SThe etnaviv authors /* Get Interrupt: */ 1746a8c21a54SThe etnaviv authors gpu->irq = platform_get_irq(pdev, 0); 1747a8c21a54SThe etnaviv authors if (gpu->irq < 0) { 1748db60eda3SFabio Estevam dev_err(dev, "failed to get irq: %d\n", gpu->irq); 1749db60eda3SFabio Estevam return gpu->irq; 1750a8c21a54SThe etnaviv authors } 1751a8c21a54SThe etnaviv authors 1752a8c21a54SThe etnaviv authors err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1753a8c21a54SThe etnaviv authors dev_name(gpu->dev), gpu); 1754a8c21a54SThe etnaviv authors if (err) { 1755a8c21a54SThe etnaviv authors dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1756db60eda3SFabio Estevam return err; 1757a8c21a54SThe etnaviv authors } 1758a8c21a54SThe etnaviv authors 1759a8c21a54SThe etnaviv authors /* Get Clocks: */ 176065f037e8SLucas Stach gpu->clk_reg = devm_clk_get(&pdev->dev, "reg"); 176165f037e8SLucas Stach DBG("clk_reg: %p", gpu->clk_reg); 176265f037e8SLucas Stach if (IS_ERR(gpu->clk_reg)) 176365f037e8SLucas Stach gpu->clk_reg = NULL; 176465f037e8SLucas Stach 1765a8c21a54SThe etnaviv authors gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1766a8c21a54SThe etnaviv authors DBG("clk_bus: %p", gpu->clk_bus); 1767a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_bus)) 1768a8c21a54SThe etnaviv authors gpu->clk_bus = NULL; 1769a8c21a54SThe etnaviv authors 1770a8c21a54SThe etnaviv authors gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1771a8c21a54SThe etnaviv authors DBG("clk_core: %p", gpu->clk_core); 1772a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_core)) 1773a8c21a54SThe etnaviv authors gpu->clk_core = NULL; 1774d79fd1ccSLucas Stach gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1775a8c21a54SThe etnaviv authors 1776a8c21a54SThe etnaviv authors gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); 1777a8c21a54SThe etnaviv authors DBG("clk_shader: %p", gpu->clk_shader); 1778a8c21a54SThe etnaviv authors if (IS_ERR(gpu->clk_shader)) 1779a8c21a54SThe etnaviv authors gpu->clk_shader = NULL; 1780d79fd1ccSLucas Stach gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1781a8c21a54SThe etnaviv authors 1782a8c21a54SThe etnaviv authors /* TODO: figure out max mapped size */ 1783a8c21a54SThe etnaviv authors dev_set_drvdata(dev, gpu); 1784a8c21a54SThe etnaviv authors 1785a8c21a54SThe etnaviv authors /* 1786a8c21a54SThe etnaviv authors * We treat the device as initially suspended. The runtime PM 1787a8c21a54SThe etnaviv authors * autosuspend delay is rather arbitary: no measurements have 1788a8c21a54SThe etnaviv authors * yet been performed to determine an appropriate value. 1789a8c21a54SThe etnaviv authors */ 1790a8c21a54SThe etnaviv authors pm_runtime_use_autosuspend(gpu->dev); 1791a8c21a54SThe etnaviv authors pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1792a8c21a54SThe etnaviv authors pm_runtime_enable(gpu->dev); 1793a8c21a54SThe etnaviv authors 1794a8c21a54SThe etnaviv authors err = component_add(&pdev->dev, &gpu_ops); 1795a8c21a54SThe etnaviv authors if (err < 0) { 1796a8c21a54SThe etnaviv authors dev_err(&pdev->dev, "failed to register component: %d\n", err); 1797db60eda3SFabio Estevam return err; 1798a8c21a54SThe etnaviv authors } 1799a8c21a54SThe etnaviv authors 1800a8c21a54SThe etnaviv authors return 0; 1801a8c21a54SThe etnaviv authors } 1802a8c21a54SThe etnaviv authors 1803a8c21a54SThe etnaviv authors static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1804a8c21a54SThe etnaviv authors { 1805a8c21a54SThe etnaviv authors component_del(&pdev->dev, &gpu_ops); 1806a8c21a54SThe etnaviv authors pm_runtime_disable(&pdev->dev); 1807a8c21a54SThe etnaviv authors return 0; 1808a8c21a54SThe etnaviv authors } 1809a8c21a54SThe etnaviv authors 1810a8c21a54SThe etnaviv authors #ifdef CONFIG_PM 1811a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_suspend(struct device *dev) 1812a8c21a54SThe etnaviv authors { 1813a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1814a8c21a54SThe etnaviv authors u32 idle, mask; 1815a8c21a54SThe etnaviv authors 1816a8c21a54SThe etnaviv authors /* If we have outstanding fences, we're not idle */ 1817a8c21a54SThe etnaviv authors if (gpu->completed_fence != gpu->active_fence) 1818a8c21a54SThe etnaviv authors return -EBUSY; 1819a8c21a54SThe etnaviv authors 1820a8c21a54SThe etnaviv authors /* Check whether the hardware (except FE) is idle */ 1821a8c21a54SThe etnaviv authors mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; 1822a8c21a54SThe etnaviv authors idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1823a8c21a54SThe etnaviv authors if (idle != mask) 1824a8c21a54SThe etnaviv authors return -EBUSY; 1825a8c21a54SThe etnaviv authors 1826a8c21a54SThe etnaviv authors return etnaviv_gpu_hw_suspend(gpu); 1827a8c21a54SThe etnaviv authors } 1828a8c21a54SThe etnaviv authors 1829a8c21a54SThe etnaviv authors static int etnaviv_gpu_rpm_resume(struct device *dev) 1830a8c21a54SThe etnaviv authors { 1831a8c21a54SThe etnaviv authors struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1832a8c21a54SThe etnaviv authors int ret; 1833a8c21a54SThe etnaviv authors 1834a8c21a54SThe etnaviv authors ret = etnaviv_gpu_clk_enable(gpu); 1835a8c21a54SThe etnaviv authors if (ret) 1836a8c21a54SThe etnaviv authors return ret; 1837a8c21a54SThe etnaviv authors 1838a8c21a54SThe etnaviv authors /* Re-initialise the basic hardware state */ 18392f9225dbSLucas Stach if (gpu->drm && gpu->buffer.suballoc) { 1840a8c21a54SThe etnaviv authors ret = etnaviv_gpu_hw_resume(gpu); 1841a8c21a54SThe etnaviv authors if (ret) { 1842a8c21a54SThe etnaviv authors etnaviv_gpu_clk_disable(gpu); 1843a8c21a54SThe etnaviv authors return ret; 1844a8c21a54SThe etnaviv authors } 1845a8c21a54SThe etnaviv authors } 1846a8c21a54SThe etnaviv authors 1847a8c21a54SThe etnaviv authors return 0; 1848a8c21a54SThe etnaviv authors } 1849a8c21a54SThe etnaviv authors #endif 1850a8c21a54SThe etnaviv authors 1851a8c21a54SThe etnaviv authors static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1852a8c21a54SThe etnaviv authors SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1853a8c21a54SThe etnaviv authors NULL) 1854a8c21a54SThe etnaviv authors }; 1855a8c21a54SThe etnaviv authors 1856a8c21a54SThe etnaviv authors struct platform_driver etnaviv_gpu_driver = { 1857a8c21a54SThe etnaviv authors .driver = { 1858a8c21a54SThe etnaviv authors .name = "etnaviv-gpu", 1859a8c21a54SThe etnaviv authors .owner = THIS_MODULE, 1860a8c21a54SThe etnaviv authors .pm = &etnaviv_gpu_pm_ops, 1861a8c21a54SThe etnaviv authors .of_match_table = etnaviv_gpu_match, 1862a8c21a54SThe etnaviv authors }, 1863a8c21a54SThe etnaviv authors .probe = etnaviv_gpu_platform_probe, 1864a8c21a54SThe etnaviv authors .remove = etnaviv_gpu_platform_remove, 1865a8c21a54SThe etnaviv authors .id_table = gpu_ids, 1866a8c21a54SThe etnaviv authors }; 1867