1 /* 2 * Copyright (C) 2014 Etnaviv Project 3 * Author: Christian Gmeiner <christian.gmeiner@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "etnaviv_cmdbuf.h" 19 #include "etnaviv_gpu.h" 20 #include "etnaviv_gem.h" 21 #include "etnaviv_mmu.h" 22 23 #include "common.xml.h" 24 #include "state.xml.h" 25 #include "state_hi.xml.h" 26 #include "state_3d.xml.h" 27 #include "cmdstream.xml.h" 28 29 /* 30 * Command Buffer helper: 31 */ 32 33 34 static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data) 35 { 36 u32 *vaddr = (u32 *)buffer->vaddr; 37 38 BUG_ON(buffer->user_size >= buffer->size); 39 40 vaddr[buffer->user_size / 4] = data; 41 buffer->user_size += 4; 42 } 43 44 static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer, 45 u32 reg, u32 value) 46 { 47 u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR; 48 49 buffer->user_size = ALIGN(buffer->user_size, 8); 50 51 /* write a register via cmd stream */ 52 OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE | 53 VIV_FE_LOAD_STATE_HEADER_COUNT(1) | 54 VIV_FE_LOAD_STATE_HEADER_OFFSET(index)); 55 OUT(buffer, value); 56 } 57 58 static inline void CMD_END(struct etnaviv_cmdbuf *buffer) 59 { 60 buffer->user_size = ALIGN(buffer->user_size, 8); 61 62 OUT(buffer, VIV_FE_END_HEADER_OP_END); 63 } 64 65 static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer) 66 { 67 buffer->user_size = ALIGN(buffer->user_size, 8); 68 69 OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200); 70 } 71 72 static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer, 73 u16 prefetch, u32 address) 74 { 75 buffer->user_size = ALIGN(buffer->user_size, 8); 76 77 OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK | 78 VIV_FE_LINK_HEADER_PREFETCH(prefetch)); 79 OUT(buffer, address); 80 } 81 82 static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer, 83 u32 from, u32 to) 84 { 85 buffer->user_size = ALIGN(buffer->user_size, 8); 86 87 OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL); 88 OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to)); 89 } 90 91 static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to) 92 { 93 CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN, 94 VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | 95 VIVS_GL_SEMAPHORE_TOKEN_TO(to)); 96 } 97 98 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, 99 struct etnaviv_cmdbuf *buffer, u8 pipe) 100 { 101 u32 flush = 0; 102 103 lockdep_assert_held(&gpu->lock); 104 105 /* 106 * This assumes that if we're switching to 2D, we're switching 107 * away from 3D, and vice versa. Hence, if we're switching to 108 * the 2D core, we need to flush the 3D depth and color caches, 109 * otherwise we need to flush the 2D pixel engine cache. 110 */ 111 if (gpu->exec_state == ETNA_PIPE_2D) 112 flush = VIVS_GL_FLUSH_CACHE_PE2D; 113 else if (gpu->exec_state == ETNA_PIPE_3D) 114 flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR; 115 116 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush); 117 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 118 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 119 120 CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT, 121 VIVS_GL_PIPE_SELECT_PIPE(pipe)); 122 } 123 124 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, 125 struct etnaviv_cmdbuf *buf, u32 off, u32 len) 126 { 127 u32 size = buf->size; 128 u32 *ptr = buf->vaddr + off; 129 130 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", 131 ptr, etnaviv_cmdbuf_get_va(buf) + off, size - len * 4 - off); 132 133 print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4, 134 ptr, len * 4, 0); 135 } 136 137 /* 138 * Safely replace the WAIT of a waitlink with a new command and argument. 139 * The GPU may be executing this WAIT while we're modifying it, so we have 140 * to write it in a specific order to avoid the GPU branching to somewhere 141 * else. 'wl_offset' is the offset to the first byte of the WAIT command. 142 */ 143 static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer, 144 unsigned int wl_offset, u32 cmd, u32 arg) 145 { 146 u32 *lw = buffer->vaddr + wl_offset; 147 148 lw[1] = arg; 149 mb(); 150 lw[0] = cmd; 151 mb(); 152 } 153 154 /* 155 * Ensure that there is space in the command buffer to contiguously write 156 * 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary. 157 */ 158 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, 159 struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords) 160 { 161 if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size) 162 buffer->user_size = 0; 163 164 return etnaviv_cmdbuf_get_va(buffer) + buffer->user_size; 165 } 166 167 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) 168 { 169 struct etnaviv_cmdbuf *buffer = &gpu->buffer; 170 171 lockdep_assert_held(&gpu->lock); 172 173 /* initialize buffer */ 174 buffer->user_size = 0; 175 176 CMD_WAIT(buffer); 177 CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) + 178 buffer->user_size - 4); 179 180 return buffer->user_size / 8; 181 } 182 183 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr) 184 { 185 struct etnaviv_cmdbuf *buffer = &gpu->buffer; 186 187 lockdep_assert_held(&gpu->lock); 188 189 buffer->user_size = 0; 190 191 if (gpu->identity.features & chipFeatures_PIPE_3D) { 192 CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT, 193 VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D)); 194 CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION, 195 mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K); 196 CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr); 197 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 198 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 199 } 200 201 if (gpu->identity.features & chipFeatures_PIPE_2D) { 202 CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT, 203 VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D)); 204 CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION, 205 mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K); 206 CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr); 207 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 208 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 209 } 210 211 CMD_END(buffer); 212 213 buffer->user_size = ALIGN(buffer->user_size, 8); 214 215 return buffer->user_size / 8; 216 } 217 218 u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu) 219 { 220 struct etnaviv_cmdbuf *buffer = &gpu->buffer; 221 222 lockdep_assert_held(&gpu->lock); 223 224 buffer->user_size = 0; 225 226 CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG, 227 VIVS_MMUv2_PTA_CONFIG_INDEX(0)); 228 229 CMD_END(buffer); 230 231 buffer->user_size = ALIGN(buffer->user_size, 8); 232 233 return buffer->user_size / 8; 234 } 235 236 void etnaviv_buffer_end(struct etnaviv_gpu *gpu) 237 { 238 struct etnaviv_cmdbuf *buffer = &gpu->buffer; 239 unsigned int waitlink_offset = buffer->user_size - 16; 240 u32 link_target, flush = 0; 241 242 lockdep_assert_held(&gpu->lock); 243 244 if (gpu->exec_state == ETNA_PIPE_2D) 245 flush = VIVS_GL_FLUSH_CACHE_PE2D; 246 else if (gpu->exec_state == ETNA_PIPE_3D) 247 flush = VIVS_GL_FLUSH_CACHE_DEPTH | 248 VIVS_GL_FLUSH_CACHE_COLOR | 249 VIVS_GL_FLUSH_CACHE_TEXTURE | 250 VIVS_GL_FLUSH_CACHE_TEXTUREVS | 251 VIVS_GL_FLUSH_CACHE_SHADER_L2; 252 253 if (flush) { 254 unsigned int dwords = 7; 255 256 link_target = etnaviv_buffer_reserve(gpu, buffer, dwords); 257 258 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 259 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 260 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush); 261 if (gpu->exec_state == ETNA_PIPE_3D) 262 CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE, 263 VIVS_TS_FLUSH_CACHE_FLUSH); 264 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 265 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 266 CMD_END(buffer); 267 268 etnaviv_buffer_replace_wait(buffer, waitlink_offset, 269 VIV_FE_LINK_HEADER_OP_LINK | 270 VIV_FE_LINK_HEADER_PREFETCH(dwords), 271 link_target); 272 } else { 273 /* Replace the last link-wait with an "END" command */ 274 etnaviv_buffer_replace_wait(buffer, waitlink_offset, 275 VIV_FE_END_HEADER_OP_END, 0); 276 } 277 } 278 279 /* Append a 'sync point' to the ring buffer. */ 280 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) 281 { 282 struct etnaviv_cmdbuf *buffer = &gpu->buffer; 283 unsigned int waitlink_offset = buffer->user_size - 16; 284 u32 dwords, target; 285 286 lockdep_assert_held(&gpu->lock); 287 288 /* 289 * We need at most 3 dwords in the return target: 290 * 1 event + 1 end + 1 wait + 1 link. 291 */ 292 dwords = 4; 293 target = etnaviv_buffer_reserve(gpu, buffer, dwords); 294 295 /* Signal sync point event */ 296 CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) | 297 VIVS_GL_EVENT_FROM_PE); 298 299 /* Stop the FE to 'pause' the GPU */ 300 CMD_END(buffer); 301 302 /* Append waitlink */ 303 CMD_WAIT(buffer); 304 CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) + 305 buffer->user_size - 4); 306 307 /* 308 * Kick off the 'sync point' command by replacing the previous 309 * WAIT with a link to the address in the ring buffer. 310 */ 311 etnaviv_buffer_replace_wait(buffer, waitlink_offset, 312 VIV_FE_LINK_HEADER_OP_LINK | 313 VIV_FE_LINK_HEADER_PREFETCH(dwords), 314 target); 315 } 316 317 /* Append a command buffer to the ring buffer. */ 318 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 319 unsigned int event, struct etnaviv_cmdbuf *cmdbuf) 320 { 321 struct etnaviv_cmdbuf *buffer = &gpu->buffer; 322 unsigned int waitlink_offset = buffer->user_size - 16; 323 u32 return_target, return_dwords; 324 u32 link_target, link_dwords; 325 bool switch_context = gpu->exec_state != exec_state; 326 327 lockdep_assert_held(&gpu->lock); 328 329 if (drm_debug & DRM_UT_DRIVER) 330 etnaviv_buffer_dump(gpu, buffer, 0, 0x50); 331 332 link_target = etnaviv_cmdbuf_get_va(cmdbuf); 333 link_dwords = cmdbuf->size / 8; 334 335 /* 336 * If we need maintanence prior to submitting this buffer, we will 337 * need to append a mmu flush load state, followed by a new 338 * link to this buffer - a total of four additional words. 339 */ 340 if (gpu->mmu->need_flush || switch_context) { 341 u32 target, extra_dwords; 342 343 /* link command */ 344 extra_dwords = 1; 345 346 /* flush command */ 347 if (gpu->mmu->need_flush) { 348 if (gpu->mmu->version == ETNAVIV_IOMMU_V1) 349 extra_dwords += 1; 350 else 351 extra_dwords += 3; 352 } 353 354 /* pipe switch commands */ 355 if (switch_context) 356 extra_dwords += 4; 357 358 target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords); 359 360 if (gpu->mmu->need_flush) { 361 /* Add the MMU flush */ 362 if (gpu->mmu->version == ETNAVIV_IOMMU_V1) { 363 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU, 364 VIVS_GL_FLUSH_MMU_FLUSH_FEMMU | 365 VIVS_GL_FLUSH_MMU_FLUSH_UNK1 | 366 VIVS_GL_FLUSH_MMU_FLUSH_UNK2 | 367 VIVS_GL_FLUSH_MMU_FLUSH_PEMMU | 368 VIVS_GL_FLUSH_MMU_FLUSH_UNK4); 369 } else { 370 CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION, 371 VIVS_MMUv2_CONFIGURATION_MODE_MASK | 372 VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK | 373 VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH); 374 CMD_SEM(buffer, SYNC_RECIPIENT_FE, 375 SYNC_RECIPIENT_PE); 376 CMD_STALL(buffer, SYNC_RECIPIENT_FE, 377 SYNC_RECIPIENT_PE); 378 } 379 380 gpu->mmu->need_flush = false; 381 } 382 383 if (switch_context) { 384 etnaviv_cmd_select_pipe(gpu, buffer, exec_state); 385 gpu->exec_state = exec_state; 386 } 387 388 /* And the link to the submitted buffer */ 389 CMD_LINK(buffer, link_dwords, link_target); 390 391 /* Update the link target to point to above instructions */ 392 link_target = target; 393 link_dwords = extra_dwords; 394 } 395 396 /* 397 * Append a LINK to the submitted command buffer to return to 398 * the ring buffer. return_target is the ring target address. 399 * We need at most 7 dwords in the return target: 2 cache flush + 400 * 2 semaphore stall + 1 event + 1 wait + 1 link. 401 */ 402 return_dwords = 7; 403 return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords); 404 CMD_LINK(cmdbuf, return_dwords, return_target); 405 406 /* 407 * Append a cache flush, stall, event, wait and link pointing back to 408 * the wait command to the ring buffer. 409 */ 410 if (gpu->exec_state == ETNA_PIPE_2D) { 411 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, 412 VIVS_GL_FLUSH_CACHE_PE2D); 413 } else { 414 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, 415 VIVS_GL_FLUSH_CACHE_DEPTH | 416 VIVS_GL_FLUSH_CACHE_COLOR); 417 CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE, 418 VIVS_TS_FLUSH_CACHE_FLUSH); 419 } 420 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 421 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 422 CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) | 423 VIVS_GL_EVENT_FROM_PE); 424 CMD_WAIT(buffer); 425 CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) + 426 buffer->user_size - 4); 427 428 if (drm_debug & DRM_UT_DRIVER) 429 pr_info("stream link to 0x%08x @ 0x%08x %p\n", 430 return_target, etnaviv_cmdbuf_get_va(cmdbuf), 431 cmdbuf->vaddr); 432 433 if (drm_debug & DRM_UT_DRIVER) { 434 print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4, 435 cmdbuf->vaddr, cmdbuf->size, 0); 436 437 pr_info("link op: %p\n", buffer->vaddr + waitlink_offset); 438 pr_info("addr: 0x%08x\n", link_target); 439 pr_info("back: 0x%08x\n", return_target); 440 pr_info("event: %d\n", event); 441 } 442 443 /* 444 * Kick off the submitted command by replacing the previous 445 * WAIT with a link to the address in the ring buffer. 446 */ 447 etnaviv_buffer_replace_wait(buffer, waitlink_offset, 448 VIV_FE_LINK_HEADER_OP_LINK | 449 VIV_FE_LINK_HEADER_PREFETCH(link_dwords), 450 link_target); 451 452 if (drm_debug & DRM_UT_DRIVER) 453 etnaviv_buffer_dump(gpu, buffer, 0, 0x50); 454 455 gpu->lastctx = cmdbuf->ctx; 456 } 457