1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/dma-buf.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/spi/spi.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_format_helper.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_mipi_dbi.h> 24 #include <drm/drm_modes.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_rect.h> 27 #include <video/mipi_display.h> 28 29 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 30 31 #define DCS_POWER_MODE_DISPLAY BIT(2) 32 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 33 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 34 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 35 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 36 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 37 38 /** 39 * DOC: overview 40 * 41 * This library provides helpers for MIPI Display Bus Interface (DBI) 42 * compatible display controllers. 43 * 44 * Many controllers for tiny lcd displays are MIPI compliant and can use this 45 * library. If a controller uses registers 0x2A and 0x2B to set the area to 46 * update and uses register 0x2C to write to frame memory, it is most likely 47 * MIPI compliant. 48 * 49 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 50 * 51 * There are 3 MIPI DBI implementation types: 52 * 53 * A. Motorola 6800 type parallel bus 54 * 55 * B. Intel 8080 type parallel bus 56 * 57 * C. SPI type with 3 options: 58 * 59 * 1. 9-bit with the Data/Command signal as the ninth bit 60 * 2. Same as above except it's sent as 16 bits 61 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 62 * 63 * Currently mipi_dbi only supports Type C options 1 and 3 with 64 * mipi_dbi_spi_init(). 65 */ 66 67 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 68 ({ \ 69 if (!len) \ 70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 71 else if (len <= 32) \ 72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 73 else \ 74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 75 }) 76 77 static const u8 mipi_dbi_dcs_read_commands[] = { 78 MIPI_DCS_GET_DISPLAY_ID, 79 MIPI_DCS_GET_RED_CHANNEL, 80 MIPI_DCS_GET_GREEN_CHANNEL, 81 MIPI_DCS_GET_BLUE_CHANNEL, 82 MIPI_DCS_GET_DISPLAY_STATUS, 83 MIPI_DCS_GET_POWER_MODE, 84 MIPI_DCS_GET_ADDRESS_MODE, 85 MIPI_DCS_GET_PIXEL_FORMAT, 86 MIPI_DCS_GET_DISPLAY_MODE, 87 MIPI_DCS_GET_SIGNAL_MODE, 88 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 89 MIPI_DCS_READ_MEMORY_START, 90 MIPI_DCS_READ_MEMORY_CONTINUE, 91 MIPI_DCS_GET_SCANLINE, 92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 93 MIPI_DCS_GET_CONTROL_DISPLAY, 94 MIPI_DCS_GET_POWER_SAVE, 95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 96 MIPI_DCS_READ_DDB_START, 97 MIPI_DCS_READ_DDB_CONTINUE, 98 0, /* sentinel */ 99 }; 100 101 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 102 { 103 unsigned int i; 104 105 if (!dbi->read_commands) 106 return false; 107 108 for (i = 0; i < 0xff; i++) { 109 if (!dbi->read_commands[i]) 110 return false; 111 if (cmd == dbi->read_commands[i]) 112 return true; 113 } 114 115 return false; 116 } 117 118 /** 119 * mipi_dbi_command_read - MIPI DCS read command 120 * @dbi: MIPI DBI structure 121 * @cmd: Command 122 * @val: Value read 123 * 124 * Send MIPI DCS read command to the controller. 125 * 126 * Returns: 127 * Zero on success, negative error code on failure. 128 */ 129 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 130 { 131 if (!dbi->read_commands) 132 return -EACCES; 133 134 if (!mipi_dbi_command_is_read(dbi, cmd)) 135 return -EINVAL; 136 137 return mipi_dbi_command_buf(dbi, cmd, val, 1); 138 } 139 EXPORT_SYMBOL(mipi_dbi_command_read); 140 141 /** 142 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 143 * @dbi: MIPI DBI structure 144 * @cmd: Command 145 * @data: Parameter buffer 146 * @len: Buffer length 147 * 148 * Returns: 149 * Zero on success, negative error code on failure. 150 */ 151 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 152 { 153 u8 *cmdbuf; 154 int ret; 155 156 /* SPI requires dma-safe buffers */ 157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 158 if (!cmdbuf) 159 return -ENOMEM; 160 161 mutex_lock(&dbi->cmdlock); 162 ret = dbi->command(dbi, cmdbuf, data, len); 163 mutex_unlock(&dbi->cmdlock); 164 165 kfree(cmdbuf); 166 167 return ret; 168 } 169 EXPORT_SYMBOL(mipi_dbi_command_buf); 170 171 /* This should only be used by mipi_dbi_command() */ 172 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 173 size_t len) 174 { 175 u8 *buf; 176 int ret; 177 178 buf = kmemdup(data, len, GFP_KERNEL); 179 if (!buf) 180 return -ENOMEM; 181 182 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 183 184 kfree(buf); 185 186 return ret; 187 } 188 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 189 190 /** 191 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 192 * @dst: The destination buffer 193 * @fb: The source framebuffer 194 * @clip: Clipping rectangle of the area to be copied 195 * @swap: When true, swap MSB/LSB of 16-bit values 196 * 197 * Returns: 198 * Zero on success, negative error code on failure. 199 */ 200 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb, 201 struct drm_rect *clip, bool swap) 202 { 203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 204 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem); 205 struct dma_buf_attachment *import_attach = gem->import_attach; 206 struct drm_format_name_buf format_name; 207 void *src = cma_obj->vaddr; 208 int ret = 0; 209 210 if (import_attach) { 211 ret = dma_buf_begin_cpu_access(import_attach->dmabuf, 212 DMA_FROM_DEVICE); 213 if (ret) 214 return ret; 215 } 216 217 switch (fb->format->format) { 218 case DRM_FORMAT_RGB565: 219 if (swap) 220 drm_fb_swab16(dst, src, fb, clip); 221 else 222 drm_fb_memcpy(dst, src, fb, clip); 223 break; 224 case DRM_FORMAT_XRGB8888: 225 drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap); 226 break; 227 default: 228 dev_err_once(fb->dev->dev, "Format is not supported: %s\n", 229 drm_get_format_name(fb->format->format, 230 &format_name)); 231 return -EINVAL; 232 } 233 234 if (import_attach) 235 ret = dma_buf_end_cpu_access(import_attach->dmabuf, 236 DMA_FROM_DEVICE); 237 return ret; 238 } 239 EXPORT_SYMBOL(mipi_dbi_buf_copy); 240 241 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 242 unsigned int xs, unsigned int xe, 243 unsigned int ys, unsigned int ye) 244 { 245 struct mipi_dbi *dbi = &dbidev->dbi; 246 247 xs += dbidev->left_offset; 248 xe += dbidev->left_offset; 249 ys += dbidev->top_offset; 250 ye += dbidev->top_offset; 251 252 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 253 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 254 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 255 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 256 } 257 258 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) 259 { 260 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 261 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem); 262 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 263 unsigned int height = rect->y2 - rect->y1; 264 unsigned int width = rect->x2 - rect->x1; 265 struct mipi_dbi *dbi = &dbidev->dbi; 266 bool swap = dbi->swap_bytes; 267 int idx, ret = 0; 268 bool full; 269 void *tr; 270 271 if (!dbidev->enabled) 272 return; 273 274 if (!drm_dev_enter(fb->dev, &idx)) 275 return; 276 277 full = width == fb->width && height == fb->height; 278 279 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 280 281 if (!dbi->dc || !full || swap || 282 fb->format->format == DRM_FORMAT_XRGB8888) { 283 tr = dbidev->tx_buf; 284 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap); 285 if (ret) 286 goto err_msg; 287 } else { 288 tr = cma_obj->vaddr; 289 } 290 291 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 292 rect->y2 - 1); 293 294 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, 295 width * height * 2); 296 err_msg: 297 if (ret) 298 dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret); 299 300 drm_dev_exit(idx); 301 } 302 303 /** 304 * mipi_dbi_pipe_update - Display pipe update helper 305 * @pipe: Simple display pipe 306 * @old_state: Old plane state 307 * 308 * This function handles framebuffer flushing and vblank events. Drivers can use 309 * this as their &drm_simple_display_pipe_funcs->update callback. 310 */ 311 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, 312 struct drm_plane_state *old_state) 313 { 314 struct drm_plane_state *state = pipe->plane.state; 315 struct drm_rect rect; 316 317 if (drm_atomic_helper_damage_merged(old_state, state, &rect)) 318 mipi_dbi_fb_dirty(state->fb, &rect); 319 } 320 EXPORT_SYMBOL(mipi_dbi_pipe_update); 321 322 /** 323 * mipi_dbi_enable_flush - MIPI DBI enable helper 324 * @dbidev: MIPI DBI device structure 325 * @crtc_state: CRTC state 326 * @plane_state: Plane state 327 * 328 * This function sets &mipi_dbi->enabled, flushes the whole framebuffer and 329 * enables the backlight. Drivers can use this in their 330 * &drm_simple_display_pipe_funcs->enable callback. 331 * 332 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom 333 * framebuffer flushing, can't use this function since they both use the same 334 * flushing code. 335 */ 336 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, 337 struct drm_crtc_state *crtc_state, 338 struct drm_plane_state *plane_state) 339 { 340 struct drm_framebuffer *fb = plane_state->fb; 341 struct drm_rect rect = { 342 .x1 = 0, 343 .x2 = fb->width, 344 .y1 = 0, 345 .y2 = fb->height, 346 }; 347 int idx; 348 349 if (!drm_dev_enter(&dbidev->drm, &idx)) 350 return; 351 352 dbidev->enabled = true; 353 mipi_dbi_fb_dirty(fb, &rect); 354 backlight_enable(dbidev->backlight); 355 356 drm_dev_exit(idx); 357 } 358 EXPORT_SYMBOL(mipi_dbi_enable_flush); 359 360 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 361 { 362 struct drm_device *drm = &dbidev->drm; 363 u16 height = drm->mode_config.min_height; 364 u16 width = drm->mode_config.min_width; 365 struct mipi_dbi *dbi = &dbidev->dbi; 366 size_t len = width * height * 2; 367 int idx; 368 369 if (!drm_dev_enter(drm, &idx)) 370 return; 371 372 memset(dbidev->tx_buf, 0, len); 373 374 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 375 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 376 (u8 *)dbidev->tx_buf, len); 377 378 drm_dev_exit(idx); 379 } 380 381 /** 382 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper 383 * @pipe: Display pipe 384 * 385 * This function disables backlight if present, if not the display memory is 386 * blanked. The regulator is disabled if in use. Drivers can use this as their 387 * &drm_simple_display_pipe_funcs->disable callback. 388 */ 389 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) 390 { 391 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 392 393 if (!dbidev->enabled) 394 return; 395 396 DRM_DEBUG_KMS("\n"); 397 398 dbidev->enabled = false; 399 400 if (dbidev->backlight) 401 backlight_disable(dbidev->backlight); 402 else 403 mipi_dbi_blank(dbidev); 404 405 if (dbidev->regulator) 406 regulator_disable(dbidev->regulator); 407 } 408 EXPORT_SYMBOL(mipi_dbi_pipe_disable); 409 410 static int mipi_dbi_connector_get_modes(struct drm_connector *connector) 411 { 412 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 413 struct drm_display_mode *mode; 414 415 mode = drm_mode_duplicate(connector->dev, &dbidev->mode); 416 if (!mode) { 417 DRM_ERROR("Failed to duplicate mode\n"); 418 return 0; 419 } 420 421 if (mode->name[0] == '\0') 422 drm_mode_set_name(mode); 423 424 mode->type |= DRM_MODE_TYPE_PREFERRED; 425 drm_mode_probed_add(connector, mode); 426 427 if (mode->width_mm) { 428 connector->display_info.width_mm = mode->width_mm; 429 connector->display_info.height_mm = mode->height_mm; 430 } 431 432 return 1; 433 } 434 435 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = { 436 .get_modes = mipi_dbi_connector_get_modes, 437 }; 438 439 static const struct drm_connector_funcs mipi_dbi_connector_funcs = { 440 .reset = drm_atomic_helper_connector_reset, 441 .fill_modes = drm_helper_probe_single_connector_modes, 442 .destroy = drm_connector_cleanup, 443 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 444 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 445 }; 446 447 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 448 unsigned int rotation) 449 { 450 if (rotation == 0 || rotation == 180) { 451 return 0; 452 } else if (rotation == 90 || rotation == 270) { 453 swap(mode->hdisplay, mode->vdisplay); 454 swap(mode->hsync_start, mode->vsync_start); 455 swap(mode->hsync_end, mode->vsync_end); 456 swap(mode->htotal, mode->vtotal); 457 swap(mode->width_mm, mode->height_mm); 458 return 0; 459 } else { 460 return -EINVAL; 461 } 462 } 463 464 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = { 465 .fb_create = drm_gem_fb_create_with_dirty, 466 .atomic_check = drm_atomic_helper_check, 467 .atomic_commit = drm_atomic_helper_commit, 468 }; 469 470 static const uint32_t mipi_dbi_formats[] = { 471 DRM_FORMAT_RGB565, 472 DRM_FORMAT_XRGB8888, 473 }; 474 475 /** 476 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats 477 * @dbidev: MIPI DBI device structure to initialize 478 * @funcs: Display pipe functions 479 * @formats: Array of supported formats (DRM_FORMAT\_\*). 480 * @format_count: Number of elements in @formats 481 * @mode: Display mode 482 * @rotation: Initial rotation in degrees Counter Clock Wise 483 * @tx_buf_size: Allocate a transmit buffer of this size. 484 * 485 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 486 * has one fixed &drm_display_mode which is rotated according to @rotation. 487 * This mode is used to set the mode config min/max width/height properties. 488 * 489 * Use mipi_dbi_dev_init() if you don't need custom formats. 490 * 491 * Note: 492 * Some of the helper functions expects RGB565 to be the default format and the 493 * transmit buffer sized to fit that. 494 * 495 * Returns: 496 * Zero on success, negative error code on failure. 497 */ 498 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, 499 const struct drm_simple_display_pipe_funcs *funcs, 500 const uint32_t *formats, unsigned int format_count, 501 const struct drm_display_mode *mode, 502 unsigned int rotation, size_t tx_buf_size) 503 { 504 static const uint64_t modifiers[] = { 505 DRM_FORMAT_MOD_LINEAR, 506 DRM_FORMAT_MOD_INVALID 507 }; 508 struct drm_device *drm = &dbidev->drm; 509 int ret; 510 511 if (!dbidev->dbi.command) 512 return -EINVAL; 513 514 ret = drmm_mode_config_init(drm); 515 if (ret) 516 return ret; 517 518 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 519 if (!dbidev->tx_buf) 520 return -ENOMEM; 521 522 drm_mode_copy(&dbidev->mode, mode); 523 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 524 if (ret) { 525 DRM_ERROR("Illegal rotation value %u\n", rotation); 526 return -EINVAL; 527 } 528 529 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs); 530 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, 531 DRM_MODE_CONNECTOR_SPI); 532 if (ret) 533 return ret; 534 535 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, 536 modifiers, &dbidev->connector); 537 if (ret) 538 return ret; 539 540 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane); 541 542 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; 543 drm->mode_config.min_width = dbidev->mode.hdisplay; 544 drm->mode_config.max_width = dbidev->mode.hdisplay; 545 drm->mode_config.min_height = dbidev->mode.vdisplay; 546 drm->mode_config.max_height = dbidev->mode.vdisplay; 547 dbidev->rotation = rotation; 548 549 DRM_DEBUG_KMS("rotation = %u\n", rotation); 550 551 return 0; 552 } 553 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats); 554 555 /** 556 * mipi_dbi_dev_init - MIPI DBI device initialization 557 * @dbidev: MIPI DBI device structure to initialize 558 * @funcs: Display pipe functions 559 * @mode: Display mode 560 * @rotation: Initial rotation in degrees Counter Clock Wise 561 * 562 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 563 * has one fixed &drm_display_mode which is rotated according to @rotation. 564 * This mode is used to set the mode config min/max width/height properties. 565 * Additionally &mipi_dbi.tx_buf is allocated. 566 * 567 * Supported formats: Native RGB565 and emulated XRGB8888. 568 * 569 * Returns: 570 * Zero on success, negative error code on failure. 571 */ 572 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, 573 const struct drm_simple_display_pipe_funcs *funcs, 574 const struct drm_display_mode *mode, unsigned int rotation) 575 { 576 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16); 577 578 dbidev->drm.mode_config.preferred_depth = 16; 579 580 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats, 581 ARRAY_SIZE(mipi_dbi_formats), mode, 582 rotation, bufsize); 583 } 584 EXPORT_SYMBOL(mipi_dbi_dev_init); 585 586 /** 587 * mipi_dbi_hw_reset - Hardware reset of controller 588 * @dbi: MIPI DBI structure 589 * 590 * Reset controller if the &mipi_dbi->reset gpio is set. 591 */ 592 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 593 { 594 if (!dbi->reset) 595 return; 596 597 gpiod_set_value_cansleep(dbi->reset, 0); 598 usleep_range(20, 1000); 599 gpiod_set_value_cansleep(dbi->reset, 1); 600 msleep(120); 601 } 602 EXPORT_SYMBOL(mipi_dbi_hw_reset); 603 604 /** 605 * mipi_dbi_display_is_on - Check if display is on 606 * @dbi: MIPI DBI structure 607 * 608 * This function checks the Power Mode register (if readable) to see if 609 * display output is turned on. This can be used to see if the bootloader 610 * has already turned on the display avoiding flicker when the pipeline is 611 * enabled. 612 * 613 * Returns: 614 * true if the display can be verified to be on, false otherwise. 615 */ 616 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 617 { 618 u8 val; 619 620 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 621 return false; 622 623 val &= ~DCS_POWER_MODE_RESERVED_MASK; 624 625 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 626 if (val != (DCS_POWER_MODE_DISPLAY | 627 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 628 return false; 629 630 DRM_DEBUG_DRIVER("Display is ON\n"); 631 632 return true; 633 } 634 EXPORT_SYMBOL(mipi_dbi_display_is_on); 635 636 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 637 { 638 struct device *dev = dbidev->drm.dev; 639 struct mipi_dbi *dbi = &dbidev->dbi; 640 int ret; 641 642 if (dbidev->regulator) { 643 ret = regulator_enable(dbidev->regulator); 644 if (ret) { 645 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 646 return ret; 647 } 648 } 649 650 if (cond && mipi_dbi_display_is_on(dbi)) 651 return 1; 652 653 mipi_dbi_hw_reset(dbi); 654 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 655 if (ret) { 656 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 657 if (dbidev->regulator) 658 regulator_disable(dbidev->regulator); 659 return ret; 660 } 661 662 /* 663 * If we did a hw reset, we know the controller is in Sleep mode and 664 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 665 * we assume worst case and wait 120ms. 666 */ 667 if (dbi->reset) 668 usleep_range(5000, 20000); 669 else 670 msleep(120); 671 672 return 0; 673 } 674 675 /** 676 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 677 * @dbidev: MIPI DBI device structure 678 * 679 * This function enables the regulator if used and does a hardware and software 680 * reset. 681 * 682 * Returns: 683 * Zero on success, or a negative error code. 684 */ 685 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 686 { 687 return mipi_dbi_poweron_reset_conditional(dbidev, false); 688 } 689 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 690 691 /** 692 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 693 * @dbidev: MIPI DBI device structure 694 * 695 * This function enables the regulator if used and if the display is off, it 696 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 697 * that the display is on, no reset is performed. 698 * 699 * Returns: 700 * Zero if the controller was reset, 1 if the display was already on, or a 701 * negative error code. 702 */ 703 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 704 { 705 return mipi_dbi_poweron_reset_conditional(dbidev, true); 706 } 707 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 708 709 #if IS_ENABLED(CONFIG_SPI) 710 711 /** 712 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 713 * @spi: SPI device 714 * @len: The transfer buffer length. 715 * 716 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 717 * that. Increase reliability by running pixel data at max speed and the rest 718 * at 10MHz, preventing transfer glitches from messing up the init settings. 719 */ 720 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 721 { 722 if (len > 64) 723 return 0; /* use default */ 724 725 return min_t(u32, 10000000, spi->max_speed_hz); 726 } 727 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 728 729 static bool mipi_dbi_machine_little_endian(void) 730 { 731 #if defined(__LITTLE_ENDIAN) 732 return true; 733 #else 734 return false; 735 #endif 736 } 737 738 /* 739 * MIPI DBI Type C Option 1 740 * 741 * If the SPI controller doesn't have 9 bits per word support, 742 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 743 * Pad partial blocks with MIPI_DCS_NOP (zero). 744 * This is how the D/C bit (x) is added: 745 * x7654321 746 * 0x765432 747 * 10x76543 748 * 210x7654 749 * 3210x765 750 * 43210x76 751 * 543210x7 752 * 6543210x 753 * 76543210 754 */ 755 756 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 757 const void *buf, size_t len, 758 unsigned int bpw) 759 { 760 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian()); 761 size_t chunk, max_chunk = dbi->tx_buf9_len; 762 struct spi_device *spi = dbi->spi; 763 struct spi_transfer tr = { 764 .tx_buf = dbi->tx_buf9, 765 .bits_per_word = 8, 766 }; 767 struct spi_message m; 768 const u8 *src = buf; 769 int i, ret; 770 u8 *dst; 771 772 if (drm_debug_enabled(DRM_UT_DRIVER)) 773 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 774 __func__, dc, max_chunk); 775 776 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 777 spi_message_init_with_transfers(&m, &tr, 1); 778 779 if (!dc) { 780 if (WARN_ON_ONCE(len != 1)) 781 return -EINVAL; 782 783 /* Command: pad no-op's (zeroes) at beginning of block */ 784 dst = dbi->tx_buf9; 785 memset(dst, 0, 9); 786 dst[8] = *src; 787 tr.len = 9; 788 789 return spi_sync(spi, &m); 790 } 791 792 /* max with room for adding one bit per byte */ 793 max_chunk = max_chunk / 9 * 8; 794 /* but no bigger than len */ 795 max_chunk = min(max_chunk, len); 796 /* 8 byte blocks */ 797 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 798 799 while (len) { 800 size_t added = 0; 801 802 chunk = min(len, max_chunk); 803 len -= chunk; 804 dst = dbi->tx_buf9; 805 806 if (chunk < 8) { 807 u8 val, carry = 0; 808 809 /* Data: pad no-op's (zeroes) at end of block */ 810 memset(dst, 0, 9); 811 812 if (swap_bytes) { 813 for (i = 1; i < (chunk + 1); i++) { 814 val = src[1]; 815 *dst++ = carry | BIT(8 - i) | (val >> i); 816 carry = val << (8 - i); 817 i++; 818 val = src[0]; 819 *dst++ = carry | BIT(8 - i) | (val >> i); 820 carry = val << (8 - i); 821 src += 2; 822 } 823 *dst++ = carry; 824 } else { 825 for (i = 1; i < (chunk + 1); i++) { 826 val = *src++; 827 *dst++ = carry | BIT(8 - i) | (val >> i); 828 carry = val << (8 - i); 829 } 830 *dst++ = carry; 831 } 832 833 chunk = 8; 834 added = 1; 835 } else { 836 for (i = 0; i < chunk; i += 8) { 837 if (swap_bytes) { 838 *dst++ = BIT(7) | (src[1] >> 1); 839 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 840 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 841 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 842 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 843 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 844 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 845 *dst++ = (src[7] << 1) | BIT(0); 846 *dst++ = src[6]; 847 } else { 848 *dst++ = BIT(7) | (src[0] >> 1); 849 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 850 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 851 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 852 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 853 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 854 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 855 *dst++ = (src[6] << 1) | BIT(0); 856 *dst++ = src[7]; 857 } 858 859 src += 8; 860 added++; 861 } 862 } 863 864 tr.len = chunk + added; 865 866 ret = spi_sync(spi, &m); 867 if (ret) 868 return ret; 869 } 870 871 return 0; 872 } 873 874 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 875 const void *buf, size_t len, 876 unsigned int bpw) 877 { 878 struct spi_device *spi = dbi->spi; 879 struct spi_transfer tr = { 880 .bits_per_word = 9, 881 }; 882 const u16 *src16 = buf; 883 const u8 *src8 = buf; 884 struct spi_message m; 885 size_t max_chunk; 886 u16 *dst16; 887 int ret; 888 889 if (!spi_is_bpw_supported(spi, 9)) 890 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 891 892 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 893 max_chunk = dbi->tx_buf9_len; 894 dst16 = dbi->tx_buf9; 895 896 if (drm_debug_enabled(DRM_UT_DRIVER)) 897 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 898 __func__, dc, max_chunk); 899 900 max_chunk = min(max_chunk / 2, len); 901 902 spi_message_init_with_transfers(&m, &tr, 1); 903 tr.tx_buf = dst16; 904 905 while (len) { 906 size_t chunk = min(len, max_chunk); 907 unsigned int i; 908 909 if (bpw == 16 && mipi_dbi_machine_little_endian()) { 910 for (i = 0; i < (chunk * 2); i += 2) { 911 dst16[i] = *src16 >> 8; 912 dst16[i + 1] = *src16++ & 0xFF; 913 if (dc) { 914 dst16[i] |= 0x0100; 915 dst16[i + 1] |= 0x0100; 916 } 917 } 918 } else { 919 for (i = 0; i < chunk; i++) { 920 dst16[i] = *src8++; 921 if (dc) 922 dst16[i] |= 0x0100; 923 } 924 } 925 926 tr.len = chunk; 927 len -= chunk; 928 929 ret = spi_sync(spi, &m); 930 if (ret) 931 return ret; 932 } 933 934 return 0; 935 } 936 937 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 938 u8 *parameters, size_t num) 939 { 940 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8; 941 int ret; 942 943 if (mipi_dbi_command_is_read(dbi, *cmd)) 944 return -EOPNOTSUPP; 945 946 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 947 948 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 949 if (ret || !num) 950 return ret; 951 952 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 953 } 954 955 /* MIPI DBI Type C Option 3 */ 956 957 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 958 u8 *data, size_t len) 959 { 960 struct spi_device *spi = dbi->spi; 961 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 962 spi->max_speed_hz / 2); 963 struct spi_transfer tr[2] = { 964 { 965 .speed_hz = speed_hz, 966 .tx_buf = cmd, 967 .len = 1, 968 }, { 969 .speed_hz = speed_hz, 970 .len = len, 971 }, 972 }; 973 struct spi_message m; 974 u8 *buf; 975 int ret; 976 977 if (!len) 978 return -EINVAL; 979 980 /* 981 * Support non-standard 24-bit and 32-bit Nokia read commands which 982 * start with a dummy clock, so we need to read an extra byte. 983 */ 984 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 985 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 986 if (!(len == 3 || len == 4)) 987 return -EINVAL; 988 989 tr[1].len = len + 1; 990 } 991 992 buf = kmalloc(tr[1].len, GFP_KERNEL); 993 if (!buf) 994 return -ENOMEM; 995 996 tr[1].rx_buf = buf; 997 gpiod_set_value_cansleep(dbi->dc, 0); 998 999 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1000 ret = spi_sync(spi, &m); 1001 if (ret) 1002 goto err_free; 1003 1004 if (tr[1].len == len) { 1005 memcpy(data, buf, len); 1006 } else { 1007 unsigned int i; 1008 1009 for (i = 0; i < len; i++) 1010 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1011 } 1012 1013 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1014 1015 err_free: 1016 kfree(buf); 1017 1018 return ret; 1019 } 1020 1021 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1022 u8 *par, size_t num) 1023 { 1024 struct spi_device *spi = dbi->spi; 1025 unsigned int bpw = 8; 1026 u32 speed_hz; 1027 int ret; 1028 1029 if (mipi_dbi_command_is_read(dbi, *cmd)) 1030 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1031 1032 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1033 1034 gpiod_set_value_cansleep(dbi->dc, 0); 1035 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1036 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1037 if (ret || !num) 1038 return ret; 1039 1040 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes) 1041 bpw = 16; 1042 1043 gpiod_set_value_cansleep(dbi->dc, 1); 1044 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1045 1046 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1047 } 1048 1049 /** 1050 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1051 * @spi: SPI device 1052 * @dbi: MIPI DBI structure to initialize 1053 * @dc: D/C gpio (optional) 1054 * 1055 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1056 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1057 * a driver-specific init. 1058 * 1059 * If @dc is set, a Type C Option 3 interface is assumed, if not 1060 * Type C Option 1. 1061 * 1062 * If the SPI master driver doesn't support the necessary bits per word, 1063 * the following transformation is used: 1064 * 1065 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command. 1066 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes 1067 * 1068 * Returns: 1069 * Zero on success, negative error code on failure. 1070 */ 1071 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1072 struct gpio_desc *dc) 1073 { 1074 struct device *dev = &spi->dev; 1075 int ret; 1076 1077 /* 1078 * Even though it's not the SPI device that does DMA (the master does), 1079 * the dma mask is necessary for the dma_alloc_wc() in 1080 * drm_gem_cma_create(). The dma_addr returned will be a physical 1081 * address which might be different from the bus address, but this is 1082 * not a problem since the address will not be used. 1083 * The virtual address is used in the transfer and the SPI core 1084 * re-maps it on the SPI master device using the DMA streaming API 1085 * (spi_map_buf()). 1086 */ 1087 if (!dev->coherent_dma_mask) { 1088 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1089 if (ret) { 1090 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1091 return ret; 1092 } 1093 } 1094 1095 dbi->spi = spi; 1096 dbi->read_commands = mipi_dbi_dcs_read_commands; 1097 1098 if (dc) { 1099 dbi->command = mipi_dbi_typec3_command; 1100 dbi->dc = dc; 1101 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16)) 1102 dbi->swap_bytes = true; 1103 } else { 1104 dbi->command = mipi_dbi_typec1_command; 1105 dbi->tx_buf9_len = SZ_16K; 1106 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1107 if (!dbi->tx_buf9) 1108 return -ENOMEM; 1109 } 1110 1111 mutex_init(&dbi->cmdlock); 1112 1113 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1114 1115 return 0; 1116 } 1117 EXPORT_SYMBOL(mipi_dbi_spi_init); 1118 1119 /** 1120 * mipi_dbi_spi_transfer - SPI transfer helper 1121 * @spi: SPI device 1122 * @speed_hz: Override speed (optional) 1123 * @bpw: Bits per word 1124 * @buf: Buffer to transfer 1125 * @len: Buffer length 1126 * 1127 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1128 * the SPI controller driver can handle. 1129 * 1130 * Returns: 1131 * Zero on success, negative error code on failure. 1132 */ 1133 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1134 u8 bpw, const void *buf, size_t len) 1135 { 1136 size_t max_chunk = spi_max_transfer_size(spi); 1137 struct spi_transfer tr = { 1138 .bits_per_word = bpw, 1139 .speed_hz = speed_hz, 1140 }; 1141 struct spi_message m; 1142 size_t chunk; 1143 int ret; 1144 1145 spi_message_init_with_transfers(&m, &tr, 1); 1146 1147 while (len) { 1148 chunk = min(len, max_chunk); 1149 1150 tr.tx_buf = buf; 1151 tr.len = chunk; 1152 buf += chunk; 1153 len -= chunk; 1154 1155 ret = spi_sync(spi, &m); 1156 if (ret) 1157 return ret; 1158 } 1159 1160 return 0; 1161 } 1162 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1163 1164 #endif /* CONFIG_SPI */ 1165 1166 #ifdef CONFIG_DEBUG_FS 1167 1168 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1169 const char __user *ubuf, 1170 size_t count, loff_t *ppos) 1171 { 1172 struct seq_file *m = file->private_data; 1173 struct mipi_dbi_dev *dbidev = m->private; 1174 u8 val, cmd = 0, parameters[64]; 1175 char *buf, *pos, *token; 1176 int i, ret, idx; 1177 1178 if (!drm_dev_enter(&dbidev->drm, &idx)) 1179 return -ENODEV; 1180 1181 buf = memdup_user_nul(ubuf, count); 1182 if (IS_ERR(buf)) { 1183 ret = PTR_ERR(buf); 1184 goto err_exit; 1185 } 1186 1187 /* strip trailing whitespace */ 1188 for (i = count - 1; i > 0; i--) 1189 if (isspace(buf[i])) 1190 buf[i] = '\0'; 1191 else 1192 break; 1193 i = 0; 1194 pos = buf; 1195 while (pos) { 1196 token = strsep(&pos, " "); 1197 if (!token) { 1198 ret = -EINVAL; 1199 goto err_free; 1200 } 1201 1202 ret = kstrtou8(token, 16, &val); 1203 if (ret < 0) 1204 goto err_free; 1205 1206 if (token == buf) 1207 cmd = val; 1208 else 1209 parameters[i++] = val; 1210 1211 if (i == 64) { 1212 ret = -E2BIG; 1213 goto err_free; 1214 } 1215 } 1216 1217 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1218 1219 err_free: 1220 kfree(buf); 1221 err_exit: 1222 drm_dev_exit(idx); 1223 1224 return ret < 0 ? ret : count; 1225 } 1226 1227 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1228 { 1229 struct mipi_dbi_dev *dbidev = m->private; 1230 struct mipi_dbi *dbi = &dbidev->dbi; 1231 u8 cmd, val[4]; 1232 int ret, idx; 1233 size_t len; 1234 1235 if (!drm_dev_enter(&dbidev->drm, &idx)) 1236 return -ENODEV; 1237 1238 for (cmd = 0; cmd < 255; cmd++) { 1239 if (!mipi_dbi_command_is_read(dbi, cmd)) 1240 continue; 1241 1242 switch (cmd) { 1243 case MIPI_DCS_READ_MEMORY_START: 1244 case MIPI_DCS_READ_MEMORY_CONTINUE: 1245 len = 2; 1246 break; 1247 case MIPI_DCS_GET_DISPLAY_ID: 1248 len = 3; 1249 break; 1250 case MIPI_DCS_GET_DISPLAY_STATUS: 1251 len = 4; 1252 break; 1253 default: 1254 len = 1; 1255 break; 1256 } 1257 1258 seq_printf(m, "%02x: ", cmd); 1259 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1260 if (ret) { 1261 seq_puts(m, "XX\n"); 1262 continue; 1263 } 1264 seq_printf(m, "%*phN\n", (int)len, val); 1265 } 1266 1267 drm_dev_exit(idx); 1268 1269 return 0; 1270 } 1271 1272 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1273 struct file *file) 1274 { 1275 return single_open(file, mipi_dbi_debugfs_command_show, 1276 inode->i_private); 1277 } 1278 1279 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1280 .owner = THIS_MODULE, 1281 .open = mipi_dbi_debugfs_command_open, 1282 .read = seq_read, 1283 .llseek = seq_lseek, 1284 .release = single_release, 1285 .write = mipi_dbi_debugfs_command_write, 1286 }; 1287 1288 /** 1289 * mipi_dbi_debugfs_init - Create debugfs entries 1290 * @minor: DRM minor 1291 * 1292 * This function creates a 'command' debugfs file for sending commands to the 1293 * controller or getting the read command values. 1294 * Drivers can use this as their &drm_driver->debugfs_init callback. 1295 * 1296 */ 1297 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1298 { 1299 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1300 umode_t mode = S_IFREG | S_IWUSR; 1301 1302 if (dbidev->dbi.read_commands) 1303 mode |= S_IRUGO; 1304 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1305 &mipi_dbi_debugfs_command_fops); 1306 } 1307 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1308 1309 #endif 1310 1311 MODULE_LICENSE("GPL"); 1312