1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MIPI Display Bus Interface (DBI) LCD controller support 4 * 5 * Copyright 2016 Noralf Trønnes 6 */ 7 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/dma-buf.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/spi/spi.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_format_helper.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_mipi_dbi.h> 24 #include <drm/drm_modes.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_rect.h> 27 #include <video/mipi_display.h> 28 29 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ 30 31 #define DCS_POWER_MODE_DISPLAY BIT(2) 32 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) 33 #define DCS_POWER_MODE_SLEEP_MODE BIT(4) 34 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) 35 #define DCS_POWER_MODE_IDLE_MODE BIT(6) 36 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) 37 38 /** 39 * DOC: overview 40 * 41 * This library provides helpers for MIPI Display Bus Interface (DBI) 42 * compatible display controllers. 43 * 44 * Many controllers for tiny lcd displays are MIPI compliant and can use this 45 * library. If a controller uses registers 0x2A and 0x2B to set the area to 46 * update and uses register 0x2C to write to frame memory, it is most likely 47 * MIPI compliant. 48 * 49 * Only MIPI Type 1 displays are supported since a full frame memory is needed. 50 * 51 * There are 3 MIPI DBI implementation types: 52 * 53 * A. Motorola 6800 type parallel bus 54 * 55 * B. Intel 8080 type parallel bus 56 * 57 * C. SPI type with 3 options: 58 * 59 * 1. 9-bit with the Data/Command signal as the ninth bit 60 * 2. Same as above except it's sent as 16 bits 61 * 3. 8-bit with the Data/Command signal as a separate D/CX pin 62 * 63 * Currently mipi_dbi only supports Type C options 1 and 3 with 64 * mipi_dbi_spi_init(). 65 */ 66 67 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ 68 ({ \ 69 if (!len) \ 70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \ 71 else if (len <= 32) \ 72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\ 73 else \ 74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \ 75 }) 76 77 static const u8 mipi_dbi_dcs_read_commands[] = { 78 MIPI_DCS_GET_DISPLAY_ID, 79 MIPI_DCS_GET_RED_CHANNEL, 80 MIPI_DCS_GET_GREEN_CHANNEL, 81 MIPI_DCS_GET_BLUE_CHANNEL, 82 MIPI_DCS_GET_DISPLAY_STATUS, 83 MIPI_DCS_GET_POWER_MODE, 84 MIPI_DCS_GET_ADDRESS_MODE, 85 MIPI_DCS_GET_PIXEL_FORMAT, 86 MIPI_DCS_GET_DISPLAY_MODE, 87 MIPI_DCS_GET_SIGNAL_MODE, 88 MIPI_DCS_GET_DIAGNOSTIC_RESULT, 89 MIPI_DCS_READ_MEMORY_START, 90 MIPI_DCS_READ_MEMORY_CONTINUE, 91 MIPI_DCS_GET_SCANLINE, 92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS, 93 MIPI_DCS_GET_CONTROL_DISPLAY, 94 MIPI_DCS_GET_POWER_SAVE, 95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS, 96 MIPI_DCS_READ_DDB_START, 97 MIPI_DCS_READ_DDB_CONTINUE, 98 0, /* sentinel */ 99 }; 100 101 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) 102 { 103 unsigned int i; 104 105 if (!dbi->read_commands) 106 return false; 107 108 for (i = 0; i < 0xff; i++) { 109 if (!dbi->read_commands[i]) 110 return false; 111 if (cmd == dbi->read_commands[i]) 112 return true; 113 } 114 115 return false; 116 } 117 118 /** 119 * mipi_dbi_command_read - MIPI DCS read command 120 * @dbi: MIPI DBI structure 121 * @cmd: Command 122 * @val: Value read 123 * 124 * Send MIPI DCS read command to the controller. 125 * 126 * Returns: 127 * Zero on success, negative error code on failure. 128 */ 129 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) 130 { 131 if (!dbi->read_commands) 132 return -EACCES; 133 134 if (!mipi_dbi_command_is_read(dbi, cmd)) 135 return -EINVAL; 136 137 return mipi_dbi_command_buf(dbi, cmd, val, 1); 138 } 139 EXPORT_SYMBOL(mipi_dbi_command_read); 140 141 /** 142 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array 143 * @dbi: MIPI DBI structure 144 * @cmd: Command 145 * @data: Parameter buffer 146 * @len: Buffer length 147 * 148 * Returns: 149 * Zero on success, negative error code on failure. 150 */ 151 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) 152 { 153 u8 *cmdbuf; 154 int ret; 155 156 /* SPI requires dma-safe buffers */ 157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL); 158 if (!cmdbuf) 159 return -ENOMEM; 160 161 mutex_lock(&dbi->cmdlock); 162 ret = dbi->command(dbi, cmdbuf, data, len); 163 mutex_unlock(&dbi->cmdlock); 164 165 kfree(cmdbuf); 166 167 return ret; 168 } 169 EXPORT_SYMBOL(mipi_dbi_command_buf); 170 171 /* This should only be used by mipi_dbi_command() */ 172 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data, 173 size_t len) 174 { 175 u8 *buf; 176 int ret; 177 178 buf = kmemdup(data, len, GFP_KERNEL); 179 if (!buf) 180 return -ENOMEM; 181 182 ret = mipi_dbi_command_buf(dbi, cmd, buf, len); 183 184 kfree(buf); 185 186 return ret; 187 } 188 EXPORT_SYMBOL(mipi_dbi_command_stackbuf); 189 190 /** 191 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary 192 * @dst: The destination buffer 193 * @fb: The source framebuffer 194 * @clip: Clipping rectangle of the area to be copied 195 * @swap: When true, swap MSB/LSB of 16-bit values 196 * 197 * Returns: 198 * Zero on success, negative error code on failure. 199 */ 200 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb, 201 struct drm_rect *clip, bool swap) 202 { 203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 204 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem); 205 struct dma_buf_attachment *import_attach = gem->import_attach; 206 void *src = cma_obj->vaddr; 207 int ret = 0; 208 209 if (import_attach) { 210 ret = dma_buf_begin_cpu_access(import_attach->dmabuf, 211 DMA_FROM_DEVICE); 212 if (ret) 213 return ret; 214 } 215 216 switch (fb->format->format) { 217 case DRM_FORMAT_RGB565: 218 if (swap) 219 drm_fb_swab(dst, src, fb, clip, !import_attach); 220 else 221 drm_fb_memcpy(dst, src, fb, clip); 222 break; 223 case DRM_FORMAT_XRGB8888: 224 drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap); 225 break; 226 default: 227 drm_err_once(fb->dev, "Format is not supported: %p4cc\n", 228 &fb->format->format); 229 return -EINVAL; 230 } 231 232 if (import_attach) 233 ret = dma_buf_end_cpu_access(import_attach->dmabuf, 234 DMA_FROM_DEVICE); 235 return ret; 236 } 237 EXPORT_SYMBOL(mipi_dbi_buf_copy); 238 239 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, 240 unsigned int xs, unsigned int xe, 241 unsigned int ys, unsigned int ye) 242 { 243 struct mipi_dbi *dbi = &dbidev->dbi; 244 245 xs += dbidev->left_offset; 246 xe += dbidev->left_offset; 247 ys += dbidev->top_offset; 248 ye += dbidev->top_offset; 249 250 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, 251 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); 252 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, 253 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); 254 } 255 256 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) 257 { 258 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); 259 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem); 260 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev); 261 unsigned int height = rect->y2 - rect->y1; 262 unsigned int width = rect->x2 - rect->x1; 263 struct mipi_dbi *dbi = &dbidev->dbi; 264 bool swap = dbi->swap_bytes; 265 int idx, ret = 0; 266 bool full; 267 void *tr; 268 269 if (WARN_ON(!fb)) 270 return; 271 272 if (!drm_dev_enter(fb->dev, &idx)) 273 return; 274 275 full = width == fb->width && height == fb->height; 276 277 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); 278 279 if (!dbi->dc || !full || swap || 280 fb->format->format == DRM_FORMAT_XRGB8888) { 281 tr = dbidev->tx_buf; 282 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap); 283 if (ret) 284 goto err_msg; 285 } else { 286 tr = cma_obj->vaddr; 287 } 288 289 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, 290 rect->y2 - 1); 291 292 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, 293 width * height * 2); 294 err_msg: 295 if (ret) 296 drm_err_once(fb->dev, "Failed to update display %d\n", ret); 297 298 drm_dev_exit(idx); 299 } 300 301 /** 302 * mipi_dbi_pipe_update - Display pipe update helper 303 * @pipe: Simple display pipe 304 * @old_state: Old plane state 305 * 306 * This function handles framebuffer flushing and vblank events. Drivers can use 307 * this as their &drm_simple_display_pipe_funcs->update callback. 308 */ 309 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, 310 struct drm_plane_state *old_state) 311 { 312 struct drm_plane_state *state = pipe->plane.state; 313 struct drm_rect rect; 314 315 if (!pipe->crtc.state->active) 316 return; 317 318 if (drm_atomic_helper_damage_merged(old_state, state, &rect)) 319 mipi_dbi_fb_dirty(state->fb, &rect); 320 } 321 EXPORT_SYMBOL(mipi_dbi_pipe_update); 322 323 /** 324 * mipi_dbi_enable_flush - MIPI DBI enable helper 325 * @dbidev: MIPI DBI device structure 326 * @crtc_state: CRTC state 327 * @plane_state: Plane state 328 * 329 * Flushes the whole framebuffer and enables the backlight. Drivers can use this 330 * in their &drm_simple_display_pipe_funcs->enable callback. 331 * 332 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom 333 * framebuffer flushing, can't use this function since they both use the same 334 * flushing code. 335 */ 336 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, 337 struct drm_crtc_state *crtc_state, 338 struct drm_plane_state *plane_state) 339 { 340 struct drm_framebuffer *fb = plane_state->fb; 341 struct drm_rect rect = { 342 .x1 = 0, 343 .x2 = fb->width, 344 .y1 = 0, 345 .y2 = fb->height, 346 }; 347 int idx; 348 349 if (!drm_dev_enter(&dbidev->drm, &idx)) 350 return; 351 352 mipi_dbi_fb_dirty(fb, &rect); 353 backlight_enable(dbidev->backlight); 354 355 drm_dev_exit(idx); 356 } 357 EXPORT_SYMBOL(mipi_dbi_enable_flush); 358 359 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) 360 { 361 struct drm_device *drm = &dbidev->drm; 362 u16 height = drm->mode_config.min_height; 363 u16 width = drm->mode_config.min_width; 364 struct mipi_dbi *dbi = &dbidev->dbi; 365 size_t len = width * height * 2; 366 int idx; 367 368 if (!drm_dev_enter(drm, &idx)) 369 return; 370 371 memset(dbidev->tx_buf, 0, len); 372 373 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); 374 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, 375 (u8 *)dbidev->tx_buf, len); 376 377 drm_dev_exit(idx); 378 } 379 380 /** 381 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper 382 * @pipe: Display pipe 383 * 384 * This function disables backlight if present, if not the display memory is 385 * blanked. The regulator is disabled if in use. Drivers can use this as their 386 * &drm_simple_display_pipe_funcs->disable callback. 387 */ 388 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) 389 { 390 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); 391 392 DRM_DEBUG_KMS("\n"); 393 394 if (dbidev->backlight) 395 backlight_disable(dbidev->backlight); 396 else 397 mipi_dbi_blank(dbidev); 398 399 if (dbidev->regulator) 400 regulator_disable(dbidev->regulator); 401 } 402 EXPORT_SYMBOL(mipi_dbi_pipe_disable); 403 404 static int mipi_dbi_connector_get_modes(struct drm_connector *connector) 405 { 406 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev); 407 struct drm_display_mode *mode; 408 409 mode = drm_mode_duplicate(connector->dev, &dbidev->mode); 410 if (!mode) { 411 DRM_ERROR("Failed to duplicate mode\n"); 412 return 0; 413 } 414 415 if (mode->name[0] == '\0') 416 drm_mode_set_name(mode); 417 418 mode->type |= DRM_MODE_TYPE_PREFERRED; 419 drm_mode_probed_add(connector, mode); 420 421 if (mode->width_mm) { 422 connector->display_info.width_mm = mode->width_mm; 423 connector->display_info.height_mm = mode->height_mm; 424 } 425 426 return 1; 427 } 428 429 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = { 430 .get_modes = mipi_dbi_connector_get_modes, 431 }; 432 433 static const struct drm_connector_funcs mipi_dbi_connector_funcs = { 434 .reset = drm_atomic_helper_connector_reset, 435 .fill_modes = drm_helper_probe_single_connector_modes, 436 .destroy = drm_connector_cleanup, 437 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 438 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 439 }; 440 441 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode, 442 unsigned int rotation) 443 { 444 if (rotation == 0 || rotation == 180) { 445 return 0; 446 } else if (rotation == 90 || rotation == 270) { 447 swap(mode->hdisplay, mode->vdisplay); 448 swap(mode->hsync_start, mode->vsync_start); 449 swap(mode->hsync_end, mode->vsync_end); 450 swap(mode->htotal, mode->vtotal); 451 swap(mode->width_mm, mode->height_mm); 452 return 0; 453 } else { 454 return -EINVAL; 455 } 456 } 457 458 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = { 459 .fb_create = drm_gem_fb_create_with_dirty, 460 .atomic_check = drm_atomic_helper_check, 461 .atomic_commit = drm_atomic_helper_commit, 462 }; 463 464 static const uint32_t mipi_dbi_formats[] = { 465 DRM_FORMAT_RGB565, 466 DRM_FORMAT_XRGB8888, 467 }; 468 469 /** 470 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats 471 * @dbidev: MIPI DBI device structure to initialize 472 * @funcs: Display pipe functions 473 * @formats: Array of supported formats (DRM_FORMAT\_\*). 474 * @format_count: Number of elements in @formats 475 * @mode: Display mode 476 * @rotation: Initial rotation in degrees Counter Clock Wise 477 * @tx_buf_size: Allocate a transmit buffer of this size. 478 * 479 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 480 * has one fixed &drm_display_mode which is rotated according to @rotation. 481 * This mode is used to set the mode config min/max width/height properties. 482 * 483 * Use mipi_dbi_dev_init() if you don't need custom formats. 484 * 485 * Note: 486 * Some of the helper functions expects RGB565 to be the default format and the 487 * transmit buffer sized to fit that. 488 * 489 * Returns: 490 * Zero on success, negative error code on failure. 491 */ 492 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, 493 const struct drm_simple_display_pipe_funcs *funcs, 494 const uint32_t *formats, unsigned int format_count, 495 const struct drm_display_mode *mode, 496 unsigned int rotation, size_t tx_buf_size) 497 { 498 static const uint64_t modifiers[] = { 499 DRM_FORMAT_MOD_LINEAR, 500 DRM_FORMAT_MOD_INVALID 501 }; 502 struct drm_device *drm = &dbidev->drm; 503 int ret; 504 505 if (!dbidev->dbi.command) 506 return -EINVAL; 507 508 ret = drmm_mode_config_init(drm); 509 if (ret) 510 return ret; 511 512 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); 513 if (!dbidev->tx_buf) 514 return -ENOMEM; 515 516 drm_mode_copy(&dbidev->mode, mode); 517 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation); 518 if (ret) { 519 DRM_ERROR("Illegal rotation value %u\n", rotation); 520 return -EINVAL; 521 } 522 523 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs); 524 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, 525 DRM_MODE_CONNECTOR_SPI); 526 if (ret) 527 return ret; 528 529 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, 530 modifiers, &dbidev->connector); 531 if (ret) 532 return ret; 533 534 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane); 535 536 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; 537 drm->mode_config.min_width = dbidev->mode.hdisplay; 538 drm->mode_config.max_width = dbidev->mode.hdisplay; 539 drm->mode_config.min_height = dbidev->mode.vdisplay; 540 drm->mode_config.max_height = dbidev->mode.vdisplay; 541 dbidev->rotation = rotation; 542 543 DRM_DEBUG_KMS("rotation = %u\n", rotation); 544 545 return 0; 546 } 547 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats); 548 549 /** 550 * mipi_dbi_dev_init - MIPI DBI device initialization 551 * @dbidev: MIPI DBI device structure to initialize 552 * @funcs: Display pipe functions 553 * @mode: Display mode 554 * @rotation: Initial rotation in degrees Counter Clock Wise 555 * 556 * This function sets up a &drm_simple_display_pipe with a &drm_connector that 557 * has one fixed &drm_display_mode which is rotated according to @rotation. 558 * This mode is used to set the mode config min/max width/height properties. 559 * Additionally &mipi_dbi.tx_buf is allocated. 560 * 561 * Supported formats: Native RGB565 and emulated XRGB8888. 562 * 563 * Returns: 564 * Zero on success, negative error code on failure. 565 */ 566 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev, 567 const struct drm_simple_display_pipe_funcs *funcs, 568 const struct drm_display_mode *mode, unsigned int rotation) 569 { 570 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16); 571 572 dbidev->drm.mode_config.preferred_depth = 16; 573 574 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats, 575 ARRAY_SIZE(mipi_dbi_formats), mode, 576 rotation, bufsize); 577 } 578 EXPORT_SYMBOL(mipi_dbi_dev_init); 579 580 /** 581 * mipi_dbi_hw_reset - Hardware reset of controller 582 * @dbi: MIPI DBI structure 583 * 584 * Reset controller if the &mipi_dbi->reset gpio is set. 585 */ 586 void mipi_dbi_hw_reset(struct mipi_dbi *dbi) 587 { 588 if (!dbi->reset) 589 return; 590 591 gpiod_set_value_cansleep(dbi->reset, 0); 592 usleep_range(20, 1000); 593 gpiod_set_value_cansleep(dbi->reset, 1); 594 msleep(120); 595 } 596 EXPORT_SYMBOL(mipi_dbi_hw_reset); 597 598 /** 599 * mipi_dbi_display_is_on - Check if display is on 600 * @dbi: MIPI DBI structure 601 * 602 * This function checks the Power Mode register (if readable) to see if 603 * display output is turned on. This can be used to see if the bootloader 604 * has already turned on the display avoiding flicker when the pipeline is 605 * enabled. 606 * 607 * Returns: 608 * true if the display can be verified to be on, false otherwise. 609 */ 610 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) 611 { 612 u8 val; 613 614 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) 615 return false; 616 617 val &= ~DCS_POWER_MODE_RESERVED_MASK; 618 619 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */ 620 if (val != (DCS_POWER_MODE_DISPLAY | 621 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE)) 622 return false; 623 624 DRM_DEBUG_DRIVER("Display is ON\n"); 625 626 return true; 627 } 628 EXPORT_SYMBOL(mipi_dbi_display_is_on); 629 630 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond) 631 { 632 struct device *dev = dbidev->drm.dev; 633 struct mipi_dbi *dbi = &dbidev->dbi; 634 int ret; 635 636 if (dbidev->regulator) { 637 ret = regulator_enable(dbidev->regulator); 638 if (ret) { 639 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret); 640 return ret; 641 } 642 } 643 644 if (cond && mipi_dbi_display_is_on(dbi)) 645 return 1; 646 647 mipi_dbi_hw_reset(dbi); 648 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); 649 if (ret) { 650 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret); 651 if (dbidev->regulator) 652 regulator_disable(dbidev->regulator); 653 return ret; 654 } 655 656 /* 657 * If we did a hw reset, we know the controller is in Sleep mode and 658 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't, 659 * we assume worst case and wait 120ms. 660 */ 661 if (dbi->reset) 662 usleep_range(5000, 20000); 663 else 664 msleep(120); 665 666 return 0; 667 } 668 669 /** 670 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset 671 * @dbidev: MIPI DBI device structure 672 * 673 * This function enables the regulator if used and does a hardware and software 674 * reset. 675 * 676 * Returns: 677 * Zero on success, or a negative error code. 678 */ 679 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev) 680 { 681 return mipi_dbi_poweron_reset_conditional(dbidev, false); 682 } 683 EXPORT_SYMBOL(mipi_dbi_poweron_reset); 684 685 /** 686 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset 687 * @dbidev: MIPI DBI device structure 688 * 689 * This function enables the regulator if used and if the display is off, it 690 * does a hardware and software reset. If mipi_dbi_display_is_on() determines 691 * that the display is on, no reset is performed. 692 * 693 * Returns: 694 * Zero if the controller was reset, 1 if the display was already on, or a 695 * negative error code. 696 */ 697 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev) 698 { 699 return mipi_dbi_poweron_reset_conditional(dbidev, true); 700 } 701 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset); 702 703 #if IS_ENABLED(CONFIG_SPI) 704 705 /** 706 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed 707 * @spi: SPI device 708 * @len: The transfer buffer length. 709 * 710 * Many controllers have a max speed of 10MHz, but can be pushed way beyond 711 * that. Increase reliability by running pixel data at max speed and the rest 712 * at 10MHz, preventing transfer glitches from messing up the init settings. 713 */ 714 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len) 715 { 716 if (len > 64) 717 return 0; /* use default */ 718 719 return min_t(u32, 10000000, spi->max_speed_hz); 720 } 721 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed); 722 723 static bool mipi_dbi_machine_little_endian(void) 724 { 725 #if defined(__LITTLE_ENDIAN) 726 return true; 727 #else 728 return false; 729 #endif 730 } 731 732 /* 733 * MIPI DBI Type C Option 1 734 * 735 * If the SPI controller doesn't have 9 bits per word support, 736 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer. 737 * Pad partial blocks with MIPI_DCS_NOP (zero). 738 * This is how the D/C bit (x) is added: 739 * x7654321 740 * 0x765432 741 * 10x76543 742 * 210x7654 743 * 3210x765 744 * 43210x76 745 * 543210x7 746 * 6543210x 747 * 76543210 748 */ 749 750 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, 751 const void *buf, size_t len, 752 unsigned int bpw) 753 { 754 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian()); 755 size_t chunk, max_chunk = dbi->tx_buf9_len; 756 struct spi_device *spi = dbi->spi; 757 struct spi_transfer tr = { 758 .tx_buf = dbi->tx_buf9, 759 .bits_per_word = 8, 760 }; 761 struct spi_message m; 762 const u8 *src = buf; 763 int i, ret; 764 u8 *dst; 765 766 if (drm_debug_enabled(DRM_UT_DRIVER)) 767 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 768 __func__, dc, max_chunk); 769 770 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 771 spi_message_init_with_transfers(&m, &tr, 1); 772 773 if (!dc) { 774 if (WARN_ON_ONCE(len != 1)) 775 return -EINVAL; 776 777 /* Command: pad no-op's (zeroes) at beginning of block */ 778 dst = dbi->tx_buf9; 779 memset(dst, 0, 9); 780 dst[8] = *src; 781 tr.len = 9; 782 783 return spi_sync(spi, &m); 784 } 785 786 /* max with room for adding one bit per byte */ 787 max_chunk = max_chunk / 9 * 8; 788 /* but no bigger than len */ 789 max_chunk = min(max_chunk, len); 790 /* 8 byte blocks */ 791 max_chunk = max_t(size_t, 8, max_chunk & ~0x7); 792 793 while (len) { 794 size_t added = 0; 795 796 chunk = min(len, max_chunk); 797 len -= chunk; 798 dst = dbi->tx_buf9; 799 800 if (chunk < 8) { 801 u8 val, carry = 0; 802 803 /* Data: pad no-op's (zeroes) at end of block */ 804 memset(dst, 0, 9); 805 806 if (swap_bytes) { 807 for (i = 1; i < (chunk + 1); i++) { 808 val = src[1]; 809 *dst++ = carry | BIT(8 - i) | (val >> i); 810 carry = val << (8 - i); 811 i++; 812 val = src[0]; 813 *dst++ = carry | BIT(8 - i) | (val >> i); 814 carry = val << (8 - i); 815 src += 2; 816 } 817 *dst++ = carry; 818 } else { 819 for (i = 1; i < (chunk + 1); i++) { 820 val = *src++; 821 *dst++ = carry | BIT(8 - i) | (val >> i); 822 carry = val << (8 - i); 823 } 824 *dst++ = carry; 825 } 826 827 chunk = 8; 828 added = 1; 829 } else { 830 for (i = 0; i < chunk; i += 8) { 831 if (swap_bytes) { 832 *dst++ = BIT(7) | (src[1] >> 1); 833 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); 834 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); 835 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); 836 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); 837 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); 838 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); 839 *dst++ = (src[7] << 1) | BIT(0); 840 *dst++ = src[6]; 841 } else { 842 *dst++ = BIT(7) | (src[0] >> 1); 843 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); 844 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); 845 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); 846 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); 847 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); 848 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); 849 *dst++ = (src[6] << 1) | BIT(0); 850 *dst++ = src[7]; 851 } 852 853 src += 8; 854 added++; 855 } 856 } 857 858 tr.len = chunk + added; 859 860 ret = spi_sync(spi, &m); 861 if (ret) 862 return ret; 863 } 864 865 return 0; 866 } 867 868 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, 869 const void *buf, size_t len, 870 unsigned int bpw) 871 { 872 struct spi_device *spi = dbi->spi; 873 struct spi_transfer tr = { 874 .bits_per_word = 9, 875 }; 876 const u16 *src16 = buf; 877 const u8 *src8 = buf; 878 struct spi_message m; 879 size_t max_chunk; 880 u16 *dst16; 881 int ret; 882 883 if (!spi_is_bpw_supported(spi, 9)) 884 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); 885 886 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len); 887 max_chunk = dbi->tx_buf9_len; 888 dst16 = dbi->tx_buf9; 889 890 if (drm_debug_enabled(DRM_UT_DRIVER)) 891 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n", 892 __func__, dc, max_chunk); 893 894 max_chunk = min(max_chunk / 2, len); 895 896 spi_message_init_with_transfers(&m, &tr, 1); 897 tr.tx_buf = dst16; 898 899 while (len) { 900 size_t chunk = min(len, max_chunk); 901 unsigned int i; 902 903 if (bpw == 16 && mipi_dbi_machine_little_endian()) { 904 for (i = 0; i < (chunk * 2); i += 2) { 905 dst16[i] = *src16 >> 8; 906 dst16[i + 1] = *src16++ & 0xFF; 907 if (dc) { 908 dst16[i] |= 0x0100; 909 dst16[i + 1] |= 0x0100; 910 } 911 } 912 } else { 913 for (i = 0; i < chunk; i++) { 914 dst16[i] = *src8++; 915 if (dc) 916 dst16[i] |= 0x0100; 917 } 918 } 919 920 tr.len = chunk * 2; 921 len -= chunk; 922 923 ret = spi_sync(spi, &m); 924 if (ret) 925 return ret; 926 } 927 928 return 0; 929 } 930 931 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 932 u8 *data, size_t len) 933 { 934 struct spi_device *spi = dbi->spi; 935 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 936 spi->max_speed_hz / 2); 937 struct spi_transfer tr[2] = { 938 { 939 .speed_hz = speed_hz, 940 .bits_per_word = 9, 941 .tx_buf = dbi->tx_buf9, 942 .len = 2, 943 }, { 944 .speed_hz = speed_hz, 945 .bits_per_word = 8, 946 .len = len, 947 .rx_buf = data, 948 }, 949 }; 950 struct spi_message m; 951 u16 *dst16; 952 int ret; 953 954 if (!len) 955 return -EINVAL; 956 957 if (!spi_is_bpw_supported(spi, 9)) { 958 /* 959 * FIXME: implement something like mipi_dbi_spi1e_transfer() but 960 * for reads using emulation. 961 */ 962 dev_err(&spi->dev, 963 "reading on host not supporting 9 bpw not yet implemented\n"); 964 return -EOPNOTSUPP; 965 } 966 967 /* 968 * Turn the 8bit command into a 16bit version of the command in the 969 * buffer. Only 9 bits of this will be used when executing the actual 970 * transfer. 971 */ 972 dst16 = dbi->tx_buf9; 973 dst16[0] = *cmd; 974 975 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 976 ret = spi_sync(spi, &m); 977 978 if (!ret) 979 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 980 981 return ret; 982 } 983 984 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 985 u8 *parameters, size_t num) 986 { 987 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8; 988 int ret; 989 990 if (mipi_dbi_command_is_read(dbi, *cmd)) 991 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num); 992 993 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num); 994 995 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); 996 if (ret || !num) 997 return ret; 998 999 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); 1000 } 1001 1002 /* MIPI DBI Type C Option 3 */ 1003 1004 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, 1005 u8 *data, size_t len) 1006 { 1007 struct spi_device *spi = dbi->spi; 1008 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED, 1009 spi->max_speed_hz / 2); 1010 struct spi_transfer tr[2] = { 1011 { 1012 .speed_hz = speed_hz, 1013 .tx_buf = cmd, 1014 .len = 1, 1015 }, { 1016 .speed_hz = speed_hz, 1017 .len = len, 1018 }, 1019 }; 1020 struct spi_message m; 1021 u8 *buf; 1022 int ret; 1023 1024 if (!len) 1025 return -EINVAL; 1026 1027 /* 1028 * Support non-standard 24-bit and 32-bit Nokia read commands which 1029 * start with a dummy clock, so we need to read an extra byte. 1030 */ 1031 if (*cmd == MIPI_DCS_GET_DISPLAY_ID || 1032 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) { 1033 if (!(len == 3 || len == 4)) 1034 return -EINVAL; 1035 1036 tr[1].len = len + 1; 1037 } 1038 1039 buf = kmalloc(tr[1].len, GFP_KERNEL); 1040 if (!buf) 1041 return -ENOMEM; 1042 1043 tr[1].rx_buf = buf; 1044 gpiod_set_value_cansleep(dbi->dc, 0); 1045 1046 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); 1047 ret = spi_sync(spi, &m); 1048 if (ret) 1049 goto err_free; 1050 1051 if (tr[1].len == len) { 1052 memcpy(data, buf, len); 1053 } else { 1054 unsigned int i; 1055 1056 for (i = 0; i < len; i++) 1057 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7); 1058 } 1059 1060 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len); 1061 1062 err_free: 1063 kfree(buf); 1064 1065 return ret; 1066 } 1067 1068 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 1069 u8 *par, size_t num) 1070 { 1071 struct spi_device *spi = dbi->spi; 1072 unsigned int bpw = 8; 1073 u32 speed_hz; 1074 int ret; 1075 1076 if (mipi_dbi_command_is_read(dbi, *cmd)) 1077 return mipi_dbi_typec3_command_read(dbi, cmd, par, num); 1078 1079 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); 1080 1081 gpiod_set_value_cansleep(dbi->dc, 0); 1082 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); 1083 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); 1084 if (ret || !num) 1085 return ret; 1086 1087 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes) 1088 bpw = 16; 1089 1090 gpiod_set_value_cansleep(dbi->dc, 1); 1091 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); 1092 1093 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); 1094 } 1095 1096 /** 1097 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface 1098 * @spi: SPI device 1099 * @dbi: MIPI DBI structure to initialize 1100 * @dc: D/C gpio (optional) 1101 * 1102 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the 1103 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or 1104 * a driver-specific init. 1105 * 1106 * If @dc is set, a Type C Option 3 interface is assumed, if not 1107 * Type C Option 1. 1108 * 1109 * If the SPI master driver doesn't support the necessary bits per word, 1110 * the following transformation is used: 1111 * 1112 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command. 1113 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes 1114 * 1115 * Returns: 1116 * Zero on success, negative error code on failure. 1117 */ 1118 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 1119 struct gpio_desc *dc) 1120 { 1121 struct device *dev = &spi->dev; 1122 int ret; 1123 1124 /* 1125 * Even though it's not the SPI device that does DMA (the master does), 1126 * the dma mask is necessary for the dma_alloc_wc() in 1127 * drm_gem_cma_create(). The dma_addr returned will be a physical 1128 * address which might be different from the bus address, but this is 1129 * not a problem since the address will not be used. 1130 * The virtual address is used in the transfer and the SPI core 1131 * re-maps it on the SPI master device using the DMA streaming API 1132 * (spi_map_buf()). 1133 */ 1134 if (!dev->coherent_dma_mask) { 1135 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1136 if (ret) { 1137 dev_warn(dev, "Failed to set dma mask %d\n", ret); 1138 return ret; 1139 } 1140 } 1141 1142 dbi->spi = spi; 1143 dbi->read_commands = mipi_dbi_dcs_read_commands; 1144 1145 if (dc) { 1146 dbi->command = mipi_dbi_typec3_command; 1147 dbi->dc = dc; 1148 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16)) 1149 dbi->swap_bytes = true; 1150 } else { 1151 dbi->command = mipi_dbi_typec1_command; 1152 dbi->tx_buf9_len = SZ_16K; 1153 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); 1154 if (!dbi->tx_buf9) 1155 return -ENOMEM; 1156 } 1157 1158 mutex_init(&dbi->cmdlock); 1159 1160 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000); 1161 1162 return 0; 1163 } 1164 EXPORT_SYMBOL(mipi_dbi_spi_init); 1165 1166 /** 1167 * mipi_dbi_spi_transfer - SPI transfer helper 1168 * @spi: SPI device 1169 * @speed_hz: Override speed (optional) 1170 * @bpw: Bits per word 1171 * @buf: Buffer to transfer 1172 * @len: Buffer length 1173 * 1174 * This SPI transfer helper breaks up the transfer of @buf into chunks which 1175 * the SPI controller driver can handle. 1176 * 1177 * Returns: 1178 * Zero on success, negative error code on failure. 1179 */ 1180 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, 1181 u8 bpw, const void *buf, size_t len) 1182 { 1183 size_t max_chunk = spi_max_transfer_size(spi); 1184 struct spi_transfer tr = { 1185 .bits_per_word = bpw, 1186 .speed_hz = speed_hz, 1187 }; 1188 struct spi_message m; 1189 size_t chunk; 1190 int ret; 1191 1192 spi_message_init_with_transfers(&m, &tr, 1); 1193 1194 while (len) { 1195 chunk = min(len, max_chunk); 1196 1197 tr.tx_buf = buf; 1198 tr.len = chunk; 1199 buf += chunk; 1200 len -= chunk; 1201 1202 ret = spi_sync(spi, &m); 1203 if (ret) 1204 return ret; 1205 } 1206 1207 return 0; 1208 } 1209 EXPORT_SYMBOL(mipi_dbi_spi_transfer); 1210 1211 #endif /* CONFIG_SPI */ 1212 1213 #ifdef CONFIG_DEBUG_FS 1214 1215 static ssize_t mipi_dbi_debugfs_command_write(struct file *file, 1216 const char __user *ubuf, 1217 size_t count, loff_t *ppos) 1218 { 1219 struct seq_file *m = file->private_data; 1220 struct mipi_dbi_dev *dbidev = m->private; 1221 u8 val, cmd = 0, parameters[64]; 1222 char *buf, *pos, *token; 1223 int i, ret, idx; 1224 1225 if (!drm_dev_enter(&dbidev->drm, &idx)) 1226 return -ENODEV; 1227 1228 buf = memdup_user_nul(ubuf, count); 1229 if (IS_ERR(buf)) { 1230 ret = PTR_ERR(buf); 1231 goto err_exit; 1232 } 1233 1234 /* strip trailing whitespace */ 1235 for (i = count - 1; i > 0; i--) 1236 if (isspace(buf[i])) 1237 buf[i] = '\0'; 1238 else 1239 break; 1240 i = 0; 1241 pos = buf; 1242 while (pos) { 1243 token = strsep(&pos, " "); 1244 if (!token) { 1245 ret = -EINVAL; 1246 goto err_free; 1247 } 1248 1249 ret = kstrtou8(token, 16, &val); 1250 if (ret < 0) 1251 goto err_free; 1252 1253 if (token == buf) 1254 cmd = val; 1255 else 1256 parameters[i++] = val; 1257 1258 if (i == 64) { 1259 ret = -E2BIG; 1260 goto err_free; 1261 } 1262 } 1263 1264 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); 1265 1266 err_free: 1267 kfree(buf); 1268 err_exit: 1269 drm_dev_exit(idx); 1270 1271 return ret < 0 ? ret : count; 1272 } 1273 1274 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused) 1275 { 1276 struct mipi_dbi_dev *dbidev = m->private; 1277 struct mipi_dbi *dbi = &dbidev->dbi; 1278 u8 cmd, val[4]; 1279 int ret, idx; 1280 size_t len; 1281 1282 if (!drm_dev_enter(&dbidev->drm, &idx)) 1283 return -ENODEV; 1284 1285 for (cmd = 0; cmd < 255; cmd++) { 1286 if (!mipi_dbi_command_is_read(dbi, cmd)) 1287 continue; 1288 1289 switch (cmd) { 1290 case MIPI_DCS_READ_MEMORY_START: 1291 case MIPI_DCS_READ_MEMORY_CONTINUE: 1292 len = 2; 1293 break; 1294 case MIPI_DCS_GET_DISPLAY_ID: 1295 len = 3; 1296 break; 1297 case MIPI_DCS_GET_DISPLAY_STATUS: 1298 len = 4; 1299 break; 1300 default: 1301 len = 1; 1302 break; 1303 } 1304 1305 seq_printf(m, "%02x: ", cmd); 1306 ret = mipi_dbi_command_buf(dbi, cmd, val, len); 1307 if (ret) { 1308 seq_puts(m, "XX\n"); 1309 continue; 1310 } 1311 seq_printf(m, "%*phN\n", (int)len, val); 1312 } 1313 1314 drm_dev_exit(idx); 1315 1316 return 0; 1317 } 1318 1319 static int mipi_dbi_debugfs_command_open(struct inode *inode, 1320 struct file *file) 1321 { 1322 return single_open(file, mipi_dbi_debugfs_command_show, 1323 inode->i_private); 1324 } 1325 1326 static const struct file_operations mipi_dbi_debugfs_command_fops = { 1327 .owner = THIS_MODULE, 1328 .open = mipi_dbi_debugfs_command_open, 1329 .read = seq_read, 1330 .llseek = seq_lseek, 1331 .release = single_release, 1332 .write = mipi_dbi_debugfs_command_write, 1333 }; 1334 1335 /** 1336 * mipi_dbi_debugfs_init - Create debugfs entries 1337 * @minor: DRM minor 1338 * 1339 * This function creates a 'command' debugfs file for sending commands to the 1340 * controller or getting the read command values. 1341 * Drivers can use this as their &drm_driver->debugfs_init callback. 1342 * 1343 */ 1344 void mipi_dbi_debugfs_init(struct drm_minor *minor) 1345 { 1346 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev); 1347 umode_t mode = S_IFREG | S_IWUSR; 1348 1349 if (dbidev->dbi.read_commands) 1350 mode |= S_IRUGO; 1351 debugfs_create_file("command", mode, minor->debugfs_root, dbidev, 1352 &mipi_dbi_debugfs_command_fops); 1353 } 1354 EXPORT_SYMBOL(mipi_dbi_debugfs_init); 1355 1356 #endif 1357 1358 MODULE_LICENSE("GPL"); 1359