1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 91 #define MICROSOFT_IEEE_OUI 0xca125c 92 93 struct detailed_mode_closure { 94 struct drm_connector *connector; 95 const struct drm_edid *drm_edid; 96 bool preferred; 97 u32 quirks; 98 int modes; 99 }; 100 101 #define LEVEL_DMT 0 102 #define LEVEL_GTF 1 103 #define LEVEL_GTF2 2 104 #define LEVEL_CVT 3 105 106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 107 { \ 108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 109 product_id), \ 110 .quirks = _quirks \ 111 } 112 113 static const struct edid_quirk { 114 u32 panel_id; 115 u32 quirks; 116 } edid_quirk_list[] = { 117 /* Acer AL1706 */ 118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 119 /* Acer F51 */ 120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 121 122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 124 125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 127 128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 130 131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 133 134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 136 137 /* Belinea 10 15 55 */ 138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 140 141 /* Envision Peripherals, Inc. EN-7100e */ 142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 143 /* Envision EN2028 */ 144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 145 146 /* Funai Electronics PM36B */ 147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 148 EDID_QUIRK_DETAILED_IN_CM), 149 150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 152 153 /* LG Philips LCD LP154W01-A5 */ 154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 156 157 /* Samsung SyncMaster 205BW. Note: irony */ 158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 159 /* Samsung SyncMaster 22[5-6]BW */ 160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 162 163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 165 166 /* ViewSonic VA2026w */ 167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 168 169 /* Medion MD 30217 PG */ 170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 171 172 /* Lenovo G50 */ 173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 174 175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 177 178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 180 181 /* Valve Index Headset */ 182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 199 200 /* HTC Vive and Vive Pro VR Headsets */ 201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 203 204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 209 210 /* Windows Mixed Reality Headsets */ 211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 217 218 /* Sony PlayStation VR Headset */ 219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 220 221 /* Sensics VR Headsets */ 222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 223 224 /* OSVR HDK and HDK2 VR Headsets */ 225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 226 }; 227 228 /* 229 * Autogenerated from the DMT spec. 230 * This table is copied from xfree86/modes/xf86EdidModes.c. 231 */ 232 static const struct drm_display_mode drm_dmt_modes[] = { 233 /* 0x01 - 640x350@85Hz */ 234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 235 736, 832, 0, 350, 382, 385, 445, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 0x02 - 640x400@85Hz */ 238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 239 736, 832, 0, 400, 401, 404, 445, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 0x03 - 720x400@85Hz */ 242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 243 828, 936, 0, 400, 401, 404, 446, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 0x04 - 640x480@60Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 247 752, 800, 0, 480, 490, 492, 525, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x05 - 640x480@72Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 251 704, 832, 0, 480, 489, 492, 520, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x06 - 640x480@75Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 255 720, 840, 0, 480, 481, 484, 500, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x07 - 640x480@85Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 259 752, 832, 0, 480, 481, 484, 509, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x08 - 800x600@56Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 263 896, 1024, 0, 600, 601, 603, 625, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x09 - 800x600@60Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 267 968, 1056, 0, 600, 601, 605, 628, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0a - 800x600@72Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 271 976, 1040, 0, 600, 637, 643, 666, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0b - 800x600@75Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 275 896, 1056, 0, 600, 601, 604, 625, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0c - 800x600@85Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 279 896, 1048, 0, 600, 601, 604, 631, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0d - 800x600@120Hz RB */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 283 880, 960, 0, 600, 603, 607, 636, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 285 /* 0x0e - 848x480@60Hz */ 286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 287 976, 1088, 0, 480, 486, 494, 517, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0f - 1024x768@43Hz, interlace */ 290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 291 1208, 1264, 0, 768, 768, 776, 817, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 293 DRM_MODE_FLAG_INTERLACE) }, 294 /* 0x10 - 1024x768@60Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 296 1184, 1344, 0, 768, 771, 777, 806, 0, 297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 298 /* 0x11 - 1024x768@70Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 300 1184, 1328, 0, 768, 771, 777, 806, 0, 301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 302 /* 0x12 - 1024x768@75Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 304 1136, 1312, 0, 768, 769, 772, 800, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x13 - 1024x768@85Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 308 1168, 1376, 0, 768, 769, 772, 808, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x14 - 1024x768@120Hz RB */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 312 1104, 1184, 0, 768, 771, 775, 813, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x15 - 1152x864@75Hz */ 315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 316 1344, 1600, 0, 864, 865, 868, 900, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x55 - 1280x720@60Hz */ 319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 320 1430, 1650, 0, 720, 725, 730, 750, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x16 - 1280x768@60Hz RB */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 324 1360, 1440, 0, 768, 771, 778, 790, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 326 /* 0x17 - 1280x768@60Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 328 1472, 1664, 0, 768, 771, 778, 798, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x18 - 1280x768@75Hz */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 332 1488, 1696, 0, 768, 771, 778, 805, 0, 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 334 /* 0x19 - 1280x768@85Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 336 1496, 1712, 0, 768, 771, 778, 809, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x1a - 1280x768@120Hz RB */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 340 1360, 1440, 0, 768, 771, 778, 813, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 342 /* 0x1b - 1280x800@60Hz RB */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 344 1360, 1440, 0, 800, 803, 809, 823, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 346 /* 0x1c - 1280x800@60Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 348 1480, 1680, 0, 800, 803, 809, 831, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1d - 1280x800@75Hz */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 352 1488, 1696, 0, 800, 803, 809, 838, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x1e - 1280x800@85Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 356 1496, 1712, 0, 800, 803, 809, 843, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1f - 1280x800@120Hz RB */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 360 1360, 1440, 0, 800, 803, 809, 847, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x20 - 1280x960@60Hz */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 364 1488, 1800, 0, 960, 961, 964, 1000, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x21 - 1280x960@85Hz */ 367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 368 1504, 1728, 0, 960, 961, 964, 1011, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x22 - 1280x960@120Hz RB */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 372 1360, 1440, 0, 960, 963, 967, 1017, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 374 /* 0x23 - 1280x1024@60Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x24 - 1280x1024@75Hz */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x25 - 1280x1024@85Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x26 - 1280x1024@120Hz RB */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x27 - 1360x768@60Hz */ 391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 392 1536, 1792, 0, 768, 771, 777, 795, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x28 - 1360x768@120Hz RB */ 395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 396 1440, 1520, 0, 768, 771, 776, 813, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x51 - 1366x768@60Hz */ 399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 400 1579, 1792, 0, 768, 771, 774, 798, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x56 - 1366x768@60Hz */ 403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 404 1436, 1500, 0, 768, 769, 772, 800, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x29 - 1400x1050@60Hz RB */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 410 /* 0x2a - 1400x1050@60Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2b - 1400x1050@75Hz */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x2c - 1400x1050@85Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2d - 1400x1050@120Hz RB */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 426 /* 0x2e - 1440x900@60Hz RB */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 428 1520, 1600, 0, 900, 903, 909, 926, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 430 /* 0x2f - 1440x900@60Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 432 1672, 1904, 0, 900, 903, 909, 934, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x30 - 1440x900@75Hz */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 436 1688, 1936, 0, 900, 903, 909, 942, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x31 - 1440x900@85Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 440 1696, 1952, 0, 900, 903, 909, 948, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x32 - 1440x900@120Hz RB */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 444 1520, 1600, 0, 900, 903, 909, 953, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 446 /* 0x53 - 1600x900@60Hz */ 447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 448 1704, 1800, 0, 900, 901, 904, 1000, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x33 - 1600x1200@60Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x34 - 1600x1200@65Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x35 - 1600x1200@70Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x36 - 1600x1200@75Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x37 - 1600x1200@85Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x38 - 1600x1200@120Hz RB */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 474 /* 0x39 - 1680x1050@60Hz RB */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x3a - 1680x1050@60Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3b - 1680x1050@75Hz */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x3c - 1680x1050@85Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3d - 1680x1050@120Hz RB */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 494 /* 0x3e - 1792x1344@60Hz */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3f - 1792x1344@75Hz */ 499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x40 - 1792x1344@120Hz RB */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x41 - 1856x1392@60Hz */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x42 - 1856x1392@75Hz */ 511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x43 - 1856x1392@120Hz RB */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x52 - 1920x1080@60Hz */ 519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 522 /* 0x44 - 1920x1200@60Hz RB */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x45 - 1920x1200@60Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x46 - 1920x1200@75Hz */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x47 - 1920x1200@85Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x48 - 1920x1200@120Hz RB */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 542 /* 0x49 - 1920x1440@60Hz */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x4a - 1920x1440@75Hz */ 547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4b - 1920x1440@120Hz RB */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x54 - 2048x1152@60Hz */ 555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4c - 2560x1600@60Hz RB */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x4d - 2560x1600@60Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4e - 2560x1600@75Hz */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 570 /* 0x4f - 2560x1600@85Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x50 - 2560x1600@120Hz RB */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 /* 0x57 - 4096x2160@60Hz RB */ 579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 582 /* 0x58 - 4096x2160@59.94Hz RB */ 583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 }; 587 588 /* 589 * These more or less come from the DMT spec. The 720x400 modes are 590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 593 * mode. 594 * 595 * The DMT modes have been fact-checked; the rest are mild guesses. 596 */ 597 static const struct drm_display_mode edid_est_modes[] = { 598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 599 968, 1056, 0, 600, 601, 605, 628, 0, 600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 602 896, 1024, 0, 600, 601, 603, 625, 0, 603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 605 720, 840, 0, 480, 481, 484, 500, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 608 704, 832, 0, 480, 489, 492, 520, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 611 768, 864, 0, 480, 483, 486, 525, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 614 752, 800, 0, 480, 490, 492, 525, 0, 615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 617 846, 900, 0, 400, 421, 423, 449, 0, 618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 620 846, 900, 0, 400, 412, 414, 449, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 626 1136, 1312, 0, 768, 769, 772, 800, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 629 1184, 1328, 0, 768, 771, 777, 806, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 632 1184, 1344, 0, 768, 771, 777, 806, 0, 633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 635 1208, 1264, 0, 768, 768, 776, 817, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 638 928, 1152, 0, 624, 625, 628, 667, 0, 639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 641 896, 1056, 0, 600, 601, 604, 625, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 644 976, 1040, 0, 600, 637, 643, 666, 0, 645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 647 1344, 1600, 0, 864, 865, 868, 900, 0, 648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 649 }; 650 651 struct minimode { 652 short w; 653 short h; 654 short r; 655 short rb; 656 }; 657 658 static const struct minimode est3_modes[] = { 659 /* byte 6 */ 660 { 640, 350, 85, 0 }, 661 { 640, 400, 85, 0 }, 662 { 720, 400, 85, 0 }, 663 { 640, 480, 85, 0 }, 664 { 848, 480, 60, 0 }, 665 { 800, 600, 85, 0 }, 666 { 1024, 768, 85, 0 }, 667 { 1152, 864, 75, 0 }, 668 /* byte 7 */ 669 { 1280, 768, 60, 1 }, 670 { 1280, 768, 60, 0 }, 671 { 1280, 768, 75, 0 }, 672 { 1280, 768, 85, 0 }, 673 { 1280, 960, 60, 0 }, 674 { 1280, 960, 85, 0 }, 675 { 1280, 1024, 60, 0 }, 676 { 1280, 1024, 85, 0 }, 677 /* byte 8 */ 678 { 1360, 768, 60, 0 }, 679 { 1440, 900, 60, 1 }, 680 { 1440, 900, 60, 0 }, 681 { 1440, 900, 75, 0 }, 682 { 1440, 900, 85, 0 }, 683 { 1400, 1050, 60, 1 }, 684 { 1400, 1050, 60, 0 }, 685 { 1400, 1050, 75, 0 }, 686 /* byte 9 */ 687 { 1400, 1050, 85, 0 }, 688 { 1680, 1050, 60, 1 }, 689 { 1680, 1050, 60, 0 }, 690 { 1680, 1050, 75, 0 }, 691 { 1680, 1050, 85, 0 }, 692 { 1600, 1200, 60, 0 }, 693 { 1600, 1200, 65, 0 }, 694 { 1600, 1200, 70, 0 }, 695 /* byte 10 */ 696 { 1600, 1200, 75, 0 }, 697 { 1600, 1200, 85, 0 }, 698 { 1792, 1344, 60, 0 }, 699 { 1792, 1344, 75, 0 }, 700 { 1856, 1392, 60, 0 }, 701 { 1856, 1392, 75, 0 }, 702 { 1920, 1200, 60, 1 }, 703 { 1920, 1200, 60, 0 }, 704 /* byte 11 */ 705 { 1920, 1200, 75, 0 }, 706 { 1920, 1200, 85, 0 }, 707 { 1920, 1440, 60, 0 }, 708 { 1920, 1440, 75, 0 }, 709 }; 710 711 static const struct minimode extra_modes[] = { 712 { 1024, 576, 60, 0 }, 713 { 1366, 768, 60, 0 }, 714 { 1600, 900, 60, 0 }, 715 { 1680, 945, 60, 0 }, 716 { 1920, 1080, 60, 0 }, 717 { 2048, 1152, 60, 0 }, 718 { 2048, 1536, 60, 0 }, 719 }; 720 721 /* 722 * From CEA/CTA-861 spec. 723 * 724 * Do not access directly, instead always use cea_mode_for_vic(). 725 */ 726 static const struct drm_display_mode edid_cea_modes_1[] = { 727 /* 1 - 640x480@60Hz 4:3 */ 728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 729 752, 800, 0, 480, 490, 492, 525, 0, 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 732 /* 2 - 720x480@60Hz 4:3 */ 733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 734 798, 858, 0, 480, 489, 495, 525, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 3 - 720x480@60Hz 16:9 */ 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 739 798, 858, 0, 480, 489, 495, 525, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 4 - 1280x720@60Hz 16:9 */ 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 744 1430, 1650, 0, 720, 725, 730, 750, 0, 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 5 - 1920x1080i@60Hz 16:9 */ 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 6 - 720(1440)x480i@60Hz 4:3 */ 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 755 801, 858, 0, 480, 488, 494, 525, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 759 /* 7 - 720(1440)x480i@60Hz 16:9 */ 760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 761 801, 858, 0, 480, 488, 494, 525, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 8 - 720(1440)x240@60Hz 4:3 */ 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 767 801, 858, 0, 240, 244, 247, 262, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 9 - 720(1440)x240@60Hz 16:9 */ 772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 773 801, 858, 0, 240, 244, 247, 262, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_DBLCLK), 776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 10 - 2880x480i@60Hz 4:3 */ 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 779 3204, 3432, 0, 480, 488, 494, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 11 - 2880x480i@60Hz 16:9 */ 784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 785 3204, 3432, 0, 480, 488, 494, 525, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_INTERLACE), 788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 12 - 2880x240@60Hz 4:3 */ 790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 791 3204, 3432, 0, 240, 244, 247, 262, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 13 - 2880x240@60Hz 16:9 */ 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 240, 244, 247, 262, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 14 - 1440x480@60Hz 4:3 */ 800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 801 1596, 1716, 0, 480, 489, 495, 525, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 804 /* 15 - 1440x480@60Hz 16:9 */ 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 806 1596, 1716, 0, 480, 489, 495, 525, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 16 - 1920x1080@60Hz 16:9 */ 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 17 - 720x576@50Hz 4:3 */ 815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 816 796, 864, 0, 576, 581, 586, 625, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 819 /* 18 - 720x576@50Hz 16:9 */ 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 821 796, 864, 0, 576, 581, 586, 625, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 19 - 1280x720@50Hz 16:9 */ 825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 826 1760, 1980, 0, 720, 725, 730, 750, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 20 - 1920x1080i@50Hz 16:9 */ 830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 833 DRM_MODE_FLAG_INTERLACE), 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 21 - 720(1440)x576i@50Hz 4:3 */ 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 837 795, 864, 0, 576, 580, 586, 625, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 841 /* 22 - 720(1440)x576i@50Hz 16:9 */ 842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 843 795, 864, 0, 576, 580, 586, 625, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 847 /* 23 - 720(1440)x288@50Hz 4:3 */ 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 849 795, 864, 0, 288, 290, 293, 312, 0, 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 851 DRM_MODE_FLAG_DBLCLK), 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 24 - 720(1440)x288@50Hz 16:9 */ 854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 855 795, 864, 0, 288, 290, 293, 312, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 857 DRM_MODE_FLAG_DBLCLK), 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 25 - 2880x576i@50Hz 4:3 */ 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 861 3180, 3456, 0, 576, 580, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 865 /* 26 - 2880x576i@50Hz 16:9 */ 866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 867 3180, 3456, 0, 576, 580, 586, 625, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 869 DRM_MODE_FLAG_INTERLACE), 870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 871 /* 27 - 2880x288@50Hz 4:3 */ 872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 873 3180, 3456, 0, 288, 290, 293, 312, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 28 - 2880x288@50Hz 16:9 */ 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 288, 290, 293, 312, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 881 /* 29 - 1440x576@50Hz 4:3 */ 882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 883 1592, 1728, 0, 576, 581, 586, 625, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 886 /* 30 - 1440x576@50Hz 16:9 */ 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 888 1592, 1728, 0, 576, 581, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 891 /* 31 - 1920x1080@50Hz 16:9 */ 892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 896 /* 32 - 1920x1080@24Hz 16:9 */ 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 33 - 1920x1080@25Hz 16:9 */ 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 34 - 1920x1080@30Hz 16:9 */ 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 911 /* 35 - 2880x480@60Hz 4:3 */ 912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 913 3192, 3432, 0, 480, 489, 495, 525, 0, 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 916 /* 36 - 2880x480@60Hz 16:9 */ 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 918 3192, 3432, 0, 480, 489, 495, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 37 - 2880x576@50Hz 4:3 */ 922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 923 3184, 3456, 0, 576, 581, 586, 625, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 926 /* 38 - 2880x576@50Hz 16:9 */ 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 928 3184, 3456, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 39 - 1920x1080i@50Hz 16:9 */ 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 935 DRM_MODE_FLAG_INTERLACE), 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 937 /* 40 - 1920x1080i@100Hz 16:9 */ 938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 941 DRM_MODE_FLAG_INTERLACE), 942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 41 - 1280x720@100Hz 16:9 */ 944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 945 1760, 1980, 0, 720, 725, 730, 750, 0, 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 42 - 720x576@100Hz 4:3 */ 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 950 796, 864, 0, 576, 581, 586, 625, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 953 /* 43 - 720x576@100Hz 16:9 */ 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 955 796, 864, 0, 576, 581, 586, 625, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 /* 44 - 720(1440)x576i@100Hz 4:3 */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 45 - 720(1440)x576i@100Hz 16:9 */ 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 966 795, 864, 0, 576, 580, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 46 - 1920x1080i@120Hz 16:9 */ 971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 974 DRM_MODE_FLAG_INTERLACE), 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 976 /* 47 - 1280x720@120Hz 16:9 */ 977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 978 1430, 1650, 0, 720, 725, 730, 750, 0, 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 48 - 720x480@120Hz 4:3 */ 982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 983 798, 858, 0, 480, 489, 495, 525, 0, 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 986 /* 49 - 720x480@120Hz 16:9 */ 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 988 798, 858, 0, 480, 489, 495, 525, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 991 /* 50 - 720(1440)x480i@120Hz 4:3 */ 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 993 801, 858, 0, 480, 488, 494, 525, 0, 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 997 /* 51 - 720(1440)x480i@120Hz 16:9 */ 998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 999 801, 858, 0, 480, 488, 494, 525, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1003 /* 52 - 720x576@200Hz 4:3 */ 1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1005 796, 864, 0, 576, 581, 586, 625, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1008 /* 53 - 720x576@200Hz 16:9 */ 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1010 796, 864, 0, 576, 581, 586, 625, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1013 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1015 795, 864, 0, 576, 580, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1019 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1021 795, 864, 0, 576, 580, 586, 625, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1025 /* 56 - 720x480@240Hz 4:3 */ 1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1027 798, 858, 0, 480, 489, 495, 525, 0, 1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1030 /* 57 - 720x480@240Hz 16:9 */ 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1032 798, 858, 0, 480, 489, 495, 525, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1035 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1037 801, 858, 0, 480, 488, 494, 525, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1041 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1043 801, 858, 0, 480, 488, 494, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1047 /* 60 - 1280x720@24Hz 16:9 */ 1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1049 3080, 3300, 0, 720, 725, 730, 750, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1052 /* 61 - 1280x720@25Hz 16:9 */ 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1054 3740, 3960, 0, 720, 725, 730, 750, 0, 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1057 /* 62 - 1280x720@30Hz 16:9 */ 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1059 3080, 3300, 0, 720, 725, 730, 750, 0, 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1062 /* 63 - 1920x1080@120Hz 16:9 */ 1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1067 /* 64 - 1920x1080@100Hz 16:9 */ 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1072 /* 65 - 1280x720@24Hz 64:27 */ 1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1074 3080, 3300, 0, 720, 725, 730, 750, 0, 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1077 /* 66 - 1280x720@25Hz 64:27 */ 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1079 3740, 3960, 0, 720, 725, 730, 750, 0, 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1082 /* 67 - 1280x720@30Hz 64:27 */ 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1084 3080, 3300, 0, 720, 725, 730, 750, 0, 1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1087 /* 68 - 1280x720@50Hz 64:27 */ 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1089 1760, 1980, 0, 720, 725, 730, 750, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1092 /* 69 - 1280x720@60Hz 64:27 */ 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1094 1430, 1650, 0, 720, 725, 730, 750, 0, 1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1097 /* 70 - 1280x720@100Hz 64:27 */ 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1099 1760, 1980, 0, 720, 725, 730, 750, 0, 1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1102 /* 71 - 1280x720@120Hz 64:27 */ 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1104 1430, 1650, 0, 720, 725, 730, 750, 0, 1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1107 /* 72 - 1920x1080@24Hz 64:27 */ 1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1112 /* 73 - 1920x1080@25Hz 64:27 */ 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1117 /* 74 - 1920x1080@30Hz 64:27 */ 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1122 /* 75 - 1920x1080@50Hz 64:27 */ 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1127 /* 76 - 1920x1080@60Hz 64:27 */ 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1132 /* 77 - 1920x1080@100Hz 64:27 */ 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1137 /* 78 - 1920x1080@120Hz 64:27 */ 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1142 /* 79 - 1680x720@24Hz 64:27 */ 1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1144 3080, 3300, 0, 720, 725, 730, 750, 0, 1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1147 /* 80 - 1680x720@25Hz 64:27 */ 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1149 2948, 3168, 0, 720, 725, 730, 750, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1152 /* 81 - 1680x720@30Hz 64:27 */ 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1154 2420, 2640, 0, 720, 725, 730, 750, 0, 1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1157 /* 82 - 1680x720@50Hz 64:27 */ 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1159 1980, 2200, 0, 720, 725, 730, 750, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1162 /* 83 - 1680x720@60Hz 64:27 */ 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1164 1980, 2200, 0, 720, 725, 730, 750, 0, 1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1167 /* 84 - 1680x720@100Hz 64:27 */ 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1169 1780, 2000, 0, 720, 725, 730, 825, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1172 /* 85 - 1680x720@120Hz 64:27 */ 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1174 1780, 2000, 0, 720, 725, 730, 825, 0, 1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1177 /* 86 - 2560x1080@24Hz 64:27 */ 1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1182 /* 87 - 2560x1080@25Hz 64:27 */ 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1187 /* 88 - 2560x1080@30Hz 64:27 */ 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1192 /* 89 - 2560x1080@50Hz 64:27 */ 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1197 /* 90 - 2560x1080@60Hz 64:27 */ 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1202 /* 91 - 2560x1080@100Hz 64:27 */ 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1207 /* 92 - 2560x1080@120Hz 64:27 */ 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1212 /* 93 - 3840x2160@24Hz 16:9 */ 1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1217 /* 94 - 3840x2160@25Hz 16:9 */ 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1222 /* 95 - 3840x2160@30Hz 16:9 */ 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1227 /* 96 - 3840x2160@50Hz 16:9 */ 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1232 /* 97 - 3840x2160@60Hz 16:9 */ 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1237 /* 98 - 4096x2160@24Hz 256:135 */ 1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1242 /* 99 - 4096x2160@25Hz 256:135 */ 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1247 /* 100 - 4096x2160@30Hz 256:135 */ 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1252 /* 101 - 4096x2160@50Hz 256:135 */ 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1257 /* 102 - 4096x2160@60Hz 256:135 */ 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1262 /* 103 - 3840x2160@24Hz 64:27 */ 1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1267 /* 104 - 3840x2160@25Hz 64:27 */ 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1272 /* 105 - 3840x2160@30Hz 64:27 */ 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1277 /* 106 - 3840x2160@50Hz 64:27 */ 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1282 /* 107 - 3840x2160@60Hz 64:27 */ 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1287 /* 108 - 1280x720@48Hz 16:9 */ 1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1289 2280, 2500, 0, 720, 725, 730, 750, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1292 /* 109 - 1280x720@48Hz 64:27 */ 1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1294 2280, 2500, 0, 720, 725, 730, 750, 0, 1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1297 /* 110 - 1680x720@48Hz 64:27 */ 1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1299 2530, 2750, 0, 720, 725, 730, 750, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1302 /* 111 - 1920x1080@48Hz 16:9 */ 1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1307 /* 112 - 1920x1080@48Hz 64:27 */ 1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1312 /* 113 - 2560x1080@48Hz 64:27 */ 1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1317 /* 114 - 3840x2160@48Hz 16:9 */ 1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1322 /* 115 - 4096x2160@48Hz 256:135 */ 1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1327 /* 116 - 3840x2160@48Hz 64:27 */ 1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1332 /* 117 - 3840x2160@100Hz 16:9 */ 1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1337 /* 118 - 3840x2160@120Hz 16:9 */ 1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1342 /* 119 - 3840x2160@100Hz 64:27 */ 1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1347 /* 120 - 3840x2160@120Hz 64:27 */ 1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1352 /* 121 - 5120x2160@24Hz 64:27 */ 1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1357 /* 122 - 5120x2160@25Hz 64:27 */ 1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1362 /* 123 - 5120x2160@30Hz 64:27 */ 1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1367 /* 124 - 5120x2160@48Hz 64:27 */ 1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1372 /* 125 - 5120x2160@50Hz 64:27 */ 1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1377 /* 126 - 5120x2160@60Hz 64:27 */ 1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1382 /* 127 - 5120x2160@100Hz 64:27 */ 1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1387 }; 1388 1389 /* 1390 * From CEA/CTA-861 spec. 1391 * 1392 * Do not access directly, instead always use cea_mode_for_vic(). 1393 */ 1394 static const struct drm_display_mode edid_cea_modes_193[] = { 1395 /* 193 - 5120x2160@120Hz 64:27 */ 1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1400 /* 194 - 7680x4320@24Hz 16:9 */ 1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1405 /* 195 - 7680x4320@25Hz 16:9 */ 1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1410 /* 196 - 7680x4320@30Hz 16:9 */ 1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1415 /* 197 - 7680x4320@48Hz 16:9 */ 1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1420 /* 198 - 7680x4320@50Hz 16:9 */ 1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1425 /* 199 - 7680x4320@60Hz 16:9 */ 1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1430 /* 200 - 7680x4320@100Hz 16:9 */ 1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1435 /* 201 - 7680x4320@120Hz 16:9 */ 1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1440 /* 202 - 7680x4320@24Hz 64:27 */ 1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1445 /* 203 - 7680x4320@25Hz 64:27 */ 1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1450 /* 204 - 7680x4320@30Hz 64:27 */ 1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1455 /* 205 - 7680x4320@48Hz 64:27 */ 1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1460 /* 206 - 7680x4320@50Hz 64:27 */ 1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1465 /* 207 - 7680x4320@60Hz 64:27 */ 1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1470 /* 208 - 7680x4320@100Hz 64:27 */ 1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1475 /* 209 - 7680x4320@120Hz 64:27 */ 1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1480 /* 210 - 10240x4320@24Hz 64:27 */ 1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1485 /* 211 - 10240x4320@25Hz 64:27 */ 1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1490 /* 212 - 10240x4320@30Hz 64:27 */ 1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1495 /* 213 - 10240x4320@48Hz 64:27 */ 1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1500 /* 214 - 10240x4320@50Hz 64:27 */ 1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1505 /* 215 - 10240x4320@60Hz 64:27 */ 1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1510 /* 216 - 10240x4320@100Hz 64:27 */ 1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1515 /* 217 - 10240x4320@120Hz 64:27 */ 1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1520 /* 218 - 4096x2160@100Hz 256:135 */ 1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1525 /* 219 - 4096x2160@120Hz 256:135 */ 1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1530 }; 1531 1532 /* 1533 * HDMI 1.4 4k modes. Index using the VIC. 1534 */ 1535 static const struct drm_display_mode edid_4k_modes[] = { 1536 /* 0 - dummy, VICs start at 1 */ 1537 { }, 1538 /* 1 - 3840x2160@30Hz */ 1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1540 3840, 4016, 4104, 4400, 0, 1541 2160, 2168, 2178, 2250, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1544 /* 2 - 3840x2160@25Hz */ 1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1546 3840, 4896, 4984, 5280, 0, 1547 2160, 2168, 2178, 2250, 0, 1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1550 /* 3 - 3840x2160@24Hz */ 1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1552 3840, 5116, 5204, 5500, 0, 1553 2160, 2168, 2178, 2250, 0, 1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1556 /* 4 - 4096x2160@24Hz (SMPTE) */ 1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1558 4096, 5116, 5204, 5500, 0, 1559 2160, 2168, 2178, 2250, 0, 1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1562 }; 1563 1564 /*** DDC fetch and block validation ***/ 1565 1566 /* 1567 * The opaque EDID type, internal to drm_edid.c. 1568 */ 1569 struct drm_edid { 1570 /* Size allocated for edid */ 1571 size_t size; 1572 const struct edid *edid; 1573 }; 1574 1575 static bool version_greater(const struct drm_edid *drm_edid, 1576 u8 version, u8 revision) 1577 { 1578 const struct edid *edid = drm_edid->edid; 1579 1580 return edid->version > version || 1581 (edid->version == version && edid->revision > revision); 1582 } 1583 1584 static int edid_extension_block_count(const struct edid *edid) 1585 { 1586 return edid->extensions; 1587 } 1588 1589 static int edid_block_count(const struct edid *edid) 1590 { 1591 return edid_extension_block_count(edid) + 1; 1592 } 1593 1594 static int edid_size_by_blocks(int num_blocks) 1595 { 1596 return num_blocks * EDID_LENGTH; 1597 } 1598 1599 static int edid_size(const struct edid *edid) 1600 { 1601 return edid_size_by_blocks(edid_block_count(edid)); 1602 } 1603 1604 static const void *edid_block_data(const struct edid *edid, int index) 1605 { 1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1607 1608 return edid + index; 1609 } 1610 1611 static const void *edid_extension_block_data(const struct edid *edid, int index) 1612 { 1613 return edid_block_data(edid, index + 1); 1614 } 1615 1616 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1617 { 1618 int num_blocks; 1619 1620 /* Starting point */ 1621 num_blocks = edid_block_count(drm_edid->edid); 1622 1623 /* Limit by allocated size */ 1624 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH); 1625 1626 return num_blocks; 1627 } 1628 1629 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1630 { 1631 return drm_edid_block_count(drm_edid) - 1; 1632 } 1633 1634 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1635 { 1636 return edid_block_data(drm_edid->edid, index); 1637 } 1638 1639 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1640 int index) 1641 { 1642 return edid_extension_block_data(drm_edid->edid, index); 1643 } 1644 1645 /* 1646 * Initializer helper for legacy interfaces, where we have no choice but to 1647 * trust edid size. Not for general purpose use. 1648 */ 1649 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1650 const struct edid *edid) 1651 { 1652 if (!edid) 1653 return NULL; 1654 1655 memset(drm_edid, 0, sizeof(*drm_edid)); 1656 1657 drm_edid->edid = edid; 1658 drm_edid->size = edid_size(edid); 1659 1660 return drm_edid; 1661 } 1662 1663 /* 1664 * EDID base and extension block iterator. 1665 * 1666 * struct drm_edid_iter iter; 1667 * const u8 *block; 1668 * 1669 * drm_edid_iter_begin(drm_edid, &iter); 1670 * drm_edid_iter_for_each(block, &iter) { 1671 * // do stuff with block 1672 * } 1673 * drm_edid_iter_end(&iter); 1674 */ 1675 struct drm_edid_iter { 1676 const struct drm_edid *drm_edid; 1677 1678 /* Current block index. */ 1679 int index; 1680 }; 1681 1682 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1683 struct drm_edid_iter *iter) 1684 { 1685 memset(iter, 0, sizeof(*iter)); 1686 1687 iter->drm_edid = drm_edid; 1688 } 1689 1690 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1691 { 1692 const void *block = NULL; 1693 1694 if (!iter->drm_edid) 1695 return NULL; 1696 1697 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1698 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1699 1700 return block; 1701 } 1702 1703 #define drm_edid_iter_for_each(__block, __iter) \ 1704 while (((__block) = __drm_edid_iter_next(__iter))) 1705 1706 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1707 { 1708 memset(iter, 0, sizeof(*iter)); 1709 } 1710 1711 static const u8 edid_header[] = { 1712 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1713 }; 1714 1715 static void edid_header_fix(void *edid) 1716 { 1717 memcpy(edid, edid_header, sizeof(edid_header)); 1718 } 1719 1720 /** 1721 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1722 * @_edid: pointer to raw base EDID block 1723 * 1724 * Sanity check the header of the base EDID block. 1725 * 1726 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1727 */ 1728 int drm_edid_header_is_valid(const void *_edid) 1729 { 1730 const struct edid *edid = _edid; 1731 int i, score = 0; 1732 1733 for (i = 0; i < sizeof(edid_header); i++) { 1734 if (edid->header[i] == edid_header[i]) 1735 score++; 1736 } 1737 1738 return score; 1739 } 1740 EXPORT_SYMBOL(drm_edid_header_is_valid); 1741 1742 static int edid_fixup __read_mostly = 6; 1743 module_param_named(edid_fixup, edid_fixup, int, 0400); 1744 MODULE_PARM_DESC(edid_fixup, 1745 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1746 1747 static int edid_block_compute_checksum(const void *_block) 1748 { 1749 const u8 *block = _block; 1750 int i; 1751 u8 csum = 0, crc = 0; 1752 1753 for (i = 0; i < EDID_LENGTH - 1; i++) 1754 csum += block[i]; 1755 1756 crc = 0x100 - csum; 1757 1758 return crc; 1759 } 1760 1761 static int edid_block_get_checksum(const void *_block) 1762 { 1763 const struct edid *block = _block; 1764 1765 return block->checksum; 1766 } 1767 1768 static int edid_block_tag(const void *_block) 1769 { 1770 const u8 *block = _block; 1771 1772 return block[0]; 1773 } 1774 1775 static bool edid_block_is_zero(const void *edid) 1776 { 1777 return !memchr_inv(edid, 0, EDID_LENGTH); 1778 } 1779 1780 /** 1781 * drm_edid_are_equal - compare two edid blobs. 1782 * @edid1: pointer to first blob 1783 * @edid2: pointer to second blob 1784 * This helper can be used during probing to determine if 1785 * edid had changed. 1786 */ 1787 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1788 { 1789 int edid1_len, edid2_len; 1790 bool edid1_present = edid1 != NULL; 1791 bool edid2_present = edid2 != NULL; 1792 1793 if (edid1_present != edid2_present) 1794 return false; 1795 1796 if (edid1) { 1797 edid1_len = edid_size(edid1); 1798 edid2_len = edid_size(edid2); 1799 1800 if (edid1_len != edid2_len) 1801 return false; 1802 1803 if (memcmp(edid1, edid2, edid1_len)) 1804 return false; 1805 } 1806 1807 return true; 1808 } 1809 EXPORT_SYMBOL(drm_edid_are_equal); 1810 1811 enum edid_block_status { 1812 EDID_BLOCK_OK = 0, 1813 EDID_BLOCK_READ_FAIL, 1814 EDID_BLOCK_NULL, 1815 EDID_BLOCK_ZERO, 1816 EDID_BLOCK_HEADER_CORRUPT, 1817 EDID_BLOCK_HEADER_REPAIR, 1818 EDID_BLOCK_HEADER_FIXED, 1819 EDID_BLOCK_CHECKSUM, 1820 EDID_BLOCK_VERSION, 1821 }; 1822 1823 static enum edid_block_status edid_block_check(const void *_block, 1824 bool is_base_block) 1825 { 1826 const struct edid *block = _block; 1827 1828 if (!block) 1829 return EDID_BLOCK_NULL; 1830 1831 if (is_base_block) { 1832 int score = drm_edid_header_is_valid(block); 1833 1834 if (score < clamp(edid_fixup, 0, 8)) { 1835 if (edid_block_is_zero(block)) 1836 return EDID_BLOCK_ZERO; 1837 else 1838 return EDID_BLOCK_HEADER_CORRUPT; 1839 } 1840 1841 if (score < 8) 1842 return EDID_BLOCK_HEADER_REPAIR; 1843 } 1844 1845 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1846 if (edid_block_is_zero(block)) 1847 return EDID_BLOCK_ZERO; 1848 else 1849 return EDID_BLOCK_CHECKSUM; 1850 } 1851 1852 if (is_base_block) { 1853 if (block->version != 1) 1854 return EDID_BLOCK_VERSION; 1855 } 1856 1857 return EDID_BLOCK_OK; 1858 } 1859 1860 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1861 { 1862 return status == EDID_BLOCK_OK || 1863 status == EDID_BLOCK_HEADER_FIXED || 1864 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1865 } 1866 1867 static bool edid_block_valid(const void *block, bool base) 1868 { 1869 return edid_block_status_valid(edid_block_check(block, base), 1870 edid_block_tag(block)); 1871 } 1872 1873 static void edid_block_status_print(enum edid_block_status status, 1874 const struct edid *block, 1875 int block_num) 1876 { 1877 switch (status) { 1878 case EDID_BLOCK_OK: 1879 break; 1880 case EDID_BLOCK_READ_FAIL: 1881 pr_debug("EDID block %d read failed\n", block_num); 1882 break; 1883 case EDID_BLOCK_NULL: 1884 pr_debug("EDID block %d pointer is NULL\n", block_num); 1885 break; 1886 case EDID_BLOCK_ZERO: 1887 pr_notice("EDID block %d is all zeroes\n", block_num); 1888 break; 1889 case EDID_BLOCK_HEADER_CORRUPT: 1890 pr_notice("EDID has corrupt header\n"); 1891 break; 1892 case EDID_BLOCK_HEADER_REPAIR: 1893 pr_debug("EDID corrupt header needs repair\n"); 1894 break; 1895 case EDID_BLOCK_HEADER_FIXED: 1896 pr_debug("EDID corrupt header fixed\n"); 1897 break; 1898 case EDID_BLOCK_CHECKSUM: 1899 if (edid_block_status_valid(status, edid_block_tag(block))) { 1900 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1901 block_num, edid_block_tag(block), 1902 edid_block_compute_checksum(block)); 1903 } else { 1904 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1905 block_num, edid_block_tag(block), 1906 edid_block_compute_checksum(block)); 1907 } 1908 break; 1909 case EDID_BLOCK_VERSION: 1910 pr_notice("EDID has major version %d, instead of 1\n", 1911 block->version); 1912 break; 1913 default: 1914 WARN(1, "EDID block %d unknown edid block status code %d\n", 1915 block_num, status); 1916 break; 1917 } 1918 } 1919 1920 static void edid_block_dump(const char *level, const void *block, int block_num) 1921 { 1922 enum edid_block_status status; 1923 char prefix[20]; 1924 1925 status = edid_block_check(block, block_num == 0); 1926 if (status == EDID_BLOCK_ZERO) 1927 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1928 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1929 sprintf(prefix, "\t[%02x] BAD ", block_num); 1930 else 1931 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1932 1933 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1934 block, EDID_LENGTH, false); 1935 } 1936 1937 /** 1938 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1939 * @_block: pointer to raw EDID block 1940 * @block_num: type of block to validate (0 for base, extension otherwise) 1941 * @print_bad_edid: if true, dump bad EDID blocks to the console 1942 * @edid_corrupt: if true, the header or checksum is invalid 1943 * 1944 * Validate a base or extension EDID block and optionally dump bad blocks to 1945 * the console. 1946 * 1947 * Return: True if the block is valid, false otherwise. 1948 */ 1949 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1950 bool *edid_corrupt) 1951 { 1952 struct edid *block = (struct edid *)_block; 1953 enum edid_block_status status; 1954 bool is_base_block = block_num == 0; 1955 bool valid; 1956 1957 if (WARN_ON(!block)) 1958 return false; 1959 1960 status = edid_block_check(block, is_base_block); 1961 if (status == EDID_BLOCK_HEADER_REPAIR) { 1962 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1963 edid_header_fix(block); 1964 1965 /* Retry with fixed header, update status if that worked. */ 1966 status = edid_block_check(block, is_base_block); 1967 if (status == EDID_BLOCK_OK) 1968 status = EDID_BLOCK_HEADER_FIXED; 1969 } 1970 1971 if (edid_corrupt) { 1972 /* 1973 * Unknown major version isn't corrupt but we can't use it. Only 1974 * the base block can reset edid_corrupt to false. 1975 */ 1976 if (is_base_block && 1977 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 1978 *edid_corrupt = false; 1979 else if (status != EDID_BLOCK_OK) 1980 *edid_corrupt = true; 1981 } 1982 1983 edid_block_status_print(status, block, block_num); 1984 1985 /* Determine whether we can use this block with this status. */ 1986 valid = edid_block_status_valid(status, edid_block_tag(block)); 1987 1988 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 1989 pr_notice("Raw EDID:\n"); 1990 edid_block_dump(KERN_NOTICE, block, block_num); 1991 } 1992 1993 return valid; 1994 } 1995 EXPORT_SYMBOL(drm_edid_block_valid); 1996 1997 /** 1998 * drm_edid_is_valid - sanity check EDID data 1999 * @edid: EDID data 2000 * 2001 * Sanity-check an entire EDID record (including extensions) 2002 * 2003 * Return: True if the EDID data is valid, false otherwise. 2004 */ 2005 bool drm_edid_is_valid(struct edid *edid) 2006 { 2007 int i; 2008 2009 if (!edid) 2010 return false; 2011 2012 for (i = 0; i < edid_block_count(edid); i++) { 2013 void *block = (void *)edid_block_data(edid, i); 2014 2015 if (!drm_edid_block_valid(block, i, true, NULL)) 2016 return false; 2017 } 2018 2019 return true; 2020 } 2021 EXPORT_SYMBOL(drm_edid_is_valid); 2022 2023 static struct edid *edid_filter_invalid_blocks(const struct edid *edid, 2024 int invalid_blocks, 2025 size_t *alloc_size) 2026 { 2027 struct edid *new, *dest_block; 2028 int valid_extensions = edid->extensions - invalid_blocks; 2029 int i; 2030 2031 *alloc_size = edid_size_by_blocks(valid_extensions + 1); 2032 2033 new = kmalloc(*alloc_size, GFP_KERNEL); 2034 if (!new) 2035 goto out; 2036 2037 dest_block = new; 2038 for (i = 0; i < edid_block_count(edid); i++) { 2039 const void *block = edid_block_data(edid, i); 2040 2041 if (edid_block_valid(block, i == 0)) 2042 memcpy(dest_block++, block, EDID_LENGTH); 2043 } 2044 2045 new->extensions = valid_extensions; 2046 new->checksum = edid_block_compute_checksum(new); 2047 2048 out: 2049 kfree(edid); 2050 2051 return new; 2052 } 2053 2054 #define DDC_SEGMENT_ADDR 0x30 2055 /** 2056 * drm_do_probe_ddc_edid() - get EDID information via I2C 2057 * @data: I2C device adapter 2058 * @buf: EDID data buffer to be filled 2059 * @block: 128 byte EDID block to start fetching from 2060 * @len: EDID data buffer length to fetch 2061 * 2062 * Try to fetch EDID information by calling I2C driver functions. 2063 * 2064 * Return: 0 on success or -1 on failure. 2065 */ 2066 static int 2067 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2068 { 2069 struct i2c_adapter *adapter = data; 2070 unsigned char start = block * EDID_LENGTH; 2071 unsigned char segment = block >> 1; 2072 unsigned char xfers = segment ? 3 : 2; 2073 int ret, retries = 5; 2074 2075 /* 2076 * The core I2C driver will automatically retry the transfer if the 2077 * adapter reports EAGAIN. However, we find that bit-banging transfers 2078 * are susceptible to errors under a heavily loaded machine and 2079 * generate spurious NAKs and timeouts. Retrying the transfer 2080 * of the individual block a few times seems to overcome this. 2081 */ 2082 do { 2083 struct i2c_msg msgs[] = { 2084 { 2085 .addr = DDC_SEGMENT_ADDR, 2086 .flags = 0, 2087 .len = 1, 2088 .buf = &segment, 2089 }, { 2090 .addr = DDC_ADDR, 2091 .flags = 0, 2092 .len = 1, 2093 .buf = &start, 2094 }, { 2095 .addr = DDC_ADDR, 2096 .flags = I2C_M_RD, 2097 .len = len, 2098 .buf = buf, 2099 } 2100 }; 2101 2102 /* 2103 * Avoid sending the segment addr to not upset non-compliant 2104 * DDC monitors. 2105 */ 2106 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2107 2108 if (ret == -ENXIO) { 2109 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2110 adapter->name); 2111 break; 2112 } 2113 } while (ret != xfers && --retries); 2114 2115 return ret == xfers ? 0 : -1; 2116 } 2117 2118 static void connector_bad_edid(struct drm_connector *connector, 2119 const struct edid *edid, int num_blocks) 2120 { 2121 int i; 2122 u8 last_block; 2123 2124 /* 2125 * 0x7e in the EDID is the number of extension blocks. The EDID 2126 * is 1 (base block) + num_ext_blocks big. That means we can think 2127 * of 0x7e in the EDID of the _index_ of the last block in the 2128 * combined chunk of memory. 2129 */ 2130 last_block = edid->extensions; 2131 2132 /* Calculate real checksum for the last edid extension block data */ 2133 if (last_block < num_blocks) 2134 connector->real_edid_checksum = 2135 edid_block_compute_checksum(edid + last_block); 2136 2137 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2138 return; 2139 2140 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 2141 for (i = 0; i < num_blocks; i++) 2142 edid_block_dump(KERN_DEBUG, edid + i, i); 2143 } 2144 2145 /* Get override or firmware EDID */ 2146 static struct edid *drm_get_override_edid(struct drm_connector *connector, 2147 size_t *alloc_size) 2148 { 2149 struct edid *override = NULL; 2150 2151 if (connector->override_edid) 2152 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 2153 2154 if (!override) 2155 override = drm_load_edid_firmware(connector); 2156 2157 /* FIXME: Get alloc size from deeper down the stack */ 2158 if (!IS_ERR_OR_NULL(override) && alloc_size) 2159 *alloc_size = edid_size(override); 2160 2161 return IS_ERR(override) ? NULL : override; 2162 } 2163 2164 /** 2165 * drm_add_override_edid_modes - add modes from override/firmware EDID 2166 * @connector: connector we're probing 2167 * 2168 * Add modes from the override/firmware EDID, if available. Only to be used from 2169 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2170 * failed during drm_get_edid() and caused the override/firmware EDID to be 2171 * skipped. 2172 * 2173 * Return: The number of modes added or 0 if we couldn't find any. 2174 */ 2175 int drm_add_override_edid_modes(struct drm_connector *connector) 2176 { 2177 struct edid *override; 2178 int num_modes = 0; 2179 2180 override = drm_get_override_edid(connector, NULL); 2181 if (override) { 2182 drm_connector_update_edid_property(connector, override); 2183 num_modes = drm_add_edid_modes(connector, override); 2184 kfree(override); 2185 2186 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2187 connector->base.id, connector->name, num_modes); 2188 } 2189 2190 return num_modes; 2191 } 2192 EXPORT_SYMBOL(drm_add_override_edid_modes); 2193 2194 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2195 2196 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2197 read_block_fn read_block, 2198 void *context) 2199 { 2200 enum edid_block_status status; 2201 bool is_base_block = block_num == 0; 2202 int try; 2203 2204 for (try = 0; try < 4; try++) { 2205 if (read_block(context, block, block_num, EDID_LENGTH)) 2206 return EDID_BLOCK_READ_FAIL; 2207 2208 status = edid_block_check(block, is_base_block); 2209 if (status == EDID_BLOCK_HEADER_REPAIR) { 2210 edid_header_fix(block); 2211 2212 /* Retry with fixed header, update status if that worked. */ 2213 status = edid_block_check(block, is_base_block); 2214 if (status == EDID_BLOCK_OK) 2215 status = EDID_BLOCK_HEADER_FIXED; 2216 } 2217 2218 if (edid_block_status_valid(status, edid_block_tag(block))) 2219 break; 2220 2221 /* Fail early for unrepairable base block all zeros. */ 2222 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2223 break; 2224 } 2225 2226 return status; 2227 } 2228 2229 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2230 read_block_fn read_block, void *context, 2231 size_t *size) 2232 { 2233 enum edid_block_status status; 2234 int i, invalid_blocks = 0; 2235 struct edid *edid, *new; 2236 size_t alloc_size = EDID_LENGTH; 2237 2238 edid = drm_get_override_edid(connector, &alloc_size); 2239 if (edid) 2240 goto ok; 2241 2242 edid = kmalloc(alloc_size, GFP_KERNEL); 2243 if (!edid) 2244 return NULL; 2245 2246 status = edid_block_read(edid, 0, read_block, context); 2247 2248 edid_block_status_print(status, edid, 0); 2249 2250 if (status == EDID_BLOCK_READ_FAIL) 2251 goto fail; 2252 2253 /* FIXME: Clarify what a corrupt EDID actually means. */ 2254 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2255 connector->edid_corrupt = false; 2256 else 2257 connector->edid_corrupt = true; 2258 2259 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2260 if (status == EDID_BLOCK_ZERO) 2261 connector->null_edid_counter++; 2262 2263 connector_bad_edid(connector, edid, 1); 2264 goto fail; 2265 } 2266 2267 if (!edid_extension_block_count(edid)) 2268 goto ok; 2269 2270 alloc_size = edid_size(edid); 2271 new = krealloc(edid, alloc_size, GFP_KERNEL); 2272 if (!new) 2273 goto fail; 2274 edid = new; 2275 2276 for (i = 1; i < edid_block_count(edid); i++) { 2277 void *block = (void *)edid_block_data(edid, i); 2278 2279 status = edid_block_read(block, i, read_block, context); 2280 2281 edid_block_status_print(status, block, i); 2282 2283 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2284 if (status == EDID_BLOCK_READ_FAIL) 2285 goto fail; 2286 invalid_blocks++; 2287 } 2288 } 2289 2290 if (invalid_blocks) { 2291 connector_bad_edid(connector, edid, edid_block_count(edid)); 2292 2293 edid = edid_filter_invalid_blocks(edid, invalid_blocks, 2294 &alloc_size); 2295 } 2296 2297 ok: 2298 if (size) 2299 *size = alloc_size; 2300 2301 return edid; 2302 2303 fail: 2304 kfree(edid); 2305 return NULL; 2306 } 2307 2308 /** 2309 * drm_do_get_edid - get EDID data using a custom EDID block read function 2310 * @connector: connector we're probing 2311 * @read_block: EDID block read function 2312 * @context: private data passed to the block read function 2313 * 2314 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2315 * exposes a different interface to read EDID blocks this function can be used 2316 * to get EDID data using a custom block read function. 2317 * 2318 * As in the general case the DDC bus is accessible by the kernel at the I2C 2319 * level, drivers must make all reasonable efforts to expose it as an I2C 2320 * adapter and use drm_get_edid() instead of abusing this function. 2321 * 2322 * The EDID may be overridden using debugfs override_edid or firmware EDID 2323 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2324 * order. Having either of them bypasses actual EDID reads. 2325 * 2326 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2327 */ 2328 struct edid *drm_do_get_edid(struct drm_connector *connector, 2329 read_block_fn read_block, 2330 void *context) 2331 { 2332 return _drm_do_get_edid(connector, read_block, context, NULL); 2333 } 2334 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2335 2336 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2337 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2338 { 2339 struct drm_edid *drm_edid; 2340 2341 if (!edid || !size || size < EDID_LENGTH) 2342 return NULL; 2343 2344 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2345 if (drm_edid) { 2346 drm_edid->edid = edid; 2347 drm_edid->size = size; 2348 } 2349 2350 return drm_edid; 2351 } 2352 2353 /** 2354 * drm_edid_alloc - Allocate a new drm_edid container 2355 * @edid: Pointer to raw EDID data 2356 * @size: Size of memory allocated for EDID 2357 * 2358 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2359 * the actual size that has been allocated for the data. There is no validation 2360 * of the raw EDID data against the size, but at least the EDID base block must 2361 * fit in the buffer. 2362 * 2363 * The returned pointer must be freed using drm_edid_free(). 2364 * 2365 * Return: drm_edid container, or NULL on errors 2366 */ 2367 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2368 { 2369 const struct drm_edid *drm_edid; 2370 2371 if (!edid || !size || size < EDID_LENGTH) 2372 return NULL; 2373 2374 edid = kmemdup(edid, size, GFP_KERNEL); 2375 if (!edid) 2376 return NULL; 2377 2378 drm_edid = _drm_edid_alloc(edid, size); 2379 if (!drm_edid) 2380 kfree(edid); 2381 2382 return drm_edid; 2383 } 2384 EXPORT_SYMBOL(drm_edid_alloc); 2385 2386 /** 2387 * drm_edid_dup - Duplicate a drm_edid container 2388 * @drm_edid: EDID to duplicate 2389 * 2390 * The returned pointer must be freed using drm_edid_free(). 2391 * 2392 * Returns: drm_edid container copy, or NULL on errors 2393 */ 2394 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2395 { 2396 if (!drm_edid) 2397 return NULL; 2398 2399 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2400 } 2401 EXPORT_SYMBOL(drm_edid_dup); 2402 2403 /** 2404 * drm_edid_free - Free the drm_edid container 2405 * @drm_edid: EDID to free 2406 */ 2407 void drm_edid_free(const struct drm_edid *drm_edid) 2408 { 2409 if (!drm_edid) 2410 return; 2411 2412 kfree(drm_edid->edid); 2413 kfree(drm_edid); 2414 } 2415 EXPORT_SYMBOL(drm_edid_free); 2416 2417 /** 2418 * drm_probe_ddc() - probe DDC presence 2419 * @adapter: I2C adapter to probe 2420 * 2421 * Return: True on success, false on failure. 2422 */ 2423 bool 2424 drm_probe_ddc(struct i2c_adapter *adapter) 2425 { 2426 unsigned char out; 2427 2428 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2429 } 2430 EXPORT_SYMBOL(drm_probe_ddc); 2431 2432 /** 2433 * drm_get_edid - get EDID data, if available 2434 * @connector: connector we're probing 2435 * @adapter: I2C adapter to use for DDC 2436 * 2437 * Poke the given I2C channel to grab EDID data if possible. If found, 2438 * attach it to the connector. 2439 * 2440 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2441 */ 2442 struct edid *drm_get_edid(struct drm_connector *connector, 2443 struct i2c_adapter *adapter) 2444 { 2445 struct edid *edid; 2446 2447 if (connector->force == DRM_FORCE_OFF) 2448 return NULL; 2449 2450 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2451 return NULL; 2452 2453 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2454 drm_connector_update_edid_property(connector, edid); 2455 return edid; 2456 } 2457 EXPORT_SYMBOL(drm_get_edid); 2458 2459 /** 2460 * drm_edid_read_custom - Read EDID data using given EDID block read function 2461 * @connector: Connector to use 2462 * @read_block: EDID block read function 2463 * @context: Private data passed to the block read function 2464 * 2465 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2466 * exposes a different interface to read EDID blocks this function can be used 2467 * to get EDID data using a custom block read function. 2468 * 2469 * As in the general case the DDC bus is accessible by the kernel at the I2C 2470 * level, drivers must make all reasonable efforts to expose it as an I2C 2471 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2472 * this function. 2473 * 2474 * The EDID may be overridden using debugfs override_edid or firmware EDID 2475 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2476 * order. Having either of them bypasses actual EDID reads. 2477 * 2478 * The returned pointer must be freed using drm_edid_free(). 2479 * 2480 * Return: Pointer to EDID, or NULL if probe/read failed. 2481 */ 2482 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2483 read_block_fn read_block, 2484 void *context) 2485 { 2486 const struct drm_edid *drm_edid; 2487 struct edid *edid; 2488 size_t size = 0; 2489 2490 edid = _drm_do_get_edid(connector, read_block, context, &size); 2491 if (!edid) 2492 return NULL; 2493 2494 /* Sanity check for now */ 2495 drm_WARN_ON(connector->dev, !size); 2496 2497 drm_edid = _drm_edid_alloc(edid, size); 2498 if (!drm_edid) 2499 kfree(edid); 2500 2501 return drm_edid; 2502 } 2503 EXPORT_SYMBOL(drm_edid_read_custom); 2504 2505 /** 2506 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2507 * @connector: Connector to use 2508 * @adapter: I2C adapter to use for DDC 2509 * 2510 * Read EDID using the given I2C adapter. 2511 * 2512 * The EDID may be overridden using debugfs override_edid or firmware EDID 2513 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2514 * order. Having either of them bypasses actual EDID reads. 2515 * 2516 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2517 * using drm_edid_read() instead of this function. 2518 * 2519 * The returned pointer must be freed using drm_edid_free(). 2520 * 2521 * Return: Pointer to EDID, or NULL if probe/read failed. 2522 */ 2523 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2524 struct i2c_adapter *adapter) 2525 { 2526 const struct drm_edid *drm_edid; 2527 2528 if (connector->force == DRM_FORCE_OFF) 2529 return NULL; 2530 2531 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2532 return NULL; 2533 2534 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2535 2536 /* Note: Do *not* call connector updates here. */ 2537 2538 return drm_edid; 2539 } 2540 EXPORT_SYMBOL(drm_edid_read_ddc); 2541 2542 /** 2543 * drm_edid_read - Read EDID data using connector's I2C adapter 2544 * @connector: Connector to use 2545 * 2546 * Read EDID using the connector's I2C adapter. 2547 * 2548 * The EDID may be overridden using debugfs override_edid or firmware EDID 2549 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2550 * order. Having either of them bypasses actual EDID reads. 2551 * 2552 * The returned pointer must be freed using drm_edid_free(). 2553 * 2554 * Return: Pointer to EDID, or NULL if probe/read failed. 2555 */ 2556 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2557 { 2558 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2559 return NULL; 2560 2561 return drm_edid_read_ddc(connector, connector->ddc); 2562 } 2563 EXPORT_SYMBOL(drm_edid_read); 2564 2565 static u32 edid_extract_panel_id(const struct edid *edid) 2566 { 2567 /* 2568 * We represent the ID as a 32-bit number so it can easily be compared 2569 * with "==". 2570 * 2571 * NOTE that we deal with endianness differently for the top half 2572 * of this ID than for the bottom half. The bottom half (the product 2573 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2574 * that's how everyone seems to interpret it. The top half (the mfg_id) 2575 * gets stored as big endian because that makes 2576 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2577 * to write (it's easier to extract the ASCII). It doesn't really 2578 * matter, though, as long as the number here is unique. 2579 */ 2580 return (u32)edid->mfg_id[0] << 24 | 2581 (u32)edid->mfg_id[1] << 16 | 2582 (u32)EDID_PRODUCT_ID(edid); 2583 } 2584 2585 /** 2586 * drm_edid_get_panel_id - Get a panel's ID through DDC 2587 * @adapter: I2C adapter to use for DDC 2588 * 2589 * This function reads the first block of the EDID of a panel and (assuming 2590 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2591 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2592 * supposed to be different for each different modem of panel. 2593 * 2594 * This function is intended to be used during early probing on devices where 2595 * more than one panel might be present. Because of its intended use it must 2596 * assume that the EDID of the panel is correct, at least as far as the ID 2597 * is concerned (in other words, we don't process any overrides here). 2598 * 2599 * NOTE: it's expected that this function and drm_do_get_edid() will both 2600 * be read the EDID, but there is no caching between them. Since we're only 2601 * reading the first block, hopefully this extra overhead won't be too big. 2602 * 2603 * Return: A 32-bit ID that should be different for each make/model of panel. 2604 * See the functions drm_edid_encode_panel_id() and 2605 * drm_edid_decode_panel_id() for some details on the structure of this 2606 * ID. 2607 */ 2608 2609 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2610 { 2611 enum edid_block_status status; 2612 void *base_block; 2613 u32 panel_id = 0; 2614 2615 /* 2616 * There are no manufacturer IDs of 0, so if there is a problem reading 2617 * the EDID then we'll just return 0. 2618 */ 2619 2620 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); 2621 if (!base_block) 2622 return 0; 2623 2624 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2625 2626 edid_block_status_print(status, base_block, 0); 2627 2628 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2629 panel_id = edid_extract_panel_id(base_block); 2630 2631 kfree(base_block); 2632 2633 return panel_id; 2634 } 2635 EXPORT_SYMBOL(drm_edid_get_panel_id); 2636 2637 /** 2638 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2639 * @connector: connector we're probing 2640 * @adapter: I2C adapter to use for DDC 2641 * 2642 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2643 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2644 * switch DDC to the GPU which is retrieving EDID. 2645 * 2646 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2647 */ 2648 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2649 struct i2c_adapter *adapter) 2650 { 2651 struct drm_device *dev = connector->dev; 2652 struct pci_dev *pdev = to_pci_dev(dev->dev); 2653 struct edid *edid; 2654 2655 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2656 return NULL; 2657 2658 vga_switcheroo_lock_ddc(pdev); 2659 edid = drm_get_edid(connector, adapter); 2660 vga_switcheroo_unlock_ddc(pdev); 2661 2662 return edid; 2663 } 2664 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2665 2666 /** 2667 * drm_edid_duplicate - duplicate an EDID and the extensions 2668 * @edid: EDID to duplicate 2669 * 2670 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2671 */ 2672 struct edid *drm_edid_duplicate(const struct edid *edid) 2673 { 2674 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2675 } 2676 EXPORT_SYMBOL(drm_edid_duplicate); 2677 2678 /*** EDID parsing ***/ 2679 2680 /** 2681 * edid_get_quirks - return quirk flags for a given EDID 2682 * @drm_edid: EDID to process 2683 * 2684 * This tells subsequent routines what fixes they need to apply. 2685 */ 2686 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2687 { 2688 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2689 const struct edid_quirk *quirk; 2690 int i; 2691 2692 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2693 quirk = &edid_quirk_list[i]; 2694 if (quirk->panel_id == panel_id) 2695 return quirk->quirks; 2696 } 2697 2698 return 0; 2699 } 2700 2701 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2702 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2703 2704 /* 2705 * Walk the mode list for connector, clearing the preferred status on existing 2706 * modes and setting it anew for the right mode ala quirks. 2707 */ 2708 static void edid_fixup_preferred(struct drm_connector *connector, 2709 u32 quirks) 2710 { 2711 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2712 int target_refresh = 0; 2713 int cur_vrefresh, preferred_vrefresh; 2714 2715 if (list_empty(&connector->probed_modes)) 2716 return; 2717 2718 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2719 target_refresh = 60; 2720 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2721 target_refresh = 75; 2722 2723 preferred_mode = list_first_entry(&connector->probed_modes, 2724 struct drm_display_mode, head); 2725 2726 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2727 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2728 2729 if (cur_mode == preferred_mode) 2730 continue; 2731 2732 /* Largest mode is preferred */ 2733 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2734 preferred_mode = cur_mode; 2735 2736 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2737 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2738 /* At a given size, try to get closest to target refresh */ 2739 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2740 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2741 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2742 preferred_mode = cur_mode; 2743 } 2744 } 2745 2746 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2747 } 2748 2749 static bool 2750 mode_is_rb(const struct drm_display_mode *mode) 2751 { 2752 return (mode->htotal - mode->hdisplay == 160) && 2753 (mode->hsync_end - mode->hdisplay == 80) && 2754 (mode->hsync_end - mode->hsync_start == 32) && 2755 (mode->vsync_start - mode->vdisplay == 3); 2756 } 2757 2758 /* 2759 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2760 * @dev: Device to duplicate against 2761 * @hsize: Mode width 2762 * @vsize: Mode height 2763 * @fresh: Mode refresh rate 2764 * @rb: Mode reduced-blanking-ness 2765 * 2766 * Walk the DMT mode list looking for a match for the given parameters. 2767 * 2768 * Return: A newly allocated copy of the mode, or NULL if not found. 2769 */ 2770 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2771 int hsize, int vsize, int fresh, 2772 bool rb) 2773 { 2774 int i; 2775 2776 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2777 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2778 2779 if (hsize != ptr->hdisplay) 2780 continue; 2781 if (vsize != ptr->vdisplay) 2782 continue; 2783 if (fresh != drm_mode_vrefresh(ptr)) 2784 continue; 2785 if (rb != mode_is_rb(ptr)) 2786 continue; 2787 2788 return drm_mode_duplicate(dev, ptr); 2789 } 2790 2791 return NULL; 2792 } 2793 EXPORT_SYMBOL(drm_mode_find_dmt); 2794 2795 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2796 { 2797 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2798 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2799 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2800 2801 return descriptor->pixel_clock == 0 && 2802 descriptor->data.other_data.pad1 == 0 && 2803 descriptor->data.other_data.type == type; 2804 } 2805 2806 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2807 { 2808 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2809 2810 return descriptor->pixel_clock != 0; 2811 } 2812 2813 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2814 2815 static void 2816 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2817 { 2818 int i, n; 2819 u8 d = ext[0x02]; 2820 const u8 *det_base = ext + d; 2821 2822 if (d < 4 || d > 127) 2823 return; 2824 2825 n = (127 - d) / 18; 2826 for (i = 0; i < n; i++) 2827 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2828 } 2829 2830 static void 2831 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2832 { 2833 unsigned int i, n = min((int)ext[0x02], 6); 2834 const u8 *det_base = ext + 5; 2835 2836 if (ext[0x01] != 1) 2837 return; /* unknown version */ 2838 2839 for (i = 0; i < n; i++) 2840 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2841 } 2842 2843 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 2844 detailed_cb *cb, void *closure) 2845 { 2846 struct drm_edid_iter edid_iter; 2847 const u8 *ext; 2848 int i; 2849 2850 if (!drm_edid) 2851 return; 2852 2853 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2854 cb(&drm_edid->edid->detailed_timings[i], closure); 2855 2856 drm_edid_iter_begin(drm_edid, &edid_iter); 2857 drm_edid_iter_for_each(ext, &edid_iter) { 2858 switch (*ext) { 2859 case CEA_EXT: 2860 cea_for_each_detailed_block(ext, cb, closure); 2861 break; 2862 case VTB_EXT: 2863 vtb_for_each_detailed_block(ext, cb, closure); 2864 break; 2865 default: 2866 break; 2867 } 2868 } 2869 drm_edid_iter_end(&edid_iter); 2870 } 2871 2872 static void 2873 is_rb(const struct detailed_timing *descriptor, void *data) 2874 { 2875 bool *res = data; 2876 2877 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2878 return; 2879 2880 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2881 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 2882 2883 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 2884 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) 2885 *res = true; 2886 } 2887 2888 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2889 static bool 2890 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 2891 { 2892 if (drm_edid->edid->revision >= 4) { 2893 bool ret = false; 2894 2895 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 2896 return ret; 2897 } 2898 2899 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2900 } 2901 2902 static void 2903 find_gtf2(const struct detailed_timing *descriptor, void *data) 2904 { 2905 const struct detailed_timing **res = data; 2906 2907 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2908 return; 2909 2910 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2911 2912 if (descriptor->data.other_data.data.range.flags == 0x02) 2913 *res = descriptor; 2914 } 2915 2916 /* Secondary GTF curve kicks in above some break frequency */ 2917 static int 2918 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 2919 { 2920 const struct detailed_timing *descriptor = NULL; 2921 2922 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2923 2924 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 2925 2926 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 2927 } 2928 2929 static int 2930 drm_gtf2_2c(const struct drm_edid *drm_edid) 2931 { 2932 const struct detailed_timing *descriptor = NULL; 2933 2934 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2935 2936 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 2937 2938 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 2939 } 2940 2941 static int 2942 drm_gtf2_m(const struct drm_edid *drm_edid) 2943 { 2944 const struct detailed_timing *descriptor = NULL; 2945 2946 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2947 2948 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 2949 2950 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 2951 } 2952 2953 static int 2954 drm_gtf2_k(const struct drm_edid *drm_edid) 2955 { 2956 const struct detailed_timing *descriptor = NULL; 2957 2958 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2959 2960 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 2961 2962 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 2963 } 2964 2965 static int 2966 drm_gtf2_2j(const struct drm_edid *drm_edid) 2967 { 2968 const struct detailed_timing *descriptor = NULL; 2969 2970 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2971 2972 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 2973 2974 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 2975 } 2976 2977 /* Get standard timing level (CVT/GTF/DMT). */ 2978 static int standard_timing_level(const struct drm_edid *drm_edid) 2979 { 2980 const struct edid *edid = drm_edid->edid; 2981 2982 if (edid->revision >= 2) { 2983 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2984 return LEVEL_CVT; 2985 if (drm_gtf2_hbreak(drm_edid)) 2986 return LEVEL_GTF2; 2987 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2988 return LEVEL_GTF; 2989 } 2990 return LEVEL_DMT; 2991 } 2992 2993 /* 2994 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2995 * monitors fill with ascii space (0x20) instead. 2996 */ 2997 static int 2998 bad_std_timing(u8 a, u8 b) 2999 { 3000 return (a == 0x00 && b == 0x00) || 3001 (a == 0x01 && b == 0x01) || 3002 (a == 0x20 && b == 0x20); 3003 } 3004 3005 static int drm_mode_hsync(const struct drm_display_mode *mode) 3006 { 3007 if (mode->htotal <= 0) 3008 return 0; 3009 3010 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3011 } 3012 3013 /* 3014 * Take the standard timing params (in this case width, aspect, and refresh) 3015 * and convert them into a real mode using CVT/GTF/DMT. 3016 */ 3017 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3018 const struct drm_edid *drm_edid, 3019 const struct std_timing *t) 3020 { 3021 struct drm_device *dev = connector->dev; 3022 struct drm_display_mode *m, *mode = NULL; 3023 int hsize, vsize; 3024 int vrefresh_rate; 3025 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3026 >> EDID_TIMING_ASPECT_SHIFT; 3027 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3028 >> EDID_TIMING_VFREQ_SHIFT; 3029 int timing_level = standard_timing_level(drm_edid); 3030 3031 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3032 return NULL; 3033 3034 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3035 hsize = t->hsize * 8 + 248; 3036 /* vrefresh_rate = vfreq + 60 */ 3037 vrefresh_rate = vfreq + 60; 3038 /* the vdisplay is calculated based on the aspect ratio */ 3039 if (aspect_ratio == 0) { 3040 if (drm_edid->edid->revision < 3) 3041 vsize = hsize; 3042 else 3043 vsize = (hsize * 10) / 16; 3044 } else if (aspect_ratio == 1) 3045 vsize = (hsize * 3) / 4; 3046 else if (aspect_ratio == 2) 3047 vsize = (hsize * 4) / 5; 3048 else 3049 vsize = (hsize * 9) / 16; 3050 3051 /* HDTV hack, part 1 */ 3052 if (vrefresh_rate == 60 && 3053 ((hsize == 1360 && vsize == 765) || 3054 (hsize == 1368 && vsize == 769))) { 3055 hsize = 1366; 3056 vsize = 768; 3057 } 3058 3059 /* 3060 * If this connector already has a mode for this size and refresh 3061 * rate (because it came from detailed or CVT info), use that 3062 * instead. This way we don't have to guess at interlace or 3063 * reduced blanking. 3064 */ 3065 list_for_each_entry(m, &connector->probed_modes, head) 3066 if (m->hdisplay == hsize && m->vdisplay == vsize && 3067 drm_mode_vrefresh(m) == vrefresh_rate) 3068 return NULL; 3069 3070 /* HDTV hack, part 2 */ 3071 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3072 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3073 false); 3074 if (!mode) 3075 return NULL; 3076 mode->hdisplay = 1366; 3077 mode->hsync_start = mode->hsync_start - 1; 3078 mode->hsync_end = mode->hsync_end - 1; 3079 return mode; 3080 } 3081 3082 /* check whether it can be found in default mode table */ 3083 if (drm_monitor_supports_rb(drm_edid)) { 3084 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3085 true); 3086 if (mode) 3087 return mode; 3088 } 3089 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3090 if (mode) 3091 return mode; 3092 3093 /* okay, generate it */ 3094 switch (timing_level) { 3095 case LEVEL_DMT: 3096 break; 3097 case LEVEL_GTF: 3098 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3099 break; 3100 case LEVEL_GTF2: 3101 /* 3102 * This is potentially wrong if there's ever a monitor with 3103 * more than one ranges section, each claiming a different 3104 * secondary GTF curve. Please don't do that. 3105 */ 3106 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3107 if (!mode) 3108 return NULL; 3109 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3110 drm_mode_destroy(dev, mode); 3111 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3112 vrefresh_rate, 0, 0, 3113 drm_gtf2_m(drm_edid), 3114 drm_gtf2_2c(drm_edid), 3115 drm_gtf2_k(drm_edid), 3116 drm_gtf2_2j(drm_edid)); 3117 } 3118 break; 3119 case LEVEL_CVT: 3120 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3121 false); 3122 break; 3123 } 3124 return mode; 3125 } 3126 3127 /* 3128 * EDID is delightfully ambiguous about how interlaced modes are to be 3129 * encoded. Our internal representation is of frame height, but some 3130 * HDTV detailed timings are encoded as field height. 3131 * 3132 * The format list here is from CEA, in frame size. Technically we 3133 * should be checking refresh rate too. Whatever. 3134 */ 3135 static void 3136 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3137 const struct detailed_pixel_timing *pt) 3138 { 3139 int i; 3140 static const struct { 3141 int w, h; 3142 } cea_interlaced[] = { 3143 { 1920, 1080 }, 3144 { 720, 480 }, 3145 { 1440, 480 }, 3146 { 2880, 480 }, 3147 { 720, 576 }, 3148 { 1440, 576 }, 3149 { 2880, 576 }, 3150 }; 3151 3152 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3153 return; 3154 3155 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3156 if ((mode->hdisplay == cea_interlaced[i].w) && 3157 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3158 mode->vdisplay *= 2; 3159 mode->vsync_start *= 2; 3160 mode->vsync_end *= 2; 3161 mode->vtotal *= 2; 3162 mode->vtotal |= 1; 3163 } 3164 } 3165 3166 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3167 } 3168 3169 /* 3170 * Create a new mode from an EDID detailed timing section. An EDID detailed 3171 * timing block contains enough info for us to create and return a new struct 3172 * drm_display_mode. 3173 */ 3174 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 3175 const struct drm_edid *drm_edid, 3176 const struct detailed_timing *timing, 3177 u32 quirks) 3178 { 3179 struct drm_display_mode *mode; 3180 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3181 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3182 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3183 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3184 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3185 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3186 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3187 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3188 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3189 3190 /* ignore tiny modes */ 3191 if (hactive < 64 || vactive < 64) 3192 return NULL; 3193 3194 if (pt->misc & DRM_EDID_PT_STEREO) { 3195 DRM_DEBUG_KMS("stereo mode not supported\n"); 3196 return NULL; 3197 } 3198 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3199 DRM_DEBUG_KMS("composite sync not supported\n"); 3200 } 3201 3202 /* it is incorrect if hsync/vsync width is zero */ 3203 if (!hsync_pulse_width || !vsync_pulse_width) { 3204 DRM_DEBUG_KMS("Incorrect Detailed timing. " 3205 "Wrong Hsync/Vsync pulse width\n"); 3206 return NULL; 3207 } 3208 3209 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3210 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3211 if (!mode) 3212 return NULL; 3213 3214 goto set_size; 3215 } 3216 3217 mode = drm_mode_create(dev); 3218 if (!mode) 3219 return NULL; 3220 3221 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3222 mode->clock = 1088 * 10; 3223 else 3224 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3225 3226 mode->hdisplay = hactive; 3227 mode->hsync_start = mode->hdisplay + hsync_offset; 3228 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3229 mode->htotal = mode->hdisplay + hblank; 3230 3231 mode->vdisplay = vactive; 3232 mode->vsync_start = mode->vdisplay + vsync_offset; 3233 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3234 mode->vtotal = mode->vdisplay + vblank; 3235 3236 /* Some EDIDs have bogus h/vtotal values */ 3237 if (mode->hsync_end > mode->htotal) 3238 mode->htotal = mode->hsync_end + 1; 3239 if (mode->vsync_end > mode->vtotal) 3240 mode->vtotal = mode->vsync_end + 1; 3241 3242 drm_mode_do_interlace_quirk(mode, pt); 3243 3244 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3245 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3246 } else { 3247 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3248 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3249 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3250 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3251 } 3252 3253 set_size: 3254 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3255 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3256 3257 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 3258 mode->width_mm *= 10; 3259 mode->height_mm *= 10; 3260 } 3261 3262 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3263 mode->width_mm = drm_edid->edid->width_cm * 10; 3264 mode->height_mm = drm_edid->edid->height_cm * 10; 3265 } 3266 3267 mode->type = DRM_MODE_TYPE_DRIVER; 3268 drm_mode_set_name(mode); 3269 3270 return mode; 3271 } 3272 3273 static bool 3274 mode_in_hsync_range(const struct drm_display_mode *mode, 3275 const struct edid *edid, const u8 *t) 3276 { 3277 int hsync, hmin, hmax; 3278 3279 hmin = t[7]; 3280 if (edid->revision >= 4) 3281 hmin += ((t[4] & 0x04) ? 255 : 0); 3282 hmax = t[8]; 3283 if (edid->revision >= 4) 3284 hmax += ((t[4] & 0x08) ? 255 : 0); 3285 hsync = drm_mode_hsync(mode); 3286 3287 return (hsync <= hmax && hsync >= hmin); 3288 } 3289 3290 static bool 3291 mode_in_vsync_range(const struct drm_display_mode *mode, 3292 const struct edid *edid, const u8 *t) 3293 { 3294 int vsync, vmin, vmax; 3295 3296 vmin = t[5]; 3297 if (edid->revision >= 4) 3298 vmin += ((t[4] & 0x01) ? 255 : 0); 3299 vmax = t[6]; 3300 if (edid->revision >= 4) 3301 vmax += ((t[4] & 0x02) ? 255 : 0); 3302 vsync = drm_mode_vrefresh(mode); 3303 3304 return (vsync <= vmax && vsync >= vmin); 3305 } 3306 3307 static u32 3308 range_pixel_clock(const struct edid *edid, const u8 *t) 3309 { 3310 /* unspecified */ 3311 if (t[9] == 0 || t[9] == 255) 3312 return 0; 3313 3314 /* 1.4 with CVT support gives us real precision, yay */ 3315 if (edid->revision >= 4 && t[10] == 0x04) 3316 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3317 3318 /* 1.3 is pathetic, so fuzz up a bit */ 3319 return t[9] * 10000 + 5001; 3320 } 3321 3322 static bool mode_in_range(const struct drm_display_mode *mode, 3323 const struct drm_edid *drm_edid, 3324 const struct detailed_timing *timing) 3325 { 3326 const struct edid *edid = drm_edid->edid; 3327 u32 max_clock; 3328 const u8 *t = (const u8 *)timing; 3329 3330 if (!mode_in_hsync_range(mode, edid, t)) 3331 return false; 3332 3333 if (!mode_in_vsync_range(mode, edid, t)) 3334 return false; 3335 3336 if ((max_clock = range_pixel_clock(edid, t))) 3337 if (mode->clock > max_clock) 3338 return false; 3339 3340 /* 1.4 max horizontal check */ 3341 if (edid->revision >= 4 && t[10] == 0x04) 3342 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3343 return false; 3344 3345 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3346 return false; 3347 3348 return true; 3349 } 3350 3351 static bool valid_inferred_mode(const struct drm_connector *connector, 3352 const struct drm_display_mode *mode) 3353 { 3354 const struct drm_display_mode *m; 3355 bool ok = false; 3356 3357 list_for_each_entry(m, &connector->probed_modes, head) { 3358 if (mode->hdisplay == m->hdisplay && 3359 mode->vdisplay == m->vdisplay && 3360 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3361 return false; /* duplicated */ 3362 if (mode->hdisplay <= m->hdisplay && 3363 mode->vdisplay <= m->vdisplay) 3364 ok = true; 3365 } 3366 return ok; 3367 } 3368 3369 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3370 const struct drm_edid *drm_edid, 3371 const struct detailed_timing *timing) 3372 { 3373 int i, modes = 0; 3374 struct drm_display_mode *newmode; 3375 struct drm_device *dev = connector->dev; 3376 3377 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3378 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3379 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3380 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3381 if (newmode) { 3382 drm_mode_probed_add(connector, newmode); 3383 modes++; 3384 } 3385 } 3386 } 3387 3388 return modes; 3389 } 3390 3391 /* fix up 1366x768 mode from 1368x768; 3392 * GFT/CVT can't express 1366 width which isn't dividable by 8 3393 */ 3394 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3395 { 3396 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3397 mode->hdisplay = 1366; 3398 mode->hsync_start--; 3399 mode->hsync_end--; 3400 drm_mode_set_name(mode); 3401 } 3402 } 3403 3404 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3405 const struct drm_edid *drm_edid, 3406 const struct detailed_timing *timing) 3407 { 3408 int i, modes = 0; 3409 struct drm_display_mode *newmode; 3410 struct drm_device *dev = connector->dev; 3411 3412 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3413 const struct minimode *m = &extra_modes[i]; 3414 3415 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3416 if (!newmode) 3417 return modes; 3418 3419 drm_mode_fixup_1366x768(newmode); 3420 if (!mode_in_range(newmode, drm_edid, timing) || 3421 !valid_inferred_mode(connector, newmode)) { 3422 drm_mode_destroy(dev, newmode); 3423 continue; 3424 } 3425 3426 drm_mode_probed_add(connector, newmode); 3427 modes++; 3428 } 3429 3430 return modes; 3431 } 3432 3433 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3434 const struct drm_edid *drm_edid, 3435 const struct detailed_timing *timing) 3436 { 3437 int i, modes = 0; 3438 struct drm_display_mode *newmode; 3439 struct drm_device *dev = connector->dev; 3440 bool rb = drm_monitor_supports_rb(drm_edid); 3441 3442 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3443 const struct minimode *m = &extra_modes[i]; 3444 3445 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3446 if (!newmode) 3447 return modes; 3448 3449 drm_mode_fixup_1366x768(newmode); 3450 if (!mode_in_range(newmode, drm_edid, timing) || 3451 !valid_inferred_mode(connector, newmode)) { 3452 drm_mode_destroy(dev, newmode); 3453 continue; 3454 } 3455 3456 drm_mode_probed_add(connector, newmode); 3457 modes++; 3458 } 3459 3460 return modes; 3461 } 3462 3463 static void 3464 do_inferred_modes(const struct detailed_timing *timing, void *c) 3465 { 3466 struct detailed_mode_closure *closure = c; 3467 const struct detailed_non_pixel *data = &timing->data.other_data; 3468 const struct detailed_data_monitor_range *range = &data->data.range; 3469 3470 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3471 return; 3472 3473 closure->modes += drm_dmt_modes_for_range(closure->connector, 3474 closure->drm_edid, 3475 timing); 3476 3477 if (!version_greater(closure->drm_edid, 1, 1)) 3478 return; /* GTF not defined yet */ 3479 3480 switch (range->flags) { 3481 case 0x02: /* secondary gtf, XXX could do more */ 3482 case 0x00: /* default gtf */ 3483 closure->modes += drm_gtf_modes_for_range(closure->connector, 3484 closure->drm_edid, 3485 timing); 3486 break; 3487 case 0x04: /* cvt, only in 1.4+ */ 3488 if (!version_greater(closure->drm_edid, 1, 3)) 3489 break; 3490 3491 closure->modes += drm_cvt_modes_for_range(closure->connector, 3492 closure->drm_edid, 3493 timing); 3494 break; 3495 case 0x01: /* just the ranges, no formula */ 3496 default: 3497 break; 3498 } 3499 } 3500 3501 static int add_inferred_modes(struct drm_connector *connector, 3502 const struct drm_edid *drm_edid) 3503 { 3504 struct detailed_mode_closure closure = { 3505 .connector = connector, 3506 .drm_edid = drm_edid, 3507 }; 3508 3509 if (version_greater(drm_edid, 1, 0)) 3510 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3511 3512 return closure.modes; 3513 } 3514 3515 static int 3516 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3517 { 3518 int i, j, m, modes = 0; 3519 struct drm_display_mode *mode; 3520 const u8 *est = ((const u8 *)timing) + 6; 3521 3522 for (i = 0; i < 6; i++) { 3523 for (j = 7; j >= 0; j--) { 3524 m = (i * 8) + (7 - j); 3525 if (m >= ARRAY_SIZE(est3_modes)) 3526 break; 3527 if (est[i] & (1 << j)) { 3528 mode = drm_mode_find_dmt(connector->dev, 3529 est3_modes[m].w, 3530 est3_modes[m].h, 3531 est3_modes[m].r, 3532 est3_modes[m].rb); 3533 if (mode) { 3534 drm_mode_probed_add(connector, mode); 3535 modes++; 3536 } 3537 } 3538 } 3539 } 3540 3541 return modes; 3542 } 3543 3544 static void 3545 do_established_modes(const struct detailed_timing *timing, void *c) 3546 { 3547 struct detailed_mode_closure *closure = c; 3548 3549 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3550 return; 3551 3552 closure->modes += drm_est3_modes(closure->connector, timing); 3553 } 3554 3555 /* 3556 * Get established modes from EDID and add them. Each EDID block contains a 3557 * bitmap of the supported "established modes" list (defined above). Tease them 3558 * out and add them to the global modes list. 3559 */ 3560 static int add_established_modes(struct drm_connector *connector, 3561 const struct drm_edid *drm_edid) 3562 { 3563 struct drm_device *dev = connector->dev; 3564 const struct edid *edid = drm_edid->edid; 3565 unsigned long est_bits = edid->established_timings.t1 | 3566 (edid->established_timings.t2 << 8) | 3567 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3568 int i, modes = 0; 3569 struct detailed_mode_closure closure = { 3570 .connector = connector, 3571 .drm_edid = drm_edid, 3572 }; 3573 3574 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3575 if (est_bits & (1<<i)) { 3576 struct drm_display_mode *newmode; 3577 3578 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3579 if (newmode) { 3580 drm_mode_probed_add(connector, newmode); 3581 modes++; 3582 } 3583 } 3584 } 3585 3586 if (version_greater(drm_edid, 1, 0)) 3587 drm_for_each_detailed_block(drm_edid, do_established_modes, 3588 &closure); 3589 3590 return modes + closure.modes; 3591 } 3592 3593 static void 3594 do_standard_modes(const struct detailed_timing *timing, void *c) 3595 { 3596 struct detailed_mode_closure *closure = c; 3597 const struct detailed_non_pixel *data = &timing->data.other_data; 3598 struct drm_connector *connector = closure->connector; 3599 int i; 3600 3601 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3602 return; 3603 3604 for (i = 0; i < 6; i++) { 3605 const struct std_timing *std = &data->data.timings[i]; 3606 struct drm_display_mode *newmode; 3607 3608 newmode = drm_mode_std(connector, closure->drm_edid, std); 3609 if (newmode) { 3610 drm_mode_probed_add(connector, newmode); 3611 closure->modes++; 3612 } 3613 } 3614 } 3615 3616 /* 3617 * Get standard modes from EDID and add them. Standard modes can be calculated 3618 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3619 * add them to the list. 3620 */ 3621 static int add_standard_modes(struct drm_connector *connector, 3622 const struct drm_edid *drm_edid) 3623 { 3624 int i, modes = 0; 3625 struct detailed_mode_closure closure = { 3626 .connector = connector, 3627 .drm_edid = drm_edid, 3628 }; 3629 3630 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3631 struct drm_display_mode *newmode; 3632 3633 newmode = drm_mode_std(connector, drm_edid, 3634 &drm_edid->edid->standard_timings[i]); 3635 if (newmode) { 3636 drm_mode_probed_add(connector, newmode); 3637 modes++; 3638 } 3639 } 3640 3641 if (version_greater(drm_edid, 1, 0)) 3642 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3643 &closure); 3644 3645 /* XXX should also look for standard codes in VTB blocks */ 3646 3647 return modes + closure.modes; 3648 } 3649 3650 static int drm_cvt_modes(struct drm_connector *connector, 3651 const struct detailed_timing *timing) 3652 { 3653 int i, j, modes = 0; 3654 struct drm_display_mode *newmode; 3655 struct drm_device *dev = connector->dev; 3656 const struct cvt_timing *cvt; 3657 const int rates[] = { 60, 85, 75, 60, 50 }; 3658 const u8 empty[3] = { 0, 0, 0 }; 3659 3660 for (i = 0; i < 4; i++) { 3661 int width, height; 3662 3663 cvt = &(timing->data.other_data.data.cvt[i]); 3664 3665 if (!memcmp(cvt->code, empty, 3)) 3666 continue; 3667 3668 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3669 switch (cvt->code[1] & 0x0c) { 3670 /* default - because compiler doesn't see that we've enumerated all cases */ 3671 default: 3672 case 0x00: 3673 width = height * 4 / 3; 3674 break; 3675 case 0x04: 3676 width = height * 16 / 9; 3677 break; 3678 case 0x08: 3679 width = height * 16 / 10; 3680 break; 3681 case 0x0c: 3682 width = height * 15 / 9; 3683 break; 3684 } 3685 3686 for (j = 1; j < 5; j++) { 3687 if (cvt->code[2] & (1 << j)) { 3688 newmode = drm_cvt_mode(dev, width, height, 3689 rates[j], j == 0, 3690 false, false); 3691 if (newmode) { 3692 drm_mode_probed_add(connector, newmode); 3693 modes++; 3694 } 3695 } 3696 } 3697 } 3698 3699 return modes; 3700 } 3701 3702 static void 3703 do_cvt_mode(const struct detailed_timing *timing, void *c) 3704 { 3705 struct detailed_mode_closure *closure = c; 3706 3707 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3708 return; 3709 3710 closure->modes += drm_cvt_modes(closure->connector, timing); 3711 } 3712 3713 static int 3714 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 3715 { 3716 struct detailed_mode_closure closure = { 3717 .connector = connector, 3718 .drm_edid = drm_edid, 3719 }; 3720 3721 if (version_greater(drm_edid, 1, 2)) 3722 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 3723 3724 /* XXX should also look for CVT codes in VTB blocks */ 3725 3726 return closure.modes; 3727 } 3728 3729 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3730 3731 static void 3732 do_detailed_mode(const struct detailed_timing *timing, void *c) 3733 { 3734 struct detailed_mode_closure *closure = c; 3735 struct drm_display_mode *newmode; 3736 3737 if (!is_detailed_timing_descriptor(timing)) 3738 return; 3739 3740 newmode = drm_mode_detailed(closure->connector->dev, 3741 closure->drm_edid, timing, 3742 closure->quirks); 3743 if (!newmode) 3744 return; 3745 3746 if (closure->preferred) 3747 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3748 3749 /* 3750 * Detailed modes are limited to 10kHz pixel clock resolution, 3751 * so fix up anything that looks like CEA/HDMI mode, but the clock 3752 * is just slightly off. 3753 */ 3754 fixup_detailed_cea_mode_clock(newmode); 3755 3756 drm_mode_probed_add(closure->connector, newmode); 3757 closure->modes++; 3758 closure->preferred = false; 3759 } 3760 3761 /* 3762 * add_detailed_modes - Add modes from detailed timings 3763 * @connector: attached connector 3764 * @drm_edid: EDID block to scan 3765 * @quirks: quirks to apply 3766 */ 3767 static int add_detailed_modes(struct drm_connector *connector, 3768 const struct drm_edid *drm_edid, u32 quirks) 3769 { 3770 struct detailed_mode_closure closure = { 3771 .connector = connector, 3772 .drm_edid = drm_edid, 3773 .preferred = true, 3774 .quirks = quirks, 3775 }; 3776 3777 if (closure.preferred && !version_greater(drm_edid, 1, 3)) 3778 closure.preferred = 3779 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3780 3781 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 3782 3783 return closure.modes; 3784 } 3785 3786 /* CTA-861-H Table 60 - CTA Tag Codes */ 3787 #define CTA_DB_AUDIO 1 3788 #define CTA_DB_VIDEO 2 3789 #define CTA_DB_VENDOR 3 3790 #define CTA_DB_SPEAKER 4 3791 #define CTA_DB_EXTENDED_TAG 7 3792 3793 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 3794 #define CTA_EXT_DB_VIDEO_CAP 0 3795 #define CTA_EXT_DB_VENDOR 1 3796 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 3797 #define CTA_EXT_DB_420_VIDEO_DATA 14 3798 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 3799 #define CTA_EXT_DB_HF_SCDB 0x79 3800 3801 #define EDID_BASIC_AUDIO (1 << 6) 3802 #define EDID_CEA_YCRCB444 (1 << 5) 3803 #define EDID_CEA_YCRCB422 (1 << 4) 3804 #define EDID_CEA_VCDB_QS (1 << 6) 3805 3806 /* 3807 * Search EDID for CEA extension block. 3808 * 3809 * FIXME: Prefer not returning pointers to raw EDID data. 3810 */ 3811 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 3812 int ext_id, int *ext_index) 3813 { 3814 const u8 *edid_ext = NULL; 3815 int i; 3816 3817 /* No EDID or EDID extensions */ 3818 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 3819 return NULL; 3820 3821 /* Find CEA extension */ 3822 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 3823 edid_ext = drm_edid_extension_block_data(drm_edid, i); 3824 if (edid_block_tag(edid_ext) == ext_id) 3825 break; 3826 } 3827 3828 if (i >= drm_edid_extension_block_count(drm_edid)) 3829 return NULL; 3830 3831 *ext_index = i + 1; 3832 3833 return edid_ext; 3834 } 3835 3836 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 3837 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 3838 { 3839 const struct displayid_block *block; 3840 struct displayid_iter iter; 3841 int ext_index = 0; 3842 bool found = false; 3843 3844 /* Look for a top level CEA extension block */ 3845 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 3846 return true; 3847 3848 /* CEA blocks can also be found embedded in a DisplayID block */ 3849 displayid_iter_edid_begin(drm_edid, &iter); 3850 displayid_iter_for_each(block, &iter) { 3851 if (block->tag == DATA_BLOCK_CTA) { 3852 found = true; 3853 break; 3854 } 3855 } 3856 displayid_iter_end(&iter); 3857 3858 return found; 3859 } 3860 3861 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3862 { 3863 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3864 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3865 3866 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3867 return &edid_cea_modes_1[vic - 1]; 3868 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3869 return &edid_cea_modes_193[vic - 193]; 3870 return NULL; 3871 } 3872 3873 static u8 cea_num_vics(void) 3874 { 3875 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3876 } 3877 3878 static u8 cea_next_vic(u8 vic) 3879 { 3880 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3881 vic = 193; 3882 return vic; 3883 } 3884 3885 /* 3886 * Calculate the alternate clock for the CEA mode 3887 * (60Hz vs. 59.94Hz etc.) 3888 */ 3889 static unsigned int 3890 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3891 { 3892 unsigned int clock = cea_mode->clock; 3893 3894 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3895 return clock; 3896 3897 /* 3898 * edid_cea_modes contains the 59.94Hz 3899 * variant for 240 and 480 line modes, 3900 * and the 60Hz variant otherwise. 3901 */ 3902 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3903 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3904 else 3905 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3906 3907 return clock; 3908 } 3909 3910 static bool 3911 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3912 { 3913 /* 3914 * For certain VICs the spec allows the vertical 3915 * front porch to vary by one or two lines. 3916 * 3917 * cea_modes[] stores the variant with the shortest 3918 * vertical front porch. We can adjust the mode to 3919 * get the other variants by simply increasing the 3920 * vertical front porch length. 3921 */ 3922 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3923 cea_mode_for_vic(9)->vtotal != 262 || 3924 cea_mode_for_vic(12)->vtotal != 262 || 3925 cea_mode_for_vic(13)->vtotal != 262 || 3926 cea_mode_for_vic(23)->vtotal != 312 || 3927 cea_mode_for_vic(24)->vtotal != 312 || 3928 cea_mode_for_vic(27)->vtotal != 312 || 3929 cea_mode_for_vic(28)->vtotal != 312); 3930 3931 if (((vic == 8 || vic == 9 || 3932 vic == 12 || vic == 13) && mode->vtotal < 263) || 3933 ((vic == 23 || vic == 24 || 3934 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3935 mode->vsync_start++; 3936 mode->vsync_end++; 3937 mode->vtotal++; 3938 3939 return true; 3940 } 3941 3942 return false; 3943 } 3944 3945 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3946 unsigned int clock_tolerance) 3947 { 3948 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3949 u8 vic; 3950 3951 if (!to_match->clock) 3952 return 0; 3953 3954 if (to_match->picture_aspect_ratio) 3955 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3956 3957 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3958 struct drm_display_mode cea_mode; 3959 unsigned int clock1, clock2; 3960 3961 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 3962 3963 /* Check both 60Hz and 59.94Hz */ 3964 clock1 = cea_mode.clock; 3965 clock2 = cea_mode_alternate_clock(&cea_mode); 3966 3967 if (abs(to_match->clock - clock1) > clock_tolerance && 3968 abs(to_match->clock - clock2) > clock_tolerance) 3969 continue; 3970 3971 do { 3972 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3973 return vic; 3974 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3975 } 3976 3977 return 0; 3978 } 3979 3980 /** 3981 * drm_match_cea_mode - look for a CEA mode matching given mode 3982 * @to_match: display mode 3983 * 3984 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3985 * mode. 3986 */ 3987 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3988 { 3989 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3990 u8 vic; 3991 3992 if (!to_match->clock) 3993 return 0; 3994 3995 if (to_match->picture_aspect_ratio) 3996 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3997 3998 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3999 struct drm_display_mode cea_mode; 4000 unsigned int clock1, clock2; 4001 4002 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4003 4004 /* Check both 60Hz and 59.94Hz */ 4005 clock1 = cea_mode.clock; 4006 clock2 = cea_mode_alternate_clock(&cea_mode); 4007 4008 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4009 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4010 continue; 4011 4012 do { 4013 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4014 return vic; 4015 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4016 } 4017 4018 return 0; 4019 } 4020 EXPORT_SYMBOL(drm_match_cea_mode); 4021 4022 static bool drm_valid_cea_vic(u8 vic) 4023 { 4024 return cea_mode_for_vic(vic) != NULL; 4025 } 4026 4027 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4028 { 4029 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4030 4031 if (mode) 4032 return mode->picture_aspect_ratio; 4033 4034 return HDMI_PICTURE_ASPECT_NONE; 4035 } 4036 4037 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4038 { 4039 return edid_4k_modes[video_code].picture_aspect_ratio; 4040 } 4041 4042 /* 4043 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4044 * specific block). 4045 */ 4046 static unsigned int 4047 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4048 { 4049 return cea_mode_alternate_clock(hdmi_mode); 4050 } 4051 4052 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4053 unsigned int clock_tolerance) 4054 { 4055 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4056 u8 vic; 4057 4058 if (!to_match->clock) 4059 return 0; 4060 4061 if (to_match->picture_aspect_ratio) 4062 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4063 4064 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4065 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4066 unsigned int clock1, clock2; 4067 4068 /* Make sure to also match alternate clocks */ 4069 clock1 = hdmi_mode->clock; 4070 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4071 4072 if (abs(to_match->clock - clock1) > clock_tolerance && 4073 abs(to_match->clock - clock2) > clock_tolerance) 4074 continue; 4075 4076 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4077 return vic; 4078 } 4079 4080 return 0; 4081 } 4082 4083 /* 4084 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4085 * @to_match: display mode 4086 * 4087 * An HDMI mode is one defined in the HDMI vendor specific block. 4088 * 4089 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4090 */ 4091 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4092 { 4093 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4094 u8 vic; 4095 4096 if (!to_match->clock) 4097 return 0; 4098 4099 if (to_match->picture_aspect_ratio) 4100 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4101 4102 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4103 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4104 unsigned int clock1, clock2; 4105 4106 /* Make sure to also match alternate clocks */ 4107 clock1 = hdmi_mode->clock; 4108 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4109 4110 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4111 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4112 drm_mode_match(to_match, hdmi_mode, match_flags)) 4113 return vic; 4114 } 4115 return 0; 4116 } 4117 4118 static bool drm_valid_hdmi_vic(u8 vic) 4119 { 4120 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4121 } 4122 4123 static int add_alternate_cea_modes(struct drm_connector *connector, 4124 const struct drm_edid *drm_edid) 4125 { 4126 struct drm_device *dev = connector->dev; 4127 struct drm_display_mode *mode, *tmp; 4128 LIST_HEAD(list); 4129 int modes = 0; 4130 4131 /* Don't add CTA modes if the CTA extension block is missing */ 4132 if (!drm_edid_has_cta_extension(drm_edid)) 4133 return 0; 4134 4135 /* 4136 * Go through all probed modes and create a new mode 4137 * with the alternate clock for certain CEA modes. 4138 */ 4139 list_for_each_entry(mode, &connector->probed_modes, head) { 4140 const struct drm_display_mode *cea_mode = NULL; 4141 struct drm_display_mode *newmode; 4142 u8 vic = drm_match_cea_mode(mode); 4143 unsigned int clock1, clock2; 4144 4145 if (drm_valid_cea_vic(vic)) { 4146 cea_mode = cea_mode_for_vic(vic); 4147 clock2 = cea_mode_alternate_clock(cea_mode); 4148 } else { 4149 vic = drm_match_hdmi_mode(mode); 4150 if (drm_valid_hdmi_vic(vic)) { 4151 cea_mode = &edid_4k_modes[vic]; 4152 clock2 = hdmi_mode_alternate_clock(cea_mode); 4153 } 4154 } 4155 4156 if (!cea_mode) 4157 continue; 4158 4159 clock1 = cea_mode->clock; 4160 4161 if (clock1 == clock2) 4162 continue; 4163 4164 if (mode->clock != clock1 && mode->clock != clock2) 4165 continue; 4166 4167 newmode = drm_mode_duplicate(dev, cea_mode); 4168 if (!newmode) 4169 continue; 4170 4171 /* Carry over the stereo flags */ 4172 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4173 4174 /* 4175 * The current mode could be either variant. Make 4176 * sure to pick the "other" clock for the new mode. 4177 */ 4178 if (mode->clock != clock1) 4179 newmode->clock = clock1; 4180 else 4181 newmode->clock = clock2; 4182 4183 list_add_tail(&newmode->head, &list); 4184 } 4185 4186 list_for_each_entry_safe(mode, tmp, &list, head) { 4187 list_del(&mode->head); 4188 drm_mode_probed_add(connector, mode); 4189 modes++; 4190 } 4191 4192 return modes; 4193 } 4194 4195 static u8 svd_to_vic(u8 svd) 4196 { 4197 /* 0-6 bit vic, 7th bit native mode indicator */ 4198 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4199 return svd & 127; 4200 4201 return svd; 4202 } 4203 4204 static struct drm_display_mode * 4205 drm_display_mode_from_vic_index(struct drm_connector *connector, 4206 const u8 *video_db, u8 video_len, 4207 u8 video_index) 4208 { 4209 struct drm_device *dev = connector->dev; 4210 struct drm_display_mode *newmode; 4211 u8 vic; 4212 4213 if (video_db == NULL || video_index >= video_len) 4214 return NULL; 4215 4216 /* CEA modes are numbered 1..127 */ 4217 vic = svd_to_vic(video_db[video_index]); 4218 if (!drm_valid_cea_vic(vic)) 4219 return NULL; 4220 4221 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4222 if (!newmode) 4223 return NULL; 4224 4225 return newmode; 4226 } 4227 4228 /* 4229 * do_y420vdb_modes - Parse YCBCR 420 only modes 4230 * @connector: connector corresponding to the HDMI sink 4231 * @svds: start of the data block of CEA YCBCR 420 VDB 4232 * @len: length of the CEA YCBCR 420 VDB 4233 * 4234 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4235 * which contains modes which can be supported in YCBCR 420 4236 * output format only. 4237 */ 4238 static int do_y420vdb_modes(struct drm_connector *connector, 4239 const u8 *svds, u8 svds_len) 4240 { 4241 int modes = 0, i; 4242 struct drm_device *dev = connector->dev; 4243 struct drm_display_info *info = &connector->display_info; 4244 struct drm_hdmi_info *hdmi = &info->hdmi; 4245 4246 for (i = 0; i < svds_len; i++) { 4247 u8 vic = svd_to_vic(svds[i]); 4248 struct drm_display_mode *newmode; 4249 4250 if (!drm_valid_cea_vic(vic)) 4251 continue; 4252 4253 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4254 if (!newmode) 4255 break; 4256 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 4257 drm_mode_probed_add(connector, newmode); 4258 modes++; 4259 } 4260 4261 if (modes > 0) 4262 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4263 return modes; 4264 } 4265 4266 /* 4267 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 4268 * @connector: connector corresponding to the HDMI sink 4269 * @vic: CEA vic for the video mode to be added in the map 4270 * 4271 * Makes an entry for a videomode in the YCBCR 420 bitmap 4272 */ 4273 static void 4274 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 4275 { 4276 u8 vic = svd_to_vic(svd); 4277 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4278 4279 if (!drm_valid_cea_vic(vic)) 4280 return; 4281 4282 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 4283 } 4284 4285 /** 4286 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4287 * @dev: DRM device 4288 * @video_code: CEA VIC of the mode 4289 * 4290 * Creates a new mode matching the specified CEA VIC. 4291 * 4292 * Returns: A new drm_display_mode on success or NULL on failure 4293 */ 4294 struct drm_display_mode * 4295 drm_display_mode_from_cea_vic(struct drm_device *dev, 4296 u8 video_code) 4297 { 4298 const struct drm_display_mode *cea_mode; 4299 struct drm_display_mode *newmode; 4300 4301 cea_mode = cea_mode_for_vic(video_code); 4302 if (!cea_mode) 4303 return NULL; 4304 4305 newmode = drm_mode_duplicate(dev, cea_mode); 4306 if (!newmode) 4307 return NULL; 4308 4309 return newmode; 4310 } 4311 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4312 4313 static int 4314 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 4315 { 4316 int i, modes = 0; 4317 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4318 4319 for (i = 0; i < len; i++) { 4320 struct drm_display_mode *mode; 4321 4322 mode = drm_display_mode_from_vic_index(connector, db, len, i); 4323 if (mode) { 4324 /* 4325 * YCBCR420 capability block contains a bitmap which 4326 * gives the index of CEA modes from CEA VDB, which 4327 * can support YCBCR 420 sampling output also (apart 4328 * from RGB/YCBCR444 etc). 4329 * For example, if the bit 0 in bitmap is set, 4330 * first mode in VDB can support YCBCR420 output too. 4331 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 4332 */ 4333 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 4334 drm_add_cmdb_modes(connector, db[i]); 4335 4336 drm_mode_probed_add(connector, mode); 4337 modes++; 4338 } 4339 } 4340 4341 return modes; 4342 } 4343 4344 struct stereo_mandatory_mode { 4345 int width, height, vrefresh; 4346 unsigned int flags; 4347 }; 4348 4349 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4350 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4351 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4352 { 1920, 1080, 50, 4353 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4354 { 1920, 1080, 60, 4355 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4356 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4357 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4358 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4359 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4360 }; 4361 4362 static bool 4363 stereo_match_mandatory(const struct drm_display_mode *mode, 4364 const struct stereo_mandatory_mode *stereo_mode) 4365 { 4366 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4367 4368 return mode->hdisplay == stereo_mode->width && 4369 mode->vdisplay == stereo_mode->height && 4370 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4371 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4372 } 4373 4374 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4375 { 4376 struct drm_device *dev = connector->dev; 4377 const struct drm_display_mode *mode; 4378 struct list_head stereo_modes; 4379 int modes = 0, i; 4380 4381 INIT_LIST_HEAD(&stereo_modes); 4382 4383 list_for_each_entry(mode, &connector->probed_modes, head) { 4384 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4385 const struct stereo_mandatory_mode *mandatory; 4386 struct drm_display_mode *new_mode; 4387 4388 if (!stereo_match_mandatory(mode, 4389 &stereo_mandatory_modes[i])) 4390 continue; 4391 4392 mandatory = &stereo_mandatory_modes[i]; 4393 new_mode = drm_mode_duplicate(dev, mode); 4394 if (!new_mode) 4395 continue; 4396 4397 new_mode->flags |= mandatory->flags; 4398 list_add_tail(&new_mode->head, &stereo_modes); 4399 modes++; 4400 } 4401 } 4402 4403 list_splice_tail(&stereo_modes, &connector->probed_modes); 4404 4405 return modes; 4406 } 4407 4408 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4409 { 4410 struct drm_device *dev = connector->dev; 4411 struct drm_display_mode *newmode; 4412 4413 if (!drm_valid_hdmi_vic(vic)) { 4414 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 4415 return 0; 4416 } 4417 4418 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4419 if (!newmode) 4420 return 0; 4421 4422 drm_mode_probed_add(connector, newmode); 4423 4424 return 1; 4425 } 4426 4427 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4428 const u8 *video_db, u8 video_len, u8 video_index) 4429 { 4430 struct drm_display_mode *newmode; 4431 int modes = 0; 4432 4433 if (structure & (1 << 0)) { 4434 newmode = drm_display_mode_from_vic_index(connector, video_db, 4435 video_len, 4436 video_index); 4437 if (newmode) { 4438 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4439 drm_mode_probed_add(connector, newmode); 4440 modes++; 4441 } 4442 } 4443 if (structure & (1 << 6)) { 4444 newmode = drm_display_mode_from_vic_index(connector, video_db, 4445 video_len, 4446 video_index); 4447 if (newmode) { 4448 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4449 drm_mode_probed_add(connector, newmode); 4450 modes++; 4451 } 4452 } 4453 if (structure & (1 << 8)) { 4454 newmode = drm_display_mode_from_vic_index(connector, video_db, 4455 video_len, 4456 video_index); 4457 if (newmode) { 4458 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4459 drm_mode_probed_add(connector, newmode); 4460 modes++; 4461 } 4462 } 4463 4464 return modes; 4465 } 4466 4467 /* 4468 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4469 * @connector: connector corresponding to the HDMI sink 4470 * @db: start of the CEA vendor specific block 4471 * @len: length of the CEA block payload, ie. one can access up to db[len] 4472 * 4473 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4474 * also adds the stereo 3d modes when applicable. 4475 */ 4476 static int 4477 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4478 const u8 *video_db, u8 video_len) 4479 { 4480 struct drm_display_info *info = &connector->display_info; 4481 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4482 u8 vic_len, hdmi_3d_len = 0; 4483 u16 mask; 4484 u16 structure_all; 4485 4486 if (len < 8) 4487 goto out; 4488 4489 /* no HDMI_Video_Present */ 4490 if (!(db[8] & (1 << 5))) 4491 goto out; 4492 4493 /* Latency_Fields_Present */ 4494 if (db[8] & (1 << 7)) 4495 offset += 2; 4496 4497 /* I_Latency_Fields_Present */ 4498 if (db[8] & (1 << 6)) 4499 offset += 2; 4500 4501 /* the declared length is not long enough for the 2 first bytes 4502 * of additional video format capabilities */ 4503 if (len < (8 + offset + 2)) 4504 goto out; 4505 4506 /* 3D_Present */ 4507 offset++; 4508 if (db[8 + offset] & (1 << 7)) { 4509 modes += add_hdmi_mandatory_stereo_modes(connector); 4510 4511 /* 3D_Multi_present */ 4512 multi_present = (db[8 + offset] & 0x60) >> 5; 4513 } 4514 4515 offset++; 4516 vic_len = db[8 + offset] >> 5; 4517 hdmi_3d_len = db[8 + offset] & 0x1f; 4518 4519 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4520 u8 vic; 4521 4522 vic = db[9 + offset + i]; 4523 modes += add_hdmi_mode(connector, vic); 4524 } 4525 offset += 1 + vic_len; 4526 4527 if (multi_present == 1) 4528 multi_len = 2; 4529 else if (multi_present == 2) 4530 multi_len = 4; 4531 else 4532 multi_len = 0; 4533 4534 if (len < (8 + offset + hdmi_3d_len - 1)) 4535 goto out; 4536 4537 if (hdmi_3d_len < multi_len) 4538 goto out; 4539 4540 if (multi_present == 1 || multi_present == 2) { 4541 /* 3D_Structure_ALL */ 4542 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4543 4544 /* check if 3D_MASK is present */ 4545 if (multi_present == 2) 4546 mask = (db[10 + offset] << 8) | db[11 + offset]; 4547 else 4548 mask = 0xffff; 4549 4550 for (i = 0; i < 16; i++) { 4551 if (mask & (1 << i)) 4552 modes += add_3d_struct_modes(connector, 4553 structure_all, 4554 video_db, 4555 video_len, i); 4556 } 4557 } 4558 4559 offset += multi_len; 4560 4561 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4562 int vic_index; 4563 struct drm_display_mode *newmode = NULL; 4564 unsigned int newflag = 0; 4565 bool detail_present; 4566 4567 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4568 4569 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4570 break; 4571 4572 /* 2D_VIC_order_X */ 4573 vic_index = db[8 + offset + i] >> 4; 4574 4575 /* 3D_Structure_X */ 4576 switch (db[8 + offset + i] & 0x0f) { 4577 case 0: 4578 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4579 break; 4580 case 6: 4581 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4582 break; 4583 case 8: 4584 /* 3D_Detail_X */ 4585 if ((db[9 + offset + i] >> 4) == 1) 4586 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4587 break; 4588 } 4589 4590 if (newflag != 0) { 4591 newmode = drm_display_mode_from_vic_index(connector, 4592 video_db, 4593 video_len, 4594 vic_index); 4595 4596 if (newmode) { 4597 newmode->flags |= newflag; 4598 drm_mode_probed_add(connector, newmode); 4599 modes++; 4600 } 4601 } 4602 4603 if (detail_present) 4604 i++; 4605 } 4606 4607 out: 4608 if (modes > 0) 4609 info->has_hdmi_infoframe = true; 4610 return modes; 4611 } 4612 4613 static int 4614 cea_revision(const u8 *cea) 4615 { 4616 /* 4617 * FIXME is this correct for the DispID variant? 4618 * The DispID spec doesn't really specify whether 4619 * this is the revision of the CEA extension or 4620 * the DispID CEA data block. And the only value 4621 * given as an example is 0. 4622 */ 4623 return cea[1]; 4624 } 4625 4626 /* 4627 * CTA Data Block iterator. 4628 * 4629 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4630 * CTA Data Blocks. 4631 * 4632 * struct cea_db *db: 4633 * struct cea_db_iter iter; 4634 * 4635 * cea_db_iter_edid_begin(edid, &iter); 4636 * cea_db_iter_for_each(db, &iter) { 4637 * // do stuff with db 4638 * } 4639 * cea_db_iter_end(&iter); 4640 */ 4641 struct cea_db_iter { 4642 struct drm_edid_iter edid_iter; 4643 struct displayid_iter displayid_iter; 4644 4645 /* Current Data Block Collection. */ 4646 const u8 *collection; 4647 4648 /* Current Data Block index in current collection. */ 4649 int index; 4650 4651 /* End index in current collection. */ 4652 int end; 4653 }; 4654 4655 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4656 struct cea_db { 4657 u8 tag_length; 4658 u8 data[]; 4659 } __packed; 4660 4661 static int cea_db_tag(const struct cea_db *db) 4662 { 4663 return db->tag_length >> 5; 4664 } 4665 4666 static int cea_db_payload_len(const void *_db) 4667 { 4668 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4669 const struct cea_db *db = _db; 4670 4671 return db->tag_length & 0x1f; 4672 } 4673 4674 static const void *cea_db_data(const struct cea_db *db) 4675 { 4676 return db->data; 4677 } 4678 4679 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4680 { 4681 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4682 cea_db_payload_len(db) >= 1 && 4683 db->data[0] == tag; 4684 } 4685 4686 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4687 { 4688 const u8 *data = cea_db_data(db); 4689 4690 return cea_db_tag(db) == CTA_DB_VENDOR && 4691 cea_db_payload_len(db) >= 3 && 4692 oui(data[2], data[1], data[0]) == vendor_oui; 4693 } 4694 4695 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4696 struct cea_db_iter *iter) 4697 { 4698 memset(iter, 0, sizeof(*iter)); 4699 4700 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4701 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4702 } 4703 4704 static const struct cea_db * 4705 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4706 { 4707 const struct cea_db *db; 4708 4709 if (!iter->collection) 4710 return NULL; 4711 4712 db = (const struct cea_db *)&iter->collection[iter->index]; 4713 4714 if (iter->index + sizeof(*db) <= iter->end && 4715 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4716 return db; 4717 4718 return NULL; 4719 } 4720 4721 /* 4722 * References: 4723 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4724 */ 4725 static int cea_db_collection_size(const u8 *cta) 4726 { 4727 u8 d = cta[2]; 4728 4729 if (d < 4 || d > 127) 4730 return 0; 4731 4732 return d - 4; 4733 } 4734 4735 /* 4736 * References: 4737 * - VESA E-EDID v1.4 4738 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4739 */ 4740 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4741 { 4742 const u8 *ext; 4743 4744 drm_edid_iter_for_each(ext, &iter->edid_iter) { 4745 int size; 4746 4747 /* Only support CTA Extension revision 3+ */ 4748 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 4749 continue; 4750 4751 size = cea_db_collection_size(ext); 4752 if (!size) 4753 continue; 4754 4755 iter->index = 4; 4756 iter->end = iter->index + size; 4757 4758 return ext; 4759 } 4760 4761 return NULL; 4762 } 4763 4764 /* 4765 * References: 4766 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 4767 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 4768 * 4769 * Note that the above do not specify any connection between DisplayID Data 4770 * Block revision and CTA Extension versions. 4771 */ 4772 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 4773 { 4774 const struct displayid_block *block; 4775 4776 displayid_iter_for_each(block, &iter->displayid_iter) { 4777 if (block->tag != DATA_BLOCK_CTA) 4778 continue; 4779 4780 /* 4781 * The displayid iterator has already verified the block bounds 4782 * in displayid_iter_block(). 4783 */ 4784 iter->index = sizeof(*block); 4785 iter->end = iter->index + block->num_bytes; 4786 4787 return block; 4788 } 4789 4790 return NULL; 4791 } 4792 4793 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 4794 { 4795 const struct cea_db *db; 4796 4797 if (iter->collection) { 4798 /* Current collection should always be valid. */ 4799 db = __cea_db_iter_current_block(iter); 4800 if (WARN_ON(!db)) { 4801 iter->collection = NULL; 4802 return NULL; 4803 } 4804 4805 /* Next block in CTA Data Block Collection */ 4806 iter->index += sizeof(*db) + cea_db_payload_len(db); 4807 4808 db = __cea_db_iter_current_block(iter); 4809 if (db) 4810 return db; 4811 } 4812 4813 for (;;) { 4814 /* 4815 * Find the next CTA Data Block Collection. First iterate all 4816 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 4817 * 4818 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 4819 * Extension, it's recommended that DisplayID extensions are 4820 * exposed after all of the CTA Extensions. 4821 */ 4822 iter->collection = __cea_db_iter_edid_next(iter); 4823 if (!iter->collection) 4824 iter->collection = __cea_db_iter_displayid_next(iter); 4825 4826 if (!iter->collection) 4827 return NULL; 4828 4829 db = __cea_db_iter_current_block(iter); 4830 if (db) 4831 return db; 4832 } 4833 } 4834 4835 #define cea_db_iter_for_each(__db, __iter) \ 4836 while (((__db) = __cea_db_iter_next(__iter))) 4837 4838 static void cea_db_iter_end(struct cea_db_iter *iter) 4839 { 4840 displayid_iter_end(&iter->displayid_iter); 4841 drm_edid_iter_end(&iter->edid_iter); 4842 4843 memset(iter, 0, sizeof(*iter)); 4844 } 4845 4846 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 4847 { 4848 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 4849 cea_db_payload_len(db) >= 5; 4850 } 4851 4852 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 4853 { 4854 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 4855 cea_db_payload_len(db) >= 7; 4856 } 4857 4858 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 4859 { 4860 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 4861 cea_db_payload_len(db) == 21; 4862 } 4863 4864 static bool cea_db_is_vcdb(const struct cea_db *db) 4865 { 4866 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 4867 cea_db_payload_len(db) == 2; 4868 } 4869 4870 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 4871 { 4872 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 4873 cea_db_payload_len(db) >= 7; 4874 } 4875 4876 static bool cea_db_is_y420cmdb(const struct cea_db *db) 4877 { 4878 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 4879 } 4880 4881 static bool cea_db_is_y420vdb(const struct cea_db *db) 4882 { 4883 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 4884 } 4885 4886 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 4887 { 4888 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 4889 cea_db_payload_len(db) >= 3; 4890 } 4891 4892 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4893 const u8 *db) 4894 { 4895 struct drm_display_info *info = &connector->display_info; 4896 struct drm_hdmi_info *hdmi = &info->hdmi; 4897 u8 map_len = cea_db_payload_len(db) - 1; 4898 u8 count; 4899 u64 map = 0; 4900 4901 if (map_len == 0) { 4902 /* All CEA modes support ycbcr420 sampling also.*/ 4903 hdmi->y420_cmdb_map = U64_MAX; 4904 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4905 return; 4906 } 4907 4908 /* 4909 * This map indicates which of the existing CEA block modes 4910 * from VDB can support YCBCR420 output too. So if bit=0 is 4911 * set, first mode from VDB can support YCBCR420 output too. 4912 * We will parse and keep this map, before parsing VDB itself 4913 * to avoid going through the same block again and again. 4914 * 4915 * Spec is not clear about max possible size of this block. 4916 * Clamping max bitmap block size at 8 bytes. Every byte can 4917 * address 8 CEA modes, in this way this map can address 4918 * 8*8 = first 64 SVDs. 4919 */ 4920 if (WARN_ON_ONCE(map_len > 8)) 4921 map_len = 8; 4922 4923 for (count = 0; count < map_len; count++) 4924 map |= (u64)db[2 + count] << (8 * count); 4925 4926 if (map) 4927 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4928 4929 hdmi->y420_cmdb_map = map; 4930 } 4931 4932 static int add_cea_modes(struct drm_connector *connector, 4933 const struct drm_edid *drm_edid) 4934 { 4935 const struct cea_db *db; 4936 struct cea_db_iter iter; 4937 int modes = 0; 4938 4939 cea_db_iter_edid_begin(drm_edid, &iter); 4940 cea_db_iter_for_each(db, &iter) { 4941 const u8 *hdmi = NULL, *video = NULL; 4942 u8 hdmi_len = 0, video_len = 0; 4943 4944 if (cea_db_tag(db) == CTA_DB_VIDEO) { 4945 video = cea_db_data(db); 4946 video_len = cea_db_payload_len(db); 4947 modes += do_cea_modes(connector, video, video_len); 4948 } else if (cea_db_is_hdmi_vsdb(db)) { 4949 /* FIXME: Switch to use cea_db_data() */ 4950 hdmi = (const u8 *)db; 4951 hdmi_len = cea_db_payload_len(db); 4952 } else if (cea_db_is_y420vdb(db)) { 4953 const u8 *vdb420 = cea_db_data(db) + 1; 4954 4955 /* Add 4:2:0(only) modes present in EDID */ 4956 modes += do_y420vdb_modes(connector, vdb420, 4957 cea_db_payload_len(db) - 1); 4958 } 4959 4960 /* 4961 * We parse the HDMI VSDB after having added the cea modes as we 4962 * will be patching their flags when the sink supports stereo 4963 * 3D. 4964 */ 4965 if (hdmi) 4966 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, 4967 video, video_len); 4968 } 4969 cea_db_iter_end(&iter); 4970 4971 return modes; 4972 } 4973 4974 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4975 { 4976 const struct drm_display_mode *cea_mode; 4977 int clock1, clock2, clock; 4978 u8 vic; 4979 const char *type; 4980 4981 /* 4982 * allow 5kHz clock difference either way to account for 4983 * the 10kHz clock resolution limit of detailed timings. 4984 */ 4985 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4986 if (drm_valid_cea_vic(vic)) { 4987 type = "CEA"; 4988 cea_mode = cea_mode_for_vic(vic); 4989 clock1 = cea_mode->clock; 4990 clock2 = cea_mode_alternate_clock(cea_mode); 4991 } else { 4992 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4993 if (drm_valid_hdmi_vic(vic)) { 4994 type = "HDMI"; 4995 cea_mode = &edid_4k_modes[vic]; 4996 clock1 = cea_mode->clock; 4997 clock2 = hdmi_mode_alternate_clock(cea_mode); 4998 } else { 4999 return; 5000 } 5001 } 5002 5003 /* pick whichever is closest */ 5004 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5005 clock = clock1; 5006 else 5007 clock = clock2; 5008 5009 if (mode->clock == clock) 5010 return; 5011 5012 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5013 type, vic, mode->clock, clock); 5014 mode->clock = clock; 5015 } 5016 5017 static uint8_t eotf_supported(const u8 *edid_ext) 5018 { 5019 return edid_ext[2] & 5020 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5021 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5022 BIT(HDMI_EOTF_SMPTE_ST2084) | 5023 BIT(HDMI_EOTF_BT_2100_HLG)); 5024 } 5025 5026 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5027 { 5028 return edid_ext[3] & 5029 BIT(HDMI_STATIC_METADATA_TYPE1); 5030 } 5031 5032 static void 5033 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5034 { 5035 u16 len; 5036 5037 len = cea_db_payload_len(db); 5038 5039 connector->hdr_sink_metadata.hdmi_type1.eotf = 5040 eotf_supported(db); 5041 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5042 hdr_metadata_type(db); 5043 5044 if (len >= 4) 5045 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5046 if (len >= 5) 5047 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5048 if (len >= 6) 5049 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5050 } 5051 5052 static void 5053 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5054 { 5055 u8 len = cea_db_payload_len(db); 5056 5057 if (len >= 6 && (db[6] & (1 << 7))) 5058 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5059 if (len >= 8) { 5060 connector->latency_present[0] = db[8] >> 7; 5061 connector->latency_present[1] = (db[8] >> 6) & 1; 5062 } 5063 if (len >= 9) 5064 connector->video_latency[0] = db[9]; 5065 if (len >= 10) 5066 connector->audio_latency[0] = db[10]; 5067 if (len >= 11) 5068 connector->video_latency[1] = db[11]; 5069 if (len >= 12) 5070 connector->audio_latency[1] = db[12]; 5071 5072 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 5073 "video latency %d %d, " 5074 "audio latency %d %d\n", 5075 connector->latency_present[0], 5076 connector->latency_present[1], 5077 connector->video_latency[0], 5078 connector->video_latency[1], 5079 connector->audio_latency[0], 5080 connector->audio_latency[1]); 5081 } 5082 5083 static void 5084 monitor_name(const struct detailed_timing *timing, void *data) 5085 { 5086 const char **res = data; 5087 5088 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5089 return; 5090 5091 *res = timing->data.other_data.data.str.str; 5092 } 5093 5094 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5095 { 5096 const char *edid_name = NULL; 5097 int mnl; 5098 5099 if (!drm_edid || !name) 5100 return 0; 5101 5102 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5103 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5104 if (edid_name[mnl] == 0x0a) 5105 break; 5106 5107 name[mnl] = edid_name[mnl]; 5108 } 5109 5110 return mnl; 5111 } 5112 5113 /** 5114 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5115 * @edid: monitor EDID information 5116 * @name: pointer to a character array to hold the name of the monitor 5117 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5118 * 5119 */ 5120 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5121 { 5122 int name_length = 0; 5123 5124 if (bufsize <= 0) 5125 return; 5126 5127 if (edid) { 5128 char buf[13]; 5129 struct drm_edid drm_edid = { 5130 .edid = edid, 5131 .size = edid_size(edid), 5132 }; 5133 5134 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5135 memcpy(name, buf, name_length); 5136 } 5137 5138 name[name_length] = '\0'; 5139 } 5140 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5141 5142 static void clear_eld(struct drm_connector *connector) 5143 { 5144 memset(connector->eld, 0, sizeof(connector->eld)); 5145 5146 connector->latency_present[0] = false; 5147 connector->latency_present[1] = false; 5148 connector->video_latency[0] = 0; 5149 connector->audio_latency[0] = 0; 5150 connector->video_latency[1] = 0; 5151 connector->audio_latency[1] = 0; 5152 } 5153 5154 /* 5155 * drm_edid_to_eld - build ELD from EDID 5156 * @connector: connector corresponding to the HDMI/DP sink 5157 * @drm_edid: EDID to parse 5158 * 5159 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5160 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5161 */ 5162 static void drm_edid_to_eld(struct drm_connector *connector, 5163 const struct drm_edid *drm_edid) 5164 { 5165 const struct drm_display_info *info = &connector->display_info; 5166 const struct cea_db *db; 5167 struct cea_db_iter iter; 5168 uint8_t *eld = connector->eld; 5169 int total_sad_count = 0; 5170 int mnl; 5171 5172 clear_eld(connector); 5173 5174 if (!drm_edid) 5175 return; 5176 5177 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5178 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 5179 5180 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5181 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5182 5183 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5184 5185 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5186 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5187 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5188 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5189 5190 cea_db_iter_edid_begin(drm_edid, &iter); 5191 cea_db_iter_for_each(db, &iter) { 5192 const u8 *data = cea_db_data(db); 5193 int len = cea_db_payload_len(db); 5194 int sad_count; 5195 5196 switch (cea_db_tag(db)) { 5197 case CTA_DB_AUDIO: 5198 /* Audio Data Block, contains SADs */ 5199 sad_count = min(len / 3, 15 - total_sad_count); 5200 if (sad_count >= 1) 5201 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5202 data, sad_count * 3); 5203 total_sad_count += sad_count; 5204 break; 5205 case CTA_DB_SPEAKER: 5206 /* Speaker Allocation Data Block */ 5207 if (len >= 1) 5208 eld[DRM_ELD_SPEAKER] = data[0]; 5209 break; 5210 case CTA_DB_VENDOR: 5211 /* HDMI Vendor-Specific Data Block */ 5212 if (cea_db_is_hdmi_vsdb(db)) 5213 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5214 break; 5215 default: 5216 break; 5217 } 5218 } 5219 cea_db_iter_end(&iter); 5220 5221 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5222 5223 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5224 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5225 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5226 else 5227 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5228 5229 eld[DRM_ELD_BASELINE_ELD_LEN] = 5230 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5231 5232 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 5233 drm_eld_size(eld), total_sad_count); 5234 } 5235 5236 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5237 struct cea_sad **sads) 5238 { 5239 const struct cea_db *db; 5240 struct cea_db_iter iter; 5241 int count = 0; 5242 5243 cea_db_iter_edid_begin(drm_edid, &iter); 5244 cea_db_iter_for_each(db, &iter) { 5245 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5246 int j; 5247 5248 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5249 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5250 if (!*sads) 5251 return -ENOMEM; 5252 for (j = 0; j < count; j++) { 5253 const u8 *sad = &db->data[j * 3]; 5254 5255 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5256 (*sads)[j].channels = sad[0] & 0x7; 5257 (*sads)[j].freq = sad[1] & 0x7F; 5258 (*sads)[j].byte2 = sad[2]; 5259 } 5260 break; 5261 } 5262 } 5263 cea_db_iter_end(&iter); 5264 5265 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5266 5267 return count; 5268 } 5269 5270 /** 5271 * drm_edid_to_sad - extracts SADs from EDID 5272 * @edid: EDID to parse 5273 * @sads: pointer that will be set to the extracted SADs 5274 * 5275 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5276 * 5277 * Note: The returned pointer needs to be freed using kfree(). 5278 * 5279 * Return: The number of found SADs or negative number on error. 5280 */ 5281 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5282 { 5283 struct drm_edid drm_edid; 5284 5285 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5286 } 5287 EXPORT_SYMBOL(drm_edid_to_sad); 5288 5289 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5290 u8 **sadb) 5291 { 5292 const struct cea_db *db; 5293 struct cea_db_iter iter; 5294 int count = 0; 5295 5296 cea_db_iter_edid_begin(drm_edid, &iter); 5297 cea_db_iter_for_each(db, &iter) { 5298 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5299 cea_db_payload_len(db) == 3) { 5300 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5301 GFP_KERNEL); 5302 if (!*sadb) 5303 return -ENOMEM; 5304 count = cea_db_payload_len(db); 5305 break; 5306 } 5307 } 5308 cea_db_iter_end(&iter); 5309 5310 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5311 5312 return count; 5313 } 5314 5315 /** 5316 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5317 * @edid: EDID to parse 5318 * @sadb: pointer to the speaker block 5319 * 5320 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5321 * 5322 * Note: The returned pointer needs to be freed using kfree(). 5323 * 5324 * Return: The number of found Speaker Allocation Blocks or negative number on 5325 * error. 5326 */ 5327 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5328 { 5329 struct drm_edid drm_edid; 5330 5331 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5332 sadb); 5333 } 5334 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5335 5336 /** 5337 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5338 * @connector: connector associated with the HDMI/DP sink 5339 * @mode: the display mode 5340 * 5341 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5342 * the sink doesn't support audio or video. 5343 */ 5344 int drm_av_sync_delay(struct drm_connector *connector, 5345 const struct drm_display_mode *mode) 5346 { 5347 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5348 int a, v; 5349 5350 if (!connector->latency_present[0]) 5351 return 0; 5352 if (!connector->latency_present[1]) 5353 i = 0; 5354 5355 a = connector->audio_latency[i]; 5356 v = connector->video_latency[i]; 5357 5358 /* 5359 * HDMI/DP sink doesn't support audio or video? 5360 */ 5361 if (a == 255 || v == 255) 5362 return 0; 5363 5364 /* 5365 * Convert raw EDID values to millisecond. 5366 * Treat unknown latency as 0ms. 5367 */ 5368 if (a) 5369 a = min(2 * (a - 1), 500); 5370 if (v) 5371 v = min(2 * (v - 1), 500); 5372 5373 return max(v - a, 0); 5374 } 5375 EXPORT_SYMBOL(drm_av_sync_delay); 5376 5377 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5378 { 5379 const struct cea_db *db; 5380 struct cea_db_iter iter; 5381 bool hdmi = false; 5382 5383 /* 5384 * Because HDMI identifier is in Vendor Specific Block, 5385 * search it from all data blocks of CEA extension. 5386 */ 5387 cea_db_iter_edid_begin(drm_edid, &iter); 5388 cea_db_iter_for_each(db, &iter) { 5389 if (cea_db_is_hdmi_vsdb(db)) { 5390 hdmi = true; 5391 break; 5392 } 5393 } 5394 cea_db_iter_end(&iter); 5395 5396 return hdmi; 5397 } 5398 5399 /** 5400 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5401 * @edid: monitor EDID information 5402 * 5403 * Parse the CEA extension according to CEA-861-B. 5404 * 5405 * Drivers that have added the modes parsed from EDID to drm_display_info 5406 * should use &drm_display_info.is_hdmi instead of calling this function. 5407 * 5408 * Return: True if the monitor is HDMI, false if not or unknown. 5409 */ 5410 bool drm_detect_hdmi_monitor(const struct edid *edid) 5411 { 5412 struct drm_edid drm_edid; 5413 5414 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5415 } 5416 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5417 5418 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5419 { 5420 struct drm_edid_iter edid_iter; 5421 const struct cea_db *db; 5422 struct cea_db_iter iter; 5423 const u8 *edid_ext; 5424 bool has_audio = false; 5425 5426 drm_edid_iter_begin(drm_edid, &edid_iter); 5427 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5428 if (edid_ext[0] == CEA_EXT) { 5429 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5430 if (has_audio) 5431 break; 5432 } 5433 } 5434 drm_edid_iter_end(&edid_iter); 5435 5436 if (has_audio) { 5437 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5438 goto end; 5439 } 5440 5441 cea_db_iter_edid_begin(drm_edid, &iter); 5442 cea_db_iter_for_each(db, &iter) { 5443 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5444 const u8 *data = cea_db_data(db); 5445 int i; 5446 5447 for (i = 0; i < cea_db_payload_len(db); i += 3) 5448 DRM_DEBUG_KMS("CEA audio format %d\n", 5449 (data[i] >> 3) & 0xf); 5450 has_audio = true; 5451 break; 5452 } 5453 } 5454 cea_db_iter_end(&iter); 5455 5456 end: 5457 return has_audio; 5458 } 5459 5460 /** 5461 * drm_detect_monitor_audio - check monitor audio capability 5462 * @edid: EDID block to scan 5463 * 5464 * Monitor should have CEA extension block. 5465 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5466 * audio' only. If there is any audio extension block and supported 5467 * audio format, assume at least 'basic audio' support, even if 'basic 5468 * audio' is not defined in EDID. 5469 * 5470 * Return: True if the monitor supports audio, false otherwise. 5471 */ 5472 bool drm_detect_monitor_audio(const struct edid *edid) 5473 { 5474 struct drm_edid drm_edid; 5475 5476 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5477 } 5478 EXPORT_SYMBOL(drm_detect_monitor_audio); 5479 5480 5481 /** 5482 * drm_default_rgb_quant_range - default RGB quantization range 5483 * @mode: display mode 5484 * 5485 * Determine the default RGB quantization range for the mode, 5486 * as specified in CEA-861. 5487 * 5488 * Return: The default RGB quantization range for the mode 5489 */ 5490 enum hdmi_quantization_range 5491 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5492 { 5493 /* All CEA modes other than VIC 1 use limited quantization range. */ 5494 return drm_match_cea_mode(mode) > 1 ? 5495 HDMI_QUANTIZATION_RANGE_LIMITED : 5496 HDMI_QUANTIZATION_RANGE_FULL; 5497 } 5498 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5499 5500 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5501 { 5502 struct drm_display_info *info = &connector->display_info; 5503 5504 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 5505 5506 if (db[2] & EDID_CEA_VCDB_QS) 5507 info->rgb_quant_range_selectable = true; 5508 } 5509 5510 static 5511 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5512 { 5513 switch (max_frl_rate) { 5514 case 1: 5515 *max_lanes = 3; 5516 *max_rate_per_lane = 3; 5517 break; 5518 case 2: 5519 *max_lanes = 3; 5520 *max_rate_per_lane = 6; 5521 break; 5522 case 3: 5523 *max_lanes = 4; 5524 *max_rate_per_lane = 6; 5525 break; 5526 case 4: 5527 *max_lanes = 4; 5528 *max_rate_per_lane = 8; 5529 break; 5530 case 5: 5531 *max_lanes = 4; 5532 *max_rate_per_lane = 10; 5533 break; 5534 case 6: 5535 *max_lanes = 4; 5536 *max_rate_per_lane = 12; 5537 break; 5538 case 0: 5539 default: 5540 *max_lanes = 0; 5541 *max_rate_per_lane = 0; 5542 } 5543 } 5544 5545 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5546 const u8 *db) 5547 { 5548 u8 dc_mask; 5549 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5550 5551 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5552 hdmi->y420_dc_modes = dc_mask; 5553 } 5554 5555 /* Sink Capability Data Structure */ 5556 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 5557 const u8 *hf_scds) 5558 { 5559 struct drm_display_info *display = &connector->display_info; 5560 struct drm_hdmi_info *hdmi = &display->hdmi; 5561 5562 display->has_hdmi_infoframe = true; 5563 5564 if (hf_scds[6] & 0x80) { 5565 hdmi->scdc.supported = true; 5566 if (hf_scds[6] & 0x40) 5567 hdmi->scdc.read_request = true; 5568 } 5569 5570 /* 5571 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 5572 * And as per the spec, three factors confirm this: 5573 * * Availability of a HF-VSDB block in EDID (check) 5574 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 5575 * * SCDC support available (let's check) 5576 * Lets check it out. 5577 */ 5578 5579 if (hf_scds[5]) { 5580 /* max clock is 5000 KHz times block value */ 5581 u32 max_tmds_clock = hf_scds[5] * 5000; 5582 struct drm_scdc *scdc = &hdmi->scdc; 5583 5584 if (max_tmds_clock > 340000) { 5585 display->max_tmds_clock = max_tmds_clock; 5586 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 5587 display->max_tmds_clock); 5588 } 5589 5590 if (scdc->supported) { 5591 scdc->scrambling.supported = true; 5592 5593 /* Few sinks support scrambling for clocks < 340M */ 5594 if ((hf_scds[6] & 0x8)) 5595 scdc->scrambling.low_rates = true; 5596 } 5597 } 5598 5599 if (hf_scds[7]) { 5600 u8 max_frl_rate; 5601 u8 dsc_max_frl_rate; 5602 u8 dsc_max_slices; 5603 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5604 5605 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 5606 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 5607 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 5608 &hdmi->max_frl_rate_per_lane); 5609 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5610 5611 if (hdmi_dsc->v_1p2) { 5612 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5613 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5614 5615 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 5616 hdmi_dsc->bpc_supported = 16; 5617 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 5618 hdmi_dsc->bpc_supported = 12; 5619 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 5620 hdmi_dsc->bpc_supported = 10; 5621 else 5622 hdmi_dsc->bpc_supported = 0; 5623 5624 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5625 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5626 &hdmi_dsc->max_frl_rate_per_lane); 5627 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5628 5629 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 5630 switch (dsc_max_slices) { 5631 case 1: 5632 hdmi_dsc->max_slices = 1; 5633 hdmi_dsc->clk_per_slice = 340; 5634 break; 5635 case 2: 5636 hdmi_dsc->max_slices = 2; 5637 hdmi_dsc->clk_per_slice = 340; 5638 break; 5639 case 3: 5640 hdmi_dsc->max_slices = 4; 5641 hdmi_dsc->clk_per_slice = 340; 5642 break; 5643 case 4: 5644 hdmi_dsc->max_slices = 8; 5645 hdmi_dsc->clk_per_slice = 340; 5646 break; 5647 case 5: 5648 hdmi_dsc->max_slices = 8; 5649 hdmi_dsc->clk_per_slice = 400; 5650 break; 5651 case 6: 5652 hdmi_dsc->max_slices = 12; 5653 hdmi_dsc->clk_per_slice = 400; 5654 break; 5655 case 7: 5656 hdmi_dsc->max_slices = 16; 5657 hdmi_dsc->clk_per_slice = 400; 5658 break; 5659 case 0: 5660 default: 5661 hdmi_dsc->max_slices = 0; 5662 hdmi_dsc->clk_per_slice = 0; 5663 } 5664 } 5665 } 5666 5667 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 5668 } 5669 5670 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5671 const u8 *hdmi) 5672 { 5673 struct drm_display_info *info = &connector->display_info; 5674 unsigned int dc_bpc = 0; 5675 5676 /* HDMI supports at least 8 bpc */ 5677 info->bpc = 8; 5678 5679 if (cea_db_payload_len(hdmi) < 6) 5680 return; 5681 5682 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5683 dc_bpc = 10; 5684 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5685 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5686 connector->name); 5687 } 5688 5689 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5690 dc_bpc = 12; 5691 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5692 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5693 connector->name); 5694 } 5695 5696 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5697 dc_bpc = 16; 5698 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5699 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5700 connector->name); 5701 } 5702 5703 if (dc_bpc == 0) { 5704 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5705 connector->name); 5706 return; 5707 } 5708 5709 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5710 connector->name, dc_bpc); 5711 info->bpc = dc_bpc; 5712 5713 /* YCRCB444 is optional according to spec. */ 5714 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5715 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5716 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5717 connector->name); 5718 } 5719 5720 /* 5721 * Spec says that if any deep color mode is supported at all, 5722 * then deep color 36 bit must be supported. 5723 */ 5724 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5725 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5726 connector->name); 5727 } 5728 } 5729 5730 static void 5731 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5732 { 5733 struct drm_display_info *info = &connector->display_info; 5734 u8 len = cea_db_payload_len(db); 5735 5736 info->is_hdmi = true; 5737 5738 if (len >= 6) 5739 info->dvi_dual = db[6] & 1; 5740 if (len >= 7) 5741 info->max_tmds_clock = db[7] * 5000; 5742 5743 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5744 "max TMDS clock %d kHz\n", 5745 info->dvi_dual, 5746 info->max_tmds_clock); 5747 5748 drm_parse_hdmi_deep_color_info(connector, db); 5749 } 5750 5751 /* 5752 * See EDID extension for head-mounted and specialized monitors, specified at: 5753 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 5754 */ 5755 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 5756 const u8 *db) 5757 { 5758 struct drm_display_info *info = &connector->display_info; 5759 u8 version = db[4]; 5760 bool desktop_usage = db[5] & BIT(6); 5761 5762 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 5763 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 5764 info->non_desktop = true; 5765 5766 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", 5767 version, db[5]); 5768 } 5769 5770 static void drm_parse_cea_ext(struct drm_connector *connector, 5771 const struct drm_edid *drm_edid) 5772 { 5773 struct drm_display_info *info = &connector->display_info; 5774 struct drm_edid_iter edid_iter; 5775 const struct cea_db *db; 5776 struct cea_db_iter iter; 5777 const u8 *edid_ext; 5778 5779 drm_edid_iter_begin(drm_edid, &edid_iter); 5780 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5781 if (edid_ext[0] != CEA_EXT) 5782 continue; 5783 5784 if (!info->cea_rev) 5785 info->cea_rev = edid_ext[1]; 5786 5787 if (info->cea_rev != edid_ext[1]) 5788 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n", 5789 info->cea_rev, edid_ext[1]); 5790 5791 /* The existence of a CTA extension should imply RGB support */ 5792 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5793 if (edid_ext[3] & EDID_CEA_YCRCB444) 5794 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5795 if (edid_ext[3] & EDID_CEA_YCRCB422) 5796 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5797 } 5798 drm_edid_iter_end(&edid_iter); 5799 5800 cea_db_iter_edid_begin(drm_edid, &iter); 5801 cea_db_iter_for_each(db, &iter) { 5802 /* FIXME: convert parsers to use struct cea_db */ 5803 const u8 *data = (const u8 *)db; 5804 5805 if (cea_db_is_hdmi_vsdb(db)) 5806 drm_parse_hdmi_vsdb_video(connector, data); 5807 else if (cea_db_is_hdmi_forum_vsdb(db) || 5808 cea_db_is_hdmi_forum_scdb(db)) 5809 drm_parse_hdmi_forum_scds(connector, data); 5810 else if (cea_db_is_microsoft_vsdb(db)) 5811 drm_parse_microsoft_vsdb(connector, data); 5812 else if (cea_db_is_y420cmdb(db)) 5813 drm_parse_y420cmdb_bitmap(connector, data); 5814 else if (cea_db_is_vcdb(db)) 5815 drm_parse_vcdb(connector, data); 5816 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 5817 drm_parse_hdr_metadata_block(connector, data); 5818 } 5819 cea_db_iter_end(&iter); 5820 } 5821 5822 static 5823 void get_monitor_range(const struct detailed_timing *timing, 5824 void *info_monitor_range) 5825 { 5826 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5827 const struct detailed_non_pixel *data = &timing->data.other_data; 5828 const struct detailed_data_monitor_range *range = &data->data.range; 5829 5830 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 5831 return; 5832 5833 /* 5834 * Check for flag range limits only. If flag == 1 then 5835 * no additional timing information provided. 5836 * Default GTF, GTF Secondary curve and CVT are not 5837 * supported 5838 */ 5839 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5840 return; 5841 5842 monitor_range->min_vfreq = range->min_vfreq; 5843 monitor_range->max_vfreq = range->max_vfreq; 5844 } 5845 5846 static void drm_get_monitor_range(struct drm_connector *connector, 5847 const struct drm_edid *drm_edid) 5848 { 5849 struct drm_display_info *info = &connector->display_info; 5850 5851 if (!version_greater(drm_edid, 1, 1)) 5852 return; 5853 5854 drm_for_each_detailed_block(drm_edid, get_monitor_range, 5855 &info->monitor_range); 5856 5857 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5858 info->monitor_range.min_vfreq, 5859 info->monitor_range.max_vfreq); 5860 } 5861 5862 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 5863 const struct displayid_block *block) 5864 { 5865 struct displayid_vesa_vendor_specific_block *vesa = 5866 (struct displayid_vesa_vendor_specific_block *)block; 5867 struct drm_display_info *info = &connector->display_info; 5868 5869 if (block->num_bytes < 3) { 5870 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", 5871 block->num_bytes); 5872 return; 5873 } 5874 5875 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 5876 return; 5877 5878 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 5879 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); 5880 return; 5881 } 5882 5883 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 5884 default: 5885 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); 5886 fallthrough; 5887 case 0: 5888 info->mso_stream_count = 0; 5889 break; 5890 case 1: 5891 info->mso_stream_count = 2; /* 2 or 4 links */ 5892 break; 5893 case 2: 5894 info->mso_stream_count = 4; /* 4 links */ 5895 break; 5896 } 5897 5898 if (!info->mso_stream_count) { 5899 info->mso_pixel_overlap = 0; 5900 return; 5901 } 5902 5903 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 5904 if (info->mso_pixel_overlap > 8) { 5905 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", 5906 info->mso_pixel_overlap); 5907 info->mso_pixel_overlap = 8; 5908 } 5909 5910 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", 5911 info->mso_stream_count, info->mso_pixel_overlap); 5912 } 5913 5914 static void drm_update_mso(struct drm_connector *connector, 5915 const struct drm_edid *drm_edid) 5916 { 5917 const struct displayid_block *block; 5918 struct displayid_iter iter; 5919 5920 displayid_iter_edid_begin(drm_edid, &iter); 5921 displayid_iter_for_each(block, &iter) { 5922 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 5923 drm_parse_vesa_mso_data(connector, block); 5924 } 5925 displayid_iter_end(&iter); 5926 } 5927 5928 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5929 * all of the values which would have been set from EDID 5930 */ 5931 void 5932 drm_reset_display_info(struct drm_connector *connector) 5933 { 5934 struct drm_display_info *info = &connector->display_info; 5935 5936 info->width_mm = 0; 5937 info->height_mm = 0; 5938 5939 info->bpc = 0; 5940 info->color_formats = 0; 5941 info->cea_rev = 0; 5942 info->max_tmds_clock = 0; 5943 info->dvi_dual = false; 5944 info->is_hdmi = false; 5945 info->has_hdmi_infoframe = false; 5946 info->rgb_quant_range_selectable = false; 5947 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5948 5949 info->edid_hdmi_rgb444_dc_modes = 0; 5950 info->edid_hdmi_ycbcr444_dc_modes = 0; 5951 5952 info->non_desktop = 0; 5953 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5954 5955 info->mso_stream_count = 0; 5956 info->mso_pixel_overlap = 0; 5957 } 5958 5959 static u32 update_display_info(struct drm_connector *connector, 5960 const struct drm_edid *drm_edid) 5961 { 5962 struct drm_display_info *info = &connector->display_info; 5963 const struct edid *edid = drm_edid->edid; 5964 5965 u32 quirks = edid_get_quirks(drm_edid); 5966 5967 drm_reset_display_info(connector); 5968 5969 info->width_mm = edid->width_cm * 10; 5970 info->height_mm = edid->height_cm * 10; 5971 5972 drm_get_monitor_range(connector, drm_edid); 5973 5974 if (edid->revision < 3) 5975 goto out; 5976 5977 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5978 goto out; 5979 5980 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5981 drm_parse_cea_ext(connector, drm_edid); 5982 5983 /* 5984 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5985 * 5986 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5987 * tells us to assume 8 bpc color depth if the EDID doesn't have 5988 * extensions which tell otherwise. 5989 */ 5990 if (info->bpc == 0 && edid->revision == 3 && 5991 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5992 info->bpc = 8; 5993 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5994 connector->name, info->bpc); 5995 } 5996 5997 /* Only defined for 1.4 with digital displays */ 5998 if (edid->revision < 4) 5999 goto out; 6000 6001 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6002 case DRM_EDID_DIGITAL_DEPTH_6: 6003 info->bpc = 6; 6004 break; 6005 case DRM_EDID_DIGITAL_DEPTH_8: 6006 info->bpc = 8; 6007 break; 6008 case DRM_EDID_DIGITAL_DEPTH_10: 6009 info->bpc = 10; 6010 break; 6011 case DRM_EDID_DIGITAL_DEPTH_12: 6012 info->bpc = 12; 6013 break; 6014 case DRM_EDID_DIGITAL_DEPTH_14: 6015 info->bpc = 14; 6016 break; 6017 case DRM_EDID_DIGITAL_DEPTH_16: 6018 info->bpc = 16; 6019 break; 6020 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6021 default: 6022 info->bpc = 0; 6023 break; 6024 } 6025 6026 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6027 connector->name, info->bpc); 6028 6029 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6030 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6031 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6032 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6033 6034 drm_update_mso(connector, drm_edid); 6035 6036 out: 6037 if (quirks & EDID_QUIRK_NON_DESKTOP) { 6038 drm_dbg_kms(connector->dev, "Non-desktop display%s\n", 6039 info->non_desktop ? " (redundant quirk)" : ""); 6040 info->non_desktop = true; 6041 } 6042 6043 return quirks; 6044 } 6045 6046 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 6047 { 6048 struct drm_edid drm_edid; 6049 6050 return update_display_info(connector, 6051 drm_edid_legacy_init(&drm_edid, edid)); 6052 } 6053 6054 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6055 struct displayid_detailed_timings_1 *timings, 6056 bool type_7) 6057 { 6058 struct drm_display_mode *mode; 6059 unsigned pixel_clock = (timings->pixel_clock[0] | 6060 (timings->pixel_clock[1] << 8) | 6061 (timings->pixel_clock[2] << 16)) + 1; 6062 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6063 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6064 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6065 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6066 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6067 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6068 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6069 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6070 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6071 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6072 6073 mode = drm_mode_create(dev); 6074 if (!mode) 6075 return NULL; 6076 6077 /* resolution is kHz for type VII, and 10 kHz for type I */ 6078 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6079 mode->hdisplay = hactive; 6080 mode->hsync_start = mode->hdisplay + hsync; 6081 mode->hsync_end = mode->hsync_start + hsync_width; 6082 mode->htotal = mode->hdisplay + hblank; 6083 6084 mode->vdisplay = vactive; 6085 mode->vsync_start = mode->vdisplay + vsync; 6086 mode->vsync_end = mode->vsync_start + vsync_width; 6087 mode->vtotal = mode->vdisplay + vblank; 6088 6089 mode->flags = 0; 6090 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6091 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6092 mode->type = DRM_MODE_TYPE_DRIVER; 6093 6094 if (timings->flags & 0x80) 6095 mode->type |= DRM_MODE_TYPE_PREFERRED; 6096 drm_mode_set_name(mode); 6097 6098 return mode; 6099 } 6100 6101 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6102 const struct displayid_block *block) 6103 { 6104 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6105 int i; 6106 int num_timings; 6107 struct drm_display_mode *newmode; 6108 int num_modes = 0; 6109 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6110 /* blocks must be multiple of 20 bytes length */ 6111 if (block->num_bytes % 20) 6112 return 0; 6113 6114 num_timings = block->num_bytes / 20; 6115 for (i = 0; i < num_timings; i++) { 6116 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6117 6118 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6119 if (!newmode) 6120 continue; 6121 6122 drm_mode_probed_add(connector, newmode); 6123 num_modes++; 6124 } 6125 return num_modes; 6126 } 6127 6128 static int add_displayid_detailed_modes(struct drm_connector *connector, 6129 const struct drm_edid *drm_edid) 6130 { 6131 const struct displayid_block *block; 6132 struct displayid_iter iter; 6133 int num_modes = 0; 6134 6135 displayid_iter_edid_begin(drm_edid, &iter); 6136 displayid_iter_for_each(block, &iter) { 6137 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6138 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6139 num_modes += add_displayid_detailed_1_modes(connector, block); 6140 } 6141 displayid_iter_end(&iter); 6142 6143 return num_modes; 6144 } 6145 6146 static int drm_edid_connector_update(struct drm_connector *connector, 6147 const struct drm_edid *drm_edid) 6148 { 6149 int num_modes = 0; 6150 u32 quirks; 6151 6152 if (!drm_edid) { 6153 drm_reset_display_info(connector); 6154 clear_eld(connector); 6155 return 0; 6156 } 6157 6158 /* 6159 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 6160 * To avoid multiple parsing of same block, lets parse that map 6161 * from sink info, before parsing CEA modes. 6162 */ 6163 quirks = update_display_info(connector, drm_edid); 6164 6165 /* Depends on info->cea_rev set by update_display_info() above */ 6166 drm_edid_to_eld(connector, drm_edid); 6167 6168 /* 6169 * EDID spec says modes should be preferred in this order: 6170 * - preferred detailed mode 6171 * - other detailed modes from base block 6172 * - detailed modes from extension blocks 6173 * - CVT 3-byte code modes 6174 * - standard timing codes 6175 * - established timing codes 6176 * - modes inferred from GTF or CVT range information 6177 * 6178 * We get this pretty much right. 6179 * 6180 * XXX order for additional mode types in extension blocks? 6181 */ 6182 num_modes += add_detailed_modes(connector, drm_edid, quirks); 6183 num_modes += add_cvt_modes(connector, drm_edid); 6184 num_modes += add_standard_modes(connector, drm_edid); 6185 num_modes += add_established_modes(connector, drm_edid); 6186 num_modes += add_cea_modes(connector, drm_edid); 6187 num_modes += add_alternate_cea_modes(connector, drm_edid); 6188 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6189 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 6190 num_modes += add_inferred_modes(connector, drm_edid); 6191 6192 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6193 edid_fixup_preferred(connector, quirks); 6194 6195 if (quirks & EDID_QUIRK_FORCE_6BPC) 6196 connector->display_info.bpc = 6; 6197 6198 if (quirks & EDID_QUIRK_FORCE_8BPC) 6199 connector->display_info.bpc = 8; 6200 6201 if (quirks & EDID_QUIRK_FORCE_10BPC) 6202 connector->display_info.bpc = 10; 6203 6204 if (quirks & EDID_QUIRK_FORCE_12BPC) 6205 connector->display_info.bpc = 12; 6206 6207 return num_modes; 6208 } 6209 6210 /** 6211 * drm_add_edid_modes - add modes from EDID data, if available 6212 * @connector: connector we're probing 6213 * @edid: EDID data 6214 * 6215 * Add the specified modes to the connector's mode list. Also fills out the 6216 * &drm_display_info structure and ELD in @connector with any information which 6217 * can be derived from the edid. 6218 * 6219 * Return: The number of modes added or 0 if we couldn't find any. 6220 */ 6221 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6222 { 6223 struct drm_edid drm_edid; 6224 6225 if (edid && !drm_edid_is_valid(edid)) { 6226 drm_warn(connector->dev, "%s: EDID invalid.\n", 6227 connector->name); 6228 edid = NULL; 6229 } 6230 6231 return drm_edid_connector_update(connector, 6232 drm_edid_legacy_init(&drm_edid, edid)); 6233 } 6234 EXPORT_SYMBOL(drm_add_edid_modes); 6235 6236 /** 6237 * drm_add_modes_noedid - add modes for the connectors without EDID 6238 * @connector: connector we're probing 6239 * @hdisplay: the horizontal display limit 6240 * @vdisplay: the vertical display limit 6241 * 6242 * Add the specified modes to the connector's mode list. Only when the 6243 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6244 * 6245 * Return: The number of modes added or 0 if we couldn't find any. 6246 */ 6247 int drm_add_modes_noedid(struct drm_connector *connector, 6248 int hdisplay, int vdisplay) 6249 { 6250 int i, count, num_modes = 0; 6251 struct drm_display_mode *mode; 6252 struct drm_device *dev = connector->dev; 6253 6254 count = ARRAY_SIZE(drm_dmt_modes); 6255 if (hdisplay < 0) 6256 hdisplay = 0; 6257 if (vdisplay < 0) 6258 vdisplay = 0; 6259 6260 for (i = 0; i < count; i++) { 6261 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6262 6263 if (hdisplay && vdisplay) { 6264 /* 6265 * Only when two are valid, they will be used to check 6266 * whether the mode should be added to the mode list of 6267 * the connector. 6268 */ 6269 if (ptr->hdisplay > hdisplay || 6270 ptr->vdisplay > vdisplay) 6271 continue; 6272 } 6273 if (drm_mode_vrefresh(ptr) > 61) 6274 continue; 6275 mode = drm_mode_duplicate(dev, ptr); 6276 if (mode) { 6277 drm_mode_probed_add(connector, mode); 6278 num_modes++; 6279 } 6280 } 6281 return num_modes; 6282 } 6283 EXPORT_SYMBOL(drm_add_modes_noedid); 6284 6285 /** 6286 * drm_set_preferred_mode - Sets the preferred mode of a connector 6287 * @connector: connector whose mode list should be processed 6288 * @hpref: horizontal resolution of preferred mode 6289 * @vpref: vertical resolution of preferred mode 6290 * 6291 * Marks a mode as preferred if it matches the resolution specified by @hpref 6292 * and @vpref. 6293 */ 6294 void drm_set_preferred_mode(struct drm_connector *connector, 6295 int hpref, int vpref) 6296 { 6297 struct drm_display_mode *mode; 6298 6299 list_for_each_entry(mode, &connector->probed_modes, head) { 6300 if (mode->hdisplay == hpref && 6301 mode->vdisplay == vpref) 6302 mode->type |= DRM_MODE_TYPE_PREFERRED; 6303 } 6304 } 6305 EXPORT_SYMBOL(drm_set_preferred_mode); 6306 6307 static bool is_hdmi2_sink(const struct drm_connector *connector) 6308 { 6309 /* 6310 * FIXME: sil-sii8620 doesn't have a connector around when 6311 * we need one, so we have to be prepared for a NULL connector. 6312 */ 6313 if (!connector) 6314 return true; 6315 6316 return connector->display_info.hdmi.scdc.supported || 6317 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6318 } 6319 6320 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6321 const struct drm_display_mode *mode) 6322 { 6323 bool has_hdmi_infoframe = connector ? 6324 connector->display_info.has_hdmi_infoframe : false; 6325 6326 if (!has_hdmi_infoframe) 6327 return 0; 6328 6329 /* No HDMI VIC when signalling 3D video format */ 6330 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 6331 return 0; 6332 6333 return drm_match_hdmi_mode(mode); 6334 } 6335 6336 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 6337 const struct drm_display_mode *mode) 6338 { 6339 u8 vic; 6340 6341 /* 6342 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 6343 * we should send its VIC in vendor infoframes, else send the 6344 * VIC in AVI infoframes. Lets check if this mode is present in 6345 * HDMI 1.4b 4K modes 6346 */ 6347 if (drm_mode_hdmi_vic(connector, mode)) 6348 return 0; 6349 6350 vic = drm_match_cea_mode(mode); 6351 6352 /* 6353 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 6354 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 6355 * have to make sure we dont break HDMI 1.4 sinks. 6356 */ 6357 if (!is_hdmi2_sink(connector) && vic > 64) 6358 return 0; 6359 6360 return vic; 6361 } 6362 6363 /** 6364 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 6365 * data from a DRM display mode 6366 * @frame: HDMI AVI infoframe 6367 * @connector: the connector 6368 * @mode: DRM display mode 6369 * 6370 * Return: 0 on success or a negative error code on failure. 6371 */ 6372 int 6373 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 6374 const struct drm_connector *connector, 6375 const struct drm_display_mode *mode) 6376 { 6377 enum hdmi_picture_aspect picture_aspect; 6378 u8 vic, hdmi_vic; 6379 6380 if (!frame || !mode) 6381 return -EINVAL; 6382 6383 hdmi_avi_infoframe_init(frame); 6384 6385 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 6386 frame->pixel_repeat = 1; 6387 6388 vic = drm_mode_cea_vic(connector, mode); 6389 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 6390 6391 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6392 6393 /* 6394 * As some drivers don't support atomic, we can't use connector state. 6395 * So just initialize the frame with default values, just the same way 6396 * as it's done with other properties here. 6397 */ 6398 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 6399 frame->itc = 0; 6400 6401 /* 6402 * Populate picture aspect ratio from either 6403 * user input (if specified) or from the CEA/HDMI mode lists. 6404 */ 6405 picture_aspect = mode->picture_aspect_ratio; 6406 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 6407 if (vic) 6408 picture_aspect = drm_get_cea_aspect_ratio(vic); 6409 else if (hdmi_vic) 6410 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 6411 } 6412 6413 /* 6414 * The infoframe can't convey anything but none, 4:3 6415 * and 16:9, so if the user has asked for anything else 6416 * we can only satisfy it by specifying the right VIC. 6417 */ 6418 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 6419 if (vic) { 6420 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 6421 return -EINVAL; 6422 } else if (hdmi_vic) { 6423 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 6424 return -EINVAL; 6425 } else { 6426 return -EINVAL; 6427 } 6428 6429 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6430 } 6431 6432 frame->video_code = vic; 6433 frame->picture_aspect = picture_aspect; 6434 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 6435 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 6436 6437 return 0; 6438 } 6439 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 6440 6441 /** 6442 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 6443 * quantization range information 6444 * @frame: HDMI AVI infoframe 6445 * @connector: the connector 6446 * @mode: DRM display mode 6447 * @rgb_quant_range: RGB quantization range (Q) 6448 */ 6449 void 6450 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6451 const struct drm_connector *connector, 6452 const struct drm_display_mode *mode, 6453 enum hdmi_quantization_range rgb_quant_range) 6454 { 6455 const struct drm_display_info *info = &connector->display_info; 6456 6457 /* 6458 * CEA-861: 6459 * "A Source shall not send a non-zero Q value that does not correspond 6460 * to the default RGB Quantization Range for the transmitted Picture 6461 * unless the Sink indicates support for the Q bit in a Video 6462 * Capabilities Data Block." 6463 * 6464 * HDMI 2.0 recommends sending non-zero Q when it does match the 6465 * default RGB quantization range for the mode, even when QS=0. 6466 */ 6467 if (info->rgb_quant_range_selectable || 6468 rgb_quant_range == drm_default_rgb_quant_range(mode)) 6469 frame->quantization_range = rgb_quant_range; 6470 else 6471 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 6472 6473 /* 6474 * CEA-861-F: 6475 * "When transmitting any RGB colorimetry, the Source should set the 6476 * YQ-field to match the RGB Quantization Range being transmitted 6477 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 6478 * set YQ=1) and the Sink shall ignore the YQ-field." 6479 * 6480 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 6481 * by non-zero YQ when receiving RGB. There doesn't seem to be any 6482 * good way to tell which version of CEA-861 the sink supports, so 6483 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 6484 * on on CEA-861-F. 6485 */ 6486 if (!is_hdmi2_sink(connector) || 6487 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 6488 frame->ycc_quantization_range = 6489 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 6490 else 6491 frame->ycc_quantization_range = 6492 HDMI_YCC_QUANTIZATION_RANGE_FULL; 6493 } 6494 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 6495 6496 static enum hdmi_3d_structure 6497 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 6498 { 6499 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 6500 6501 switch (layout) { 6502 case DRM_MODE_FLAG_3D_FRAME_PACKING: 6503 return HDMI_3D_STRUCTURE_FRAME_PACKING; 6504 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 6505 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 6506 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 6507 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 6508 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 6509 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 6510 case DRM_MODE_FLAG_3D_L_DEPTH: 6511 return HDMI_3D_STRUCTURE_L_DEPTH; 6512 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 6513 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 6514 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 6515 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 6516 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 6517 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 6518 default: 6519 return HDMI_3D_STRUCTURE_INVALID; 6520 } 6521 } 6522 6523 /** 6524 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 6525 * data from a DRM display mode 6526 * @frame: HDMI vendor infoframe 6527 * @connector: the connector 6528 * @mode: DRM display mode 6529 * 6530 * Note that there's is a need to send HDMI vendor infoframes only when using a 6531 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 6532 * function will return -EINVAL, error that can be safely ignored. 6533 * 6534 * Return: 0 on success or a negative error code on failure. 6535 */ 6536 int 6537 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 6538 const struct drm_connector *connector, 6539 const struct drm_display_mode *mode) 6540 { 6541 /* 6542 * FIXME: sil-sii8620 doesn't have a connector around when 6543 * we need one, so we have to be prepared for a NULL connector. 6544 */ 6545 bool has_hdmi_infoframe = connector ? 6546 connector->display_info.has_hdmi_infoframe : false; 6547 int err; 6548 6549 if (!frame || !mode) 6550 return -EINVAL; 6551 6552 if (!has_hdmi_infoframe) 6553 return -EINVAL; 6554 6555 err = hdmi_vendor_infoframe_init(frame); 6556 if (err < 0) 6557 return err; 6558 6559 /* 6560 * Even if it's not absolutely necessary to send the infoframe 6561 * (ie.vic==0 and s3d_struct==0) we will still send it if we 6562 * know that the sink can handle it. This is based on a 6563 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 6564 * have trouble realizing that they should switch from 3D to 2D 6565 * mode if the source simply stops sending the infoframe when 6566 * it wants to switch from 3D to 2D. 6567 */ 6568 frame->vic = drm_mode_hdmi_vic(connector, mode); 6569 frame->s3d_struct = s3d_structure_from_display_mode(mode); 6570 6571 return 0; 6572 } 6573 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 6574 6575 static void drm_parse_tiled_block(struct drm_connector *connector, 6576 const struct displayid_block *block) 6577 { 6578 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6579 u16 w, h; 6580 u8 tile_v_loc, tile_h_loc; 6581 u8 num_v_tile, num_h_tile; 6582 struct drm_tile_group *tg; 6583 6584 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6585 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6586 6587 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6588 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6589 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6590 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6591 6592 connector->has_tile = true; 6593 if (tile->tile_cap & 0x80) 6594 connector->tile_is_single_monitor = true; 6595 6596 connector->num_h_tile = num_h_tile + 1; 6597 connector->num_v_tile = num_v_tile + 1; 6598 connector->tile_h_loc = tile_h_loc; 6599 connector->tile_v_loc = tile_v_loc; 6600 connector->tile_h_size = w + 1; 6601 connector->tile_v_size = h + 1; 6602 6603 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6604 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6605 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6606 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6607 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6608 6609 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6610 if (!tg) 6611 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6612 if (!tg) 6613 return; 6614 6615 if (connector->tile_group != tg) { 6616 /* if we haven't got a pointer, 6617 take the reference, drop ref to old tile group */ 6618 if (connector->tile_group) 6619 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6620 connector->tile_group = tg; 6621 } else { 6622 /* if same tile group, then release the ref we just took. */ 6623 drm_mode_put_tile_group(connector->dev, tg); 6624 } 6625 } 6626 6627 static void _drm_update_tile_info(struct drm_connector *connector, 6628 const struct drm_edid *drm_edid) 6629 { 6630 const struct displayid_block *block; 6631 struct displayid_iter iter; 6632 6633 connector->has_tile = false; 6634 6635 displayid_iter_edid_begin(drm_edid, &iter); 6636 displayid_iter_for_each(block, &iter) { 6637 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6638 drm_parse_tiled_block(connector, block); 6639 } 6640 displayid_iter_end(&iter); 6641 6642 if (!connector->has_tile && connector->tile_group) { 6643 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6644 connector->tile_group = NULL; 6645 } 6646 } 6647 6648 void drm_update_tile_info(struct drm_connector *connector, 6649 const struct edid *edid) 6650 { 6651 struct drm_edid drm_edid; 6652 6653 _drm_update_tile_info(connector, drm_edid_legacy_init(&drm_edid, edid)); 6654 } 6655