1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <drm/drmP.h> 36 #include <drm/drm_edid.h> 37 38 #define version_greater(edid, maj, min) \ 39 (((edid)->version > (maj)) || \ 40 ((edid)->version == (maj) && (edid)->revision > (min))) 41 42 #define EDID_EST_TIMINGS 16 43 #define EDID_STD_TIMINGS 8 44 #define EDID_DETAILED_TIMINGS 4 45 46 /* 47 * EDID blocks out in the wild have a variety of bugs, try to collect 48 * them here (note that userspace may work around broken monitors first, 49 * but fixes should make their way here so that the kernel "just works" 50 * on as many displays as possible). 51 */ 52 53 /* First detailed mode wrong, use largest 60Hz mode */ 54 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 55 /* Reported 135MHz pixel clock is too high, needs adjustment */ 56 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 57 /* Prefer the largest mode at 75 Hz */ 58 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 59 /* Detail timing is in cm not mm */ 60 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 61 /* Detailed timing descriptors have bogus size values, so just take the 62 * maximum size and use that. 63 */ 64 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 65 /* Monitor forgot to set the first detailed is preferred bit. */ 66 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 67 /* use +hsync +vsync for detailed mode */ 68 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 69 /* Force reduced-blanking timings for detailed modes */ 70 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 71 72 struct detailed_mode_closure { 73 struct drm_connector *connector; 74 struct edid *edid; 75 bool preferred; 76 u32 quirks; 77 int modes; 78 }; 79 80 #define LEVEL_DMT 0 81 #define LEVEL_GTF 1 82 #define LEVEL_GTF2 2 83 #define LEVEL_CVT 3 84 85 static struct edid_quirk { 86 char vendor[4]; 87 int product_id; 88 u32 quirks; 89 } edid_quirk_list[] = { 90 /* Acer AL1706 */ 91 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 92 /* Acer F51 */ 93 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Unknown Acer */ 95 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 96 97 /* Belinea 10 15 55 */ 98 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 99 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 100 101 /* Envision Peripherals, Inc. EN-7100e */ 102 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 103 /* Envision EN2028 */ 104 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Funai Electronics PM36B */ 107 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 108 EDID_QUIRK_DETAILED_IN_CM }, 109 110 /* LG Philips LCD LP154W01-A5 */ 111 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 112 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 113 114 /* Philips 107p5 CRT */ 115 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 116 117 /* Proview AY765C */ 118 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 119 120 /* Samsung SyncMaster 205BW. Note: irony */ 121 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 122 /* Samsung SyncMaster 22[5-6]BW */ 123 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 124 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 125 126 /* ViewSonic VA2026w */ 127 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 128 }; 129 130 /* 131 * Autogenerated from the DMT spec. 132 * This table is copied from xfree86/modes/xf86EdidModes.c. 133 */ 134 static const struct drm_display_mode drm_dmt_modes[] = { 135 /* 640x350@85Hz */ 136 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 137 736, 832, 0, 350, 382, 385, 445, 0, 138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 139 /* 640x400@85Hz */ 140 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 141 736, 832, 0, 400, 401, 404, 445, 0, 142 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 143 /* 720x400@85Hz */ 144 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 145 828, 936, 0, 400, 401, 404, 446, 0, 146 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 147 /* 640x480@60Hz */ 148 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 149 752, 800, 0, 480, 489, 492, 525, 0, 150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 151 /* 640x480@72Hz */ 152 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 153 704, 832, 0, 480, 489, 492, 520, 0, 154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 155 /* 640x480@75Hz */ 156 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 157 720, 840, 0, 480, 481, 484, 500, 0, 158 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 159 /* 640x480@85Hz */ 160 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 161 752, 832, 0, 480, 481, 484, 509, 0, 162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 163 /* 800x600@56Hz */ 164 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 165 896, 1024, 0, 600, 601, 603, 625, 0, 166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 167 /* 800x600@60Hz */ 168 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 169 968, 1056, 0, 600, 601, 605, 628, 0, 170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 171 /* 800x600@72Hz */ 172 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 173 976, 1040, 0, 600, 637, 643, 666, 0, 174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 175 /* 800x600@75Hz */ 176 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 177 896, 1056, 0, 600, 601, 604, 625, 0, 178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 179 /* 800x600@85Hz */ 180 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 181 896, 1048, 0, 600, 601, 604, 631, 0, 182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 183 /* 800x600@120Hz RB */ 184 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 185 880, 960, 0, 600, 603, 607, 636, 0, 186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 187 /* 848x480@60Hz */ 188 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 189 976, 1088, 0, 480, 486, 494, 517, 0, 190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 191 /* 1024x768@43Hz, interlace */ 192 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 193 1208, 1264, 0, 768, 768, 772, 817, 0, 194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 195 DRM_MODE_FLAG_INTERLACE) }, 196 /* 1024x768@60Hz */ 197 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 198 1184, 1344, 0, 768, 771, 777, 806, 0, 199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 200 /* 1024x768@70Hz */ 201 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 202 1184, 1328, 0, 768, 771, 777, 806, 0, 203 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 204 /* 1024x768@75Hz */ 205 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 206 1136, 1312, 0, 768, 769, 772, 800, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 1024x768@85Hz */ 209 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 210 1168, 1376, 0, 768, 769, 772, 808, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 212 /* 1024x768@120Hz RB */ 213 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 214 1104, 1184, 0, 768, 771, 775, 813, 0, 215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 216 /* 1152x864@75Hz */ 217 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 218 1344, 1600, 0, 864, 865, 868, 900, 0, 219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 220 /* 1280x768@60Hz RB */ 221 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 222 1360, 1440, 0, 768, 771, 778, 790, 0, 223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 224 /* 1280x768@60Hz */ 225 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 226 1472, 1664, 0, 768, 771, 778, 798, 0, 227 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 228 /* 1280x768@75Hz */ 229 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 230 1488, 1696, 0, 768, 771, 778, 805, 0, 231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 232 /* 1280x768@85Hz */ 233 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 234 1496, 1712, 0, 768, 771, 778, 809, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 236 /* 1280x768@120Hz RB */ 237 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 238 1360, 1440, 0, 768, 771, 778, 813, 0, 239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 240 /* 1280x800@60Hz RB */ 241 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 242 1360, 1440, 0, 800, 803, 809, 823, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 1280x800@60Hz */ 245 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 246 1480, 1680, 0, 800, 803, 809, 831, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 1280x800@75Hz */ 249 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 250 1488, 1696, 0, 800, 803, 809, 838, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 1280x800@85Hz */ 253 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 254 1496, 1712, 0, 800, 803, 809, 843, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 1280x800@120Hz RB */ 257 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 258 1360, 1440, 0, 800, 803, 809, 847, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 1280x960@60Hz */ 261 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 262 1488, 1800, 0, 960, 961, 964, 1000, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 1280x960@85Hz */ 265 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 266 1504, 1728, 0, 960, 961, 964, 1011, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 1280x960@120Hz RB */ 269 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 270 1360, 1440, 0, 960, 963, 967, 1017, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 1280x1024@60Hz */ 273 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 274 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 1280x1024@75Hz */ 277 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 278 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 1280x1024@85Hz */ 281 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 282 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 1280x1024@120Hz RB */ 285 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 286 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 288 /* 1360x768@60Hz */ 289 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 290 1536, 1792, 0, 768, 771, 777, 795, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 1360x768@120Hz RB */ 293 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 294 1440, 1520, 0, 768, 771, 776, 813, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 1400x1050@60Hz RB */ 297 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 298 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 300 /* 1400x1050@60Hz */ 301 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 302 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 303 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 1400x1050@75Hz */ 305 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 306 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 307 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 308 /* 1400x1050@85Hz */ 309 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 310 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 312 /* 1400x1050@120Hz RB */ 313 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 314 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 316 /* 1440x900@60Hz RB */ 317 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 318 1520, 1600, 0, 900, 903, 909, 926, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 320 /* 1440x900@60Hz */ 321 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 322 1672, 1904, 0, 900, 903, 909, 934, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 1440x900@75Hz */ 325 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 326 1688, 1936, 0, 900, 903, 909, 942, 0, 327 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 1440x900@85Hz */ 329 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 330 1696, 1952, 0, 900, 903, 909, 948, 0, 331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 332 /* 1440x900@120Hz RB */ 333 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 334 1520, 1600, 0, 900, 903, 909, 953, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 336 /* 1600x1200@60Hz */ 337 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 338 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 1600x1200@65Hz */ 341 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 342 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 344 /* 1600x1200@70Hz */ 345 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 346 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 1600x1200@75Hz */ 349 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 350 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 1600x1200@85Hz */ 353 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 354 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 1600x1200@120Hz RB */ 357 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 358 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 1680x1050@60Hz RB */ 361 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 362 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 364 /* 1680x1050@60Hz */ 365 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 366 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 1680x1050@75Hz */ 369 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 370 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 1680x1050@85Hz */ 373 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 374 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 1680x1050@120Hz RB */ 377 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 378 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 380 /* 1792x1344@60Hz */ 381 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 382 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 1792x1344@75Hz */ 385 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 386 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 1792x1344@120Hz RB */ 389 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 390 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 392 /* 1856x1392@60Hz */ 393 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 394 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 396 /* 1856x1392@75Hz */ 397 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 398 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, 399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 1856x1392@120Hz RB */ 401 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 402 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 404 /* 1920x1200@60Hz RB */ 405 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 406 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 408 /* 1920x1200@60Hz */ 409 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 410 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 1920x1200@75Hz */ 413 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 414 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 1920x1200@85Hz */ 417 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 418 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 1920x1200@120Hz RB */ 421 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 422 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 424 /* 1920x1440@60Hz */ 425 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 426 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 1920x1440@75Hz */ 429 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 430 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 1920x1440@120Hz RB */ 433 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 434 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 436 /* 2560x1600@60Hz RB */ 437 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 438 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 2560x1600@60Hz */ 441 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 442 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 444 /* 2560x1600@75HZ */ 445 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 446 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 2560x1600@85HZ */ 449 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 450 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 2560x1600@120Hz RB */ 453 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 454 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 456 }; 457 458 static const struct drm_display_mode edid_est_modes[] = { 459 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 460 968, 1056, 0, 600, 601, 605, 628, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 462 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 463 896, 1024, 0, 600, 601, 603, 625, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 465 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 466 720, 840, 0, 480, 481, 484, 500, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 468 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 469 704, 832, 0, 480, 489, 491, 520, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 471 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 472 768, 864, 0, 480, 483, 486, 525, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 474 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 475 752, 800, 0, 480, 490, 492, 525, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 477 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 478 846, 900, 0, 400, 421, 423, 449, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 480 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 481 846, 900, 0, 400, 412, 414, 449, 0, 482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 483 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 484 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 486 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 487 1136, 1312, 0, 768, 769, 772, 800, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 489 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 490 1184, 1328, 0, 768, 771, 777, 806, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 492 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 493 1184, 1344, 0, 768, 771, 777, 806, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 495 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 496 1208, 1264, 0, 768, 768, 776, 817, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 498 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 499 928, 1152, 0, 624, 625, 628, 667, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 501 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 502 896, 1056, 0, 600, 601, 604, 625, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 504 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 505 976, 1040, 0, 600, 637, 643, 666, 0, 506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 507 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 508 1344, 1600, 0, 864, 865, 868, 900, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 510 }; 511 512 struct minimode { 513 short w; 514 short h; 515 short r; 516 short rb; 517 }; 518 519 static const struct minimode est3_modes[] = { 520 /* byte 6 */ 521 { 640, 350, 85, 0 }, 522 { 640, 400, 85, 0 }, 523 { 720, 400, 85, 0 }, 524 { 640, 480, 85, 0 }, 525 { 848, 480, 60, 0 }, 526 { 800, 600, 85, 0 }, 527 { 1024, 768, 85, 0 }, 528 { 1152, 864, 75, 0 }, 529 /* byte 7 */ 530 { 1280, 768, 60, 1 }, 531 { 1280, 768, 60, 0 }, 532 { 1280, 768, 75, 0 }, 533 { 1280, 768, 85, 0 }, 534 { 1280, 960, 60, 0 }, 535 { 1280, 960, 85, 0 }, 536 { 1280, 1024, 60, 0 }, 537 { 1280, 1024, 85, 0 }, 538 /* byte 8 */ 539 { 1360, 768, 60, 0 }, 540 { 1440, 900, 60, 1 }, 541 { 1440, 900, 60, 0 }, 542 { 1440, 900, 75, 0 }, 543 { 1440, 900, 85, 0 }, 544 { 1400, 1050, 60, 1 }, 545 { 1400, 1050, 60, 0 }, 546 { 1400, 1050, 75, 0 }, 547 /* byte 9 */ 548 { 1400, 1050, 85, 0 }, 549 { 1680, 1050, 60, 1 }, 550 { 1680, 1050, 60, 0 }, 551 { 1680, 1050, 75, 0 }, 552 { 1680, 1050, 85, 0 }, 553 { 1600, 1200, 60, 0 }, 554 { 1600, 1200, 65, 0 }, 555 { 1600, 1200, 70, 0 }, 556 /* byte 10 */ 557 { 1600, 1200, 75, 0 }, 558 { 1600, 1200, 85, 0 }, 559 { 1792, 1344, 60, 0 }, 560 { 1792, 1344, 85, 0 }, 561 { 1856, 1392, 60, 0 }, 562 { 1856, 1392, 75, 0 }, 563 { 1920, 1200, 60, 1 }, 564 { 1920, 1200, 60, 0 }, 565 /* byte 11 */ 566 { 1920, 1200, 75, 0 }, 567 { 1920, 1200, 85, 0 }, 568 { 1920, 1440, 60, 0 }, 569 { 1920, 1440, 75, 0 }, 570 }; 571 572 static const struct minimode extra_modes[] = { 573 { 1024, 576, 60, 0 }, 574 { 1366, 768, 60, 0 }, 575 { 1600, 900, 60, 0 }, 576 { 1680, 945, 60, 0 }, 577 { 1920, 1080, 60, 0 }, 578 { 2048, 1152, 60, 0 }, 579 { 2048, 1536, 60, 0 }, 580 }; 581 582 /* 583 * Probably taken from CEA-861 spec. 584 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 585 */ 586 static const struct drm_display_mode edid_cea_modes[] = { 587 /* 1 - 640x480@60Hz */ 588 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 589 752, 800, 0, 480, 490, 492, 525, 0, 590 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 591 .vrefresh = 60, }, 592 /* 2 - 720x480@60Hz */ 593 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 594 798, 858, 0, 480, 489, 495, 525, 0, 595 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 596 .vrefresh = 60, }, 597 /* 3 - 720x480@60Hz */ 598 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 599 798, 858, 0, 480, 489, 495, 525, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 601 .vrefresh = 60, }, 602 /* 4 - 1280x720@60Hz */ 603 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 604 1430, 1650, 0, 720, 725, 730, 750, 0, 605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 606 .vrefresh = 60, }, 607 /* 5 - 1920x1080i@60Hz */ 608 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 609 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 611 DRM_MODE_FLAG_INTERLACE), 612 .vrefresh = 60, }, 613 /* 6 - 1440x480i@60Hz */ 614 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 615 1602, 1716, 0, 480, 488, 494, 525, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 617 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 618 .vrefresh = 60, }, 619 /* 7 - 1440x480i@60Hz */ 620 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 621 1602, 1716, 0, 480, 488, 494, 525, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 623 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 624 .vrefresh = 60, }, 625 /* 8 - 1440x240@60Hz */ 626 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 627 1602, 1716, 0, 240, 244, 247, 262, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 629 DRM_MODE_FLAG_DBLCLK), 630 .vrefresh = 60, }, 631 /* 9 - 1440x240@60Hz */ 632 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 633 1602, 1716, 0, 240, 244, 247, 262, 0, 634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 635 DRM_MODE_FLAG_DBLCLK), 636 .vrefresh = 60, }, 637 /* 10 - 2880x480i@60Hz */ 638 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 639 3204, 3432, 0, 480, 488, 494, 525, 0, 640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 641 DRM_MODE_FLAG_INTERLACE), 642 .vrefresh = 60, }, 643 /* 11 - 2880x480i@60Hz */ 644 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 645 3204, 3432, 0, 480, 488, 494, 525, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 647 DRM_MODE_FLAG_INTERLACE), 648 .vrefresh = 60, }, 649 /* 12 - 2880x240@60Hz */ 650 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 651 3204, 3432, 0, 240, 244, 247, 262, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 653 .vrefresh = 60, }, 654 /* 13 - 2880x240@60Hz */ 655 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 656 3204, 3432, 0, 240, 244, 247, 262, 0, 657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 658 .vrefresh = 60, }, 659 /* 14 - 1440x480@60Hz */ 660 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 661 1596, 1716, 0, 480, 489, 495, 525, 0, 662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 663 .vrefresh = 60, }, 664 /* 15 - 1440x480@60Hz */ 665 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 666 1596, 1716, 0, 480, 489, 495, 525, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 668 .vrefresh = 60, }, 669 /* 16 - 1920x1080@60Hz */ 670 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 671 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 60, }, 674 /* 17 - 720x576@50Hz */ 675 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 676 796, 864, 0, 576, 581, 586, 625, 0, 677 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 678 .vrefresh = 50, }, 679 /* 18 - 720x576@50Hz */ 680 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 681 796, 864, 0, 576, 581, 586, 625, 0, 682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 683 .vrefresh = 50, }, 684 /* 19 - 1280x720@50Hz */ 685 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 686 1760, 1980, 0, 720, 725, 730, 750, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 688 .vrefresh = 50, }, 689 /* 20 - 1920x1080i@50Hz */ 690 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 691 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 693 DRM_MODE_FLAG_INTERLACE), 694 .vrefresh = 50, }, 695 /* 21 - 1440x576i@50Hz */ 696 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 697 1590, 1728, 0, 576, 580, 586, 625, 0, 698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 699 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 700 .vrefresh = 50, }, 701 /* 22 - 1440x576i@50Hz */ 702 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 703 1590, 1728, 0, 576, 580, 586, 625, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 705 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 706 .vrefresh = 50, }, 707 /* 23 - 1440x288@50Hz */ 708 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 709 1590, 1728, 0, 288, 290, 293, 312, 0, 710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 711 DRM_MODE_FLAG_DBLCLK), 712 .vrefresh = 50, }, 713 /* 24 - 1440x288@50Hz */ 714 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 715 1590, 1728, 0, 288, 290, 293, 312, 0, 716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 717 DRM_MODE_FLAG_DBLCLK), 718 .vrefresh = 50, }, 719 /* 25 - 2880x576i@50Hz */ 720 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 721 3180, 3456, 0, 576, 580, 586, 625, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 723 DRM_MODE_FLAG_INTERLACE), 724 .vrefresh = 50, }, 725 /* 26 - 2880x576i@50Hz */ 726 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 727 3180, 3456, 0, 576, 580, 586, 625, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 729 DRM_MODE_FLAG_INTERLACE), 730 .vrefresh = 50, }, 731 /* 27 - 2880x288@50Hz */ 732 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 733 3180, 3456, 0, 288, 290, 293, 312, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 50, }, 736 /* 28 - 2880x288@50Hz */ 737 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 738 3180, 3456, 0, 288, 290, 293, 312, 0, 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 740 .vrefresh = 50, }, 741 /* 29 - 1440x576@50Hz */ 742 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 743 1592, 1728, 0, 576, 581, 586, 625, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .vrefresh = 50, }, 746 /* 30 - 1440x576@50Hz */ 747 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 748 1592, 1728, 0, 576, 581, 586, 625, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 750 .vrefresh = 50, }, 751 /* 31 - 1920x1080@50Hz */ 752 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 753 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 50, }, 756 /* 32 - 1920x1080@24Hz */ 757 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 758 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 760 .vrefresh = 24, }, 761 /* 33 - 1920x1080@25Hz */ 762 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 763 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 25, }, 766 /* 34 - 1920x1080@30Hz */ 767 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 768 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 770 .vrefresh = 30, }, 771 /* 35 - 2880x480@60Hz */ 772 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 773 3192, 3432, 0, 480, 489, 495, 525, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 775 .vrefresh = 60, }, 776 /* 36 - 2880x480@60Hz */ 777 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 778 3192, 3432, 0, 480, 489, 495, 525, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 780 .vrefresh = 60, }, 781 /* 37 - 2880x576@50Hz */ 782 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 783 3184, 3456, 0, 576, 581, 586, 625, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .vrefresh = 50, }, 786 /* 38 - 2880x576@50Hz */ 787 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 788 3184, 3456, 0, 576, 581, 586, 625, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .vrefresh = 50, }, 791 /* 39 - 1920x1080i@50Hz */ 792 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 793 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_INTERLACE), 796 .vrefresh = 50, }, 797 /* 40 - 1920x1080i@100Hz */ 798 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 799 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 801 DRM_MODE_FLAG_INTERLACE), 802 .vrefresh = 100, }, 803 /* 41 - 1280x720@100Hz */ 804 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 805 1760, 1980, 0, 720, 725, 730, 750, 0, 806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 807 .vrefresh = 100, }, 808 /* 42 - 720x576@100Hz */ 809 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 810 796, 864, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 100, }, 813 /* 43 - 720x576@100Hz */ 814 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 815 796, 864, 0, 576, 581, 586, 625, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 100, }, 818 /* 44 - 1440x576i@100Hz */ 819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 820 1590, 1728, 0, 576, 580, 586, 625, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 822 DRM_MODE_FLAG_DBLCLK), 823 .vrefresh = 100, }, 824 /* 45 - 1440x576i@100Hz */ 825 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 826 1590, 1728, 0, 576, 580, 586, 625, 0, 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 828 DRM_MODE_FLAG_DBLCLK), 829 .vrefresh = 100, }, 830 /* 46 - 1920x1080i@120Hz */ 831 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 832 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 834 DRM_MODE_FLAG_INTERLACE), 835 .vrefresh = 120, }, 836 /* 47 - 1280x720@120Hz */ 837 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 838 1430, 1650, 0, 720, 725, 730, 750, 0, 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 840 .vrefresh = 120, }, 841 /* 48 - 720x480@120Hz */ 842 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 843 798, 858, 0, 480, 489, 495, 525, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 845 .vrefresh = 120, }, 846 /* 49 - 720x480@120Hz */ 847 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 848 798, 858, 0, 480, 489, 495, 525, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 850 .vrefresh = 120, }, 851 /* 50 - 1440x480i@120Hz */ 852 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 853 1602, 1716, 0, 480, 488, 494, 525, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 856 .vrefresh = 120, }, 857 /* 51 - 1440x480i@120Hz */ 858 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 859 1602, 1716, 0, 480, 488, 494, 525, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 862 .vrefresh = 120, }, 863 /* 52 - 720x576@200Hz */ 864 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 865 796, 864, 0, 576, 581, 586, 625, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 200, }, 868 /* 53 - 720x576@200Hz */ 869 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 870 796, 864, 0, 576, 581, 586, 625, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .vrefresh = 200, }, 873 /* 54 - 1440x576i@200Hz */ 874 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 875 1590, 1728, 0, 576, 580, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 878 .vrefresh = 200, }, 879 /* 55 - 1440x576i@200Hz */ 880 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 881 1590, 1728, 0, 576, 580, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 883 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 884 .vrefresh = 200, }, 885 /* 56 - 720x480@240Hz */ 886 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 887 798, 858, 0, 480, 489, 495, 525, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 240, }, 890 /* 57 - 720x480@240Hz */ 891 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 892 798, 858, 0, 480, 489, 495, 525, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .vrefresh = 240, }, 895 /* 58 - 1440x480i@240 */ 896 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 897 1602, 1716, 0, 480, 488, 494, 525, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 900 .vrefresh = 240, }, 901 /* 59 - 1440x480i@240 */ 902 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 903 1602, 1716, 0, 480, 488, 494, 525, 0, 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 906 .vrefresh = 240, }, 907 /* 60 - 1280x720@24Hz */ 908 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 909 3080, 3300, 0, 720, 725, 730, 750, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 911 .vrefresh = 24, }, 912 /* 61 - 1280x720@25Hz */ 913 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 914 3740, 3960, 0, 720, 725, 730, 750, 0, 915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 916 .vrefresh = 25, }, 917 /* 62 - 1280x720@30Hz */ 918 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 919 3080, 3300, 0, 720, 725, 730, 750, 0, 920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 921 .vrefresh = 30, }, 922 /* 63 - 1920x1080@120Hz */ 923 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 924 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 926 .vrefresh = 120, }, 927 /* 64 - 1920x1080@100Hz */ 928 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 929 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 930 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 931 .vrefresh = 100, }, 932 }; 933 934 /*** DDC fetch and block validation ***/ 935 936 static const u8 edid_header[] = { 937 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 938 }; 939 940 /* 941 * Sanity check the header of the base EDID block. Return 8 if the header 942 * is perfect, down to 0 if it's totally wrong. 943 */ 944 int drm_edid_header_is_valid(const u8 *raw_edid) 945 { 946 int i, score = 0; 947 948 for (i = 0; i < sizeof(edid_header); i++) 949 if (raw_edid[i] == edid_header[i]) 950 score++; 951 952 return score; 953 } 954 EXPORT_SYMBOL(drm_edid_header_is_valid); 955 956 static int edid_fixup __read_mostly = 6; 957 module_param_named(edid_fixup, edid_fixup, int, 0400); 958 MODULE_PARM_DESC(edid_fixup, 959 "Minimum number of valid EDID header bytes (0-8, default 6)"); 960 961 /* 962 * Sanity check the EDID block (base or extension). Return 0 if the block 963 * doesn't check out, or 1 if it's valid. 964 */ 965 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) 966 { 967 int i; 968 u8 csum = 0; 969 struct edid *edid = (struct edid *)raw_edid; 970 971 if (edid_fixup > 8 || edid_fixup < 0) 972 edid_fixup = 6; 973 974 if (block == 0) { 975 int score = drm_edid_header_is_valid(raw_edid); 976 if (score == 8) ; 977 else if (score >= edid_fixup) { 978 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 979 memcpy(raw_edid, edid_header, sizeof(edid_header)); 980 } else { 981 goto bad; 982 } 983 } 984 985 for (i = 0; i < EDID_LENGTH; i++) 986 csum += raw_edid[i]; 987 if (csum) { 988 if (print_bad_edid) { 989 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 990 } 991 992 /* allow CEA to slide through, switches mangle this */ 993 if (raw_edid[0] != 0x02) 994 goto bad; 995 } 996 997 /* per-block-type checks */ 998 switch (raw_edid[0]) { 999 case 0: /* base */ 1000 if (edid->version != 1) { 1001 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1002 goto bad; 1003 } 1004 1005 if (edid->revision > 4) 1006 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1007 break; 1008 1009 default: 1010 break; 1011 } 1012 1013 return 1; 1014 1015 bad: 1016 if (raw_edid && print_bad_edid) { 1017 printk(KERN_ERR "Raw EDID:\n"); 1018 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1019 raw_edid, EDID_LENGTH, false); 1020 } 1021 return 0; 1022 } 1023 EXPORT_SYMBOL(drm_edid_block_valid); 1024 1025 /** 1026 * drm_edid_is_valid - sanity check EDID data 1027 * @edid: EDID data 1028 * 1029 * Sanity-check an entire EDID record (including extensions) 1030 */ 1031 bool drm_edid_is_valid(struct edid *edid) 1032 { 1033 int i; 1034 u8 *raw = (u8 *)edid; 1035 1036 if (!edid) 1037 return false; 1038 1039 for (i = 0; i <= edid->extensions; i++) 1040 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) 1041 return false; 1042 1043 return true; 1044 } 1045 EXPORT_SYMBOL(drm_edid_is_valid); 1046 1047 #define DDC_SEGMENT_ADDR 0x30 1048 /** 1049 * Get EDID information via I2C. 1050 * 1051 * \param adapter : i2c device adaptor 1052 * \param buf : EDID data buffer to be filled 1053 * \param len : EDID data buffer length 1054 * \return 0 on success or -1 on failure. 1055 * 1056 * Try to fetch EDID information by calling i2c driver function. 1057 */ 1058 static int 1059 drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, 1060 int block, int len) 1061 { 1062 unsigned char start = block * EDID_LENGTH; 1063 unsigned char segment = block >> 1; 1064 unsigned char xfers = segment ? 3 : 2; 1065 int ret, retries = 5; 1066 1067 /* The core i2c driver will automatically retry the transfer if the 1068 * adapter reports EAGAIN. However, we find that bit-banging transfers 1069 * are susceptible to errors under a heavily loaded machine and 1070 * generate spurious NAKs and timeouts. Retrying the transfer 1071 * of the individual block a few times seems to overcome this. 1072 */ 1073 do { 1074 struct i2c_msg msgs[] = { 1075 { 1076 .addr = DDC_SEGMENT_ADDR, 1077 .flags = 0, 1078 .len = 1, 1079 .buf = &segment, 1080 }, { 1081 .addr = DDC_ADDR, 1082 .flags = 0, 1083 .len = 1, 1084 .buf = &start, 1085 }, { 1086 .addr = DDC_ADDR, 1087 .flags = I2C_M_RD, 1088 .len = len, 1089 .buf = buf, 1090 } 1091 }; 1092 1093 /* 1094 * Avoid sending the segment addr to not upset non-compliant ddc 1095 * monitors. 1096 */ 1097 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1098 1099 if (ret == -ENXIO) { 1100 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1101 adapter->name); 1102 break; 1103 } 1104 } while (ret != xfers && --retries); 1105 1106 return ret == xfers ? 0 : -1; 1107 } 1108 1109 static bool drm_edid_is_zero(u8 *in_edid, int length) 1110 { 1111 if (memchr_inv(in_edid, 0, length)) 1112 return false; 1113 1114 return true; 1115 } 1116 1117 static u8 * 1118 drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 1119 { 1120 int i, j = 0, valid_extensions = 0; 1121 u8 *block, *new; 1122 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1123 1124 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1125 return NULL; 1126 1127 /* base block fetch */ 1128 for (i = 0; i < 4; i++) { 1129 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) 1130 goto out; 1131 if (drm_edid_block_valid(block, 0, print_bad_edid)) 1132 break; 1133 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1134 connector->null_edid_counter++; 1135 goto carp; 1136 } 1137 } 1138 if (i == 4) 1139 goto carp; 1140 1141 /* if there's no extensions, we're done */ 1142 if (block[0x7e] == 0) 1143 return block; 1144 1145 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1146 if (!new) 1147 goto out; 1148 block = new; 1149 1150 for (j = 1; j <= block[0x7e]; j++) { 1151 for (i = 0; i < 4; i++) { 1152 if (drm_do_probe_ddc_edid(adapter, 1153 block + (valid_extensions + 1) * EDID_LENGTH, 1154 j, EDID_LENGTH)) 1155 goto out; 1156 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { 1157 valid_extensions++; 1158 break; 1159 } 1160 } 1161 1162 if (i == 4 && print_bad_edid) { 1163 dev_warn(connector->dev->dev, 1164 "%s: Ignoring invalid EDID block %d.\n", 1165 drm_get_connector_name(connector), j); 1166 1167 connector->bad_edid_counter++; 1168 } 1169 } 1170 1171 if (valid_extensions != block[0x7e]) { 1172 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1173 block[0x7e] = valid_extensions; 1174 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1175 if (!new) 1176 goto out; 1177 block = new; 1178 } 1179 1180 return block; 1181 1182 carp: 1183 if (print_bad_edid) { 1184 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1185 drm_get_connector_name(connector), j); 1186 } 1187 connector->bad_edid_counter++; 1188 1189 out: 1190 kfree(block); 1191 return NULL; 1192 } 1193 1194 /** 1195 * Probe DDC presence. 1196 * 1197 * \param adapter : i2c device adaptor 1198 * \return 1 on success 1199 */ 1200 bool 1201 drm_probe_ddc(struct i2c_adapter *adapter) 1202 { 1203 unsigned char out; 1204 1205 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1206 } 1207 EXPORT_SYMBOL(drm_probe_ddc); 1208 1209 /** 1210 * drm_get_edid - get EDID data, if available 1211 * @connector: connector we're probing 1212 * @adapter: i2c adapter to use for DDC 1213 * 1214 * Poke the given i2c channel to grab EDID data if possible. If found, 1215 * attach it to the connector. 1216 * 1217 * Return edid data or NULL if we couldn't find any. 1218 */ 1219 struct edid *drm_get_edid(struct drm_connector *connector, 1220 struct i2c_adapter *adapter) 1221 { 1222 struct edid *edid = NULL; 1223 1224 if (drm_probe_ddc(adapter)) 1225 edid = (struct edid *)drm_do_get_edid(connector, adapter); 1226 1227 return edid; 1228 } 1229 EXPORT_SYMBOL(drm_get_edid); 1230 1231 /*** EDID parsing ***/ 1232 1233 /** 1234 * edid_vendor - match a string against EDID's obfuscated vendor field 1235 * @edid: EDID to match 1236 * @vendor: vendor string 1237 * 1238 * Returns true if @vendor is in @edid, false otherwise 1239 */ 1240 static bool edid_vendor(struct edid *edid, char *vendor) 1241 { 1242 char edid_vendor[3]; 1243 1244 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1245 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1246 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1247 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1248 1249 return !strncmp(edid_vendor, vendor, 3); 1250 } 1251 1252 /** 1253 * edid_get_quirks - return quirk flags for a given EDID 1254 * @edid: EDID to process 1255 * 1256 * This tells subsequent routines what fixes they need to apply. 1257 */ 1258 static u32 edid_get_quirks(struct edid *edid) 1259 { 1260 struct edid_quirk *quirk; 1261 int i; 1262 1263 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1264 quirk = &edid_quirk_list[i]; 1265 1266 if (edid_vendor(edid, quirk->vendor) && 1267 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1268 return quirk->quirks; 1269 } 1270 1271 return 0; 1272 } 1273 1274 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1275 #define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh)) 1276 1277 /** 1278 * edid_fixup_preferred - set preferred modes based on quirk list 1279 * @connector: has mode list to fix up 1280 * @quirks: quirks list 1281 * 1282 * Walk the mode list for @connector, clearing the preferred status 1283 * on existing modes and setting it anew for the right mode ala @quirks. 1284 */ 1285 static void edid_fixup_preferred(struct drm_connector *connector, 1286 u32 quirks) 1287 { 1288 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1289 int target_refresh = 0; 1290 1291 if (list_empty(&connector->probed_modes)) 1292 return; 1293 1294 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1295 target_refresh = 60; 1296 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1297 target_refresh = 75; 1298 1299 preferred_mode = list_first_entry(&connector->probed_modes, 1300 struct drm_display_mode, head); 1301 1302 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1303 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1304 1305 if (cur_mode == preferred_mode) 1306 continue; 1307 1308 /* Largest mode is preferred */ 1309 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1310 preferred_mode = cur_mode; 1311 1312 /* At a given size, try to get closest to target refresh */ 1313 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1314 MODE_REFRESH_DIFF(cur_mode, target_refresh) < 1315 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) { 1316 preferred_mode = cur_mode; 1317 } 1318 } 1319 1320 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1321 } 1322 1323 static bool 1324 mode_is_rb(const struct drm_display_mode *mode) 1325 { 1326 return (mode->htotal - mode->hdisplay == 160) && 1327 (mode->hsync_end - mode->hdisplay == 80) && 1328 (mode->hsync_end - mode->hsync_start == 32) && 1329 (mode->vsync_start - mode->vdisplay == 3); 1330 } 1331 1332 /* 1333 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1334 * @dev: Device to duplicate against 1335 * @hsize: Mode width 1336 * @vsize: Mode height 1337 * @fresh: Mode refresh rate 1338 * @rb: Mode reduced-blanking-ness 1339 * 1340 * Walk the DMT mode list looking for a match for the given parameters. 1341 * Return a newly allocated copy of the mode, or NULL if not found. 1342 */ 1343 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1344 int hsize, int vsize, int fresh, 1345 bool rb) 1346 { 1347 int i; 1348 1349 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1350 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1351 if (hsize != ptr->hdisplay) 1352 continue; 1353 if (vsize != ptr->vdisplay) 1354 continue; 1355 if (fresh != drm_mode_vrefresh(ptr)) 1356 continue; 1357 if (rb != mode_is_rb(ptr)) 1358 continue; 1359 1360 return drm_mode_duplicate(dev, ptr); 1361 } 1362 1363 return NULL; 1364 } 1365 EXPORT_SYMBOL(drm_mode_find_dmt); 1366 1367 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1368 1369 static void 1370 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1371 { 1372 int i, n = 0; 1373 u8 d = ext[0x02]; 1374 u8 *det_base = ext + d; 1375 1376 n = (127 - d) / 18; 1377 for (i = 0; i < n; i++) 1378 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1379 } 1380 1381 static void 1382 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1383 { 1384 unsigned int i, n = min((int)ext[0x02], 6); 1385 u8 *det_base = ext + 5; 1386 1387 if (ext[0x01] != 1) 1388 return; /* unknown version */ 1389 1390 for (i = 0; i < n; i++) 1391 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1392 } 1393 1394 static void 1395 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1396 { 1397 int i; 1398 struct edid *edid = (struct edid *)raw_edid; 1399 1400 if (edid == NULL) 1401 return; 1402 1403 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1404 cb(&(edid->detailed_timings[i]), closure); 1405 1406 for (i = 1; i <= raw_edid[0x7e]; i++) { 1407 u8 *ext = raw_edid + (i * EDID_LENGTH); 1408 switch (*ext) { 1409 case CEA_EXT: 1410 cea_for_each_detailed_block(ext, cb, closure); 1411 break; 1412 case VTB_EXT: 1413 vtb_for_each_detailed_block(ext, cb, closure); 1414 break; 1415 default: 1416 break; 1417 } 1418 } 1419 } 1420 1421 static void 1422 is_rb(struct detailed_timing *t, void *data) 1423 { 1424 u8 *r = (u8 *)t; 1425 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1426 if (r[15] & 0x10) 1427 *(bool *)data = true; 1428 } 1429 1430 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1431 static bool 1432 drm_monitor_supports_rb(struct edid *edid) 1433 { 1434 if (edid->revision >= 4) { 1435 bool ret = false; 1436 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1437 return ret; 1438 } 1439 1440 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1441 } 1442 1443 static void 1444 find_gtf2(struct detailed_timing *t, void *data) 1445 { 1446 u8 *r = (u8 *)t; 1447 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1448 *(u8 **)data = r; 1449 } 1450 1451 /* Secondary GTF curve kicks in above some break frequency */ 1452 static int 1453 drm_gtf2_hbreak(struct edid *edid) 1454 { 1455 u8 *r = NULL; 1456 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1457 return r ? (r[12] * 2) : 0; 1458 } 1459 1460 static int 1461 drm_gtf2_2c(struct edid *edid) 1462 { 1463 u8 *r = NULL; 1464 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1465 return r ? r[13] : 0; 1466 } 1467 1468 static int 1469 drm_gtf2_m(struct edid *edid) 1470 { 1471 u8 *r = NULL; 1472 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1473 return r ? (r[15] << 8) + r[14] : 0; 1474 } 1475 1476 static int 1477 drm_gtf2_k(struct edid *edid) 1478 { 1479 u8 *r = NULL; 1480 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1481 return r ? r[16] : 0; 1482 } 1483 1484 static int 1485 drm_gtf2_2j(struct edid *edid) 1486 { 1487 u8 *r = NULL; 1488 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1489 return r ? r[17] : 0; 1490 } 1491 1492 /** 1493 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1494 * @edid: EDID block to scan 1495 */ 1496 static int standard_timing_level(struct edid *edid) 1497 { 1498 if (edid->revision >= 2) { 1499 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1500 return LEVEL_CVT; 1501 if (drm_gtf2_hbreak(edid)) 1502 return LEVEL_GTF2; 1503 return LEVEL_GTF; 1504 } 1505 return LEVEL_DMT; 1506 } 1507 1508 /* 1509 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1510 * monitors fill with ascii space (0x20) instead. 1511 */ 1512 static int 1513 bad_std_timing(u8 a, u8 b) 1514 { 1515 return (a == 0x00 && b == 0x00) || 1516 (a == 0x01 && b == 0x01) || 1517 (a == 0x20 && b == 0x20); 1518 } 1519 1520 /** 1521 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1522 * @t: standard timing params 1523 * @timing_level: standard timing level 1524 * 1525 * Take the standard timing params (in this case width, aspect, and refresh) 1526 * and convert them into a real mode using CVT/GTF/DMT. 1527 */ 1528 static struct drm_display_mode * 1529 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1530 struct std_timing *t, int revision) 1531 { 1532 struct drm_device *dev = connector->dev; 1533 struct drm_display_mode *m, *mode = NULL; 1534 int hsize, vsize; 1535 int vrefresh_rate; 1536 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1537 >> EDID_TIMING_ASPECT_SHIFT; 1538 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1539 >> EDID_TIMING_VFREQ_SHIFT; 1540 int timing_level = standard_timing_level(edid); 1541 1542 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1543 return NULL; 1544 1545 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1546 hsize = t->hsize * 8 + 248; 1547 /* vrefresh_rate = vfreq + 60 */ 1548 vrefresh_rate = vfreq + 60; 1549 /* the vdisplay is calculated based on the aspect ratio */ 1550 if (aspect_ratio == 0) { 1551 if (revision < 3) 1552 vsize = hsize; 1553 else 1554 vsize = (hsize * 10) / 16; 1555 } else if (aspect_ratio == 1) 1556 vsize = (hsize * 3) / 4; 1557 else if (aspect_ratio == 2) 1558 vsize = (hsize * 4) / 5; 1559 else 1560 vsize = (hsize * 9) / 16; 1561 1562 /* HDTV hack, part 1 */ 1563 if (vrefresh_rate == 60 && 1564 ((hsize == 1360 && vsize == 765) || 1565 (hsize == 1368 && vsize == 769))) { 1566 hsize = 1366; 1567 vsize = 768; 1568 } 1569 1570 /* 1571 * If this connector already has a mode for this size and refresh 1572 * rate (because it came from detailed or CVT info), use that 1573 * instead. This way we don't have to guess at interlace or 1574 * reduced blanking. 1575 */ 1576 list_for_each_entry(m, &connector->probed_modes, head) 1577 if (m->hdisplay == hsize && m->vdisplay == vsize && 1578 drm_mode_vrefresh(m) == vrefresh_rate) 1579 return NULL; 1580 1581 /* HDTV hack, part 2 */ 1582 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1583 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1584 false); 1585 mode->hdisplay = 1366; 1586 mode->hsync_start = mode->hsync_start - 1; 1587 mode->hsync_end = mode->hsync_end - 1; 1588 return mode; 1589 } 1590 1591 /* check whether it can be found in default mode table */ 1592 if (drm_monitor_supports_rb(edid)) { 1593 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1594 true); 1595 if (mode) 1596 return mode; 1597 } 1598 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1599 if (mode) 1600 return mode; 1601 1602 /* okay, generate it */ 1603 switch (timing_level) { 1604 case LEVEL_DMT: 1605 break; 1606 case LEVEL_GTF: 1607 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1608 break; 1609 case LEVEL_GTF2: 1610 /* 1611 * This is potentially wrong if there's ever a monitor with 1612 * more than one ranges section, each claiming a different 1613 * secondary GTF curve. Please don't do that. 1614 */ 1615 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1616 if (!mode) 1617 return NULL; 1618 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1619 drm_mode_destroy(dev, mode); 1620 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1621 vrefresh_rate, 0, 0, 1622 drm_gtf2_m(edid), 1623 drm_gtf2_2c(edid), 1624 drm_gtf2_k(edid), 1625 drm_gtf2_2j(edid)); 1626 } 1627 break; 1628 case LEVEL_CVT: 1629 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1630 false); 1631 break; 1632 } 1633 return mode; 1634 } 1635 1636 /* 1637 * EDID is delightfully ambiguous about how interlaced modes are to be 1638 * encoded. Our internal representation is of frame height, but some 1639 * HDTV detailed timings are encoded as field height. 1640 * 1641 * The format list here is from CEA, in frame size. Technically we 1642 * should be checking refresh rate too. Whatever. 1643 */ 1644 static void 1645 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1646 struct detailed_pixel_timing *pt) 1647 { 1648 int i; 1649 static const struct { 1650 int w, h; 1651 } cea_interlaced[] = { 1652 { 1920, 1080 }, 1653 { 720, 480 }, 1654 { 1440, 480 }, 1655 { 2880, 480 }, 1656 { 720, 576 }, 1657 { 1440, 576 }, 1658 { 2880, 576 }, 1659 }; 1660 1661 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1662 return; 1663 1664 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1665 if ((mode->hdisplay == cea_interlaced[i].w) && 1666 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1667 mode->vdisplay *= 2; 1668 mode->vsync_start *= 2; 1669 mode->vsync_end *= 2; 1670 mode->vtotal *= 2; 1671 mode->vtotal |= 1; 1672 } 1673 } 1674 1675 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1676 } 1677 1678 /** 1679 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1680 * @dev: DRM device (needed to create new mode) 1681 * @edid: EDID block 1682 * @timing: EDID detailed timing info 1683 * @quirks: quirks to apply 1684 * 1685 * An EDID detailed timing block contains enough info for us to create and 1686 * return a new struct drm_display_mode. 1687 */ 1688 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1689 struct edid *edid, 1690 struct detailed_timing *timing, 1691 u32 quirks) 1692 { 1693 struct drm_display_mode *mode; 1694 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1695 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1696 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1697 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1698 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1699 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1700 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1701 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1702 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1703 1704 /* ignore tiny modes */ 1705 if (hactive < 64 || vactive < 64) 1706 return NULL; 1707 1708 if (pt->misc & DRM_EDID_PT_STEREO) { 1709 printk(KERN_WARNING "stereo mode not supported\n"); 1710 return NULL; 1711 } 1712 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1713 printk(KERN_WARNING "composite sync not supported\n"); 1714 } 1715 1716 /* it is incorrect if hsync/vsync width is zero */ 1717 if (!hsync_pulse_width || !vsync_pulse_width) { 1718 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1719 "Wrong Hsync/Vsync pulse width\n"); 1720 return NULL; 1721 } 1722 1723 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1724 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1725 if (!mode) 1726 return NULL; 1727 1728 goto set_size; 1729 } 1730 1731 mode = drm_mode_create(dev); 1732 if (!mode) 1733 return NULL; 1734 1735 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1736 timing->pixel_clock = cpu_to_le16(1088); 1737 1738 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1739 1740 mode->hdisplay = hactive; 1741 mode->hsync_start = mode->hdisplay + hsync_offset; 1742 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1743 mode->htotal = mode->hdisplay + hblank; 1744 1745 mode->vdisplay = vactive; 1746 mode->vsync_start = mode->vdisplay + vsync_offset; 1747 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1748 mode->vtotal = mode->vdisplay + vblank; 1749 1750 /* Some EDIDs have bogus h/vtotal values */ 1751 if (mode->hsync_end > mode->htotal) 1752 mode->htotal = mode->hsync_end + 1; 1753 if (mode->vsync_end > mode->vtotal) 1754 mode->vtotal = mode->vsync_end + 1; 1755 1756 drm_mode_do_interlace_quirk(mode, pt); 1757 1758 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1759 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1760 } 1761 1762 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1763 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1764 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1765 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1766 1767 set_size: 1768 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1769 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1770 1771 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1772 mode->width_mm *= 10; 1773 mode->height_mm *= 10; 1774 } 1775 1776 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1777 mode->width_mm = edid->width_cm * 10; 1778 mode->height_mm = edid->height_cm * 10; 1779 } 1780 1781 mode->type = DRM_MODE_TYPE_DRIVER; 1782 mode->vrefresh = drm_mode_vrefresh(mode); 1783 drm_mode_set_name(mode); 1784 1785 return mode; 1786 } 1787 1788 static bool 1789 mode_in_hsync_range(const struct drm_display_mode *mode, 1790 struct edid *edid, u8 *t) 1791 { 1792 int hsync, hmin, hmax; 1793 1794 hmin = t[7]; 1795 if (edid->revision >= 4) 1796 hmin += ((t[4] & 0x04) ? 255 : 0); 1797 hmax = t[8]; 1798 if (edid->revision >= 4) 1799 hmax += ((t[4] & 0x08) ? 255 : 0); 1800 hsync = drm_mode_hsync(mode); 1801 1802 return (hsync <= hmax && hsync >= hmin); 1803 } 1804 1805 static bool 1806 mode_in_vsync_range(const struct drm_display_mode *mode, 1807 struct edid *edid, u8 *t) 1808 { 1809 int vsync, vmin, vmax; 1810 1811 vmin = t[5]; 1812 if (edid->revision >= 4) 1813 vmin += ((t[4] & 0x01) ? 255 : 0); 1814 vmax = t[6]; 1815 if (edid->revision >= 4) 1816 vmax += ((t[4] & 0x02) ? 255 : 0); 1817 vsync = drm_mode_vrefresh(mode); 1818 1819 return (vsync <= vmax && vsync >= vmin); 1820 } 1821 1822 static u32 1823 range_pixel_clock(struct edid *edid, u8 *t) 1824 { 1825 /* unspecified */ 1826 if (t[9] == 0 || t[9] == 255) 1827 return 0; 1828 1829 /* 1.4 with CVT support gives us real precision, yay */ 1830 if (edid->revision >= 4 && t[10] == 0x04) 1831 return (t[9] * 10000) - ((t[12] >> 2) * 250); 1832 1833 /* 1.3 is pathetic, so fuzz up a bit */ 1834 return t[9] * 10000 + 5001; 1835 } 1836 1837 static bool 1838 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 1839 struct detailed_timing *timing) 1840 { 1841 u32 max_clock; 1842 u8 *t = (u8 *)timing; 1843 1844 if (!mode_in_hsync_range(mode, edid, t)) 1845 return false; 1846 1847 if (!mode_in_vsync_range(mode, edid, t)) 1848 return false; 1849 1850 if ((max_clock = range_pixel_clock(edid, t))) 1851 if (mode->clock > max_clock) 1852 return false; 1853 1854 /* 1.4 max horizontal check */ 1855 if (edid->revision >= 4 && t[10] == 0x04) 1856 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 1857 return false; 1858 1859 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 1860 return false; 1861 1862 return true; 1863 } 1864 1865 static bool valid_inferred_mode(const struct drm_connector *connector, 1866 const struct drm_display_mode *mode) 1867 { 1868 struct drm_display_mode *m; 1869 bool ok = false; 1870 1871 list_for_each_entry(m, &connector->probed_modes, head) { 1872 if (mode->hdisplay == m->hdisplay && 1873 mode->vdisplay == m->vdisplay && 1874 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 1875 return false; /* duplicated */ 1876 if (mode->hdisplay <= m->hdisplay && 1877 mode->vdisplay <= m->vdisplay) 1878 ok = true; 1879 } 1880 return ok; 1881 } 1882 1883 static int 1884 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1885 struct detailed_timing *timing) 1886 { 1887 int i, modes = 0; 1888 struct drm_display_mode *newmode; 1889 struct drm_device *dev = connector->dev; 1890 1891 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1892 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 1893 valid_inferred_mode(connector, drm_dmt_modes + i)) { 1894 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 1895 if (newmode) { 1896 drm_mode_probed_add(connector, newmode); 1897 modes++; 1898 } 1899 } 1900 } 1901 1902 return modes; 1903 } 1904 1905 /* fix up 1366x768 mode from 1368x768; 1906 * GFT/CVT can't express 1366 width which isn't dividable by 8 1907 */ 1908 static void fixup_mode_1366x768(struct drm_display_mode *mode) 1909 { 1910 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 1911 mode->hdisplay = 1366; 1912 mode->hsync_start--; 1913 mode->hsync_end--; 1914 drm_mode_set_name(mode); 1915 } 1916 } 1917 1918 static int 1919 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 1920 struct detailed_timing *timing) 1921 { 1922 int i, modes = 0; 1923 struct drm_display_mode *newmode; 1924 struct drm_device *dev = connector->dev; 1925 1926 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 1927 const struct minimode *m = &extra_modes[i]; 1928 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 1929 if (!newmode) 1930 return modes; 1931 1932 fixup_mode_1366x768(newmode); 1933 if (!mode_in_range(newmode, edid, timing) || 1934 !valid_inferred_mode(connector, newmode)) { 1935 drm_mode_destroy(dev, newmode); 1936 continue; 1937 } 1938 1939 drm_mode_probed_add(connector, newmode); 1940 modes++; 1941 } 1942 1943 return modes; 1944 } 1945 1946 static int 1947 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1948 struct detailed_timing *timing) 1949 { 1950 int i, modes = 0; 1951 struct drm_display_mode *newmode; 1952 struct drm_device *dev = connector->dev; 1953 bool rb = drm_monitor_supports_rb(edid); 1954 1955 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 1956 const struct minimode *m = &extra_modes[i]; 1957 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 1958 if (!newmode) 1959 return modes; 1960 1961 fixup_mode_1366x768(newmode); 1962 if (!mode_in_range(newmode, edid, timing) || 1963 !valid_inferred_mode(connector, newmode)) { 1964 drm_mode_destroy(dev, newmode); 1965 continue; 1966 } 1967 1968 drm_mode_probed_add(connector, newmode); 1969 modes++; 1970 } 1971 1972 return modes; 1973 } 1974 1975 static void 1976 do_inferred_modes(struct detailed_timing *timing, void *c) 1977 { 1978 struct detailed_mode_closure *closure = c; 1979 struct detailed_non_pixel *data = &timing->data.other_data; 1980 struct detailed_data_monitor_range *range = &data->data.range; 1981 1982 if (data->type != EDID_DETAIL_MONITOR_RANGE) 1983 return; 1984 1985 closure->modes += drm_dmt_modes_for_range(closure->connector, 1986 closure->edid, 1987 timing); 1988 1989 if (!version_greater(closure->edid, 1, 1)) 1990 return; /* GTF not defined yet */ 1991 1992 switch (range->flags) { 1993 case 0x02: /* secondary gtf, XXX could do more */ 1994 case 0x00: /* default gtf */ 1995 closure->modes += drm_gtf_modes_for_range(closure->connector, 1996 closure->edid, 1997 timing); 1998 break; 1999 case 0x04: /* cvt, only in 1.4+ */ 2000 if (!version_greater(closure->edid, 1, 3)) 2001 break; 2002 2003 closure->modes += drm_cvt_modes_for_range(closure->connector, 2004 closure->edid, 2005 timing); 2006 break; 2007 case 0x01: /* just the ranges, no formula */ 2008 default: 2009 break; 2010 } 2011 } 2012 2013 static int 2014 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2015 { 2016 struct detailed_mode_closure closure = { 2017 connector, edid, 0, 0, 0 2018 }; 2019 2020 if (version_greater(edid, 1, 0)) 2021 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2022 &closure); 2023 2024 return closure.modes; 2025 } 2026 2027 static int 2028 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2029 { 2030 int i, j, m, modes = 0; 2031 struct drm_display_mode *mode; 2032 u8 *est = ((u8 *)timing) + 5; 2033 2034 for (i = 0; i < 6; i++) { 2035 for (j = 7; j > 0; j--) { 2036 m = (i * 8) + (7 - j); 2037 if (m >= ARRAY_SIZE(est3_modes)) 2038 break; 2039 if (est[i] & (1 << j)) { 2040 mode = drm_mode_find_dmt(connector->dev, 2041 est3_modes[m].w, 2042 est3_modes[m].h, 2043 est3_modes[m].r, 2044 est3_modes[m].rb); 2045 if (mode) { 2046 drm_mode_probed_add(connector, mode); 2047 modes++; 2048 } 2049 } 2050 } 2051 } 2052 2053 return modes; 2054 } 2055 2056 static void 2057 do_established_modes(struct detailed_timing *timing, void *c) 2058 { 2059 struct detailed_mode_closure *closure = c; 2060 struct detailed_non_pixel *data = &timing->data.other_data; 2061 2062 if (data->type == EDID_DETAIL_EST_TIMINGS) 2063 closure->modes += drm_est3_modes(closure->connector, timing); 2064 } 2065 2066 /** 2067 * add_established_modes - get est. modes from EDID and add them 2068 * @edid: EDID block to scan 2069 * 2070 * Each EDID block contains a bitmap of the supported "established modes" list 2071 * (defined above). Tease them out and add them to the global modes list. 2072 */ 2073 static int 2074 add_established_modes(struct drm_connector *connector, struct edid *edid) 2075 { 2076 struct drm_device *dev = connector->dev; 2077 unsigned long est_bits = edid->established_timings.t1 | 2078 (edid->established_timings.t2 << 8) | 2079 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2080 int i, modes = 0; 2081 struct detailed_mode_closure closure = { 2082 connector, edid, 0, 0, 0 2083 }; 2084 2085 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2086 if (est_bits & (1<<i)) { 2087 struct drm_display_mode *newmode; 2088 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2089 if (newmode) { 2090 drm_mode_probed_add(connector, newmode); 2091 modes++; 2092 } 2093 } 2094 } 2095 2096 if (version_greater(edid, 1, 0)) 2097 drm_for_each_detailed_block((u8 *)edid, 2098 do_established_modes, &closure); 2099 2100 return modes + closure.modes; 2101 } 2102 2103 static void 2104 do_standard_modes(struct detailed_timing *timing, void *c) 2105 { 2106 struct detailed_mode_closure *closure = c; 2107 struct detailed_non_pixel *data = &timing->data.other_data; 2108 struct drm_connector *connector = closure->connector; 2109 struct edid *edid = closure->edid; 2110 2111 if (data->type == EDID_DETAIL_STD_MODES) { 2112 int i; 2113 for (i = 0; i < 6; i++) { 2114 struct std_timing *std; 2115 struct drm_display_mode *newmode; 2116 2117 std = &data->data.timings[i]; 2118 newmode = drm_mode_std(connector, edid, std, 2119 edid->revision); 2120 if (newmode) { 2121 drm_mode_probed_add(connector, newmode); 2122 closure->modes++; 2123 } 2124 } 2125 } 2126 } 2127 2128 /** 2129 * add_standard_modes - get std. modes from EDID and add them 2130 * @edid: EDID block to scan 2131 * 2132 * Standard modes can be calculated using the appropriate standard (DMT, 2133 * GTF or CVT. Grab them from @edid and add them to the list. 2134 */ 2135 static int 2136 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2137 { 2138 int i, modes = 0; 2139 struct detailed_mode_closure closure = { 2140 connector, edid, 0, 0, 0 2141 }; 2142 2143 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2144 struct drm_display_mode *newmode; 2145 2146 newmode = drm_mode_std(connector, edid, 2147 &edid->standard_timings[i], 2148 edid->revision); 2149 if (newmode) { 2150 drm_mode_probed_add(connector, newmode); 2151 modes++; 2152 } 2153 } 2154 2155 if (version_greater(edid, 1, 0)) 2156 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2157 &closure); 2158 2159 /* XXX should also look for standard codes in VTB blocks */ 2160 2161 return modes + closure.modes; 2162 } 2163 2164 static int drm_cvt_modes(struct drm_connector *connector, 2165 struct detailed_timing *timing) 2166 { 2167 int i, j, modes = 0; 2168 struct drm_display_mode *newmode; 2169 struct drm_device *dev = connector->dev; 2170 struct cvt_timing *cvt; 2171 const int rates[] = { 60, 85, 75, 60, 50 }; 2172 const u8 empty[3] = { 0, 0, 0 }; 2173 2174 for (i = 0; i < 4; i++) { 2175 int uninitialized_var(width), height; 2176 cvt = &(timing->data.other_data.data.cvt[i]); 2177 2178 if (!memcmp(cvt->code, empty, 3)) 2179 continue; 2180 2181 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2182 switch (cvt->code[1] & 0x0c) { 2183 case 0x00: 2184 width = height * 4 / 3; 2185 break; 2186 case 0x04: 2187 width = height * 16 / 9; 2188 break; 2189 case 0x08: 2190 width = height * 16 / 10; 2191 break; 2192 case 0x0c: 2193 width = height * 15 / 9; 2194 break; 2195 } 2196 2197 for (j = 1; j < 5; j++) { 2198 if (cvt->code[2] & (1 << j)) { 2199 newmode = drm_cvt_mode(dev, width, height, 2200 rates[j], j == 0, 2201 false, false); 2202 if (newmode) { 2203 drm_mode_probed_add(connector, newmode); 2204 modes++; 2205 } 2206 } 2207 } 2208 } 2209 2210 return modes; 2211 } 2212 2213 static void 2214 do_cvt_mode(struct detailed_timing *timing, void *c) 2215 { 2216 struct detailed_mode_closure *closure = c; 2217 struct detailed_non_pixel *data = &timing->data.other_data; 2218 2219 if (data->type == EDID_DETAIL_CVT_3BYTE) 2220 closure->modes += drm_cvt_modes(closure->connector, timing); 2221 } 2222 2223 static int 2224 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2225 { 2226 struct detailed_mode_closure closure = { 2227 connector, edid, 0, 0, 0 2228 }; 2229 2230 if (version_greater(edid, 1, 2)) 2231 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2232 2233 /* XXX should also look for CVT codes in VTB blocks */ 2234 2235 return closure.modes; 2236 } 2237 2238 static void 2239 do_detailed_mode(struct detailed_timing *timing, void *c) 2240 { 2241 struct detailed_mode_closure *closure = c; 2242 struct drm_display_mode *newmode; 2243 2244 if (timing->pixel_clock) { 2245 newmode = drm_mode_detailed(closure->connector->dev, 2246 closure->edid, timing, 2247 closure->quirks); 2248 if (!newmode) 2249 return; 2250 2251 if (closure->preferred) 2252 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2253 2254 drm_mode_probed_add(closure->connector, newmode); 2255 closure->modes++; 2256 closure->preferred = 0; 2257 } 2258 } 2259 2260 /* 2261 * add_detailed_modes - Add modes from detailed timings 2262 * @connector: attached connector 2263 * @edid: EDID block to scan 2264 * @quirks: quirks to apply 2265 */ 2266 static int 2267 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2268 u32 quirks) 2269 { 2270 struct detailed_mode_closure closure = { 2271 connector, 2272 edid, 2273 1, 2274 quirks, 2275 0 2276 }; 2277 2278 if (closure.preferred && !version_greater(edid, 1, 3)) 2279 closure.preferred = 2280 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2281 2282 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2283 2284 return closure.modes; 2285 } 2286 2287 #define HDMI_IDENTIFIER 0x000C03 2288 #define AUDIO_BLOCK 0x01 2289 #define VIDEO_BLOCK 0x02 2290 #define VENDOR_BLOCK 0x03 2291 #define SPEAKER_BLOCK 0x04 2292 #define VIDEO_CAPABILITY_BLOCK 0x07 2293 #define EDID_BASIC_AUDIO (1 << 6) 2294 #define EDID_CEA_YCRCB444 (1 << 5) 2295 #define EDID_CEA_YCRCB422 (1 << 4) 2296 #define EDID_CEA_VCDB_QS (1 << 6) 2297 2298 /** 2299 * Search EDID for CEA extension block. 2300 */ 2301 u8 *drm_find_cea_extension(struct edid *edid) 2302 { 2303 u8 *edid_ext = NULL; 2304 int i; 2305 2306 /* No EDID or EDID extensions */ 2307 if (edid == NULL || edid->extensions == 0) 2308 return NULL; 2309 2310 /* Find CEA extension */ 2311 for (i = 0; i < edid->extensions; i++) { 2312 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2313 if (edid_ext[0] == CEA_EXT) 2314 break; 2315 } 2316 2317 if (i == edid->extensions) 2318 return NULL; 2319 2320 return edid_ext; 2321 } 2322 EXPORT_SYMBOL(drm_find_cea_extension); 2323 2324 /** 2325 * drm_match_cea_mode - look for a CEA mode matching given mode 2326 * @to_match: display mode 2327 * 2328 * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2329 * mode. 2330 */ 2331 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2332 { 2333 u8 mode; 2334 2335 if (!to_match->clock) 2336 return 0; 2337 2338 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2339 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2340 unsigned int clock1, clock2; 2341 2342 clock1 = clock2 = cea_mode->clock; 2343 2344 /* Check both 60Hz and 59.94Hz */ 2345 if (cea_mode->vrefresh % 6 == 0) { 2346 /* 2347 * edid_cea_modes contains the 59.94Hz 2348 * variant for 240 and 480 line modes, 2349 * and the 60Hz variant otherwise. 2350 */ 2351 if (cea_mode->vdisplay == 240 || 2352 cea_mode->vdisplay == 480) 2353 clock1 = clock1 * 1001 / 1000; 2354 else 2355 clock2 = DIV_ROUND_UP(clock2 * 1000, 1001); 2356 } 2357 2358 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2359 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2360 drm_mode_equal_no_clocks(to_match, cea_mode)) 2361 return mode + 1; 2362 } 2363 return 0; 2364 } 2365 EXPORT_SYMBOL(drm_match_cea_mode); 2366 2367 2368 static int 2369 do_cea_modes (struct drm_connector *connector, u8 *db, u8 len) 2370 { 2371 struct drm_device *dev = connector->dev; 2372 u8 * mode, cea_mode; 2373 int modes = 0; 2374 2375 for (mode = db; mode < db + len; mode++) { 2376 cea_mode = (*mode & 127) - 1; /* CEA modes are numbered 1..127 */ 2377 if (cea_mode < ARRAY_SIZE(edid_cea_modes)) { 2378 struct drm_display_mode *newmode; 2379 newmode = drm_mode_duplicate(dev, 2380 &edid_cea_modes[cea_mode]); 2381 if (newmode) { 2382 newmode->vrefresh = 0; 2383 drm_mode_probed_add(connector, newmode); 2384 modes++; 2385 } 2386 } 2387 } 2388 2389 return modes; 2390 } 2391 2392 static int 2393 cea_db_payload_len(const u8 *db) 2394 { 2395 return db[0] & 0x1f; 2396 } 2397 2398 static int 2399 cea_db_tag(const u8 *db) 2400 { 2401 return db[0] >> 5; 2402 } 2403 2404 static int 2405 cea_revision(const u8 *cea) 2406 { 2407 return cea[1]; 2408 } 2409 2410 static int 2411 cea_db_offsets(const u8 *cea, int *start, int *end) 2412 { 2413 /* Data block offset in CEA extension block */ 2414 *start = 4; 2415 *end = cea[2]; 2416 if (*end == 0) 2417 *end = 127; 2418 if (*end < 4 || *end > 127) 2419 return -ERANGE; 2420 return 0; 2421 } 2422 2423 #define for_each_cea_db(cea, i, start, end) \ 2424 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2425 2426 static int 2427 add_cea_modes(struct drm_connector *connector, struct edid *edid) 2428 { 2429 u8 * cea = drm_find_cea_extension(edid); 2430 u8 * db, dbl; 2431 int modes = 0; 2432 2433 if (cea && cea_revision(cea) >= 3) { 2434 int i, start, end; 2435 2436 if (cea_db_offsets(cea, &start, &end)) 2437 return 0; 2438 2439 for_each_cea_db(cea, i, start, end) { 2440 db = &cea[i]; 2441 dbl = cea_db_payload_len(db); 2442 2443 if (cea_db_tag(db) == VIDEO_BLOCK) 2444 modes += do_cea_modes (connector, db+1, dbl); 2445 } 2446 } 2447 2448 return modes; 2449 } 2450 2451 static void 2452 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 2453 { 2454 u8 len = cea_db_payload_len(db); 2455 2456 if (len >= 6) { 2457 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 2458 connector->dvi_dual = db[6] & 1; 2459 } 2460 if (len >= 7) 2461 connector->max_tmds_clock = db[7] * 5; 2462 if (len >= 8) { 2463 connector->latency_present[0] = db[8] >> 7; 2464 connector->latency_present[1] = (db[8] >> 6) & 1; 2465 } 2466 if (len >= 9) 2467 connector->video_latency[0] = db[9]; 2468 if (len >= 10) 2469 connector->audio_latency[0] = db[10]; 2470 if (len >= 11) 2471 connector->video_latency[1] = db[11]; 2472 if (len >= 12) 2473 connector->audio_latency[1] = db[12]; 2474 2475 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 2476 "max TMDS clock %d, " 2477 "latency present %d %d, " 2478 "video latency %d %d, " 2479 "audio latency %d %d\n", 2480 connector->dvi_dual, 2481 connector->max_tmds_clock, 2482 (int) connector->latency_present[0], 2483 (int) connector->latency_present[1], 2484 connector->video_latency[0], 2485 connector->video_latency[1], 2486 connector->audio_latency[0], 2487 connector->audio_latency[1]); 2488 } 2489 2490 static void 2491 monitor_name(struct detailed_timing *t, void *data) 2492 { 2493 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 2494 *(u8 **)data = t->data.other_data.data.str.str; 2495 } 2496 2497 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2498 { 2499 int hdmi_id; 2500 2501 if (cea_db_tag(db) != VENDOR_BLOCK) 2502 return false; 2503 2504 if (cea_db_payload_len(db) < 5) 2505 return false; 2506 2507 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2508 2509 return hdmi_id == HDMI_IDENTIFIER; 2510 } 2511 2512 /** 2513 * drm_edid_to_eld - build ELD from EDID 2514 * @connector: connector corresponding to the HDMI/DP sink 2515 * @edid: EDID to parse 2516 * 2517 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. 2518 * Some ELD fields are left to the graphics driver caller: 2519 * - Conn_Type 2520 * - HDCP 2521 * - Port_ID 2522 */ 2523 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 2524 { 2525 uint8_t *eld = connector->eld; 2526 u8 *cea; 2527 u8 *name; 2528 u8 *db; 2529 int sad_count = 0; 2530 int mnl; 2531 int dbl; 2532 2533 memset(eld, 0, sizeof(connector->eld)); 2534 2535 cea = drm_find_cea_extension(edid); 2536 if (!cea) { 2537 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 2538 return; 2539 } 2540 2541 name = NULL; 2542 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 2543 for (mnl = 0; name && mnl < 13; mnl++) { 2544 if (name[mnl] == 0x0a) 2545 break; 2546 eld[20 + mnl] = name[mnl]; 2547 } 2548 eld[4] = (cea[1] << 5) | mnl; 2549 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 2550 2551 eld[0] = 2 << 3; /* ELD version: 2 */ 2552 2553 eld[16] = edid->mfg_id[0]; 2554 eld[17] = edid->mfg_id[1]; 2555 eld[18] = edid->prod_code[0]; 2556 eld[19] = edid->prod_code[1]; 2557 2558 if (cea_revision(cea) >= 3) { 2559 int i, start, end; 2560 2561 if (cea_db_offsets(cea, &start, &end)) { 2562 start = 0; 2563 end = 0; 2564 } 2565 2566 for_each_cea_db(cea, i, start, end) { 2567 db = &cea[i]; 2568 dbl = cea_db_payload_len(db); 2569 2570 switch (cea_db_tag(db)) { 2571 case AUDIO_BLOCK: 2572 /* Audio Data Block, contains SADs */ 2573 sad_count = dbl / 3; 2574 if (dbl >= 1) 2575 memcpy(eld + 20 + mnl, &db[1], dbl); 2576 break; 2577 case SPEAKER_BLOCK: 2578 /* Speaker Allocation Data Block */ 2579 if (dbl >= 1) 2580 eld[7] = db[1]; 2581 break; 2582 case VENDOR_BLOCK: 2583 /* HDMI Vendor-Specific Data Block */ 2584 if (cea_db_is_hdmi_vsdb(db)) 2585 parse_hdmi_vsdb(connector, db); 2586 break; 2587 default: 2588 break; 2589 } 2590 } 2591 } 2592 eld[5] |= sad_count << 4; 2593 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 2594 2595 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 2596 } 2597 EXPORT_SYMBOL(drm_edid_to_eld); 2598 2599 /** 2600 * drm_edid_to_sad - extracts SADs from EDID 2601 * @edid: EDID to parse 2602 * @sads: pointer that will be set to the extracted SADs 2603 * 2604 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 2605 * Note: returned pointer needs to be kfreed 2606 * 2607 * Return number of found SADs or negative number on error. 2608 */ 2609 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 2610 { 2611 int count = 0; 2612 int i, start, end, dbl; 2613 u8 *cea; 2614 2615 cea = drm_find_cea_extension(edid); 2616 if (!cea) { 2617 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 2618 return -ENOENT; 2619 } 2620 2621 if (cea_revision(cea) < 3) { 2622 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 2623 return -ENOTSUPP; 2624 } 2625 2626 if (cea_db_offsets(cea, &start, &end)) { 2627 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 2628 return -EPROTO; 2629 } 2630 2631 for_each_cea_db(cea, i, start, end) { 2632 u8 *db = &cea[i]; 2633 2634 if (cea_db_tag(db) == AUDIO_BLOCK) { 2635 int j; 2636 dbl = cea_db_payload_len(db); 2637 2638 count = dbl / 3; /* SAD is 3B */ 2639 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 2640 if (!*sads) 2641 return -ENOMEM; 2642 for (j = 0; j < count; j++) { 2643 u8 *sad = &db[1 + j * 3]; 2644 2645 (*sads)[j].format = (sad[0] & 0x78) >> 3; 2646 (*sads)[j].channels = sad[0] & 0x7; 2647 (*sads)[j].freq = sad[1] & 0x7F; 2648 (*sads)[j].byte2 = sad[2]; 2649 } 2650 break; 2651 } 2652 } 2653 2654 return count; 2655 } 2656 EXPORT_SYMBOL(drm_edid_to_sad); 2657 2658 /** 2659 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond 2660 * @connector: connector associated with the HDMI/DP sink 2661 * @mode: the display mode 2662 */ 2663 int drm_av_sync_delay(struct drm_connector *connector, 2664 struct drm_display_mode *mode) 2665 { 2666 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 2667 int a, v; 2668 2669 if (!connector->latency_present[0]) 2670 return 0; 2671 if (!connector->latency_present[1]) 2672 i = 0; 2673 2674 a = connector->audio_latency[i]; 2675 v = connector->video_latency[i]; 2676 2677 /* 2678 * HDMI/DP sink doesn't support audio or video? 2679 */ 2680 if (a == 255 || v == 255) 2681 return 0; 2682 2683 /* 2684 * Convert raw EDID values to millisecond. 2685 * Treat unknown latency as 0ms. 2686 */ 2687 if (a) 2688 a = min(2 * (a - 1), 500); 2689 if (v) 2690 v = min(2 * (v - 1), 500); 2691 2692 return max(v - a, 0); 2693 } 2694 EXPORT_SYMBOL(drm_av_sync_delay); 2695 2696 /** 2697 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 2698 * @encoder: the encoder just changed display mode 2699 * @mode: the adjusted display mode 2700 * 2701 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 2702 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 2703 */ 2704 struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 2705 struct drm_display_mode *mode) 2706 { 2707 struct drm_connector *connector; 2708 struct drm_device *dev = encoder->dev; 2709 2710 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 2711 if (connector->encoder == encoder && connector->eld[0]) 2712 return connector; 2713 2714 return NULL; 2715 } 2716 EXPORT_SYMBOL(drm_select_eld); 2717 2718 /** 2719 * drm_detect_hdmi_monitor - detect whether monitor is hdmi. 2720 * @edid: monitor EDID information 2721 * 2722 * Parse the CEA extension according to CEA-861-B. 2723 * Return true if HDMI, false if not or unknown. 2724 */ 2725 bool drm_detect_hdmi_monitor(struct edid *edid) 2726 { 2727 u8 *edid_ext; 2728 int i; 2729 int start_offset, end_offset; 2730 2731 edid_ext = drm_find_cea_extension(edid); 2732 if (!edid_ext) 2733 return false; 2734 2735 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2736 return false; 2737 2738 /* 2739 * Because HDMI identifier is in Vendor Specific Block, 2740 * search it from all data blocks of CEA extension. 2741 */ 2742 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2743 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 2744 return true; 2745 } 2746 2747 return false; 2748 } 2749 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 2750 2751 /** 2752 * drm_detect_monitor_audio - check monitor audio capability 2753 * 2754 * Monitor should have CEA extension block. 2755 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 2756 * audio' only. If there is any audio extension block and supported 2757 * audio format, assume at least 'basic audio' support, even if 'basic 2758 * audio' is not defined in EDID. 2759 * 2760 */ 2761 bool drm_detect_monitor_audio(struct edid *edid) 2762 { 2763 u8 *edid_ext; 2764 int i, j; 2765 bool has_audio = false; 2766 int start_offset, end_offset; 2767 2768 edid_ext = drm_find_cea_extension(edid); 2769 if (!edid_ext) 2770 goto end; 2771 2772 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 2773 2774 if (has_audio) { 2775 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 2776 goto end; 2777 } 2778 2779 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2780 goto end; 2781 2782 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2783 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 2784 has_audio = true; 2785 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 2786 DRM_DEBUG_KMS("CEA audio format %d\n", 2787 (edid_ext[i + j] >> 3) & 0xf); 2788 goto end; 2789 } 2790 } 2791 end: 2792 return has_audio; 2793 } 2794 EXPORT_SYMBOL(drm_detect_monitor_audio); 2795 2796 /** 2797 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 2798 * 2799 * Check whether the monitor reports the RGB quantization range selection 2800 * as supported. The AVI infoframe can then be used to inform the monitor 2801 * which quantization range (full or limited) is used. 2802 */ 2803 bool drm_rgb_quant_range_selectable(struct edid *edid) 2804 { 2805 u8 *edid_ext; 2806 int i, start, end; 2807 2808 edid_ext = drm_find_cea_extension(edid); 2809 if (!edid_ext) 2810 return false; 2811 2812 if (cea_db_offsets(edid_ext, &start, &end)) 2813 return false; 2814 2815 for_each_cea_db(edid_ext, i, start, end) { 2816 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 2817 cea_db_payload_len(&edid_ext[i]) == 2) { 2818 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 2819 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 2820 } 2821 } 2822 2823 return false; 2824 } 2825 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 2826 2827 /** 2828 * drm_add_display_info - pull display info out if present 2829 * @edid: EDID data 2830 * @info: display info (attached to connector) 2831 * 2832 * Grab any available display info and stuff it into the drm_display_info 2833 * structure that's part of the connector. Useful for tracking bpp and 2834 * color spaces. 2835 */ 2836 static void drm_add_display_info(struct edid *edid, 2837 struct drm_display_info *info) 2838 { 2839 u8 *edid_ext; 2840 2841 info->width_mm = edid->width_cm * 10; 2842 info->height_mm = edid->height_cm * 10; 2843 2844 /* driver figures it out in this case */ 2845 info->bpc = 0; 2846 info->color_formats = 0; 2847 2848 if (edid->revision < 3) 2849 return; 2850 2851 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 2852 return; 2853 2854 /* Get data from CEA blocks if present */ 2855 edid_ext = drm_find_cea_extension(edid); 2856 if (edid_ext) { 2857 info->cea_rev = edid_ext[1]; 2858 2859 /* The existence of a CEA block should imply RGB support */ 2860 info->color_formats = DRM_COLOR_FORMAT_RGB444; 2861 if (edid_ext[3] & EDID_CEA_YCRCB444) 2862 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2863 if (edid_ext[3] & EDID_CEA_YCRCB422) 2864 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2865 } 2866 2867 /* Only defined for 1.4 with digital displays */ 2868 if (edid->revision < 4) 2869 return; 2870 2871 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 2872 case DRM_EDID_DIGITAL_DEPTH_6: 2873 info->bpc = 6; 2874 break; 2875 case DRM_EDID_DIGITAL_DEPTH_8: 2876 info->bpc = 8; 2877 break; 2878 case DRM_EDID_DIGITAL_DEPTH_10: 2879 info->bpc = 10; 2880 break; 2881 case DRM_EDID_DIGITAL_DEPTH_12: 2882 info->bpc = 12; 2883 break; 2884 case DRM_EDID_DIGITAL_DEPTH_14: 2885 info->bpc = 14; 2886 break; 2887 case DRM_EDID_DIGITAL_DEPTH_16: 2888 info->bpc = 16; 2889 break; 2890 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 2891 default: 2892 info->bpc = 0; 2893 break; 2894 } 2895 2896 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 2897 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 2898 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2899 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 2900 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2901 } 2902 2903 /** 2904 * drm_add_edid_modes - add modes from EDID data, if available 2905 * @connector: connector we're probing 2906 * @edid: edid data 2907 * 2908 * Add the specified modes to the connector's mode list. 2909 * 2910 * Return number of modes added or 0 if we couldn't find any. 2911 */ 2912 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 2913 { 2914 int num_modes = 0; 2915 u32 quirks; 2916 2917 if (edid == NULL) { 2918 return 0; 2919 } 2920 if (!drm_edid_is_valid(edid)) { 2921 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 2922 drm_get_connector_name(connector)); 2923 return 0; 2924 } 2925 2926 quirks = edid_get_quirks(edid); 2927 2928 /* 2929 * EDID spec says modes should be preferred in this order: 2930 * - preferred detailed mode 2931 * - other detailed modes from base block 2932 * - detailed modes from extension blocks 2933 * - CVT 3-byte code modes 2934 * - standard timing codes 2935 * - established timing codes 2936 * - modes inferred from GTF or CVT range information 2937 * 2938 * We get this pretty much right. 2939 * 2940 * XXX order for additional mode types in extension blocks? 2941 */ 2942 num_modes += add_detailed_modes(connector, edid, quirks); 2943 num_modes += add_cvt_modes(connector, edid); 2944 num_modes += add_standard_modes(connector, edid); 2945 num_modes += add_established_modes(connector, edid); 2946 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2947 num_modes += add_inferred_modes(connector, edid); 2948 num_modes += add_cea_modes(connector, edid); 2949 2950 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 2951 edid_fixup_preferred(connector, quirks); 2952 2953 drm_add_display_info(edid, &connector->display_info); 2954 2955 return num_modes; 2956 } 2957 EXPORT_SYMBOL(drm_add_edid_modes); 2958 2959 /** 2960 * drm_add_modes_noedid - add modes for the connectors without EDID 2961 * @connector: connector we're probing 2962 * @hdisplay: the horizontal display limit 2963 * @vdisplay: the vertical display limit 2964 * 2965 * Add the specified modes to the connector's mode list. Only when the 2966 * hdisplay/vdisplay is not beyond the given limit, it will be added. 2967 * 2968 * Return number of modes added or 0 if we couldn't find any. 2969 */ 2970 int drm_add_modes_noedid(struct drm_connector *connector, 2971 int hdisplay, int vdisplay) 2972 { 2973 int i, count, num_modes = 0; 2974 struct drm_display_mode *mode; 2975 struct drm_device *dev = connector->dev; 2976 2977 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); 2978 if (hdisplay < 0) 2979 hdisplay = 0; 2980 if (vdisplay < 0) 2981 vdisplay = 0; 2982 2983 for (i = 0; i < count; i++) { 2984 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2985 if (hdisplay && vdisplay) { 2986 /* 2987 * Only when two are valid, they will be used to check 2988 * whether the mode should be added to the mode list of 2989 * the connector. 2990 */ 2991 if (ptr->hdisplay > hdisplay || 2992 ptr->vdisplay > vdisplay) 2993 continue; 2994 } 2995 if (drm_mode_vrefresh(ptr) > 61) 2996 continue; 2997 mode = drm_mode_duplicate(dev, ptr); 2998 if (mode) { 2999 drm_mode_probed_add(connector, mode); 3000 num_modes++; 3001 } 3002 } 3003 return num_modes; 3004 } 3005 EXPORT_SYMBOL(drm_add_modes_noedid); 3006 3007 /** 3008 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3009 * data from a DRM display mode 3010 * @frame: HDMI AVI infoframe 3011 * @mode: DRM display mode 3012 * 3013 * Returns 0 on success or a negative error code on failure. 3014 */ 3015 int 3016 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3017 const struct drm_display_mode *mode) 3018 { 3019 int err; 3020 3021 if (!frame || !mode) 3022 return -EINVAL; 3023 3024 err = hdmi_avi_infoframe_init(frame); 3025 if (err < 0) 3026 return err; 3027 3028 frame->video_code = drm_match_cea_mode(mode); 3029 if (!frame->video_code) 3030 return 0; 3031 3032 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3033 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3034 3035 return 0; 3036 } 3037 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3038