1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 int modes; 100 }; 101 102 #define LEVEL_DMT 0 103 #define LEVEL_GTF 1 104 #define LEVEL_GTF2 2 105 #define LEVEL_CVT 3 106 107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 108 { \ 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 110 product_id), \ 111 .quirks = _quirks \ 112 } 113 114 static const struct edid_quirk { 115 u32 panel_id; 116 u32 quirks; 117 } edid_quirk_list[] = { 118 /* Acer AL1706 */ 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 120 /* Acer F51 */ 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 122 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 125 126 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 127 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 128 129 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 131 132 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 134 135 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 137 138 /* Belinea 10 15 55 */ 139 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 140 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 141 142 /* Envision Peripherals, Inc. EN-7100e */ 143 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 144 /* Envision EN2028 */ 145 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 146 147 /* Funai Electronics PM36B */ 148 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 149 EDID_QUIRK_DETAILED_IN_CM), 150 151 /* LG 27GP950 */ 152 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 153 154 /* LG 27GN950 */ 155 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 156 157 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 158 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 159 160 /* LG Philips LCD LP154W01-A5 */ 161 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 162 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 163 164 /* Samsung SyncMaster 205BW. Note: irony */ 165 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 166 /* Samsung SyncMaster 22[5-6]BW */ 167 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 168 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 169 170 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 171 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 172 173 /* ViewSonic VA2026w */ 174 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 175 176 /* Medion MD 30217 PG */ 177 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 178 179 /* Lenovo G50 */ 180 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 181 182 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 183 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 184 185 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 186 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 187 188 /* Valve Index Headset */ 189 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 206 207 /* HTC Vive and Vive Pro VR Headsets */ 208 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 210 211 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 212 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 216 217 /* Windows Mixed Reality Headsets */ 218 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 224 225 /* Sony PlayStation VR Headset */ 226 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 227 228 /* Sensics VR Headsets */ 229 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 230 231 /* OSVR HDK and HDK2 VR Headsets */ 232 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 233 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 234 }; 235 236 /* 237 * Autogenerated from the DMT spec. 238 * This table is copied from xfree86/modes/xf86EdidModes.c. 239 */ 240 static const struct drm_display_mode drm_dmt_modes[] = { 241 /* 0x01 - 640x350@85Hz */ 242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 243 736, 832, 0, 350, 382, 385, 445, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x02 - 640x400@85Hz */ 246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 247 736, 832, 0, 400, 401, 404, 445, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x03 - 720x400@85Hz */ 250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 251 828, 936, 0, 400, 401, 404, 446, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x04 - 640x480@60Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 255 752, 800, 0, 480, 490, 492, 525, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x05 - 640x480@72Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 259 704, 832, 0, 480, 489, 492, 520, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x06 - 640x480@75Hz */ 262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 263 720, 840, 0, 480, 481, 484, 500, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x07 - 640x480@85Hz */ 266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 267 752, 832, 0, 480, 481, 484, 509, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 269 /* 0x08 - 800x600@56Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 271 896, 1024, 0, 600, 601, 603, 625, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x09 - 800x600@60Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 275 968, 1056, 0, 600, 601, 605, 628, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0a - 800x600@72Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 279 976, 1040, 0, 600, 637, 643, 666, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0b - 800x600@75Hz */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 283 896, 1056, 0, 600, 601, 604, 625, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x0c - 800x600@85Hz */ 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 287 896, 1048, 0, 600, 601, 604, 631, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0d - 800x600@120Hz RB */ 290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 291 880, 960, 0, 600, 603, 607, 636, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x0e - 848x480@60Hz */ 294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 295 976, 1088, 0, 480, 486, 494, 517, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x0f - 1024x768@43Hz, interlace */ 298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 299 1208, 1264, 0, 768, 768, 776, 817, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 301 DRM_MODE_FLAG_INTERLACE) }, 302 /* 0x10 - 1024x768@60Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 304 1184, 1344, 0, 768, 771, 777, 806, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x11 - 1024x768@70Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 308 1184, 1328, 0, 768, 771, 777, 806, 0, 309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 310 /* 0x12 - 1024x768@75Hz */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 312 1136, 1312, 0, 768, 769, 772, 800, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x13 - 1024x768@85Hz */ 315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 316 1168, 1376, 0, 768, 769, 772, 808, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x14 - 1024x768@120Hz RB */ 319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 320 1104, 1184, 0, 768, 771, 775, 813, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x15 - 1152x864@75Hz */ 323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 324 1344, 1600, 0, 864, 865, 868, 900, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x55 - 1280x720@60Hz */ 327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 328 1430, 1650, 0, 720, 725, 730, 750, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x16 - 1280x768@60Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 790, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x17 - 1280x768@60Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 336 1472, 1664, 0, 768, 771, 778, 798, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x18 - 1280x768@75Hz */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 340 1488, 1696, 0, 768, 771, 778, 805, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x19 - 1280x768@85Hz */ 343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 344 1496, 1712, 0, 768, 771, 778, 809, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1a - 1280x768@120Hz RB */ 347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 348 1360, 1440, 0, 768, 771, 778, 813, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x1b - 1280x800@60Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 823, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x1c - 1280x800@60Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 356 1480, 1680, 0, 800, 803, 809, 831, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1d - 1280x800@75Hz */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 360 1488, 1696, 0, 800, 803, 809, 838, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x1e - 1280x800@85Hz */ 363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 364 1496, 1712, 0, 800, 803, 809, 843, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x1f - 1280x800@120Hz RB */ 367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 368 1360, 1440, 0, 800, 803, 809, 847, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x20 - 1280x960@60Hz */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 372 1488, 1800, 0, 960, 961, 964, 1000, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x21 - 1280x960@85Hz */ 375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 376 1504, 1728, 0, 960, 961, 964, 1011, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x22 - 1280x960@120Hz RB */ 379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 380 1360, 1440, 0, 960, 963, 967, 1017, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x23 - 1280x1024@60Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x24 - 1280x1024@75Hz */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x25 - 1280x1024@85Hz */ 391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x26 - 1280x1024@120Hz RB */ 395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x27 - 1360x768@60Hz */ 399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 400 1536, 1792, 0, 768, 771, 777, 795, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x28 - 1360x768@120Hz RB */ 403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 404 1440, 1520, 0, 768, 771, 776, 813, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 406 /* 0x51 - 1366x768@60Hz */ 407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 408 1579, 1792, 0, 768, 771, 774, 798, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x56 - 1366x768@60Hz */ 411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 412 1436, 1500, 0, 768, 769, 772, 800, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x29 - 1400x1050@60Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2a - 1400x1050@60Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2b - 1400x1050@75Hz */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x2c - 1400x1050@85Hz */ 427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x2d - 1400x1050@120Hz RB */ 431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x2e - 1440x900@60Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 926, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x2f - 1440x900@60Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 440 1672, 1904, 0, 900, 903, 909, 934, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x30 - 1440x900@75Hz */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 444 1688, 1936, 0, 900, 903, 909, 942, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x31 - 1440x900@85Hz */ 447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 448 1696, 1952, 0, 900, 903, 909, 948, 0, 449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x32 - 1440x900@120Hz RB */ 451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 452 1520, 1600, 0, 900, 903, 909, 953, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 454 /* 0x53 - 1600x900@60Hz */ 455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 456 1704, 1800, 0, 900, 901, 904, 1000, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x33 - 1600x1200@60Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x34 - 1600x1200@65Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x35 - 1600x1200@70Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x36 - 1600x1200@75Hz */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x37 - 1600x1200@85Hz */ 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x38 - 1600x1200@120Hz RB */ 479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x39 - 1680x1050@60Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3a - 1680x1050@60Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3b - 1680x1050@75Hz */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x3c - 1680x1050@85Hz */ 495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3d - 1680x1050@120Hz RB */ 499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x3e - 1792x1344@60Hz */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x3f - 1792x1344@75Hz */ 507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x40 - 1792x1344@120Hz RB */ 511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x41 - 1856x1392@60Hz */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x42 - 1856x1392@75Hz */ 519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x43 - 1856x1392@120Hz RB */ 523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x52 - 1920x1080@60Hz */ 527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x44 - 1920x1200@60Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x45 - 1920x1200@60Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x46 - 1920x1200@75Hz */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x47 - 1920x1200@85Hz */ 543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x48 - 1920x1200@120Hz RB */ 547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x49 - 1920x1440@60Hz */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4a - 1920x1440@75Hz */ 555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4b - 1920x1440@120Hz RB */ 559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x54 - 2048x1152@60Hz */ 563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4c - 2560x1600@60Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x4d - 2560x1600@60Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x4e - 2560x1600@75Hz */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 578 /* 0x4f - 2560x1600@85Hz */ 579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 582 /* 0x50 - 2560x1600@120Hz RB */ 583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x57 - 4096x2160@60Hz RB */ 587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 590 /* 0x58 - 4096x2160@59.94Hz RB */ 591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 594 }; 595 596 /* 597 * These more or less come from the DMT spec. The 720x400 modes are 598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 601 * mode. 602 * 603 * The DMT modes have been fact-checked; the rest are mild guesses. 604 */ 605 static const struct drm_display_mode edid_est_modes[] = { 606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 607 968, 1056, 0, 600, 601, 605, 628, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 610 896, 1024, 0, 600, 601, 603, 625, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 613 720, 840, 0, 480, 481, 484, 500, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 616 704, 832, 0, 480, 489, 492, 520, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 619 768, 864, 0, 480, 483, 486, 525, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 622 752, 800, 0, 480, 490, 492, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 625 846, 900, 0, 400, 421, 423, 449, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 628 846, 900, 0, 400, 412, 414, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 634 1136, 1312, 0, 768, 769, 772, 800, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 637 1184, 1328, 0, 768, 771, 777, 806, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 640 1184, 1344, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 643 1208, 1264, 0, 768, 768, 776, 817, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 646 928, 1152, 0, 624, 625, 628, 667, 0, 647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 649 896, 1056, 0, 600, 601, 604, 625, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 652 976, 1040, 0, 600, 637, 643, 666, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 655 1344, 1600, 0, 864, 865, 868, 900, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 657 }; 658 659 struct minimode { 660 short w; 661 short h; 662 short r; 663 short rb; 664 }; 665 666 static const struct minimode est3_modes[] = { 667 /* byte 6 */ 668 { 640, 350, 85, 0 }, 669 { 640, 400, 85, 0 }, 670 { 720, 400, 85, 0 }, 671 { 640, 480, 85, 0 }, 672 { 848, 480, 60, 0 }, 673 { 800, 600, 85, 0 }, 674 { 1024, 768, 85, 0 }, 675 { 1152, 864, 75, 0 }, 676 /* byte 7 */ 677 { 1280, 768, 60, 1 }, 678 { 1280, 768, 60, 0 }, 679 { 1280, 768, 75, 0 }, 680 { 1280, 768, 85, 0 }, 681 { 1280, 960, 60, 0 }, 682 { 1280, 960, 85, 0 }, 683 { 1280, 1024, 60, 0 }, 684 { 1280, 1024, 85, 0 }, 685 /* byte 8 */ 686 { 1360, 768, 60, 0 }, 687 { 1440, 900, 60, 1 }, 688 { 1440, 900, 60, 0 }, 689 { 1440, 900, 75, 0 }, 690 { 1440, 900, 85, 0 }, 691 { 1400, 1050, 60, 1 }, 692 { 1400, 1050, 60, 0 }, 693 { 1400, 1050, 75, 0 }, 694 /* byte 9 */ 695 { 1400, 1050, 85, 0 }, 696 { 1680, 1050, 60, 1 }, 697 { 1680, 1050, 60, 0 }, 698 { 1680, 1050, 75, 0 }, 699 { 1680, 1050, 85, 0 }, 700 { 1600, 1200, 60, 0 }, 701 { 1600, 1200, 65, 0 }, 702 { 1600, 1200, 70, 0 }, 703 /* byte 10 */ 704 { 1600, 1200, 75, 0 }, 705 { 1600, 1200, 85, 0 }, 706 { 1792, 1344, 60, 0 }, 707 { 1792, 1344, 75, 0 }, 708 { 1856, 1392, 60, 0 }, 709 { 1856, 1392, 75, 0 }, 710 { 1920, 1200, 60, 1 }, 711 { 1920, 1200, 60, 0 }, 712 /* byte 11 */ 713 { 1920, 1200, 75, 0 }, 714 { 1920, 1200, 85, 0 }, 715 { 1920, 1440, 60, 0 }, 716 { 1920, 1440, 75, 0 }, 717 }; 718 719 static const struct minimode extra_modes[] = { 720 { 1024, 576, 60, 0 }, 721 { 1366, 768, 60, 0 }, 722 { 1600, 900, 60, 0 }, 723 { 1680, 945, 60, 0 }, 724 { 1920, 1080, 60, 0 }, 725 { 2048, 1152, 60, 0 }, 726 { 2048, 1536, 60, 0 }, 727 }; 728 729 /* 730 * From CEA/CTA-861 spec. 731 * 732 * Do not access directly, instead always use cea_mode_for_vic(). 733 */ 734 static const struct drm_display_mode edid_cea_modes_1[] = { 735 /* 1 - 640x480@60Hz 4:3 */ 736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 737 752, 800, 0, 480, 490, 492, 525, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 740 /* 2 - 720x480@60Hz 4:3 */ 741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 742 798, 858, 0, 480, 489, 495, 525, 0, 743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 745 /* 3 - 720x480@60Hz 16:9 */ 746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 747 798, 858, 0, 480, 489, 495, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 750 /* 4 - 1280x720@60Hz 16:9 */ 751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 752 1430, 1650, 0, 720, 725, 730, 750, 0, 753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 755 /* 5 - 1920x1080i@60Hz 16:9 */ 756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 759 DRM_MODE_FLAG_INTERLACE), 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 6 - 720(1440)x480i@60Hz 4:3 */ 762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 763 801, 858, 0, 480, 488, 494, 525, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 767 /* 7 - 720(1440)x480i@60Hz 16:9 */ 768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 769 801, 858, 0, 480, 488, 494, 525, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 8 - 720(1440)x240@60Hz 4:3 */ 774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 775 801, 858, 0, 240, 244, 247, 262, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 777 DRM_MODE_FLAG_DBLCLK), 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 779 /* 9 - 720(1440)x240@60Hz 16:9 */ 780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 781 801, 858, 0, 240, 244, 247, 262, 0, 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 783 DRM_MODE_FLAG_DBLCLK), 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 785 /* 10 - 2880x480i@60Hz 4:3 */ 786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 480, 488, 494, 525, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 789 DRM_MODE_FLAG_INTERLACE), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 791 /* 11 - 2880x480i@60Hz 16:9 */ 792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 793 3204, 3432, 0, 480, 488, 494, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_INTERLACE), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 12 - 2880x240@60Hz 4:3 */ 798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 799 3204, 3432, 0, 240, 244, 247, 262, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 13 - 2880x240@60Hz 16:9 */ 803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 804 3204, 3432, 0, 240, 244, 247, 262, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 14 - 1440x480@60Hz 4:3 */ 808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 809 1596, 1716, 0, 480, 489, 495, 525, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 15 - 1440x480@60Hz 16:9 */ 813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 814 1596, 1716, 0, 480, 489, 495, 525, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 16 - 1920x1080@60Hz 16:9 */ 818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 17 - 720x576@50Hz 4:3 */ 823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 824 796, 864, 0, 576, 581, 586, 625, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 827 /* 18 - 720x576@50Hz 16:9 */ 828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 829 796, 864, 0, 576, 581, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 19 - 1280x720@50Hz 16:9 */ 833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 834 1760, 1980, 0, 720, 725, 730, 750, 0, 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 837 /* 20 - 1920x1080i@50Hz 16:9 */ 838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 841 DRM_MODE_FLAG_INTERLACE), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 21 - 720(1440)x576i@50Hz 4:3 */ 844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 845 795, 864, 0, 576, 580, 586, 625, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 849 /* 22 - 720(1440)x576i@50Hz 16:9 */ 850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 851 795, 864, 0, 576, 580, 586, 625, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 23 - 720(1440)x288@50Hz 4:3 */ 856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 857 795, 864, 0, 288, 290, 293, 312, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 859 DRM_MODE_FLAG_DBLCLK), 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 861 /* 24 - 720(1440)x288@50Hz 16:9 */ 862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 863 795, 864, 0, 288, 290, 293, 312, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 865 DRM_MODE_FLAG_DBLCLK), 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 25 - 2880x576i@50Hz 4:3 */ 868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 576, 580, 586, 625, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 871 DRM_MODE_FLAG_INTERLACE), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 873 /* 26 - 2880x576i@50Hz 16:9 */ 874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 875 3180, 3456, 0, 576, 580, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 27 - 2880x288@50Hz 4:3 */ 880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 881 3180, 3456, 0, 288, 290, 293, 312, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 884 /* 28 - 2880x288@50Hz 16:9 */ 885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 886 3180, 3456, 0, 288, 290, 293, 312, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 29 - 1440x576@50Hz 4:3 */ 890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 891 1592, 1728, 0, 576, 581, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 894 /* 30 - 1440x576@50Hz 16:9 */ 895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 896 1592, 1728, 0, 576, 581, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 31 - 1920x1080@50Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 32 - 1920x1080@24Hz 16:9 */ 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 33 - 1920x1080@25Hz 16:9 */ 910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 34 - 1920x1080@30Hz 16:9 */ 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 35 - 2880x480@60Hz 4:3 */ 920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 921 3192, 3432, 0, 480, 489, 495, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 36 - 2880x480@60Hz 16:9 */ 925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 926 3192, 3432, 0, 480, 489, 495, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 37 - 2880x576@50Hz 4:3 */ 930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 931 3184, 3456, 0, 576, 581, 586, 625, 0, 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 934 /* 38 - 2880x576@50Hz 16:9 */ 935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 936 3184, 3456, 0, 576, 581, 586, 625, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 39 - 1920x1080i@50Hz 16:9 */ 940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 943 DRM_MODE_FLAG_INTERLACE), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 40 - 1920x1080i@100Hz 16:9 */ 946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 949 DRM_MODE_FLAG_INTERLACE), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 41 - 1280x720@100Hz 16:9 */ 952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 953 1760, 1980, 0, 720, 725, 730, 750, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 42 - 720x576@100Hz 4:3 */ 957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 796, 864, 0, 576, 581, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 961 /* 43 - 720x576@100Hz 16:9 */ 962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 963 796, 864, 0, 576, 581, 586, 625, 0, 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 44 - 720(1440)x576i@100Hz 4:3 */ 967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 968 795, 864, 0, 576, 580, 586, 625, 0, 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 972 /* 45 - 720(1440)x576i@100Hz 16:9 */ 973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 974 795, 864, 0, 576, 580, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 978 /* 46 - 1920x1080i@120Hz 16:9 */ 979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 982 DRM_MODE_FLAG_INTERLACE), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 47 - 1280x720@120Hz 16:9 */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 986 1430, 1650, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 48 - 720x480@120Hz 4:3 */ 990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 991 798, 858, 0, 480, 489, 495, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 994 /* 49 - 720x480@120Hz 16:9 */ 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 996 798, 858, 0, 480, 489, 495, 525, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1001 801, 858, 0, 480, 488, 494, 525, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1005 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1007 801, 858, 0, 480, 488, 494, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 52 - 720x576@200Hz 4:3 */ 1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1013 796, 864, 0, 576, 581, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1016 /* 53 - 720x576@200Hz 16:9 */ 1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1018 796, 864, 0, 576, 581, 586, 625, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1021 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1023 795, 864, 0, 576, 580, 586, 625, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1027 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1029 795, 864, 0, 576, 580, 586, 625, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1033 /* 56 - 720x480@240Hz 4:3 */ 1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1035 798, 858, 0, 480, 489, 495, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1038 /* 57 - 720x480@240Hz 16:9 */ 1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1040 798, 858, 0, 480, 489, 495, 525, 0, 1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1045 801, 858, 0, 480, 488, 494, 525, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1049 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1051 801, 858, 0, 480, 488, 494, 525, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 60 - 1280x720@24Hz 16:9 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 61 - 1280x720@25Hz 16:9 */ 1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1062 3740, 3960, 0, 720, 725, 730, 750, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 62 - 1280x720@30Hz 16:9 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1067 3080, 3300, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 63 - 1920x1080@120Hz 16:9 */ 1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1075 /* 64 - 1920x1080@100Hz 16:9 */ 1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1080 /* 65 - 1280x720@24Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 66 - 1280x720@25Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1087 3740, 3960, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 67 - 1280x720@30Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1092 3080, 3300, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 68 - 1280x720@50Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1097 1760, 1980, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 69 - 1280x720@60Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1102 1430, 1650, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 70 - 1280x720@100Hz 64:27 */ 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1107 1760, 1980, 0, 720, 725, 730, 750, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 71 - 1280x720@120Hz 64:27 */ 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1112 1430, 1650, 0, 720, 725, 730, 750, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 72 - 1920x1080@24Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 73 - 1920x1080@25Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 74 - 1920x1080@30Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 75 - 1920x1080@50Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 76 - 1920x1080@60Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 77 - 1920x1080@100Hz 64:27 */ 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 78 - 1920x1080@120Hz 64:27 */ 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 79 - 1680x720@24Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1152 3080, 3300, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 80 - 1680x720@25Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1157 2948, 3168, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 81 - 1680x720@30Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1162 2420, 2640, 0, 720, 725, 730, 750, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 82 - 1680x720@50Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1167 1980, 2200, 0, 720, 725, 730, 750, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 83 - 1680x720@60Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1172 1980, 2200, 0, 720, 725, 730, 750, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 84 - 1680x720@100Hz 64:27 */ 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1177 1780, 2000, 0, 720, 725, 730, 825, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 85 - 1680x720@120Hz 64:27 */ 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1182 1780, 2000, 0, 720, 725, 730, 825, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 86 - 2560x1080@24Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 87 - 2560x1080@25Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 88 - 2560x1080@30Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 89 - 2560x1080@50Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 90 - 2560x1080@60Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 91 - 2560x1080@100Hz 64:27 */ 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1215 /* 92 - 2560x1080@120Hz 64:27 */ 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1220 /* 93 - 3840x2160@24Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 94 - 3840x2160@25Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 95 - 3840x2160@30Hz 16:9 */ 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1235 /* 96 - 3840x2160@50Hz 16:9 */ 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1240 /* 97 - 3840x2160@60Hz 16:9 */ 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1245 /* 98 - 4096x2160@24Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 99 - 4096x2160@25Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 100 - 4096x2160@30Hz 256:135 */ 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1260 /* 101 - 4096x2160@50Hz 256:135 */ 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1265 /* 102 - 4096x2160@60Hz 256:135 */ 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1270 /* 103 - 3840x2160@24Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 104 - 3840x2160@25Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 105 - 3840x2160@30Hz 64:27 */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1285 /* 106 - 3840x2160@50Hz 64:27 */ 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 107 - 3840x2160@60Hz 64:27 */ 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 108 - 1280x720@48Hz 16:9 */ 1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1297 2280, 2500, 0, 720, 725, 730, 750, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1300 /* 109 - 1280x720@48Hz 64:27 */ 1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1302 2280, 2500, 0, 720, 725, 730, 750, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 110 - 1680x720@48Hz 64:27 */ 1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1307 2530, 2750, 0, 720, 725, 730, 750, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 111 - 1920x1080@48Hz 16:9 */ 1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 112 - 1920x1080@48Hz 64:27 */ 1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1320 /* 113 - 2560x1080@48Hz 64:27 */ 1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 114 - 3840x2160@48Hz 16:9 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 115 - 4096x2160@48Hz 256:135 */ 1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1335 /* 116 - 3840x2160@48Hz 64:27 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 117 - 3840x2160@100Hz 16:9 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1345 /* 118 - 3840x2160@120Hz 16:9 */ 1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1350 /* 119 - 3840x2160@100Hz 64:27 */ 1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 120 - 3840x2160@120Hz 64:27 */ 1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 121 - 5120x2160@24Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 122 - 5120x2160@25Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 123 - 5120x2160@30Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 124 - 5120x2160@48Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 /* 125 - 5120x2160@50Hz 64:27 */ 1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1385 /* 126 - 5120x2160@60Hz 64:27 */ 1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1390 /* 127 - 5120x2160@100Hz 64:27 */ 1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1395 }; 1396 1397 /* 1398 * From CEA/CTA-861 spec. 1399 * 1400 * Do not access directly, instead always use cea_mode_for_vic(). 1401 */ 1402 static const struct drm_display_mode edid_cea_modes_193[] = { 1403 /* 193 - 5120x2160@120Hz 64:27 */ 1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1408 /* 194 - 7680x4320@24Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 195 - 7680x4320@25Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 196 - 7680x4320@30Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 197 - 7680x4320@48Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 198 - 7680x4320@50Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 199 - 7680x4320@60Hz 16:9 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1438 /* 200 - 7680x4320@100Hz 16:9 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1443 /* 201 - 7680x4320@120Hz 16:9 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1448 /* 202 - 7680x4320@24Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 203 - 7680x4320@25Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 204 - 7680x4320@30Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 205 - 7680x4320@48Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 206 - 7680x4320@50Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 207 - 7680x4320@60Hz 64:27 */ 1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 208 - 7680x4320@100Hz 64:27 */ 1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 209 - 7680x4320@120Hz 64:27 */ 1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 210 - 10240x4320@24Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 211 - 10240x4320@25Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 212 - 10240x4320@30Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 213 - 10240x4320@48Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 214 - 10240x4320@50Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 215 - 10240x4320@60Hz 64:27 */ 1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1518 /* 216 - 10240x4320@100Hz 64:27 */ 1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1523 /* 217 - 10240x4320@120Hz 64:27 */ 1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1528 /* 218 - 4096x2160@100Hz 256:135 */ 1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1533 /* 219 - 4096x2160@120Hz 256:135 */ 1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1538 }; 1539 1540 /* 1541 * HDMI 1.4 4k modes. Index using the VIC. 1542 */ 1543 static const struct drm_display_mode edid_4k_modes[] = { 1544 /* 0 - dummy, VICs start at 1 */ 1545 { }, 1546 /* 1 - 3840x2160@30Hz */ 1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1548 3840, 4016, 4104, 4400, 0, 1549 2160, 2168, 2178, 2250, 0, 1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1552 /* 2 - 3840x2160@25Hz */ 1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1554 3840, 4896, 4984, 5280, 0, 1555 2160, 2168, 2178, 2250, 0, 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1558 /* 3 - 3840x2160@24Hz */ 1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1560 3840, 5116, 5204, 5500, 0, 1561 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 4 - 4096x2160@24Hz (SMPTE) */ 1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1566 4096, 5116, 5204, 5500, 0, 1567 2160, 2168, 2178, 2250, 0, 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1570 }; 1571 1572 /*** DDC fetch and block validation ***/ 1573 1574 /* 1575 * The opaque EDID type, internal to drm_edid.c. 1576 */ 1577 struct drm_edid { 1578 /* Size allocated for edid */ 1579 size_t size; 1580 const struct edid *edid; 1581 }; 1582 1583 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1584 1585 static int edid_hfeeodb_block_count(const struct edid *edid) 1586 { 1587 int eeodb = edid_hfeeodb_extension_block_count(edid); 1588 1589 return eeodb ? eeodb + 1 : 0; 1590 } 1591 1592 static int edid_extension_block_count(const struct edid *edid) 1593 { 1594 return edid->extensions; 1595 } 1596 1597 static int edid_block_count(const struct edid *edid) 1598 { 1599 return edid_extension_block_count(edid) + 1; 1600 } 1601 1602 static int edid_size_by_blocks(int num_blocks) 1603 { 1604 return num_blocks * EDID_LENGTH; 1605 } 1606 1607 static int edid_size(const struct edid *edid) 1608 { 1609 return edid_size_by_blocks(edid_block_count(edid)); 1610 } 1611 1612 static const void *edid_block_data(const struct edid *edid, int index) 1613 { 1614 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1615 1616 return edid + index; 1617 } 1618 1619 static const void *edid_extension_block_data(const struct edid *edid, int index) 1620 { 1621 return edid_block_data(edid, index + 1); 1622 } 1623 1624 /* EDID block count indicated in EDID, may exceed allocated size */ 1625 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1626 { 1627 int num_blocks; 1628 1629 /* Starting point */ 1630 num_blocks = edid_block_count(drm_edid->edid); 1631 1632 /* HF-EEODB override */ 1633 if (drm_edid->size >= edid_size_by_blocks(2)) { 1634 int eeodb; 1635 1636 /* 1637 * Note: HF-EEODB may specify a smaller extension count than the 1638 * regular one. Unlike in buffer allocation, here we can use it. 1639 */ 1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1641 if (eeodb) 1642 num_blocks = eeodb; 1643 } 1644 1645 return num_blocks; 1646 } 1647 1648 /* EDID block count, limited by allocated size */ 1649 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1650 { 1651 /* Limit by allocated size */ 1652 return min(__drm_edid_block_count(drm_edid), 1653 (int)drm_edid->size / EDID_LENGTH); 1654 } 1655 1656 /* EDID extension block count, limited by allocated size */ 1657 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1658 { 1659 return drm_edid_block_count(drm_edid) - 1; 1660 } 1661 1662 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1663 { 1664 return edid_block_data(drm_edid->edid, index); 1665 } 1666 1667 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1668 int index) 1669 { 1670 return edid_extension_block_data(drm_edid->edid, index); 1671 } 1672 1673 /* 1674 * Initializer helper for legacy interfaces, where we have no choice but to 1675 * trust edid size. Not for general purpose use. 1676 */ 1677 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1678 const struct edid *edid) 1679 { 1680 if (!edid) 1681 return NULL; 1682 1683 memset(drm_edid, 0, sizeof(*drm_edid)); 1684 1685 drm_edid->edid = edid; 1686 drm_edid->size = edid_size(edid); 1687 1688 return drm_edid; 1689 } 1690 1691 /* 1692 * EDID base and extension block iterator. 1693 * 1694 * struct drm_edid_iter iter; 1695 * const u8 *block; 1696 * 1697 * drm_edid_iter_begin(drm_edid, &iter); 1698 * drm_edid_iter_for_each(block, &iter) { 1699 * // do stuff with block 1700 * } 1701 * drm_edid_iter_end(&iter); 1702 */ 1703 struct drm_edid_iter { 1704 const struct drm_edid *drm_edid; 1705 1706 /* Current block index. */ 1707 int index; 1708 }; 1709 1710 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1711 struct drm_edid_iter *iter) 1712 { 1713 memset(iter, 0, sizeof(*iter)); 1714 1715 iter->drm_edid = drm_edid; 1716 } 1717 1718 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1719 { 1720 const void *block = NULL; 1721 1722 if (!iter->drm_edid) 1723 return NULL; 1724 1725 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1726 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1727 1728 return block; 1729 } 1730 1731 #define drm_edid_iter_for_each(__block, __iter) \ 1732 while (((__block) = __drm_edid_iter_next(__iter))) 1733 1734 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1735 { 1736 memset(iter, 0, sizeof(*iter)); 1737 } 1738 1739 static const u8 edid_header[] = { 1740 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1741 }; 1742 1743 static void edid_header_fix(void *edid) 1744 { 1745 memcpy(edid, edid_header, sizeof(edid_header)); 1746 } 1747 1748 /** 1749 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1750 * @_edid: pointer to raw base EDID block 1751 * 1752 * Sanity check the header of the base EDID block. 1753 * 1754 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1755 */ 1756 int drm_edid_header_is_valid(const void *_edid) 1757 { 1758 const struct edid *edid = _edid; 1759 int i, score = 0; 1760 1761 for (i = 0; i < sizeof(edid_header); i++) { 1762 if (edid->header[i] == edid_header[i]) 1763 score++; 1764 } 1765 1766 return score; 1767 } 1768 EXPORT_SYMBOL(drm_edid_header_is_valid); 1769 1770 static int edid_fixup __read_mostly = 6; 1771 module_param_named(edid_fixup, edid_fixup, int, 0400); 1772 MODULE_PARM_DESC(edid_fixup, 1773 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1774 1775 static int edid_block_compute_checksum(const void *_block) 1776 { 1777 const u8 *block = _block; 1778 int i; 1779 u8 csum = 0, crc = 0; 1780 1781 for (i = 0; i < EDID_LENGTH - 1; i++) 1782 csum += block[i]; 1783 1784 crc = 0x100 - csum; 1785 1786 return crc; 1787 } 1788 1789 static int edid_block_get_checksum(const void *_block) 1790 { 1791 const struct edid *block = _block; 1792 1793 return block->checksum; 1794 } 1795 1796 static int edid_block_tag(const void *_block) 1797 { 1798 const u8 *block = _block; 1799 1800 return block[0]; 1801 } 1802 1803 static bool edid_block_is_zero(const void *edid) 1804 { 1805 return !memchr_inv(edid, 0, EDID_LENGTH); 1806 } 1807 1808 /** 1809 * drm_edid_are_equal - compare two edid blobs. 1810 * @edid1: pointer to first blob 1811 * @edid2: pointer to second blob 1812 * This helper can be used during probing to determine if 1813 * edid had changed. 1814 */ 1815 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1816 { 1817 int edid1_len, edid2_len; 1818 bool edid1_present = edid1 != NULL; 1819 bool edid2_present = edid2 != NULL; 1820 1821 if (edid1_present != edid2_present) 1822 return false; 1823 1824 if (edid1) { 1825 edid1_len = edid_size(edid1); 1826 edid2_len = edid_size(edid2); 1827 1828 if (edid1_len != edid2_len) 1829 return false; 1830 1831 if (memcmp(edid1, edid2, edid1_len)) 1832 return false; 1833 } 1834 1835 return true; 1836 } 1837 EXPORT_SYMBOL(drm_edid_are_equal); 1838 1839 enum edid_block_status { 1840 EDID_BLOCK_OK = 0, 1841 EDID_BLOCK_READ_FAIL, 1842 EDID_BLOCK_NULL, 1843 EDID_BLOCK_ZERO, 1844 EDID_BLOCK_HEADER_CORRUPT, 1845 EDID_BLOCK_HEADER_REPAIR, 1846 EDID_BLOCK_HEADER_FIXED, 1847 EDID_BLOCK_CHECKSUM, 1848 EDID_BLOCK_VERSION, 1849 }; 1850 1851 static enum edid_block_status edid_block_check(const void *_block, 1852 bool is_base_block) 1853 { 1854 const struct edid *block = _block; 1855 1856 if (!block) 1857 return EDID_BLOCK_NULL; 1858 1859 if (is_base_block) { 1860 int score = drm_edid_header_is_valid(block); 1861 1862 if (score < clamp(edid_fixup, 0, 8)) { 1863 if (edid_block_is_zero(block)) 1864 return EDID_BLOCK_ZERO; 1865 else 1866 return EDID_BLOCK_HEADER_CORRUPT; 1867 } 1868 1869 if (score < 8) 1870 return EDID_BLOCK_HEADER_REPAIR; 1871 } 1872 1873 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1874 if (edid_block_is_zero(block)) 1875 return EDID_BLOCK_ZERO; 1876 else 1877 return EDID_BLOCK_CHECKSUM; 1878 } 1879 1880 if (is_base_block) { 1881 if (block->version != 1) 1882 return EDID_BLOCK_VERSION; 1883 } 1884 1885 return EDID_BLOCK_OK; 1886 } 1887 1888 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1889 { 1890 return status == EDID_BLOCK_OK || 1891 status == EDID_BLOCK_HEADER_FIXED || 1892 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1893 } 1894 1895 static bool edid_block_valid(const void *block, bool base) 1896 { 1897 return edid_block_status_valid(edid_block_check(block, base), 1898 edid_block_tag(block)); 1899 } 1900 1901 static void edid_block_status_print(enum edid_block_status status, 1902 const struct edid *block, 1903 int block_num) 1904 { 1905 switch (status) { 1906 case EDID_BLOCK_OK: 1907 break; 1908 case EDID_BLOCK_READ_FAIL: 1909 pr_debug("EDID block %d read failed\n", block_num); 1910 break; 1911 case EDID_BLOCK_NULL: 1912 pr_debug("EDID block %d pointer is NULL\n", block_num); 1913 break; 1914 case EDID_BLOCK_ZERO: 1915 pr_notice("EDID block %d is all zeroes\n", block_num); 1916 break; 1917 case EDID_BLOCK_HEADER_CORRUPT: 1918 pr_notice("EDID has corrupt header\n"); 1919 break; 1920 case EDID_BLOCK_HEADER_REPAIR: 1921 pr_debug("EDID corrupt header needs repair\n"); 1922 break; 1923 case EDID_BLOCK_HEADER_FIXED: 1924 pr_debug("EDID corrupt header fixed\n"); 1925 break; 1926 case EDID_BLOCK_CHECKSUM: 1927 if (edid_block_status_valid(status, edid_block_tag(block))) { 1928 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1929 block_num, edid_block_tag(block), 1930 edid_block_compute_checksum(block)); 1931 } else { 1932 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1933 block_num, edid_block_tag(block), 1934 edid_block_compute_checksum(block)); 1935 } 1936 break; 1937 case EDID_BLOCK_VERSION: 1938 pr_notice("EDID has major version %d, instead of 1\n", 1939 block->version); 1940 break; 1941 default: 1942 WARN(1, "EDID block %d unknown edid block status code %d\n", 1943 block_num, status); 1944 break; 1945 } 1946 } 1947 1948 static void edid_block_dump(const char *level, const void *block, int block_num) 1949 { 1950 enum edid_block_status status; 1951 char prefix[20]; 1952 1953 status = edid_block_check(block, block_num == 0); 1954 if (status == EDID_BLOCK_ZERO) 1955 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1956 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1957 sprintf(prefix, "\t[%02x] BAD ", block_num); 1958 else 1959 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1960 1961 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1962 block, EDID_LENGTH, false); 1963 } 1964 1965 /** 1966 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1967 * @_block: pointer to raw EDID block 1968 * @block_num: type of block to validate (0 for base, extension otherwise) 1969 * @print_bad_edid: if true, dump bad EDID blocks to the console 1970 * @edid_corrupt: if true, the header or checksum is invalid 1971 * 1972 * Validate a base or extension EDID block and optionally dump bad blocks to 1973 * the console. 1974 * 1975 * Return: True if the block is valid, false otherwise. 1976 */ 1977 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1978 bool *edid_corrupt) 1979 { 1980 struct edid *block = (struct edid *)_block; 1981 enum edid_block_status status; 1982 bool is_base_block = block_num == 0; 1983 bool valid; 1984 1985 if (WARN_ON(!block)) 1986 return false; 1987 1988 status = edid_block_check(block, is_base_block); 1989 if (status == EDID_BLOCK_HEADER_REPAIR) { 1990 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1991 edid_header_fix(block); 1992 1993 /* Retry with fixed header, update status if that worked. */ 1994 status = edid_block_check(block, is_base_block); 1995 if (status == EDID_BLOCK_OK) 1996 status = EDID_BLOCK_HEADER_FIXED; 1997 } 1998 1999 if (edid_corrupt) { 2000 /* 2001 * Unknown major version isn't corrupt but we can't use it. Only 2002 * the base block can reset edid_corrupt to false. 2003 */ 2004 if (is_base_block && 2005 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2006 *edid_corrupt = false; 2007 else if (status != EDID_BLOCK_OK) 2008 *edid_corrupt = true; 2009 } 2010 2011 edid_block_status_print(status, block, block_num); 2012 2013 /* Determine whether we can use this block with this status. */ 2014 valid = edid_block_status_valid(status, edid_block_tag(block)); 2015 2016 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2017 pr_notice("Raw EDID:\n"); 2018 edid_block_dump(KERN_NOTICE, block, block_num); 2019 } 2020 2021 return valid; 2022 } 2023 EXPORT_SYMBOL(drm_edid_block_valid); 2024 2025 /** 2026 * drm_edid_is_valid - sanity check EDID data 2027 * @edid: EDID data 2028 * 2029 * Sanity-check an entire EDID record (including extensions) 2030 * 2031 * Return: True if the EDID data is valid, false otherwise. 2032 */ 2033 bool drm_edid_is_valid(struct edid *edid) 2034 { 2035 int i; 2036 2037 if (!edid) 2038 return false; 2039 2040 for (i = 0; i < edid_block_count(edid); i++) { 2041 void *block = (void *)edid_block_data(edid, i); 2042 2043 if (!drm_edid_block_valid(block, i, true, NULL)) 2044 return false; 2045 } 2046 2047 return true; 2048 } 2049 EXPORT_SYMBOL(drm_edid_is_valid); 2050 2051 /** 2052 * drm_edid_valid - sanity check EDID data 2053 * @drm_edid: EDID data 2054 * 2055 * Sanity check an EDID. Cross check block count against allocated size and 2056 * checksum the blocks. 2057 * 2058 * Return: True if the EDID data is valid, false otherwise. 2059 */ 2060 bool drm_edid_valid(const struct drm_edid *drm_edid) 2061 { 2062 int i; 2063 2064 if (!drm_edid) 2065 return false; 2066 2067 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2068 return false; 2069 2070 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2071 const void *block = drm_edid_block_data(drm_edid, i); 2072 2073 if (!edid_block_valid(block, i == 0)) 2074 return false; 2075 } 2076 2077 return true; 2078 } 2079 EXPORT_SYMBOL(drm_edid_valid); 2080 2081 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2082 size_t *alloc_size) 2083 { 2084 struct edid *new; 2085 int i, valid_blocks = 0; 2086 2087 /* 2088 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2089 * back to regular extension count here. We don't want to start 2090 * modifying the HF-EEODB extension too. 2091 */ 2092 for (i = 0; i < edid_block_count(edid); i++) { 2093 const void *src_block = edid_block_data(edid, i); 2094 2095 if (edid_block_valid(src_block, i == 0)) { 2096 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2097 2098 memmove(dst_block, src_block, EDID_LENGTH); 2099 valid_blocks++; 2100 } 2101 } 2102 2103 /* We already trusted the base block to be valid here... */ 2104 if (WARN_ON(!valid_blocks)) { 2105 kfree(edid); 2106 return NULL; 2107 } 2108 2109 edid->extensions = valid_blocks - 1; 2110 edid->checksum = edid_block_compute_checksum(edid); 2111 2112 *alloc_size = edid_size_by_blocks(valid_blocks); 2113 2114 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2115 if (!new) 2116 kfree(edid); 2117 2118 return new; 2119 } 2120 2121 #define DDC_SEGMENT_ADDR 0x30 2122 /** 2123 * drm_do_probe_ddc_edid() - get EDID information via I2C 2124 * @data: I2C device adapter 2125 * @buf: EDID data buffer to be filled 2126 * @block: 128 byte EDID block to start fetching from 2127 * @len: EDID data buffer length to fetch 2128 * 2129 * Try to fetch EDID information by calling I2C driver functions. 2130 * 2131 * Return: 0 on success or -1 on failure. 2132 */ 2133 static int 2134 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2135 { 2136 struct i2c_adapter *adapter = data; 2137 unsigned char start = block * EDID_LENGTH; 2138 unsigned char segment = block >> 1; 2139 unsigned char xfers = segment ? 3 : 2; 2140 int ret, retries = 5; 2141 2142 /* 2143 * The core I2C driver will automatically retry the transfer if the 2144 * adapter reports EAGAIN. However, we find that bit-banging transfers 2145 * are susceptible to errors under a heavily loaded machine and 2146 * generate spurious NAKs and timeouts. Retrying the transfer 2147 * of the individual block a few times seems to overcome this. 2148 */ 2149 do { 2150 struct i2c_msg msgs[] = { 2151 { 2152 .addr = DDC_SEGMENT_ADDR, 2153 .flags = 0, 2154 .len = 1, 2155 .buf = &segment, 2156 }, { 2157 .addr = DDC_ADDR, 2158 .flags = 0, 2159 .len = 1, 2160 .buf = &start, 2161 }, { 2162 .addr = DDC_ADDR, 2163 .flags = I2C_M_RD, 2164 .len = len, 2165 .buf = buf, 2166 } 2167 }; 2168 2169 /* 2170 * Avoid sending the segment addr to not upset non-compliant 2171 * DDC monitors. 2172 */ 2173 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2174 2175 if (ret == -ENXIO) { 2176 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2177 adapter->name); 2178 break; 2179 } 2180 } while (ret != xfers && --retries); 2181 2182 return ret == xfers ? 0 : -1; 2183 } 2184 2185 static void connector_bad_edid(struct drm_connector *connector, 2186 const struct edid *edid, int num_blocks) 2187 { 2188 int i; 2189 u8 last_block; 2190 2191 /* 2192 * 0x7e in the EDID is the number of extension blocks. The EDID 2193 * is 1 (base block) + num_ext_blocks big. That means we can think 2194 * of 0x7e in the EDID of the _index_ of the last block in the 2195 * combined chunk of memory. 2196 */ 2197 last_block = edid->extensions; 2198 2199 /* Calculate real checksum for the last edid extension block data */ 2200 if (last_block < num_blocks) 2201 connector->real_edid_checksum = 2202 edid_block_compute_checksum(edid + last_block); 2203 2204 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2205 return; 2206 2207 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2208 connector->base.id, connector->name); 2209 for (i = 0; i < num_blocks; i++) 2210 edid_block_dump(KERN_DEBUG, edid + i, i); 2211 } 2212 2213 /* Get override or firmware EDID */ 2214 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2215 { 2216 const struct drm_edid *override = NULL; 2217 2218 mutex_lock(&connector->edid_override_mutex); 2219 2220 if (connector->edid_override) 2221 override = drm_edid_dup(connector->edid_override); 2222 2223 mutex_unlock(&connector->edid_override_mutex); 2224 2225 if (!override) 2226 override = drm_edid_load_firmware(connector); 2227 2228 return IS_ERR(override) ? NULL : override; 2229 } 2230 2231 /* For debugfs edid_override implementation */ 2232 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2233 { 2234 const struct drm_edid *drm_edid; 2235 2236 mutex_lock(&connector->edid_override_mutex); 2237 2238 drm_edid = connector->edid_override; 2239 if (drm_edid) 2240 seq_write(m, drm_edid->edid, drm_edid->size); 2241 2242 mutex_unlock(&connector->edid_override_mutex); 2243 2244 return 0; 2245 } 2246 2247 /* For debugfs edid_override implementation */ 2248 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2249 size_t size) 2250 { 2251 const struct drm_edid *drm_edid; 2252 2253 drm_edid = drm_edid_alloc(edid, size); 2254 if (!drm_edid_valid(drm_edid)) { 2255 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2256 connector->base.id, connector->name); 2257 drm_edid_free(drm_edid); 2258 return -EINVAL; 2259 } 2260 2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2262 connector->base.id, connector->name); 2263 2264 mutex_lock(&connector->edid_override_mutex); 2265 2266 drm_edid_free(connector->edid_override); 2267 connector->edid_override = drm_edid; 2268 2269 mutex_unlock(&connector->edid_override_mutex); 2270 2271 return 0; 2272 } 2273 2274 /* For debugfs edid_override implementation */ 2275 int drm_edid_override_reset(struct drm_connector *connector) 2276 { 2277 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2278 connector->base.id, connector->name); 2279 2280 mutex_lock(&connector->edid_override_mutex); 2281 2282 drm_edid_free(connector->edid_override); 2283 connector->edid_override = NULL; 2284 2285 mutex_unlock(&connector->edid_override_mutex); 2286 2287 return 0; 2288 } 2289 2290 /** 2291 * drm_edid_override_connector_update - add modes from override/firmware EDID 2292 * @connector: connector we're probing 2293 * 2294 * Add modes from the override/firmware EDID, if available. Only to be used from 2295 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2296 * failed during drm_get_edid() and caused the override/firmware EDID to be 2297 * skipped. 2298 * 2299 * Return: The number of modes added or 0 if we couldn't find any. 2300 */ 2301 int drm_edid_override_connector_update(struct drm_connector *connector) 2302 { 2303 const struct drm_edid *override; 2304 int num_modes = 0; 2305 2306 override = drm_edid_override_get(connector); 2307 if (override) { 2308 num_modes = drm_edid_connector_update(connector, override); 2309 2310 drm_edid_free(override); 2311 2312 drm_dbg_kms(connector->dev, 2313 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2314 connector->base.id, connector->name, num_modes); 2315 } 2316 2317 return num_modes; 2318 } 2319 EXPORT_SYMBOL(drm_edid_override_connector_update); 2320 2321 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2322 2323 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2324 read_block_fn read_block, 2325 void *context) 2326 { 2327 enum edid_block_status status; 2328 bool is_base_block = block_num == 0; 2329 int try; 2330 2331 for (try = 0; try < 4; try++) { 2332 if (read_block(context, block, block_num, EDID_LENGTH)) 2333 return EDID_BLOCK_READ_FAIL; 2334 2335 status = edid_block_check(block, is_base_block); 2336 if (status == EDID_BLOCK_HEADER_REPAIR) { 2337 edid_header_fix(block); 2338 2339 /* Retry with fixed header, update status if that worked. */ 2340 status = edid_block_check(block, is_base_block); 2341 if (status == EDID_BLOCK_OK) 2342 status = EDID_BLOCK_HEADER_FIXED; 2343 } 2344 2345 if (edid_block_status_valid(status, edid_block_tag(block))) 2346 break; 2347 2348 /* Fail early for unrepairable base block all zeros. */ 2349 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2350 break; 2351 } 2352 2353 return status; 2354 } 2355 2356 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2357 read_block_fn read_block, void *context, 2358 size_t *size) 2359 { 2360 enum edid_block_status status; 2361 int i, num_blocks, invalid_blocks = 0; 2362 const struct drm_edid *override; 2363 struct edid *edid, *new; 2364 size_t alloc_size = EDID_LENGTH; 2365 2366 override = drm_edid_override_get(connector); 2367 if (override) { 2368 alloc_size = override->size; 2369 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2370 drm_edid_free(override); 2371 if (!edid) 2372 return NULL; 2373 goto ok; 2374 } 2375 2376 edid = kmalloc(alloc_size, GFP_KERNEL); 2377 if (!edid) 2378 return NULL; 2379 2380 status = edid_block_read(edid, 0, read_block, context); 2381 2382 edid_block_status_print(status, edid, 0); 2383 2384 if (status == EDID_BLOCK_READ_FAIL) 2385 goto fail; 2386 2387 /* FIXME: Clarify what a corrupt EDID actually means. */ 2388 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2389 connector->edid_corrupt = false; 2390 else 2391 connector->edid_corrupt = true; 2392 2393 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2394 if (status == EDID_BLOCK_ZERO) 2395 connector->null_edid_counter++; 2396 2397 connector_bad_edid(connector, edid, 1); 2398 goto fail; 2399 } 2400 2401 if (!edid_extension_block_count(edid)) 2402 goto ok; 2403 2404 alloc_size = edid_size(edid); 2405 new = krealloc(edid, alloc_size, GFP_KERNEL); 2406 if (!new) 2407 goto fail; 2408 edid = new; 2409 2410 num_blocks = edid_block_count(edid); 2411 for (i = 1; i < num_blocks; i++) { 2412 void *block = (void *)edid_block_data(edid, i); 2413 2414 status = edid_block_read(block, i, read_block, context); 2415 2416 edid_block_status_print(status, block, i); 2417 2418 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2419 if (status == EDID_BLOCK_READ_FAIL) 2420 goto fail; 2421 invalid_blocks++; 2422 } else if (i == 1) { 2423 /* 2424 * If the first EDID extension is a CTA extension, and 2425 * the first Data Block is HF-EEODB, override the 2426 * extension block count. 2427 * 2428 * Note: HF-EEODB could specify a smaller extension 2429 * count too, but we can't risk allocating a smaller 2430 * amount. 2431 */ 2432 int eeodb = edid_hfeeodb_block_count(edid); 2433 2434 if (eeodb > num_blocks) { 2435 num_blocks = eeodb; 2436 alloc_size = edid_size_by_blocks(num_blocks); 2437 new = krealloc(edid, alloc_size, GFP_KERNEL); 2438 if (!new) 2439 goto fail; 2440 edid = new; 2441 } 2442 } 2443 } 2444 2445 if (invalid_blocks) { 2446 connector_bad_edid(connector, edid, num_blocks); 2447 2448 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2449 } 2450 2451 ok: 2452 if (size) 2453 *size = alloc_size; 2454 2455 return edid; 2456 2457 fail: 2458 kfree(edid); 2459 return NULL; 2460 } 2461 2462 /** 2463 * drm_do_get_edid - get EDID data using a custom EDID block read function 2464 * @connector: connector we're probing 2465 * @read_block: EDID block read function 2466 * @context: private data passed to the block read function 2467 * 2468 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2469 * exposes a different interface to read EDID blocks this function can be used 2470 * to get EDID data using a custom block read function. 2471 * 2472 * As in the general case the DDC bus is accessible by the kernel at the I2C 2473 * level, drivers must make all reasonable efforts to expose it as an I2C 2474 * adapter and use drm_get_edid() instead of abusing this function. 2475 * 2476 * The EDID may be overridden using debugfs override_edid or firmware EDID 2477 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2478 * order. Having either of them bypasses actual EDID reads. 2479 * 2480 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2481 */ 2482 struct edid *drm_do_get_edid(struct drm_connector *connector, 2483 read_block_fn read_block, 2484 void *context) 2485 { 2486 return _drm_do_get_edid(connector, read_block, context, NULL); 2487 } 2488 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2489 2490 /** 2491 * drm_edid_raw - Get a pointer to the raw EDID data. 2492 * @drm_edid: drm_edid container 2493 * 2494 * Get a pointer to the raw EDID data. 2495 * 2496 * This is for transition only. Avoid using this like the plague. 2497 * 2498 * Return: Pointer to raw EDID data. 2499 */ 2500 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2501 { 2502 if (!drm_edid || !drm_edid->size) 2503 return NULL; 2504 2505 /* 2506 * Do not return pointers where relying on EDID extension count would 2507 * lead to buffer overflow. 2508 */ 2509 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2510 return NULL; 2511 2512 return drm_edid->edid; 2513 } 2514 EXPORT_SYMBOL(drm_edid_raw); 2515 2516 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2517 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2518 { 2519 struct drm_edid *drm_edid; 2520 2521 if (!edid || !size || size < EDID_LENGTH) 2522 return NULL; 2523 2524 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2525 if (drm_edid) { 2526 drm_edid->edid = edid; 2527 drm_edid->size = size; 2528 } 2529 2530 return drm_edid; 2531 } 2532 2533 /** 2534 * drm_edid_alloc - Allocate a new drm_edid container 2535 * @edid: Pointer to raw EDID data 2536 * @size: Size of memory allocated for EDID 2537 * 2538 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2539 * the actual size that has been allocated for the data. There is no validation 2540 * of the raw EDID data against the size, but at least the EDID base block must 2541 * fit in the buffer. 2542 * 2543 * The returned pointer must be freed using drm_edid_free(). 2544 * 2545 * Return: drm_edid container, or NULL on errors 2546 */ 2547 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2548 { 2549 const struct drm_edid *drm_edid; 2550 2551 if (!edid || !size || size < EDID_LENGTH) 2552 return NULL; 2553 2554 edid = kmemdup(edid, size, GFP_KERNEL); 2555 if (!edid) 2556 return NULL; 2557 2558 drm_edid = _drm_edid_alloc(edid, size); 2559 if (!drm_edid) 2560 kfree(edid); 2561 2562 return drm_edid; 2563 } 2564 EXPORT_SYMBOL(drm_edid_alloc); 2565 2566 /** 2567 * drm_edid_dup - Duplicate a drm_edid container 2568 * @drm_edid: EDID to duplicate 2569 * 2570 * The returned pointer must be freed using drm_edid_free(). 2571 * 2572 * Returns: drm_edid container copy, or NULL on errors 2573 */ 2574 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2575 { 2576 if (!drm_edid) 2577 return NULL; 2578 2579 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2580 } 2581 EXPORT_SYMBOL(drm_edid_dup); 2582 2583 /** 2584 * drm_edid_free - Free the drm_edid container 2585 * @drm_edid: EDID to free 2586 */ 2587 void drm_edid_free(const struct drm_edid *drm_edid) 2588 { 2589 if (!drm_edid) 2590 return; 2591 2592 kfree(drm_edid->edid); 2593 kfree(drm_edid); 2594 } 2595 EXPORT_SYMBOL(drm_edid_free); 2596 2597 /** 2598 * drm_probe_ddc() - probe DDC presence 2599 * @adapter: I2C adapter to probe 2600 * 2601 * Return: True on success, false on failure. 2602 */ 2603 bool 2604 drm_probe_ddc(struct i2c_adapter *adapter) 2605 { 2606 unsigned char out; 2607 2608 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2609 } 2610 EXPORT_SYMBOL(drm_probe_ddc); 2611 2612 /** 2613 * drm_get_edid - get EDID data, if available 2614 * @connector: connector we're probing 2615 * @adapter: I2C adapter to use for DDC 2616 * 2617 * Poke the given I2C channel to grab EDID data if possible. If found, 2618 * attach it to the connector. 2619 * 2620 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2621 */ 2622 struct edid *drm_get_edid(struct drm_connector *connector, 2623 struct i2c_adapter *adapter) 2624 { 2625 struct edid *edid; 2626 2627 if (connector->force == DRM_FORCE_OFF) 2628 return NULL; 2629 2630 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2631 return NULL; 2632 2633 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2634 drm_connector_update_edid_property(connector, edid); 2635 return edid; 2636 } 2637 EXPORT_SYMBOL(drm_get_edid); 2638 2639 /** 2640 * drm_edid_read_custom - Read EDID data using given EDID block read function 2641 * @connector: Connector to use 2642 * @read_block: EDID block read function 2643 * @context: Private data passed to the block read function 2644 * 2645 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2646 * exposes a different interface to read EDID blocks this function can be used 2647 * to get EDID data using a custom block read function. 2648 * 2649 * As in the general case the DDC bus is accessible by the kernel at the I2C 2650 * level, drivers must make all reasonable efforts to expose it as an I2C 2651 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2652 * this function. 2653 * 2654 * The EDID may be overridden using debugfs override_edid or firmware EDID 2655 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2656 * order. Having either of them bypasses actual EDID reads. 2657 * 2658 * The returned pointer must be freed using drm_edid_free(). 2659 * 2660 * Return: Pointer to EDID, or NULL if probe/read failed. 2661 */ 2662 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2663 read_block_fn read_block, 2664 void *context) 2665 { 2666 const struct drm_edid *drm_edid; 2667 struct edid *edid; 2668 size_t size = 0; 2669 2670 edid = _drm_do_get_edid(connector, read_block, context, &size); 2671 if (!edid) 2672 return NULL; 2673 2674 /* Sanity check for now */ 2675 drm_WARN_ON(connector->dev, !size); 2676 2677 drm_edid = _drm_edid_alloc(edid, size); 2678 if (!drm_edid) 2679 kfree(edid); 2680 2681 return drm_edid; 2682 } 2683 EXPORT_SYMBOL(drm_edid_read_custom); 2684 2685 /** 2686 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2687 * @connector: Connector to use 2688 * @adapter: I2C adapter to use for DDC 2689 * 2690 * Read EDID using the given I2C adapter. 2691 * 2692 * The EDID may be overridden using debugfs override_edid or firmware EDID 2693 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2694 * order. Having either of them bypasses actual EDID reads. 2695 * 2696 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2697 * using drm_edid_read() instead of this function. 2698 * 2699 * The returned pointer must be freed using drm_edid_free(). 2700 * 2701 * Return: Pointer to EDID, or NULL if probe/read failed. 2702 */ 2703 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2704 struct i2c_adapter *adapter) 2705 { 2706 const struct drm_edid *drm_edid; 2707 2708 if (connector->force == DRM_FORCE_OFF) 2709 return NULL; 2710 2711 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2712 return NULL; 2713 2714 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2715 2716 /* Note: Do *not* call connector updates here. */ 2717 2718 return drm_edid; 2719 } 2720 EXPORT_SYMBOL(drm_edid_read_ddc); 2721 2722 /** 2723 * drm_edid_read - Read EDID data using connector's I2C adapter 2724 * @connector: Connector to use 2725 * 2726 * Read EDID using the connector's I2C adapter. 2727 * 2728 * The EDID may be overridden using debugfs override_edid or firmware EDID 2729 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2730 * order. Having either of them bypasses actual EDID reads. 2731 * 2732 * The returned pointer must be freed using drm_edid_free(). 2733 * 2734 * Return: Pointer to EDID, or NULL if probe/read failed. 2735 */ 2736 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2737 { 2738 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2739 return NULL; 2740 2741 return drm_edid_read_ddc(connector, connector->ddc); 2742 } 2743 EXPORT_SYMBOL(drm_edid_read); 2744 2745 static u32 edid_extract_panel_id(const struct edid *edid) 2746 { 2747 /* 2748 * We represent the ID as a 32-bit number so it can easily be compared 2749 * with "==". 2750 * 2751 * NOTE that we deal with endianness differently for the top half 2752 * of this ID than for the bottom half. The bottom half (the product 2753 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2754 * that's how everyone seems to interpret it. The top half (the mfg_id) 2755 * gets stored as big endian because that makes 2756 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2757 * to write (it's easier to extract the ASCII). It doesn't really 2758 * matter, though, as long as the number here is unique. 2759 */ 2760 return (u32)edid->mfg_id[0] << 24 | 2761 (u32)edid->mfg_id[1] << 16 | 2762 (u32)EDID_PRODUCT_ID(edid); 2763 } 2764 2765 /** 2766 * drm_edid_get_panel_id - Get a panel's ID through DDC 2767 * @adapter: I2C adapter to use for DDC 2768 * 2769 * This function reads the first block of the EDID of a panel and (assuming 2770 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2771 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2772 * supposed to be different for each different modem of panel. 2773 * 2774 * This function is intended to be used during early probing on devices where 2775 * more than one panel might be present. Because of its intended use it must 2776 * assume that the EDID of the panel is correct, at least as far as the ID 2777 * is concerned (in other words, we don't process any overrides here). 2778 * 2779 * NOTE: it's expected that this function and drm_do_get_edid() will both 2780 * be read the EDID, but there is no caching between them. Since we're only 2781 * reading the first block, hopefully this extra overhead won't be too big. 2782 * 2783 * Return: A 32-bit ID that should be different for each make/model of panel. 2784 * See the functions drm_edid_encode_panel_id() and 2785 * drm_edid_decode_panel_id() for some details on the structure of this 2786 * ID. 2787 */ 2788 2789 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2790 { 2791 enum edid_block_status status; 2792 void *base_block; 2793 u32 panel_id = 0; 2794 2795 /* 2796 * There are no manufacturer IDs of 0, so if there is a problem reading 2797 * the EDID then we'll just return 0. 2798 */ 2799 2800 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2801 if (!base_block) 2802 return 0; 2803 2804 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2805 2806 edid_block_status_print(status, base_block, 0); 2807 2808 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2809 panel_id = edid_extract_panel_id(base_block); 2810 else 2811 edid_block_dump(KERN_NOTICE, base_block, 0); 2812 2813 kfree(base_block); 2814 2815 return panel_id; 2816 } 2817 EXPORT_SYMBOL(drm_edid_get_panel_id); 2818 2819 /** 2820 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2821 * @connector: connector we're probing 2822 * @adapter: I2C adapter to use for DDC 2823 * 2824 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2825 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2826 * switch DDC to the GPU which is retrieving EDID. 2827 * 2828 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2829 */ 2830 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2831 struct i2c_adapter *adapter) 2832 { 2833 struct drm_device *dev = connector->dev; 2834 struct pci_dev *pdev = to_pci_dev(dev->dev); 2835 struct edid *edid; 2836 2837 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2838 return NULL; 2839 2840 vga_switcheroo_lock_ddc(pdev); 2841 edid = drm_get_edid(connector, adapter); 2842 vga_switcheroo_unlock_ddc(pdev); 2843 2844 return edid; 2845 } 2846 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2847 2848 /** 2849 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2850 * @connector: connector we're probing 2851 * @adapter: I2C adapter to use for DDC 2852 * 2853 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2854 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2855 * temporarily switch DDC to the GPU which is retrieving EDID. 2856 * 2857 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2858 */ 2859 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2860 struct i2c_adapter *adapter) 2861 { 2862 struct drm_device *dev = connector->dev; 2863 struct pci_dev *pdev = to_pci_dev(dev->dev); 2864 const struct drm_edid *drm_edid; 2865 2866 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2867 return NULL; 2868 2869 vga_switcheroo_lock_ddc(pdev); 2870 drm_edid = drm_edid_read_ddc(connector, adapter); 2871 vga_switcheroo_unlock_ddc(pdev); 2872 2873 return drm_edid; 2874 } 2875 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2876 2877 /** 2878 * drm_edid_duplicate - duplicate an EDID and the extensions 2879 * @edid: EDID to duplicate 2880 * 2881 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2882 */ 2883 struct edid *drm_edid_duplicate(const struct edid *edid) 2884 { 2885 if (!edid) 2886 return NULL; 2887 2888 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2889 } 2890 EXPORT_SYMBOL(drm_edid_duplicate); 2891 2892 /*** EDID parsing ***/ 2893 2894 /** 2895 * edid_get_quirks - return quirk flags for a given EDID 2896 * @drm_edid: EDID to process 2897 * 2898 * This tells subsequent routines what fixes they need to apply. 2899 */ 2900 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2901 { 2902 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2903 const struct edid_quirk *quirk; 2904 int i; 2905 2906 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2907 quirk = &edid_quirk_list[i]; 2908 if (quirk->panel_id == panel_id) 2909 return quirk->quirks; 2910 } 2911 2912 return 0; 2913 } 2914 2915 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2916 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2917 2918 /* 2919 * Walk the mode list for connector, clearing the preferred status on existing 2920 * modes and setting it anew for the right mode ala quirks. 2921 */ 2922 static void edid_fixup_preferred(struct drm_connector *connector) 2923 { 2924 const struct drm_display_info *info = &connector->display_info; 2925 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2926 int target_refresh = 0; 2927 int cur_vrefresh, preferred_vrefresh; 2928 2929 if (list_empty(&connector->probed_modes)) 2930 return; 2931 2932 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2933 target_refresh = 60; 2934 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2935 target_refresh = 75; 2936 2937 preferred_mode = list_first_entry(&connector->probed_modes, 2938 struct drm_display_mode, head); 2939 2940 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2941 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2942 2943 if (cur_mode == preferred_mode) 2944 continue; 2945 2946 /* Largest mode is preferred */ 2947 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2948 preferred_mode = cur_mode; 2949 2950 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2951 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2952 /* At a given size, try to get closest to target refresh */ 2953 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2954 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2955 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2956 preferred_mode = cur_mode; 2957 } 2958 } 2959 2960 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2961 } 2962 2963 static bool 2964 mode_is_rb(const struct drm_display_mode *mode) 2965 { 2966 return (mode->htotal - mode->hdisplay == 160) && 2967 (mode->hsync_end - mode->hdisplay == 80) && 2968 (mode->hsync_end - mode->hsync_start == 32) && 2969 (mode->vsync_start - mode->vdisplay == 3); 2970 } 2971 2972 /* 2973 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2974 * @dev: Device to duplicate against 2975 * @hsize: Mode width 2976 * @vsize: Mode height 2977 * @fresh: Mode refresh rate 2978 * @rb: Mode reduced-blanking-ness 2979 * 2980 * Walk the DMT mode list looking for a match for the given parameters. 2981 * 2982 * Return: A newly allocated copy of the mode, or NULL if not found. 2983 */ 2984 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2985 int hsize, int vsize, int fresh, 2986 bool rb) 2987 { 2988 int i; 2989 2990 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2991 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2992 2993 if (hsize != ptr->hdisplay) 2994 continue; 2995 if (vsize != ptr->vdisplay) 2996 continue; 2997 if (fresh != drm_mode_vrefresh(ptr)) 2998 continue; 2999 if (rb != mode_is_rb(ptr)) 3000 continue; 3001 3002 return drm_mode_duplicate(dev, ptr); 3003 } 3004 3005 return NULL; 3006 } 3007 EXPORT_SYMBOL(drm_mode_find_dmt); 3008 3009 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3010 { 3011 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3012 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3014 3015 return descriptor->pixel_clock == 0 && 3016 descriptor->data.other_data.pad1 == 0 && 3017 descriptor->data.other_data.type == type; 3018 } 3019 3020 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3021 { 3022 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3023 3024 return descriptor->pixel_clock != 0; 3025 } 3026 3027 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3028 3029 static void 3030 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3031 { 3032 int i, n; 3033 u8 d = ext[0x02]; 3034 const u8 *det_base = ext + d; 3035 3036 if (d < 4 || d > 127) 3037 return; 3038 3039 n = (127 - d) / 18; 3040 for (i = 0; i < n; i++) 3041 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3042 } 3043 3044 static void 3045 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3046 { 3047 unsigned int i, n = min((int)ext[0x02], 6); 3048 const u8 *det_base = ext + 5; 3049 3050 if (ext[0x01] != 1) 3051 return; /* unknown version */ 3052 3053 for (i = 0; i < n; i++) 3054 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3055 } 3056 3057 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3058 detailed_cb *cb, void *closure) 3059 { 3060 struct drm_edid_iter edid_iter; 3061 const u8 *ext; 3062 int i; 3063 3064 if (!drm_edid) 3065 return; 3066 3067 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3068 cb(&drm_edid->edid->detailed_timings[i], closure); 3069 3070 drm_edid_iter_begin(drm_edid, &edid_iter); 3071 drm_edid_iter_for_each(ext, &edid_iter) { 3072 switch (*ext) { 3073 case CEA_EXT: 3074 cea_for_each_detailed_block(ext, cb, closure); 3075 break; 3076 case VTB_EXT: 3077 vtb_for_each_detailed_block(ext, cb, closure); 3078 break; 3079 default: 3080 break; 3081 } 3082 } 3083 drm_edid_iter_end(&edid_iter); 3084 } 3085 3086 static void 3087 is_rb(const struct detailed_timing *descriptor, void *data) 3088 { 3089 bool *res = data; 3090 3091 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3092 return; 3093 3094 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3095 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3096 3097 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3098 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3099 *res = true; 3100 } 3101 3102 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3103 static bool 3104 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3105 { 3106 if (drm_edid->edid->revision >= 4) { 3107 bool ret = false; 3108 3109 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3110 return ret; 3111 } 3112 3113 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3114 } 3115 3116 static void 3117 find_gtf2(const struct detailed_timing *descriptor, void *data) 3118 { 3119 const struct detailed_timing **res = data; 3120 3121 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3122 return; 3123 3124 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3125 3126 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3127 *res = descriptor; 3128 } 3129 3130 /* Secondary GTF curve kicks in above some break frequency */ 3131 static int 3132 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3133 { 3134 const struct detailed_timing *descriptor = NULL; 3135 3136 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3137 3138 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3139 3140 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3141 } 3142 3143 static int 3144 drm_gtf2_2c(const struct drm_edid *drm_edid) 3145 { 3146 const struct detailed_timing *descriptor = NULL; 3147 3148 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3149 3150 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3151 3152 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3153 } 3154 3155 static int 3156 drm_gtf2_m(const struct drm_edid *drm_edid) 3157 { 3158 const struct detailed_timing *descriptor = NULL; 3159 3160 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3161 3162 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3163 3164 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3165 } 3166 3167 static int 3168 drm_gtf2_k(const struct drm_edid *drm_edid) 3169 { 3170 const struct detailed_timing *descriptor = NULL; 3171 3172 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3173 3174 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3175 3176 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3177 } 3178 3179 static int 3180 drm_gtf2_2j(const struct drm_edid *drm_edid) 3181 { 3182 const struct detailed_timing *descriptor = NULL; 3183 3184 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3185 3186 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3187 3188 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3189 } 3190 3191 static void 3192 get_timing_level(const struct detailed_timing *descriptor, void *data) 3193 { 3194 int *res = data; 3195 3196 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3197 return; 3198 3199 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3200 3201 switch (descriptor->data.other_data.data.range.flags) { 3202 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3203 *res = LEVEL_GTF; 3204 break; 3205 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3206 *res = LEVEL_GTF2; 3207 break; 3208 case DRM_EDID_CVT_SUPPORT_FLAG: 3209 *res = LEVEL_CVT; 3210 break; 3211 default: 3212 break; 3213 } 3214 } 3215 3216 /* Get standard timing level (CVT/GTF/DMT). */ 3217 static int standard_timing_level(const struct drm_edid *drm_edid) 3218 { 3219 const struct edid *edid = drm_edid->edid; 3220 3221 if (edid->revision >= 4) { 3222 /* 3223 * If the range descriptor doesn't 3224 * indicate otherwise default to CVT 3225 */ 3226 int ret = LEVEL_CVT; 3227 3228 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3229 3230 return ret; 3231 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3232 return LEVEL_GTF2; 3233 } else if (edid->revision >= 2) { 3234 return LEVEL_GTF; 3235 } else { 3236 return LEVEL_DMT; 3237 } 3238 } 3239 3240 /* 3241 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3242 * monitors fill with ascii space (0x20) instead. 3243 */ 3244 static int 3245 bad_std_timing(u8 a, u8 b) 3246 { 3247 return (a == 0x00 && b == 0x00) || 3248 (a == 0x01 && b == 0x01) || 3249 (a == 0x20 && b == 0x20); 3250 } 3251 3252 static int drm_mode_hsync(const struct drm_display_mode *mode) 3253 { 3254 if (mode->htotal <= 0) 3255 return 0; 3256 3257 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3258 } 3259 3260 static struct drm_display_mode * 3261 drm_gtf2_mode(struct drm_device *dev, 3262 const struct drm_edid *drm_edid, 3263 int hsize, int vsize, int vrefresh_rate) 3264 { 3265 struct drm_display_mode *mode; 3266 3267 /* 3268 * This is potentially wrong if there's ever a monitor with 3269 * more than one ranges section, each claiming a different 3270 * secondary GTF curve. Please don't do that. 3271 */ 3272 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3273 if (!mode) 3274 return NULL; 3275 3276 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3277 drm_mode_destroy(dev, mode); 3278 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3279 vrefresh_rate, 0, 0, 3280 drm_gtf2_m(drm_edid), 3281 drm_gtf2_2c(drm_edid), 3282 drm_gtf2_k(drm_edid), 3283 drm_gtf2_2j(drm_edid)); 3284 } 3285 3286 return mode; 3287 } 3288 3289 /* 3290 * Take the standard timing params (in this case width, aspect, and refresh) 3291 * and convert them into a real mode using CVT/GTF/DMT. 3292 */ 3293 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3294 const struct drm_edid *drm_edid, 3295 const struct std_timing *t) 3296 { 3297 struct drm_device *dev = connector->dev; 3298 struct drm_display_mode *m, *mode = NULL; 3299 int hsize, vsize; 3300 int vrefresh_rate; 3301 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3302 >> EDID_TIMING_ASPECT_SHIFT; 3303 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3304 >> EDID_TIMING_VFREQ_SHIFT; 3305 int timing_level = standard_timing_level(drm_edid); 3306 3307 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3308 return NULL; 3309 3310 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3311 hsize = t->hsize * 8 + 248; 3312 /* vrefresh_rate = vfreq + 60 */ 3313 vrefresh_rate = vfreq + 60; 3314 /* the vdisplay is calculated based on the aspect ratio */ 3315 if (aspect_ratio == 0) { 3316 if (drm_edid->edid->revision < 3) 3317 vsize = hsize; 3318 else 3319 vsize = (hsize * 10) / 16; 3320 } else if (aspect_ratio == 1) 3321 vsize = (hsize * 3) / 4; 3322 else if (aspect_ratio == 2) 3323 vsize = (hsize * 4) / 5; 3324 else 3325 vsize = (hsize * 9) / 16; 3326 3327 /* HDTV hack, part 1 */ 3328 if (vrefresh_rate == 60 && 3329 ((hsize == 1360 && vsize == 765) || 3330 (hsize == 1368 && vsize == 769))) { 3331 hsize = 1366; 3332 vsize = 768; 3333 } 3334 3335 /* 3336 * If this connector already has a mode for this size and refresh 3337 * rate (because it came from detailed or CVT info), use that 3338 * instead. This way we don't have to guess at interlace or 3339 * reduced blanking. 3340 */ 3341 list_for_each_entry(m, &connector->probed_modes, head) 3342 if (m->hdisplay == hsize && m->vdisplay == vsize && 3343 drm_mode_vrefresh(m) == vrefresh_rate) 3344 return NULL; 3345 3346 /* HDTV hack, part 2 */ 3347 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3348 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3349 false); 3350 if (!mode) 3351 return NULL; 3352 mode->hdisplay = 1366; 3353 mode->hsync_start = mode->hsync_start - 1; 3354 mode->hsync_end = mode->hsync_end - 1; 3355 return mode; 3356 } 3357 3358 /* check whether it can be found in default mode table */ 3359 if (drm_monitor_supports_rb(drm_edid)) { 3360 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3361 true); 3362 if (mode) 3363 return mode; 3364 } 3365 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3366 if (mode) 3367 return mode; 3368 3369 /* okay, generate it */ 3370 switch (timing_level) { 3371 case LEVEL_DMT: 3372 break; 3373 case LEVEL_GTF: 3374 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3375 break; 3376 case LEVEL_GTF2: 3377 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3378 break; 3379 case LEVEL_CVT: 3380 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3381 false); 3382 break; 3383 } 3384 return mode; 3385 } 3386 3387 /* 3388 * EDID is delightfully ambiguous about how interlaced modes are to be 3389 * encoded. Our internal representation is of frame height, but some 3390 * HDTV detailed timings are encoded as field height. 3391 * 3392 * The format list here is from CEA, in frame size. Technically we 3393 * should be checking refresh rate too. Whatever. 3394 */ 3395 static void 3396 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3397 const struct detailed_pixel_timing *pt) 3398 { 3399 int i; 3400 static const struct { 3401 int w, h; 3402 } cea_interlaced[] = { 3403 { 1920, 1080 }, 3404 { 720, 480 }, 3405 { 1440, 480 }, 3406 { 2880, 480 }, 3407 { 720, 576 }, 3408 { 1440, 576 }, 3409 { 2880, 576 }, 3410 }; 3411 3412 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3413 return; 3414 3415 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3416 if ((mode->hdisplay == cea_interlaced[i].w) && 3417 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3418 mode->vdisplay *= 2; 3419 mode->vsync_start *= 2; 3420 mode->vsync_end *= 2; 3421 mode->vtotal *= 2; 3422 mode->vtotal |= 1; 3423 } 3424 } 3425 3426 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3427 } 3428 3429 /* 3430 * Create a new mode from an EDID detailed timing section. An EDID detailed 3431 * timing block contains enough info for us to create and return a new struct 3432 * drm_display_mode. 3433 */ 3434 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3435 const struct drm_edid *drm_edid, 3436 const struct detailed_timing *timing) 3437 { 3438 const struct drm_display_info *info = &connector->display_info; 3439 struct drm_device *dev = connector->dev; 3440 struct drm_display_mode *mode; 3441 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3442 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3443 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3444 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3445 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3446 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3447 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3448 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3449 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3450 3451 /* ignore tiny modes */ 3452 if (hactive < 64 || vactive < 64) 3453 return NULL; 3454 3455 if (pt->misc & DRM_EDID_PT_STEREO) { 3456 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3457 connector->base.id, connector->name); 3458 return NULL; 3459 } 3460 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3461 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3462 connector->base.id, connector->name); 3463 } 3464 3465 /* it is incorrect if hsync/vsync width is zero */ 3466 if (!hsync_pulse_width || !vsync_pulse_width) { 3467 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3468 connector->base.id, connector->name); 3469 return NULL; 3470 } 3471 3472 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3473 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3474 if (!mode) 3475 return NULL; 3476 3477 goto set_size; 3478 } 3479 3480 mode = drm_mode_create(dev); 3481 if (!mode) 3482 return NULL; 3483 3484 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3485 mode->clock = 1088 * 10; 3486 else 3487 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3488 3489 mode->hdisplay = hactive; 3490 mode->hsync_start = mode->hdisplay + hsync_offset; 3491 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3492 mode->htotal = mode->hdisplay + hblank; 3493 3494 mode->vdisplay = vactive; 3495 mode->vsync_start = mode->vdisplay + vsync_offset; 3496 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3497 mode->vtotal = mode->vdisplay + vblank; 3498 3499 /* Some EDIDs have bogus h/vtotal values */ 3500 if (mode->hsync_end > mode->htotal) 3501 mode->htotal = mode->hsync_end + 1; 3502 if (mode->vsync_end > mode->vtotal) 3503 mode->vtotal = mode->vsync_end + 1; 3504 3505 drm_mode_do_interlace_quirk(mode, pt); 3506 3507 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3508 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3509 } else { 3510 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3511 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3512 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3513 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3514 } 3515 3516 set_size: 3517 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3518 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3519 3520 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3521 mode->width_mm *= 10; 3522 mode->height_mm *= 10; 3523 } 3524 3525 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3526 mode->width_mm = drm_edid->edid->width_cm * 10; 3527 mode->height_mm = drm_edid->edid->height_cm * 10; 3528 } 3529 3530 mode->type = DRM_MODE_TYPE_DRIVER; 3531 drm_mode_set_name(mode); 3532 3533 return mode; 3534 } 3535 3536 static bool 3537 mode_in_hsync_range(const struct drm_display_mode *mode, 3538 const struct edid *edid, const u8 *t) 3539 { 3540 int hsync, hmin, hmax; 3541 3542 hmin = t[7]; 3543 if (edid->revision >= 4) 3544 hmin += ((t[4] & 0x04) ? 255 : 0); 3545 hmax = t[8]; 3546 if (edid->revision >= 4) 3547 hmax += ((t[4] & 0x08) ? 255 : 0); 3548 hsync = drm_mode_hsync(mode); 3549 3550 return (hsync <= hmax && hsync >= hmin); 3551 } 3552 3553 static bool 3554 mode_in_vsync_range(const struct drm_display_mode *mode, 3555 const struct edid *edid, const u8 *t) 3556 { 3557 int vsync, vmin, vmax; 3558 3559 vmin = t[5]; 3560 if (edid->revision >= 4) 3561 vmin += ((t[4] & 0x01) ? 255 : 0); 3562 vmax = t[6]; 3563 if (edid->revision >= 4) 3564 vmax += ((t[4] & 0x02) ? 255 : 0); 3565 vsync = drm_mode_vrefresh(mode); 3566 3567 return (vsync <= vmax && vsync >= vmin); 3568 } 3569 3570 static u32 3571 range_pixel_clock(const struct edid *edid, const u8 *t) 3572 { 3573 /* unspecified */ 3574 if (t[9] == 0 || t[9] == 255) 3575 return 0; 3576 3577 /* 1.4 with CVT support gives us real precision, yay */ 3578 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3579 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3580 3581 /* 1.3 is pathetic, so fuzz up a bit */ 3582 return t[9] * 10000 + 5001; 3583 } 3584 3585 static bool mode_in_range(const struct drm_display_mode *mode, 3586 const struct drm_edid *drm_edid, 3587 const struct detailed_timing *timing) 3588 { 3589 const struct edid *edid = drm_edid->edid; 3590 u32 max_clock; 3591 const u8 *t = (const u8 *)timing; 3592 3593 if (!mode_in_hsync_range(mode, edid, t)) 3594 return false; 3595 3596 if (!mode_in_vsync_range(mode, edid, t)) 3597 return false; 3598 3599 if ((max_clock = range_pixel_clock(edid, t))) 3600 if (mode->clock > max_clock) 3601 return false; 3602 3603 /* 1.4 max horizontal check */ 3604 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3605 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3606 return false; 3607 3608 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3609 return false; 3610 3611 return true; 3612 } 3613 3614 static bool valid_inferred_mode(const struct drm_connector *connector, 3615 const struct drm_display_mode *mode) 3616 { 3617 const struct drm_display_mode *m; 3618 bool ok = false; 3619 3620 list_for_each_entry(m, &connector->probed_modes, head) { 3621 if (mode->hdisplay == m->hdisplay && 3622 mode->vdisplay == m->vdisplay && 3623 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3624 return false; /* duplicated */ 3625 if (mode->hdisplay <= m->hdisplay && 3626 mode->vdisplay <= m->vdisplay) 3627 ok = true; 3628 } 3629 return ok; 3630 } 3631 3632 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3633 const struct drm_edid *drm_edid, 3634 const struct detailed_timing *timing) 3635 { 3636 int i, modes = 0; 3637 struct drm_display_mode *newmode; 3638 struct drm_device *dev = connector->dev; 3639 3640 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3641 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3642 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3643 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3644 if (newmode) { 3645 drm_mode_probed_add(connector, newmode); 3646 modes++; 3647 } 3648 } 3649 } 3650 3651 return modes; 3652 } 3653 3654 /* fix up 1366x768 mode from 1368x768; 3655 * GFT/CVT can't express 1366 width which isn't dividable by 8 3656 */ 3657 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3658 { 3659 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3660 mode->hdisplay = 1366; 3661 mode->hsync_start--; 3662 mode->hsync_end--; 3663 drm_mode_set_name(mode); 3664 } 3665 } 3666 3667 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3668 const struct drm_edid *drm_edid, 3669 const struct detailed_timing *timing) 3670 { 3671 int i, modes = 0; 3672 struct drm_display_mode *newmode; 3673 struct drm_device *dev = connector->dev; 3674 3675 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3676 const struct minimode *m = &extra_modes[i]; 3677 3678 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3679 if (!newmode) 3680 return modes; 3681 3682 drm_mode_fixup_1366x768(newmode); 3683 if (!mode_in_range(newmode, drm_edid, timing) || 3684 !valid_inferred_mode(connector, newmode)) { 3685 drm_mode_destroy(dev, newmode); 3686 continue; 3687 } 3688 3689 drm_mode_probed_add(connector, newmode); 3690 modes++; 3691 } 3692 3693 return modes; 3694 } 3695 3696 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3697 const struct drm_edid *drm_edid, 3698 const struct detailed_timing *timing) 3699 { 3700 int i, modes = 0; 3701 struct drm_display_mode *newmode; 3702 struct drm_device *dev = connector->dev; 3703 3704 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3705 const struct minimode *m = &extra_modes[i]; 3706 3707 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3708 if (!newmode) 3709 return modes; 3710 3711 drm_mode_fixup_1366x768(newmode); 3712 if (!mode_in_range(newmode, drm_edid, timing) || 3713 !valid_inferred_mode(connector, newmode)) { 3714 drm_mode_destroy(dev, newmode); 3715 continue; 3716 } 3717 3718 drm_mode_probed_add(connector, newmode); 3719 modes++; 3720 } 3721 3722 return modes; 3723 } 3724 3725 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3726 const struct drm_edid *drm_edid, 3727 const struct detailed_timing *timing) 3728 { 3729 int i, modes = 0; 3730 struct drm_display_mode *newmode; 3731 struct drm_device *dev = connector->dev; 3732 bool rb = drm_monitor_supports_rb(drm_edid); 3733 3734 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3735 const struct minimode *m = &extra_modes[i]; 3736 3737 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3738 if (!newmode) 3739 return modes; 3740 3741 drm_mode_fixup_1366x768(newmode); 3742 if (!mode_in_range(newmode, drm_edid, timing) || 3743 !valid_inferred_mode(connector, newmode)) { 3744 drm_mode_destroy(dev, newmode); 3745 continue; 3746 } 3747 3748 drm_mode_probed_add(connector, newmode); 3749 modes++; 3750 } 3751 3752 return modes; 3753 } 3754 3755 static void 3756 do_inferred_modes(const struct detailed_timing *timing, void *c) 3757 { 3758 struct detailed_mode_closure *closure = c; 3759 const struct detailed_non_pixel *data = &timing->data.other_data; 3760 const struct detailed_data_monitor_range *range = &data->data.range; 3761 3762 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3763 return; 3764 3765 closure->modes += drm_dmt_modes_for_range(closure->connector, 3766 closure->drm_edid, 3767 timing); 3768 3769 if (closure->drm_edid->edid->revision < 2) 3770 return; /* GTF not defined yet */ 3771 3772 switch (range->flags) { 3773 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3774 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3775 closure->drm_edid, 3776 timing); 3777 break; 3778 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3779 closure->modes += drm_gtf_modes_for_range(closure->connector, 3780 closure->drm_edid, 3781 timing); 3782 break; 3783 case DRM_EDID_CVT_SUPPORT_FLAG: 3784 if (closure->drm_edid->edid->revision < 4) 3785 break; 3786 3787 closure->modes += drm_cvt_modes_for_range(closure->connector, 3788 closure->drm_edid, 3789 timing); 3790 break; 3791 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3792 default: 3793 break; 3794 } 3795 } 3796 3797 static int add_inferred_modes(struct drm_connector *connector, 3798 const struct drm_edid *drm_edid) 3799 { 3800 struct detailed_mode_closure closure = { 3801 .connector = connector, 3802 .drm_edid = drm_edid, 3803 }; 3804 3805 if (drm_edid->edid->revision >= 1) 3806 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3807 3808 return closure.modes; 3809 } 3810 3811 static int 3812 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3813 { 3814 int i, j, m, modes = 0; 3815 struct drm_display_mode *mode; 3816 const u8 *est = ((const u8 *)timing) + 6; 3817 3818 for (i = 0; i < 6; i++) { 3819 for (j = 7; j >= 0; j--) { 3820 m = (i * 8) + (7 - j); 3821 if (m >= ARRAY_SIZE(est3_modes)) 3822 break; 3823 if (est[i] & (1 << j)) { 3824 mode = drm_mode_find_dmt(connector->dev, 3825 est3_modes[m].w, 3826 est3_modes[m].h, 3827 est3_modes[m].r, 3828 est3_modes[m].rb); 3829 if (mode) { 3830 drm_mode_probed_add(connector, mode); 3831 modes++; 3832 } 3833 } 3834 } 3835 } 3836 3837 return modes; 3838 } 3839 3840 static void 3841 do_established_modes(const struct detailed_timing *timing, void *c) 3842 { 3843 struct detailed_mode_closure *closure = c; 3844 3845 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3846 return; 3847 3848 closure->modes += drm_est3_modes(closure->connector, timing); 3849 } 3850 3851 /* 3852 * Get established modes from EDID and add them. Each EDID block contains a 3853 * bitmap of the supported "established modes" list (defined above). Tease them 3854 * out and add them to the global modes list. 3855 */ 3856 static int add_established_modes(struct drm_connector *connector, 3857 const struct drm_edid *drm_edid) 3858 { 3859 struct drm_device *dev = connector->dev; 3860 const struct edid *edid = drm_edid->edid; 3861 unsigned long est_bits = edid->established_timings.t1 | 3862 (edid->established_timings.t2 << 8) | 3863 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3864 int i, modes = 0; 3865 struct detailed_mode_closure closure = { 3866 .connector = connector, 3867 .drm_edid = drm_edid, 3868 }; 3869 3870 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3871 if (est_bits & (1<<i)) { 3872 struct drm_display_mode *newmode; 3873 3874 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3875 if (newmode) { 3876 drm_mode_probed_add(connector, newmode); 3877 modes++; 3878 } 3879 } 3880 } 3881 3882 if (edid->revision >= 1) 3883 drm_for_each_detailed_block(drm_edid, do_established_modes, 3884 &closure); 3885 3886 return modes + closure.modes; 3887 } 3888 3889 static void 3890 do_standard_modes(const struct detailed_timing *timing, void *c) 3891 { 3892 struct detailed_mode_closure *closure = c; 3893 const struct detailed_non_pixel *data = &timing->data.other_data; 3894 struct drm_connector *connector = closure->connector; 3895 int i; 3896 3897 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3898 return; 3899 3900 for (i = 0; i < 6; i++) { 3901 const struct std_timing *std = &data->data.timings[i]; 3902 struct drm_display_mode *newmode; 3903 3904 newmode = drm_mode_std(connector, closure->drm_edid, std); 3905 if (newmode) { 3906 drm_mode_probed_add(connector, newmode); 3907 closure->modes++; 3908 } 3909 } 3910 } 3911 3912 /* 3913 * Get standard modes from EDID and add them. Standard modes can be calculated 3914 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3915 * add them to the list. 3916 */ 3917 static int add_standard_modes(struct drm_connector *connector, 3918 const struct drm_edid *drm_edid) 3919 { 3920 int i, modes = 0; 3921 struct detailed_mode_closure closure = { 3922 .connector = connector, 3923 .drm_edid = drm_edid, 3924 }; 3925 3926 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3927 struct drm_display_mode *newmode; 3928 3929 newmode = drm_mode_std(connector, drm_edid, 3930 &drm_edid->edid->standard_timings[i]); 3931 if (newmode) { 3932 drm_mode_probed_add(connector, newmode); 3933 modes++; 3934 } 3935 } 3936 3937 if (drm_edid->edid->revision >= 1) 3938 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3939 &closure); 3940 3941 /* XXX should also look for standard codes in VTB blocks */ 3942 3943 return modes + closure.modes; 3944 } 3945 3946 static int drm_cvt_modes(struct drm_connector *connector, 3947 const struct detailed_timing *timing) 3948 { 3949 int i, j, modes = 0; 3950 struct drm_display_mode *newmode; 3951 struct drm_device *dev = connector->dev; 3952 const struct cvt_timing *cvt; 3953 static const int rates[] = { 60, 85, 75, 60, 50 }; 3954 const u8 empty[3] = { 0, 0, 0 }; 3955 3956 for (i = 0; i < 4; i++) { 3957 int width, height; 3958 3959 cvt = &(timing->data.other_data.data.cvt[i]); 3960 3961 if (!memcmp(cvt->code, empty, 3)) 3962 continue; 3963 3964 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3965 switch (cvt->code[1] & 0x0c) { 3966 /* default - because compiler doesn't see that we've enumerated all cases */ 3967 default: 3968 case 0x00: 3969 width = height * 4 / 3; 3970 break; 3971 case 0x04: 3972 width = height * 16 / 9; 3973 break; 3974 case 0x08: 3975 width = height * 16 / 10; 3976 break; 3977 case 0x0c: 3978 width = height * 15 / 9; 3979 break; 3980 } 3981 3982 for (j = 1; j < 5; j++) { 3983 if (cvt->code[2] & (1 << j)) { 3984 newmode = drm_cvt_mode(dev, width, height, 3985 rates[j], j == 0, 3986 false, false); 3987 if (newmode) { 3988 drm_mode_probed_add(connector, newmode); 3989 modes++; 3990 } 3991 } 3992 } 3993 } 3994 3995 return modes; 3996 } 3997 3998 static void 3999 do_cvt_mode(const struct detailed_timing *timing, void *c) 4000 { 4001 struct detailed_mode_closure *closure = c; 4002 4003 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4004 return; 4005 4006 closure->modes += drm_cvt_modes(closure->connector, timing); 4007 } 4008 4009 static int 4010 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4011 { 4012 struct detailed_mode_closure closure = { 4013 .connector = connector, 4014 .drm_edid = drm_edid, 4015 }; 4016 4017 if (drm_edid->edid->revision >= 3) 4018 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4019 4020 /* XXX should also look for CVT codes in VTB blocks */ 4021 4022 return closure.modes; 4023 } 4024 4025 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4026 struct drm_display_mode *mode); 4027 4028 static void 4029 do_detailed_mode(const struct detailed_timing *timing, void *c) 4030 { 4031 struct detailed_mode_closure *closure = c; 4032 struct drm_display_mode *newmode; 4033 4034 if (!is_detailed_timing_descriptor(timing)) 4035 return; 4036 4037 newmode = drm_mode_detailed(closure->connector, 4038 closure->drm_edid, timing); 4039 if (!newmode) 4040 return; 4041 4042 if (closure->preferred) 4043 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4044 4045 /* 4046 * Detailed modes are limited to 10kHz pixel clock resolution, 4047 * so fix up anything that looks like CEA/HDMI mode, but the clock 4048 * is just slightly off. 4049 */ 4050 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4051 4052 drm_mode_probed_add(closure->connector, newmode); 4053 closure->modes++; 4054 closure->preferred = false; 4055 } 4056 4057 /* 4058 * add_detailed_modes - Add modes from detailed timings 4059 * @connector: attached connector 4060 * @drm_edid: EDID block to scan 4061 */ 4062 static int add_detailed_modes(struct drm_connector *connector, 4063 const struct drm_edid *drm_edid) 4064 { 4065 struct detailed_mode_closure closure = { 4066 .connector = connector, 4067 .drm_edid = drm_edid, 4068 }; 4069 4070 if (drm_edid->edid->revision >= 4) 4071 closure.preferred = true; /* first detailed timing is always preferred */ 4072 else 4073 closure.preferred = 4074 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4075 4076 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4077 4078 return closure.modes; 4079 } 4080 4081 /* CTA-861-H Table 60 - CTA Tag Codes */ 4082 #define CTA_DB_AUDIO 1 4083 #define CTA_DB_VIDEO 2 4084 #define CTA_DB_VENDOR 3 4085 #define CTA_DB_SPEAKER 4 4086 #define CTA_DB_EXTENDED_TAG 7 4087 4088 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4089 #define CTA_EXT_DB_VIDEO_CAP 0 4090 #define CTA_EXT_DB_VENDOR 1 4091 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4092 #define CTA_EXT_DB_420_VIDEO_DATA 14 4093 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4094 #define CTA_EXT_DB_HF_EEODB 0x78 4095 #define CTA_EXT_DB_HF_SCDB 0x79 4096 4097 #define EDID_BASIC_AUDIO (1 << 6) 4098 #define EDID_CEA_YCRCB444 (1 << 5) 4099 #define EDID_CEA_YCRCB422 (1 << 4) 4100 #define EDID_CEA_VCDB_QS (1 << 6) 4101 4102 /* 4103 * Search EDID for CEA extension block. 4104 * 4105 * FIXME: Prefer not returning pointers to raw EDID data. 4106 */ 4107 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4108 int ext_id, int *ext_index) 4109 { 4110 const u8 *edid_ext = NULL; 4111 int i; 4112 4113 /* No EDID or EDID extensions */ 4114 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4115 return NULL; 4116 4117 /* Find CEA extension */ 4118 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4119 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4120 if (edid_block_tag(edid_ext) == ext_id) 4121 break; 4122 } 4123 4124 if (i >= drm_edid_extension_block_count(drm_edid)) 4125 return NULL; 4126 4127 *ext_index = i + 1; 4128 4129 return edid_ext; 4130 } 4131 4132 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4133 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4134 { 4135 const struct displayid_block *block; 4136 struct displayid_iter iter; 4137 int ext_index = 0; 4138 bool found = false; 4139 4140 /* Look for a top level CEA extension block */ 4141 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4142 return true; 4143 4144 /* CEA blocks can also be found embedded in a DisplayID block */ 4145 displayid_iter_edid_begin(drm_edid, &iter); 4146 displayid_iter_for_each(block, &iter) { 4147 if (block->tag == DATA_BLOCK_CTA) { 4148 found = true; 4149 break; 4150 } 4151 } 4152 displayid_iter_end(&iter); 4153 4154 return found; 4155 } 4156 4157 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4158 { 4159 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4160 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4161 4162 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4163 return &edid_cea_modes_1[vic - 1]; 4164 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4165 return &edid_cea_modes_193[vic - 193]; 4166 return NULL; 4167 } 4168 4169 static u8 cea_num_vics(void) 4170 { 4171 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4172 } 4173 4174 static u8 cea_next_vic(u8 vic) 4175 { 4176 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4177 vic = 193; 4178 return vic; 4179 } 4180 4181 /* 4182 * Calculate the alternate clock for the CEA mode 4183 * (60Hz vs. 59.94Hz etc.) 4184 */ 4185 static unsigned int 4186 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4187 { 4188 unsigned int clock = cea_mode->clock; 4189 4190 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4191 return clock; 4192 4193 /* 4194 * edid_cea_modes contains the 59.94Hz 4195 * variant for 240 and 480 line modes, 4196 * and the 60Hz variant otherwise. 4197 */ 4198 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4199 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4200 else 4201 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4202 4203 return clock; 4204 } 4205 4206 static bool 4207 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4208 { 4209 /* 4210 * For certain VICs the spec allows the vertical 4211 * front porch to vary by one or two lines. 4212 * 4213 * cea_modes[] stores the variant with the shortest 4214 * vertical front porch. We can adjust the mode to 4215 * get the other variants by simply increasing the 4216 * vertical front porch length. 4217 */ 4218 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4219 cea_mode_for_vic(9)->vtotal != 262 || 4220 cea_mode_for_vic(12)->vtotal != 262 || 4221 cea_mode_for_vic(13)->vtotal != 262 || 4222 cea_mode_for_vic(23)->vtotal != 312 || 4223 cea_mode_for_vic(24)->vtotal != 312 || 4224 cea_mode_for_vic(27)->vtotal != 312 || 4225 cea_mode_for_vic(28)->vtotal != 312); 4226 4227 if (((vic == 8 || vic == 9 || 4228 vic == 12 || vic == 13) && mode->vtotal < 263) || 4229 ((vic == 23 || vic == 24 || 4230 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4231 mode->vsync_start++; 4232 mode->vsync_end++; 4233 mode->vtotal++; 4234 4235 return true; 4236 } 4237 4238 return false; 4239 } 4240 4241 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4242 unsigned int clock_tolerance) 4243 { 4244 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4245 u8 vic; 4246 4247 if (!to_match->clock) 4248 return 0; 4249 4250 if (to_match->picture_aspect_ratio) 4251 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4252 4253 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4254 struct drm_display_mode cea_mode; 4255 unsigned int clock1, clock2; 4256 4257 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4258 4259 /* Check both 60Hz and 59.94Hz */ 4260 clock1 = cea_mode.clock; 4261 clock2 = cea_mode_alternate_clock(&cea_mode); 4262 4263 if (abs(to_match->clock - clock1) > clock_tolerance && 4264 abs(to_match->clock - clock2) > clock_tolerance) 4265 continue; 4266 4267 do { 4268 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4269 return vic; 4270 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4271 } 4272 4273 return 0; 4274 } 4275 4276 /** 4277 * drm_match_cea_mode - look for a CEA mode matching given mode 4278 * @to_match: display mode 4279 * 4280 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4281 * mode. 4282 */ 4283 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4284 { 4285 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4286 u8 vic; 4287 4288 if (!to_match->clock) 4289 return 0; 4290 4291 if (to_match->picture_aspect_ratio) 4292 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4293 4294 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4295 struct drm_display_mode cea_mode; 4296 unsigned int clock1, clock2; 4297 4298 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4299 4300 /* Check both 60Hz and 59.94Hz */ 4301 clock1 = cea_mode.clock; 4302 clock2 = cea_mode_alternate_clock(&cea_mode); 4303 4304 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4305 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4306 continue; 4307 4308 do { 4309 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4310 return vic; 4311 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4312 } 4313 4314 return 0; 4315 } 4316 EXPORT_SYMBOL(drm_match_cea_mode); 4317 4318 static bool drm_valid_cea_vic(u8 vic) 4319 { 4320 return cea_mode_for_vic(vic) != NULL; 4321 } 4322 4323 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4324 { 4325 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4326 4327 if (mode) 4328 return mode->picture_aspect_ratio; 4329 4330 return HDMI_PICTURE_ASPECT_NONE; 4331 } 4332 4333 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4334 { 4335 return edid_4k_modes[video_code].picture_aspect_ratio; 4336 } 4337 4338 /* 4339 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4340 * specific block). 4341 */ 4342 static unsigned int 4343 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4344 { 4345 return cea_mode_alternate_clock(hdmi_mode); 4346 } 4347 4348 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4349 unsigned int clock_tolerance) 4350 { 4351 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4352 u8 vic; 4353 4354 if (!to_match->clock) 4355 return 0; 4356 4357 if (to_match->picture_aspect_ratio) 4358 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4359 4360 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4361 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4362 unsigned int clock1, clock2; 4363 4364 /* Make sure to also match alternate clocks */ 4365 clock1 = hdmi_mode->clock; 4366 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4367 4368 if (abs(to_match->clock - clock1) > clock_tolerance && 4369 abs(to_match->clock - clock2) > clock_tolerance) 4370 continue; 4371 4372 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4373 return vic; 4374 } 4375 4376 return 0; 4377 } 4378 4379 /* 4380 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4381 * @to_match: display mode 4382 * 4383 * An HDMI mode is one defined in the HDMI vendor specific block. 4384 * 4385 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4386 */ 4387 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4388 { 4389 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4390 u8 vic; 4391 4392 if (!to_match->clock) 4393 return 0; 4394 4395 if (to_match->picture_aspect_ratio) 4396 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4397 4398 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4399 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4400 unsigned int clock1, clock2; 4401 4402 /* Make sure to also match alternate clocks */ 4403 clock1 = hdmi_mode->clock; 4404 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4405 4406 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4407 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4408 drm_mode_match(to_match, hdmi_mode, match_flags)) 4409 return vic; 4410 } 4411 return 0; 4412 } 4413 4414 static bool drm_valid_hdmi_vic(u8 vic) 4415 { 4416 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4417 } 4418 4419 static int add_alternate_cea_modes(struct drm_connector *connector, 4420 const struct drm_edid *drm_edid) 4421 { 4422 struct drm_device *dev = connector->dev; 4423 struct drm_display_mode *mode, *tmp; 4424 LIST_HEAD(list); 4425 int modes = 0; 4426 4427 /* Don't add CTA modes if the CTA extension block is missing */ 4428 if (!drm_edid_has_cta_extension(drm_edid)) 4429 return 0; 4430 4431 /* 4432 * Go through all probed modes and create a new mode 4433 * with the alternate clock for certain CEA modes. 4434 */ 4435 list_for_each_entry(mode, &connector->probed_modes, head) { 4436 const struct drm_display_mode *cea_mode = NULL; 4437 struct drm_display_mode *newmode; 4438 u8 vic = drm_match_cea_mode(mode); 4439 unsigned int clock1, clock2; 4440 4441 if (drm_valid_cea_vic(vic)) { 4442 cea_mode = cea_mode_for_vic(vic); 4443 clock2 = cea_mode_alternate_clock(cea_mode); 4444 } else { 4445 vic = drm_match_hdmi_mode(mode); 4446 if (drm_valid_hdmi_vic(vic)) { 4447 cea_mode = &edid_4k_modes[vic]; 4448 clock2 = hdmi_mode_alternate_clock(cea_mode); 4449 } 4450 } 4451 4452 if (!cea_mode) 4453 continue; 4454 4455 clock1 = cea_mode->clock; 4456 4457 if (clock1 == clock2) 4458 continue; 4459 4460 if (mode->clock != clock1 && mode->clock != clock2) 4461 continue; 4462 4463 newmode = drm_mode_duplicate(dev, cea_mode); 4464 if (!newmode) 4465 continue; 4466 4467 /* Carry over the stereo flags */ 4468 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4469 4470 /* 4471 * The current mode could be either variant. Make 4472 * sure to pick the "other" clock for the new mode. 4473 */ 4474 if (mode->clock != clock1) 4475 newmode->clock = clock1; 4476 else 4477 newmode->clock = clock2; 4478 4479 list_add_tail(&newmode->head, &list); 4480 } 4481 4482 list_for_each_entry_safe(mode, tmp, &list, head) { 4483 list_del(&mode->head); 4484 drm_mode_probed_add(connector, mode); 4485 modes++; 4486 } 4487 4488 return modes; 4489 } 4490 4491 static u8 svd_to_vic(u8 svd) 4492 { 4493 /* 0-6 bit vic, 7th bit native mode indicator */ 4494 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4495 return svd & 127; 4496 4497 return svd; 4498 } 4499 4500 /* 4501 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4502 * the EDID, or NULL on errors. 4503 */ 4504 static struct drm_display_mode * 4505 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4506 { 4507 const struct drm_display_info *info = &connector->display_info; 4508 struct drm_device *dev = connector->dev; 4509 4510 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4511 return NULL; 4512 4513 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4514 } 4515 4516 /* 4517 * do_y420vdb_modes - Parse YCBCR 420 only modes 4518 * @connector: connector corresponding to the HDMI sink 4519 * @svds: start of the data block of CEA YCBCR 420 VDB 4520 * @len: length of the CEA YCBCR 420 VDB 4521 * 4522 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4523 * which contains modes which can be supported in YCBCR 420 4524 * output format only. 4525 */ 4526 static int do_y420vdb_modes(struct drm_connector *connector, 4527 const u8 *svds, u8 svds_len) 4528 { 4529 struct drm_device *dev = connector->dev; 4530 int modes = 0, i; 4531 4532 for (i = 0; i < svds_len; i++) { 4533 u8 vic = svd_to_vic(svds[i]); 4534 struct drm_display_mode *newmode; 4535 4536 if (!drm_valid_cea_vic(vic)) 4537 continue; 4538 4539 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4540 if (!newmode) 4541 break; 4542 drm_mode_probed_add(connector, newmode); 4543 modes++; 4544 } 4545 4546 return modes; 4547 } 4548 4549 /** 4550 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4551 * @dev: DRM device 4552 * @video_code: CEA VIC of the mode 4553 * 4554 * Creates a new mode matching the specified CEA VIC. 4555 * 4556 * Returns: A new drm_display_mode on success or NULL on failure 4557 */ 4558 struct drm_display_mode * 4559 drm_display_mode_from_cea_vic(struct drm_device *dev, 4560 u8 video_code) 4561 { 4562 const struct drm_display_mode *cea_mode; 4563 struct drm_display_mode *newmode; 4564 4565 cea_mode = cea_mode_for_vic(video_code); 4566 if (!cea_mode) 4567 return NULL; 4568 4569 newmode = drm_mode_duplicate(dev, cea_mode); 4570 if (!newmode) 4571 return NULL; 4572 4573 return newmode; 4574 } 4575 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4576 4577 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4578 static int add_cta_vdb_modes(struct drm_connector *connector) 4579 { 4580 const struct drm_display_info *info = &connector->display_info; 4581 int i, modes = 0; 4582 4583 if (!info->vics) 4584 return 0; 4585 4586 for (i = 0; i < info->vics_len; i++) { 4587 struct drm_display_mode *mode; 4588 4589 mode = drm_display_mode_from_vic_index(connector, i); 4590 if (mode) { 4591 drm_mode_probed_add(connector, mode); 4592 modes++; 4593 } 4594 } 4595 4596 return modes; 4597 } 4598 4599 struct stereo_mandatory_mode { 4600 int width, height, vrefresh; 4601 unsigned int flags; 4602 }; 4603 4604 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4605 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4606 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4607 { 1920, 1080, 50, 4608 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4609 { 1920, 1080, 60, 4610 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4611 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4612 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4613 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4614 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4615 }; 4616 4617 static bool 4618 stereo_match_mandatory(const struct drm_display_mode *mode, 4619 const struct stereo_mandatory_mode *stereo_mode) 4620 { 4621 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4622 4623 return mode->hdisplay == stereo_mode->width && 4624 mode->vdisplay == stereo_mode->height && 4625 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4626 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4627 } 4628 4629 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4630 { 4631 struct drm_device *dev = connector->dev; 4632 const struct drm_display_mode *mode; 4633 struct list_head stereo_modes; 4634 int modes = 0, i; 4635 4636 INIT_LIST_HEAD(&stereo_modes); 4637 4638 list_for_each_entry(mode, &connector->probed_modes, head) { 4639 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4640 const struct stereo_mandatory_mode *mandatory; 4641 struct drm_display_mode *new_mode; 4642 4643 if (!stereo_match_mandatory(mode, 4644 &stereo_mandatory_modes[i])) 4645 continue; 4646 4647 mandatory = &stereo_mandatory_modes[i]; 4648 new_mode = drm_mode_duplicate(dev, mode); 4649 if (!new_mode) 4650 continue; 4651 4652 new_mode->flags |= mandatory->flags; 4653 list_add_tail(&new_mode->head, &stereo_modes); 4654 modes++; 4655 } 4656 } 4657 4658 list_splice_tail(&stereo_modes, &connector->probed_modes); 4659 4660 return modes; 4661 } 4662 4663 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4664 { 4665 struct drm_device *dev = connector->dev; 4666 struct drm_display_mode *newmode; 4667 4668 if (!drm_valid_hdmi_vic(vic)) { 4669 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4670 connector->base.id, connector->name, vic); 4671 return 0; 4672 } 4673 4674 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4675 if (!newmode) 4676 return 0; 4677 4678 drm_mode_probed_add(connector, newmode); 4679 4680 return 1; 4681 } 4682 4683 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4684 int vic_index) 4685 { 4686 struct drm_display_mode *newmode; 4687 int modes = 0; 4688 4689 if (structure & (1 << 0)) { 4690 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4691 if (newmode) { 4692 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4693 drm_mode_probed_add(connector, newmode); 4694 modes++; 4695 } 4696 } 4697 if (structure & (1 << 6)) { 4698 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4699 if (newmode) { 4700 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4701 drm_mode_probed_add(connector, newmode); 4702 modes++; 4703 } 4704 } 4705 if (structure & (1 << 8)) { 4706 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4707 if (newmode) { 4708 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4709 drm_mode_probed_add(connector, newmode); 4710 modes++; 4711 } 4712 } 4713 4714 return modes; 4715 } 4716 4717 static bool hdmi_vsdb_latency_present(const u8 *db) 4718 { 4719 return db[8] & BIT(7); 4720 } 4721 4722 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4723 { 4724 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4725 } 4726 4727 static int hdmi_vsdb_latency_length(const u8 *db) 4728 { 4729 if (hdmi_vsdb_i_latency_present(db)) 4730 return 4; 4731 else if (hdmi_vsdb_latency_present(db)) 4732 return 2; 4733 else 4734 return 0; 4735 } 4736 4737 /* 4738 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4739 * @connector: connector corresponding to the HDMI sink 4740 * @db: start of the CEA vendor specific block 4741 * @len: length of the CEA block payload, ie. one can access up to db[len] 4742 * 4743 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4744 * also adds the stereo 3d modes when applicable. 4745 */ 4746 static int 4747 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4748 { 4749 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4750 u8 vic_len, hdmi_3d_len = 0; 4751 u16 mask; 4752 u16 structure_all; 4753 4754 if (len < 8) 4755 goto out; 4756 4757 /* no HDMI_Video_Present */ 4758 if (!(db[8] & (1 << 5))) 4759 goto out; 4760 4761 offset += hdmi_vsdb_latency_length(db); 4762 4763 /* the declared length is not long enough for the 2 first bytes 4764 * of additional video format capabilities */ 4765 if (len < (8 + offset + 2)) 4766 goto out; 4767 4768 /* 3D_Present */ 4769 offset++; 4770 if (db[8 + offset] & (1 << 7)) { 4771 modes += add_hdmi_mandatory_stereo_modes(connector); 4772 4773 /* 3D_Multi_present */ 4774 multi_present = (db[8 + offset] & 0x60) >> 5; 4775 } 4776 4777 offset++; 4778 vic_len = db[8 + offset] >> 5; 4779 hdmi_3d_len = db[8 + offset] & 0x1f; 4780 4781 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4782 u8 vic; 4783 4784 vic = db[9 + offset + i]; 4785 modes += add_hdmi_mode(connector, vic); 4786 } 4787 offset += 1 + vic_len; 4788 4789 if (multi_present == 1) 4790 multi_len = 2; 4791 else if (multi_present == 2) 4792 multi_len = 4; 4793 else 4794 multi_len = 0; 4795 4796 if (len < (8 + offset + hdmi_3d_len - 1)) 4797 goto out; 4798 4799 if (hdmi_3d_len < multi_len) 4800 goto out; 4801 4802 if (multi_present == 1 || multi_present == 2) { 4803 /* 3D_Structure_ALL */ 4804 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4805 4806 /* check if 3D_MASK is present */ 4807 if (multi_present == 2) 4808 mask = (db[10 + offset] << 8) | db[11 + offset]; 4809 else 4810 mask = 0xffff; 4811 4812 for (i = 0; i < 16; i++) { 4813 if (mask & (1 << i)) 4814 modes += add_3d_struct_modes(connector, 4815 structure_all, i); 4816 } 4817 } 4818 4819 offset += multi_len; 4820 4821 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4822 int vic_index; 4823 struct drm_display_mode *newmode = NULL; 4824 unsigned int newflag = 0; 4825 bool detail_present; 4826 4827 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4828 4829 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4830 break; 4831 4832 /* 2D_VIC_order_X */ 4833 vic_index = db[8 + offset + i] >> 4; 4834 4835 /* 3D_Structure_X */ 4836 switch (db[8 + offset + i] & 0x0f) { 4837 case 0: 4838 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4839 break; 4840 case 6: 4841 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4842 break; 4843 case 8: 4844 /* 3D_Detail_X */ 4845 if ((db[9 + offset + i] >> 4) == 1) 4846 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4847 break; 4848 } 4849 4850 if (newflag != 0) { 4851 newmode = drm_display_mode_from_vic_index(connector, 4852 vic_index); 4853 4854 if (newmode) { 4855 newmode->flags |= newflag; 4856 drm_mode_probed_add(connector, newmode); 4857 modes++; 4858 } 4859 } 4860 4861 if (detail_present) 4862 i++; 4863 } 4864 4865 out: 4866 return modes; 4867 } 4868 4869 static int 4870 cea_revision(const u8 *cea) 4871 { 4872 /* 4873 * FIXME is this correct for the DispID variant? 4874 * The DispID spec doesn't really specify whether 4875 * this is the revision of the CEA extension or 4876 * the DispID CEA data block. And the only value 4877 * given as an example is 0. 4878 */ 4879 return cea[1]; 4880 } 4881 4882 /* 4883 * CTA Data Block iterator. 4884 * 4885 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4886 * CTA Data Blocks. 4887 * 4888 * struct cea_db *db: 4889 * struct cea_db_iter iter; 4890 * 4891 * cea_db_iter_edid_begin(edid, &iter); 4892 * cea_db_iter_for_each(db, &iter) { 4893 * // do stuff with db 4894 * } 4895 * cea_db_iter_end(&iter); 4896 */ 4897 struct cea_db_iter { 4898 struct drm_edid_iter edid_iter; 4899 struct displayid_iter displayid_iter; 4900 4901 /* Current Data Block Collection. */ 4902 const u8 *collection; 4903 4904 /* Current Data Block index in current collection. */ 4905 int index; 4906 4907 /* End index in current collection. */ 4908 int end; 4909 }; 4910 4911 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4912 struct cea_db { 4913 u8 tag_length; 4914 u8 data[]; 4915 } __packed; 4916 4917 static int cea_db_tag(const struct cea_db *db) 4918 { 4919 return db->tag_length >> 5; 4920 } 4921 4922 static int cea_db_payload_len(const void *_db) 4923 { 4924 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4925 const struct cea_db *db = _db; 4926 4927 return db->tag_length & 0x1f; 4928 } 4929 4930 static const void *cea_db_data(const struct cea_db *db) 4931 { 4932 return db->data; 4933 } 4934 4935 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4936 { 4937 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4938 cea_db_payload_len(db) >= 1 && 4939 db->data[0] == tag; 4940 } 4941 4942 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4943 { 4944 const u8 *data = cea_db_data(db); 4945 4946 return cea_db_tag(db) == CTA_DB_VENDOR && 4947 cea_db_payload_len(db) >= 3 && 4948 oui(data[2], data[1], data[0]) == vendor_oui; 4949 } 4950 4951 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4952 struct cea_db_iter *iter) 4953 { 4954 memset(iter, 0, sizeof(*iter)); 4955 4956 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4957 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4958 } 4959 4960 static const struct cea_db * 4961 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4962 { 4963 const struct cea_db *db; 4964 4965 if (!iter->collection) 4966 return NULL; 4967 4968 db = (const struct cea_db *)&iter->collection[iter->index]; 4969 4970 if (iter->index + sizeof(*db) <= iter->end && 4971 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4972 return db; 4973 4974 return NULL; 4975 } 4976 4977 /* 4978 * References: 4979 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4980 */ 4981 static int cea_db_collection_size(const u8 *cta) 4982 { 4983 u8 d = cta[2]; 4984 4985 if (d < 4 || d > 127) 4986 return 0; 4987 4988 return d - 4; 4989 } 4990 4991 /* 4992 * References: 4993 * - VESA E-EDID v1.4 4994 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4995 */ 4996 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4997 { 4998 const u8 *ext; 4999 5000 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5001 int size; 5002 5003 /* Only support CTA Extension revision 3+ */ 5004 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5005 continue; 5006 5007 size = cea_db_collection_size(ext); 5008 if (!size) 5009 continue; 5010 5011 iter->index = 4; 5012 iter->end = iter->index + size; 5013 5014 return ext; 5015 } 5016 5017 return NULL; 5018 } 5019 5020 /* 5021 * References: 5022 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5023 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5024 * 5025 * Note that the above do not specify any connection between DisplayID Data 5026 * Block revision and CTA Extension versions. 5027 */ 5028 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5029 { 5030 const struct displayid_block *block; 5031 5032 displayid_iter_for_each(block, &iter->displayid_iter) { 5033 if (block->tag != DATA_BLOCK_CTA) 5034 continue; 5035 5036 /* 5037 * The displayid iterator has already verified the block bounds 5038 * in displayid_iter_block(). 5039 */ 5040 iter->index = sizeof(*block); 5041 iter->end = iter->index + block->num_bytes; 5042 5043 return block; 5044 } 5045 5046 return NULL; 5047 } 5048 5049 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5050 { 5051 const struct cea_db *db; 5052 5053 if (iter->collection) { 5054 /* Current collection should always be valid. */ 5055 db = __cea_db_iter_current_block(iter); 5056 if (WARN_ON(!db)) { 5057 iter->collection = NULL; 5058 return NULL; 5059 } 5060 5061 /* Next block in CTA Data Block Collection */ 5062 iter->index += sizeof(*db) + cea_db_payload_len(db); 5063 5064 db = __cea_db_iter_current_block(iter); 5065 if (db) 5066 return db; 5067 } 5068 5069 for (;;) { 5070 /* 5071 * Find the next CTA Data Block Collection. First iterate all 5072 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5073 * 5074 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5075 * Extension, it's recommended that DisplayID extensions are 5076 * exposed after all of the CTA Extensions. 5077 */ 5078 iter->collection = __cea_db_iter_edid_next(iter); 5079 if (!iter->collection) 5080 iter->collection = __cea_db_iter_displayid_next(iter); 5081 5082 if (!iter->collection) 5083 return NULL; 5084 5085 db = __cea_db_iter_current_block(iter); 5086 if (db) 5087 return db; 5088 } 5089 } 5090 5091 #define cea_db_iter_for_each(__db, __iter) \ 5092 while (((__db) = __cea_db_iter_next(__iter))) 5093 5094 static void cea_db_iter_end(struct cea_db_iter *iter) 5095 { 5096 displayid_iter_end(&iter->displayid_iter); 5097 drm_edid_iter_end(&iter->edid_iter); 5098 5099 memset(iter, 0, sizeof(*iter)); 5100 } 5101 5102 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5103 { 5104 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5105 cea_db_payload_len(db) >= 5; 5106 } 5107 5108 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5109 { 5110 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5111 cea_db_payload_len(db) >= 7; 5112 } 5113 5114 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5115 { 5116 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5117 cea_db_payload_len(db) >= 2; 5118 } 5119 5120 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5121 { 5122 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5123 cea_db_payload_len(db) == 21; 5124 } 5125 5126 static bool cea_db_is_vcdb(const struct cea_db *db) 5127 { 5128 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5129 cea_db_payload_len(db) == 2; 5130 } 5131 5132 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5133 { 5134 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5135 cea_db_payload_len(db) >= 7; 5136 } 5137 5138 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5139 { 5140 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5141 } 5142 5143 static bool cea_db_is_y420vdb(const struct cea_db *db) 5144 { 5145 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5146 } 5147 5148 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5149 { 5150 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5151 cea_db_payload_len(db) >= 3; 5152 } 5153 5154 /* 5155 * Get the HF-EEODB override extension block count from EDID. 5156 * 5157 * The passed in EDID may be partially read, as long as it has at least two 5158 * blocks (base block and one extension block) if EDID extension count is > 0. 5159 * 5160 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5161 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5162 * iterators instead. 5163 * 5164 * References: 5165 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5166 */ 5167 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5168 { 5169 const u8 *cta; 5170 5171 /* No extensions according to base block, no HF-EEODB. */ 5172 if (!edid_extension_block_count(edid)) 5173 return 0; 5174 5175 /* HF-EEODB is always in the first EDID extension block only */ 5176 cta = edid_extension_block_data(edid, 0); 5177 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5178 return 0; 5179 5180 /* Need to have the data block collection, and at least 3 bytes. */ 5181 if (cea_db_collection_size(cta) < 3) 5182 return 0; 5183 5184 /* 5185 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5186 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5187 * through 6 of Block 1 of the E-EDID. 5188 */ 5189 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5190 return 0; 5191 5192 return cta[4 + 2]; 5193 } 5194 5195 /* 5196 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5197 * 5198 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5199 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5200 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5201 * support YCBCR420 output too. 5202 */ 5203 static void parse_cta_y420cmdb(struct drm_connector *connector, 5204 const struct cea_db *db, u64 *y420cmdb_map) 5205 { 5206 struct drm_display_info *info = &connector->display_info; 5207 int i, map_len = cea_db_payload_len(db) - 1; 5208 const u8 *data = cea_db_data(db) + 1; 5209 u64 map = 0; 5210 5211 if (map_len == 0) { 5212 /* All CEA modes support ycbcr420 sampling also.*/ 5213 map = U64_MAX; 5214 goto out; 5215 } 5216 5217 /* 5218 * This map indicates which of the existing CEA block modes 5219 * from VDB can support YCBCR420 output too. So if bit=0 is 5220 * set, first mode from VDB can support YCBCR420 output too. 5221 * We will parse and keep this map, before parsing VDB itself 5222 * to avoid going through the same block again and again. 5223 * 5224 * Spec is not clear about max possible size of this block. 5225 * Clamping max bitmap block size at 8 bytes. Every byte can 5226 * address 8 CEA modes, in this way this map can address 5227 * 8*8 = first 64 SVDs. 5228 */ 5229 if (WARN_ON_ONCE(map_len > 8)) 5230 map_len = 8; 5231 5232 for (i = 0; i < map_len; i++) 5233 map |= (u64)data[i] << (8 * i); 5234 5235 out: 5236 if (map) 5237 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5238 5239 *y420cmdb_map = map; 5240 } 5241 5242 static int add_cea_modes(struct drm_connector *connector, 5243 const struct drm_edid *drm_edid) 5244 { 5245 const struct cea_db *db; 5246 struct cea_db_iter iter; 5247 int modes; 5248 5249 /* CTA VDB block VICs parsed earlier */ 5250 modes = add_cta_vdb_modes(connector); 5251 5252 cea_db_iter_edid_begin(drm_edid, &iter); 5253 cea_db_iter_for_each(db, &iter) { 5254 if (cea_db_is_hdmi_vsdb(db)) { 5255 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5256 cea_db_payload_len(db)); 5257 } else if (cea_db_is_y420vdb(db)) { 5258 const u8 *vdb420 = cea_db_data(db) + 1; 5259 5260 /* Add 4:2:0(only) modes present in EDID */ 5261 modes += do_y420vdb_modes(connector, vdb420, 5262 cea_db_payload_len(db) - 1); 5263 } 5264 } 5265 cea_db_iter_end(&iter); 5266 5267 return modes; 5268 } 5269 5270 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5271 struct drm_display_mode *mode) 5272 { 5273 const struct drm_display_mode *cea_mode; 5274 int clock1, clock2, clock; 5275 u8 vic; 5276 const char *type; 5277 5278 /* 5279 * allow 5kHz clock difference either way to account for 5280 * the 10kHz clock resolution limit of detailed timings. 5281 */ 5282 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5283 if (drm_valid_cea_vic(vic)) { 5284 type = "CEA"; 5285 cea_mode = cea_mode_for_vic(vic); 5286 clock1 = cea_mode->clock; 5287 clock2 = cea_mode_alternate_clock(cea_mode); 5288 } else { 5289 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5290 if (drm_valid_hdmi_vic(vic)) { 5291 type = "HDMI"; 5292 cea_mode = &edid_4k_modes[vic]; 5293 clock1 = cea_mode->clock; 5294 clock2 = hdmi_mode_alternate_clock(cea_mode); 5295 } else { 5296 return; 5297 } 5298 } 5299 5300 /* pick whichever is closest */ 5301 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5302 clock = clock1; 5303 else 5304 clock = clock2; 5305 5306 if (mode->clock == clock) 5307 return; 5308 5309 drm_dbg_kms(connector->dev, 5310 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5311 connector->base.id, connector->name, 5312 type, vic, mode->clock, clock); 5313 mode->clock = clock; 5314 } 5315 5316 static void drm_calculate_luminance_range(struct drm_connector *connector) 5317 { 5318 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5319 struct drm_luminance_range_info *luminance_range = 5320 &connector->display_info.luminance_range; 5321 static const u8 pre_computed_values[] = { 5322 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5323 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5324 }; 5325 u32 max_avg, min_cll, max, min, q, r; 5326 5327 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5328 return; 5329 5330 max_avg = hdr_metadata->max_fall; 5331 min_cll = hdr_metadata->min_cll; 5332 5333 /* 5334 * From the specification (CTA-861-G), for calculating the maximum 5335 * luminance we need to use: 5336 * Luminance = 50*2**(CV/32) 5337 * Where CV is a one-byte value. 5338 * For calculating this expression we may need float point precision; 5339 * to avoid this complexity level, we take advantage that CV is divided 5340 * by a constant. From the Euclids division algorithm, we know that CV 5341 * can be written as: CV = 32*q + r. Next, we replace CV in the 5342 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5343 * need to pre-compute the value of r/32. For pre-computing the values 5344 * We just used the following Ruby line: 5345 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5346 * The results of the above expressions can be verified at 5347 * pre_computed_values. 5348 */ 5349 q = max_avg >> 5; 5350 r = max_avg % 32; 5351 max = (1 << q) * pre_computed_values[r]; 5352 5353 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5354 q = DIV_ROUND_CLOSEST(min_cll, 255); 5355 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5356 5357 luminance_range->min_luminance = min; 5358 luminance_range->max_luminance = max; 5359 } 5360 5361 static uint8_t eotf_supported(const u8 *edid_ext) 5362 { 5363 return edid_ext[2] & 5364 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5365 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5366 BIT(HDMI_EOTF_SMPTE_ST2084) | 5367 BIT(HDMI_EOTF_BT_2100_HLG)); 5368 } 5369 5370 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5371 { 5372 return edid_ext[3] & 5373 BIT(HDMI_STATIC_METADATA_TYPE1); 5374 } 5375 5376 static void 5377 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5378 { 5379 u16 len; 5380 5381 len = cea_db_payload_len(db); 5382 5383 connector->hdr_sink_metadata.hdmi_type1.eotf = 5384 eotf_supported(db); 5385 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5386 hdr_metadata_type(db); 5387 5388 if (len >= 4) 5389 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5390 if (len >= 5) 5391 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5392 if (len >= 6) { 5393 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5394 5395 /* Calculate only when all values are available */ 5396 drm_calculate_luminance_range(connector); 5397 } 5398 } 5399 5400 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5401 static void 5402 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5403 { 5404 u8 len = cea_db_payload_len(db); 5405 5406 if (len >= 6 && (db[6] & (1 << 7))) 5407 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5408 5409 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5410 connector->latency_present[0] = true; 5411 connector->video_latency[0] = db[9]; 5412 connector->audio_latency[0] = db[10]; 5413 } 5414 5415 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5416 connector->latency_present[1] = true; 5417 connector->video_latency[1] = db[11]; 5418 connector->audio_latency[1] = db[12]; 5419 } 5420 5421 drm_dbg_kms(connector->dev, 5422 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5423 connector->base.id, connector->name, 5424 connector->latency_present[0], connector->latency_present[1], 5425 connector->video_latency[0], connector->video_latency[1], 5426 connector->audio_latency[0], connector->audio_latency[1]); 5427 } 5428 5429 static void 5430 monitor_name(const struct detailed_timing *timing, void *data) 5431 { 5432 const char **res = data; 5433 5434 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5435 return; 5436 5437 *res = timing->data.other_data.data.str.str; 5438 } 5439 5440 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5441 { 5442 const char *edid_name = NULL; 5443 int mnl; 5444 5445 if (!drm_edid || !name) 5446 return 0; 5447 5448 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5449 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5450 if (edid_name[mnl] == 0x0a) 5451 break; 5452 5453 name[mnl] = edid_name[mnl]; 5454 } 5455 5456 return mnl; 5457 } 5458 5459 /** 5460 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5461 * @edid: monitor EDID information 5462 * @name: pointer to a character array to hold the name of the monitor 5463 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5464 * 5465 */ 5466 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5467 { 5468 int name_length = 0; 5469 5470 if (bufsize <= 0) 5471 return; 5472 5473 if (edid) { 5474 char buf[13]; 5475 struct drm_edid drm_edid = { 5476 .edid = edid, 5477 .size = edid_size(edid), 5478 }; 5479 5480 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5481 memcpy(name, buf, name_length); 5482 } 5483 5484 name[name_length] = '\0'; 5485 } 5486 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5487 5488 static void clear_eld(struct drm_connector *connector) 5489 { 5490 memset(connector->eld, 0, sizeof(connector->eld)); 5491 5492 connector->latency_present[0] = false; 5493 connector->latency_present[1] = false; 5494 connector->video_latency[0] = 0; 5495 connector->audio_latency[0] = 0; 5496 connector->video_latency[1] = 0; 5497 connector->audio_latency[1] = 0; 5498 } 5499 5500 /* 5501 * drm_edid_to_eld - build ELD from EDID 5502 * @connector: connector corresponding to the HDMI/DP sink 5503 * @drm_edid: EDID to parse 5504 * 5505 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5506 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5507 */ 5508 static void drm_edid_to_eld(struct drm_connector *connector, 5509 const struct drm_edid *drm_edid) 5510 { 5511 const struct drm_display_info *info = &connector->display_info; 5512 const struct cea_db *db; 5513 struct cea_db_iter iter; 5514 uint8_t *eld = connector->eld; 5515 int total_sad_count = 0; 5516 int mnl; 5517 5518 if (!drm_edid) 5519 return; 5520 5521 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5522 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5523 connector->base.id, connector->name, 5524 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5525 5526 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5527 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5528 5529 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5530 5531 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5532 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5533 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5534 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5535 5536 cea_db_iter_edid_begin(drm_edid, &iter); 5537 cea_db_iter_for_each(db, &iter) { 5538 const u8 *data = cea_db_data(db); 5539 int len = cea_db_payload_len(db); 5540 int sad_count; 5541 5542 switch (cea_db_tag(db)) { 5543 case CTA_DB_AUDIO: 5544 /* Audio Data Block, contains SADs */ 5545 sad_count = min(len / 3, 15 - total_sad_count); 5546 if (sad_count >= 1) 5547 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5548 data, sad_count * 3); 5549 total_sad_count += sad_count; 5550 break; 5551 case CTA_DB_SPEAKER: 5552 /* Speaker Allocation Data Block */ 5553 if (len >= 1) 5554 eld[DRM_ELD_SPEAKER] = data[0]; 5555 break; 5556 case CTA_DB_VENDOR: 5557 /* HDMI Vendor-Specific Data Block */ 5558 if (cea_db_is_hdmi_vsdb(db)) 5559 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5560 break; 5561 default: 5562 break; 5563 } 5564 } 5565 cea_db_iter_end(&iter); 5566 5567 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5568 5569 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5570 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5571 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5572 else 5573 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5574 5575 eld[DRM_ELD_BASELINE_ELD_LEN] = 5576 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5577 5578 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5579 connector->base.id, connector->name, 5580 drm_eld_size(eld), total_sad_count); 5581 } 5582 5583 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5584 struct cea_sad **sads) 5585 { 5586 const struct cea_db *db; 5587 struct cea_db_iter iter; 5588 int count = 0; 5589 5590 cea_db_iter_edid_begin(drm_edid, &iter); 5591 cea_db_iter_for_each(db, &iter) { 5592 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5593 int j; 5594 5595 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5596 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5597 if (!*sads) 5598 return -ENOMEM; 5599 for (j = 0; j < count; j++) { 5600 const u8 *sad = &db->data[j * 3]; 5601 5602 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5603 (*sads)[j].channels = sad[0] & 0x7; 5604 (*sads)[j].freq = sad[1] & 0x7F; 5605 (*sads)[j].byte2 = sad[2]; 5606 } 5607 break; 5608 } 5609 } 5610 cea_db_iter_end(&iter); 5611 5612 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5613 5614 return count; 5615 } 5616 5617 /** 5618 * drm_edid_to_sad - extracts SADs from EDID 5619 * @edid: EDID to parse 5620 * @sads: pointer that will be set to the extracted SADs 5621 * 5622 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5623 * 5624 * Note: The returned pointer needs to be freed using kfree(). 5625 * 5626 * Return: The number of found SADs or negative number on error. 5627 */ 5628 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5629 { 5630 struct drm_edid drm_edid; 5631 5632 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5633 } 5634 EXPORT_SYMBOL(drm_edid_to_sad); 5635 5636 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5637 u8 **sadb) 5638 { 5639 const struct cea_db *db; 5640 struct cea_db_iter iter; 5641 int count = 0; 5642 5643 cea_db_iter_edid_begin(drm_edid, &iter); 5644 cea_db_iter_for_each(db, &iter) { 5645 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5646 cea_db_payload_len(db) == 3) { 5647 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5648 GFP_KERNEL); 5649 if (!*sadb) 5650 return -ENOMEM; 5651 count = cea_db_payload_len(db); 5652 break; 5653 } 5654 } 5655 cea_db_iter_end(&iter); 5656 5657 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5658 5659 return count; 5660 } 5661 5662 /** 5663 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5664 * @edid: EDID to parse 5665 * @sadb: pointer to the speaker block 5666 * 5667 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5668 * 5669 * Note: The returned pointer needs to be freed using kfree(). 5670 * 5671 * Return: The number of found Speaker Allocation Blocks or negative number on 5672 * error. 5673 */ 5674 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5675 { 5676 struct drm_edid drm_edid; 5677 5678 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5679 sadb); 5680 } 5681 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5682 5683 /** 5684 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5685 * @connector: connector associated with the HDMI/DP sink 5686 * @mode: the display mode 5687 * 5688 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5689 * the sink doesn't support audio or video. 5690 */ 5691 int drm_av_sync_delay(struct drm_connector *connector, 5692 const struct drm_display_mode *mode) 5693 { 5694 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5695 int a, v; 5696 5697 if (!connector->latency_present[0]) 5698 return 0; 5699 if (!connector->latency_present[1]) 5700 i = 0; 5701 5702 a = connector->audio_latency[i]; 5703 v = connector->video_latency[i]; 5704 5705 /* 5706 * HDMI/DP sink doesn't support audio or video? 5707 */ 5708 if (a == 255 || v == 255) 5709 return 0; 5710 5711 /* 5712 * Convert raw EDID values to millisecond. 5713 * Treat unknown latency as 0ms. 5714 */ 5715 if (a) 5716 a = min(2 * (a - 1), 500); 5717 if (v) 5718 v = min(2 * (v - 1), 500); 5719 5720 return max(v - a, 0); 5721 } 5722 EXPORT_SYMBOL(drm_av_sync_delay); 5723 5724 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5725 { 5726 const struct cea_db *db; 5727 struct cea_db_iter iter; 5728 bool hdmi = false; 5729 5730 /* 5731 * Because HDMI identifier is in Vendor Specific Block, 5732 * search it from all data blocks of CEA extension. 5733 */ 5734 cea_db_iter_edid_begin(drm_edid, &iter); 5735 cea_db_iter_for_each(db, &iter) { 5736 if (cea_db_is_hdmi_vsdb(db)) { 5737 hdmi = true; 5738 break; 5739 } 5740 } 5741 cea_db_iter_end(&iter); 5742 5743 return hdmi; 5744 } 5745 5746 /** 5747 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5748 * @edid: monitor EDID information 5749 * 5750 * Parse the CEA extension according to CEA-861-B. 5751 * 5752 * Drivers that have added the modes parsed from EDID to drm_display_info 5753 * should use &drm_display_info.is_hdmi instead of calling this function. 5754 * 5755 * Return: True if the monitor is HDMI, false if not or unknown. 5756 */ 5757 bool drm_detect_hdmi_monitor(const struct edid *edid) 5758 { 5759 struct drm_edid drm_edid; 5760 5761 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5762 } 5763 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5764 5765 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5766 { 5767 struct drm_edid_iter edid_iter; 5768 const struct cea_db *db; 5769 struct cea_db_iter iter; 5770 const u8 *edid_ext; 5771 bool has_audio = false; 5772 5773 drm_edid_iter_begin(drm_edid, &edid_iter); 5774 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5775 if (edid_ext[0] == CEA_EXT) { 5776 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5777 if (has_audio) 5778 break; 5779 } 5780 } 5781 drm_edid_iter_end(&edid_iter); 5782 5783 if (has_audio) { 5784 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5785 goto end; 5786 } 5787 5788 cea_db_iter_edid_begin(drm_edid, &iter); 5789 cea_db_iter_for_each(db, &iter) { 5790 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5791 const u8 *data = cea_db_data(db); 5792 int i; 5793 5794 for (i = 0; i < cea_db_payload_len(db); i += 3) 5795 DRM_DEBUG_KMS("CEA audio format %d\n", 5796 (data[i] >> 3) & 0xf); 5797 has_audio = true; 5798 break; 5799 } 5800 } 5801 cea_db_iter_end(&iter); 5802 5803 end: 5804 return has_audio; 5805 } 5806 5807 /** 5808 * drm_detect_monitor_audio - check monitor audio capability 5809 * @edid: EDID block to scan 5810 * 5811 * Monitor should have CEA extension block. 5812 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5813 * audio' only. If there is any audio extension block and supported 5814 * audio format, assume at least 'basic audio' support, even if 'basic 5815 * audio' is not defined in EDID. 5816 * 5817 * Return: True if the monitor supports audio, false otherwise. 5818 */ 5819 bool drm_detect_monitor_audio(const struct edid *edid) 5820 { 5821 struct drm_edid drm_edid; 5822 5823 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5824 } 5825 EXPORT_SYMBOL(drm_detect_monitor_audio); 5826 5827 5828 /** 5829 * drm_default_rgb_quant_range - default RGB quantization range 5830 * @mode: display mode 5831 * 5832 * Determine the default RGB quantization range for the mode, 5833 * as specified in CEA-861. 5834 * 5835 * Return: The default RGB quantization range for the mode 5836 */ 5837 enum hdmi_quantization_range 5838 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5839 { 5840 /* All CEA modes other than VIC 1 use limited quantization range. */ 5841 return drm_match_cea_mode(mode) > 1 ? 5842 HDMI_QUANTIZATION_RANGE_LIMITED : 5843 HDMI_QUANTIZATION_RANGE_FULL; 5844 } 5845 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5846 5847 /* CTA-861 Video Data Block (CTA VDB) */ 5848 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5849 { 5850 struct drm_display_info *info = &connector->display_info; 5851 int i, vic_index, len = cea_db_payload_len(db); 5852 const u8 *svds = cea_db_data(db); 5853 u8 *vics; 5854 5855 if (!len) 5856 return; 5857 5858 /* Gracefully handle multiple VDBs, however unlikely that is */ 5859 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5860 if (!vics) 5861 return; 5862 5863 vic_index = info->vics_len; 5864 info->vics_len += len; 5865 info->vics = vics; 5866 5867 for (i = 0; i < len; i++) { 5868 u8 vic = svd_to_vic(svds[i]); 5869 5870 if (!drm_valid_cea_vic(vic)) 5871 vic = 0; 5872 5873 info->vics[vic_index++] = vic; 5874 } 5875 } 5876 5877 /* 5878 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5879 * 5880 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5881 * using the VICs themselves. 5882 */ 5883 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5884 { 5885 struct drm_display_info *info = &connector->display_info; 5886 struct drm_hdmi_info *hdmi = &info->hdmi; 5887 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5888 5889 for (i = 0; i < len; i++) { 5890 u8 vic = info->vics[i]; 5891 5892 if (vic && y420cmdb_map & BIT_ULL(i)) 5893 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5894 } 5895 } 5896 5897 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5898 { 5899 const struct drm_display_info *info = &connector->display_info; 5900 int i; 5901 5902 if (!vic || !info->vics) 5903 return false; 5904 5905 for (i = 0; i < info->vics_len; i++) { 5906 if (info->vics[i] == vic) 5907 return true; 5908 } 5909 5910 return false; 5911 } 5912 5913 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5914 static void parse_cta_y420vdb(struct drm_connector *connector, 5915 const struct cea_db *db) 5916 { 5917 struct drm_display_info *info = &connector->display_info; 5918 struct drm_hdmi_info *hdmi = &info->hdmi; 5919 const u8 *svds = cea_db_data(db) + 1; 5920 int i; 5921 5922 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5923 u8 vic = svd_to_vic(svds[i]); 5924 5925 if (!drm_valid_cea_vic(vic)) 5926 continue; 5927 5928 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5929 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5930 } 5931 } 5932 5933 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5934 { 5935 struct drm_display_info *info = &connector->display_info; 5936 5937 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5938 connector->base.id, connector->name, db[2]); 5939 5940 if (db[2] & EDID_CEA_VCDB_QS) 5941 info->rgb_quant_range_selectable = true; 5942 } 5943 5944 static 5945 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5946 { 5947 switch (max_frl_rate) { 5948 case 1: 5949 *max_lanes = 3; 5950 *max_rate_per_lane = 3; 5951 break; 5952 case 2: 5953 *max_lanes = 3; 5954 *max_rate_per_lane = 6; 5955 break; 5956 case 3: 5957 *max_lanes = 4; 5958 *max_rate_per_lane = 6; 5959 break; 5960 case 4: 5961 *max_lanes = 4; 5962 *max_rate_per_lane = 8; 5963 break; 5964 case 5: 5965 *max_lanes = 4; 5966 *max_rate_per_lane = 10; 5967 break; 5968 case 6: 5969 *max_lanes = 4; 5970 *max_rate_per_lane = 12; 5971 break; 5972 case 0: 5973 default: 5974 *max_lanes = 0; 5975 *max_rate_per_lane = 0; 5976 } 5977 } 5978 5979 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5980 const u8 *db) 5981 { 5982 u8 dc_mask; 5983 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5984 5985 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5986 hdmi->y420_dc_modes = dc_mask; 5987 } 5988 5989 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 5990 const u8 *hf_scds) 5991 { 5992 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5993 5994 if (!hdmi_dsc->v_1p2) 5995 return; 5996 5997 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5998 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5999 6000 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6001 hdmi_dsc->bpc_supported = 16; 6002 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6003 hdmi_dsc->bpc_supported = 12; 6004 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6005 hdmi_dsc->bpc_supported = 10; 6006 else 6007 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6008 hdmi_dsc->bpc_supported = 8; 6009 6010 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6011 u8 dsc_max_slices; 6012 u8 dsc_max_frl_rate; 6013 6014 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6015 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6016 &hdmi_dsc->max_frl_rate_per_lane); 6017 6018 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6019 6020 switch (dsc_max_slices) { 6021 case 1: 6022 hdmi_dsc->max_slices = 1; 6023 hdmi_dsc->clk_per_slice = 340; 6024 break; 6025 case 2: 6026 hdmi_dsc->max_slices = 2; 6027 hdmi_dsc->clk_per_slice = 340; 6028 break; 6029 case 3: 6030 hdmi_dsc->max_slices = 4; 6031 hdmi_dsc->clk_per_slice = 340; 6032 break; 6033 case 4: 6034 hdmi_dsc->max_slices = 8; 6035 hdmi_dsc->clk_per_slice = 340; 6036 break; 6037 case 5: 6038 hdmi_dsc->max_slices = 8; 6039 hdmi_dsc->clk_per_slice = 400; 6040 break; 6041 case 6: 6042 hdmi_dsc->max_slices = 12; 6043 hdmi_dsc->clk_per_slice = 400; 6044 break; 6045 case 7: 6046 hdmi_dsc->max_slices = 16; 6047 hdmi_dsc->clk_per_slice = 400; 6048 break; 6049 case 0: 6050 default: 6051 hdmi_dsc->max_slices = 0; 6052 hdmi_dsc->clk_per_slice = 0; 6053 } 6054 } 6055 6056 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6057 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6058 } 6059 6060 /* Sink Capability Data Structure */ 6061 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6062 const u8 *hf_scds) 6063 { 6064 struct drm_display_info *info = &connector->display_info; 6065 struct drm_hdmi_info *hdmi = &info->hdmi; 6066 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6067 int max_tmds_clock = 0; 6068 u8 max_frl_rate = 0; 6069 bool dsc_support = false; 6070 6071 info->has_hdmi_infoframe = true; 6072 6073 if (hf_scds[6] & 0x80) { 6074 hdmi->scdc.supported = true; 6075 if (hf_scds[6] & 0x40) 6076 hdmi->scdc.read_request = true; 6077 } 6078 6079 /* 6080 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6081 * And as per the spec, three factors confirm this: 6082 * * Availability of a HF-VSDB block in EDID (check) 6083 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6084 * * SCDC support available (let's check) 6085 * Lets check it out. 6086 */ 6087 6088 if (hf_scds[5]) { 6089 struct drm_scdc *scdc = &hdmi->scdc; 6090 6091 /* max clock is 5000 KHz times block value */ 6092 max_tmds_clock = hf_scds[5] * 5000; 6093 6094 if (max_tmds_clock > 340000) { 6095 info->max_tmds_clock = max_tmds_clock; 6096 } 6097 6098 if (scdc->supported) { 6099 scdc->scrambling.supported = true; 6100 6101 /* Few sinks support scrambling for clocks < 340M */ 6102 if ((hf_scds[6] & 0x8)) 6103 scdc->scrambling.low_rates = true; 6104 } 6105 } 6106 6107 if (hf_scds[7]) { 6108 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6109 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6110 &hdmi->max_frl_rate_per_lane); 6111 } 6112 6113 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6114 6115 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6116 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6117 dsc_support = true; 6118 } 6119 6120 drm_dbg_kms(connector->dev, 6121 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6122 connector->base.id, connector->name, 6123 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6124 } 6125 6126 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6127 const u8 *hdmi) 6128 { 6129 struct drm_display_info *info = &connector->display_info; 6130 unsigned int dc_bpc = 0; 6131 6132 /* HDMI supports at least 8 bpc */ 6133 info->bpc = 8; 6134 6135 if (cea_db_payload_len(hdmi) < 6) 6136 return; 6137 6138 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6139 dc_bpc = 10; 6140 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6141 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6142 connector->base.id, connector->name); 6143 } 6144 6145 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6146 dc_bpc = 12; 6147 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6148 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6149 connector->base.id, connector->name); 6150 } 6151 6152 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6153 dc_bpc = 16; 6154 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6155 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6156 connector->base.id, connector->name); 6157 } 6158 6159 if (dc_bpc == 0) { 6160 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6161 connector->base.id, connector->name); 6162 return; 6163 } 6164 6165 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6166 connector->base.id, connector->name, dc_bpc); 6167 info->bpc = dc_bpc; 6168 6169 /* YCRCB444 is optional according to spec. */ 6170 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6171 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6172 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6173 connector->base.id, connector->name); 6174 } 6175 6176 /* 6177 * Spec says that if any deep color mode is supported at all, 6178 * then deep color 36 bit must be supported. 6179 */ 6180 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6181 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6182 connector->base.id, connector->name); 6183 } 6184 } 6185 6186 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6187 static void 6188 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6189 { 6190 struct drm_display_info *info = &connector->display_info; 6191 u8 len = cea_db_payload_len(db); 6192 6193 info->is_hdmi = true; 6194 6195 if (len >= 6) 6196 info->dvi_dual = db[6] & 1; 6197 if (len >= 7) 6198 info->max_tmds_clock = db[7] * 5000; 6199 6200 /* 6201 * Try to infer whether the sink supports HDMI infoframes. 6202 * 6203 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6204 * supports infoframes if HDMI_Video_present is set. 6205 */ 6206 if (len >= 8 && db[8] & BIT(5)) 6207 info->has_hdmi_infoframe = true; 6208 6209 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6210 connector->base.id, connector->name, 6211 info->dvi_dual, info->max_tmds_clock); 6212 6213 drm_parse_hdmi_deep_color_info(connector, db); 6214 } 6215 6216 /* 6217 * See EDID extension for head-mounted and specialized monitors, specified at: 6218 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6219 */ 6220 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6221 const u8 *db) 6222 { 6223 struct drm_display_info *info = &connector->display_info; 6224 u8 version = db[4]; 6225 bool desktop_usage = db[5] & BIT(6); 6226 6227 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6228 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6229 info->non_desktop = true; 6230 6231 drm_dbg_kms(connector->dev, 6232 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6233 connector->base.id, connector->name, version, db[5]); 6234 } 6235 6236 static void drm_parse_cea_ext(struct drm_connector *connector, 6237 const struct drm_edid *drm_edid) 6238 { 6239 struct drm_display_info *info = &connector->display_info; 6240 struct drm_edid_iter edid_iter; 6241 const struct cea_db *db; 6242 struct cea_db_iter iter; 6243 const u8 *edid_ext; 6244 u64 y420cmdb_map = 0; 6245 6246 drm_edid_iter_begin(drm_edid, &edid_iter); 6247 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6248 if (edid_ext[0] != CEA_EXT) 6249 continue; 6250 6251 if (!info->cea_rev) 6252 info->cea_rev = edid_ext[1]; 6253 6254 if (info->cea_rev != edid_ext[1]) 6255 drm_dbg_kms(connector->dev, 6256 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6257 connector->base.id, connector->name, 6258 info->cea_rev, edid_ext[1]); 6259 6260 /* The existence of a CTA extension should imply RGB support */ 6261 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6262 if (edid_ext[3] & EDID_CEA_YCRCB444) 6263 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6264 if (edid_ext[3] & EDID_CEA_YCRCB422) 6265 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6266 if (edid_ext[3] & EDID_BASIC_AUDIO) 6267 info->has_audio = true; 6268 6269 } 6270 drm_edid_iter_end(&edid_iter); 6271 6272 cea_db_iter_edid_begin(drm_edid, &iter); 6273 cea_db_iter_for_each(db, &iter) { 6274 /* FIXME: convert parsers to use struct cea_db */ 6275 const u8 *data = (const u8 *)db; 6276 6277 if (cea_db_is_hdmi_vsdb(db)) 6278 drm_parse_hdmi_vsdb_video(connector, data); 6279 else if (cea_db_is_hdmi_forum_vsdb(db) || 6280 cea_db_is_hdmi_forum_scdb(db)) 6281 drm_parse_hdmi_forum_scds(connector, data); 6282 else if (cea_db_is_microsoft_vsdb(db)) 6283 drm_parse_microsoft_vsdb(connector, data); 6284 else if (cea_db_is_y420cmdb(db)) 6285 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6286 else if (cea_db_is_y420vdb(db)) 6287 parse_cta_y420vdb(connector, db); 6288 else if (cea_db_is_vcdb(db)) 6289 drm_parse_vcdb(connector, data); 6290 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6291 drm_parse_hdr_metadata_block(connector, data); 6292 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6293 parse_cta_vdb(connector, db); 6294 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6295 info->has_audio = true; 6296 } 6297 cea_db_iter_end(&iter); 6298 6299 if (y420cmdb_map) 6300 update_cta_y420cmdb(connector, y420cmdb_map); 6301 } 6302 6303 static 6304 void get_monitor_range(const struct detailed_timing *timing, void *c) 6305 { 6306 struct detailed_mode_closure *closure = c; 6307 struct drm_display_info *info = &closure->connector->display_info; 6308 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6309 const struct detailed_non_pixel *data = &timing->data.other_data; 6310 const struct detailed_data_monitor_range *range = &data->data.range; 6311 const struct edid *edid = closure->drm_edid->edid; 6312 6313 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6314 return; 6315 6316 /* 6317 * These limits are used to determine the VRR refresh 6318 * rate range. Only the "range limits only" variant 6319 * of the range descriptor seems to guarantee that 6320 * any and all timings are accepted by the sink, as 6321 * opposed to just timings conforming to the indicated 6322 * formula (GTF/GTF2/CVT). Thus other variants of the 6323 * range descriptor are not accepted here. 6324 */ 6325 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6326 return; 6327 6328 monitor_range->min_vfreq = range->min_vfreq; 6329 monitor_range->max_vfreq = range->max_vfreq; 6330 6331 if (edid->revision >= 4) { 6332 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6333 monitor_range->min_vfreq += 255; 6334 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6335 monitor_range->max_vfreq += 255; 6336 } 6337 } 6338 6339 static void drm_get_monitor_range(struct drm_connector *connector, 6340 const struct drm_edid *drm_edid) 6341 { 6342 const struct drm_display_info *info = &connector->display_info; 6343 struct detailed_mode_closure closure = { 6344 .connector = connector, 6345 .drm_edid = drm_edid, 6346 }; 6347 6348 if (drm_edid->edid->revision < 4) 6349 return; 6350 6351 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6352 return; 6353 6354 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6355 6356 drm_dbg_kms(connector->dev, 6357 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6358 connector->base.id, connector->name, 6359 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6360 } 6361 6362 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6363 const struct displayid_block *block) 6364 { 6365 struct displayid_vesa_vendor_specific_block *vesa = 6366 (struct displayid_vesa_vendor_specific_block *)block; 6367 struct drm_display_info *info = &connector->display_info; 6368 6369 if (block->num_bytes < 3) { 6370 drm_dbg_kms(connector->dev, 6371 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6372 connector->base.id, connector->name, block->num_bytes); 6373 return; 6374 } 6375 6376 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6377 return; 6378 6379 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6380 drm_dbg_kms(connector->dev, 6381 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6382 connector->base.id, connector->name); 6383 return; 6384 } 6385 6386 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6387 default: 6388 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6389 connector->base.id, connector->name); 6390 fallthrough; 6391 case 0: 6392 info->mso_stream_count = 0; 6393 break; 6394 case 1: 6395 info->mso_stream_count = 2; /* 2 or 4 links */ 6396 break; 6397 case 2: 6398 info->mso_stream_count = 4; /* 4 links */ 6399 break; 6400 } 6401 6402 if (!info->mso_stream_count) { 6403 info->mso_pixel_overlap = 0; 6404 return; 6405 } 6406 6407 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6408 if (info->mso_pixel_overlap > 8) { 6409 drm_dbg_kms(connector->dev, 6410 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6411 connector->base.id, connector->name, 6412 info->mso_pixel_overlap); 6413 info->mso_pixel_overlap = 8; 6414 } 6415 6416 drm_dbg_kms(connector->dev, 6417 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6418 connector->base.id, connector->name, 6419 info->mso_stream_count, info->mso_pixel_overlap); 6420 } 6421 6422 static void drm_update_mso(struct drm_connector *connector, 6423 const struct drm_edid *drm_edid) 6424 { 6425 const struct displayid_block *block; 6426 struct displayid_iter iter; 6427 6428 displayid_iter_edid_begin(drm_edid, &iter); 6429 displayid_iter_for_each(block, &iter) { 6430 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6431 drm_parse_vesa_mso_data(connector, block); 6432 } 6433 displayid_iter_end(&iter); 6434 } 6435 6436 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6437 * all of the values which would have been set from EDID 6438 */ 6439 static void drm_reset_display_info(struct drm_connector *connector) 6440 { 6441 struct drm_display_info *info = &connector->display_info; 6442 6443 info->width_mm = 0; 6444 info->height_mm = 0; 6445 6446 info->bpc = 0; 6447 info->color_formats = 0; 6448 info->cea_rev = 0; 6449 info->max_tmds_clock = 0; 6450 info->dvi_dual = false; 6451 info->is_hdmi = false; 6452 info->has_audio = false; 6453 info->has_hdmi_infoframe = false; 6454 info->rgb_quant_range_selectable = false; 6455 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6456 6457 info->edid_hdmi_rgb444_dc_modes = 0; 6458 info->edid_hdmi_ycbcr444_dc_modes = 0; 6459 6460 info->non_desktop = 0; 6461 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6462 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6463 6464 info->mso_stream_count = 0; 6465 info->mso_pixel_overlap = 0; 6466 info->max_dsc_bpp = 0; 6467 6468 kfree(info->vics); 6469 info->vics = NULL; 6470 info->vics_len = 0; 6471 6472 info->quirks = 0; 6473 } 6474 6475 static void update_displayid_info(struct drm_connector *connector, 6476 const struct drm_edid *drm_edid) 6477 { 6478 struct drm_display_info *info = &connector->display_info; 6479 const struct displayid_block *block; 6480 struct displayid_iter iter; 6481 6482 displayid_iter_edid_begin(drm_edid, &iter); 6483 displayid_iter_for_each(block, &iter) { 6484 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6485 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6486 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6487 info->non_desktop = true; 6488 6489 /* 6490 * We're only interested in the base section here, no need to 6491 * iterate further. 6492 */ 6493 break; 6494 } 6495 displayid_iter_end(&iter); 6496 } 6497 6498 static void update_display_info(struct drm_connector *connector, 6499 const struct drm_edid *drm_edid) 6500 { 6501 struct drm_display_info *info = &connector->display_info; 6502 const struct edid *edid; 6503 6504 drm_reset_display_info(connector); 6505 clear_eld(connector); 6506 6507 if (!drm_edid) 6508 return; 6509 6510 edid = drm_edid->edid; 6511 6512 info->quirks = edid_get_quirks(drm_edid); 6513 6514 info->width_mm = edid->width_cm * 10; 6515 info->height_mm = edid->height_cm * 10; 6516 6517 drm_get_monitor_range(connector, drm_edid); 6518 6519 if (edid->revision < 3) 6520 goto out; 6521 6522 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6523 goto out; 6524 6525 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6526 drm_parse_cea_ext(connector, drm_edid); 6527 6528 update_displayid_info(connector, drm_edid); 6529 6530 /* 6531 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6532 * 6533 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6534 * tells us to assume 8 bpc color depth if the EDID doesn't have 6535 * extensions which tell otherwise. 6536 */ 6537 if (info->bpc == 0 && edid->revision == 3 && 6538 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6539 info->bpc = 8; 6540 drm_dbg_kms(connector->dev, 6541 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6542 connector->base.id, connector->name, info->bpc); 6543 } 6544 6545 /* Only defined for 1.4 with digital displays */ 6546 if (edid->revision < 4) 6547 goto out; 6548 6549 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6550 case DRM_EDID_DIGITAL_DEPTH_6: 6551 info->bpc = 6; 6552 break; 6553 case DRM_EDID_DIGITAL_DEPTH_8: 6554 info->bpc = 8; 6555 break; 6556 case DRM_EDID_DIGITAL_DEPTH_10: 6557 info->bpc = 10; 6558 break; 6559 case DRM_EDID_DIGITAL_DEPTH_12: 6560 info->bpc = 12; 6561 break; 6562 case DRM_EDID_DIGITAL_DEPTH_14: 6563 info->bpc = 14; 6564 break; 6565 case DRM_EDID_DIGITAL_DEPTH_16: 6566 info->bpc = 16; 6567 break; 6568 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6569 default: 6570 info->bpc = 0; 6571 break; 6572 } 6573 6574 drm_dbg_kms(connector->dev, 6575 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6576 connector->base.id, connector->name, info->bpc); 6577 6578 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6579 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6580 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6581 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6582 6583 drm_update_mso(connector, drm_edid); 6584 6585 out: 6586 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6587 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6588 connector->base.id, connector->name, 6589 info->non_desktop ? " (redundant quirk)" : ""); 6590 info->non_desktop = true; 6591 } 6592 6593 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6594 info->max_dsc_bpp = 15; 6595 6596 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6597 info->bpc = 6; 6598 6599 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6600 info->bpc = 8; 6601 6602 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6603 info->bpc = 10; 6604 6605 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6606 info->bpc = 12; 6607 6608 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6609 drm_edid_to_eld(connector, drm_edid); 6610 } 6611 6612 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6613 struct displayid_detailed_timings_1 *timings, 6614 bool type_7) 6615 { 6616 struct drm_display_mode *mode; 6617 unsigned pixel_clock = (timings->pixel_clock[0] | 6618 (timings->pixel_clock[1] << 8) | 6619 (timings->pixel_clock[2] << 16)) + 1; 6620 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6621 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6622 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6623 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6624 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6625 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6626 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6627 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6628 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6629 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6630 6631 mode = drm_mode_create(dev); 6632 if (!mode) 6633 return NULL; 6634 6635 /* resolution is kHz for type VII, and 10 kHz for type I */ 6636 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6637 mode->hdisplay = hactive; 6638 mode->hsync_start = mode->hdisplay + hsync; 6639 mode->hsync_end = mode->hsync_start + hsync_width; 6640 mode->htotal = mode->hdisplay + hblank; 6641 6642 mode->vdisplay = vactive; 6643 mode->vsync_start = mode->vdisplay + vsync; 6644 mode->vsync_end = mode->vsync_start + vsync_width; 6645 mode->vtotal = mode->vdisplay + vblank; 6646 6647 mode->flags = 0; 6648 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6649 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6650 mode->type = DRM_MODE_TYPE_DRIVER; 6651 6652 if (timings->flags & 0x80) 6653 mode->type |= DRM_MODE_TYPE_PREFERRED; 6654 drm_mode_set_name(mode); 6655 6656 return mode; 6657 } 6658 6659 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6660 const struct displayid_block *block) 6661 { 6662 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6663 int i; 6664 int num_timings; 6665 struct drm_display_mode *newmode; 6666 int num_modes = 0; 6667 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6668 /* blocks must be multiple of 20 bytes length */ 6669 if (block->num_bytes % 20) 6670 return 0; 6671 6672 num_timings = block->num_bytes / 20; 6673 for (i = 0; i < num_timings; i++) { 6674 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6675 6676 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6677 if (!newmode) 6678 continue; 6679 6680 drm_mode_probed_add(connector, newmode); 6681 num_modes++; 6682 } 6683 return num_modes; 6684 } 6685 6686 static int add_displayid_detailed_modes(struct drm_connector *connector, 6687 const struct drm_edid *drm_edid) 6688 { 6689 const struct displayid_block *block; 6690 struct displayid_iter iter; 6691 int num_modes = 0; 6692 6693 displayid_iter_edid_begin(drm_edid, &iter); 6694 displayid_iter_for_each(block, &iter) { 6695 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6696 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6697 num_modes += add_displayid_detailed_1_modes(connector, block); 6698 } 6699 displayid_iter_end(&iter); 6700 6701 return num_modes; 6702 } 6703 6704 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6705 const struct drm_edid *drm_edid) 6706 { 6707 const struct drm_display_info *info = &connector->display_info; 6708 int num_modes = 0; 6709 6710 if (!drm_edid) 6711 return 0; 6712 6713 /* 6714 * EDID spec says modes should be preferred in this order: 6715 * - preferred detailed mode 6716 * - other detailed modes from base block 6717 * - detailed modes from extension blocks 6718 * - CVT 3-byte code modes 6719 * - standard timing codes 6720 * - established timing codes 6721 * - modes inferred from GTF or CVT range information 6722 * 6723 * We get this pretty much right. 6724 * 6725 * XXX order for additional mode types in extension blocks? 6726 */ 6727 num_modes += add_detailed_modes(connector, drm_edid); 6728 num_modes += add_cvt_modes(connector, drm_edid); 6729 num_modes += add_standard_modes(connector, drm_edid); 6730 num_modes += add_established_modes(connector, drm_edid); 6731 num_modes += add_cea_modes(connector, drm_edid); 6732 num_modes += add_alternate_cea_modes(connector, drm_edid); 6733 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6734 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6735 num_modes += add_inferred_modes(connector, drm_edid); 6736 6737 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6738 edid_fixup_preferred(connector); 6739 6740 return num_modes; 6741 } 6742 6743 static void _drm_update_tile_info(struct drm_connector *connector, 6744 const struct drm_edid *drm_edid); 6745 6746 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6747 const struct drm_edid *drm_edid) 6748 { 6749 struct drm_device *dev = connector->dev; 6750 int ret; 6751 6752 if (connector->edid_blob_ptr) { 6753 const struct edid *old_edid = connector->edid_blob_ptr->data; 6754 6755 if (old_edid) { 6756 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6757 connector->epoch_counter++; 6758 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6759 connector->base.id, connector->name, 6760 connector->epoch_counter); 6761 } 6762 } 6763 } 6764 6765 ret = drm_property_replace_global_blob(dev, 6766 &connector->edid_blob_ptr, 6767 drm_edid ? drm_edid->size : 0, 6768 drm_edid ? drm_edid->edid : NULL, 6769 &connector->base, 6770 dev->mode_config.edid_property); 6771 if (ret) { 6772 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6773 connector->base.id, connector->name, ret); 6774 goto out; 6775 } 6776 6777 ret = drm_object_property_set_value(&connector->base, 6778 dev->mode_config.non_desktop_property, 6779 connector->display_info.non_desktop); 6780 if (ret) { 6781 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6782 connector->base.id, connector->name, ret); 6783 goto out; 6784 } 6785 6786 ret = drm_connector_set_tile_property(connector); 6787 if (ret) { 6788 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6789 connector->base.id, connector->name, ret); 6790 goto out; 6791 } 6792 6793 out: 6794 return ret; 6795 } 6796 6797 /** 6798 * drm_edid_connector_update - Update connector information from EDID 6799 * @connector: Connector 6800 * @drm_edid: EDID 6801 * 6802 * Update the connector display info, ELD, HDR metadata, relevant properties, 6803 * etc. from the passed in EDID. 6804 * 6805 * If EDID is NULL, reset the information. 6806 * 6807 * Must be called before calling drm_edid_connector_add_modes(). 6808 * 6809 * Return: 0 on success, negative error on errors. 6810 */ 6811 int drm_edid_connector_update(struct drm_connector *connector, 6812 const struct drm_edid *drm_edid) 6813 { 6814 update_display_info(connector, drm_edid); 6815 6816 _drm_update_tile_info(connector, drm_edid); 6817 6818 return _drm_edid_connector_property_update(connector, drm_edid); 6819 } 6820 EXPORT_SYMBOL(drm_edid_connector_update); 6821 6822 /** 6823 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6824 * @connector: Connector 6825 * 6826 * Add the modes from the previously updated EDID property to the connector 6827 * probed modes list. 6828 * 6829 * drm_edid_connector_update() must have been called before this to update the 6830 * EDID property. 6831 * 6832 * Return: The number of modes added, or 0 if we couldn't find any. 6833 */ 6834 int drm_edid_connector_add_modes(struct drm_connector *connector) 6835 { 6836 const struct drm_edid *drm_edid = NULL; 6837 int count; 6838 6839 if (connector->edid_blob_ptr) 6840 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6841 connector->edid_blob_ptr->length); 6842 6843 count = _drm_edid_connector_add_modes(connector, drm_edid); 6844 6845 drm_edid_free(drm_edid); 6846 6847 return count; 6848 } 6849 EXPORT_SYMBOL(drm_edid_connector_add_modes); 6850 6851 /** 6852 * drm_connector_update_edid_property - update the edid property of a connector 6853 * @connector: drm connector 6854 * @edid: new value of the edid property 6855 * 6856 * This function creates a new blob modeset object and assigns its id to the 6857 * connector's edid property. 6858 * Since we also parse tile information from EDID's displayID block, we also 6859 * set the connector's tile property here. See drm_connector_set_tile_property() 6860 * for more details. 6861 * 6862 * This function is deprecated. Use drm_edid_connector_update() instead. 6863 * 6864 * Returns: 6865 * Zero on success, negative errno on failure. 6866 */ 6867 int drm_connector_update_edid_property(struct drm_connector *connector, 6868 const struct edid *edid) 6869 { 6870 struct drm_edid drm_edid; 6871 6872 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6873 } 6874 EXPORT_SYMBOL(drm_connector_update_edid_property); 6875 6876 /** 6877 * drm_add_edid_modes - add modes from EDID data, if available 6878 * @connector: connector we're probing 6879 * @edid: EDID data 6880 * 6881 * Add the specified modes to the connector's mode list. Also fills out the 6882 * &drm_display_info structure and ELD in @connector with any information which 6883 * can be derived from the edid. 6884 * 6885 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6886 * 6887 * Return: The number of modes added or 0 if we couldn't find any. 6888 */ 6889 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6890 { 6891 struct drm_edid _drm_edid; 6892 const struct drm_edid *drm_edid; 6893 6894 if (edid && !drm_edid_is_valid(edid)) { 6895 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6896 connector->base.id, connector->name); 6897 edid = NULL; 6898 } 6899 6900 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6901 6902 update_display_info(connector, drm_edid); 6903 6904 return _drm_edid_connector_add_modes(connector, drm_edid); 6905 } 6906 EXPORT_SYMBOL(drm_add_edid_modes); 6907 6908 /** 6909 * drm_add_modes_noedid - add modes for the connectors without EDID 6910 * @connector: connector we're probing 6911 * @hdisplay: the horizontal display limit 6912 * @vdisplay: the vertical display limit 6913 * 6914 * Add the specified modes to the connector's mode list. Only when the 6915 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6916 * 6917 * Return: The number of modes added or 0 if we couldn't find any. 6918 */ 6919 int drm_add_modes_noedid(struct drm_connector *connector, 6920 int hdisplay, int vdisplay) 6921 { 6922 int i, count, num_modes = 0; 6923 struct drm_display_mode *mode; 6924 struct drm_device *dev = connector->dev; 6925 6926 count = ARRAY_SIZE(drm_dmt_modes); 6927 if (hdisplay < 0) 6928 hdisplay = 0; 6929 if (vdisplay < 0) 6930 vdisplay = 0; 6931 6932 for (i = 0; i < count; i++) { 6933 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6934 6935 if (hdisplay && vdisplay) { 6936 /* 6937 * Only when two are valid, they will be used to check 6938 * whether the mode should be added to the mode list of 6939 * the connector. 6940 */ 6941 if (ptr->hdisplay > hdisplay || 6942 ptr->vdisplay > vdisplay) 6943 continue; 6944 } 6945 if (drm_mode_vrefresh(ptr) > 61) 6946 continue; 6947 mode = drm_mode_duplicate(dev, ptr); 6948 if (mode) { 6949 drm_mode_probed_add(connector, mode); 6950 num_modes++; 6951 } 6952 } 6953 return num_modes; 6954 } 6955 EXPORT_SYMBOL(drm_add_modes_noedid); 6956 6957 /** 6958 * drm_set_preferred_mode - Sets the preferred mode of a connector 6959 * @connector: connector whose mode list should be processed 6960 * @hpref: horizontal resolution of preferred mode 6961 * @vpref: vertical resolution of preferred mode 6962 * 6963 * Marks a mode as preferred if it matches the resolution specified by @hpref 6964 * and @vpref. 6965 */ 6966 void drm_set_preferred_mode(struct drm_connector *connector, 6967 int hpref, int vpref) 6968 { 6969 struct drm_display_mode *mode; 6970 6971 list_for_each_entry(mode, &connector->probed_modes, head) { 6972 if (mode->hdisplay == hpref && 6973 mode->vdisplay == vpref) 6974 mode->type |= DRM_MODE_TYPE_PREFERRED; 6975 } 6976 } 6977 EXPORT_SYMBOL(drm_set_preferred_mode); 6978 6979 static bool is_hdmi2_sink(const struct drm_connector *connector) 6980 { 6981 /* 6982 * FIXME: sil-sii8620 doesn't have a connector around when 6983 * we need one, so we have to be prepared for a NULL connector. 6984 */ 6985 if (!connector) 6986 return true; 6987 6988 return connector->display_info.hdmi.scdc.supported || 6989 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6990 } 6991 6992 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6993 const struct drm_display_mode *mode) 6994 { 6995 bool has_hdmi_infoframe = connector ? 6996 connector->display_info.has_hdmi_infoframe : false; 6997 6998 if (!has_hdmi_infoframe) 6999 return 0; 7000 7001 /* No HDMI VIC when signalling 3D video format */ 7002 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7003 return 0; 7004 7005 return drm_match_hdmi_mode(mode); 7006 } 7007 7008 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7009 const struct drm_display_mode *mode) 7010 { 7011 /* 7012 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7013 * we should send its VIC in vendor infoframes, else send the 7014 * VIC in AVI infoframes. Lets check if this mode is present in 7015 * HDMI 1.4b 4K modes 7016 */ 7017 if (drm_mode_hdmi_vic(connector, mode)) 7018 return 0; 7019 7020 return drm_match_cea_mode(mode); 7021 } 7022 7023 /* 7024 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7025 * conform to HDMI 1.4. 7026 * 7027 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7028 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7029 * 7030 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7031 * version. 7032 */ 7033 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7034 { 7035 if (!is_hdmi2_sink(connector) && vic > 64 && 7036 !cta_vdb_has_vic(connector, vic)) 7037 return 0; 7038 7039 return vic; 7040 } 7041 7042 /** 7043 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7044 * data from a DRM display mode 7045 * @frame: HDMI AVI infoframe 7046 * @connector: the connector 7047 * @mode: DRM display mode 7048 * 7049 * Return: 0 on success or a negative error code on failure. 7050 */ 7051 int 7052 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7053 const struct drm_connector *connector, 7054 const struct drm_display_mode *mode) 7055 { 7056 enum hdmi_picture_aspect picture_aspect; 7057 u8 vic, hdmi_vic; 7058 7059 if (!frame || !mode) 7060 return -EINVAL; 7061 7062 hdmi_avi_infoframe_init(frame); 7063 7064 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7065 frame->pixel_repeat = 1; 7066 7067 vic = drm_mode_cea_vic(connector, mode); 7068 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7069 7070 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7071 7072 /* 7073 * As some drivers don't support atomic, we can't use connector state. 7074 * So just initialize the frame with default values, just the same way 7075 * as it's done with other properties here. 7076 */ 7077 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7078 frame->itc = 0; 7079 7080 /* 7081 * Populate picture aspect ratio from either 7082 * user input (if specified) or from the CEA/HDMI mode lists. 7083 */ 7084 picture_aspect = mode->picture_aspect_ratio; 7085 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7086 if (vic) 7087 picture_aspect = drm_get_cea_aspect_ratio(vic); 7088 else if (hdmi_vic) 7089 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7090 } 7091 7092 /* 7093 * The infoframe can't convey anything but none, 4:3 7094 * and 16:9, so if the user has asked for anything else 7095 * we can only satisfy it by specifying the right VIC. 7096 */ 7097 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7098 if (vic) { 7099 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7100 return -EINVAL; 7101 } else if (hdmi_vic) { 7102 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7103 return -EINVAL; 7104 } else { 7105 return -EINVAL; 7106 } 7107 7108 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7109 } 7110 7111 frame->video_code = vic_for_avi_infoframe(connector, vic); 7112 frame->picture_aspect = picture_aspect; 7113 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7114 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7115 7116 return 0; 7117 } 7118 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7119 7120 /** 7121 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7122 * quantization range information 7123 * @frame: HDMI AVI infoframe 7124 * @connector: the connector 7125 * @mode: DRM display mode 7126 * @rgb_quant_range: RGB quantization range (Q) 7127 */ 7128 void 7129 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7130 const struct drm_connector *connector, 7131 const struct drm_display_mode *mode, 7132 enum hdmi_quantization_range rgb_quant_range) 7133 { 7134 const struct drm_display_info *info = &connector->display_info; 7135 7136 /* 7137 * CEA-861: 7138 * "A Source shall not send a non-zero Q value that does not correspond 7139 * to the default RGB Quantization Range for the transmitted Picture 7140 * unless the Sink indicates support for the Q bit in a Video 7141 * Capabilities Data Block." 7142 * 7143 * HDMI 2.0 recommends sending non-zero Q when it does match the 7144 * default RGB quantization range for the mode, even when QS=0. 7145 */ 7146 if (info->rgb_quant_range_selectable || 7147 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7148 frame->quantization_range = rgb_quant_range; 7149 else 7150 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7151 7152 /* 7153 * CEA-861-F: 7154 * "When transmitting any RGB colorimetry, the Source should set the 7155 * YQ-field to match the RGB Quantization Range being transmitted 7156 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7157 * set YQ=1) and the Sink shall ignore the YQ-field." 7158 * 7159 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7160 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7161 * good way to tell which version of CEA-861 the sink supports, so 7162 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7163 * on CEA-861-F. 7164 */ 7165 if (!is_hdmi2_sink(connector) || 7166 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7167 frame->ycc_quantization_range = 7168 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7169 else 7170 frame->ycc_quantization_range = 7171 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7172 } 7173 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7174 7175 static enum hdmi_3d_structure 7176 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7177 { 7178 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7179 7180 switch (layout) { 7181 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7182 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7183 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7184 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7185 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7186 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7187 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7188 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7189 case DRM_MODE_FLAG_3D_L_DEPTH: 7190 return HDMI_3D_STRUCTURE_L_DEPTH; 7191 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7192 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7193 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7194 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7195 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7196 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7197 default: 7198 return HDMI_3D_STRUCTURE_INVALID; 7199 } 7200 } 7201 7202 /** 7203 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7204 * data from a DRM display mode 7205 * @frame: HDMI vendor infoframe 7206 * @connector: the connector 7207 * @mode: DRM display mode 7208 * 7209 * Note that there's is a need to send HDMI vendor infoframes only when using a 7210 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7211 * function will return -EINVAL, error that can be safely ignored. 7212 * 7213 * Return: 0 on success or a negative error code on failure. 7214 */ 7215 int 7216 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7217 const struct drm_connector *connector, 7218 const struct drm_display_mode *mode) 7219 { 7220 /* 7221 * FIXME: sil-sii8620 doesn't have a connector around when 7222 * we need one, so we have to be prepared for a NULL connector. 7223 */ 7224 bool has_hdmi_infoframe = connector ? 7225 connector->display_info.has_hdmi_infoframe : false; 7226 int err; 7227 7228 if (!frame || !mode) 7229 return -EINVAL; 7230 7231 if (!has_hdmi_infoframe) 7232 return -EINVAL; 7233 7234 err = hdmi_vendor_infoframe_init(frame); 7235 if (err < 0) 7236 return err; 7237 7238 /* 7239 * Even if it's not absolutely necessary to send the infoframe 7240 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7241 * know that the sink can handle it. This is based on a 7242 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7243 * have trouble realizing that they should switch from 3D to 2D 7244 * mode if the source simply stops sending the infoframe when 7245 * it wants to switch from 3D to 2D. 7246 */ 7247 frame->vic = drm_mode_hdmi_vic(connector, mode); 7248 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7249 7250 return 0; 7251 } 7252 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7253 7254 static void drm_parse_tiled_block(struct drm_connector *connector, 7255 const struct displayid_block *block) 7256 { 7257 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7258 u16 w, h; 7259 u8 tile_v_loc, tile_h_loc; 7260 u8 num_v_tile, num_h_tile; 7261 struct drm_tile_group *tg; 7262 7263 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7264 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7265 7266 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7267 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7268 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7269 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7270 7271 connector->has_tile = true; 7272 if (tile->tile_cap & 0x80) 7273 connector->tile_is_single_monitor = true; 7274 7275 connector->num_h_tile = num_h_tile + 1; 7276 connector->num_v_tile = num_v_tile + 1; 7277 connector->tile_h_loc = tile_h_loc; 7278 connector->tile_v_loc = tile_v_loc; 7279 connector->tile_h_size = w + 1; 7280 connector->tile_v_size = h + 1; 7281 7282 drm_dbg_kms(connector->dev, 7283 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7284 connector->base.id, connector->name, 7285 tile->tile_cap, 7286 connector->tile_h_size, connector->tile_v_size, 7287 connector->num_h_tile, connector->num_v_tile, 7288 connector->tile_h_loc, connector->tile_v_loc, 7289 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7290 7291 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7292 if (!tg) 7293 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7294 if (!tg) 7295 return; 7296 7297 if (connector->tile_group != tg) { 7298 /* if we haven't got a pointer, 7299 take the reference, drop ref to old tile group */ 7300 if (connector->tile_group) 7301 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7302 connector->tile_group = tg; 7303 } else { 7304 /* if same tile group, then release the ref we just took. */ 7305 drm_mode_put_tile_group(connector->dev, tg); 7306 } 7307 } 7308 7309 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7310 const struct displayid_block *block) 7311 { 7312 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7313 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7314 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7315 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7316 } 7317 7318 static void _drm_update_tile_info(struct drm_connector *connector, 7319 const struct drm_edid *drm_edid) 7320 { 7321 const struct displayid_block *block; 7322 struct displayid_iter iter; 7323 7324 connector->has_tile = false; 7325 7326 displayid_iter_edid_begin(drm_edid, &iter); 7327 displayid_iter_for_each(block, &iter) { 7328 if (displayid_is_tiled_block(&iter, block)) 7329 drm_parse_tiled_block(connector, block); 7330 } 7331 displayid_iter_end(&iter); 7332 7333 if (!connector->has_tile && connector->tile_group) { 7334 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7335 connector->tile_group = NULL; 7336 } 7337 } 7338