1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 #include <drm/drm_scdc_helper.h> 46 47 #include "drm_crtc_internal.h" 48 49 #define version_greater(edid, maj, min) \ 50 (((edid)->version > (maj)) || \ 51 ((edid)->version == (maj) && (edid)->revision > (min))) 52 53 static int oui(u8 first, u8 second, u8 third) 54 { 55 return (first << 16) | (second << 8) | third; 56 } 57 58 #define EDID_EST_TIMINGS 16 59 #define EDID_STD_TIMINGS 8 60 #define EDID_DETAILED_TIMINGS 4 61 62 /* 63 * EDID blocks out in the wild have a variety of bugs, try to collect 64 * them here (note that userspace may work around broken monitors first, 65 * but fixes should make their way here so that the kernel "just works" 66 * on as many displays as possible). 67 */ 68 69 /* First detailed mode wrong, use largest 60Hz mode */ 70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 71 /* Reported 135MHz pixel clock is too high, needs adjustment */ 72 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 73 /* Prefer the largest mode at 75 Hz */ 74 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 75 /* Detail timing is in cm not mm */ 76 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 77 /* Detailed timing descriptors have bogus size values, so just take the 78 * maximum size and use that. 79 */ 80 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 81 /* use +hsync +vsync for detailed mode */ 82 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 83 /* Force reduced-blanking timings for detailed modes */ 84 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 85 /* Force 8bpc */ 86 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 87 /* Force 12bpc */ 88 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 89 /* Force 6bpc */ 90 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 91 /* Force 10bpc */ 92 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 93 /* Non desktop display (i.e. HMD) */ 94 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 95 96 #define MICROSOFT_IEEE_OUI 0xca125c 97 98 struct detailed_mode_closure { 99 struct drm_connector *connector; 100 const struct edid *edid; 101 bool preferred; 102 u32 quirks; 103 int modes; 104 }; 105 106 #define LEVEL_DMT 0 107 #define LEVEL_GTF 1 108 #define LEVEL_GTF2 2 109 #define LEVEL_CVT 3 110 111 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 112 { \ 113 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 114 product_id), \ 115 .quirks = _quirks \ 116 } 117 118 static const struct edid_quirk { 119 u32 panel_id; 120 u32 quirks; 121 } edid_quirk_list[] = { 122 /* Acer AL1706 */ 123 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 124 /* Acer F51 */ 125 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 126 127 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 128 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 129 130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 132 133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 135 136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 138 139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 141 142 /* Belinea 10 15 55 */ 143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 145 146 /* Envision Peripherals, Inc. EN-7100e */ 147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 148 /* Envision EN2028 */ 149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 150 151 /* Funai Electronics PM36B */ 152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 153 EDID_QUIRK_DETAILED_IN_CM), 154 155 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 156 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 157 158 /* LG Philips LCD LP154W01-A5 */ 159 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 160 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 161 162 /* Samsung SyncMaster 205BW. Note: irony */ 163 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 164 /* Samsung SyncMaster 22[5-6]BW */ 165 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 166 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 167 168 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 169 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 170 171 /* ViewSonic VA2026w */ 172 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 173 174 /* Medion MD 30217 PG */ 175 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 176 177 /* Lenovo G50 */ 178 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 179 180 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 181 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 182 183 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 184 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 185 186 /* Valve Index Headset */ 187 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 188 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 189 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 204 205 /* HTC Vive and Vive Pro VR Headsets */ 206 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 208 209 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 210 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 211 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 214 215 /* Windows Mixed Reality Headsets */ 216 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 222 223 /* Sony PlayStation VR Headset */ 224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 225 226 /* Sensics VR Headsets */ 227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 228 229 /* OSVR HDK and HDK2 VR Headsets */ 230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 231 }; 232 233 /* 234 * Autogenerated from the DMT spec. 235 * This table is copied from xfree86/modes/xf86EdidModes.c. 236 */ 237 static const struct drm_display_mode drm_dmt_modes[] = { 238 /* 0x01 - 640x350@85Hz */ 239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 240 736, 832, 0, 350, 382, 385, 445, 0, 241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 242 /* 0x02 - 640x400@85Hz */ 243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 244 736, 832, 0, 400, 401, 404, 445, 0, 245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 246 /* 0x03 - 720x400@85Hz */ 247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 248 828, 936, 0, 400, 401, 404, 446, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 250 /* 0x04 - 640x480@60Hz */ 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 252 752, 800, 0, 480, 490, 492, 525, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 254 /* 0x05 - 640x480@72Hz */ 255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 256 704, 832, 0, 480, 489, 492, 520, 0, 257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 258 /* 0x06 - 640x480@75Hz */ 259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 260 720, 840, 0, 480, 481, 484, 500, 0, 261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 262 /* 0x07 - 640x480@85Hz */ 263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 264 752, 832, 0, 480, 481, 484, 509, 0, 265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 266 /* 0x08 - 800x600@56Hz */ 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 268 896, 1024, 0, 600, 601, 603, 625, 0, 269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 270 /* 0x09 - 800x600@60Hz */ 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 272 968, 1056, 0, 600, 601, 605, 628, 0, 273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x0a - 800x600@72Hz */ 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 276 976, 1040, 0, 600, 637, 643, 666, 0, 277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 278 /* 0x0b - 800x600@75Hz */ 279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 280 896, 1056, 0, 600, 601, 604, 625, 0, 281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x0c - 800x600@85Hz */ 283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 284 896, 1048, 0, 600, 601, 604, 631, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 286 /* 0x0d - 800x600@120Hz RB */ 287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 288 880, 960, 0, 600, 603, 607, 636, 0, 289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x0e - 848x480@60Hz */ 291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 292 976, 1088, 0, 480, 486, 494, 517, 0, 293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x0f - 1024x768@43Hz, interlace */ 295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 296 1208, 1264, 0, 768, 768, 776, 817, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 298 DRM_MODE_FLAG_INTERLACE) }, 299 /* 0x10 - 1024x768@60Hz */ 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 301 1184, 1344, 0, 768, 771, 777, 806, 0, 302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 303 /* 0x11 - 1024x768@70Hz */ 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 305 1184, 1328, 0, 768, 771, 777, 806, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 307 /* 0x12 - 1024x768@75Hz */ 308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 309 1136, 1312, 0, 768, 769, 772, 800, 0, 310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 0x13 - 1024x768@85Hz */ 312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 313 1168, 1376, 0, 768, 769, 772, 808, 0, 314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 0x14 - 1024x768@120Hz RB */ 316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 317 1104, 1184, 0, 768, 771, 775, 813, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 319 /* 0x15 - 1152x864@75Hz */ 320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 321 1344, 1600, 0, 864, 865, 868, 900, 0, 322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 323 /* 0x55 - 1280x720@60Hz */ 324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 325 1430, 1650, 0, 720, 725, 730, 750, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 0x16 - 1280x768@60Hz RB */ 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 329 1360, 1440, 0, 768, 771, 778, 790, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 331 /* 0x17 - 1280x768@60Hz */ 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 333 1472, 1664, 0, 768, 771, 778, 798, 0, 334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 335 /* 0x18 - 1280x768@75Hz */ 336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 337 1488, 1696, 0, 768, 771, 778, 805, 0, 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 339 /* 0x19 - 1280x768@85Hz */ 340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 341 1496, 1712, 0, 768, 771, 778, 809, 0, 342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 0x1a - 1280x768@120Hz RB */ 344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 345 1360, 1440, 0, 768, 771, 778, 813, 0, 346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 347 /* 0x1b - 1280x800@60Hz RB */ 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 349 1360, 1440, 0, 800, 803, 809, 823, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 351 /* 0x1c - 1280x800@60Hz */ 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 353 1480, 1680, 0, 800, 803, 809, 831, 0, 354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 355 /* 0x1d - 1280x800@75Hz */ 356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 357 1488, 1696, 0, 800, 803, 809, 838, 0, 358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 0x1e - 1280x800@85Hz */ 360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 361 1496, 1712, 0, 800, 803, 809, 843, 0, 362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 363 /* 0x1f - 1280x800@120Hz RB */ 364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 365 1360, 1440, 0, 800, 803, 809, 847, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 367 /* 0x20 - 1280x960@60Hz */ 368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 369 1488, 1800, 0, 960, 961, 964, 1000, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 0x21 - 1280x960@85Hz */ 372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 373 1504, 1728, 0, 960, 961, 964, 1011, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 0x22 - 1280x960@120Hz RB */ 376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 377 1360, 1440, 0, 960, 963, 967, 1017, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 379 /* 0x23 - 1280x1024@60Hz */ 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 383 /* 0x24 - 1280x1024@75Hz */ 384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 0x25 - 1280x1024@85Hz */ 388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 391 /* 0x26 - 1280x1024@120Hz RB */ 392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 395 /* 0x27 - 1360x768@60Hz */ 396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 397 1536, 1792, 0, 768, 771, 777, 795, 0, 398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 0x28 - 1360x768@120Hz RB */ 400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 401 1440, 1520, 0, 768, 771, 776, 813, 0, 402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 403 /* 0x51 - 1366x768@60Hz */ 404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 405 1579, 1792, 0, 768, 771, 774, 798, 0, 406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 407 /* 0x56 - 1366x768@60Hz */ 408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 409 1436, 1500, 0, 768, 769, 772, 800, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 411 /* 0x29 - 1400x1050@60Hz RB */ 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 415 /* 0x2a - 1400x1050@60Hz */ 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 419 /* 0x2b - 1400x1050@75Hz */ 420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 423 /* 0x2c - 1400x1050@85Hz */ 424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 427 /* 0x2d - 1400x1050@120Hz RB */ 428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 431 /* 0x2e - 1440x900@60Hz RB */ 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 433 1520, 1600, 0, 900, 903, 909, 926, 0, 434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 435 /* 0x2f - 1440x900@60Hz */ 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 437 1672, 1904, 0, 900, 903, 909, 934, 0, 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 439 /* 0x30 - 1440x900@75Hz */ 440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 441 1688, 1936, 0, 900, 903, 909, 942, 0, 442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 443 /* 0x31 - 1440x900@85Hz */ 444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 445 1696, 1952, 0, 900, 903, 909, 948, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 0x32 - 1440x900@120Hz RB */ 448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 449 1520, 1600, 0, 900, 903, 909, 953, 0, 450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 451 /* 0x53 - 1600x900@60Hz */ 452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 453 1704, 1800, 0, 900, 901, 904, 1000, 0, 454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 0x33 - 1600x1200@60Hz */ 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 0x34 - 1600x1200@65Hz */ 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 463 /* 0x35 - 1600x1200@70Hz */ 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 467 /* 0x36 - 1600x1200@75Hz */ 468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 471 /* 0x37 - 1600x1200@85Hz */ 472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 475 /* 0x38 - 1600x1200@120Hz RB */ 476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 479 /* 0x39 - 1680x1050@60Hz RB */ 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 483 /* 0x3a - 1680x1050@60Hz */ 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 487 /* 0x3b - 1680x1050@75Hz */ 488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 491 /* 0x3c - 1680x1050@85Hz */ 492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 495 /* 0x3d - 1680x1050@120Hz RB */ 496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 499 /* 0x3e - 1792x1344@60Hz */ 500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 503 /* 0x3f - 1792x1344@75Hz */ 504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 507 /* 0x40 - 1792x1344@120Hz RB */ 508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 511 /* 0x41 - 1856x1392@60Hz */ 512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 515 /* 0x42 - 1856x1392@75Hz */ 516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 519 /* 0x43 - 1856x1392@120Hz RB */ 520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 523 /* 0x52 - 1920x1080@60Hz */ 524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 527 /* 0x44 - 1920x1200@60Hz RB */ 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 531 /* 0x45 - 1920x1200@60Hz */ 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 535 /* 0x46 - 1920x1200@75Hz */ 536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 539 /* 0x47 - 1920x1200@85Hz */ 540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 543 /* 0x48 - 1920x1200@120Hz RB */ 544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 547 /* 0x49 - 1920x1440@60Hz */ 548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 551 /* 0x4a - 1920x1440@75Hz */ 552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 555 /* 0x4b - 1920x1440@120Hz RB */ 556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 559 /* 0x54 - 2048x1152@60Hz */ 560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 563 /* 0x4c - 2560x1600@60Hz RB */ 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 567 /* 0x4d - 2560x1600@60Hz */ 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 571 /* 0x4e - 2560x1600@75Hz */ 572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 575 /* 0x4f - 2560x1600@85Hz */ 576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 579 /* 0x50 - 2560x1600@120Hz RB */ 580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 583 /* 0x57 - 4096x2160@60Hz RB */ 584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 587 /* 0x58 - 4096x2160@59.94Hz RB */ 588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 591 }; 592 593 /* 594 * These more or less come from the DMT spec. The 720x400 modes are 595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 598 * mode. 599 * 600 * The DMT modes have been fact-checked; the rest are mild guesses. 601 */ 602 static const struct drm_display_mode edid_est_modes[] = { 603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 604 968, 1056, 0, 600, 601, 605, 628, 0, 605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 607 896, 1024, 0, 600, 601, 603, 625, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 610 720, 840, 0, 480, 481, 484, 500, 0, 611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 613 704, 832, 0, 480, 489, 492, 520, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 616 768, 864, 0, 480, 483, 486, 525, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 619 752, 800, 0, 480, 490, 492, 525, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 622 846, 900, 0, 400, 421, 423, 449, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 625 846, 900, 0, 400, 412, 414, 449, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 631 1136, 1312, 0, 768, 769, 772, 800, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 634 1184, 1328, 0, 768, 771, 777, 806, 0, 635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 637 1184, 1344, 0, 768, 771, 777, 806, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 640 1208, 1264, 0, 768, 768, 776, 817, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 643 928, 1152, 0, 624, 625, 628, 667, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 646 896, 1056, 0, 600, 601, 604, 625, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 649 976, 1040, 0, 600, 637, 643, 666, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 652 1344, 1600, 0, 864, 865, 868, 900, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 654 }; 655 656 struct minimode { 657 short w; 658 short h; 659 short r; 660 short rb; 661 }; 662 663 static const struct minimode est3_modes[] = { 664 /* byte 6 */ 665 { 640, 350, 85, 0 }, 666 { 640, 400, 85, 0 }, 667 { 720, 400, 85, 0 }, 668 { 640, 480, 85, 0 }, 669 { 848, 480, 60, 0 }, 670 { 800, 600, 85, 0 }, 671 { 1024, 768, 85, 0 }, 672 { 1152, 864, 75, 0 }, 673 /* byte 7 */ 674 { 1280, 768, 60, 1 }, 675 { 1280, 768, 60, 0 }, 676 { 1280, 768, 75, 0 }, 677 { 1280, 768, 85, 0 }, 678 { 1280, 960, 60, 0 }, 679 { 1280, 960, 85, 0 }, 680 { 1280, 1024, 60, 0 }, 681 { 1280, 1024, 85, 0 }, 682 /* byte 8 */ 683 { 1360, 768, 60, 0 }, 684 { 1440, 900, 60, 1 }, 685 { 1440, 900, 60, 0 }, 686 { 1440, 900, 75, 0 }, 687 { 1440, 900, 85, 0 }, 688 { 1400, 1050, 60, 1 }, 689 { 1400, 1050, 60, 0 }, 690 { 1400, 1050, 75, 0 }, 691 /* byte 9 */ 692 { 1400, 1050, 85, 0 }, 693 { 1680, 1050, 60, 1 }, 694 { 1680, 1050, 60, 0 }, 695 { 1680, 1050, 75, 0 }, 696 { 1680, 1050, 85, 0 }, 697 { 1600, 1200, 60, 0 }, 698 { 1600, 1200, 65, 0 }, 699 { 1600, 1200, 70, 0 }, 700 /* byte 10 */ 701 { 1600, 1200, 75, 0 }, 702 { 1600, 1200, 85, 0 }, 703 { 1792, 1344, 60, 0 }, 704 { 1792, 1344, 75, 0 }, 705 { 1856, 1392, 60, 0 }, 706 { 1856, 1392, 75, 0 }, 707 { 1920, 1200, 60, 1 }, 708 { 1920, 1200, 60, 0 }, 709 /* byte 11 */ 710 { 1920, 1200, 75, 0 }, 711 { 1920, 1200, 85, 0 }, 712 { 1920, 1440, 60, 0 }, 713 { 1920, 1440, 75, 0 }, 714 }; 715 716 static const struct minimode extra_modes[] = { 717 { 1024, 576, 60, 0 }, 718 { 1366, 768, 60, 0 }, 719 { 1600, 900, 60, 0 }, 720 { 1680, 945, 60, 0 }, 721 { 1920, 1080, 60, 0 }, 722 { 2048, 1152, 60, 0 }, 723 { 2048, 1536, 60, 0 }, 724 }; 725 726 /* 727 * From CEA/CTA-861 spec. 728 * 729 * Do not access directly, instead always use cea_mode_for_vic(). 730 */ 731 static const struct drm_display_mode edid_cea_modes_1[] = { 732 /* 1 - 640x480@60Hz 4:3 */ 733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 734 752, 800, 0, 480, 490, 492, 525, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 2 - 720x480@60Hz 4:3 */ 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 739 798, 858, 0, 480, 489, 495, 525, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 742 /* 3 - 720x480@60Hz 16:9 */ 743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 744 798, 858, 0, 480, 489, 495, 525, 0, 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 4 - 1280x720@60Hz 16:9 */ 748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 749 1430, 1650, 0, 720, 725, 730, 750, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 752 /* 5 - 1920x1080i@60Hz 16:9 */ 753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 756 DRM_MODE_FLAG_INTERLACE), 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 6 - 720(1440)x480i@60Hz 4:3 */ 759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 760 801, 858, 0, 480, 488, 494, 525, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 764 /* 7 - 720(1440)x480i@60Hz 16:9 */ 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 480, 488, 494, 525, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 770 /* 8 - 720(1440)x240@60Hz 4:3 */ 771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 772 801, 858, 0, 240, 244, 247, 262, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_DBLCLK), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 776 /* 9 - 720(1440)x240@60Hz 16:9 */ 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 778 801, 858, 0, 240, 244, 247, 262, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_DBLCLK), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 782 /* 10 - 2880x480i@60Hz 4:3 */ 783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 784 3204, 3432, 0, 480, 488, 494, 525, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 786 DRM_MODE_FLAG_INTERLACE), 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 788 /* 11 - 2880x480i@60Hz 16:9 */ 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 480, 488, 494, 525, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 792 DRM_MODE_FLAG_INTERLACE), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 794 /* 12 - 2880x240@60Hz 4:3 */ 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 240, 244, 247, 262, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 799 /* 13 - 2880x240@60Hz 16:9 */ 800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 801 3204, 3432, 0, 240, 244, 247, 262, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 804 /* 14 - 1440x480@60Hz 4:3 */ 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 806 1596, 1716, 0, 480, 489, 495, 525, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 809 /* 15 - 1440x480@60Hz 16:9 */ 810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 811 1596, 1716, 0, 480, 489, 495, 525, 0, 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 16 - 1920x1080@60Hz 16:9 */ 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 819 /* 17 - 720x576@50Hz 4:3 */ 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 821 796, 864, 0, 576, 581, 586, 625, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 824 /* 18 - 720x576@50Hz 16:9 */ 825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 826 796, 864, 0, 576, 581, 586, 625, 0, 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 19 - 1280x720@50Hz 16:9 */ 830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 831 1760, 1980, 0, 720, 725, 730, 750, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 20 - 1920x1080i@50Hz 16:9 */ 835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 838 DRM_MODE_FLAG_INTERLACE), 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 21 - 720(1440)x576i@50Hz 4:3 */ 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 842 795, 864, 0, 576, 580, 586, 625, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 846 /* 22 - 720(1440)x576i@50Hz 16:9 */ 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 576, 580, 586, 625, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 852 /* 23 - 720(1440)x288@50Hz 4:3 */ 853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 854 795, 864, 0, 288, 290, 293, 312, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_DBLCLK), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 858 /* 24 - 720(1440)x288@50Hz 16:9 */ 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 860 795, 864, 0, 288, 290, 293, 312, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_DBLCLK), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 25 - 2880x576i@50Hz 4:3 */ 865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 866 3180, 3456, 0, 576, 580, 586, 625, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 868 DRM_MODE_FLAG_INTERLACE), 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 870 /* 26 - 2880x576i@50Hz 16:9 */ 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 576, 580, 586, 625, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 874 DRM_MODE_FLAG_INTERLACE), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 876 /* 27 - 2880x288@50Hz 4:3 */ 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 288, 290, 293, 312, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 881 /* 28 - 2880x288@50Hz 16:9 */ 882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 883 3180, 3456, 0, 288, 290, 293, 312, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 886 /* 29 - 1440x576@50Hz 4:3 */ 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 888 1592, 1728, 0, 576, 581, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 891 /* 30 - 1440x576@50Hz 16:9 */ 892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 893 1592, 1728, 0, 576, 581, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 896 /* 31 - 1920x1080@50Hz 16:9 */ 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 32 - 1920x1080@24Hz 16:9 */ 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 33 - 1920x1080@25Hz 16:9 */ 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 911 /* 34 - 1920x1080@30Hz 16:9 */ 912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 916 /* 35 - 2880x480@60Hz 4:3 */ 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 918 3192, 3432, 0, 480, 489, 495, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 921 /* 36 - 2880x480@60Hz 16:9 */ 922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 923 3192, 3432, 0, 480, 489, 495, 525, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 926 /* 37 - 2880x576@50Hz 4:3 */ 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 928 3184, 3456, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 931 /* 38 - 2880x576@50Hz 16:9 */ 932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 933 3184, 3456, 0, 576, 581, 586, 625, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 39 - 1920x1080i@50Hz 16:9 */ 937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 940 DRM_MODE_FLAG_INTERLACE), 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 40 - 1920x1080i@100Hz 16:9 */ 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 946 DRM_MODE_FLAG_INTERLACE), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 41 - 1280x720@100Hz 16:9 */ 949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 950 1760, 1980, 0, 720, 725, 730, 750, 0, 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 953 /* 42 - 720x576@100Hz 4:3 */ 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 955 796, 864, 0, 576, 581, 586, 625, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 958 /* 43 - 720x576@100Hz 16:9 */ 959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 960 796, 864, 0, 576, 581, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 963 /* 44 - 720(1440)x576i@100Hz 4:3 */ 964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 965 795, 864, 0, 576, 580, 586, 625, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 969 /* 45 - 720(1440)x576i@100Hz 16:9 */ 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 971 795, 864, 0, 576, 580, 586, 625, 0, 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 46 - 1920x1080i@120Hz 16:9 */ 976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 979 DRM_MODE_FLAG_INTERLACE), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 47 - 1280x720@120Hz 16:9 */ 982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 983 1430, 1650, 0, 720, 725, 730, 750, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 986 /* 48 - 720x480@120Hz 4:3 */ 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 988 798, 858, 0, 480, 489, 495, 525, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 991 /* 49 - 720x480@120Hz 16:9 */ 992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 993 798, 858, 0, 480, 489, 495, 525, 0, 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 996 /* 50 - 720(1440)x480i@120Hz 4:3 */ 997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 998 801, 858, 0, 480, 488, 494, 525, 0, 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1002 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1004 801, 858, 0, 480, 488, 494, 525, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1008 /* 52 - 720x576@200Hz 4:3 */ 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1010 796, 864, 0, 576, 581, 586, 625, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1013 /* 53 - 720x576@200Hz 16:9 */ 1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1015 796, 864, 0, 576, 581, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1018 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1020 795, 864, 0, 576, 580, 586, 625, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1024 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1026 795, 864, 0, 576, 580, 586, 625, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1030 /* 56 - 720x480@240Hz 4:3 */ 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1032 798, 858, 0, 480, 489, 495, 525, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1035 /* 57 - 720x480@240Hz 16:9 */ 1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1037 798, 858, 0, 480, 489, 495, 525, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1040 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1042 801, 858, 0, 480, 488, 494, 525, 0, 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1046 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1048 801, 858, 0, 480, 488, 494, 525, 0, 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1052 /* 60 - 1280x720@24Hz 16:9 */ 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1054 3080, 3300, 0, 720, 725, 730, 750, 0, 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1057 /* 61 - 1280x720@25Hz 16:9 */ 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1059 3740, 3960, 0, 720, 725, 730, 750, 0, 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1062 /* 62 - 1280x720@30Hz 16:9 */ 1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1064 3080, 3300, 0, 720, 725, 730, 750, 0, 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1067 /* 63 - 1920x1080@120Hz 16:9 */ 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1072 /* 64 - 1920x1080@100Hz 16:9 */ 1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1077 /* 65 - 1280x720@24Hz 64:27 */ 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1079 3080, 3300, 0, 720, 725, 730, 750, 0, 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1082 /* 66 - 1280x720@25Hz 64:27 */ 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1084 3740, 3960, 0, 720, 725, 730, 750, 0, 1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1087 /* 67 - 1280x720@30Hz 64:27 */ 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1089 3080, 3300, 0, 720, 725, 730, 750, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1092 /* 68 - 1280x720@50Hz 64:27 */ 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1094 1760, 1980, 0, 720, 725, 730, 750, 0, 1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1097 /* 69 - 1280x720@60Hz 64:27 */ 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1099 1430, 1650, 0, 720, 725, 730, 750, 0, 1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1102 /* 70 - 1280x720@100Hz 64:27 */ 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1104 1760, 1980, 0, 720, 725, 730, 750, 0, 1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1107 /* 71 - 1280x720@120Hz 64:27 */ 1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1109 1430, 1650, 0, 720, 725, 730, 750, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1112 /* 72 - 1920x1080@24Hz 64:27 */ 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1117 /* 73 - 1920x1080@25Hz 64:27 */ 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1122 /* 74 - 1920x1080@30Hz 64:27 */ 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1127 /* 75 - 1920x1080@50Hz 64:27 */ 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1132 /* 76 - 1920x1080@60Hz 64:27 */ 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1137 /* 77 - 1920x1080@100Hz 64:27 */ 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1142 /* 78 - 1920x1080@120Hz 64:27 */ 1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1147 /* 79 - 1680x720@24Hz 64:27 */ 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1149 3080, 3300, 0, 720, 725, 730, 750, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1152 /* 80 - 1680x720@25Hz 64:27 */ 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1154 2948, 3168, 0, 720, 725, 730, 750, 0, 1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1157 /* 81 - 1680x720@30Hz 64:27 */ 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1159 2420, 2640, 0, 720, 725, 730, 750, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1162 /* 82 - 1680x720@50Hz 64:27 */ 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1164 1980, 2200, 0, 720, 725, 730, 750, 0, 1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1167 /* 83 - 1680x720@60Hz 64:27 */ 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1169 1980, 2200, 0, 720, 725, 730, 750, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1172 /* 84 - 1680x720@100Hz 64:27 */ 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1174 1780, 2000, 0, 720, 725, 730, 825, 0, 1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1177 /* 85 - 1680x720@120Hz 64:27 */ 1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1179 1780, 2000, 0, 720, 725, 730, 825, 0, 1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1182 /* 86 - 2560x1080@24Hz 64:27 */ 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1187 /* 87 - 2560x1080@25Hz 64:27 */ 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1192 /* 88 - 2560x1080@30Hz 64:27 */ 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1197 /* 89 - 2560x1080@50Hz 64:27 */ 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1202 /* 90 - 2560x1080@60Hz 64:27 */ 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1207 /* 91 - 2560x1080@100Hz 64:27 */ 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1212 /* 92 - 2560x1080@120Hz 64:27 */ 1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1217 /* 93 - 3840x2160@24Hz 16:9 */ 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1222 /* 94 - 3840x2160@25Hz 16:9 */ 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1227 /* 95 - 3840x2160@30Hz 16:9 */ 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1232 /* 96 - 3840x2160@50Hz 16:9 */ 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1237 /* 97 - 3840x2160@60Hz 16:9 */ 1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1242 /* 98 - 4096x2160@24Hz 256:135 */ 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1247 /* 99 - 4096x2160@25Hz 256:135 */ 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1252 /* 100 - 4096x2160@30Hz 256:135 */ 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1257 /* 101 - 4096x2160@50Hz 256:135 */ 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1262 /* 102 - 4096x2160@60Hz 256:135 */ 1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1267 /* 103 - 3840x2160@24Hz 64:27 */ 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1272 /* 104 - 3840x2160@25Hz 64:27 */ 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1277 /* 105 - 3840x2160@30Hz 64:27 */ 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1282 /* 106 - 3840x2160@50Hz 64:27 */ 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1287 /* 107 - 3840x2160@60Hz 64:27 */ 1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1292 /* 108 - 1280x720@48Hz 16:9 */ 1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1294 2280, 2500, 0, 720, 725, 730, 750, 0, 1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1297 /* 109 - 1280x720@48Hz 64:27 */ 1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1299 2280, 2500, 0, 720, 725, 730, 750, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1302 /* 110 - 1680x720@48Hz 64:27 */ 1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1304 2530, 2750, 0, 720, 725, 730, 750, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1307 /* 111 - 1920x1080@48Hz 16:9 */ 1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1312 /* 112 - 1920x1080@48Hz 64:27 */ 1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1317 /* 113 - 2560x1080@48Hz 64:27 */ 1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1322 /* 114 - 3840x2160@48Hz 16:9 */ 1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1327 /* 115 - 4096x2160@48Hz 256:135 */ 1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1332 /* 116 - 3840x2160@48Hz 64:27 */ 1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1337 /* 117 - 3840x2160@100Hz 16:9 */ 1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1342 /* 118 - 3840x2160@120Hz 16:9 */ 1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1347 /* 119 - 3840x2160@100Hz 64:27 */ 1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1352 /* 120 - 3840x2160@120Hz 64:27 */ 1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1357 /* 121 - 5120x2160@24Hz 64:27 */ 1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1362 /* 122 - 5120x2160@25Hz 64:27 */ 1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1367 /* 123 - 5120x2160@30Hz 64:27 */ 1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1372 /* 124 - 5120x2160@48Hz 64:27 */ 1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1377 /* 125 - 5120x2160@50Hz 64:27 */ 1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1382 /* 126 - 5120x2160@60Hz 64:27 */ 1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1387 /* 127 - 5120x2160@100Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 }; 1393 1394 /* 1395 * From CEA/CTA-861 spec. 1396 * 1397 * Do not access directly, instead always use cea_mode_for_vic(). 1398 */ 1399 static const struct drm_display_mode edid_cea_modes_193[] = { 1400 /* 193 - 5120x2160@120Hz 64:27 */ 1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1405 /* 194 - 7680x4320@24Hz 16:9 */ 1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1410 /* 195 - 7680x4320@25Hz 16:9 */ 1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1415 /* 196 - 7680x4320@30Hz 16:9 */ 1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1420 /* 197 - 7680x4320@48Hz 16:9 */ 1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1425 /* 198 - 7680x4320@50Hz 16:9 */ 1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1430 /* 199 - 7680x4320@60Hz 16:9 */ 1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1435 /* 200 - 7680x4320@100Hz 16:9 */ 1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1440 /* 201 - 7680x4320@120Hz 16:9 */ 1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1445 /* 202 - 7680x4320@24Hz 64:27 */ 1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1450 /* 203 - 7680x4320@25Hz 64:27 */ 1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1455 /* 204 - 7680x4320@30Hz 64:27 */ 1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1460 /* 205 - 7680x4320@48Hz 64:27 */ 1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1465 /* 206 - 7680x4320@50Hz 64:27 */ 1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1470 /* 207 - 7680x4320@60Hz 64:27 */ 1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1475 /* 208 - 7680x4320@100Hz 64:27 */ 1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1480 /* 209 - 7680x4320@120Hz 64:27 */ 1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1485 /* 210 - 10240x4320@24Hz 64:27 */ 1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1490 /* 211 - 10240x4320@25Hz 64:27 */ 1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1495 /* 212 - 10240x4320@30Hz 64:27 */ 1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1500 /* 213 - 10240x4320@48Hz 64:27 */ 1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1505 /* 214 - 10240x4320@50Hz 64:27 */ 1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1510 /* 215 - 10240x4320@60Hz 64:27 */ 1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1515 /* 216 - 10240x4320@100Hz 64:27 */ 1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1520 /* 217 - 10240x4320@120Hz 64:27 */ 1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1525 /* 218 - 4096x2160@100Hz 256:135 */ 1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1530 /* 219 - 4096x2160@120Hz 256:135 */ 1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1535 }; 1536 1537 /* 1538 * HDMI 1.4 4k modes. Index using the VIC. 1539 */ 1540 static const struct drm_display_mode edid_4k_modes[] = { 1541 /* 0 - dummy, VICs start at 1 */ 1542 { }, 1543 /* 1 - 3840x2160@30Hz */ 1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1545 3840, 4016, 4104, 4400, 0, 1546 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1549 /* 2 - 3840x2160@25Hz */ 1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 3840, 4896, 4984, 5280, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1555 /* 3 - 3840x2160@24Hz */ 1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1557 3840, 5116, 5204, 5500, 0, 1558 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1561 /* 4 - 4096x2160@24Hz (SMPTE) */ 1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1563 4096, 5116, 5204, 5500, 0, 1564 2160, 2168, 2178, 2250, 0, 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1567 }; 1568 1569 /*** DDC fetch and block validation ***/ 1570 1571 static const u8 edid_header[] = { 1572 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1573 }; 1574 1575 /** 1576 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1577 * @raw_edid: pointer to raw base EDID block 1578 * 1579 * Sanity check the header of the base EDID block. 1580 * 1581 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1582 */ 1583 int drm_edid_header_is_valid(const u8 *raw_edid) 1584 { 1585 int i, score = 0; 1586 1587 for (i = 0; i < sizeof(edid_header); i++) 1588 if (raw_edid[i] == edid_header[i]) 1589 score++; 1590 1591 return score; 1592 } 1593 EXPORT_SYMBOL(drm_edid_header_is_valid); 1594 1595 static int edid_fixup __read_mostly = 6; 1596 module_param_named(edid_fixup, edid_fixup, int, 0400); 1597 MODULE_PARM_DESC(edid_fixup, 1598 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1599 1600 static int drm_edid_block_checksum(const u8 *raw_edid) 1601 { 1602 int i; 1603 u8 csum = 0, crc = 0; 1604 1605 for (i = 0; i < EDID_LENGTH - 1; i++) 1606 csum += raw_edid[i]; 1607 1608 crc = 0x100 - csum; 1609 1610 return crc; 1611 } 1612 1613 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1614 { 1615 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1616 return true; 1617 else 1618 return false; 1619 } 1620 1621 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1622 { 1623 if (memchr_inv(in_edid, 0, length)) 1624 return false; 1625 1626 return true; 1627 } 1628 1629 /** 1630 * drm_edid_are_equal - compare two edid blobs. 1631 * @edid1: pointer to first blob 1632 * @edid2: pointer to second blob 1633 * This helper can be used during probing to determine if 1634 * edid had changed. 1635 */ 1636 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1637 { 1638 int edid1_len, edid2_len; 1639 bool edid1_present = edid1 != NULL; 1640 bool edid2_present = edid2 != NULL; 1641 1642 if (edid1_present != edid2_present) 1643 return false; 1644 1645 if (edid1) { 1646 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1647 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1648 1649 if (edid1_len != edid2_len) 1650 return false; 1651 1652 if (memcmp(edid1, edid2, edid1_len)) 1653 return false; 1654 } 1655 1656 return true; 1657 } 1658 EXPORT_SYMBOL(drm_edid_are_equal); 1659 1660 /** 1661 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1662 * @raw_edid: pointer to raw EDID block 1663 * @block: type of block to validate (0 for base, extension otherwise) 1664 * @print_bad_edid: if true, dump bad EDID blocks to the console 1665 * @edid_corrupt: if true, the header or checksum is invalid 1666 * 1667 * Validate a base or extension EDID block and optionally dump bad blocks to 1668 * the console. 1669 * 1670 * Return: True if the block is valid, false otherwise. 1671 */ 1672 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1673 bool *edid_corrupt) 1674 { 1675 u8 csum; 1676 struct edid *edid = (struct edid *)raw_edid; 1677 1678 if (WARN_ON(!raw_edid)) 1679 return false; 1680 1681 if (edid_fixup > 8 || edid_fixup < 0) 1682 edid_fixup = 6; 1683 1684 if (block == 0) { 1685 int score = drm_edid_header_is_valid(raw_edid); 1686 1687 if (score == 8) { 1688 if (edid_corrupt) 1689 *edid_corrupt = false; 1690 } else if (score >= edid_fixup) { 1691 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1692 * The corrupt flag needs to be set here otherwise, the 1693 * fix-up code here will correct the problem, the 1694 * checksum is correct and the test fails 1695 */ 1696 if (edid_corrupt) 1697 *edid_corrupt = true; 1698 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1699 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1700 } else { 1701 if (edid_corrupt) 1702 *edid_corrupt = true; 1703 goto bad; 1704 } 1705 } 1706 1707 csum = drm_edid_block_checksum(raw_edid); 1708 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1709 if (edid_corrupt) 1710 *edid_corrupt = true; 1711 1712 /* allow CEA to slide through, switches mangle this */ 1713 if (raw_edid[0] == CEA_EXT) { 1714 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1715 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1716 } else { 1717 if (print_bad_edid) 1718 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1719 1720 goto bad; 1721 } 1722 } 1723 1724 /* per-block-type checks */ 1725 switch (raw_edid[0]) { 1726 case 0: /* base */ 1727 if (edid->version != 1) { 1728 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1729 goto bad; 1730 } 1731 1732 if (edid->revision > 4) 1733 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1734 break; 1735 1736 default: 1737 break; 1738 } 1739 1740 return true; 1741 1742 bad: 1743 if (print_bad_edid) { 1744 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1745 pr_notice("EDID block is all zeroes\n"); 1746 } else { 1747 pr_notice("Raw EDID:\n"); 1748 print_hex_dump(KERN_NOTICE, 1749 " \t", DUMP_PREFIX_NONE, 16, 1, 1750 raw_edid, EDID_LENGTH, false); 1751 } 1752 } 1753 return false; 1754 } 1755 EXPORT_SYMBOL(drm_edid_block_valid); 1756 1757 /** 1758 * drm_edid_is_valid - sanity check EDID data 1759 * @edid: EDID data 1760 * 1761 * Sanity-check an entire EDID record (including extensions) 1762 * 1763 * Return: True if the EDID data is valid, false otherwise. 1764 */ 1765 bool drm_edid_is_valid(struct edid *edid) 1766 { 1767 int i; 1768 u8 *raw = (u8 *)edid; 1769 1770 if (!edid) 1771 return false; 1772 1773 for (i = 0; i <= edid->extensions; i++) 1774 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1775 return false; 1776 1777 return true; 1778 } 1779 EXPORT_SYMBOL(drm_edid_is_valid); 1780 1781 #define DDC_SEGMENT_ADDR 0x30 1782 /** 1783 * drm_do_probe_ddc_edid() - get EDID information via I2C 1784 * @data: I2C device adapter 1785 * @buf: EDID data buffer to be filled 1786 * @block: 128 byte EDID block to start fetching from 1787 * @len: EDID data buffer length to fetch 1788 * 1789 * Try to fetch EDID information by calling I2C driver functions. 1790 * 1791 * Return: 0 on success or -1 on failure. 1792 */ 1793 static int 1794 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1795 { 1796 struct i2c_adapter *adapter = data; 1797 unsigned char start = block * EDID_LENGTH; 1798 unsigned char segment = block >> 1; 1799 unsigned char xfers = segment ? 3 : 2; 1800 int ret, retries = 5; 1801 1802 /* 1803 * The core I2C driver will automatically retry the transfer if the 1804 * adapter reports EAGAIN. However, we find that bit-banging transfers 1805 * are susceptible to errors under a heavily loaded machine and 1806 * generate spurious NAKs and timeouts. Retrying the transfer 1807 * of the individual block a few times seems to overcome this. 1808 */ 1809 do { 1810 struct i2c_msg msgs[] = { 1811 { 1812 .addr = DDC_SEGMENT_ADDR, 1813 .flags = 0, 1814 .len = 1, 1815 .buf = &segment, 1816 }, { 1817 .addr = DDC_ADDR, 1818 .flags = 0, 1819 .len = 1, 1820 .buf = &start, 1821 }, { 1822 .addr = DDC_ADDR, 1823 .flags = I2C_M_RD, 1824 .len = len, 1825 .buf = buf, 1826 } 1827 }; 1828 1829 /* 1830 * Avoid sending the segment addr to not upset non-compliant 1831 * DDC monitors. 1832 */ 1833 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1834 1835 if (ret == -ENXIO) { 1836 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1837 adapter->name); 1838 break; 1839 } 1840 } while (ret != xfers && --retries); 1841 1842 return ret == xfers ? 0 : -1; 1843 } 1844 1845 static void connector_bad_edid(struct drm_connector *connector, 1846 u8 *edid, int num_blocks) 1847 { 1848 int i; 1849 u8 last_block; 1850 1851 /* 1852 * 0x7e in the EDID is the number of extension blocks. The EDID 1853 * is 1 (base block) + num_ext_blocks big. That means we can think 1854 * of 0x7e in the EDID of the _index_ of the last block in the 1855 * combined chunk of memory. 1856 */ 1857 last_block = edid[0x7e]; 1858 1859 /* Calculate real checksum for the last edid extension block data */ 1860 if (last_block < num_blocks) 1861 connector->real_edid_checksum = 1862 drm_edid_block_checksum(edid + last_block * EDID_LENGTH); 1863 1864 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1865 return; 1866 1867 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 1868 for (i = 0; i < num_blocks; i++) { 1869 u8 *block = edid + i * EDID_LENGTH; 1870 char prefix[20]; 1871 1872 if (drm_edid_is_zero(block, EDID_LENGTH)) 1873 sprintf(prefix, "\t[%02x] ZERO ", i); 1874 else if (!drm_edid_block_valid(block, i, false, NULL)) 1875 sprintf(prefix, "\t[%02x] BAD ", i); 1876 else 1877 sprintf(prefix, "\t[%02x] GOOD ", i); 1878 1879 print_hex_dump(KERN_DEBUG, 1880 prefix, DUMP_PREFIX_NONE, 16, 1, 1881 block, EDID_LENGTH, false); 1882 } 1883 } 1884 1885 /* Get override or firmware EDID */ 1886 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1887 { 1888 struct edid *override = NULL; 1889 1890 if (connector->override_edid) 1891 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1892 1893 if (!override) 1894 override = drm_load_edid_firmware(connector); 1895 1896 return IS_ERR(override) ? NULL : override; 1897 } 1898 1899 /** 1900 * drm_add_override_edid_modes - add modes from override/firmware EDID 1901 * @connector: connector we're probing 1902 * 1903 * Add modes from the override/firmware EDID, if available. Only to be used from 1904 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1905 * failed during drm_get_edid() and caused the override/firmware EDID to be 1906 * skipped. 1907 * 1908 * Return: The number of modes added or 0 if we couldn't find any. 1909 */ 1910 int drm_add_override_edid_modes(struct drm_connector *connector) 1911 { 1912 struct edid *override; 1913 int num_modes = 0; 1914 1915 override = drm_get_override_edid(connector); 1916 if (override) { 1917 drm_connector_update_edid_property(connector, override); 1918 num_modes = drm_add_edid_modes(connector, override); 1919 kfree(override); 1920 1921 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1922 connector->base.id, connector->name, num_modes); 1923 } 1924 1925 return num_modes; 1926 } 1927 EXPORT_SYMBOL(drm_add_override_edid_modes); 1928 1929 static struct edid *drm_do_get_edid_base_block(struct drm_connector *connector, 1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1931 size_t len), 1932 void *data) 1933 { 1934 int *null_edid_counter = connector ? &connector->null_edid_counter : NULL; 1935 bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL; 1936 void *edid; 1937 int i; 1938 1939 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 1940 if (edid == NULL) 1941 return NULL; 1942 1943 /* base block fetch */ 1944 for (i = 0; i < 4; i++) { 1945 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1946 goto out; 1947 if (drm_edid_block_valid(edid, 0, false, edid_corrupt)) 1948 break; 1949 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1950 if (null_edid_counter) 1951 (*null_edid_counter)++; 1952 goto carp; 1953 } 1954 } 1955 if (i == 4) 1956 goto carp; 1957 1958 return edid; 1959 1960 carp: 1961 if (connector) 1962 connector_bad_edid(connector, edid, 1); 1963 out: 1964 kfree(edid); 1965 return NULL; 1966 } 1967 1968 /** 1969 * drm_do_get_edid - get EDID data using a custom EDID block read function 1970 * @connector: connector we're probing 1971 * @get_edid_block: EDID block read function 1972 * @data: private data passed to the block read function 1973 * 1974 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1975 * exposes a different interface to read EDID blocks this function can be used 1976 * to get EDID data using a custom block read function. 1977 * 1978 * As in the general case the DDC bus is accessible by the kernel at the I2C 1979 * level, drivers must make all reasonable efforts to expose it as an I2C 1980 * adapter and use drm_get_edid() instead of abusing this function. 1981 * 1982 * The EDID may be overridden using debugfs override_edid or firmware EDID 1983 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1984 * order. Having either of them bypasses actual EDID reads. 1985 * 1986 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1987 */ 1988 struct edid *drm_do_get_edid(struct drm_connector *connector, 1989 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1990 size_t len), 1991 void *data) 1992 { 1993 int i, j = 0, valid_extensions = 0; 1994 u8 *edid, *new; 1995 struct edid *override; 1996 1997 override = drm_get_override_edid(connector); 1998 if (override) 1999 return override; 2000 2001 edid = (u8 *)drm_do_get_edid_base_block(connector, get_edid_block, data); 2002 if (!edid) 2003 return NULL; 2004 2005 /* if there's no extensions or no connector, we're done */ 2006 valid_extensions = edid[0x7e]; 2007 if (valid_extensions == 0) 2008 return (struct edid *)edid; 2009 2010 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2011 if (!new) 2012 goto out; 2013 edid = new; 2014 2015 for (j = 1; j <= edid[0x7e]; j++) { 2016 u8 *block = edid + j * EDID_LENGTH; 2017 2018 for (i = 0; i < 4; i++) { 2019 if (get_edid_block(data, block, j, EDID_LENGTH)) 2020 goto out; 2021 if (drm_edid_block_valid(block, j, false, NULL)) 2022 break; 2023 } 2024 2025 if (i == 4) 2026 valid_extensions--; 2027 } 2028 2029 if (valid_extensions != edid[0x7e]) { 2030 u8 *base; 2031 2032 connector_bad_edid(connector, edid, edid[0x7e] + 1); 2033 2034 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 2035 GFP_KERNEL); 2036 if (!new) 2037 goto out; 2038 2039 base = new; 2040 for (i = 0; i <= edid[0x7e]; i++) { 2041 u8 *block = edid + i * EDID_LENGTH; 2042 2043 if (!drm_edid_block_valid(block, i, false, NULL)) 2044 continue; 2045 2046 memcpy(base, block, EDID_LENGTH); 2047 base += EDID_LENGTH; 2048 } 2049 2050 new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions; 2051 new[0x7e] = valid_extensions; 2052 2053 kfree(edid); 2054 edid = new; 2055 } 2056 2057 return (struct edid *)edid; 2058 2059 out: 2060 kfree(edid); 2061 return NULL; 2062 } 2063 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2064 2065 /** 2066 * drm_probe_ddc() - probe DDC presence 2067 * @adapter: I2C adapter to probe 2068 * 2069 * Return: True on success, false on failure. 2070 */ 2071 bool 2072 drm_probe_ddc(struct i2c_adapter *adapter) 2073 { 2074 unsigned char out; 2075 2076 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2077 } 2078 EXPORT_SYMBOL(drm_probe_ddc); 2079 2080 /** 2081 * drm_get_edid - get EDID data, if available 2082 * @connector: connector we're probing 2083 * @adapter: I2C adapter to use for DDC 2084 * 2085 * Poke the given I2C channel to grab EDID data if possible. If found, 2086 * attach it to the connector. 2087 * 2088 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2089 */ 2090 struct edid *drm_get_edid(struct drm_connector *connector, 2091 struct i2c_adapter *adapter) 2092 { 2093 struct edid *edid; 2094 2095 if (connector->force == DRM_FORCE_OFF) 2096 return NULL; 2097 2098 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2099 return NULL; 2100 2101 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2102 drm_connector_update_edid_property(connector, edid); 2103 return edid; 2104 } 2105 EXPORT_SYMBOL(drm_get_edid); 2106 2107 static u32 edid_extract_panel_id(const struct edid *edid) 2108 { 2109 /* 2110 * We represent the ID as a 32-bit number so it can easily be compared 2111 * with "==". 2112 * 2113 * NOTE that we deal with endianness differently for the top half 2114 * of this ID than for the bottom half. The bottom half (the product 2115 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2116 * that's how everyone seems to interpret it. The top half (the mfg_id) 2117 * gets stored as big endian because that makes 2118 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2119 * to write (it's easier to extract the ASCII). It doesn't really 2120 * matter, though, as long as the number here is unique. 2121 */ 2122 return (u32)edid->mfg_id[0] << 24 | 2123 (u32)edid->mfg_id[1] << 16 | 2124 (u32)EDID_PRODUCT_ID(edid); 2125 } 2126 2127 /** 2128 * drm_edid_get_panel_id - Get a panel's ID through DDC 2129 * @adapter: I2C adapter to use for DDC 2130 * 2131 * This function reads the first block of the EDID of a panel and (assuming 2132 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2133 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2134 * supposed to be different for each different modem of panel. 2135 * 2136 * This function is intended to be used during early probing on devices where 2137 * more than one panel might be present. Because of its intended use it must 2138 * assume that the EDID of the panel is correct, at least as far as the ID 2139 * is concerned (in other words, we don't process any overrides here). 2140 * 2141 * NOTE: it's expected that this function and drm_do_get_edid() will both 2142 * be read the EDID, but there is no caching between them. Since we're only 2143 * reading the first block, hopefully this extra overhead won't be too big. 2144 * 2145 * Return: A 32-bit ID that should be different for each make/model of panel. 2146 * See the functions drm_edid_encode_panel_id() and 2147 * drm_edid_decode_panel_id() for some details on the structure of this 2148 * ID. 2149 */ 2150 2151 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2152 { 2153 const struct edid *edid; 2154 u32 panel_id; 2155 2156 edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter); 2157 2158 /* 2159 * There are no manufacturer IDs of 0, so if there is a problem reading 2160 * the EDID then we'll just return 0. 2161 */ 2162 if (!edid) 2163 return 0; 2164 2165 panel_id = edid_extract_panel_id(edid); 2166 kfree(edid); 2167 2168 return panel_id; 2169 } 2170 EXPORT_SYMBOL(drm_edid_get_panel_id); 2171 2172 /** 2173 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2174 * @connector: connector we're probing 2175 * @adapter: I2C adapter to use for DDC 2176 * 2177 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2178 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2179 * switch DDC to the GPU which is retrieving EDID. 2180 * 2181 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2182 */ 2183 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2184 struct i2c_adapter *adapter) 2185 { 2186 struct drm_device *dev = connector->dev; 2187 struct pci_dev *pdev = to_pci_dev(dev->dev); 2188 struct edid *edid; 2189 2190 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2191 return NULL; 2192 2193 vga_switcheroo_lock_ddc(pdev); 2194 edid = drm_get_edid(connector, adapter); 2195 vga_switcheroo_unlock_ddc(pdev); 2196 2197 return edid; 2198 } 2199 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2200 2201 /** 2202 * drm_edid_duplicate - duplicate an EDID and the extensions 2203 * @edid: EDID to duplicate 2204 * 2205 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2206 */ 2207 struct edid *drm_edid_duplicate(const struct edid *edid) 2208 { 2209 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2210 } 2211 EXPORT_SYMBOL(drm_edid_duplicate); 2212 2213 /*** EDID parsing ***/ 2214 2215 /** 2216 * edid_get_quirks - return quirk flags for a given EDID 2217 * @edid: EDID to process 2218 * 2219 * This tells subsequent routines what fixes they need to apply. 2220 */ 2221 static u32 edid_get_quirks(const struct edid *edid) 2222 { 2223 u32 panel_id = edid_extract_panel_id(edid); 2224 const struct edid_quirk *quirk; 2225 int i; 2226 2227 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2228 quirk = &edid_quirk_list[i]; 2229 if (quirk->panel_id == panel_id) 2230 return quirk->quirks; 2231 } 2232 2233 return 0; 2234 } 2235 2236 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2237 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2238 2239 /** 2240 * edid_fixup_preferred - set preferred modes based on quirk list 2241 * @connector: has mode list to fix up 2242 * @quirks: quirks list 2243 * 2244 * Walk the mode list for @connector, clearing the preferred status 2245 * on existing modes and setting it anew for the right mode ala @quirks. 2246 */ 2247 static void edid_fixup_preferred(struct drm_connector *connector, 2248 u32 quirks) 2249 { 2250 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2251 int target_refresh = 0; 2252 int cur_vrefresh, preferred_vrefresh; 2253 2254 if (list_empty(&connector->probed_modes)) 2255 return; 2256 2257 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2258 target_refresh = 60; 2259 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2260 target_refresh = 75; 2261 2262 preferred_mode = list_first_entry(&connector->probed_modes, 2263 struct drm_display_mode, head); 2264 2265 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2266 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2267 2268 if (cur_mode == preferred_mode) 2269 continue; 2270 2271 /* Largest mode is preferred */ 2272 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2273 preferred_mode = cur_mode; 2274 2275 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2276 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2277 /* At a given size, try to get closest to target refresh */ 2278 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2279 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2280 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2281 preferred_mode = cur_mode; 2282 } 2283 } 2284 2285 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2286 } 2287 2288 static bool 2289 mode_is_rb(const struct drm_display_mode *mode) 2290 { 2291 return (mode->htotal - mode->hdisplay == 160) && 2292 (mode->hsync_end - mode->hdisplay == 80) && 2293 (mode->hsync_end - mode->hsync_start == 32) && 2294 (mode->vsync_start - mode->vdisplay == 3); 2295 } 2296 2297 /* 2298 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2299 * @dev: Device to duplicate against 2300 * @hsize: Mode width 2301 * @vsize: Mode height 2302 * @fresh: Mode refresh rate 2303 * @rb: Mode reduced-blanking-ness 2304 * 2305 * Walk the DMT mode list looking for a match for the given parameters. 2306 * 2307 * Return: A newly allocated copy of the mode, or NULL if not found. 2308 */ 2309 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2310 int hsize, int vsize, int fresh, 2311 bool rb) 2312 { 2313 int i; 2314 2315 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2316 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2317 2318 if (hsize != ptr->hdisplay) 2319 continue; 2320 if (vsize != ptr->vdisplay) 2321 continue; 2322 if (fresh != drm_mode_vrefresh(ptr)) 2323 continue; 2324 if (rb != mode_is_rb(ptr)) 2325 continue; 2326 2327 return drm_mode_duplicate(dev, ptr); 2328 } 2329 2330 return NULL; 2331 } 2332 EXPORT_SYMBOL(drm_mode_find_dmt); 2333 2334 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2335 { 2336 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2337 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2338 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2339 2340 return descriptor->pixel_clock == 0 && 2341 descriptor->data.other_data.pad1 == 0 && 2342 descriptor->data.other_data.type == type; 2343 } 2344 2345 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2346 { 2347 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2348 2349 return descriptor->pixel_clock != 0; 2350 } 2351 2352 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2353 2354 static void 2355 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2356 { 2357 int i, n; 2358 u8 d = ext[0x02]; 2359 const u8 *det_base = ext + d; 2360 2361 if (d < 4 || d > 127) 2362 return; 2363 2364 n = (127 - d) / 18; 2365 for (i = 0; i < n; i++) 2366 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2367 } 2368 2369 static void 2370 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2371 { 2372 unsigned int i, n = min((int)ext[0x02], 6); 2373 const u8 *det_base = ext + 5; 2374 2375 if (ext[0x01] != 1) 2376 return; /* unknown version */ 2377 2378 for (i = 0; i < n; i++) 2379 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2380 } 2381 2382 static void 2383 drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure) 2384 { 2385 int i; 2386 2387 if (edid == NULL) 2388 return; 2389 2390 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2391 cb(&(edid->detailed_timings[i]), closure); 2392 2393 for (i = 1; i <= edid->extensions; i++) { 2394 const u8 *ext = (const u8 *)edid + (i * EDID_LENGTH); 2395 2396 switch (*ext) { 2397 case CEA_EXT: 2398 cea_for_each_detailed_block(ext, cb, closure); 2399 break; 2400 case VTB_EXT: 2401 vtb_for_each_detailed_block(ext, cb, closure); 2402 break; 2403 default: 2404 break; 2405 } 2406 } 2407 } 2408 2409 static void 2410 is_rb(const struct detailed_timing *descriptor, void *data) 2411 { 2412 bool *res = data; 2413 2414 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2415 return; 2416 2417 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2418 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 2419 2420 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 2421 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) 2422 *res = true; 2423 } 2424 2425 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2426 static bool 2427 drm_monitor_supports_rb(const struct edid *edid) 2428 { 2429 if (edid->revision >= 4) { 2430 bool ret = false; 2431 2432 drm_for_each_detailed_block(edid, is_rb, &ret); 2433 return ret; 2434 } 2435 2436 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2437 } 2438 2439 static void 2440 find_gtf2(const struct detailed_timing *descriptor, void *data) 2441 { 2442 const struct detailed_timing **res = data; 2443 2444 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2445 return; 2446 2447 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2448 2449 if (descriptor->data.other_data.data.range.flags == 0x02) 2450 *res = descriptor; 2451 } 2452 2453 /* Secondary GTF curve kicks in above some break frequency */ 2454 static int 2455 drm_gtf2_hbreak(const struct edid *edid) 2456 { 2457 const struct detailed_timing *descriptor = NULL; 2458 2459 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2460 2461 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 2462 2463 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 2464 } 2465 2466 static int 2467 drm_gtf2_2c(const struct edid *edid) 2468 { 2469 const struct detailed_timing *descriptor = NULL; 2470 2471 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2472 2473 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 2474 2475 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 2476 } 2477 2478 static int 2479 drm_gtf2_m(const struct edid *edid) 2480 { 2481 const struct detailed_timing *descriptor = NULL; 2482 2483 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2484 2485 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 2486 2487 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 2488 } 2489 2490 static int 2491 drm_gtf2_k(const struct edid *edid) 2492 { 2493 const struct detailed_timing *descriptor = NULL; 2494 2495 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2496 2497 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 2498 2499 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 2500 } 2501 2502 static int 2503 drm_gtf2_2j(const struct edid *edid) 2504 { 2505 const struct detailed_timing *descriptor = NULL; 2506 2507 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2508 2509 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 2510 2511 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 2512 } 2513 2514 /** 2515 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2516 * @edid: EDID block to scan 2517 */ 2518 static int standard_timing_level(const struct edid *edid) 2519 { 2520 if (edid->revision >= 2) { 2521 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2522 return LEVEL_CVT; 2523 if (drm_gtf2_hbreak(edid)) 2524 return LEVEL_GTF2; 2525 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2526 return LEVEL_GTF; 2527 } 2528 return LEVEL_DMT; 2529 } 2530 2531 /* 2532 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2533 * monitors fill with ascii space (0x20) instead. 2534 */ 2535 static int 2536 bad_std_timing(u8 a, u8 b) 2537 { 2538 return (a == 0x00 && b == 0x00) || 2539 (a == 0x01 && b == 0x01) || 2540 (a == 0x20 && b == 0x20); 2541 } 2542 2543 static int drm_mode_hsync(const struct drm_display_mode *mode) 2544 { 2545 if (mode->htotal <= 0) 2546 return 0; 2547 2548 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2549 } 2550 2551 /** 2552 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2553 * @connector: connector of for the EDID block 2554 * @edid: EDID block to scan 2555 * @t: standard timing params 2556 * 2557 * Take the standard timing params (in this case width, aspect, and refresh) 2558 * and convert them into a real mode using CVT/GTF/DMT. 2559 */ 2560 static struct drm_display_mode * 2561 drm_mode_std(struct drm_connector *connector, const struct edid *edid, 2562 const struct std_timing *t) 2563 { 2564 struct drm_device *dev = connector->dev; 2565 struct drm_display_mode *m, *mode = NULL; 2566 int hsize, vsize; 2567 int vrefresh_rate; 2568 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2569 >> EDID_TIMING_ASPECT_SHIFT; 2570 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2571 >> EDID_TIMING_VFREQ_SHIFT; 2572 int timing_level = standard_timing_level(edid); 2573 2574 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2575 return NULL; 2576 2577 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2578 hsize = t->hsize * 8 + 248; 2579 /* vrefresh_rate = vfreq + 60 */ 2580 vrefresh_rate = vfreq + 60; 2581 /* the vdisplay is calculated based on the aspect ratio */ 2582 if (aspect_ratio == 0) { 2583 if (edid->revision < 3) 2584 vsize = hsize; 2585 else 2586 vsize = (hsize * 10) / 16; 2587 } else if (aspect_ratio == 1) 2588 vsize = (hsize * 3) / 4; 2589 else if (aspect_ratio == 2) 2590 vsize = (hsize * 4) / 5; 2591 else 2592 vsize = (hsize * 9) / 16; 2593 2594 /* HDTV hack, part 1 */ 2595 if (vrefresh_rate == 60 && 2596 ((hsize == 1360 && vsize == 765) || 2597 (hsize == 1368 && vsize == 769))) { 2598 hsize = 1366; 2599 vsize = 768; 2600 } 2601 2602 /* 2603 * If this connector already has a mode for this size and refresh 2604 * rate (because it came from detailed or CVT info), use that 2605 * instead. This way we don't have to guess at interlace or 2606 * reduced blanking. 2607 */ 2608 list_for_each_entry(m, &connector->probed_modes, head) 2609 if (m->hdisplay == hsize && m->vdisplay == vsize && 2610 drm_mode_vrefresh(m) == vrefresh_rate) 2611 return NULL; 2612 2613 /* HDTV hack, part 2 */ 2614 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2615 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2616 false); 2617 if (!mode) 2618 return NULL; 2619 mode->hdisplay = 1366; 2620 mode->hsync_start = mode->hsync_start - 1; 2621 mode->hsync_end = mode->hsync_end - 1; 2622 return mode; 2623 } 2624 2625 /* check whether it can be found in default mode table */ 2626 if (drm_monitor_supports_rb(edid)) { 2627 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2628 true); 2629 if (mode) 2630 return mode; 2631 } 2632 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2633 if (mode) 2634 return mode; 2635 2636 /* okay, generate it */ 2637 switch (timing_level) { 2638 case LEVEL_DMT: 2639 break; 2640 case LEVEL_GTF: 2641 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2642 break; 2643 case LEVEL_GTF2: 2644 /* 2645 * This is potentially wrong if there's ever a monitor with 2646 * more than one ranges section, each claiming a different 2647 * secondary GTF curve. Please don't do that. 2648 */ 2649 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2650 if (!mode) 2651 return NULL; 2652 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2653 drm_mode_destroy(dev, mode); 2654 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2655 vrefresh_rate, 0, 0, 2656 drm_gtf2_m(edid), 2657 drm_gtf2_2c(edid), 2658 drm_gtf2_k(edid), 2659 drm_gtf2_2j(edid)); 2660 } 2661 break; 2662 case LEVEL_CVT: 2663 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2664 false); 2665 break; 2666 } 2667 return mode; 2668 } 2669 2670 /* 2671 * EDID is delightfully ambiguous about how interlaced modes are to be 2672 * encoded. Our internal representation is of frame height, but some 2673 * HDTV detailed timings are encoded as field height. 2674 * 2675 * The format list here is from CEA, in frame size. Technically we 2676 * should be checking refresh rate too. Whatever. 2677 */ 2678 static void 2679 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2680 const struct detailed_pixel_timing *pt) 2681 { 2682 int i; 2683 static const struct { 2684 int w, h; 2685 } cea_interlaced[] = { 2686 { 1920, 1080 }, 2687 { 720, 480 }, 2688 { 1440, 480 }, 2689 { 2880, 480 }, 2690 { 720, 576 }, 2691 { 1440, 576 }, 2692 { 2880, 576 }, 2693 }; 2694 2695 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2696 return; 2697 2698 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2699 if ((mode->hdisplay == cea_interlaced[i].w) && 2700 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2701 mode->vdisplay *= 2; 2702 mode->vsync_start *= 2; 2703 mode->vsync_end *= 2; 2704 mode->vtotal *= 2; 2705 mode->vtotal |= 1; 2706 } 2707 } 2708 2709 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2710 } 2711 2712 /** 2713 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2714 * @dev: DRM device (needed to create new mode) 2715 * @edid: EDID block 2716 * @timing: EDID detailed timing info 2717 * @quirks: quirks to apply 2718 * 2719 * An EDID detailed timing block contains enough info for us to create and 2720 * return a new struct drm_display_mode. 2721 */ 2722 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2723 const struct edid *edid, 2724 const struct detailed_timing *timing, 2725 u32 quirks) 2726 { 2727 struct drm_display_mode *mode; 2728 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2729 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2730 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2731 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2732 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2733 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2734 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2735 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2736 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2737 2738 /* ignore tiny modes */ 2739 if (hactive < 64 || vactive < 64) 2740 return NULL; 2741 2742 if (pt->misc & DRM_EDID_PT_STEREO) { 2743 DRM_DEBUG_KMS("stereo mode not supported\n"); 2744 return NULL; 2745 } 2746 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2747 DRM_DEBUG_KMS("composite sync not supported\n"); 2748 } 2749 2750 /* it is incorrect if hsync/vsync width is zero */ 2751 if (!hsync_pulse_width || !vsync_pulse_width) { 2752 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2753 "Wrong Hsync/Vsync pulse width\n"); 2754 return NULL; 2755 } 2756 2757 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2758 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2759 if (!mode) 2760 return NULL; 2761 2762 goto set_size; 2763 } 2764 2765 mode = drm_mode_create(dev); 2766 if (!mode) 2767 return NULL; 2768 2769 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2770 mode->clock = 1088 * 10; 2771 else 2772 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2773 2774 mode->hdisplay = hactive; 2775 mode->hsync_start = mode->hdisplay + hsync_offset; 2776 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2777 mode->htotal = mode->hdisplay + hblank; 2778 2779 mode->vdisplay = vactive; 2780 mode->vsync_start = mode->vdisplay + vsync_offset; 2781 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2782 mode->vtotal = mode->vdisplay + vblank; 2783 2784 /* Some EDIDs have bogus h/vtotal values */ 2785 if (mode->hsync_end > mode->htotal) 2786 mode->htotal = mode->hsync_end + 1; 2787 if (mode->vsync_end > mode->vtotal) 2788 mode->vtotal = mode->vsync_end + 1; 2789 2790 drm_mode_do_interlace_quirk(mode, pt); 2791 2792 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2793 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 2794 } else { 2795 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2796 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2797 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2798 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2799 } 2800 2801 set_size: 2802 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2803 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2804 2805 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2806 mode->width_mm *= 10; 2807 mode->height_mm *= 10; 2808 } 2809 2810 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2811 mode->width_mm = edid->width_cm * 10; 2812 mode->height_mm = edid->height_cm * 10; 2813 } 2814 2815 mode->type = DRM_MODE_TYPE_DRIVER; 2816 drm_mode_set_name(mode); 2817 2818 return mode; 2819 } 2820 2821 static bool 2822 mode_in_hsync_range(const struct drm_display_mode *mode, 2823 const struct edid *edid, const u8 *t) 2824 { 2825 int hsync, hmin, hmax; 2826 2827 hmin = t[7]; 2828 if (edid->revision >= 4) 2829 hmin += ((t[4] & 0x04) ? 255 : 0); 2830 hmax = t[8]; 2831 if (edid->revision >= 4) 2832 hmax += ((t[4] & 0x08) ? 255 : 0); 2833 hsync = drm_mode_hsync(mode); 2834 2835 return (hsync <= hmax && hsync >= hmin); 2836 } 2837 2838 static bool 2839 mode_in_vsync_range(const struct drm_display_mode *mode, 2840 const struct edid *edid, const u8 *t) 2841 { 2842 int vsync, vmin, vmax; 2843 2844 vmin = t[5]; 2845 if (edid->revision >= 4) 2846 vmin += ((t[4] & 0x01) ? 255 : 0); 2847 vmax = t[6]; 2848 if (edid->revision >= 4) 2849 vmax += ((t[4] & 0x02) ? 255 : 0); 2850 vsync = drm_mode_vrefresh(mode); 2851 2852 return (vsync <= vmax && vsync >= vmin); 2853 } 2854 2855 static u32 2856 range_pixel_clock(const struct edid *edid, const u8 *t) 2857 { 2858 /* unspecified */ 2859 if (t[9] == 0 || t[9] == 255) 2860 return 0; 2861 2862 /* 1.4 with CVT support gives us real precision, yay */ 2863 if (edid->revision >= 4 && t[10] == 0x04) 2864 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2865 2866 /* 1.3 is pathetic, so fuzz up a bit */ 2867 return t[9] * 10000 + 5001; 2868 } 2869 2870 static bool 2871 mode_in_range(const struct drm_display_mode *mode, const struct edid *edid, 2872 const struct detailed_timing *timing) 2873 { 2874 u32 max_clock; 2875 const u8 *t = (const u8 *)timing; 2876 2877 if (!mode_in_hsync_range(mode, edid, t)) 2878 return false; 2879 2880 if (!mode_in_vsync_range(mode, edid, t)) 2881 return false; 2882 2883 if ((max_clock = range_pixel_clock(edid, t))) 2884 if (mode->clock > max_clock) 2885 return false; 2886 2887 /* 1.4 max horizontal check */ 2888 if (edid->revision >= 4 && t[10] == 0x04) 2889 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2890 return false; 2891 2892 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2893 return false; 2894 2895 return true; 2896 } 2897 2898 static bool valid_inferred_mode(const struct drm_connector *connector, 2899 const struct drm_display_mode *mode) 2900 { 2901 const struct drm_display_mode *m; 2902 bool ok = false; 2903 2904 list_for_each_entry(m, &connector->probed_modes, head) { 2905 if (mode->hdisplay == m->hdisplay && 2906 mode->vdisplay == m->vdisplay && 2907 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2908 return false; /* duplicated */ 2909 if (mode->hdisplay <= m->hdisplay && 2910 mode->vdisplay <= m->vdisplay) 2911 ok = true; 2912 } 2913 return ok; 2914 } 2915 2916 static int 2917 drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid, 2918 const struct detailed_timing *timing) 2919 { 2920 int i, modes = 0; 2921 struct drm_display_mode *newmode; 2922 struct drm_device *dev = connector->dev; 2923 2924 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2925 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2926 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2927 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2928 if (newmode) { 2929 drm_mode_probed_add(connector, newmode); 2930 modes++; 2931 } 2932 } 2933 } 2934 2935 return modes; 2936 } 2937 2938 /* fix up 1366x768 mode from 1368x768; 2939 * GFT/CVT can't express 1366 width which isn't dividable by 8 2940 */ 2941 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2942 { 2943 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2944 mode->hdisplay = 1366; 2945 mode->hsync_start--; 2946 mode->hsync_end--; 2947 drm_mode_set_name(mode); 2948 } 2949 } 2950 2951 static int 2952 drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid, 2953 const struct detailed_timing *timing) 2954 { 2955 int i, modes = 0; 2956 struct drm_display_mode *newmode; 2957 struct drm_device *dev = connector->dev; 2958 2959 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2960 const struct minimode *m = &extra_modes[i]; 2961 2962 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2963 if (!newmode) 2964 return modes; 2965 2966 drm_mode_fixup_1366x768(newmode); 2967 if (!mode_in_range(newmode, edid, timing) || 2968 !valid_inferred_mode(connector, newmode)) { 2969 drm_mode_destroy(dev, newmode); 2970 continue; 2971 } 2972 2973 drm_mode_probed_add(connector, newmode); 2974 modes++; 2975 } 2976 2977 return modes; 2978 } 2979 2980 static int 2981 drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid, 2982 const struct detailed_timing *timing) 2983 { 2984 int i, modes = 0; 2985 struct drm_display_mode *newmode; 2986 struct drm_device *dev = connector->dev; 2987 bool rb = drm_monitor_supports_rb(edid); 2988 2989 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2990 const struct minimode *m = &extra_modes[i]; 2991 2992 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2993 if (!newmode) 2994 return modes; 2995 2996 drm_mode_fixup_1366x768(newmode); 2997 if (!mode_in_range(newmode, edid, timing) || 2998 !valid_inferred_mode(connector, newmode)) { 2999 drm_mode_destroy(dev, newmode); 3000 continue; 3001 } 3002 3003 drm_mode_probed_add(connector, newmode); 3004 modes++; 3005 } 3006 3007 return modes; 3008 } 3009 3010 static void 3011 do_inferred_modes(const struct detailed_timing *timing, void *c) 3012 { 3013 struct detailed_mode_closure *closure = c; 3014 const struct detailed_non_pixel *data = &timing->data.other_data; 3015 const struct detailed_data_monitor_range *range = &data->data.range; 3016 3017 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3018 return; 3019 3020 closure->modes += drm_dmt_modes_for_range(closure->connector, 3021 closure->edid, 3022 timing); 3023 3024 if (!version_greater(closure->edid, 1, 1)) 3025 return; /* GTF not defined yet */ 3026 3027 switch (range->flags) { 3028 case 0x02: /* secondary gtf, XXX could do more */ 3029 case 0x00: /* default gtf */ 3030 closure->modes += drm_gtf_modes_for_range(closure->connector, 3031 closure->edid, 3032 timing); 3033 break; 3034 case 0x04: /* cvt, only in 1.4+ */ 3035 if (!version_greater(closure->edid, 1, 3)) 3036 break; 3037 3038 closure->modes += drm_cvt_modes_for_range(closure->connector, 3039 closure->edid, 3040 timing); 3041 break; 3042 case 0x01: /* just the ranges, no formula */ 3043 default: 3044 break; 3045 } 3046 } 3047 3048 static int 3049 add_inferred_modes(struct drm_connector *connector, const struct edid *edid) 3050 { 3051 struct detailed_mode_closure closure = { 3052 .connector = connector, 3053 .edid = edid, 3054 }; 3055 3056 if (version_greater(edid, 1, 0)) 3057 drm_for_each_detailed_block(edid, do_inferred_modes, &closure); 3058 3059 return closure.modes; 3060 } 3061 3062 static int 3063 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3064 { 3065 int i, j, m, modes = 0; 3066 struct drm_display_mode *mode; 3067 const u8 *est = ((const u8 *)timing) + 6; 3068 3069 for (i = 0; i < 6; i++) { 3070 for (j = 7; j >= 0; j--) { 3071 m = (i * 8) + (7 - j); 3072 if (m >= ARRAY_SIZE(est3_modes)) 3073 break; 3074 if (est[i] & (1 << j)) { 3075 mode = drm_mode_find_dmt(connector->dev, 3076 est3_modes[m].w, 3077 est3_modes[m].h, 3078 est3_modes[m].r, 3079 est3_modes[m].rb); 3080 if (mode) { 3081 drm_mode_probed_add(connector, mode); 3082 modes++; 3083 } 3084 } 3085 } 3086 } 3087 3088 return modes; 3089 } 3090 3091 static void 3092 do_established_modes(const struct detailed_timing *timing, void *c) 3093 { 3094 struct detailed_mode_closure *closure = c; 3095 3096 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3097 return; 3098 3099 closure->modes += drm_est3_modes(closure->connector, timing); 3100 } 3101 3102 /** 3103 * add_established_modes - get est. modes from EDID and add them 3104 * @connector: connector to add mode(s) to 3105 * @edid: EDID block to scan 3106 * 3107 * Each EDID block contains a bitmap of the supported "established modes" list 3108 * (defined above). Tease them out and add them to the global modes list. 3109 */ 3110 static int 3111 add_established_modes(struct drm_connector *connector, const struct edid *edid) 3112 { 3113 struct drm_device *dev = connector->dev; 3114 unsigned long est_bits = edid->established_timings.t1 | 3115 (edid->established_timings.t2 << 8) | 3116 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3117 int i, modes = 0; 3118 struct detailed_mode_closure closure = { 3119 .connector = connector, 3120 .edid = edid, 3121 }; 3122 3123 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3124 if (est_bits & (1<<i)) { 3125 struct drm_display_mode *newmode; 3126 3127 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3128 if (newmode) { 3129 drm_mode_probed_add(connector, newmode); 3130 modes++; 3131 } 3132 } 3133 } 3134 3135 if (version_greater(edid, 1, 0)) 3136 drm_for_each_detailed_block(edid, do_established_modes, 3137 &closure); 3138 3139 return modes + closure.modes; 3140 } 3141 3142 static void 3143 do_standard_modes(const struct detailed_timing *timing, void *c) 3144 { 3145 struct detailed_mode_closure *closure = c; 3146 const struct detailed_non_pixel *data = &timing->data.other_data; 3147 struct drm_connector *connector = closure->connector; 3148 const struct edid *edid = closure->edid; 3149 int i; 3150 3151 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3152 return; 3153 3154 for (i = 0; i < 6; i++) { 3155 const struct std_timing *std = &data->data.timings[i]; 3156 struct drm_display_mode *newmode; 3157 3158 newmode = drm_mode_std(connector, edid, std); 3159 if (newmode) { 3160 drm_mode_probed_add(connector, newmode); 3161 closure->modes++; 3162 } 3163 } 3164 } 3165 3166 /** 3167 * add_standard_modes - get std. modes from EDID and add them 3168 * @connector: connector to add mode(s) to 3169 * @edid: EDID block to scan 3170 * 3171 * Standard modes can be calculated using the appropriate standard (DMT, 3172 * GTF or CVT. Grab them from @edid and add them to the list. 3173 */ 3174 static int 3175 add_standard_modes(struct drm_connector *connector, const struct edid *edid) 3176 { 3177 int i, modes = 0; 3178 struct detailed_mode_closure closure = { 3179 .connector = connector, 3180 .edid = edid, 3181 }; 3182 3183 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3184 struct drm_display_mode *newmode; 3185 3186 newmode = drm_mode_std(connector, edid, 3187 &edid->standard_timings[i]); 3188 if (newmode) { 3189 drm_mode_probed_add(connector, newmode); 3190 modes++; 3191 } 3192 } 3193 3194 if (version_greater(edid, 1, 0)) 3195 drm_for_each_detailed_block(edid, do_standard_modes, 3196 &closure); 3197 3198 /* XXX should also look for standard codes in VTB blocks */ 3199 3200 return modes + closure.modes; 3201 } 3202 3203 static int drm_cvt_modes(struct drm_connector *connector, 3204 const struct detailed_timing *timing) 3205 { 3206 int i, j, modes = 0; 3207 struct drm_display_mode *newmode; 3208 struct drm_device *dev = connector->dev; 3209 const struct cvt_timing *cvt; 3210 const int rates[] = { 60, 85, 75, 60, 50 }; 3211 const u8 empty[3] = { 0, 0, 0 }; 3212 3213 for (i = 0; i < 4; i++) { 3214 int width, height; 3215 3216 cvt = &(timing->data.other_data.data.cvt[i]); 3217 3218 if (!memcmp(cvt->code, empty, 3)) 3219 continue; 3220 3221 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3222 switch (cvt->code[1] & 0x0c) { 3223 /* default - because compiler doesn't see that we've enumerated all cases */ 3224 default: 3225 case 0x00: 3226 width = height * 4 / 3; 3227 break; 3228 case 0x04: 3229 width = height * 16 / 9; 3230 break; 3231 case 0x08: 3232 width = height * 16 / 10; 3233 break; 3234 case 0x0c: 3235 width = height * 15 / 9; 3236 break; 3237 } 3238 3239 for (j = 1; j < 5; j++) { 3240 if (cvt->code[2] & (1 << j)) { 3241 newmode = drm_cvt_mode(dev, width, height, 3242 rates[j], j == 0, 3243 false, false); 3244 if (newmode) { 3245 drm_mode_probed_add(connector, newmode); 3246 modes++; 3247 } 3248 } 3249 } 3250 } 3251 3252 return modes; 3253 } 3254 3255 static void 3256 do_cvt_mode(const struct detailed_timing *timing, void *c) 3257 { 3258 struct detailed_mode_closure *closure = c; 3259 3260 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3261 return; 3262 3263 closure->modes += drm_cvt_modes(closure->connector, timing); 3264 } 3265 3266 static int 3267 add_cvt_modes(struct drm_connector *connector, const struct edid *edid) 3268 { 3269 struct detailed_mode_closure closure = { 3270 .connector = connector, 3271 .edid = edid, 3272 }; 3273 3274 if (version_greater(edid, 1, 2)) 3275 drm_for_each_detailed_block(edid, do_cvt_mode, &closure); 3276 3277 /* XXX should also look for CVT codes in VTB blocks */ 3278 3279 return closure.modes; 3280 } 3281 3282 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3283 3284 static void 3285 do_detailed_mode(const struct detailed_timing *timing, void *c) 3286 { 3287 struct detailed_mode_closure *closure = c; 3288 struct drm_display_mode *newmode; 3289 3290 if (!is_detailed_timing_descriptor(timing)) 3291 return; 3292 3293 newmode = drm_mode_detailed(closure->connector->dev, 3294 closure->edid, timing, 3295 closure->quirks); 3296 if (!newmode) 3297 return; 3298 3299 if (closure->preferred) 3300 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3301 3302 /* 3303 * Detailed modes are limited to 10kHz pixel clock resolution, 3304 * so fix up anything that looks like CEA/HDMI mode, but the clock 3305 * is just slightly off. 3306 */ 3307 fixup_detailed_cea_mode_clock(newmode); 3308 3309 drm_mode_probed_add(closure->connector, newmode); 3310 closure->modes++; 3311 closure->preferred = false; 3312 } 3313 3314 /* 3315 * add_detailed_modes - Add modes from detailed timings 3316 * @connector: attached connector 3317 * @edid: EDID block to scan 3318 * @quirks: quirks to apply 3319 */ 3320 static int 3321 add_detailed_modes(struct drm_connector *connector, const struct edid *edid, 3322 u32 quirks) 3323 { 3324 struct detailed_mode_closure closure = { 3325 .connector = connector, 3326 .edid = edid, 3327 .preferred = true, 3328 .quirks = quirks, 3329 }; 3330 3331 if (closure.preferred && !version_greater(edid, 1, 3)) 3332 closure.preferred = 3333 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3334 3335 drm_for_each_detailed_block(edid, do_detailed_mode, &closure); 3336 3337 return closure.modes; 3338 } 3339 3340 #define AUDIO_BLOCK 0x01 3341 #define VIDEO_BLOCK 0x02 3342 #define VENDOR_BLOCK 0x03 3343 #define SPEAKER_BLOCK 0x04 3344 #define HDR_STATIC_METADATA_BLOCK 0x6 3345 #define USE_EXTENDED_TAG 0x07 3346 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3347 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3348 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3349 #define EDID_BASIC_AUDIO (1 << 6) 3350 #define EDID_CEA_YCRCB444 (1 << 5) 3351 #define EDID_CEA_YCRCB422 (1 << 4) 3352 #define EDID_CEA_VCDB_QS (1 << 6) 3353 3354 /* 3355 * Search EDID for CEA extension block. 3356 */ 3357 const u8 *drm_find_edid_extension(const struct edid *edid, 3358 int ext_id, int *ext_index) 3359 { 3360 const u8 *edid_ext = NULL; 3361 int i; 3362 3363 /* No EDID or EDID extensions */ 3364 if (edid == NULL || edid->extensions == 0) 3365 return NULL; 3366 3367 /* Find CEA extension */ 3368 for (i = *ext_index; i < edid->extensions; i++) { 3369 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1); 3370 if (edid_ext[0] == ext_id) 3371 break; 3372 } 3373 3374 if (i >= edid->extensions) 3375 return NULL; 3376 3377 *ext_index = i + 1; 3378 3379 return edid_ext; 3380 } 3381 3382 static const u8 *drm_find_cea_extension(const struct edid *edid) 3383 { 3384 const struct displayid_block *block; 3385 struct displayid_iter iter; 3386 const u8 *cea; 3387 int ext_index = 0; 3388 3389 /* Look for a top level CEA extension block */ 3390 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3391 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3392 if (cea) 3393 return cea; 3394 3395 /* CEA blocks can also be found embedded in a DisplayID block */ 3396 displayid_iter_edid_begin(edid, &iter); 3397 displayid_iter_for_each(block, &iter) { 3398 if (block->tag == DATA_BLOCK_CTA) { 3399 cea = (const u8 *)block; 3400 break; 3401 } 3402 } 3403 displayid_iter_end(&iter); 3404 3405 return cea; 3406 } 3407 3408 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3409 { 3410 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3411 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3412 3413 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3414 return &edid_cea_modes_1[vic - 1]; 3415 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3416 return &edid_cea_modes_193[vic - 193]; 3417 return NULL; 3418 } 3419 3420 static u8 cea_num_vics(void) 3421 { 3422 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3423 } 3424 3425 static u8 cea_next_vic(u8 vic) 3426 { 3427 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3428 vic = 193; 3429 return vic; 3430 } 3431 3432 /* 3433 * Calculate the alternate clock for the CEA mode 3434 * (60Hz vs. 59.94Hz etc.) 3435 */ 3436 static unsigned int 3437 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3438 { 3439 unsigned int clock = cea_mode->clock; 3440 3441 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3442 return clock; 3443 3444 /* 3445 * edid_cea_modes contains the 59.94Hz 3446 * variant for 240 and 480 line modes, 3447 * and the 60Hz variant otherwise. 3448 */ 3449 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3450 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3451 else 3452 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3453 3454 return clock; 3455 } 3456 3457 static bool 3458 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3459 { 3460 /* 3461 * For certain VICs the spec allows the vertical 3462 * front porch to vary by one or two lines. 3463 * 3464 * cea_modes[] stores the variant with the shortest 3465 * vertical front porch. We can adjust the mode to 3466 * get the other variants by simply increasing the 3467 * vertical front porch length. 3468 */ 3469 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3470 cea_mode_for_vic(9)->vtotal != 262 || 3471 cea_mode_for_vic(12)->vtotal != 262 || 3472 cea_mode_for_vic(13)->vtotal != 262 || 3473 cea_mode_for_vic(23)->vtotal != 312 || 3474 cea_mode_for_vic(24)->vtotal != 312 || 3475 cea_mode_for_vic(27)->vtotal != 312 || 3476 cea_mode_for_vic(28)->vtotal != 312); 3477 3478 if (((vic == 8 || vic == 9 || 3479 vic == 12 || vic == 13) && mode->vtotal < 263) || 3480 ((vic == 23 || vic == 24 || 3481 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3482 mode->vsync_start++; 3483 mode->vsync_end++; 3484 mode->vtotal++; 3485 3486 return true; 3487 } 3488 3489 return false; 3490 } 3491 3492 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3493 unsigned int clock_tolerance) 3494 { 3495 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3496 u8 vic; 3497 3498 if (!to_match->clock) 3499 return 0; 3500 3501 if (to_match->picture_aspect_ratio) 3502 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3503 3504 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3505 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3506 unsigned int clock1, clock2; 3507 3508 /* Check both 60Hz and 59.94Hz */ 3509 clock1 = cea_mode.clock; 3510 clock2 = cea_mode_alternate_clock(&cea_mode); 3511 3512 if (abs(to_match->clock - clock1) > clock_tolerance && 3513 abs(to_match->clock - clock2) > clock_tolerance) 3514 continue; 3515 3516 do { 3517 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3518 return vic; 3519 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3520 } 3521 3522 return 0; 3523 } 3524 3525 /** 3526 * drm_match_cea_mode - look for a CEA mode matching given mode 3527 * @to_match: display mode 3528 * 3529 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3530 * mode. 3531 */ 3532 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3533 { 3534 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3535 u8 vic; 3536 3537 if (!to_match->clock) 3538 return 0; 3539 3540 if (to_match->picture_aspect_ratio) 3541 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3542 3543 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3544 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3545 unsigned int clock1, clock2; 3546 3547 /* Check both 60Hz and 59.94Hz */ 3548 clock1 = cea_mode.clock; 3549 clock2 = cea_mode_alternate_clock(&cea_mode); 3550 3551 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3552 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3553 continue; 3554 3555 do { 3556 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3557 return vic; 3558 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3559 } 3560 3561 return 0; 3562 } 3563 EXPORT_SYMBOL(drm_match_cea_mode); 3564 3565 static bool drm_valid_cea_vic(u8 vic) 3566 { 3567 return cea_mode_for_vic(vic) != NULL; 3568 } 3569 3570 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3571 { 3572 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3573 3574 if (mode) 3575 return mode->picture_aspect_ratio; 3576 3577 return HDMI_PICTURE_ASPECT_NONE; 3578 } 3579 3580 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3581 { 3582 return edid_4k_modes[video_code].picture_aspect_ratio; 3583 } 3584 3585 /* 3586 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3587 * specific block). 3588 */ 3589 static unsigned int 3590 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3591 { 3592 return cea_mode_alternate_clock(hdmi_mode); 3593 } 3594 3595 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3596 unsigned int clock_tolerance) 3597 { 3598 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3599 u8 vic; 3600 3601 if (!to_match->clock) 3602 return 0; 3603 3604 if (to_match->picture_aspect_ratio) 3605 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3606 3607 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3608 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3609 unsigned int clock1, clock2; 3610 3611 /* Make sure to also match alternate clocks */ 3612 clock1 = hdmi_mode->clock; 3613 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3614 3615 if (abs(to_match->clock - clock1) > clock_tolerance && 3616 abs(to_match->clock - clock2) > clock_tolerance) 3617 continue; 3618 3619 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3620 return vic; 3621 } 3622 3623 return 0; 3624 } 3625 3626 /* 3627 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3628 * @to_match: display mode 3629 * 3630 * An HDMI mode is one defined in the HDMI vendor specific block. 3631 * 3632 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3633 */ 3634 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3635 { 3636 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3637 u8 vic; 3638 3639 if (!to_match->clock) 3640 return 0; 3641 3642 if (to_match->picture_aspect_ratio) 3643 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3644 3645 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3646 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3647 unsigned int clock1, clock2; 3648 3649 /* Make sure to also match alternate clocks */ 3650 clock1 = hdmi_mode->clock; 3651 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3652 3653 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3654 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3655 drm_mode_match(to_match, hdmi_mode, match_flags)) 3656 return vic; 3657 } 3658 return 0; 3659 } 3660 3661 static bool drm_valid_hdmi_vic(u8 vic) 3662 { 3663 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3664 } 3665 3666 static int 3667 add_alternate_cea_modes(struct drm_connector *connector, const struct edid *edid) 3668 { 3669 struct drm_device *dev = connector->dev; 3670 struct drm_display_mode *mode, *tmp; 3671 LIST_HEAD(list); 3672 int modes = 0; 3673 3674 /* Don't add CEA modes if the CEA extension block is missing */ 3675 if (!drm_find_cea_extension(edid)) 3676 return 0; 3677 3678 /* 3679 * Go through all probed modes and create a new mode 3680 * with the alternate clock for certain CEA modes. 3681 */ 3682 list_for_each_entry(mode, &connector->probed_modes, head) { 3683 const struct drm_display_mode *cea_mode = NULL; 3684 struct drm_display_mode *newmode; 3685 u8 vic = drm_match_cea_mode(mode); 3686 unsigned int clock1, clock2; 3687 3688 if (drm_valid_cea_vic(vic)) { 3689 cea_mode = cea_mode_for_vic(vic); 3690 clock2 = cea_mode_alternate_clock(cea_mode); 3691 } else { 3692 vic = drm_match_hdmi_mode(mode); 3693 if (drm_valid_hdmi_vic(vic)) { 3694 cea_mode = &edid_4k_modes[vic]; 3695 clock2 = hdmi_mode_alternate_clock(cea_mode); 3696 } 3697 } 3698 3699 if (!cea_mode) 3700 continue; 3701 3702 clock1 = cea_mode->clock; 3703 3704 if (clock1 == clock2) 3705 continue; 3706 3707 if (mode->clock != clock1 && mode->clock != clock2) 3708 continue; 3709 3710 newmode = drm_mode_duplicate(dev, cea_mode); 3711 if (!newmode) 3712 continue; 3713 3714 /* Carry over the stereo flags */ 3715 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3716 3717 /* 3718 * The current mode could be either variant. Make 3719 * sure to pick the "other" clock for the new mode. 3720 */ 3721 if (mode->clock != clock1) 3722 newmode->clock = clock1; 3723 else 3724 newmode->clock = clock2; 3725 3726 list_add_tail(&newmode->head, &list); 3727 } 3728 3729 list_for_each_entry_safe(mode, tmp, &list, head) { 3730 list_del(&mode->head); 3731 drm_mode_probed_add(connector, mode); 3732 modes++; 3733 } 3734 3735 return modes; 3736 } 3737 3738 static u8 svd_to_vic(u8 svd) 3739 { 3740 /* 0-6 bit vic, 7th bit native mode indicator */ 3741 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3742 return svd & 127; 3743 3744 return svd; 3745 } 3746 3747 static struct drm_display_mode * 3748 drm_display_mode_from_vic_index(struct drm_connector *connector, 3749 const u8 *video_db, u8 video_len, 3750 u8 video_index) 3751 { 3752 struct drm_device *dev = connector->dev; 3753 struct drm_display_mode *newmode; 3754 u8 vic; 3755 3756 if (video_db == NULL || video_index >= video_len) 3757 return NULL; 3758 3759 /* CEA modes are numbered 1..127 */ 3760 vic = svd_to_vic(video_db[video_index]); 3761 if (!drm_valid_cea_vic(vic)) 3762 return NULL; 3763 3764 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3765 if (!newmode) 3766 return NULL; 3767 3768 return newmode; 3769 } 3770 3771 /* 3772 * do_y420vdb_modes - Parse YCBCR 420 only modes 3773 * @connector: connector corresponding to the HDMI sink 3774 * @svds: start of the data block of CEA YCBCR 420 VDB 3775 * @len: length of the CEA YCBCR 420 VDB 3776 * 3777 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3778 * which contains modes which can be supported in YCBCR 420 3779 * output format only. 3780 */ 3781 static int do_y420vdb_modes(struct drm_connector *connector, 3782 const u8 *svds, u8 svds_len) 3783 { 3784 int modes = 0, i; 3785 struct drm_device *dev = connector->dev; 3786 struct drm_display_info *info = &connector->display_info; 3787 struct drm_hdmi_info *hdmi = &info->hdmi; 3788 3789 for (i = 0; i < svds_len; i++) { 3790 u8 vic = svd_to_vic(svds[i]); 3791 struct drm_display_mode *newmode; 3792 3793 if (!drm_valid_cea_vic(vic)) 3794 continue; 3795 3796 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3797 if (!newmode) 3798 break; 3799 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3800 drm_mode_probed_add(connector, newmode); 3801 modes++; 3802 } 3803 3804 if (modes > 0) 3805 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 3806 return modes; 3807 } 3808 3809 /* 3810 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3811 * @connector: connector corresponding to the HDMI sink 3812 * @vic: CEA vic for the video mode to be added in the map 3813 * 3814 * Makes an entry for a videomode in the YCBCR 420 bitmap 3815 */ 3816 static void 3817 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3818 { 3819 u8 vic = svd_to_vic(svd); 3820 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3821 3822 if (!drm_valid_cea_vic(vic)) 3823 return; 3824 3825 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3826 } 3827 3828 /** 3829 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3830 * @dev: DRM device 3831 * @video_code: CEA VIC of the mode 3832 * 3833 * Creates a new mode matching the specified CEA VIC. 3834 * 3835 * Returns: A new drm_display_mode on success or NULL on failure 3836 */ 3837 struct drm_display_mode * 3838 drm_display_mode_from_cea_vic(struct drm_device *dev, 3839 u8 video_code) 3840 { 3841 const struct drm_display_mode *cea_mode; 3842 struct drm_display_mode *newmode; 3843 3844 cea_mode = cea_mode_for_vic(video_code); 3845 if (!cea_mode) 3846 return NULL; 3847 3848 newmode = drm_mode_duplicate(dev, cea_mode); 3849 if (!newmode) 3850 return NULL; 3851 3852 return newmode; 3853 } 3854 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3855 3856 static int 3857 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3858 { 3859 int i, modes = 0; 3860 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3861 3862 for (i = 0; i < len; i++) { 3863 struct drm_display_mode *mode; 3864 3865 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3866 if (mode) { 3867 /* 3868 * YCBCR420 capability block contains a bitmap which 3869 * gives the index of CEA modes from CEA VDB, which 3870 * can support YCBCR 420 sampling output also (apart 3871 * from RGB/YCBCR444 etc). 3872 * For example, if the bit 0 in bitmap is set, 3873 * first mode in VDB can support YCBCR420 output too. 3874 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3875 */ 3876 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3877 drm_add_cmdb_modes(connector, db[i]); 3878 3879 drm_mode_probed_add(connector, mode); 3880 modes++; 3881 } 3882 } 3883 3884 return modes; 3885 } 3886 3887 struct stereo_mandatory_mode { 3888 int width, height, vrefresh; 3889 unsigned int flags; 3890 }; 3891 3892 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3893 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3894 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3895 { 1920, 1080, 50, 3896 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3897 { 1920, 1080, 60, 3898 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3899 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3900 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3901 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3902 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3903 }; 3904 3905 static bool 3906 stereo_match_mandatory(const struct drm_display_mode *mode, 3907 const struct stereo_mandatory_mode *stereo_mode) 3908 { 3909 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3910 3911 return mode->hdisplay == stereo_mode->width && 3912 mode->vdisplay == stereo_mode->height && 3913 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3914 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3915 } 3916 3917 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3918 { 3919 struct drm_device *dev = connector->dev; 3920 const struct drm_display_mode *mode; 3921 struct list_head stereo_modes; 3922 int modes = 0, i; 3923 3924 INIT_LIST_HEAD(&stereo_modes); 3925 3926 list_for_each_entry(mode, &connector->probed_modes, head) { 3927 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3928 const struct stereo_mandatory_mode *mandatory; 3929 struct drm_display_mode *new_mode; 3930 3931 if (!stereo_match_mandatory(mode, 3932 &stereo_mandatory_modes[i])) 3933 continue; 3934 3935 mandatory = &stereo_mandatory_modes[i]; 3936 new_mode = drm_mode_duplicate(dev, mode); 3937 if (!new_mode) 3938 continue; 3939 3940 new_mode->flags |= mandatory->flags; 3941 list_add_tail(&new_mode->head, &stereo_modes); 3942 modes++; 3943 } 3944 } 3945 3946 list_splice_tail(&stereo_modes, &connector->probed_modes); 3947 3948 return modes; 3949 } 3950 3951 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3952 { 3953 struct drm_device *dev = connector->dev; 3954 struct drm_display_mode *newmode; 3955 3956 if (!drm_valid_hdmi_vic(vic)) { 3957 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3958 return 0; 3959 } 3960 3961 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3962 if (!newmode) 3963 return 0; 3964 3965 drm_mode_probed_add(connector, newmode); 3966 3967 return 1; 3968 } 3969 3970 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3971 const u8 *video_db, u8 video_len, u8 video_index) 3972 { 3973 struct drm_display_mode *newmode; 3974 int modes = 0; 3975 3976 if (structure & (1 << 0)) { 3977 newmode = drm_display_mode_from_vic_index(connector, video_db, 3978 video_len, 3979 video_index); 3980 if (newmode) { 3981 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3982 drm_mode_probed_add(connector, newmode); 3983 modes++; 3984 } 3985 } 3986 if (structure & (1 << 6)) { 3987 newmode = drm_display_mode_from_vic_index(connector, video_db, 3988 video_len, 3989 video_index); 3990 if (newmode) { 3991 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3992 drm_mode_probed_add(connector, newmode); 3993 modes++; 3994 } 3995 } 3996 if (structure & (1 << 8)) { 3997 newmode = drm_display_mode_from_vic_index(connector, video_db, 3998 video_len, 3999 video_index); 4000 if (newmode) { 4001 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4002 drm_mode_probed_add(connector, newmode); 4003 modes++; 4004 } 4005 } 4006 4007 return modes; 4008 } 4009 4010 /* 4011 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4012 * @connector: connector corresponding to the HDMI sink 4013 * @db: start of the CEA vendor specific block 4014 * @len: length of the CEA block payload, ie. one can access up to db[len] 4015 * 4016 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4017 * also adds the stereo 3d modes when applicable. 4018 */ 4019 static int 4020 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4021 const u8 *video_db, u8 video_len) 4022 { 4023 struct drm_display_info *info = &connector->display_info; 4024 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4025 u8 vic_len, hdmi_3d_len = 0; 4026 u16 mask; 4027 u16 structure_all; 4028 4029 if (len < 8) 4030 goto out; 4031 4032 /* no HDMI_Video_Present */ 4033 if (!(db[8] & (1 << 5))) 4034 goto out; 4035 4036 /* Latency_Fields_Present */ 4037 if (db[8] & (1 << 7)) 4038 offset += 2; 4039 4040 /* I_Latency_Fields_Present */ 4041 if (db[8] & (1 << 6)) 4042 offset += 2; 4043 4044 /* the declared length is not long enough for the 2 first bytes 4045 * of additional video format capabilities */ 4046 if (len < (8 + offset + 2)) 4047 goto out; 4048 4049 /* 3D_Present */ 4050 offset++; 4051 if (db[8 + offset] & (1 << 7)) { 4052 modes += add_hdmi_mandatory_stereo_modes(connector); 4053 4054 /* 3D_Multi_present */ 4055 multi_present = (db[8 + offset] & 0x60) >> 5; 4056 } 4057 4058 offset++; 4059 vic_len = db[8 + offset] >> 5; 4060 hdmi_3d_len = db[8 + offset] & 0x1f; 4061 4062 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4063 u8 vic; 4064 4065 vic = db[9 + offset + i]; 4066 modes += add_hdmi_mode(connector, vic); 4067 } 4068 offset += 1 + vic_len; 4069 4070 if (multi_present == 1) 4071 multi_len = 2; 4072 else if (multi_present == 2) 4073 multi_len = 4; 4074 else 4075 multi_len = 0; 4076 4077 if (len < (8 + offset + hdmi_3d_len - 1)) 4078 goto out; 4079 4080 if (hdmi_3d_len < multi_len) 4081 goto out; 4082 4083 if (multi_present == 1 || multi_present == 2) { 4084 /* 3D_Structure_ALL */ 4085 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4086 4087 /* check if 3D_MASK is present */ 4088 if (multi_present == 2) 4089 mask = (db[10 + offset] << 8) | db[11 + offset]; 4090 else 4091 mask = 0xffff; 4092 4093 for (i = 0; i < 16; i++) { 4094 if (mask & (1 << i)) 4095 modes += add_3d_struct_modes(connector, 4096 structure_all, 4097 video_db, 4098 video_len, i); 4099 } 4100 } 4101 4102 offset += multi_len; 4103 4104 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4105 int vic_index; 4106 struct drm_display_mode *newmode = NULL; 4107 unsigned int newflag = 0; 4108 bool detail_present; 4109 4110 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4111 4112 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4113 break; 4114 4115 /* 2D_VIC_order_X */ 4116 vic_index = db[8 + offset + i] >> 4; 4117 4118 /* 3D_Structure_X */ 4119 switch (db[8 + offset + i] & 0x0f) { 4120 case 0: 4121 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4122 break; 4123 case 6: 4124 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4125 break; 4126 case 8: 4127 /* 3D_Detail_X */ 4128 if ((db[9 + offset + i] >> 4) == 1) 4129 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4130 break; 4131 } 4132 4133 if (newflag != 0) { 4134 newmode = drm_display_mode_from_vic_index(connector, 4135 video_db, 4136 video_len, 4137 vic_index); 4138 4139 if (newmode) { 4140 newmode->flags |= newflag; 4141 drm_mode_probed_add(connector, newmode); 4142 modes++; 4143 } 4144 } 4145 4146 if (detail_present) 4147 i++; 4148 } 4149 4150 out: 4151 if (modes > 0) 4152 info->has_hdmi_infoframe = true; 4153 return modes; 4154 } 4155 4156 static int 4157 cea_db_payload_len(const u8 *db) 4158 { 4159 return db[0] & 0x1f; 4160 } 4161 4162 static int 4163 cea_db_extended_tag(const u8 *db) 4164 { 4165 return db[1]; 4166 } 4167 4168 static int 4169 cea_db_tag(const u8 *db) 4170 { 4171 return db[0] >> 5; 4172 } 4173 4174 static int 4175 cea_revision(const u8 *cea) 4176 { 4177 /* 4178 * FIXME is this correct for the DispID variant? 4179 * The DispID spec doesn't really specify whether 4180 * this is the revision of the CEA extension or 4181 * the DispID CEA data block. And the only value 4182 * given as an example is 0. 4183 */ 4184 return cea[1]; 4185 } 4186 4187 static int 4188 cea_db_offsets(const u8 *cea, int *start, int *end) 4189 { 4190 /* DisplayID CTA extension blocks and top-level CEA EDID 4191 * block header definitions differ in the following bytes: 4192 * 1) Byte 2 of the header specifies length differently, 4193 * 2) Byte 3 is only present in the CEA top level block. 4194 * 4195 * The different definitions for byte 2 follow. 4196 * 4197 * DisplayID CTA extension block defines byte 2 as: 4198 * Number of payload bytes 4199 * 4200 * CEA EDID block defines byte 2 as: 4201 * Byte number (decimal) within this block where the 18-byte 4202 * DTDs begin. If no non-DTD data is present in this extension 4203 * block, the value should be set to 04h (the byte after next). 4204 * If set to 00h, there are no DTDs present in this block and 4205 * no non-DTD data. 4206 */ 4207 if (cea[0] == DATA_BLOCK_CTA) { 4208 /* 4209 * for_each_displayid_db() has already verified 4210 * that these stay within expected bounds. 4211 */ 4212 *start = 3; 4213 *end = *start + cea[2]; 4214 } else if (cea[0] == CEA_EXT) { 4215 /* Data block offset in CEA extension block */ 4216 *start = 4; 4217 *end = cea[2]; 4218 if (*end == 0) 4219 *end = 127; 4220 if (*end < 4 || *end > 127) 4221 return -ERANGE; 4222 } else { 4223 return -EOPNOTSUPP; 4224 } 4225 4226 return 0; 4227 } 4228 4229 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4230 { 4231 if (cea_db_tag(db) != VENDOR_BLOCK) 4232 return false; 4233 4234 if (cea_db_payload_len(db) < 5) 4235 return false; 4236 4237 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI; 4238 } 4239 4240 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4241 { 4242 if (cea_db_tag(db) != VENDOR_BLOCK) 4243 return false; 4244 4245 if (cea_db_payload_len(db) < 7) 4246 return false; 4247 4248 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI; 4249 } 4250 4251 static bool cea_db_is_microsoft_vsdb(const u8 *db) 4252 { 4253 if (cea_db_tag(db) != VENDOR_BLOCK) 4254 return false; 4255 4256 if (cea_db_payload_len(db) != 21) 4257 return false; 4258 4259 return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI; 4260 } 4261 4262 static bool cea_db_is_vcdb(const u8 *db) 4263 { 4264 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4265 return false; 4266 4267 if (cea_db_payload_len(db) != 2) 4268 return false; 4269 4270 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4271 return false; 4272 4273 return true; 4274 } 4275 4276 static bool cea_db_is_y420cmdb(const u8 *db) 4277 { 4278 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4279 return false; 4280 4281 if (!cea_db_payload_len(db)) 4282 return false; 4283 4284 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4285 return false; 4286 4287 return true; 4288 } 4289 4290 static bool cea_db_is_y420vdb(const u8 *db) 4291 { 4292 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4293 return false; 4294 4295 if (!cea_db_payload_len(db)) 4296 return false; 4297 4298 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4299 return false; 4300 4301 return true; 4302 } 4303 4304 #define for_each_cea_db(cea, i, start, end) \ 4305 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4306 4307 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4308 const u8 *db) 4309 { 4310 struct drm_display_info *info = &connector->display_info; 4311 struct drm_hdmi_info *hdmi = &info->hdmi; 4312 u8 map_len = cea_db_payload_len(db) - 1; 4313 u8 count; 4314 u64 map = 0; 4315 4316 if (map_len == 0) { 4317 /* All CEA modes support ycbcr420 sampling also.*/ 4318 hdmi->y420_cmdb_map = U64_MAX; 4319 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4320 return; 4321 } 4322 4323 /* 4324 * This map indicates which of the existing CEA block modes 4325 * from VDB can support YCBCR420 output too. So if bit=0 is 4326 * set, first mode from VDB can support YCBCR420 output too. 4327 * We will parse and keep this map, before parsing VDB itself 4328 * to avoid going through the same block again and again. 4329 * 4330 * Spec is not clear about max possible size of this block. 4331 * Clamping max bitmap block size at 8 bytes. Every byte can 4332 * address 8 CEA modes, in this way this map can address 4333 * 8*8 = first 64 SVDs. 4334 */ 4335 if (WARN_ON_ONCE(map_len > 8)) 4336 map_len = 8; 4337 4338 for (count = 0; count < map_len; count++) 4339 map |= (u64)db[2 + count] << (8 * count); 4340 4341 if (map) 4342 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4343 4344 hdmi->y420_cmdb_map = map; 4345 } 4346 4347 static int 4348 add_cea_modes(struct drm_connector *connector, const struct edid *edid) 4349 { 4350 const u8 *cea = drm_find_cea_extension(edid); 4351 const u8 *db, *hdmi = NULL, *video = NULL; 4352 u8 dbl, hdmi_len, video_len = 0; 4353 int modes = 0; 4354 4355 if (cea && cea_revision(cea) >= 3) { 4356 int i, start, end; 4357 4358 if (cea_db_offsets(cea, &start, &end)) 4359 return 0; 4360 4361 for_each_cea_db(cea, i, start, end) { 4362 db = &cea[i]; 4363 dbl = cea_db_payload_len(db); 4364 4365 if (cea_db_tag(db) == VIDEO_BLOCK) { 4366 video = db + 1; 4367 video_len = dbl; 4368 modes += do_cea_modes(connector, video, dbl); 4369 } else if (cea_db_is_hdmi_vsdb(db)) { 4370 hdmi = db; 4371 hdmi_len = dbl; 4372 } else if (cea_db_is_y420vdb(db)) { 4373 const u8 *vdb420 = &db[2]; 4374 4375 /* Add 4:2:0(only) modes present in EDID */ 4376 modes += do_y420vdb_modes(connector, 4377 vdb420, 4378 dbl - 1); 4379 } 4380 } 4381 } 4382 4383 /* 4384 * We parse the HDMI VSDB after having added the cea modes as we will 4385 * be patching their flags when the sink supports stereo 3D. 4386 */ 4387 if (hdmi) 4388 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4389 video_len); 4390 4391 return modes; 4392 } 4393 4394 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4395 { 4396 const struct drm_display_mode *cea_mode; 4397 int clock1, clock2, clock; 4398 u8 vic; 4399 const char *type; 4400 4401 /* 4402 * allow 5kHz clock difference either way to account for 4403 * the 10kHz clock resolution limit of detailed timings. 4404 */ 4405 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4406 if (drm_valid_cea_vic(vic)) { 4407 type = "CEA"; 4408 cea_mode = cea_mode_for_vic(vic); 4409 clock1 = cea_mode->clock; 4410 clock2 = cea_mode_alternate_clock(cea_mode); 4411 } else { 4412 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4413 if (drm_valid_hdmi_vic(vic)) { 4414 type = "HDMI"; 4415 cea_mode = &edid_4k_modes[vic]; 4416 clock1 = cea_mode->clock; 4417 clock2 = hdmi_mode_alternate_clock(cea_mode); 4418 } else { 4419 return; 4420 } 4421 } 4422 4423 /* pick whichever is closest */ 4424 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4425 clock = clock1; 4426 else 4427 clock = clock2; 4428 4429 if (mode->clock == clock) 4430 return; 4431 4432 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4433 type, vic, mode->clock, clock); 4434 mode->clock = clock; 4435 } 4436 4437 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4438 { 4439 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4440 return false; 4441 4442 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4443 return false; 4444 4445 if (cea_db_payload_len(db) < 3) 4446 return false; 4447 4448 return true; 4449 } 4450 4451 static uint8_t eotf_supported(const u8 *edid_ext) 4452 { 4453 return edid_ext[2] & 4454 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4455 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4456 BIT(HDMI_EOTF_SMPTE_ST2084) | 4457 BIT(HDMI_EOTF_BT_2100_HLG)); 4458 } 4459 4460 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4461 { 4462 return edid_ext[3] & 4463 BIT(HDMI_STATIC_METADATA_TYPE1); 4464 } 4465 4466 static void 4467 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4468 { 4469 u16 len; 4470 4471 len = cea_db_payload_len(db); 4472 4473 connector->hdr_sink_metadata.hdmi_type1.eotf = 4474 eotf_supported(db); 4475 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4476 hdr_metadata_type(db); 4477 4478 if (len >= 4) 4479 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4480 if (len >= 5) 4481 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4482 if (len >= 6) 4483 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4484 } 4485 4486 static void 4487 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4488 { 4489 u8 len = cea_db_payload_len(db); 4490 4491 if (len >= 6 && (db[6] & (1 << 7))) 4492 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4493 if (len >= 8) { 4494 connector->latency_present[0] = db[8] >> 7; 4495 connector->latency_present[1] = (db[8] >> 6) & 1; 4496 } 4497 if (len >= 9) 4498 connector->video_latency[0] = db[9]; 4499 if (len >= 10) 4500 connector->audio_latency[0] = db[10]; 4501 if (len >= 11) 4502 connector->video_latency[1] = db[11]; 4503 if (len >= 12) 4504 connector->audio_latency[1] = db[12]; 4505 4506 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4507 "video latency %d %d, " 4508 "audio latency %d %d\n", 4509 connector->latency_present[0], 4510 connector->latency_present[1], 4511 connector->video_latency[0], 4512 connector->video_latency[1], 4513 connector->audio_latency[0], 4514 connector->audio_latency[1]); 4515 } 4516 4517 static void 4518 monitor_name(const struct detailed_timing *timing, void *data) 4519 { 4520 const char **res = data; 4521 4522 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 4523 return; 4524 4525 *res = timing->data.other_data.data.str.str; 4526 } 4527 4528 static int get_monitor_name(const struct edid *edid, char name[13]) 4529 { 4530 const char *edid_name = NULL; 4531 int mnl; 4532 4533 if (!edid || !name) 4534 return 0; 4535 4536 drm_for_each_detailed_block(edid, monitor_name, &edid_name); 4537 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4538 if (edid_name[mnl] == 0x0a) 4539 break; 4540 4541 name[mnl] = edid_name[mnl]; 4542 } 4543 4544 return mnl; 4545 } 4546 4547 /** 4548 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4549 * @edid: monitor EDID information 4550 * @name: pointer to a character array to hold the name of the monitor 4551 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4552 * 4553 */ 4554 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 4555 { 4556 int name_length; 4557 char buf[13]; 4558 4559 if (bufsize <= 0) 4560 return; 4561 4562 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4563 memcpy(name, buf, name_length); 4564 name[name_length] = '\0'; 4565 } 4566 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4567 4568 static void clear_eld(struct drm_connector *connector) 4569 { 4570 memset(connector->eld, 0, sizeof(connector->eld)); 4571 4572 connector->latency_present[0] = false; 4573 connector->latency_present[1] = false; 4574 connector->video_latency[0] = 0; 4575 connector->audio_latency[0] = 0; 4576 connector->video_latency[1] = 0; 4577 connector->audio_latency[1] = 0; 4578 } 4579 4580 /* 4581 * drm_edid_to_eld - build ELD from EDID 4582 * @connector: connector corresponding to the HDMI/DP sink 4583 * @edid: EDID to parse 4584 * 4585 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4586 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4587 */ 4588 static void drm_edid_to_eld(struct drm_connector *connector, 4589 const struct edid *edid) 4590 { 4591 uint8_t *eld = connector->eld; 4592 const u8 *cea; 4593 const u8 *db; 4594 int total_sad_count = 0; 4595 int mnl; 4596 int dbl; 4597 4598 clear_eld(connector); 4599 4600 if (!edid) 4601 return; 4602 4603 cea = drm_find_cea_extension(edid); 4604 if (!cea) { 4605 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4606 return; 4607 } 4608 4609 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4610 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4611 4612 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4613 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4614 4615 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4616 4617 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4618 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4619 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4620 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4621 4622 if (cea_revision(cea) >= 3) { 4623 int i, start, end; 4624 int sad_count; 4625 4626 if (cea_db_offsets(cea, &start, &end)) { 4627 start = 0; 4628 end = 0; 4629 } 4630 4631 for_each_cea_db(cea, i, start, end) { 4632 db = &cea[i]; 4633 dbl = cea_db_payload_len(db); 4634 4635 switch (cea_db_tag(db)) { 4636 case AUDIO_BLOCK: 4637 /* Audio Data Block, contains SADs */ 4638 sad_count = min(dbl / 3, 15 - total_sad_count); 4639 if (sad_count >= 1) 4640 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4641 &db[1], sad_count * 3); 4642 total_sad_count += sad_count; 4643 break; 4644 case SPEAKER_BLOCK: 4645 /* Speaker Allocation Data Block */ 4646 if (dbl >= 1) 4647 eld[DRM_ELD_SPEAKER] = db[1]; 4648 break; 4649 case VENDOR_BLOCK: 4650 /* HDMI Vendor-Specific Data Block */ 4651 if (cea_db_is_hdmi_vsdb(db)) 4652 drm_parse_hdmi_vsdb_audio(connector, db); 4653 break; 4654 default: 4655 break; 4656 } 4657 } 4658 } 4659 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4660 4661 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4662 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4663 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4664 else 4665 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4666 4667 eld[DRM_ELD_BASELINE_ELD_LEN] = 4668 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4669 4670 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4671 drm_eld_size(eld), total_sad_count); 4672 } 4673 4674 /** 4675 * drm_edid_to_sad - extracts SADs from EDID 4676 * @edid: EDID to parse 4677 * @sads: pointer that will be set to the extracted SADs 4678 * 4679 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4680 * 4681 * Note: The returned pointer needs to be freed using kfree(). 4682 * 4683 * Return: The number of found SADs or negative number on error. 4684 */ 4685 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 4686 { 4687 int count = 0; 4688 int i, start, end, dbl; 4689 const u8 *cea; 4690 4691 cea = drm_find_cea_extension(edid); 4692 if (!cea) { 4693 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4694 return 0; 4695 } 4696 4697 if (cea_revision(cea) < 3) { 4698 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4699 return 0; 4700 } 4701 4702 if (cea_db_offsets(cea, &start, &end)) { 4703 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4704 return -EPROTO; 4705 } 4706 4707 for_each_cea_db(cea, i, start, end) { 4708 const u8 *db = &cea[i]; 4709 4710 if (cea_db_tag(db) == AUDIO_BLOCK) { 4711 int j; 4712 4713 dbl = cea_db_payload_len(db); 4714 4715 count = dbl / 3; /* SAD is 3B */ 4716 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4717 if (!*sads) 4718 return -ENOMEM; 4719 for (j = 0; j < count; j++) { 4720 const u8 *sad = &db[1 + j * 3]; 4721 4722 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4723 (*sads)[j].channels = sad[0] & 0x7; 4724 (*sads)[j].freq = sad[1] & 0x7F; 4725 (*sads)[j].byte2 = sad[2]; 4726 } 4727 break; 4728 } 4729 } 4730 4731 return count; 4732 } 4733 EXPORT_SYMBOL(drm_edid_to_sad); 4734 4735 /** 4736 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4737 * @edid: EDID to parse 4738 * @sadb: pointer to the speaker block 4739 * 4740 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4741 * 4742 * Note: The returned pointer needs to be freed using kfree(). 4743 * 4744 * Return: The number of found Speaker Allocation Blocks or negative number on 4745 * error. 4746 */ 4747 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 4748 { 4749 int count = 0; 4750 int i, start, end, dbl; 4751 const u8 *cea; 4752 4753 cea = drm_find_cea_extension(edid); 4754 if (!cea) { 4755 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4756 return 0; 4757 } 4758 4759 if (cea_revision(cea) < 3) { 4760 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4761 return 0; 4762 } 4763 4764 if (cea_db_offsets(cea, &start, &end)) { 4765 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4766 return -EPROTO; 4767 } 4768 4769 for_each_cea_db(cea, i, start, end) { 4770 const u8 *db = &cea[i]; 4771 4772 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4773 dbl = cea_db_payload_len(db); 4774 4775 /* Speaker Allocation Data Block */ 4776 if (dbl == 3) { 4777 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4778 if (!*sadb) 4779 return -ENOMEM; 4780 count = dbl; 4781 break; 4782 } 4783 } 4784 } 4785 4786 return count; 4787 } 4788 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4789 4790 /** 4791 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4792 * @connector: connector associated with the HDMI/DP sink 4793 * @mode: the display mode 4794 * 4795 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4796 * the sink doesn't support audio or video. 4797 */ 4798 int drm_av_sync_delay(struct drm_connector *connector, 4799 const struct drm_display_mode *mode) 4800 { 4801 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4802 int a, v; 4803 4804 if (!connector->latency_present[0]) 4805 return 0; 4806 if (!connector->latency_present[1]) 4807 i = 0; 4808 4809 a = connector->audio_latency[i]; 4810 v = connector->video_latency[i]; 4811 4812 /* 4813 * HDMI/DP sink doesn't support audio or video? 4814 */ 4815 if (a == 255 || v == 255) 4816 return 0; 4817 4818 /* 4819 * Convert raw EDID values to millisecond. 4820 * Treat unknown latency as 0ms. 4821 */ 4822 if (a) 4823 a = min(2 * (a - 1), 500); 4824 if (v) 4825 v = min(2 * (v - 1), 500); 4826 4827 return max(v - a, 0); 4828 } 4829 EXPORT_SYMBOL(drm_av_sync_delay); 4830 4831 /** 4832 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4833 * @edid: monitor EDID information 4834 * 4835 * Parse the CEA extension according to CEA-861-B. 4836 * 4837 * Drivers that have added the modes parsed from EDID to drm_display_info 4838 * should use &drm_display_info.is_hdmi instead of calling this function. 4839 * 4840 * Return: True if the monitor is HDMI, false if not or unknown. 4841 */ 4842 bool drm_detect_hdmi_monitor(const struct edid *edid) 4843 { 4844 const u8 *edid_ext; 4845 int i; 4846 int start_offset, end_offset; 4847 4848 edid_ext = drm_find_cea_extension(edid); 4849 if (!edid_ext) 4850 return false; 4851 4852 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4853 return false; 4854 4855 /* 4856 * Because HDMI identifier is in Vendor Specific Block, 4857 * search it from all data blocks of CEA extension. 4858 */ 4859 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4860 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4861 return true; 4862 } 4863 4864 return false; 4865 } 4866 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4867 4868 /** 4869 * drm_detect_monitor_audio - check monitor audio capability 4870 * @edid: EDID block to scan 4871 * 4872 * Monitor should have CEA extension block. 4873 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4874 * audio' only. If there is any audio extension block and supported 4875 * audio format, assume at least 'basic audio' support, even if 'basic 4876 * audio' is not defined in EDID. 4877 * 4878 * Return: True if the monitor supports audio, false otherwise. 4879 */ 4880 bool drm_detect_monitor_audio(const struct edid *edid) 4881 { 4882 const u8 *edid_ext; 4883 int i, j; 4884 bool has_audio = false; 4885 int start_offset, end_offset; 4886 4887 edid_ext = drm_find_cea_extension(edid); 4888 if (!edid_ext) 4889 goto end; 4890 4891 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4892 4893 if (has_audio) { 4894 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4895 goto end; 4896 } 4897 4898 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4899 goto end; 4900 4901 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4902 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4903 has_audio = true; 4904 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4905 DRM_DEBUG_KMS("CEA audio format %d\n", 4906 (edid_ext[i + j] >> 3) & 0xf); 4907 goto end; 4908 } 4909 } 4910 end: 4911 return has_audio; 4912 } 4913 EXPORT_SYMBOL(drm_detect_monitor_audio); 4914 4915 4916 /** 4917 * drm_default_rgb_quant_range - default RGB quantization range 4918 * @mode: display mode 4919 * 4920 * Determine the default RGB quantization range for the mode, 4921 * as specified in CEA-861. 4922 * 4923 * Return: The default RGB quantization range for the mode 4924 */ 4925 enum hdmi_quantization_range 4926 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4927 { 4928 /* All CEA modes other than VIC 1 use limited quantization range. */ 4929 return drm_match_cea_mode(mode) > 1 ? 4930 HDMI_QUANTIZATION_RANGE_LIMITED : 4931 HDMI_QUANTIZATION_RANGE_FULL; 4932 } 4933 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4934 4935 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4936 { 4937 struct drm_display_info *info = &connector->display_info; 4938 4939 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4940 4941 if (db[2] & EDID_CEA_VCDB_QS) 4942 info->rgb_quant_range_selectable = true; 4943 } 4944 4945 static 4946 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 4947 { 4948 switch (max_frl_rate) { 4949 case 1: 4950 *max_lanes = 3; 4951 *max_rate_per_lane = 3; 4952 break; 4953 case 2: 4954 *max_lanes = 3; 4955 *max_rate_per_lane = 6; 4956 break; 4957 case 3: 4958 *max_lanes = 4; 4959 *max_rate_per_lane = 6; 4960 break; 4961 case 4: 4962 *max_lanes = 4; 4963 *max_rate_per_lane = 8; 4964 break; 4965 case 5: 4966 *max_lanes = 4; 4967 *max_rate_per_lane = 10; 4968 break; 4969 case 6: 4970 *max_lanes = 4; 4971 *max_rate_per_lane = 12; 4972 break; 4973 case 0: 4974 default: 4975 *max_lanes = 0; 4976 *max_rate_per_lane = 0; 4977 } 4978 } 4979 4980 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4981 const u8 *db) 4982 { 4983 u8 dc_mask; 4984 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4985 4986 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4987 hdmi->y420_dc_modes = dc_mask; 4988 } 4989 4990 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4991 const u8 *hf_vsdb) 4992 { 4993 struct drm_display_info *display = &connector->display_info; 4994 struct drm_hdmi_info *hdmi = &display->hdmi; 4995 4996 display->has_hdmi_infoframe = true; 4997 4998 if (hf_vsdb[6] & 0x80) { 4999 hdmi->scdc.supported = true; 5000 if (hf_vsdb[6] & 0x40) 5001 hdmi->scdc.read_request = true; 5002 } 5003 5004 /* 5005 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 5006 * And as per the spec, three factors confirm this: 5007 * * Availability of a HF-VSDB block in EDID (check) 5008 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 5009 * * SCDC support available (let's check) 5010 * Lets check it out. 5011 */ 5012 5013 if (hf_vsdb[5]) { 5014 /* max clock is 5000 KHz times block value */ 5015 u32 max_tmds_clock = hf_vsdb[5] * 5000; 5016 struct drm_scdc *scdc = &hdmi->scdc; 5017 5018 if (max_tmds_clock > 340000) { 5019 display->max_tmds_clock = max_tmds_clock; 5020 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 5021 display->max_tmds_clock); 5022 } 5023 5024 if (scdc->supported) { 5025 scdc->scrambling.supported = true; 5026 5027 /* Few sinks support scrambling for clocks < 340M */ 5028 if ((hf_vsdb[6] & 0x8)) 5029 scdc->scrambling.low_rates = true; 5030 } 5031 } 5032 5033 if (hf_vsdb[7]) { 5034 u8 max_frl_rate; 5035 u8 dsc_max_frl_rate; 5036 u8 dsc_max_slices; 5037 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5038 5039 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 5040 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 5041 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 5042 &hdmi->max_frl_rate_per_lane); 5043 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 5044 5045 if (hdmi_dsc->v_1p2) { 5046 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 5047 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 5048 5049 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 5050 hdmi_dsc->bpc_supported = 16; 5051 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 5052 hdmi_dsc->bpc_supported = 12; 5053 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 5054 hdmi_dsc->bpc_supported = 10; 5055 else 5056 hdmi_dsc->bpc_supported = 0; 5057 5058 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5059 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5060 &hdmi_dsc->max_frl_rate_per_lane); 5061 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5062 5063 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 5064 switch (dsc_max_slices) { 5065 case 1: 5066 hdmi_dsc->max_slices = 1; 5067 hdmi_dsc->clk_per_slice = 340; 5068 break; 5069 case 2: 5070 hdmi_dsc->max_slices = 2; 5071 hdmi_dsc->clk_per_slice = 340; 5072 break; 5073 case 3: 5074 hdmi_dsc->max_slices = 4; 5075 hdmi_dsc->clk_per_slice = 340; 5076 break; 5077 case 4: 5078 hdmi_dsc->max_slices = 8; 5079 hdmi_dsc->clk_per_slice = 340; 5080 break; 5081 case 5: 5082 hdmi_dsc->max_slices = 8; 5083 hdmi_dsc->clk_per_slice = 400; 5084 break; 5085 case 6: 5086 hdmi_dsc->max_slices = 12; 5087 hdmi_dsc->clk_per_slice = 400; 5088 break; 5089 case 7: 5090 hdmi_dsc->max_slices = 16; 5091 hdmi_dsc->clk_per_slice = 400; 5092 break; 5093 case 0: 5094 default: 5095 hdmi_dsc->max_slices = 0; 5096 hdmi_dsc->clk_per_slice = 0; 5097 } 5098 } 5099 } 5100 5101 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 5102 } 5103 5104 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5105 const u8 *hdmi) 5106 { 5107 struct drm_display_info *info = &connector->display_info; 5108 unsigned int dc_bpc = 0; 5109 5110 /* HDMI supports at least 8 bpc */ 5111 info->bpc = 8; 5112 5113 if (cea_db_payload_len(hdmi) < 6) 5114 return; 5115 5116 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5117 dc_bpc = 10; 5118 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5119 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5120 connector->name); 5121 } 5122 5123 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5124 dc_bpc = 12; 5125 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5126 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5127 connector->name); 5128 } 5129 5130 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5131 dc_bpc = 16; 5132 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5133 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5134 connector->name); 5135 } 5136 5137 if (dc_bpc == 0) { 5138 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5139 connector->name); 5140 return; 5141 } 5142 5143 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5144 connector->name, dc_bpc); 5145 info->bpc = dc_bpc; 5146 5147 /* YCRCB444 is optional according to spec. */ 5148 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5149 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5150 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5151 connector->name); 5152 } 5153 5154 /* 5155 * Spec says that if any deep color mode is supported at all, 5156 * then deep color 36 bit must be supported. 5157 */ 5158 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5159 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5160 connector->name); 5161 } 5162 } 5163 5164 static void 5165 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5166 { 5167 struct drm_display_info *info = &connector->display_info; 5168 u8 len = cea_db_payload_len(db); 5169 5170 info->is_hdmi = true; 5171 5172 if (len >= 6) 5173 info->dvi_dual = db[6] & 1; 5174 if (len >= 7) 5175 info->max_tmds_clock = db[7] * 5000; 5176 5177 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5178 "max TMDS clock %d kHz\n", 5179 info->dvi_dual, 5180 info->max_tmds_clock); 5181 5182 drm_parse_hdmi_deep_color_info(connector, db); 5183 } 5184 5185 /* 5186 * See EDID extension for head-mounted and specialized monitors, specified at: 5187 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 5188 */ 5189 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 5190 const u8 *db) 5191 { 5192 struct drm_display_info *info = &connector->display_info; 5193 u8 version = db[4]; 5194 bool desktop_usage = db[5] & BIT(6); 5195 5196 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 5197 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 5198 info->non_desktop = true; 5199 5200 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", 5201 version, db[5]); 5202 } 5203 5204 static void drm_parse_cea_ext(struct drm_connector *connector, 5205 const struct edid *edid) 5206 { 5207 struct drm_display_info *info = &connector->display_info; 5208 const u8 *edid_ext; 5209 int i, start, end; 5210 5211 edid_ext = drm_find_cea_extension(edid); 5212 if (!edid_ext) 5213 return; 5214 5215 info->cea_rev = edid_ext[1]; 5216 5217 /* The existence of a CEA block should imply RGB support */ 5218 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5219 if (edid_ext[3] & EDID_CEA_YCRCB444) 5220 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5221 if (edid_ext[3] & EDID_CEA_YCRCB422) 5222 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5223 5224 if (cea_db_offsets(edid_ext, &start, &end)) 5225 return; 5226 5227 for_each_cea_db(edid_ext, i, start, end) { 5228 const u8 *db = &edid_ext[i]; 5229 5230 if (cea_db_is_hdmi_vsdb(db)) 5231 drm_parse_hdmi_vsdb_video(connector, db); 5232 if (cea_db_is_hdmi_forum_vsdb(db)) 5233 drm_parse_hdmi_forum_vsdb(connector, db); 5234 if (cea_db_is_microsoft_vsdb(db)) 5235 drm_parse_microsoft_vsdb(connector, db); 5236 if (cea_db_is_y420cmdb(db)) 5237 drm_parse_y420cmdb_bitmap(connector, db); 5238 if (cea_db_is_vcdb(db)) 5239 drm_parse_vcdb(connector, db); 5240 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5241 drm_parse_hdr_metadata_block(connector, db); 5242 } 5243 } 5244 5245 static 5246 void get_monitor_range(const struct detailed_timing *timing, 5247 void *info_monitor_range) 5248 { 5249 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5250 const struct detailed_non_pixel *data = &timing->data.other_data; 5251 const struct detailed_data_monitor_range *range = &data->data.range; 5252 5253 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 5254 return; 5255 5256 /* 5257 * Check for flag range limits only. If flag == 1 then 5258 * no additional timing information provided. 5259 * Default GTF, GTF Secondary curve and CVT are not 5260 * supported 5261 */ 5262 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5263 return; 5264 5265 monitor_range->min_vfreq = range->min_vfreq; 5266 monitor_range->max_vfreq = range->max_vfreq; 5267 } 5268 5269 static 5270 void drm_get_monitor_range(struct drm_connector *connector, 5271 const struct edid *edid) 5272 { 5273 struct drm_display_info *info = &connector->display_info; 5274 5275 if (!version_greater(edid, 1, 1)) 5276 return; 5277 5278 drm_for_each_detailed_block(edid, get_monitor_range, 5279 &info->monitor_range); 5280 5281 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5282 info->monitor_range.min_vfreq, 5283 info->monitor_range.max_vfreq); 5284 } 5285 5286 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 5287 const struct displayid_block *block) 5288 { 5289 struct displayid_vesa_vendor_specific_block *vesa = 5290 (struct displayid_vesa_vendor_specific_block *)block; 5291 struct drm_display_info *info = &connector->display_info; 5292 5293 if (block->num_bytes < 3) { 5294 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", 5295 block->num_bytes); 5296 return; 5297 } 5298 5299 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 5300 return; 5301 5302 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 5303 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); 5304 return; 5305 } 5306 5307 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 5308 default: 5309 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); 5310 fallthrough; 5311 case 0: 5312 info->mso_stream_count = 0; 5313 break; 5314 case 1: 5315 info->mso_stream_count = 2; /* 2 or 4 links */ 5316 break; 5317 case 2: 5318 info->mso_stream_count = 4; /* 4 links */ 5319 break; 5320 } 5321 5322 if (!info->mso_stream_count) { 5323 info->mso_pixel_overlap = 0; 5324 return; 5325 } 5326 5327 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 5328 if (info->mso_pixel_overlap > 8) { 5329 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", 5330 info->mso_pixel_overlap); 5331 info->mso_pixel_overlap = 8; 5332 } 5333 5334 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", 5335 info->mso_stream_count, info->mso_pixel_overlap); 5336 } 5337 5338 static void drm_update_mso(struct drm_connector *connector, const struct edid *edid) 5339 { 5340 const struct displayid_block *block; 5341 struct displayid_iter iter; 5342 5343 displayid_iter_edid_begin(edid, &iter); 5344 displayid_iter_for_each(block, &iter) { 5345 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 5346 drm_parse_vesa_mso_data(connector, block); 5347 } 5348 displayid_iter_end(&iter); 5349 } 5350 5351 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5352 * all of the values which would have been set from EDID 5353 */ 5354 void 5355 drm_reset_display_info(struct drm_connector *connector) 5356 { 5357 struct drm_display_info *info = &connector->display_info; 5358 5359 info->width_mm = 0; 5360 info->height_mm = 0; 5361 5362 info->bpc = 0; 5363 info->color_formats = 0; 5364 info->cea_rev = 0; 5365 info->max_tmds_clock = 0; 5366 info->dvi_dual = false; 5367 info->is_hdmi = false; 5368 info->has_hdmi_infoframe = false; 5369 info->rgb_quant_range_selectable = false; 5370 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5371 5372 info->edid_hdmi_rgb444_dc_modes = 0; 5373 info->edid_hdmi_ycbcr444_dc_modes = 0; 5374 5375 info->non_desktop = 0; 5376 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5377 5378 info->mso_stream_count = 0; 5379 info->mso_pixel_overlap = 0; 5380 } 5381 5382 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5383 { 5384 struct drm_display_info *info = &connector->display_info; 5385 5386 u32 quirks = edid_get_quirks(edid); 5387 5388 drm_reset_display_info(connector); 5389 5390 info->width_mm = edid->width_cm * 10; 5391 info->height_mm = edid->height_cm * 10; 5392 5393 drm_get_monitor_range(connector, edid); 5394 5395 if (edid->revision < 3) 5396 goto out; 5397 5398 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5399 goto out; 5400 5401 drm_parse_cea_ext(connector, edid); 5402 5403 /* 5404 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5405 * 5406 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5407 * tells us to assume 8 bpc color depth if the EDID doesn't have 5408 * extensions which tell otherwise. 5409 */ 5410 if (info->bpc == 0 && edid->revision == 3 && 5411 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5412 info->bpc = 8; 5413 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5414 connector->name, info->bpc); 5415 } 5416 5417 /* Only defined for 1.4 with digital displays */ 5418 if (edid->revision < 4) 5419 goto out; 5420 5421 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5422 case DRM_EDID_DIGITAL_DEPTH_6: 5423 info->bpc = 6; 5424 break; 5425 case DRM_EDID_DIGITAL_DEPTH_8: 5426 info->bpc = 8; 5427 break; 5428 case DRM_EDID_DIGITAL_DEPTH_10: 5429 info->bpc = 10; 5430 break; 5431 case DRM_EDID_DIGITAL_DEPTH_12: 5432 info->bpc = 12; 5433 break; 5434 case DRM_EDID_DIGITAL_DEPTH_14: 5435 info->bpc = 14; 5436 break; 5437 case DRM_EDID_DIGITAL_DEPTH_16: 5438 info->bpc = 16; 5439 break; 5440 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5441 default: 5442 info->bpc = 0; 5443 break; 5444 } 5445 5446 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5447 connector->name, info->bpc); 5448 5449 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5450 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5451 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5452 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5453 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5454 5455 drm_update_mso(connector, edid); 5456 5457 out: 5458 if (quirks & EDID_QUIRK_NON_DESKTOP) { 5459 drm_dbg_kms(connector->dev, "Non-desktop display%s\n", 5460 info->non_desktop ? " (redundant quirk)" : ""); 5461 info->non_desktop = true; 5462 } 5463 5464 return quirks; 5465 } 5466 5467 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5468 struct displayid_detailed_timings_1 *timings, 5469 bool type_7) 5470 { 5471 struct drm_display_mode *mode; 5472 unsigned pixel_clock = (timings->pixel_clock[0] | 5473 (timings->pixel_clock[1] << 8) | 5474 (timings->pixel_clock[2] << 16)) + 1; 5475 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5476 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5477 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5478 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5479 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5480 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5481 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5482 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5483 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5484 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5485 5486 mode = drm_mode_create(dev); 5487 if (!mode) 5488 return NULL; 5489 5490 /* resolution is kHz for type VII, and 10 kHz for type I */ 5491 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 5492 mode->hdisplay = hactive; 5493 mode->hsync_start = mode->hdisplay + hsync; 5494 mode->hsync_end = mode->hsync_start + hsync_width; 5495 mode->htotal = mode->hdisplay + hblank; 5496 5497 mode->vdisplay = vactive; 5498 mode->vsync_start = mode->vdisplay + vsync; 5499 mode->vsync_end = mode->vsync_start + vsync_width; 5500 mode->vtotal = mode->vdisplay + vblank; 5501 5502 mode->flags = 0; 5503 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5504 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5505 mode->type = DRM_MODE_TYPE_DRIVER; 5506 5507 if (timings->flags & 0x80) 5508 mode->type |= DRM_MODE_TYPE_PREFERRED; 5509 drm_mode_set_name(mode); 5510 5511 return mode; 5512 } 5513 5514 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5515 const struct displayid_block *block) 5516 { 5517 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5518 int i; 5519 int num_timings; 5520 struct drm_display_mode *newmode; 5521 int num_modes = 0; 5522 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 5523 /* blocks must be multiple of 20 bytes length */ 5524 if (block->num_bytes % 20) 5525 return 0; 5526 5527 num_timings = block->num_bytes / 20; 5528 for (i = 0; i < num_timings; i++) { 5529 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5530 5531 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 5532 if (!newmode) 5533 continue; 5534 5535 drm_mode_probed_add(connector, newmode); 5536 num_modes++; 5537 } 5538 return num_modes; 5539 } 5540 5541 static int add_displayid_detailed_modes(struct drm_connector *connector, 5542 const struct edid *edid) 5543 { 5544 const struct displayid_block *block; 5545 struct displayid_iter iter; 5546 int num_modes = 0; 5547 5548 displayid_iter_edid_begin(edid, &iter); 5549 displayid_iter_for_each(block, &iter) { 5550 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 5551 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 5552 num_modes += add_displayid_detailed_1_modes(connector, block); 5553 } 5554 displayid_iter_end(&iter); 5555 5556 return num_modes; 5557 } 5558 5559 static int drm_edid_connector_update(struct drm_connector *connector, 5560 const struct edid *edid) 5561 { 5562 int num_modes = 0; 5563 u32 quirks; 5564 5565 if (edid == NULL) { 5566 clear_eld(connector); 5567 return 0; 5568 } 5569 5570 drm_edid_to_eld(connector, edid); 5571 5572 /* 5573 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5574 * To avoid multiple parsing of same block, lets parse that map 5575 * from sink info, before parsing CEA modes. 5576 */ 5577 quirks = drm_add_display_info(connector, edid); 5578 5579 /* 5580 * EDID spec says modes should be preferred in this order: 5581 * - preferred detailed mode 5582 * - other detailed modes from base block 5583 * - detailed modes from extension blocks 5584 * - CVT 3-byte code modes 5585 * - standard timing codes 5586 * - established timing codes 5587 * - modes inferred from GTF or CVT range information 5588 * 5589 * We get this pretty much right. 5590 * 5591 * XXX order for additional mode types in extension blocks? 5592 */ 5593 num_modes += add_detailed_modes(connector, edid, quirks); 5594 num_modes += add_cvt_modes(connector, edid); 5595 num_modes += add_standard_modes(connector, edid); 5596 num_modes += add_established_modes(connector, edid); 5597 num_modes += add_cea_modes(connector, edid); 5598 num_modes += add_alternate_cea_modes(connector, edid); 5599 num_modes += add_displayid_detailed_modes(connector, edid); 5600 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5601 num_modes += add_inferred_modes(connector, edid); 5602 5603 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5604 edid_fixup_preferred(connector, quirks); 5605 5606 if (quirks & EDID_QUIRK_FORCE_6BPC) 5607 connector->display_info.bpc = 6; 5608 5609 if (quirks & EDID_QUIRK_FORCE_8BPC) 5610 connector->display_info.bpc = 8; 5611 5612 if (quirks & EDID_QUIRK_FORCE_10BPC) 5613 connector->display_info.bpc = 10; 5614 5615 if (quirks & EDID_QUIRK_FORCE_12BPC) 5616 connector->display_info.bpc = 12; 5617 5618 return num_modes; 5619 } 5620 5621 /** 5622 * drm_add_edid_modes - add modes from EDID data, if available 5623 * @connector: connector we're probing 5624 * @edid: EDID data 5625 * 5626 * Add the specified modes to the connector's mode list. Also fills out the 5627 * &drm_display_info structure and ELD in @connector with any information which 5628 * can be derived from the edid. 5629 * 5630 * Return: The number of modes added or 0 if we couldn't find any. 5631 */ 5632 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5633 { 5634 if (edid && !drm_edid_is_valid(edid)) { 5635 drm_warn(connector->dev, "%s: EDID invalid.\n", 5636 connector->name); 5637 edid = NULL; 5638 } 5639 5640 return drm_edid_connector_update(connector, edid); 5641 } 5642 EXPORT_SYMBOL(drm_add_edid_modes); 5643 5644 /** 5645 * drm_add_modes_noedid - add modes for the connectors without EDID 5646 * @connector: connector we're probing 5647 * @hdisplay: the horizontal display limit 5648 * @vdisplay: the vertical display limit 5649 * 5650 * Add the specified modes to the connector's mode list. Only when the 5651 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5652 * 5653 * Return: The number of modes added or 0 if we couldn't find any. 5654 */ 5655 int drm_add_modes_noedid(struct drm_connector *connector, 5656 int hdisplay, int vdisplay) 5657 { 5658 int i, count, num_modes = 0; 5659 struct drm_display_mode *mode; 5660 struct drm_device *dev = connector->dev; 5661 5662 count = ARRAY_SIZE(drm_dmt_modes); 5663 if (hdisplay < 0) 5664 hdisplay = 0; 5665 if (vdisplay < 0) 5666 vdisplay = 0; 5667 5668 for (i = 0; i < count; i++) { 5669 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5670 5671 if (hdisplay && vdisplay) { 5672 /* 5673 * Only when two are valid, they will be used to check 5674 * whether the mode should be added to the mode list of 5675 * the connector. 5676 */ 5677 if (ptr->hdisplay > hdisplay || 5678 ptr->vdisplay > vdisplay) 5679 continue; 5680 } 5681 if (drm_mode_vrefresh(ptr) > 61) 5682 continue; 5683 mode = drm_mode_duplicate(dev, ptr); 5684 if (mode) { 5685 drm_mode_probed_add(connector, mode); 5686 num_modes++; 5687 } 5688 } 5689 return num_modes; 5690 } 5691 EXPORT_SYMBOL(drm_add_modes_noedid); 5692 5693 /** 5694 * drm_set_preferred_mode - Sets the preferred mode of a connector 5695 * @connector: connector whose mode list should be processed 5696 * @hpref: horizontal resolution of preferred mode 5697 * @vpref: vertical resolution of preferred mode 5698 * 5699 * Marks a mode as preferred if it matches the resolution specified by @hpref 5700 * and @vpref. 5701 */ 5702 void drm_set_preferred_mode(struct drm_connector *connector, 5703 int hpref, int vpref) 5704 { 5705 struct drm_display_mode *mode; 5706 5707 list_for_each_entry(mode, &connector->probed_modes, head) { 5708 if (mode->hdisplay == hpref && 5709 mode->vdisplay == vpref) 5710 mode->type |= DRM_MODE_TYPE_PREFERRED; 5711 } 5712 } 5713 EXPORT_SYMBOL(drm_set_preferred_mode); 5714 5715 static bool is_hdmi2_sink(const struct drm_connector *connector) 5716 { 5717 /* 5718 * FIXME: sil-sii8620 doesn't have a connector around when 5719 * we need one, so we have to be prepared for a NULL connector. 5720 */ 5721 if (!connector) 5722 return true; 5723 5724 return connector->display_info.hdmi.scdc.supported || 5725 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 5726 } 5727 5728 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5729 { 5730 return sink_eotf & BIT(output_eotf); 5731 } 5732 5733 /** 5734 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5735 * HDR metadata from userspace 5736 * @frame: HDMI DRM infoframe 5737 * @conn_state: Connector state containing HDR metadata 5738 * 5739 * Return: 0 on success or a negative error code on failure. 5740 */ 5741 int 5742 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5743 const struct drm_connector_state *conn_state) 5744 { 5745 struct drm_connector *connector; 5746 struct hdr_output_metadata *hdr_metadata; 5747 int err; 5748 5749 if (!frame || !conn_state) 5750 return -EINVAL; 5751 5752 connector = conn_state->connector; 5753 5754 if (!conn_state->hdr_output_metadata) 5755 return -EINVAL; 5756 5757 hdr_metadata = conn_state->hdr_output_metadata->data; 5758 5759 if (!hdr_metadata || !connector) 5760 return -EINVAL; 5761 5762 /* Sink EOTF is Bit map while infoframe is absolute values */ 5763 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5764 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5765 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5766 return -EINVAL; 5767 } 5768 5769 err = hdmi_drm_infoframe_init(frame); 5770 if (err < 0) 5771 return err; 5772 5773 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5774 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5775 5776 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5777 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5778 BUILD_BUG_ON(sizeof(frame->white_point) != 5779 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5780 5781 memcpy(&frame->display_primaries, 5782 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5783 sizeof(frame->display_primaries)); 5784 5785 memcpy(&frame->white_point, 5786 &hdr_metadata->hdmi_metadata_type1.white_point, 5787 sizeof(frame->white_point)); 5788 5789 frame->max_display_mastering_luminance = 5790 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5791 frame->min_display_mastering_luminance = 5792 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5793 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5794 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5795 5796 return 0; 5797 } 5798 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5799 5800 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5801 const struct drm_display_mode *mode) 5802 { 5803 bool has_hdmi_infoframe = connector ? 5804 connector->display_info.has_hdmi_infoframe : false; 5805 5806 if (!has_hdmi_infoframe) 5807 return 0; 5808 5809 /* No HDMI VIC when signalling 3D video format */ 5810 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5811 return 0; 5812 5813 return drm_match_hdmi_mode(mode); 5814 } 5815 5816 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5817 const struct drm_display_mode *mode) 5818 { 5819 u8 vic; 5820 5821 /* 5822 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5823 * we should send its VIC in vendor infoframes, else send the 5824 * VIC in AVI infoframes. Lets check if this mode is present in 5825 * HDMI 1.4b 4K modes 5826 */ 5827 if (drm_mode_hdmi_vic(connector, mode)) 5828 return 0; 5829 5830 vic = drm_match_cea_mode(mode); 5831 5832 /* 5833 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5834 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5835 * have to make sure we dont break HDMI 1.4 sinks. 5836 */ 5837 if (!is_hdmi2_sink(connector) && vic > 64) 5838 return 0; 5839 5840 return vic; 5841 } 5842 5843 /** 5844 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5845 * data from a DRM display mode 5846 * @frame: HDMI AVI infoframe 5847 * @connector: the connector 5848 * @mode: DRM display mode 5849 * 5850 * Return: 0 on success or a negative error code on failure. 5851 */ 5852 int 5853 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5854 const struct drm_connector *connector, 5855 const struct drm_display_mode *mode) 5856 { 5857 enum hdmi_picture_aspect picture_aspect; 5858 u8 vic, hdmi_vic; 5859 5860 if (!frame || !mode) 5861 return -EINVAL; 5862 5863 hdmi_avi_infoframe_init(frame); 5864 5865 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5866 frame->pixel_repeat = 1; 5867 5868 vic = drm_mode_cea_vic(connector, mode); 5869 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5870 5871 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5872 5873 /* 5874 * As some drivers don't support atomic, we can't use connector state. 5875 * So just initialize the frame with default values, just the same way 5876 * as it's done with other properties here. 5877 */ 5878 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5879 frame->itc = 0; 5880 5881 /* 5882 * Populate picture aspect ratio from either 5883 * user input (if specified) or from the CEA/HDMI mode lists. 5884 */ 5885 picture_aspect = mode->picture_aspect_ratio; 5886 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5887 if (vic) 5888 picture_aspect = drm_get_cea_aspect_ratio(vic); 5889 else if (hdmi_vic) 5890 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5891 } 5892 5893 /* 5894 * The infoframe can't convey anything but none, 4:3 5895 * and 16:9, so if the user has asked for anything else 5896 * we can only satisfy it by specifying the right VIC. 5897 */ 5898 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5899 if (vic) { 5900 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5901 return -EINVAL; 5902 } else if (hdmi_vic) { 5903 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5904 return -EINVAL; 5905 } else { 5906 return -EINVAL; 5907 } 5908 5909 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5910 } 5911 5912 frame->video_code = vic; 5913 frame->picture_aspect = picture_aspect; 5914 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5915 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5916 5917 return 0; 5918 } 5919 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5920 5921 /* HDMI Colorspace Spec Definitions */ 5922 #define FULL_COLORIMETRY_MASK 0x1FF 5923 #define NORMAL_COLORIMETRY_MASK 0x3 5924 #define EXTENDED_COLORIMETRY_MASK 0x7 5925 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5926 5927 #define C(x) ((x) << 0) 5928 #define EC(x) ((x) << 2) 5929 #define ACE(x) ((x) << 5) 5930 5931 #define HDMI_COLORIMETRY_NO_DATA 0x0 5932 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5933 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5934 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5935 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5936 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5937 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5938 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5939 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5940 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5941 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5942 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5943 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5944 5945 static const u32 hdmi_colorimetry_val[] = { 5946 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5947 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5948 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5949 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5950 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5951 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5952 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5953 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5954 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5955 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5956 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5957 }; 5958 5959 #undef C 5960 #undef EC 5961 #undef ACE 5962 5963 /** 5964 * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe 5965 * colorimetry information 5966 * @frame: HDMI AVI infoframe 5967 * @conn_state: connector state 5968 */ 5969 void 5970 drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame, 5971 const struct drm_connector_state *conn_state) 5972 { 5973 u32 colorimetry_val; 5974 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5975 5976 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5977 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5978 else 5979 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5980 5981 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5982 /* 5983 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5984 * structure and extend it in drivers/video/hdmi 5985 */ 5986 frame->extended_colorimetry = (colorimetry_val >> 2) & 5987 EXTENDED_COLORIMETRY_MASK; 5988 } 5989 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry); 5990 5991 /** 5992 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5993 * quantization range information 5994 * @frame: HDMI AVI infoframe 5995 * @connector: the connector 5996 * @mode: DRM display mode 5997 * @rgb_quant_range: RGB quantization range (Q) 5998 */ 5999 void 6000 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6001 const struct drm_connector *connector, 6002 const struct drm_display_mode *mode, 6003 enum hdmi_quantization_range rgb_quant_range) 6004 { 6005 const struct drm_display_info *info = &connector->display_info; 6006 6007 /* 6008 * CEA-861: 6009 * "A Source shall not send a non-zero Q value that does not correspond 6010 * to the default RGB Quantization Range for the transmitted Picture 6011 * unless the Sink indicates support for the Q bit in a Video 6012 * Capabilities Data Block." 6013 * 6014 * HDMI 2.0 recommends sending non-zero Q when it does match the 6015 * default RGB quantization range for the mode, even when QS=0. 6016 */ 6017 if (info->rgb_quant_range_selectable || 6018 rgb_quant_range == drm_default_rgb_quant_range(mode)) 6019 frame->quantization_range = rgb_quant_range; 6020 else 6021 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 6022 6023 /* 6024 * CEA-861-F: 6025 * "When transmitting any RGB colorimetry, the Source should set the 6026 * YQ-field to match the RGB Quantization Range being transmitted 6027 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 6028 * set YQ=1) and the Sink shall ignore the YQ-field." 6029 * 6030 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 6031 * by non-zero YQ when receiving RGB. There doesn't seem to be any 6032 * good way to tell which version of CEA-861 the sink supports, so 6033 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 6034 * on on CEA-861-F. 6035 */ 6036 if (!is_hdmi2_sink(connector) || 6037 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 6038 frame->ycc_quantization_range = 6039 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 6040 else 6041 frame->ycc_quantization_range = 6042 HDMI_YCC_QUANTIZATION_RANGE_FULL; 6043 } 6044 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 6045 6046 /** 6047 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 6048 * bar information 6049 * @frame: HDMI AVI infoframe 6050 * @conn_state: connector state 6051 */ 6052 void 6053 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 6054 const struct drm_connector_state *conn_state) 6055 { 6056 frame->right_bar = conn_state->tv.margins.right; 6057 frame->left_bar = conn_state->tv.margins.left; 6058 frame->top_bar = conn_state->tv.margins.top; 6059 frame->bottom_bar = conn_state->tv.margins.bottom; 6060 } 6061 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 6062 6063 static enum hdmi_3d_structure 6064 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 6065 { 6066 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 6067 6068 switch (layout) { 6069 case DRM_MODE_FLAG_3D_FRAME_PACKING: 6070 return HDMI_3D_STRUCTURE_FRAME_PACKING; 6071 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 6072 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 6073 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 6074 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 6075 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 6076 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 6077 case DRM_MODE_FLAG_3D_L_DEPTH: 6078 return HDMI_3D_STRUCTURE_L_DEPTH; 6079 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 6080 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 6081 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 6082 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 6083 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 6084 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 6085 default: 6086 return HDMI_3D_STRUCTURE_INVALID; 6087 } 6088 } 6089 6090 /** 6091 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 6092 * data from a DRM display mode 6093 * @frame: HDMI vendor infoframe 6094 * @connector: the connector 6095 * @mode: DRM display mode 6096 * 6097 * Note that there's is a need to send HDMI vendor infoframes only when using a 6098 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 6099 * function will return -EINVAL, error that can be safely ignored. 6100 * 6101 * Return: 0 on success or a negative error code on failure. 6102 */ 6103 int 6104 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 6105 const struct drm_connector *connector, 6106 const struct drm_display_mode *mode) 6107 { 6108 /* 6109 * FIXME: sil-sii8620 doesn't have a connector around when 6110 * we need one, so we have to be prepared for a NULL connector. 6111 */ 6112 bool has_hdmi_infoframe = connector ? 6113 connector->display_info.has_hdmi_infoframe : false; 6114 int err; 6115 6116 if (!frame || !mode) 6117 return -EINVAL; 6118 6119 if (!has_hdmi_infoframe) 6120 return -EINVAL; 6121 6122 err = hdmi_vendor_infoframe_init(frame); 6123 if (err < 0) 6124 return err; 6125 6126 /* 6127 * Even if it's not absolutely necessary to send the infoframe 6128 * (ie.vic==0 and s3d_struct==0) we will still send it if we 6129 * know that the sink can handle it. This is based on a 6130 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 6131 * have trouble realizing that they should switch from 3D to 2D 6132 * mode if the source simply stops sending the infoframe when 6133 * it wants to switch from 3D to 2D. 6134 */ 6135 frame->vic = drm_mode_hdmi_vic(connector, mode); 6136 frame->s3d_struct = s3d_structure_from_display_mode(mode); 6137 6138 return 0; 6139 } 6140 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 6141 6142 static void drm_parse_tiled_block(struct drm_connector *connector, 6143 const struct displayid_block *block) 6144 { 6145 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6146 u16 w, h; 6147 u8 tile_v_loc, tile_h_loc; 6148 u8 num_v_tile, num_h_tile; 6149 struct drm_tile_group *tg; 6150 6151 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6152 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6153 6154 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6155 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6156 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6157 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6158 6159 connector->has_tile = true; 6160 if (tile->tile_cap & 0x80) 6161 connector->tile_is_single_monitor = true; 6162 6163 connector->num_h_tile = num_h_tile + 1; 6164 connector->num_v_tile = num_v_tile + 1; 6165 connector->tile_h_loc = tile_h_loc; 6166 connector->tile_v_loc = tile_v_loc; 6167 connector->tile_h_size = w + 1; 6168 connector->tile_v_size = h + 1; 6169 6170 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6171 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6172 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6173 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6174 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6175 6176 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6177 if (!tg) 6178 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6179 if (!tg) 6180 return; 6181 6182 if (connector->tile_group != tg) { 6183 /* if we haven't got a pointer, 6184 take the reference, drop ref to old tile group */ 6185 if (connector->tile_group) 6186 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6187 connector->tile_group = tg; 6188 } else { 6189 /* if same tile group, then release the ref we just took. */ 6190 drm_mode_put_tile_group(connector->dev, tg); 6191 } 6192 } 6193 6194 void drm_update_tile_info(struct drm_connector *connector, 6195 const struct edid *edid) 6196 { 6197 const struct displayid_block *block; 6198 struct displayid_iter iter; 6199 6200 connector->has_tile = false; 6201 6202 displayid_iter_edid_begin(edid, &iter); 6203 displayid_iter_for_each(block, &iter) { 6204 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6205 drm_parse_tiled_block(connector, block); 6206 } 6207 displayid_iter_end(&iter); 6208 6209 if (!connector->has_tile && connector->tile_group) { 6210 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6211 connector->tile_group = NULL; 6212 } 6213 } 6214