1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 199 /* Windows Mixed Reality Headsets */ 200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 208 209 /* Sony PlayStation VR Headset */ 210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 211 212 /* Sensics VR Headsets */ 213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 214 215 /* OSVR HDK and HDK2 VR Headsets */ 216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 217 }; 218 219 /* 220 * Autogenerated from the DMT spec. 221 * This table is copied from xfree86/modes/xf86EdidModes.c. 222 */ 223 static const struct drm_display_mode drm_dmt_modes[] = { 224 /* 0x01 - 640x350@85Hz */ 225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 226 736, 832, 0, 350, 382, 385, 445, 0, 227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 228 /* 0x02 - 640x400@85Hz */ 229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 230 736, 832, 0, 400, 401, 404, 445, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 232 /* 0x03 - 720x400@85Hz */ 233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 234 828, 936, 0, 400, 401, 404, 446, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 236 /* 0x04 - 640x480@60Hz */ 237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 238 752, 800, 0, 480, 490, 492, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 240 /* 0x05 - 640x480@72Hz */ 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 242 704, 832, 0, 480, 489, 492, 520, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x06 - 640x480@75Hz */ 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 246 720, 840, 0, 480, 481, 484, 500, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x07 - 640x480@85Hz */ 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 250 752, 832, 0, 480, 481, 484, 509, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 252 /* 0x08 - 800x600@56Hz */ 253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 254 896, 1024, 0, 600, 601, 603, 625, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x09 - 800x600@60Hz */ 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 258 968, 1056, 0, 600, 601, 605, 628, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x0a - 800x600@72Hz */ 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 262 976, 1040, 0, 600, 637, 643, 666, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x0b - 800x600@75Hz */ 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 266 896, 1056, 0, 600, 601, 604, 625, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x0c - 800x600@85Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 270 896, 1048, 0, 600, 601, 604, 631, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x0d - 800x600@120Hz RB */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 274 880, 960, 0, 600, 603, 607, 636, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x0e - 848x480@60Hz */ 277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 278 976, 1088, 0, 480, 486, 494, 517, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0f - 1024x768@43Hz, interlace */ 281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 282 1208, 1264, 0, 768, 768, 776, 817, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 284 DRM_MODE_FLAG_INTERLACE) }, 285 /* 0x10 - 1024x768@60Hz */ 286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 287 1184, 1344, 0, 768, 771, 777, 806, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 0x11 - 1024x768@70Hz */ 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 291 1184, 1328, 0, 768, 771, 777, 806, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x12 - 1024x768@75Hz */ 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 295 1136, 1312, 0, 768, 769, 772, 800, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x13 - 1024x768@85Hz */ 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 299 1168, 1376, 0, 768, 769, 772, 808, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x14 - 1024x768@120Hz RB */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 303 1104, 1184, 0, 768, 771, 775, 813, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 305 /* 0x15 - 1152x864@75Hz */ 306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 307 1344, 1600, 0, 864, 865, 868, 900, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x55 - 1280x720@60Hz */ 310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 311 1430, 1650, 0, 720, 725, 730, 750, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x16 - 1280x768@60Hz RB */ 314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 315 1360, 1440, 0, 768, 771, 778, 790, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x17 - 1280x768@60Hz */ 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 319 1472, 1664, 0, 768, 771, 778, 798, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x18 - 1280x768@75Hz */ 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 323 1488, 1696, 0, 768, 771, 778, 805, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x19 - 1280x768@85Hz */ 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 327 1496, 1712, 0, 768, 771, 778, 809, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x1a - 1280x768@120Hz RB */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 331 1360, 1440, 0, 768, 771, 778, 813, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 0x1b - 1280x800@60Hz RB */ 334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 335 1360, 1440, 0, 800, 803, 809, 823, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x1c - 1280x800@60Hz */ 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 339 1480, 1680, 0, 800, 803, 809, 831, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x1d - 1280x800@75Hz */ 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 343 1488, 1696, 0, 800, 803, 809, 838, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x1e - 1280x800@85Hz */ 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 347 1496, 1712, 0, 800, 803, 809, 843, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1f - 1280x800@120Hz RB */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 351 1360, 1440, 0, 800, 803, 809, 847, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x20 - 1280x960@60Hz */ 354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 355 1488, 1800, 0, 960, 961, 964, 1000, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x21 - 1280x960@85Hz */ 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 359 1504, 1728, 0, 960, 961, 964, 1011, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x22 - 1280x960@120Hz RB */ 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 363 1360, 1440, 0, 960, 963, 967, 1017, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x23 - 1280x1024@60Hz */ 366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x24 - 1280x1024@75Hz */ 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x25 - 1280x1024@85Hz */ 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x26 - 1280x1024@120Hz RB */ 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 381 /* 0x27 - 1360x768@60Hz */ 382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 383 1536, 1792, 0, 768, 771, 777, 795, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x28 - 1360x768@120Hz RB */ 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 387 1440, 1520, 0, 768, 771, 776, 813, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 389 /* 0x51 - 1366x768@60Hz */ 390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 391 1579, 1792, 0, 768, 771, 774, 798, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x56 - 1366x768@60Hz */ 394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 395 1436, 1500, 0, 768, 769, 772, 800, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x29 - 1400x1050@60Hz RB */ 398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x2a - 1400x1050@60Hz */ 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x2b - 1400x1050@75Hz */ 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x2c - 1400x1050@85Hz */ 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x2d - 1400x1050@120Hz RB */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 0x2e - 1440x900@60Hz RB */ 418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 419 1520, 1600, 0, 900, 903, 909, 926, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2f - 1440x900@60Hz */ 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 423 1672, 1904, 0, 900, 903, 909, 934, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x30 - 1440x900@75Hz */ 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 427 1688, 1936, 0, 900, 903, 909, 942, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x31 - 1440x900@85Hz */ 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 431 1696, 1952, 0, 900, 903, 909, 948, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x32 - 1440x900@120Hz RB */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 435 1520, 1600, 0, 900, 903, 909, 953, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x53 - 1600x900@60Hz */ 438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 439 1704, 1800, 0, 900, 901, 904, 1000, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x33 - 1600x1200@60Hz */ 442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x34 - 1600x1200@65Hz */ 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x35 - 1600x1200@70Hz */ 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x36 - 1600x1200@75Hz */ 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x37 - 1600x1200@85Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x38 - 1600x1200@120Hz RB */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 465 /* 0x39 - 1680x1050@60Hz RB */ 466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x3a - 1680x1050@60Hz */ 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x3b - 1680x1050@75Hz */ 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x3c - 1680x1050@85Hz */ 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x3d - 1680x1050@120Hz RB */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x3e - 1792x1344@60Hz */ 486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x3f - 1792x1344@75Hz */ 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x40 - 1792x1344@120Hz RB */ 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x41 - 1856x1392@60Hz */ 498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x42 - 1856x1392@75Hz */ 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x43 - 1856x1392@120Hz RB */ 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 509 /* 0x52 - 1920x1080@60Hz */ 510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 /* 0x44 - 1920x1200@60Hz RB */ 514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x45 - 1920x1200@60Hz */ 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x46 - 1920x1200@75Hz */ 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x47 - 1920x1200@85Hz */ 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 529 /* 0x48 - 1920x1200@120Hz RB */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x49 - 1920x1440@60Hz */ 534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x4a - 1920x1440@75Hz */ 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x4b - 1920x1440@120Hz RB */ 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 545 /* 0x54 - 2048x1152@60Hz */ 546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x4c - 2560x1600@60Hz RB */ 550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x4d - 2560x1600@60Hz */ 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4e - 2560x1600@75Hz */ 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4f - 2560x1600@85Hz */ 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x50 - 2560x1600@120Hz RB */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 569 /* 0x57 - 4096x2160@60Hz RB */ 570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x58 - 4096x2160@59.94Hz RB */ 574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 }; 578 579 /* 580 * These more or less come from the DMT spec. The 720x400 modes are 581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 584 * mode. 585 * 586 * The DMT modes have been fact-checked; the rest are mild guesses. 587 */ 588 static const struct drm_display_mode edid_est_modes[] = { 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 590 968, 1056, 0, 600, 601, 605, 628, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 593 896, 1024, 0, 600, 601, 603, 625, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 596 720, 840, 0, 480, 481, 484, 500, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 599 704, 832, 0, 480, 489, 492, 520, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 602 768, 864, 0, 480, 483, 486, 525, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 605 752, 800, 0, 480, 490, 492, 525, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 608 846, 900, 0, 400, 421, 423, 449, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 611 846, 900, 0, 400, 412, 414, 449, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 617 1136, 1312, 0, 768, 769, 772, 800, 0, 618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 620 1184, 1328, 0, 768, 771, 777, 806, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 623 1184, 1344, 0, 768, 771, 777, 806, 0, 624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 626 1208, 1264, 0, 768, 768, 776, 817, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 629 928, 1152, 0, 624, 625, 628, 667, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 632 896, 1056, 0, 600, 601, 604, 625, 0, 633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 635 976, 1040, 0, 600, 637, 643, 666, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 638 1344, 1600, 0, 864, 865, 868, 900, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 640 }; 641 642 struct minimode { 643 short w; 644 short h; 645 short r; 646 short rb; 647 }; 648 649 static const struct minimode est3_modes[] = { 650 /* byte 6 */ 651 { 640, 350, 85, 0 }, 652 { 640, 400, 85, 0 }, 653 { 720, 400, 85, 0 }, 654 { 640, 480, 85, 0 }, 655 { 848, 480, 60, 0 }, 656 { 800, 600, 85, 0 }, 657 { 1024, 768, 85, 0 }, 658 { 1152, 864, 75, 0 }, 659 /* byte 7 */ 660 { 1280, 768, 60, 1 }, 661 { 1280, 768, 60, 0 }, 662 { 1280, 768, 75, 0 }, 663 { 1280, 768, 85, 0 }, 664 { 1280, 960, 60, 0 }, 665 { 1280, 960, 85, 0 }, 666 { 1280, 1024, 60, 0 }, 667 { 1280, 1024, 85, 0 }, 668 /* byte 8 */ 669 { 1360, 768, 60, 0 }, 670 { 1440, 900, 60, 1 }, 671 { 1440, 900, 60, 0 }, 672 { 1440, 900, 75, 0 }, 673 { 1440, 900, 85, 0 }, 674 { 1400, 1050, 60, 1 }, 675 { 1400, 1050, 60, 0 }, 676 { 1400, 1050, 75, 0 }, 677 /* byte 9 */ 678 { 1400, 1050, 85, 0 }, 679 { 1680, 1050, 60, 1 }, 680 { 1680, 1050, 60, 0 }, 681 { 1680, 1050, 75, 0 }, 682 { 1680, 1050, 85, 0 }, 683 { 1600, 1200, 60, 0 }, 684 { 1600, 1200, 65, 0 }, 685 { 1600, 1200, 70, 0 }, 686 /* byte 10 */ 687 { 1600, 1200, 75, 0 }, 688 { 1600, 1200, 85, 0 }, 689 { 1792, 1344, 60, 0 }, 690 { 1792, 1344, 75, 0 }, 691 { 1856, 1392, 60, 0 }, 692 { 1856, 1392, 75, 0 }, 693 { 1920, 1200, 60, 1 }, 694 { 1920, 1200, 60, 0 }, 695 /* byte 11 */ 696 { 1920, 1200, 75, 0 }, 697 { 1920, 1200, 85, 0 }, 698 { 1920, 1440, 60, 0 }, 699 { 1920, 1440, 75, 0 }, 700 }; 701 702 static const struct minimode extra_modes[] = { 703 { 1024, 576, 60, 0 }, 704 { 1366, 768, 60, 0 }, 705 { 1600, 900, 60, 0 }, 706 { 1680, 945, 60, 0 }, 707 { 1920, 1080, 60, 0 }, 708 { 2048, 1152, 60, 0 }, 709 { 2048, 1536, 60, 0 }, 710 }; 711 712 /* 713 * Probably taken from CEA-861 spec. 714 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 715 * 716 * Index using the VIC. 717 */ 718 static const struct drm_display_mode edid_cea_modes[] = { 719 /* 0 - dummy, VICs start at 1 */ 720 { }, 721 /* 1 - 640x480@60Hz 4:3 */ 722 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 723 752, 800, 0, 480, 490, 492, 525, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 726 /* 2 - 720x480@60Hz 4:3 */ 727 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 728 798, 858, 0, 480, 489, 495, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 3 - 720x480@60Hz 16:9 */ 732 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 733 798, 858, 0, 480, 489, 495, 525, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 4 - 1280x720@60Hz 16:9 */ 737 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 738 1430, 1650, 0, 720, 725, 730, 750, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 5 - 1920x1080i@60Hz 16:9 */ 742 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 743 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 745 DRM_MODE_FLAG_INTERLACE), 746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 6 - 720(1440)x480i@60Hz 4:3 */ 748 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 749 801, 858, 0, 480, 488, 494, 525, 0, 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 751 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 753 /* 7 - 720(1440)x480i@60Hz 16:9 */ 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 755 801, 858, 0, 480, 488, 494, 525, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 759 /* 8 - 720(1440)x240@60Hz 4:3 */ 760 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 761 801, 858, 0, 240, 244, 247, 262, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_DBLCLK), 764 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 765 /* 9 - 720(1440)x240@60Hz 16:9 */ 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 767 801, 858, 0, 240, 244, 247, 262, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 10 - 2880x480i@60Hz 4:3 */ 772 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 773 3204, 3432, 0, 480, 488, 494, 525, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_INTERLACE), 776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 777 /* 11 - 2880x480i@60Hz 16:9 */ 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 779 3204, 3432, 0, 480, 488, 494, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 783 /* 12 - 2880x240@60Hz 4:3 */ 784 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 785 3204, 3432, 0, 240, 244, 247, 262, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 787 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 788 /* 13 - 2880x240@60Hz 16:9 */ 789 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 240, 244, 247, 262, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 14 - 1440x480@60Hz 4:3 */ 794 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 795 1596, 1716, 0, 480, 489, 495, 525, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 15 - 1440x480@60Hz 16:9 */ 799 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 800 1596, 1716, 0, 480, 489, 495, 525, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 803 /* 16 - 1920x1080@60Hz 16:9 */ 804 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 805 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 807 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 17 - 720x576@50Hz 4:3 */ 809 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 810 796, 864, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 813 /* 18 - 720x576@50Hz 16:9 */ 814 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 815 796, 864, 0, 576, 581, 586, 625, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 19 - 1280x720@50Hz 16:9 */ 819 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 820 1760, 1980, 0, 720, 725, 730, 750, 0, 821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 20 - 1920x1080i@50Hz 16:9 */ 824 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 825 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 827 DRM_MODE_FLAG_INTERLACE), 828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 21 - 720(1440)x576i@50Hz 4:3 */ 830 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 831 795, 864, 0, 576, 580, 586, 625, 0, 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 833 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 835 /* 22 - 720(1440)x576i@50Hz 16:9 */ 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 837 795, 864, 0, 576, 580, 586, 625, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 841 /* 23 - 720(1440)x288@50Hz 4:3 */ 842 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 843 795, 864, 0, 288, 290, 293, 312, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 845 DRM_MODE_FLAG_DBLCLK), 846 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 847 /* 24 - 720(1440)x288@50Hz 16:9 */ 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 849 795, 864, 0, 288, 290, 293, 312, 0, 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 851 DRM_MODE_FLAG_DBLCLK), 852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 853 /* 25 - 2880x576i@50Hz 4:3 */ 854 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 855 3180, 3456, 0, 576, 580, 586, 625, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 857 DRM_MODE_FLAG_INTERLACE), 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 859 /* 26 - 2880x576i@50Hz 16:9 */ 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 861 3180, 3456, 0, 576, 580, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 27 - 2880x288@50Hz 4:3 */ 866 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 867 3180, 3456, 0, 288, 290, 293, 312, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 870 /* 28 - 2880x288@50Hz 16:9 */ 871 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 288, 290, 293, 312, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 874 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 29 - 1440x576@50Hz 4:3 */ 876 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 877 1592, 1728, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 880 /* 30 - 1440x576@50Hz 16:9 */ 881 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 882 1592, 1728, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 31 - 1920x1080@50Hz 16:9 */ 886 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 887 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 889 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 890 /* 32 - 1920x1080@24Hz 16:9 */ 891 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 892 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 894 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 33 - 1920x1080@25Hz 16:9 */ 896 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 897 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 899 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 34 - 1920x1080@30Hz 16:9 */ 901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 902 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 904 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 35 - 2880x480@60Hz 4:3 */ 906 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 907 3192, 3432, 0, 480, 489, 495, 525, 0, 908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 909 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 910 /* 36 - 2880x480@60Hz 16:9 */ 911 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 912 3192, 3432, 0, 480, 489, 495, 525, 0, 913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 914 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 37 - 2880x576@50Hz 4:3 */ 916 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 917 3184, 3456, 0, 576, 581, 586, 625, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 919 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 920 /* 38 - 2880x576@50Hz 16:9 */ 921 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 922 3184, 3456, 0, 576, 581, 586, 625, 0, 923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 924 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 39 - 1920x1080i@50Hz 16:9 */ 926 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 927 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 929 DRM_MODE_FLAG_INTERLACE), 930 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 40 - 1920x1080i@100Hz 16:9 */ 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 933 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 935 DRM_MODE_FLAG_INTERLACE), 936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 937 /* 41 - 1280x720@100Hz 16:9 */ 938 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 939 1760, 1980, 0, 720, 725, 730, 750, 0, 940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 941 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 42 - 720x576@100Hz 4:3 */ 943 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 944 796, 864, 0, 576, 581, 586, 625, 0, 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 946 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 947 /* 43 - 720x576@100Hz 16:9 */ 948 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 949 796, 864, 0, 576, 581, 586, 625, 0, 950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 951 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 952 /* 44 - 720(1440)x576i@100Hz 4:3 */ 953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 954 795, 864, 0, 576, 580, 586, 625, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 957 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 958 /* 45 - 720(1440)x576i@100Hz 16:9 */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 964 /* 46 - 1920x1080i@120Hz 16:9 */ 965 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 966 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 967 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 968 DRM_MODE_FLAG_INTERLACE), 969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 47 - 1280x720@120Hz 16:9 */ 971 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 972 1430, 1650, 0, 720, 725, 730, 750, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 974 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 48 - 720x480@120Hz 4:3 */ 976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 977 798, 858, 0, 480, 489, 495, 525, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 979 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 980 /* 49 - 720x480@120Hz 16:9 */ 981 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 982 798, 858, 0, 480, 489, 495, 525, 0, 983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 50 - 720(1440)x480i@120Hz 4:3 */ 986 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 987 801, 858, 0, 480, 488, 494, 525, 0, 988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 989 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 990 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 991 /* 51 - 720(1440)x480i@120Hz 16:9 */ 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 993 801, 858, 0, 480, 488, 494, 525, 0, 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 996 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 /* 52 - 720x576@200Hz 4:3 */ 998 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 999 796, 864, 0, 576, 581, 586, 625, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1001 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1002 /* 53 - 720x576@200Hz 16:9 */ 1003 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1004 796, 864, 0, 576, 581, 586, 625, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1006 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1007 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1008 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1009 795, 864, 0, 576, 580, 586, 625, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1011 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1012 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1013 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1015 795, 864, 0, 576, 580, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1018 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1019 /* 56 - 720x480@240Hz 4:3 */ 1020 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1021 798, 858, 0, 480, 489, 495, 525, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1023 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1024 /* 57 - 720x480@240Hz 16:9 */ 1025 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1026 798, 858, 0, 480, 489, 495, 525, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1028 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1029 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1030 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1031 801, 858, 0, 480, 488, 494, 525, 0, 1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1033 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1034 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1035 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1037 801, 858, 0, 480, 488, 494, 525, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1040 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1041 /* 60 - 1280x720@24Hz 16:9 */ 1042 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1043 3080, 3300, 0, 720, 725, 730, 750, 0, 1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1045 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1046 /* 61 - 1280x720@25Hz 16:9 */ 1047 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1048 3740, 3960, 0, 720, 725, 730, 750, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1050 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1051 /* 62 - 1280x720@30Hz 16:9 */ 1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1053 3080, 3300, 0, 720, 725, 730, 750, 0, 1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1055 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1056 /* 63 - 1920x1080@120Hz 16:9 */ 1057 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1058 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1060 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1061 /* 64 - 1920x1080@100Hz 16:9 */ 1062 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1063 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1066 /* 65 - 1280x720@24Hz 64:27 */ 1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1068 3080, 3300, 0, 720, 725, 730, 750, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1071 /* 66 - 1280x720@25Hz 64:27 */ 1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1073 3740, 3960, 0, 720, 725, 730, 750, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1076 /* 67 - 1280x720@30Hz 64:27 */ 1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1078 3080, 3300, 0, 720, 725, 730, 750, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1081 /* 68 - 1280x720@50Hz 64:27 */ 1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1083 1760, 1980, 0, 720, 725, 730, 750, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1086 /* 69 - 1280x720@60Hz 64:27 */ 1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1088 1430, 1650, 0, 720, 725, 730, 750, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 70 - 1280x720@100Hz 64:27 */ 1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1093 1760, 1980, 0, 720, 725, 730, 750, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 71 - 1280x720@120Hz 64:27 */ 1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1098 1430, 1650, 0, 720, 725, 730, 750, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 72 - 1920x1080@24Hz 64:27 */ 1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1103 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 73 - 1920x1080@25Hz 64:27 */ 1107 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1108 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 74 - 1920x1080@30Hz 64:27 */ 1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1113 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 75 - 1920x1080@50Hz 64:27 */ 1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1118 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 76 - 1920x1080@60Hz 64:27 */ 1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1123 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 77 - 1920x1080@100Hz 64:27 */ 1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 78 - 1920x1080@120Hz 64:27 */ 1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 79 - 1680x720@24Hz 64:27 */ 1137 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1138 3080, 3300, 0, 720, 725, 730, 750, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 80 - 1680x720@25Hz 64:27 */ 1142 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1143 2948, 3168, 0, 720, 725, 730, 750, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 81 - 1680x720@30Hz 64:27 */ 1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1148 2420, 2640, 0, 720, 725, 730, 750, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 82 - 1680x720@50Hz 64:27 */ 1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1153 1980, 2200, 0, 720, 725, 730, 750, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 83 - 1680x720@60Hz 64:27 */ 1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1158 1980, 2200, 0, 720, 725, 730, 750, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 84 - 1680x720@100Hz 64:27 */ 1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1163 1780, 2000, 0, 720, 725, 730, 825, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 85 - 1680x720@120Hz 64:27 */ 1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1168 1780, 2000, 0, 720, 725, 730, 825, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 86 - 2560x1080@24Hz 64:27 */ 1172 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1173 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 87 - 2560x1080@25Hz 64:27 */ 1177 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1178 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 88 - 2560x1080@30Hz 64:27 */ 1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1183 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 89 - 2560x1080@50Hz 64:27 */ 1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1188 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 90 - 2560x1080@60Hz 64:27 */ 1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1193 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 91 - 2560x1080@100Hz 64:27 */ 1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1198 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 92 - 2560x1080@120Hz 64:27 */ 1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1203 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 93 - 3840x2160@24Hz 16:9 */ 1207 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1208 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1211 /* 94 - 3840x2160@25Hz 16:9 */ 1212 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1213 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1216 /* 95 - 3840x2160@30Hz 16:9 */ 1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1218 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1221 /* 96 - 3840x2160@50Hz 16:9 */ 1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1223 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1226 /* 97 - 3840x2160@60Hz 16:9 */ 1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1228 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1231 /* 98 - 4096x2160@24Hz 256:135 */ 1232 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1233 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1236 /* 99 - 4096x2160@25Hz 256:135 */ 1237 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1238 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1241 /* 100 - 4096x2160@30Hz 256:135 */ 1242 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1243 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1246 /* 101 - 4096x2160@50Hz 256:135 */ 1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1248 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1251 /* 102 - 4096x2160@60Hz 256:135 */ 1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1253 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1256 /* 103 - 3840x2160@24Hz 64:27 */ 1257 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1258 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1261 /* 104 - 3840x2160@25Hz 64:27 */ 1262 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1263 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1266 /* 105 - 3840x2160@30Hz 64:27 */ 1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1268 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1271 /* 106 - 3840x2160@50Hz 64:27 */ 1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1273 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1276 /* 107 - 3840x2160@60Hz 64:27 */ 1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1278 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1281 /* 108 - 1280x720@48Hz 16:9 */ 1282 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1283 2280, 2500, 0, 720, 725, 730, 750, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1286 /* 109 - 1280x720@48Hz 64:27 */ 1287 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1288 2280, 2500, 0, 720, 725, 730, 750, 0, 1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1290 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1291 /* 110 - 1680x720@48Hz 64:27 */ 1292 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1293 2530, 2750, 0, 720, 725, 730, 750, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1296 /* 111 - 1920x1080@48Hz 16:9 */ 1297 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1298 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1301 /* 112 - 1920x1080@48Hz 64:27 */ 1302 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1303 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1306 /* 113 - 2560x1080@48Hz 64:27 */ 1307 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1308 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1311 /* 114 - 3840x2160@48Hz 16:9 */ 1312 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1313 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1316 /* 115 - 4096x2160@48Hz 256:135 */ 1317 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1318 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1321 /* 116 - 3840x2160@48Hz 64:27 */ 1322 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1323 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1326 /* 117 - 3840x2160@100Hz 16:9 */ 1327 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1328 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1331 /* 118 - 3840x2160@120Hz 16:9 */ 1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1333 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1336 /* 119 - 3840x2160@100Hz 64:27 */ 1337 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1338 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1341 /* 120 - 3840x2160@120Hz 64:27 */ 1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1343 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1346 /* 121 - 5120x2160@24Hz 64:27 */ 1347 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1348 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1351 /* 122 - 5120x2160@25Hz 64:27 */ 1352 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1353 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1356 /* 123 - 5120x2160@30Hz 64:27 */ 1357 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1358 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1360 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1361 /* 124 - 5120x2160@48Hz 64:27 */ 1362 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1363 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1365 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1366 /* 125 - 5120x2160@50Hz 64:27 */ 1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1368 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1370 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1371 /* 126 - 5120x2160@60Hz 64:27 */ 1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1373 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1375 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1376 /* 127 - 5120x2160@100Hz 64:27 */ 1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1378 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1380 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1381 }; 1382 1383 /* 1384 * HDMI 1.4 4k modes. Index using the VIC. 1385 */ 1386 static const struct drm_display_mode edid_4k_modes[] = { 1387 /* 0 - dummy, VICs start at 1 */ 1388 { }, 1389 /* 1 - 3840x2160@30Hz */ 1390 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1391 3840, 4016, 4104, 4400, 0, 1392 2160, 2168, 2178, 2250, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1394 .vrefresh = 30, }, 1395 /* 2 - 3840x2160@25Hz */ 1396 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1397 3840, 4896, 4984, 5280, 0, 1398 2160, 2168, 2178, 2250, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1400 .vrefresh = 25, }, 1401 /* 3 - 3840x2160@24Hz */ 1402 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1403 3840, 5116, 5204, 5500, 0, 1404 2160, 2168, 2178, 2250, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .vrefresh = 24, }, 1407 /* 4 - 4096x2160@24Hz (SMPTE) */ 1408 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1409 4096, 5116, 5204, 5500, 0, 1410 2160, 2168, 2178, 2250, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .vrefresh = 24, }, 1413 }; 1414 1415 /*** DDC fetch and block validation ***/ 1416 1417 static const u8 edid_header[] = { 1418 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1419 }; 1420 1421 /** 1422 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1423 * @raw_edid: pointer to raw base EDID block 1424 * 1425 * Sanity check the header of the base EDID block. 1426 * 1427 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1428 */ 1429 int drm_edid_header_is_valid(const u8 *raw_edid) 1430 { 1431 int i, score = 0; 1432 1433 for (i = 0; i < sizeof(edid_header); i++) 1434 if (raw_edid[i] == edid_header[i]) 1435 score++; 1436 1437 return score; 1438 } 1439 EXPORT_SYMBOL(drm_edid_header_is_valid); 1440 1441 static int edid_fixup __read_mostly = 6; 1442 module_param_named(edid_fixup, edid_fixup, int, 0400); 1443 MODULE_PARM_DESC(edid_fixup, 1444 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1445 1446 static void drm_get_displayid(struct drm_connector *connector, 1447 struct edid *edid); 1448 static int validate_displayid(u8 *displayid, int length, int idx); 1449 1450 static int drm_edid_block_checksum(const u8 *raw_edid) 1451 { 1452 int i; 1453 u8 csum = 0; 1454 for (i = 0; i < EDID_LENGTH; i++) 1455 csum += raw_edid[i]; 1456 1457 return csum; 1458 } 1459 1460 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1461 { 1462 if (memchr_inv(in_edid, 0, length)) 1463 return false; 1464 1465 return true; 1466 } 1467 1468 /** 1469 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1470 * @raw_edid: pointer to raw EDID block 1471 * @block: type of block to validate (0 for base, extension otherwise) 1472 * @print_bad_edid: if true, dump bad EDID blocks to the console 1473 * @edid_corrupt: if true, the header or checksum is invalid 1474 * 1475 * Validate a base or extension EDID block and optionally dump bad blocks to 1476 * the console. 1477 * 1478 * Return: True if the block is valid, false otherwise. 1479 */ 1480 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1481 bool *edid_corrupt) 1482 { 1483 u8 csum; 1484 struct edid *edid = (struct edid *)raw_edid; 1485 1486 if (WARN_ON(!raw_edid)) 1487 return false; 1488 1489 if (edid_fixup > 8 || edid_fixup < 0) 1490 edid_fixup = 6; 1491 1492 if (block == 0) { 1493 int score = drm_edid_header_is_valid(raw_edid); 1494 if (score == 8) { 1495 if (edid_corrupt) 1496 *edid_corrupt = false; 1497 } else if (score >= edid_fixup) { 1498 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1499 * The corrupt flag needs to be set here otherwise, the 1500 * fix-up code here will correct the problem, the 1501 * checksum is correct and the test fails 1502 */ 1503 if (edid_corrupt) 1504 *edid_corrupt = true; 1505 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1506 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1507 } else { 1508 if (edid_corrupt) 1509 *edid_corrupt = true; 1510 goto bad; 1511 } 1512 } 1513 1514 csum = drm_edid_block_checksum(raw_edid); 1515 if (csum) { 1516 if (edid_corrupt) 1517 *edid_corrupt = true; 1518 1519 /* allow CEA to slide through, switches mangle this */ 1520 if (raw_edid[0] == CEA_EXT) { 1521 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1522 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1523 } else { 1524 if (print_bad_edid) 1525 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1526 1527 goto bad; 1528 } 1529 } 1530 1531 /* per-block-type checks */ 1532 switch (raw_edid[0]) { 1533 case 0: /* base */ 1534 if (edid->version != 1) { 1535 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1536 goto bad; 1537 } 1538 1539 if (edid->revision > 4) 1540 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1541 break; 1542 1543 default: 1544 break; 1545 } 1546 1547 return true; 1548 1549 bad: 1550 if (print_bad_edid) { 1551 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1552 pr_notice("EDID block is all zeroes\n"); 1553 } else { 1554 pr_notice("Raw EDID:\n"); 1555 print_hex_dump(KERN_NOTICE, 1556 " \t", DUMP_PREFIX_NONE, 16, 1, 1557 raw_edid, EDID_LENGTH, false); 1558 } 1559 } 1560 return false; 1561 } 1562 EXPORT_SYMBOL(drm_edid_block_valid); 1563 1564 /** 1565 * drm_edid_is_valid - sanity check EDID data 1566 * @edid: EDID data 1567 * 1568 * Sanity-check an entire EDID record (including extensions) 1569 * 1570 * Return: True if the EDID data is valid, false otherwise. 1571 */ 1572 bool drm_edid_is_valid(struct edid *edid) 1573 { 1574 int i; 1575 u8 *raw = (u8 *)edid; 1576 1577 if (!edid) 1578 return false; 1579 1580 for (i = 0; i <= edid->extensions; i++) 1581 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1582 return false; 1583 1584 return true; 1585 } 1586 EXPORT_SYMBOL(drm_edid_is_valid); 1587 1588 #define DDC_SEGMENT_ADDR 0x30 1589 /** 1590 * drm_do_probe_ddc_edid() - get EDID information via I2C 1591 * @data: I2C device adapter 1592 * @buf: EDID data buffer to be filled 1593 * @block: 128 byte EDID block to start fetching from 1594 * @len: EDID data buffer length to fetch 1595 * 1596 * Try to fetch EDID information by calling I2C driver functions. 1597 * 1598 * Return: 0 on success or -1 on failure. 1599 */ 1600 static int 1601 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1602 { 1603 struct i2c_adapter *adapter = data; 1604 unsigned char start = block * EDID_LENGTH; 1605 unsigned char segment = block >> 1; 1606 unsigned char xfers = segment ? 3 : 2; 1607 int ret, retries = 5; 1608 1609 /* 1610 * The core I2C driver will automatically retry the transfer if the 1611 * adapter reports EAGAIN. However, we find that bit-banging transfers 1612 * are susceptible to errors under a heavily loaded machine and 1613 * generate spurious NAKs and timeouts. Retrying the transfer 1614 * of the individual block a few times seems to overcome this. 1615 */ 1616 do { 1617 struct i2c_msg msgs[] = { 1618 { 1619 .addr = DDC_SEGMENT_ADDR, 1620 .flags = 0, 1621 .len = 1, 1622 .buf = &segment, 1623 }, { 1624 .addr = DDC_ADDR, 1625 .flags = 0, 1626 .len = 1, 1627 .buf = &start, 1628 }, { 1629 .addr = DDC_ADDR, 1630 .flags = I2C_M_RD, 1631 .len = len, 1632 .buf = buf, 1633 } 1634 }; 1635 1636 /* 1637 * Avoid sending the segment addr to not upset non-compliant 1638 * DDC monitors. 1639 */ 1640 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1641 1642 if (ret == -ENXIO) { 1643 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1644 adapter->name); 1645 break; 1646 } 1647 } while (ret != xfers && --retries); 1648 1649 return ret == xfers ? 0 : -1; 1650 } 1651 1652 static void connector_bad_edid(struct drm_connector *connector, 1653 u8 *edid, int num_blocks) 1654 { 1655 int i; 1656 1657 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1658 return; 1659 1660 dev_warn(connector->dev->dev, 1661 "%s: EDID is invalid:\n", 1662 connector->name); 1663 for (i = 0; i < num_blocks; i++) { 1664 u8 *block = edid + i * EDID_LENGTH; 1665 char prefix[20]; 1666 1667 if (drm_edid_is_zero(block, EDID_LENGTH)) 1668 sprintf(prefix, "\t[%02x] ZERO ", i); 1669 else if (!drm_edid_block_valid(block, i, false, NULL)) 1670 sprintf(prefix, "\t[%02x] BAD ", i); 1671 else 1672 sprintf(prefix, "\t[%02x] GOOD ", i); 1673 1674 print_hex_dump(KERN_WARNING, 1675 prefix, DUMP_PREFIX_NONE, 16, 1, 1676 block, EDID_LENGTH, false); 1677 } 1678 } 1679 1680 /* Get override or firmware EDID */ 1681 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1682 { 1683 struct edid *override = NULL; 1684 1685 if (connector->override_edid) 1686 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1687 1688 if (!override) 1689 override = drm_load_edid_firmware(connector); 1690 1691 return IS_ERR(override) ? NULL : override; 1692 } 1693 1694 /** 1695 * drm_add_override_edid_modes - add modes from override/firmware EDID 1696 * @connector: connector we're probing 1697 * 1698 * Add modes from the override/firmware EDID, if available. Only to be used from 1699 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1700 * failed during drm_get_edid() and caused the override/firmware EDID to be 1701 * skipped. 1702 * 1703 * Return: The number of modes added or 0 if we couldn't find any. 1704 */ 1705 int drm_add_override_edid_modes(struct drm_connector *connector) 1706 { 1707 struct edid *override; 1708 int num_modes = 0; 1709 1710 override = drm_get_override_edid(connector); 1711 if (override) { 1712 drm_connector_update_edid_property(connector, override); 1713 num_modes = drm_add_edid_modes(connector, override); 1714 kfree(override); 1715 1716 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1717 connector->base.id, connector->name, num_modes); 1718 } 1719 1720 return num_modes; 1721 } 1722 EXPORT_SYMBOL(drm_add_override_edid_modes); 1723 1724 /** 1725 * drm_do_get_edid - get EDID data using a custom EDID block read function 1726 * @connector: connector we're probing 1727 * @get_edid_block: EDID block read function 1728 * @data: private data passed to the block read function 1729 * 1730 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1731 * exposes a different interface to read EDID blocks this function can be used 1732 * to get EDID data using a custom block read function. 1733 * 1734 * As in the general case the DDC bus is accessible by the kernel at the I2C 1735 * level, drivers must make all reasonable efforts to expose it as an I2C 1736 * adapter and use drm_get_edid() instead of abusing this function. 1737 * 1738 * The EDID may be overridden using debugfs override_edid or firmare EDID 1739 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1740 * order. Having either of them bypasses actual EDID reads. 1741 * 1742 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1743 */ 1744 struct edid *drm_do_get_edid(struct drm_connector *connector, 1745 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1746 size_t len), 1747 void *data) 1748 { 1749 int i, j = 0, valid_extensions = 0; 1750 u8 *edid, *new; 1751 struct edid *override; 1752 1753 override = drm_get_override_edid(connector); 1754 if (override) 1755 return override; 1756 1757 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1758 return NULL; 1759 1760 /* base block fetch */ 1761 for (i = 0; i < 4; i++) { 1762 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1763 goto out; 1764 if (drm_edid_block_valid(edid, 0, false, 1765 &connector->edid_corrupt)) 1766 break; 1767 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1768 connector->null_edid_counter++; 1769 goto carp; 1770 } 1771 } 1772 if (i == 4) 1773 goto carp; 1774 1775 /* if there's no extensions, we're done */ 1776 valid_extensions = edid[0x7e]; 1777 if (valid_extensions == 0) 1778 return (struct edid *)edid; 1779 1780 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1781 if (!new) 1782 goto out; 1783 edid = new; 1784 1785 for (j = 1; j <= edid[0x7e]; j++) { 1786 u8 *block = edid + j * EDID_LENGTH; 1787 1788 for (i = 0; i < 4; i++) { 1789 if (get_edid_block(data, block, j, EDID_LENGTH)) 1790 goto out; 1791 if (drm_edid_block_valid(block, j, false, NULL)) 1792 break; 1793 } 1794 1795 if (i == 4) 1796 valid_extensions--; 1797 } 1798 1799 if (valid_extensions != edid[0x7e]) { 1800 u8 *base; 1801 1802 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1803 1804 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1805 edid[0x7e] = valid_extensions; 1806 1807 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1808 GFP_KERNEL); 1809 if (!new) 1810 goto out; 1811 1812 base = new; 1813 for (i = 0; i <= edid[0x7e]; i++) { 1814 u8 *block = edid + i * EDID_LENGTH; 1815 1816 if (!drm_edid_block_valid(block, i, false, NULL)) 1817 continue; 1818 1819 memcpy(base, block, EDID_LENGTH); 1820 base += EDID_LENGTH; 1821 } 1822 1823 kfree(edid); 1824 edid = new; 1825 } 1826 1827 return (struct edid *)edid; 1828 1829 carp: 1830 connector_bad_edid(connector, edid, 1); 1831 out: 1832 kfree(edid); 1833 return NULL; 1834 } 1835 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1836 1837 /** 1838 * drm_probe_ddc() - probe DDC presence 1839 * @adapter: I2C adapter to probe 1840 * 1841 * Return: True on success, false on failure. 1842 */ 1843 bool 1844 drm_probe_ddc(struct i2c_adapter *adapter) 1845 { 1846 unsigned char out; 1847 1848 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1849 } 1850 EXPORT_SYMBOL(drm_probe_ddc); 1851 1852 /** 1853 * drm_get_edid - get EDID data, if available 1854 * @connector: connector we're probing 1855 * @adapter: I2C adapter to use for DDC 1856 * 1857 * Poke the given I2C channel to grab EDID data if possible. If found, 1858 * attach it to the connector. 1859 * 1860 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1861 */ 1862 struct edid *drm_get_edid(struct drm_connector *connector, 1863 struct i2c_adapter *adapter) 1864 { 1865 struct edid *edid; 1866 1867 if (connector->force == DRM_FORCE_OFF) 1868 return NULL; 1869 1870 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1871 return NULL; 1872 1873 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1874 if (edid) 1875 drm_get_displayid(connector, edid); 1876 return edid; 1877 } 1878 EXPORT_SYMBOL(drm_get_edid); 1879 1880 /** 1881 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1882 * @connector: connector we're probing 1883 * @adapter: I2C adapter to use for DDC 1884 * 1885 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1886 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1887 * switch DDC to the GPU which is retrieving EDID. 1888 * 1889 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1890 */ 1891 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1892 struct i2c_adapter *adapter) 1893 { 1894 struct pci_dev *pdev = connector->dev->pdev; 1895 struct edid *edid; 1896 1897 vga_switcheroo_lock_ddc(pdev); 1898 edid = drm_get_edid(connector, adapter); 1899 vga_switcheroo_unlock_ddc(pdev); 1900 1901 return edid; 1902 } 1903 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1904 1905 /** 1906 * drm_edid_duplicate - duplicate an EDID and the extensions 1907 * @edid: EDID to duplicate 1908 * 1909 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1910 */ 1911 struct edid *drm_edid_duplicate(const struct edid *edid) 1912 { 1913 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1914 } 1915 EXPORT_SYMBOL(drm_edid_duplicate); 1916 1917 /*** EDID parsing ***/ 1918 1919 /** 1920 * edid_vendor - match a string against EDID's obfuscated vendor field 1921 * @edid: EDID to match 1922 * @vendor: vendor string 1923 * 1924 * Returns true if @vendor is in @edid, false otherwise 1925 */ 1926 static bool edid_vendor(const struct edid *edid, const char *vendor) 1927 { 1928 char edid_vendor[3]; 1929 1930 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1931 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1932 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1933 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1934 1935 return !strncmp(edid_vendor, vendor, 3); 1936 } 1937 1938 /** 1939 * edid_get_quirks - return quirk flags for a given EDID 1940 * @edid: EDID to process 1941 * 1942 * This tells subsequent routines what fixes they need to apply. 1943 */ 1944 static u32 edid_get_quirks(const struct edid *edid) 1945 { 1946 const struct edid_quirk *quirk; 1947 int i; 1948 1949 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1950 quirk = &edid_quirk_list[i]; 1951 1952 if (edid_vendor(edid, quirk->vendor) && 1953 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1954 return quirk->quirks; 1955 } 1956 1957 return 0; 1958 } 1959 1960 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1961 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1962 1963 /** 1964 * edid_fixup_preferred - set preferred modes based on quirk list 1965 * @connector: has mode list to fix up 1966 * @quirks: quirks list 1967 * 1968 * Walk the mode list for @connector, clearing the preferred status 1969 * on existing modes and setting it anew for the right mode ala @quirks. 1970 */ 1971 static void edid_fixup_preferred(struct drm_connector *connector, 1972 u32 quirks) 1973 { 1974 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1975 int target_refresh = 0; 1976 int cur_vrefresh, preferred_vrefresh; 1977 1978 if (list_empty(&connector->probed_modes)) 1979 return; 1980 1981 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1982 target_refresh = 60; 1983 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1984 target_refresh = 75; 1985 1986 preferred_mode = list_first_entry(&connector->probed_modes, 1987 struct drm_display_mode, head); 1988 1989 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1990 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1991 1992 if (cur_mode == preferred_mode) 1993 continue; 1994 1995 /* Largest mode is preferred */ 1996 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1997 preferred_mode = cur_mode; 1998 1999 cur_vrefresh = cur_mode->vrefresh ? 2000 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 2001 preferred_vrefresh = preferred_mode->vrefresh ? 2002 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 2003 /* At a given size, try to get closest to target refresh */ 2004 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2005 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2006 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2007 preferred_mode = cur_mode; 2008 } 2009 } 2010 2011 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2012 } 2013 2014 static bool 2015 mode_is_rb(const struct drm_display_mode *mode) 2016 { 2017 return (mode->htotal - mode->hdisplay == 160) && 2018 (mode->hsync_end - mode->hdisplay == 80) && 2019 (mode->hsync_end - mode->hsync_start == 32) && 2020 (mode->vsync_start - mode->vdisplay == 3); 2021 } 2022 2023 /* 2024 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2025 * @dev: Device to duplicate against 2026 * @hsize: Mode width 2027 * @vsize: Mode height 2028 * @fresh: Mode refresh rate 2029 * @rb: Mode reduced-blanking-ness 2030 * 2031 * Walk the DMT mode list looking for a match for the given parameters. 2032 * 2033 * Return: A newly allocated copy of the mode, or NULL if not found. 2034 */ 2035 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2036 int hsize, int vsize, int fresh, 2037 bool rb) 2038 { 2039 int i; 2040 2041 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2042 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2043 if (hsize != ptr->hdisplay) 2044 continue; 2045 if (vsize != ptr->vdisplay) 2046 continue; 2047 if (fresh != drm_mode_vrefresh(ptr)) 2048 continue; 2049 if (rb != mode_is_rb(ptr)) 2050 continue; 2051 2052 return drm_mode_duplicate(dev, ptr); 2053 } 2054 2055 return NULL; 2056 } 2057 EXPORT_SYMBOL(drm_mode_find_dmt); 2058 2059 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2060 2061 static void 2062 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2063 { 2064 int i, n = 0; 2065 u8 d = ext[0x02]; 2066 u8 *det_base = ext + d; 2067 2068 n = (127 - d) / 18; 2069 for (i = 0; i < n; i++) 2070 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2071 } 2072 2073 static void 2074 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2075 { 2076 unsigned int i, n = min((int)ext[0x02], 6); 2077 u8 *det_base = ext + 5; 2078 2079 if (ext[0x01] != 1) 2080 return; /* unknown version */ 2081 2082 for (i = 0; i < n; i++) 2083 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2084 } 2085 2086 static void 2087 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2088 { 2089 int i; 2090 struct edid *edid = (struct edid *)raw_edid; 2091 2092 if (edid == NULL) 2093 return; 2094 2095 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2096 cb(&(edid->detailed_timings[i]), closure); 2097 2098 for (i = 1; i <= raw_edid[0x7e]; i++) { 2099 u8 *ext = raw_edid + (i * EDID_LENGTH); 2100 switch (*ext) { 2101 case CEA_EXT: 2102 cea_for_each_detailed_block(ext, cb, closure); 2103 break; 2104 case VTB_EXT: 2105 vtb_for_each_detailed_block(ext, cb, closure); 2106 break; 2107 default: 2108 break; 2109 } 2110 } 2111 } 2112 2113 static void 2114 is_rb(struct detailed_timing *t, void *data) 2115 { 2116 u8 *r = (u8 *)t; 2117 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 2118 if (r[15] & 0x10) 2119 *(bool *)data = true; 2120 } 2121 2122 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2123 static bool 2124 drm_monitor_supports_rb(struct edid *edid) 2125 { 2126 if (edid->revision >= 4) { 2127 bool ret = false; 2128 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2129 return ret; 2130 } 2131 2132 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2133 } 2134 2135 static void 2136 find_gtf2(struct detailed_timing *t, void *data) 2137 { 2138 u8 *r = (u8 *)t; 2139 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 2140 *(u8 **)data = r; 2141 } 2142 2143 /* Secondary GTF curve kicks in above some break frequency */ 2144 static int 2145 drm_gtf2_hbreak(struct edid *edid) 2146 { 2147 u8 *r = NULL; 2148 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2149 return r ? (r[12] * 2) : 0; 2150 } 2151 2152 static int 2153 drm_gtf2_2c(struct edid *edid) 2154 { 2155 u8 *r = NULL; 2156 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2157 return r ? r[13] : 0; 2158 } 2159 2160 static int 2161 drm_gtf2_m(struct edid *edid) 2162 { 2163 u8 *r = NULL; 2164 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2165 return r ? (r[15] << 8) + r[14] : 0; 2166 } 2167 2168 static int 2169 drm_gtf2_k(struct edid *edid) 2170 { 2171 u8 *r = NULL; 2172 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2173 return r ? r[16] : 0; 2174 } 2175 2176 static int 2177 drm_gtf2_2j(struct edid *edid) 2178 { 2179 u8 *r = NULL; 2180 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2181 return r ? r[17] : 0; 2182 } 2183 2184 /** 2185 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2186 * @edid: EDID block to scan 2187 */ 2188 static int standard_timing_level(struct edid *edid) 2189 { 2190 if (edid->revision >= 2) { 2191 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2192 return LEVEL_CVT; 2193 if (drm_gtf2_hbreak(edid)) 2194 return LEVEL_GTF2; 2195 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2196 return LEVEL_GTF; 2197 } 2198 return LEVEL_DMT; 2199 } 2200 2201 /* 2202 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2203 * monitors fill with ascii space (0x20) instead. 2204 */ 2205 static int 2206 bad_std_timing(u8 a, u8 b) 2207 { 2208 return (a == 0x00 && b == 0x00) || 2209 (a == 0x01 && b == 0x01) || 2210 (a == 0x20 && b == 0x20); 2211 } 2212 2213 /** 2214 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2215 * @connector: connector of for the EDID block 2216 * @edid: EDID block to scan 2217 * @t: standard timing params 2218 * 2219 * Take the standard timing params (in this case width, aspect, and refresh) 2220 * and convert them into a real mode using CVT/GTF/DMT. 2221 */ 2222 static struct drm_display_mode * 2223 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2224 struct std_timing *t) 2225 { 2226 struct drm_device *dev = connector->dev; 2227 struct drm_display_mode *m, *mode = NULL; 2228 int hsize, vsize; 2229 int vrefresh_rate; 2230 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2231 >> EDID_TIMING_ASPECT_SHIFT; 2232 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2233 >> EDID_TIMING_VFREQ_SHIFT; 2234 int timing_level = standard_timing_level(edid); 2235 2236 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2237 return NULL; 2238 2239 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2240 hsize = t->hsize * 8 + 248; 2241 /* vrefresh_rate = vfreq + 60 */ 2242 vrefresh_rate = vfreq + 60; 2243 /* the vdisplay is calculated based on the aspect ratio */ 2244 if (aspect_ratio == 0) { 2245 if (edid->revision < 3) 2246 vsize = hsize; 2247 else 2248 vsize = (hsize * 10) / 16; 2249 } else if (aspect_ratio == 1) 2250 vsize = (hsize * 3) / 4; 2251 else if (aspect_ratio == 2) 2252 vsize = (hsize * 4) / 5; 2253 else 2254 vsize = (hsize * 9) / 16; 2255 2256 /* HDTV hack, part 1 */ 2257 if (vrefresh_rate == 60 && 2258 ((hsize == 1360 && vsize == 765) || 2259 (hsize == 1368 && vsize == 769))) { 2260 hsize = 1366; 2261 vsize = 768; 2262 } 2263 2264 /* 2265 * If this connector already has a mode for this size and refresh 2266 * rate (because it came from detailed or CVT info), use that 2267 * instead. This way we don't have to guess at interlace or 2268 * reduced blanking. 2269 */ 2270 list_for_each_entry(m, &connector->probed_modes, head) 2271 if (m->hdisplay == hsize && m->vdisplay == vsize && 2272 drm_mode_vrefresh(m) == vrefresh_rate) 2273 return NULL; 2274 2275 /* HDTV hack, part 2 */ 2276 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2277 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2278 false); 2279 if (!mode) 2280 return NULL; 2281 mode->hdisplay = 1366; 2282 mode->hsync_start = mode->hsync_start - 1; 2283 mode->hsync_end = mode->hsync_end - 1; 2284 return mode; 2285 } 2286 2287 /* check whether it can be found in default mode table */ 2288 if (drm_monitor_supports_rb(edid)) { 2289 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2290 true); 2291 if (mode) 2292 return mode; 2293 } 2294 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2295 if (mode) 2296 return mode; 2297 2298 /* okay, generate it */ 2299 switch (timing_level) { 2300 case LEVEL_DMT: 2301 break; 2302 case LEVEL_GTF: 2303 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2304 break; 2305 case LEVEL_GTF2: 2306 /* 2307 * This is potentially wrong if there's ever a monitor with 2308 * more than one ranges section, each claiming a different 2309 * secondary GTF curve. Please don't do that. 2310 */ 2311 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2312 if (!mode) 2313 return NULL; 2314 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2315 drm_mode_destroy(dev, mode); 2316 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2317 vrefresh_rate, 0, 0, 2318 drm_gtf2_m(edid), 2319 drm_gtf2_2c(edid), 2320 drm_gtf2_k(edid), 2321 drm_gtf2_2j(edid)); 2322 } 2323 break; 2324 case LEVEL_CVT: 2325 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2326 false); 2327 break; 2328 } 2329 return mode; 2330 } 2331 2332 /* 2333 * EDID is delightfully ambiguous about how interlaced modes are to be 2334 * encoded. Our internal representation is of frame height, but some 2335 * HDTV detailed timings are encoded as field height. 2336 * 2337 * The format list here is from CEA, in frame size. Technically we 2338 * should be checking refresh rate too. Whatever. 2339 */ 2340 static void 2341 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2342 struct detailed_pixel_timing *pt) 2343 { 2344 int i; 2345 static const struct { 2346 int w, h; 2347 } cea_interlaced[] = { 2348 { 1920, 1080 }, 2349 { 720, 480 }, 2350 { 1440, 480 }, 2351 { 2880, 480 }, 2352 { 720, 576 }, 2353 { 1440, 576 }, 2354 { 2880, 576 }, 2355 }; 2356 2357 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2358 return; 2359 2360 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2361 if ((mode->hdisplay == cea_interlaced[i].w) && 2362 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2363 mode->vdisplay *= 2; 2364 mode->vsync_start *= 2; 2365 mode->vsync_end *= 2; 2366 mode->vtotal *= 2; 2367 mode->vtotal |= 1; 2368 } 2369 } 2370 2371 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2372 } 2373 2374 /** 2375 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2376 * @dev: DRM device (needed to create new mode) 2377 * @edid: EDID block 2378 * @timing: EDID detailed timing info 2379 * @quirks: quirks to apply 2380 * 2381 * An EDID detailed timing block contains enough info for us to create and 2382 * return a new struct drm_display_mode. 2383 */ 2384 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2385 struct edid *edid, 2386 struct detailed_timing *timing, 2387 u32 quirks) 2388 { 2389 struct drm_display_mode *mode; 2390 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2391 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2392 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2393 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2394 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2395 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2396 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2397 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2398 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2399 2400 /* ignore tiny modes */ 2401 if (hactive < 64 || vactive < 64) 2402 return NULL; 2403 2404 if (pt->misc & DRM_EDID_PT_STEREO) { 2405 DRM_DEBUG_KMS("stereo mode not supported\n"); 2406 return NULL; 2407 } 2408 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2409 DRM_DEBUG_KMS("composite sync not supported\n"); 2410 } 2411 2412 /* it is incorrect if hsync/vsync width is zero */ 2413 if (!hsync_pulse_width || !vsync_pulse_width) { 2414 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2415 "Wrong Hsync/Vsync pulse width\n"); 2416 return NULL; 2417 } 2418 2419 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2420 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2421 if (!mode) 2422 return NULL; 2423 2424 goto set_size; 2425 } 2426 2427 mode = drm_mode_create(dev); 2428 if (!mode) 2429 return NULL; 2430 2431 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2432 timing->pixel_clock = cpu_to_le16(1088); 2433 2434 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2435 2436 mode->hdisplay = hactive; 2437 mode->hsync_start = mode->hdisplay + hsync_offset; 2438 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2439 mode->htotal = mode->hdisplay + hblank; 2440 2441 mode->vdisplay = vactive; 2442 mode->vsync_start = mode->vdisplay + vsync_offset; 2443 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2444 mode->vtotal = mode->vdisplay + vblank; 2445 2446 /* Some EDIDs have bogus h/vtotal values */ 2447 if (mode->hsync_end > mode->htotal) 2448 mode->htotal = mode->hsync_end + 1; 2449 if (mode->vsync_end > mode->vtotal) 2450 mode->vtotal = mode->vsync_end + 1; 2451 2452 drm_mode_do_interlace_quirk(mode, pt); 2453 2454 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2455 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2456 } 2457 2458 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2459 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2460 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2461 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2462 2463 set_size: 2464 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2465 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2466 2467 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2468 mode->width_mm *= 10; 2469 mode->height_mm *= 10; 2470 } 2471 2472 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2473 mode->width_mm = edid->width_cm * 10; 2474 mode->height_mm = edid->height_cm * 10; 2475 } 2476 2477 mode->type = DRM_MODE_TYPE_DRIVER; 2478 mode->vrefresh = drm_mode_vrefresh(mode); 2479 drm_mode_set_name(mode); 2480 2481 return mode; 2482 } 2483 2484 static bool 2485 mode_in_hsync_range(const struct drm_display_mode *mode, 2486 struct edid *edid, u8 *t) 2487 { 2488 int hsync, hmin, hmax; 2489 2490 hmin = t[7]; 2491 if (edid->revision >= 4) 2492 hmin += ((t[4] & 0x04) ? 255 : 0); 2493 hmax = t[8]; 2494 if (edid->revision >= 4) 2495 hmax += ((t[4] & 0x08) ? 255 : 0); 2496 hsync = drm_mode_hsync(mode); 2497 2498 return (hsync <= hmax && hsync >= hmin); 2499 } 2500 2501 static bool 2502 mode_in_vsync_range(const struct drm_display_mode *mode, 2503 struct edid *edid, u8 *t) 2504 { 2505 int vsync, vmin, vmax; 2506 2507 vmin = t[5]; 2508 if (edid->revision >= 4) 2509 vmin += ((t[4] & 0x01) ? 255 : 0); 2510 vmax = t[6]; 2511 if (edid->revision >= 4) 2512 vmax += ((t[4] & 0x02) ? 255 : 0); 2513 vsync = drm_mode_vrefresh(mode); 2514 2515 return (vsync <= vmax && vsync >= vmin); 2516 } 2517 2518 static u32 2519 range_pixel_clock(struct edid *edid, u8 *t) 2520 { 2521 /* unspecified */ 2522 if (t[9] == 0 || t[9] == 255) 2523 return 0; 2524 2525 /* 1.4 with CVT support gives us real precision, yay */ 2526 if (edid->revision >= 4 && t[10] == 0x04) 2527 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2528 2529 /* 1.3 is pathetic, so fuzz up a bit */ 2530 return t[9] * 10000 + 5001; 2531 } 2532 2533 static bool 2534 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2535 struct detailed_timing *timing) 2536 { 2537 u32 max_clock; 2538 u8 *t = (u8 *)timing; 2539 2540 if (!mode_in_hsync_range(mode, edid, t)) 2541 return false; 2542 2543 if (!mode_in_vsync_range(mode, edid, t)) 2544 return false; 2545 2546 if ((max_clock = range_pixel_clock(edid, t))) 2547 if (mode->clock > max_clock) 2548 return false; 2549 2550 /* 1.4 max horizontal check */ 2551 if (edid->revision >= 4 && t[10] == 0x04) 2552 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2553 return false; 2554 2555 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2556 return false; 2557 2558 return true; 2559 } 2560 2561 static bool valid_inferred_mode(const struct drm_connector *connector, 2562 const struct drm_display_mode *mode) 2563 { 2564 const struct drm_display_mode *m; 2565 bool ok = false; 2566 2567 list_for_each_entry(m, &connector->probed_modes, head) { 2568 if (mode->hdisplay == m->hdisplay && 2569 mode->vdisplay == m->vdisplay && 2570 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2571 return false; /* duplicated */ 2572 if (mode->hdisplay <= m->hdisplay && 2573 mode->vdisplay <= m->vdisplay) 2574 ok = true; 2575 } 2576 return ok; 2577 } 2578 2579 static int 2580 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2581 struct detailed_timing *timing) 2582 { 2583 int i, modes = 0; 2584 struct drm_display_mode *newmode; 2585 struct drm_device *dev = connector->dev; 2586 2587 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2588 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2589 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2590 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2591 if (newmode) { 2592 drm_mode_probed_add(connector, newmode); 2593 modes++; 2594 } 2595 } 2596 } 2597 2598 return modes; 2599 } 2600 2601 /* fix up 1366x768 mode from 1368x768; 2602 * GFT/CVT can't express 1366 width which isn't dividable by 8 2603 */ 2604 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2605 { 2606 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2607 mode->hdisplay = 1366; 2608 mode->hsync_start--; 2609 mode->hsync_end--; 2610 drm_mode_set_name(mode); 2611 } 2612 } 2613 2614 static int 2615 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2616 struct detailed_timing *timing) 2617 { 2618 int i, modes = 0; 2619 struct drm_display_mode *newmode; 2620 struct drm_device *dev = connector->dev; 2621 2622 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2623 const struct minimode *m = &extra_modes[i]; 2624 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2625 if (!newmode) 2626 return modes; 2627 2628 drm_mode_fixup_1366x768(newmode); 2629 if (!mode_in_range(newmode, edid, timing) || 2630 !valid_inferred_mode(connector, newmode)) { 2631 drm_mode_destroy(dev, newmode); 2632 continue; 2633 } 2634 2635 drm_mode_probed_add(connector, newmode); 2636 modes++; 2637 } 2638 2639 return modes; 2640 } 2641 2642 static int 2643 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2644 struct detailed_timing *timing) 2645 { 2646 int i, modes = 0; 2647 struct drm_display_mode *newmode; 2648 struct drm_device *dev = connector->dev; 2649 bool rb = drm_monitor_supports_rb(edid); 2650 2651 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2652 const struct minimode *m = &extra_modes[i]; 2653 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2654 if (!newmode) 2655 return modes; 2656 2657 drm_mode_fixup_1366x768(newmode); 2658 if (!mode_in_range(newmode, edid, timing) || 2659 !valid_inferred_mode(connector, newmode)) { 2660 drm_mode_destroy(dev, newmode); 2661 continue; 2662 } 2663 2664 drm_mode_probed_add(connector, newmode); 2665 modes++; 2666 } 2667 2668 return modes; 2669 } 2670 2671 static void 2672 do_inferred_modes(struct detailed_timing *timing, void *c) 2673 { 2674 struct detailed_mode_closure *closure = c; 2675 struct detailed_non_pixel *data = &timing->data.other_data; 2676 struct detailed_data_monitor_range *range = &data->data.range; 2677 2678 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2679 return; 2680 2681 closure->modes += drm_dmt_modes_for_range(closure->connector, 2682 closure->edid, 2683 timing); 2684 2685 if (!version_greater(closure->edid, 1, 1)) 2686 return; /* GTF not defined yet */ 2687 2688 switch (range->flags) { 2689 case 0x02: /* secondary gtf, XXX could do more */ 2690 case 0x00: /* default gtf */ 2691 closure->modes += drm_gtf_modes_for_range(closure->connector, 2692 closure->edid, 2693 timing); 2694 break; 2695 case 0x04: /* cvt, only in 1.4+ */ 2696 if (!version_greater(closure->edid, 1, 3)) 2697 break; 2698 2699 closure->modes += drm_cvt_modes_for_range(closure->connector, 2700 closure->edid, 2701 timing); 2702 break; 2703 case 0x01: /* just the ranges, no formula */ 2704 default: 2705 break; 2706 } 2707 } 2708 2709 static int 2710 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2711 { 2712 struct detailed_mode_closure closure = { 2713 .connector = connector, 2714 .edid = edid, 2715 }; 2716 2717 if (version_greater(edid, 1, 0)) 2718 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2719 &closure); 2720 2721 return closure.modes; 2722 } 2723 2724 static int 2725 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2726 { 2727 int i, j, m, modes = 0; 2728 struct drm_display_mode *mode; 2729 u8 *est = ((u8 *)timing) + 6; 2730 2731 for (i = 0; i < 6; i++) { 2732 for (j = 7; j >= 0; j--) { 2733 m = (i * 8) + (7 - j); 2734 if (m >= ARRAY_SIZE(est3_modes)) 2735 break; 2736 if (est[i] & (1 << j)) { 2737 mode = drm_mode_find_dmt(connector->dev, 2738 est3_modes[m].w, 2739 est3_modes[m].h, 2740 est3_modes[m].r, 2741 est3_modes[m].rb); 2742 if (mode) { 2743 drm_mode_probed_add(connector, mode); 2744 modes++; 2745 } 2746 } 2747 } 2748 } 2749 2750 return modes; 2751 } 2752 2753 static void 2754 do_established_modes(struct detailed_timing *timing, void *c) 2755 { 2756 struct detailed_mode_closure *closure = c; 2757 struct detailed_non_pixel *data = &timing->data.other_data; 2758 2759 if (data->type == EDID_DETAIL_EST_TIMINGS) 2760 closure->modes += drm_est3_modes(closure->connector, timing); 2761 } 2762 2763 /** 2764 * add_established_modes - get est. modes from EDID and add them 2765 * @connector: connector to add mode(s) to 2766 * @edid: EDID block to scan 2767 * 2768 * Each EDID block contains a bitmap of the supported "established modes" list 2769 * (defined above). Tease them out and add them to the global modes list. 2770 */ 2771 static int 2772 add_established_modes(struct drm_connector *connector, struct edid *edid) 2773 { 2774 struct drm_device *dev = connector->dev; 2775 unsigned long est_bits = edid->established_timings.t1 | 2776 (edid->established_timings.t2 << 8) | 2777 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2778 int i, modes = 0; 2779 struct detailed_mode_closure closure = { 2780 .connector = connector, 2781 .edid = edid, 2782 }; 2783 2784 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2785 if (est_bits & (1<<i)) { 2786 struct drm_display_mode *newmode; 2787 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2788 if (newmode) { 2789 drm_mode_probed_add(connector, newmode); 2790 modes++; 2791 } 2792 } 2793 } 2794 2795 if (version_greater(edid, 1, 0)) 2796 drm_for_each_detailed_block((u8 *)edid, 2797 do_established_modes, &closure); 2798 2799 return modes + closure.modes; 2800 } 2801 2802 static void 2803 do_standard_modes(struct detailed_timing *timing, void *c) 2804 { 2805 struct detailed_mode_closure *closure = c; 2806 struct detailed_non_pixel *data = &timing->data.other_data; 2807 struct drm_connector *connector = closure->connector; 2808 struct edid *edid = closure->edid; 2809 2810 if (data->type == EDID_DETAIL_STD_MODES) { 2811 int i; 2812 for (i = 0; i < 6; i++) { 2813 struct std_timing *std; 2814 struct drm_display_mode *newmode; 2815 2816 std = &data->data.timings[i]; 2817 newmode = drm_mode_std(connector, edid, std); 2818 if (newmode) { 2819 drm_mode_probed_add(connector, newmode); 2820 closure->modes++; 2821 } 2822 } 2823 } 2824 } 2825 2826 /** 2827 * add_standard_modes - get std. modes from EDID and add them 2828 * @connector: connector to add mode(s) to 2829 * @edid: EDID block to scan 2830 * 2831 * Standard modes can be calculated using the appropriate standard (DMT, 2832 * GTF or CVT. Grab them from @edid and add them to the list. 2833 */ 2834 static int 2835 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2836 { 2837 int i, modes = 0; 2838 struct detailed_mode_closure closure = { 2839 .connector = connector, 2840 .edid = edid, 2841 }; 2842 2843 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2844 struct drm_display_mode *newmode; 2845 2846 newmode = drm_mode_std(connector, edid, 2847 &edid->standard_timings[i]); 2848 if (newmode) { 2849 drm_mode_probed_add(connector, newmode); 2850 modes++; 2851 } 2852 } 2853 2854 if (version_greater(edid, 1, 0)) 2855 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2856 &closure); 2857 2858 /* XXX should also look for standard codes in VTB blocks */ 2859 2860 return modes + closure.modes; 2861 } 2862 2863 static int drm_cvt_modes(struct drm_connector *connector, 2864 struct detailed_timing *timing) 2865 { 2866 int i, j, modes = 0; 2867 struct drm_display_mode *newmode; 2868 struct drm_device *dev = connector->dev; 2869 struct cvt_timing *cvt; 2870 const int rates[] = { 60, 85, 75, 60, 50 }; 2871 const u8 empty[3] = { 0, 0, 0 }; 2872 2873 for (i = 0; i < 4; i++) { 2874 int uninitialized_var(width), height; 2875 cvt = &(timing->data.other_data.data.cvt[i]); 2876 2877 if (!memcmp(cvt->code, empty, 3)) 2878 continue; 2879 2880 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2881 switch (cvt->code[1] & 0x0c) { 2882 case 0x00: 2883 width = height * 4 / 3; 2884 break; 2885 case 0x04: 2886 width = height * 16 / 9; 2887 break; 2888 case 0x08: 2889 width = height * 16 / 10; 2890 break; 2891 case 0x0c: 2892 width = height * 15 / 9; 2893 break; 2894 } 2895 2896 for (j = 1; j < 5; j++) { 2897 if (cvt->code[2] & (1 << j)) { 2898 newmode = drm_cvt_mode(dev, width, height, 2899 rates[j], j == 0, 2900 false, false); 2901 if (newmode) { 2902 drm_mode_probed_add(connector, newmode); 2903 modes++; 2904 } 2905 } 2906 } 2907 } 2908 2909 return modes; 2910 } 2911 2912 static void 2913 do_cvt_mode(struct detailed_timing *timing, void *c) 2914 { 2915 struct detailed_mode_closure *closure = c; 2916 struct detailed_non_pixel *data = &timing->data.other_data; 2917 2918 if (data->type == EDID_DETAIL_CVT_3BYTE) 2919 closure->modes += drm_cvt_modes(closure->connector, timing); 2920 } 2921 2922 static int 2923 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2924 { 2925 struct detailed_mode_closure closure = { 2926 .connector = connector, 2927 .edid = edid, 2928 }; 2929 2930 if (version_greater(edid, 1, 2)) 2931 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2932 2933 /* XXX should also look for CVT codes in VTB blocks */ 2934 2935 return closure.modes; 2936 } 2937 2938 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2939 2940 static void 2941 do_detailed_mode(struct detailed_timing *timing, void *c) 2942 { 2943 struct detailed_mode_closure *closure = c; 2944 struct drm_display_mode *newmode; 2945 2946 if (timing->pixel_clock) { 2947 newmode = drm_mode_detailed(closure->connector->dev, 2948 closure->edid, timing, 2949 closure->quirks); 2950 if (!newmode) 2951 return; 2952 2953 if (closure->preferred) 2954 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2955 2956 /* 2957 * Detailed modes are limited to 10kHz pixel clock resolution, 2958 * so fix up anything that looks like CEA/HDMI mode, but the clock 2959 * is just slightly off. 2960 */ 2961 fixup_detailed_cea_mode_clock(newmode); 2962 2963 drm_mode_probed_add(closure->connector, newmode); 2964 closure->modes++; 2965 closure->preferred = false; 2966 } 2967 } 2968 2969 /* 2970 * add_detailed_modes - Add modes from detailed timings 2971 * @connector: attached connector 2972 * @edid: EDID block to scan 2973 * @quirks: quirks to apply 2974 */ 2975 static int 2976 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2977 u32 quirks) 2978 { 2979 struct detailed_mode_closure closure = { 2980 .connector = connector, 2981 .edid = edid, 2982 .preferred = true, 2983 .quirks = quirks, 2984 }; 2985 2986 if (closure.preferred && !version_greater(edid, 1, 3)) 2987 closure.preferred = 2988 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2989 2990 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2991 2992 return closure.modes; 2993 } 2994 2995 #define AUDIO_BLOCK 0x01 2996 #define VIDEO_BLOCK 0x02 2997 #define VENDOR_BLOCK 0x03 2998 #define SPEAKER_BLOCK 0x04 2999 #define HDR_STATIC_METADATA_BLOCK 0x6 3000 #define USE_EXTENDED_TAG 0x07 3001 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3002 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3003 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3004 #define EDID_BASIC_AUDIO (1 << 6) 3005 #define EDID_CEA_YCRCB444 (1 << 5) 3006 #define EDID_CEA_YCRCB422 (1 << 4) 3007 #define EDID_CEA_VCDB_QS (1 << 6) 3008 3009 /* 3010 * Search EDID for CEA extension block. 3011 */ 3012 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3013 { 3014 u8 *edid_ext = NULL; 3015 int i; 3016 3017 /* No EDID or EDID extensions */ 3018 if (edid == NULL || edid->extensions == 0) 3019 return NULL; 3020 3021 /* Find CEA extension */ 3022 for (i = 0; i < edid->extensions; i++) { 3023 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3024 if (edid_ext[0] == ext_id) 3025 break; 3026 } 3027 3028 if (i == edid->extensions) 3029 return NULL; 3030 3031 return edid_ext; 3032 } 3033 3034 3035 static u8 *drm_find_displayid_extension(const struct edid *edid) 3036 { 3037 return drm_find_edid_extension(edid, DISPLAYID_EXT); 3038 } 3039 3040 static u8 *drm_find_cea_extension(const struct edid *edid) 3041 { 3042 int ret; 3043 int idx = 1; 3044 int length = EDID_LENGTH; 3045 struct displayid_block *block; 3046 u8 *cea; 3047 u8 *displayid; 3048 3049 /* Look for a top level CEA extension block */ 3050 cea = drm_find_edid_extension(edid, CEA_EXT); 3051 if (cea) 3052 return cea; 3053 3054 /* CEA blocks can also be found embedded in a DisplayID block */ 3055 displayid = drm_find_displayid_extension(edid); 3056 if (!displayid) 3057 return NULL; 3058 3059 ret = validate_displayid(displayid, length, idx); 3060 if (ret) 3061 return NULL; 3062 3063 idx += sizeof(struct displayid_hdr); 3064 for_each_displayid_db(displayid, block, idx, length) { 3065 if (block->tag == DATA_BLOCK_CTA) { 3066 cea = (u8 *)block; 3067 break; 3068 } 3069 } 3070 3071 return cea; 3072 } 3073 3074 /* 3075 * Calculate the alternate clock for the CEA mode 3076 * (60Hz vs. 59.94Hz etc.) 3077 */ 3078 static unsigned int 3079 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3080 { 3081 unsigned int clock = cea_mode->clock; 3082 3083 if (cea_mode->vrefresh % 6 != 0) 3084 return clock; 3085 3086 /* 3087 * edid_cea_modes contains the 59.94Hz 3088 * variant for 240 and 480 line modes, 3089 * and the 60Hz variant otherwise. 3090 */ 3091 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3092 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3093 else 3094 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3095 3096 return clock; 3097 } 3098 3099 static bool 3100 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3101 { 3102 /* 3103 * For certain VICs the spec allows the vertical 3104 * front porch to vary by one or two lines. 3105 * 3106 * cea_modes[] stores the variant with the shortest 3107 * vertical front porch. We can adjust the mode to 3108 * get the other variants by simply increasing the 3109 * vertical front porch length. 3110 */ 3111 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 3112 edid_cea_modes[9].vtotal != 262 || 3113 edid_cea_modes[12].vtotal != 262 || 3114 edid_cea_modes[13].vtotal != 262 || 3115 edid_cea_modes[23].vtotal != 312 || 3116 edid_cea_modes[24].vtotal != 312 || 3117 edid_cea_modes[27].vtotal != 312 || 3118 edid_cea_modes[28].vtotal != 312); 3119 3120 if (((vic == 8 || vic == 9 || 3121 vic == 12 || vic == 13) && mode->vtotal < 263) || 3122 ((vic == 23 || vic == 24 || 3123 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3124 mode->vsync_start++; 3125 mode->vsync_end++; 3126 mode->vtotal++; 3127 3128 return true; 3129 } 3130 3131 return false; 3132 } 3133 3134 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3135 unsigned int clock_tolerance) 3136 { 3137 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3138 u8 vic; 3139 3140 if (!to_match->clock) 3141 return 0; 3142 3143 if (to_match->picture_aspect_ratio) 3144 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3145 3146 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3147 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3148 unsigned int clock1, clock2; 3149 3150 /* Check both 60Hz and 59.94Hz */ 3151 clock1 = cea_mode.clock; 3152 clock2 = cea_mode_alternate_clock(&cea_mode); 3153 3154 if (abs(to_match->clock - clock1) > clock_tolerance && 3155 abs(to_match->clock - clock2) > clock_tolerance) 3156 continue; 3157 3158 do { 3159 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3160 return vic; 3161 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3162 } 3163 3164 return 0; 3165 } 3166 3167 /** 3168 * drm_match_cea_mode - look for a CEA mode matching given mode 3169 * @to_match: display mode 3170 * 3171 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3172 * mode. 3173 */ 3174 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3175 { 3176 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3177 u8 vic; 3178 3179 if (!to_match->clock) 3180 return 0; 3181 3182 if (to_match->picture_aspect_ratio) 3183 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3184 3185 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3186 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3187 unsigned int clock1, clock2; 3188 3189 /* Check both 60Hz and 59.94Hz */ 3190 clock1 = cea_mode.clock; 3191 clock2 = cea_mode_alternate_clock(&cea_mode); 3192 3193 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3194 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3195 continue; 3196 3197 do { 3198 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3199 return vic; 3200 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3201 } 3202 3203 return 0; 3204 } 3205 EXPORT_SYMBOL(drm_match_cea_mode); 3206 3207 static bool drm_valid_cea_vic(u8 vic) 3208 { 3209 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3210 } 3211 3212 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3213 { 3214 return edid_cea_modes[video_code].picture_aspect_ratio; 3215 } 3216 3217 /* 3218 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3219 * specific block). 3220 * 3221 * It's almost like cea_mode_alternate_clock(), we just need to add an 3222 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3223 * one. 3224 */ 3225 static unsigned int 3226 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3227 { 3228 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3229 return hdmi_mode->clock; 3230 3231 return cea_mode_alternate_clock(hdmi_mode); 3232 } 3233 3234 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3235 unsigned int clock_tolerance) 3236 { 3237 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3238 u8 vic; 3239 3240 if (!to_match->clock) 3241 return 0; 3242 3243 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3244 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3245 unsigned int clock1, clock2; 3246 3247 /* Make sure to also match alternate clocks */ 3248 clock1 = hdmi_mode->clock; 3249 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3250 3251 if (abs(to_match->clock - clock1) > clock_tolerance && 3252 abs(to_match->clock - clock2) > clock_tolerance) 3253 continue; 3254 3255 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3256 return vic; 3257 } 3258 3259 return 0; 3260 } 3261 3262 /* 3263 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3264 * @to_match: display mode 3265 * 3266 * An HDMI mode is one defined in the HDMI vendor specific block. 3267 * 3268 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3269 */ 3270 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3271 { 3272 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3273 u8 vic; 3274 3275 if (!to_match->clock) 3276 return 0; 3277 3278 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3279 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3280 unsigned int clock1, clock2; 3281 3282 /* Make sure to also match alternate clocks */ 3283 clock1 = hdmi_mode->clock; 3284 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3285 3286 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3287 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3288 drm_mode_match(to_match, hdmi_mode, match_flags)) 3289 return vic; 3290 } 3291 return 0; 3292 } 3293 3294 static bool drm_valid_hdmi_vic(u8 vic) 3295 { 3296 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3297 } 3298 3299 static int 3300 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3301 { 3302 struct drm_device *dev = connector->dev; 3303 struct drm_display_mode *mode, *tmp; 3304 LIST_HEAD(list); 3305 int modes = 0; 3306 3307 /* Don't add CEA modes if the CEA extension block is missing */ 3308 if (!drm_find_cea_extension(edid)) 3309 return 0; 3310 3311 /* 3312 * Go through all probed modes and create a new mode 3313 * with the alternate clock for certain CEA modes. 3314 */ 3315 list_for_each_entry(mode, &connector->probed_modes, head) { 3316 const struct drm_display_mode *cea_mode = NULL; 3317 struct drm_display_mode *newmode; 3318 u8 vic = drm_match_cea_mode(mode); 3319 unsigned int clock1, clock2; 3320 3321 if (drm_valid_cea_vic(vic)) { 3322 cea_mode = &edid_cea_modes[vic]; 3323 clock2 = cea_mode_alternate_clock(cea_mode); 3324 } else { 3325 vic = drm_match_hdmi_mode(mode); 3326 if (drm_valid_hdmi_vic(vic)) { 3327 cea_mode = &edid_4k_modes[vic]; 3328 clock2 = hdmi_mode_alternate_clock(cea_mode); 3329 } 3330 } 3331 3332 if (!cea_mode) 3333 continue; 3334 3335 clock1 = cea_mode->clock; 3336 3337 if (clock1 == clock2) 3338 continue; 3339 3340 if (mode->clock != clock1 && mode->clock != clock2) 3341 continue; 3342 3343 newmode = drm_mode_duplicate(dev, cea_mode); 3344 if (!newmode) 3345 continue; 3346 3347 /* Carry over the stereo flags */ 3348 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3349 3350 /* 3351 * The current mode could be either variant. Make 3352 * sure to pick the "other" clock for the new mode. 3353 */ 3354 if (mode->clock != clock1) 3355 newmode->clock = clock1; 3356 else 3357 newmode->clock = clock2; 3358 3359 list_add_tail(&newmode->head, &list); 3360 } 3361 3362 list_for_each_entry_safe(mode, tmp, &list, head) { 3363 list_del(&mode->head); 3364 drm_mode_probed_add(connector, mode); 3365 modes++; 3366 } 3367 3368 return modes; 3369 } 3370 3371 static u8 svd_to_vic(u8 svd) 3372 { 3373 /* 0-6 bit vic, 7th bit native mode indicator */ 3374 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3375 return svd & 127; 3376 3377 return svd; 3378 } 3379 3380 static struct drm_display_mode * 3381 drm_display_mode_from_vic_index(struct drm_connector *connector, 3382 const u8 *video_db, u8 video_len, 3383 u8 video_index) 3384 { 3385 struct drm_device *dev = connector->dev; 3386 struct drm_display_mode *newmode; 3387 u8 vic; 3388 3389 if (video_db == NULL || video_index >= video_len) 3390 return NULL; 3391 3392 /* CEA modes are numbered 1..127 */ 3393 vic = svd_to_vic(video_db[video_index]); 3394 if (!drm_valid_cea_vic(vic)) 3395 return NULL; 3396 3397 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3398 if (!newmode) 3399 return NULL; 3400 3401 newmode->vrefresh = 0; 3402 3403 return newmode; 3404 } 3405 3406 /* 3407 * do_y420vdb_modes - Parse YCBCR 420 only modes 3408 * @connector: connector corresponding to the HDMI sink 3409 * @svds: start of the data block of CEA YCBCR 420 VDB 3410 * @len: length of the CEA YCBCR 420 VDB 3411 * 3412 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3413 * which contains modes which can be supported in YCBCR 420 3414 * output format only. 3415 */ 3416 static int do_y420vdb_modes(struct drm_connector *connector, 3417 const u8 *svds, u8 svds_len) 3418 { 3419 int modes = 0, i; 3420 struct drm_device *dev = connector->dev; 3421 struct drm_display_info *info = &connector->display_info; 3422 struct drm_hdmi_info *hdmi = &info->hdmi; 3423 3424 for (i = 0; i < svds_len; i++) { 3425 u8 vic = svd_to_vic(svds[i]); 3426 struct drm_display_mode *newmode; 3427 3428 if (!drm_valid_cea_vic(vic)) 3429 continue; 3430 3431 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3432 if (!newmode) 3433 break; 3434 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3435 drm_mode_probed_add(connector, newmode); 3436 modes++; 3437 } 3438 3439 if (modes > 0) 3440 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3441 return modes; 3442 } 3443 3444 /* 3445 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3446 * @connector: connector corresponding to the HDMI sink 3447 * @vic: CEA vic for the video mode to be added in the map 3448 * 3449 * Makes an entry for a videomode in the YCBCR 420 bitmap 3450 */ 3451 static void 3452 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3453 { 3454 u8 vic = svd_to_vic(svd); 3455 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3456 3457 if (!drm_valid_cea_vic(vic)) 3458 return; 3459 3460 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3461 } 3462 3463 static int 3464 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3465 { 3466 int i, modes = 0; 3467 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3468 3469 for (i = 0; i < len; i++) { 3470 struct drm_display_mode *mode; 3471 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3472 if (mode) { 3473 /* 3474 * YCBCR420 capability block contains a bitmap which 3475 * gives the index of CEA modes from CEA VDB, which 3476 * can support YCBCR 420 sampling output also (apart 3477 * from RGB/YCBCR444 etc). 3478 * For example, if the bit 0 in bitmap is set, 3479 * first mode in VDB can support YCBCR420 output too. 3480 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3481 */ 3482 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3483 drm_add_cmdb_modes(connector, db[i]); 3484 3485 drm_mode_probed_add(connector, mode); 3486 modes++; 3487 } 3488 } 3489 3490 return modes; 3491 } 3492 3493 struct stereo_mandatory_mode { 3494 int width, height, vrefresh; 3495 unsigned int flags; 3496 }; 3497 3498 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3499 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3500 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3501 { 1920, 1080, 50, 3502 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3503 { 1920, 1080, 60, 3504 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3505 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3506 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3507 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3508 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3509 }; 3510 3511 static bool 3512 stereo_match_mandatory(const struct drm_display_mode *mode, 3513 const struct stereo_mandatory_mode *stereo_mode) 3514 { 3515 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3516 3517 return mode->hdisplay == stereo_mode->width && 3518 mode->vdisplay == stereo_mode->height && 3519 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3520 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3521 } 3522 3523 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3524 { 3525 struct drm_device *dev = connector->dev; 3526 const struct drm_display_mode *mode; 3527 struct list_head stereo_modes; 3528 int modes = 0, i; 3529 3530 INIT_LIST_HEAD(&stereo_modes); 3531 3532 list_for_each_entry(mode, &connector->probed_modes, head) { 3533 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3534 const struct stereo_mandatory_mode *mandatory; 3535 struct drm_display_mode *new_mode; 3536 3537 if (!stereo_match_mandatory(mode, 3538 &stereo_mandatory_modes[i])) 3539 continue; 3540 3541 mandatory = &stereo_mandatory_modes[i]; 3542 new_mode = drm_mode_duplicate(dev, mode); 3543 if (!new_mode) 3544 continue; 3545 3546 new_mode->flags |= mandatory->flags; 3547 list_add_tail(&new_mode->head, &stereo_modes); 3548 modes++; 3549 } 3550 } 3551 3552 list_splice_tail(&stereo_modes, &connector->probed_modes); 3553 3554 return modes; 3555 } 3556 3557 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3558 { 3559 struct drm_device *dev = connector->dev; 3560 struct drm_display_mode *newmode; 3561 3562 if (!drm_valid_hdmi_vic(vic)) { 3563 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3564 return 0; 3565 } 3566 3567 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3568 if (!newmode) 3569 return 0; 3570 3571 drm_mode_probed_add(connector, newmode); 3572 3573 return 1; 3574 } 3575 3576 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3577 const u8 *video_db, u8 video_len, u8 video_index) 3578 { 3579 struct drm_display_mode *newmode; 3580 int modes = 0; 3581 3582 if (structure & (1 << 0)) { 3583 newmode = drm_display_mode_from_vic_index(connector, video_db, 3584 video_len, 3585 video_index); 3586 if (newmode) { 3587 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3588 drm_mode_probed_add(connector, newmode); 3589 modes++; 3590 } 3591 } 3592 if (structure & (1 << 6)) { 3593 newmode = drm_display_mode_from_vic_index(connector, video_db, 3594 video_len, 3595 video_index); 3596 if (newmode) { 3597 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3598 drm_mode_probed_add(connector, newmode); 3599 modes++; 3600 } 3601 } 3602 if (structure & (1 << 8)) { 3603 newmode = drm_display_mode_from_vic_index(connector, video_db, 3604 video_len, 3605 video_index); 3606 if (newmode) { 3607 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3608 drm_mode_probed_add(connector, newmode); 3609 modes++; 3610 } 3611 } 3612 3613 return modes; 3614 } 3615 3616 /* 3617 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3618 * @connector: connector corresponding to the HDMI sink 3619 * @db: start of the CEA vendor specific block 3620 * @len: length of the CEA block payload, ie. one can access up to db[len] 3621 * 3622 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3623 * also adds the stereo 3d modes when applicable. 3624 */ 3625 static int 3626 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3627 const u8 *video_db, u8 video_len) 3628 { 3629 struct drm_display_info *info = &connector->display_info; 3630 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3631 u8 vic_len, hdmi_3d_len = 0; 3632 u16 mask; 3633 u16 structure_all; 3634 3635 if (len < 8) 3636 goto out; 3637 3638 /* no HDMI_Video_Present */ 3639 if (!(db[8] & (1 << 5))) 3640 goto out; 3641 3642 /* Latency_Fields_Present */ 3643 if (db[8] & (1 << 7)) 3644 offset += 2; 3645 3646 /* I_Latency_Fields_Present */ 3647 if (db[8] & (1 << 6)) 3648 offset += 2; 3649 3650 /* the declared length is not long enough for the 2 first bytes 3651 * of additional video format capabilities */ 3652 if (len < (8 + offset + 2)) 3653 goto out; 3654 3655 /* 3D_Present */ 3656 offset++; 3657 if (db[8 + offset] & (1 << 7)) { 3658 modes += add_hdmi_mandatory_stereo_modes(connector); 3659 3660 /* 3D_Multi_present */ 3661 multi_present = (db[8 + offset] & 0x60) >> 5; 3662 } 3663 3664 offset++; 3665 vic_len = db[8 + offset] >> 5; 3666 hdmi_3d_len = db[8 + offset] & 0x1f; 3667 3668 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3669 u8 vic; 3670 3671 vic = db[9 + offset + i]; 3672 modes += add_hdmi_mode(connector, vic); 3673 } 3674 offset += 1 + vic_len; 3675 3676 if (multi_present == 1) 3677 multi_len = 2; 3678 else if (multi_present == 2) 3679 multi_len = 4; 3680 else 3681 multi_len = 0; 3682 3683 if (len < (8 + offset + hdmi_3d_len - 1)) 3684 goto out; 3685 3686 if (hdmi_3d_len < multi_len) 3687 goto out; 3688 3689 if (multi_present == 1 || multi_present == 2) { 3690 /* 3D_Structure_ALL */ 3691 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3692 3693 /* check if 3D_MASK is present */ 3694 if (multi_present == 2) 3695 mask = (db[10 + offset] << 8) | db[11 + offset]; 3696 else 3697 mask = 0xffff; 3698 3699 for (i = 0; i < 16; i++) { 3700 if (mask & (1 << i)) 3701 modes += add_3d_struct_modes(connector, 3702 structure_all, 3703 video_db, 3704 video_len, i); 3705 } 3706 } 3707 3708 offset += multi_len; 3709 3710 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3711 int vic_index; 3712 struct drm_display_mode *newmode = NULL; 3713 unsigned int newflag = 0; 3714 bool detail_present; 3715 3716 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3717 3718 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3719 break; 3720 3721 /* 2D_VIC_order_X */ 3722 vic_index = db[8 + offset + i] >> 4; 3723 3724 /* 3D_Structure_X */ 3725 switch (db[8 + offset + i] & 0x0f) { 3726 case 0: 3727 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3728 break; 3729 case 6: 3730 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3731 break; 3732 case 8: 3733 /* 3D_Detail_X */ 3734 if ((db[9 + offset + i] >> 4) == 1) 3735 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3736 break; 3737 } 3738 3739 if (newflag != 0) { 3740 newmode = drm_display_mode_from_vic_index(connector, 3741 video_db, 3742 video_len, 3743 vic_index); 3744 3745 if (newmode) { 3746 newmode->flags |= newflag; 3747 drm_mode_probed_add(connector, newmode); 3748 modes++; 3749 } 3750 } 3751 3752 if (detail_present) 3753 i++; 3754 } 3755 3756 out: 3757 if (modes > 0) 3758 info->has_hdmi_infoframe = true; 3759 return modes; 3760 } 3761 3762 static int 3763 cea_db_payload_len(const u8 *db) 3764 { 3765 return db[0] & 0x1f; 3766 } 3767 3768 static int 3769 cea_db_extended_tag(const u8 *db) 3770 { 3771 return db[1]; 3772 } 3773 3774 static int 3775 cea_db_tag(const u8 *db) 3776 { 3777 return db[0] >> 5; 3778 } 3779 3780 static int 3781 cea_revision(const u8 *cea) 3782 { 3783 return cea[1]; 3784 } 3785 3786 static int 3787 cea_db_offsets(const u8 *cea, int *start, int *end) 3788 { 3789 /* DisplayID CTA extension blocks and top-level CEA EDID 3790 * block header definitions differ in the following bytes: 3791 * 1) Byte 2 of the header specifies length differently, 3792 * 2) Byte 3 is only present in the CEA top level block. 3793 * 3794 * The different definitions for byte 2 follow. 3795 * 3796 * DisplayID CTA extension block defines byte 2 as: 3797 * Number of payload bytes 3798 * 3799 * CEA EDID block defines byte 2 as: 3800 * Byte number (decimal) within this block where the 18-byte 3801 * DTDs begin. If no non-DTD data is present in this extension 3802 * block, the value should be set to 04h (the byte after next). 3803 * If set to 00h, there are no DTDs present in this block and 3804 * no non-DTD data. 3805 */ 3806 if (cea[0] == DATA_BLOCK_CTA) { 3807 *start = 3; 3808 *end = *start + cea[2]; 3809 } else if (cea[0] == CEA_EXT) { 3810 /* Data block offset in CEA extension block */ 3811 *start = 4; 3812 *end = cea[2]; 3813 if (*end == 0) 3814 *end = 127; 3815 if (*end < 4 || *end > 127) 3816 return -ERANGE; 3817 } else { 3818 return -EOPNOTSUPP; 3819 } 3820 3821 return 0; 3822 } 3823 3824 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3825 { 3826 int hdmi_id; 3827 3828 if (cea_db_tag(db) != VENDOR_BLOCK) 3829 return false; 3830 3831 if (cea_db_payload_len(db) < 5) 3832 return false; 3833 3834 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3835 3836 return hdmi_id == HDMI_IEEE_OUI; 3837 } 3838 3839 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3840 { 3841 unsigned int oui; 3842 3843 if (cea_db_tag(db) != VENDOR_BLOCK) 3844 return false; 3845 3846 if (cea_db_payload_len(db) < 7) 3847 return false; 3848 3849 oui = db[3] << 16 | db[2] << 8 | db[1]; 3850 3851 return oui == HDMI_FORUM_IEEE_OUI; 3852 } 3853 3854 static bool cea_db_is_vcdb(const u8 *db) 3855 { 3856 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3857 return false; 3858 3859 if (cea_db_payload_len(db) != 2) 3860 return false; 3861 3862 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 3863 return false; 3864 3865 return true; 3866 } 3867 3868 static bool cea_db_is_y420cmdb(const u8 *db) 3869 { 3870 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3871 return false; 3872 3873 if (!cea_db_payload_len(db)) 3874 return false; 3875 3876 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3877 return false; 3878 3879 return true; 3880 } 3881 3882 static bool cea_db_is_y420vdb(const u8 *db) 3883 { 3884 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3885 return false; 3886 3887 if (!cea_db_payload_len(db)) 3888 return false; 3889 3890 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3891 return false; 3892 3893 return true; 3894 } 3895 3896 #define for_each_cea_db(cea, i, start, end) \ 3897 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3898 3899 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3900 const u8 *db) 3901 { 3902 struct drm_display_info *info = &connector->display_info; 3903 struct drm_hdmi_info *hdmi = &info->hdmi; 3904 u8 map_len = cea_db_payload_len(db) - 1; 3905 u8 count; 3906 u64 map = 0; 3907 3908 if (map_len == 0) { 3909 /* All CEA modes support ycbcr420 sampling also.*/ 3910 hdmi->y420_cmdb_map = U64_MAX; 3911 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3912 return; 3913 } 3914 3915 /* 3916 * This map indicates which of the existing CEA block modes 3917 * from VDB can support YCBCR420 output too. So if bit=0 is 3918 * set, first mode from VDB can support YCBCR420 output too. 3919 * We will parse and keep this map, before parsing VDB itself 3920 * to avoid going through the same block again and again. 3921 * 3922 * Spec is not clear about max possible size of this block. 3923 * Clamping max bitmap block size at 8 bytes. Every byte can 3924 * address 8 CEA modes, in this way this map can address 3925 * 8*8 = first 64 SVDs. 3926 */ 3927 if (WARN_ON_ONCE(map_len > 8)) 3928 map_len = 8; 3929 3930 for (count = 0; count < map_len; count++) 3931 map |= (u64)db[2 + count] << (8 * count); 3932 3933 if (map) 3934 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3935 3936 hdmi->y420_cmdb_map = map; 3937 } 3938 3939 static int 3940 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3941 { 3942 const u8 *cea = drm_find_cea_extension(edid); 3943 const u8 *db, *hdmi = NULL, *video = NULL; 3944 u8 dbl, hdmi_len, video_len = 0; 3945 int modes = 0; 3946 3947 if (cea && cea_revision(cea) >= 3) { 3948 int i, start, end; 3949 3950 if (cea_db_offsets(cea, &start, &end)) 3951 return 0; 3952 3953 for_each_cea_db(cea, i, start, end) { 3954 db = &cea[i]; 3955 dbl = cea_db_payload_len(db); 3956 3957 if (cea_db_tag(db) == VIDEO_BLOCK) { 3958 video = db + 1; 3959 video_len = dbl; 3960 modes += do_cea_modes(connector, video, dbl); 3961 } else if (cea_db_is_hdmi_vsdb(db)) { 3962 hdmi = db; 3963 hdmi_len = dbl; 3964 } else if (cea_db_is_y420vdb(db)) { 3965 const u8 *vdb420 = &db[2]; 3966 3967 /* Add 4:2:0(only) modes present in EDID */ 3968 modes += do_y420vdb_modes(connector, 3969 vdb420, 3970 dbl - 1); 3971 } 3972 } 3973 } 3974 3975 /* 3976 * We parse the HDMI VSDB after having added the cea modes as we will 3977 * be patching their flags when the sink supports stereo 3D. 3978 */ 3979 if (hdmi) 3980 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3981 video_len); 3982 3983 return modes; 3984 } 3985 3986 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3987 { 3988 const struct drm_display_mode *cea_mode; 3989 int clock1, clock2, clock; 3990 u8 vic; 3991 const char *type; 3992 3993 /* 3994 * allow 5kHz clock difference either way to account for 3995 * the 10kHz clock resolution limit of detailed timings. 3996 */ 3997 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3998 if (drm_valid_cea_vic(vic)) { 3999 type = "CEA"; 4000 cea_mode = &edid_cea_modes[vic]; 4001 clock1 = cea_mode->clock; 4002 clock2 = cea_mode_alternate_clock(cea_mode); 4003 } else { 4004 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4005 if (drm_valid_hdmi_vic(vic)) { 4006 type = "HDMI"; 4007 cea_mode = &edid_4k_modes[vic]; 4008 clock1 = cea_mode->clock; 4009 clock2 = hdmi_mode_alternate_clock(cea_mode); 4010 } else { 4011 return; 4012 } 4013 } 4014 4015 /* pick whichever is closest */ 4016 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4017 clock = clock1; 4018 else 4019 clock = clock2; 4020 4021 if (mode->clock == clock) 4022 return; 4023 4024 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4025 type, vic, mode->clock, clock); 4026 mode->clock = clock; 4027 } 4028 4029 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4030 { 4031 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4032 return false; 4033 4034 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4035 return false; 4036 4037 if (cea_db_payload_len(db) < 3) 4038 return false; 4039 4040 return true; 4041 } 4042 4043 static uint8_t eotf_supported(const u8 *edid_ext) 4044 { 4045 return edid_ext[2] & 4046 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4047 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4048 BIT(HDMI_EOTF_SMPTE_ST2084) | 4049 BIT(HDMI_EOTF_BT_2100_HLG)); 4050 } 4051 4052 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4053 { 4054 return edid_ext[3] & 4055 BIT(HDMI_STATIC_METADATA_TYPE1); 4056 } 4057 4058 static void 4059 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4060 { 4061 u16 len; 4062 4063 len = cea_db_payload_len(db); 4064 4065 connector->hdr_sink_metadata.hdmi_type1.eotf = 4066 eotf_supported(db); 4067 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4068 hdr_metadata_type(db); 4069 4070 if (len >= 4) 4071 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4072 if (len >= 5) 4073 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4074 if (len >= 6) 4075 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4076 } 4077 4078 static void 4079 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4080 { 4081 u8 len = cea_db_payload_len(db); 4082 4083 if (len >= 6 && (db[6] & (1 << 7))) 4084 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4085 if (len >= 8) { 4086 connector->latency_present[0] = db[8] >> 7; 4087 connector->latency_present[1] = (db[8] >> 6) & 1; 4088 } 4089 if (len >= 9) 4090 connector->video_latency[0] = db[9]; 4091 if (len >= 10) 4092 connector->audio_latency[0] = db[10]; 4093 if (len >= 11) 4094 connector->video_latency[1] = db[11]; 4095 if (len >= 12) 4096 connector->audio_latency[1] = db[12]; 4097 4098 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4099 "video latency %d %d, " 4100 "audio latency %d %d\n", 4101 connector->latency_present[0], 4102 connector->latency_present[1], 4103 connector->video_latency[0], 4104 connector->video_latency[1], 4105 connector->audio_latency[0], 4106 connector->audio_latency[1]); 4107 } 4108 4109 static void 4110 monitor_name(struct detailed_timing *t, void *data) 4111 { 4112 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 4113 *(u8 **)data = t->data.other_data.data.str.str; 4114 } 4115 4116 static int get_monitor_name(struct edid *edid, char name[13]) 4117 { 4118 char *edid_name = NULL; 4119 int mnl; 4120 4121 if (!edid || !name) 4122 return 0; 4123 4124 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4125 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4126 if (edid_name[mnl] == 0x0a) 4127 break; 4128 4129 name[mnl] = edid_name[mnl]; 4130 } 4131 4132 return mnl; 4133 } 4134 4135 /** 4136 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4137 * @edid: monitor EDID information 4138 * @name: pointer to a character array to hold the name of the monitor 4139 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4140 * 4141 */ 4142 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4143 { 4144 int name_length; 4145 char buf[13]; 4146 4147 if (bufsize <= 0) 4148 return; 4149 4150 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4151 memcpy(name, buf, name_length); 4152 name[name_length] = '\0'; 4153 } 4154 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4155 4156 static void clear_eld(struct drm_connector *connector) 4157 { 4158 memset(connector->eld, 0, sizeof(connector->eld)); 4159 4160 connector->latency_present[0] = false; 4161 connector->latency_present[1] = false; 4162 connector->video_latency[0] = 0; 4163 connector->audio_latency[0] = 0; 4164 connector->video_latency[1] = 0; 4165 connector->audio_latency[1] = 0; 4166 } 4167 4168 /* 4169 * drm_edid_to_eld - build ELD from EDID 4170 * @connector: connector corresponding to the HDMI/DP sink 4171 * @edid: EDID to parse 4172 * 4173 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4174 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4175 */ 4176 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4177 { 4178 uint8_t *eld = connector->eld; 4179 u8 *cea; 4180 u8 *db; 4181 int total_sad_count = 0; 4182 int mnl; 4183 int dbl; 4184 4185 clear_eld(connector); 4186 4187 if (!edid) 4188 return; 4189 4190 cea = drm_find_cea_extension(edid); 4191 if (!cea) { 4192 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4193 return; 4194 } 4195 4196 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4197 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4198 4199 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4200 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4201 4202 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4203 4204 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4205 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4206 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4207 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4208 4209 if (cea_revision(cea) >= 3) { 4210 int i, start, end; 4211 4212 if (cea_db_offsets(cea, &start, &end)) { 4213 start = 0; 4214 end = 0; 4215 } 4216 4217 for_each_cea_db(cea, i, start, end) { 4218 db = &cea[i]; 4219 dbl = cea_db_payload_len(db); 4220 4221 switch (cea_db_tag(db)) { 4222 int sad_count; 4223 4224 case AUDIO_BLOCK: 4225 /* Audio Data Block, contains SADs */ 4226 sad_count = min(dbl / 3, 15 - total_sad_count); 4227 if (sad_count >= 1) 4228 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4229 &db[1], sad_count * 3); 4230 total_sad_count += sad_count; 4231 break; 4232 case SPEAKER_BLOCK: 4233 /* Speaker Allocation Data Block */ 4234 if (dbl >= 1) 4235 eld[DRM_ELD_SPEAKER] = db[1]; 4236 break; 4237 case VENDOR_BLOCK: 4238 /* HDMI Vendor-Specific Data Block */ 4239 if (cea_db_is_hdmi_vsdb(db)) 4240 drm_parse_hdmi_vsdb_audio(connector, db); 4241 break; 4242 default: 4243 break; 4244 } 4245 } 4246 } 4247 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4248 4249 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4250 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4251 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4252 else 4253 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4254 4255 eld[DRM_ELD_BASELINE_ELD_LEN] = 4256 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4257 4258 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4259 drm_eld_size(eld), total_sad_count); 4260 } 4261 4262 /** 4263 * drm_edid_to_sad - extracts SADs from EDID 4264 * @edid: EDID to parse 4265 * @sads: pointer that will be set to the extracted SADs 4266 * 4267 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4268 * 4269 * Note: The returned pointer needs to be freed using kfree(). 4270 * 4271 * Return: The number of found SADs or negative number on error. 4272 */ 4273 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4274 { 4275 int count = 0; 4276 int i, start, end, dbl; 4277 u8 *cea; 4278 4279 cea = drm_find_cea_extension(edid); 4280 if (!cea) { 4281 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4282 return -ENOENT; 4283 } 4284 4285 if (cea_revision(cea) < 3) { 4286 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4287 return -EOPNOTSUPP; 4288 } 4289 4290 if (cea_db_offsets(cea, &start, &end)) { 4291 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4292 return -EPROTO; 4293 } 4294 4295 for_each_cea_db(cea, i, start, end) { 4296 u8 *db = &cea[i]; 4297 4298 if (cea_db_tag(db) == AUDIO_BLOCK) { 4299 int j; 4300 dbl = cea_db_payload_len(db); 4301 4302 count = dbl / 3; /* SAD is 3B */ 4303 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4304 if (!*sads) 4305 return -ENOMEM; 4306 for (j = 0; j < count; j++) { 4307 u8 *sad = &db[1 + j * 3]; 4308 4309 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4310 (*sads)[j].channels = sad[0] & 0x7; 4311 (*sads)[j].freq = sad[1] & 0x7F; 4312 (*sads)[j].byte2 = sad[2]; 4313 } 4314 break; 4315 } 4316 } 4317 4318 return count; 4319 } 4320 EXPORT_SYMBOL(drm_edid_to_sad); 4321 4322 /** 4323 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4324 * @edid: EDID to parse 4325 * @sadb: pointer to the speaker block 4326 * 4327 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4328 * 4329 * Note: The returned pointer needs to be freed using kfree(). 4330 * 4331 * Return: The number of found Speaker Allocation Blocks or negative number on 4332 * error. 4333 */ 4334 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4335 { 4336 int count = 0; 4337 int i, start, end, dbl; 4338 const u8 *cea; 4339 4340 cea = drm_find_cea_extension(edid); 4341 if (!cea) { 4342 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4343 return -ENOENT; 4344 } 4345 4346 if (cea_revision(cea) < 3) { 4347 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4348 return -EOPNOTSUPP; 4349 } 4350 4351 if (cea_db_offsets(cea, &start, &end)) { 4352 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4353 return -EPROTO; 4354 } 4355 4356 for_each_cea_db(cea, i, start, end) { 4357 const u8 *db = &cea[i]; 4358 4359 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4360 dbl = cea_db_payload_len(db); 4361 4362 /* Speaker Allocation Data Block */ 4363 if (dbl == 3) { 4364 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4365 if (!*sadb) 4366 return -ENOMEM; 4367 count = dbl; 4368 break; 4369 } 4370 } 4371 } 4372 4373 return count; 4374 } 4375 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4376 4377 /** 4378 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4379 * @connector: connector associated with the HDMI/DP sink 4380 * @mode: the display mode 4381 * 4382 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4383 * the sink doesn't support audio or video. 4384 */ 4385 int drm_av_sync_delay(struct drm_connector *connector, 4386 const struct drm_display_mode *mode) 4387 { 4388 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4389 int a, v; 4390 4391 if (!connector->latency_present[0]) 4392 return 0; 4393 if (!connector->latency_present[1]) 4394 i = 0; 4395 4396 a = connector->audio_latency[i]; 4397 v = connector->video_latency[i]; 4398 4399 /* 4400 * HDMI/DP sink doesn't support audio or video? 4401 */ 4402 if (a == 255 || v == 255) 4403 return 0; 4404 4405 /* 4406 * Convert raw EDID values to millisecond. 4407 * Treat unknown latency as 0ms. 4408 */ 4409 if (a) 4410 a = min(2 * (a - 1), 500); 4411 if (v) 4412 v = min(2 * (v - 1), 500); 4413 4414 return max(v - a, 0); 4415 } 4416 EXPORT_SYMBOL(drm_av_sync_delay); 4417 4418 /** 4419 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4420 * @edid: monitor EDID information 4421 * 4422 * Parse the CEA extension according to CEA-861-B. 4423 * 4424 * Return: True if the monitor is HDMI, false if not or unknown. 4425 */ 4426 bool drm_detect_hdmi_monitor(struct edid *edid) 4427 { 4428 u8 *edid_ext; 4429 int i; 4430 int start_offset, end_offset; 4431 4432 edid_ext = drm_find_cea_extension(edid); 4433 if (!edid_ext) 4434 return false; 4435 4436 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4437 return false; 4438 4439 /* 4440 * Because HDMI identifier is in Vendor Specific Block, 4441 * search it from all data blocks of CEA extension. 4442 */ 4443 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4444 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4445 return true; 4446 } 4447 4448 return false; 4449 } 4450 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4451 4452 /** 4453 * drm_detect_monitor_audio - check monitor audio capability 4454 * @edid: EDID block to scan 4455 * 4456 * Monitor should have CEA extension block. 4457 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4458 * audio' only. If there is any audio extension block and supported 4459 * audio format, assume at least 'basic audio' support, even if 'basic 4460 * audio' is not defined in EDID. 4461 * 4462 * Return: True if the monitor supports audio, false otherwise. 4463 */ 4464 bool drm_detect_monitor_audio(struct edid *edid) 4465 { 4466 u8 *edid_ext; 4467 int i, j; 4468 bool has_audio = false; 4469 int start_offset, end_offset; 4470 4471 edid_ext = drm_find_cea_extension(edid); 4472 if (!edid_ext) 4473 goto end; 4474 4475 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4476 4477 if (has_audio) { 4478 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4479 goto end; 4480 } 4481 4482 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4483 goto end; 4484 4485 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4486 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4487 has_audio = true; 4488 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4489 DRM_DEBUG_KMS("CEA audio format %d\n", 4490 (edid_ext[i + j] >> 3) & 0xf); 4491 goto end; 4492 } 4493 } 4494 end: 4495 return has_audio; 4496 } 4497 EXPORT_SYMBOL(drm_detect_monitor_audio); 4498 4499 4500 /** 4501 * drm_default_rgb_quant_range - default RGB quantization range 4502 * @mode: display mode 4503 * 4504 * Determine the default RGB quantization range for the mode, 4505 * as specified in CEA-861. 4506 * 4507 * Return: The default RGB quantization range for the mode 4508 */ 4509 enum hdmi_quantization_range 4510 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4511 { 4512 /* All CEA modes other than VIC 1 use limited quantization range. */ 4513 return drm_match_cea_mode(mode) > 1 ? 4514 HDMI_QUANTIZATION_RANGE_LIMITED : 4515 HDMI_QUANTIZATION_RANGE_FULL; 4516 } 4517 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4518 4519 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4520 { 4521 struct drm_display_info *info = &connector->display_info; 4522 4523 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4524 4525 if (db[2] & EDID_CEA_VCDB_QS) 4526 info->rgb_quant_range_selectable = true; 4527 } 4528 4529 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4530 const u8 *db) 4531 { 4532 u8 dc_mask; 4533 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4534 4535 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4536 hdmi->y420_dc_modes = dc_mask; 4537 } 4538 4539 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4540 const u8 *hf_vsdb) 4541 { 4542 struct drm_display_info *display = &connector->display_info; 4543 struct drm_hdmi_info *hdmi = &display->hdmi; 4544 4545 display->has_hdmi_infoframe = true; 4546 4547 if (hf_vsdb[6] & 0x80) { 4548 hdmi->scdc.supported = true; 4549 if (hf_vsdb[6] & 0x40) 4550 hdmi->scdc.read_request = true; 4551 } 4552 4553 /* 4554 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4555 * And as per the spec, three factors confirm this: 4556 * * Availability of a HF-VSDB block in EDID (check) 4557 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4558 * * SCDC support available (let's check) 4559 * Lets check it out. 4560 */ 4561 4562 if (hf_vsdb[5]) { 4563 /* max clock is 5000 KHz times block value */ 4564 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4565 struct drm_scdc *scdc = &hdmi->scdc; 4566 4567 if (max_tmds_clock > 340000) { 4568 display->max_tmds_clock = max_tmds_clock; 4569 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4570 display->max_tmds_clock); 4571 } 4572 4573 if (scdc->supported) { 4574 scdc->scrambling.supported = true; 4575 4576 /* Few sinks support scrambling for cloks < 340M */ 4577 if ((hf_vsdb[6] & 0x8)) 4578 scdc->scrambling.low_rates = true; 4579 } 4580 } 4581 4582 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4583 } 4584 4585 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4586 const u8 *hdmi) 4587 { 4588 struct drm_display_info *info = &connector->display_info; 4589 unsigned int dc_bpc = 0; 4590 4591 /* HDMI supports at least 8 bpc */ 4592 info->bpc = 8; 4593 4594 if (cea_db_payload_len(hdmi) < 6) 4595 return; 4596 4597 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4598 dc_bpc = 10; 4599 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4600 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4601 connector->name); 4602 } 4603 4604 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4605 dc_bpc = 12; 4606 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4607 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4608 connector->name); 4609 } 4610 4611 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4612 dc_bpc = 16; 4613 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4614 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4615 connector->name); 4616 } 4617 4618 if (dc_bpc == 0) { 4619 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4620 connector->name); 4621 return; 4622 } 4623 4624 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4625 connector->name, dc_bpc); 4626 info->bpc = dc_bpc; 4627 4628 /* 4629 * Deep color support mandates RGB444 support for all video 4630 * modes and forbids YCRCB422 support for all video modes per 4631 * HDMI 1.3 spec. 4632 */ 4633 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4634 4635 /* YCRCB444 is optional according to spec. */ 4636 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4637 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4638 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4639 connector->name); 4640 } 4641 4642 /* 4643 * Spec says that if any deep color mode is supported at all, 4644 * then deep color 36 bit must be supported. 4645 */ 4646 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4647 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4648 connector->name); 4649 } 4650 } 4651 4652 static void 4653 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4654 { 4655 struct drm_display_info *info = &connector->display_info; 4656 u8 len = cea_db_payload_len(db); 4657 4658 if (len >= 6) 4659 info->dvi_dual = db[6] & 1; 4660 if (len >= 7) 4661 info->max_tmds_clock = db[7] * 5000; 4662 4663 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4664 "max TMDS clock %d kHz\n", 4665 info->dvi_dual, 4666 info->max_tmds_clock); 4667 4668 drm_parse_hdmi_deep_color_info(connector, db); 4669 } 4670 4671 static void drm_parse_cea_ext(struct drm_connector *connector, 4672 const struct edid *edid) 4673 { 4674 struct drm_display_info *info = &connector->display_info; 4675 const u8 *edid_ext; 4676 int i, start, end; 4677 4678 edid_ext = drm_find_cea_extension(edid); 4679 if (!edid_ext) 4680 return; 4681 4682 info->cea_rev = edid_ext[1]; 4683 4684 /* The existence of a CEA block should imply RGB support */ 4685 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4686 if (edid_ext[3] & EDID_CEA_YCRCB444) 4687 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4688 if (edid_ext[3] & EDID_CEA_YCRCB422) 4689 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4690 4691 if (cea_db_offsets(edid_ext, &start, &end)) 4692 return; 4693 4694 for_each_cea_db(edid_ext, i, start, end) { 4695 const u8 *db = &edid_ext[i]; 4696 4697 if (cea_db_is_hdmi_vsdb(db)) 4698 drm_parse_hdmi_vsdb_video(connector, db); 4699 if (cea_db_is_hdmi_forum_vsdb(db)) 4700 drm_parse_hdmi_forum_vsdb(connector, db); 4701 if (cea_db_is_y420cmdb(db)) 4702 drm_parse_y420cmdb_bitmap(connector, db); 4703 if (cea_db_is_vcdb(db)) 4704 drm_parse_vcdb(connector, db); 4705 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4706 drm_parse_hdr_metadata_block(connector, db); 4707 } 4708 } 4709 4710 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4711 * all of the values which would have been set from EDID 4712 */ 4713 void 4714 drm_reset_display_info(struct drm_connector *connector) 4715 { 4716 struct drm_display_info *info = &connector->display_info; 4717 4718 info->width_mm = 0; 4719 info->height_mm = 0; 4720 4721 info->bpc = 0; 4722 info->color_formats = 0; 4723 info->cea_rev = 0; 4724 info->max_tmds_clock = 0; 4725 info->dvi_dual = false; 4726 info->has_hdmi_infoframe = false; 4727 info->rgb_quant_range_selectable = false; 4728 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4729 4730 info->non_desktop = 0; 4731 } 4732 4733 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4734 { 4735 struct drm_display_info *info = &connector->display_info; 4736 4737 u32 quirks = edid_get_quirks(edid); 4738 4739 drm_reset_display_info(connector); 4740 4741 info->width_mm = edid->width_cm * 10; 4742 info->height_mm = edid->height_cm * 10; 4743 4744 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4745 4746 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4747 4748 if (edid->revision < 3) 4749 return quirks; 4750 4751 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4752 return quirks; 4753 4754 drm_parse_cea_ext(connector, edid); 4755 4756 /* 4757 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4758 * 4759 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4760 * tells us to assume 8 bpc color depth if the EDID doesn't have 4761 * extensions which tell otherwise. 4762 */ 4763 if (info->bpc == 0 && edid->revision == 3 && 4764 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 4765 info->bpc = 8; 4766 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4767 connector->name, info->bpc); 4768 } 4769 4770 /* Only defined for 1.4 with digital displays */ 4771 if (edid->revision < 4) 4772 return quirks; 4773 4774 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4775 case DRM_EDID_DIGITAL_DEPTH_6: 4776 info->bpc = 6; 4777 break; 4778 case DRM_EDID_DIGITAL_DEPTH_8: 4779 info->bpc = 8; 4780 break; 4781 case DRM_EDID_DIGITAL_DEPTH_10: 4782 info->bpc = 10; 4783 break; 4784 case DRM_EDID_DIGITAL_DEPTH_12: 4785 info->bpc = 12; 4786 break; 4787 case DRM_EDID_DIGITAL_DEPTH_14: 4788 info->bpc = 14; 4789 break; 4790 case DRM_EDID_DIGITAL_DEPTH_16: 4791 info->bpc = 16; 4792 break; 4793 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4794 default: 4795 info->bpc = 0; 4796 break; 4797 } 4798 4799 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4800 connector->name, info->bpc); 4801 4802 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4803 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4804 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4805 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4806 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4807 return quirks; 4808 } 4809 4810 static int validate_displayid(u8 *displayid, int length, int idx) 4811 { 4812 int i; 4813 u8 csum = 0; 4814 struct displayid_hdr *base; 4815 4816 base = (struct displayid_hdr *)&displayid[idx]; 4817 4818 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4819 base->rev, base->bytes, base->prod_id, base->ext_count); 4820 4821 if (base->bytes + 5 > length - idx) 4822 return -EINVAL; 4823 for (i = idx; i <= base->bytes + 5; i++) { 4824 csum += displayid[i]; 4825 } 4826 if (csum) { 4827 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4828 return -EINVAL; 4829 } 4830 return 0; 4831 } 4832 4833 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4834 struct displayid_detailed_timings_1 *timings) 4835 { 4836 struct drm_display_mode *mode; 4837 unsigned pixel_clock = (timings->pixel_clock[0] | 4838 (timings->pixel_clock[1] << 8) | 4839 (timings->pixel_clock[2] << 16)); 4840 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4841 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4842 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4843 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4844 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4845 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4846 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4847 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4848 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4849 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4850 mode = drm_mode_create(dev); 4851 if (!mode) 4852 return NULL; 4853 4854 mode->clock = pixel_clock * 10; 4855 mode->hdisplay = hactive; 4856 mode->hsync_start = mode->hdisplay + hsync; 4857 mode->hsync_end = mode->hsync_start + hsync_width; 4858 mode->htotal = mode->hdisplay + hblank; 4859 4860 mode->vdisplay = vactive; 4861 mode->vsync_start = mode->vdisplay + vsync; 4862 mode->vsync_end = mode->vsync_start + vsync_width; 4863 mode->vtotal = mode->vdisplay + vblank; 4864 4865 mode->flags = 0; 4866 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4867 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4868 mode->type = DRM_MODE_TYPE_DRIVER; 4869 4870 if (timings->flags & 0x80) 4871 mode->type |= DRM_MODE_TYPE_PREFERRED; 4872 mode->vrefresh = drm_mode_vrefresh(mode); 4873 drm_mode_set_name(mode); 4874 4875 return mode; 4876 } 4877 4878 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4879 struct displayid_block *block) 4880 { 4881 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4882 int i; 4883 int num_timings; 4884 struct drm_display_mode *newmode; 4885 int num_modes = 0; 4886 /* blocks must be multiple of 20 bytes length */ 4887 if (block->num_bytes % 20) 4888 return 0; 4889 4890 num_timings = block->num_bytes / 20; 4891 for (i = 0; i < num_timings; i++) { 4892 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4893 4894 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4895 if (!newmode) 4896 continue; 4897 4898 drm_mode_probed_add(connector, newmode); 4899 num_modes++; 4900 } 4901 return num_modes; 4902 } 4903 4904 static int add_displayid_detailed_modes(struct drm_connector *connector, 4905 struct edid *edid) 4906 { 4907 u8 *displayid; 4908 int ret; 4909 int idx = 1; 4910 int length = EDID_LENGTH; 4911 struct displayid_block *block; 4912 int num_modes = 0; 4913 4914 displayid = drm_find_displayid_extension(edid); 4915 if (!displayid) 4916 return 0; 4917 4918 ret = validate_displayid(displayid, length, idx); 4919 if (ret) 4920 return 0; 4921 4922 idx += sizeof(struct displayid_hdr); 4923 for_each_displayid_db(displayid, block, idx, length) { 4924 switch (block->tag) { 4925 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4926 num_modes += add_displayid_detailed_1_modes(connector, block); 4927 break; 4928 } 4929 } 4930 return num_modes; 4931 } 4932 4933 /** 4934 * drm_add_edid_modes - add modes from EDID data, if available 4935 * @connector: connector we're probing 4936 * @edid: EDID data 4937 * 4938 * Add the specified modes to the connector's mode list. Also fills out the 4939 * &drm_display_info structure and ELD in @connector with any information which 4940 * can be derived from the edid. 4941 * 4942 * Return: The number of modes added or 0 if we couldn't find any. 4943 */ 4944 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4945 { 4946 int num_modes = 0; 4947 u32 quirks; 4948 4949 if (edid == NULL) { 4950 clear_eld(connector); 4951 return 0; 4952 } 4953 if (!drm_edid_is_valid(edid)) { 4954 clear_eld(connector); 4955 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4956 connector->name); 4957 return 0; 4958 } 4959 4960 drm_edid_to_eld(connector, edid); 4961 4962 /* 4963 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4964 * To avoid multiple parsing of same block, lets parse that map 4965 * from sink info, before parsing CEA modes. 4966 */ 4967 quirks = drm_add_display_info(connector, edid); 4968 4969 /* 4970 * EDID spec says modes should be preferred in this order: 4971 * - preferred detailed mode 4972 * - other detailed modes from base block 4973 * - detailed modes from extension blocks 4974 * - CVT 3-byte code modes 4975 * - standard timing codes 4976 * - established timing codes 4977 * - modes inferred from GTF or CVT range information 4978 * 4979 * We get this pretty much right. 4980 * 4981 * XXX order for additional mode types in extension blocks? 4982 */ 4983 num_modes += add_detailed_modes(connector, edid, quirks); 4984 num_modes += add_cvt_modes(connector, edid); 4985 num_modes += add_standard_modes(connector, edid); 4986 num_modes += add_established_modes(connector, edid); 4987 num_modes += add_cea_modes(connector, edid); 4988 num_modes += add_alternate_cea_modes(connector, edid); 4989 num_modes += add_displayid_detailed_modes(connector, edid); 4990 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4991 num_modes += add_inferred_modes(connector, edid); 4992 4993 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4994 edid_fixup_preferred(connector, quirks); 4995 4996 if (quirks & EDID_QUIRK_FORCE_6BPC) 4997 connector->display_info.bpc = 6; 4998 4999 if (quirks & EDID_QUIRK_FORCE_8BPC) 5000 connector->display_info.bpc = 8; 5001 5002 if (quirks & EDID_QUIRK_FORCE_10BPC) 5003 connector->display_info.bpc = 10; 5004 5005 if (quirks & EDID_QUIRK_FORCE_12BPC) 5006 connector->display_info.bpc = 12; 5007 5008 return num_modes; 5009 } 5010 EXPORT_SYMBOL(drm_add_edid_modes); 5011 5012 /** 5013 * drm_add_modes_noedid - add modes for the connectors without EDID 5014 * @connector: connector we're probing 5015 * @hdisplay: the horizontal display limit 5016 * @vdisplay: the vertical display limit 5017 * 5018 * Add the specified modes to the connector's mode list. Only when the 5019 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5020 * 5021 * Return: The number of modes added or 0 if we couldn't find any. 5022 */ 5023 int drm_add_modes_noedid(struct drm_connector *connector, 5024 int hdisplay, int vdisplay) 5025 { 5026 int i, count, num_modes = 0; 5027 struct drm_display_mode *mode; 5028 struct drm_device *dev = connector->dev; 5029 5030 count = ARRAY_SIZE(drm_dmt_modes); 5031 if (hdisplay < 0) 5032 hdisplay = 0; 5033 if (vdisplay < 0) 5034 vdisplay = 0; 5035 5036 for (i = 0; i < count; i++) { 5037 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5038 if (hdisplay && vdisplay) { 5039 /* 5040 * Only when two are valid, they will be used to check 5041 * whether the mode should be added to the mode list of 5042 * the connector. 5043 */ 5044 if (ptr->hdisplay > hdisplay || 5045 ptr->vdisplay > vdisplay) 5046 continue; 5047 } 5048 if (drm_mode_vrefresh(ptr) > 61) 5049 continue; 5050 mode = drm_mode_duplicate(dev, ptr); 5051 if (mode) { 5052 drm_mode_probed_add(connector, mode); 5053 num_modes++; 5054 } 5055 } 5056 return num_modes; 5057 } 5058 EXPORT_SYMBOL(drm_add_modes_noedid); 5059 5060 /** 5061 * drm_set_preferred_mode - Sets the preferred mode of a connector 5062 * @connector: connector whose mode list should be processed 5063 * @hpref: horizontal resolution of preferred mode 5064 * @vpref: vertical resolution of preferred mode 5065 * 5066 * Marks a mode as preferred if it matches the resolution specified by @hpref 5067 * and @vpref. 5068 */ 5069 void drm_set_preferred_mode(struct drm_connector *connector, 5070 int hpref, int vpref) 5071 { 5072 struct drm_display_mode *mode; 5073 5074 list_for_each_entry(mode, &connector->probed_modes, head) { 5075 if (mode->hdisplay == hpref && 5076 mode->vdisplay == vpref) 5077 mode->type |= DRM_MODE_TYPE_PREFERRED; 5078 } 5079 } 5080 EXPORT_SYMBOL(drm_set_preferred_mode); 5081 5082 static bool is_hdmi2_sink(struct drm_connector *connector) 5083 { 5084 /* 5085 * FIXME: sil-sii8620 doesn't have a connector around when 5086 * we need one, so we have to be prepared for a NULL connector. 5087 */ 5088 if (!connector) 5089 return true; 5090 5091 return connector->display_info.hdmi.scdc.supported || 5092 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5093 } 5094 5095 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5096 { 5097 return sink_eotf & BIT(output_eotf); 5098 } 5099 5100 /** 5101 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5102 * HDR metadata from userspace 5103 * @frame: HDMI DRM infoframe 5104 * @conn_state: Connector state containing HDR metadata 5105 * 5106 * Return: 0 on success or a negative error code on failure. 5107 */ 5108 int 5109 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5110 const struct drm_connector_state *conn_state) 5111 { 5112 struct drm_connector *connector; 5113 struct hdr_output_metadata *hdr_metadata; 5114 int err; 5115 5116 if (!frame || !conn_state) 5117 return -EINVAL; 5118 5119 connector = conn_state->connector; 5120 5121 if (!conn_state->hdr_output_metadata) 5122 return -EINVAL; 5123 5124 hdr_metadata = conn_state->hdr_output_metadata->data; 5125 5126 if (!hdr_metadata || !connector) 5127 return -EINVAL; 5128 5129 /* Sink EOTF is Bit map while infoframe is absolute values */ 5130 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5131 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5132 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5133 return -EINVAL; 5134 } 5135 5136 err = hdmi_drm_infoframe_init(frame); 5137 if (err < 0) 5138 return err; 5139 5140 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5141 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5142 5143 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5144 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5145 BUILD_BUG_ON(sizeof(frame->white_point) != 5146 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5147 5148 memcpy(&frame->display_primaries, 5149 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5150 sizeof(frame->display_primaries)); 5151 5152 memcpy(&frame->white_point, 5153 &hdr_metadata->hdmi_metadata_type1.white_point, 5154 sizeof(frame->white_point)); 5155 5156 frame->max_display_mastering_luminance = 5157 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5158 frame->min_display_mastering_luminance = 5159 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5160 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5161 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5162 5163 return 0; 5164 } 5165 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5166 5167 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5168 const struct drm_display_mode *mode) 5169 { 5170 bool has_hdmi_infoframe = connector ? 5171 connector->display_info.has_hdmi_infoframe : false; 5172 5173 if (!has_hdmi_infoframe) 5174 return 0; 5175 5176 /* No HDMI VIC when signalling 3D video format */ 5177 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5178 return 0; 5179 5180 return drm_match_hdmi_mode(mode); 5181 } 5182 5183 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5184 const struct drm_display_mode *mode) 5185 { 5186 u8 vic; 5187 5188 /* 5189 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5190 * we should send its VIC in vendor infoframes, else send the 5191 * VIC in AVI infoframes. Lets check if this mode is present in 5192 * HDMI 1.4b 4K modes 5193 */ 5194 if (drm_mode_hdmi_vic(connector, mode)) 5195 return 0; 5196 5197 vic = drm_match_cea_mode(mode); 5198 5199 /* 5200 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5201 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5202 * have to make sure we dont break HDMI 1.4 sinks. 5203 */ 5204 if (!is_hdmi2_sink(connector) && vic > 64) 5205 return 0; 5206 5207 return vic; 5208 } 5209 5210 /** 5211 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5212 * data from a DRM display mode 5213 * @frame: HDMI AVI infoframe 5214 * @connector: the connector 5215 * @mode: DRM display mode 5216 * 5217 * Return: 0 on success or a negative error code on failure. 5218 */ 5219 int 5220 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5221 struct drm_connector *connector, 5222 const struct drm_display_mode *mode) 5223 { 5224 enum hdmi_picture_aspect picture_aspect; 5225 int err; 5226 5227 if (!frame || !mode) 5228 return -EINVAL; 5229 5230 err = hdmi_avi_infoframe_init(frame); 5231 if (err < 0) 5232 return err; 5233 5234 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5235 frame->pixel_repeat = 1; 5236 5237 frame->video_code = drm_mode_cea_vic(connector, mode); 5238 5239 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5240 5241 /* 5242 * As some drivers don't support atomic, we can't use connector state. 5243 * So just initialize the frame with default values, just the same way 5244 * as it's done with other properties here. 5245 */ 5246 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5247 frame->itc = 0; 5248 5249 /* 5250 * Populate picture aspect ratio from either 5251 * user input (if specified) or from the CEA mode list. 5252 */ 5253 picture_aspect = mode->picture_aspect_ratio; 5254 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 5255 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 5256 5257 /* 5258 * The infoframe can't convey anything but none, 4:3 5259 * and 16:9, so if the user has asked for anything else 5260 * we can only satisfy it by specifying the right VIC. 5261 */ 5262 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5263 if (picture_aspect != 5264 drm_get_cea_aspect_ratio(frame->video_code)) 5265 return -EINVAL; 5266 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5267 } 5268 5269 frame->picture_aspect = picture_aspect; 5270 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5271 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5272 5273 return 0; 5274 } 5275 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5276 5277 /* HDMI Colorspace Spec Definitions */ 5278 #define FULL_COLORIMETRY_MASK 0x1FF 5279 #define NORMAL_COLORIMETRY_MASK 0x3 5280 #define EXTENDED_COLORIMETRY_MASK 0x7 5281 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5282 5283 #define C(x) ((x) << 0) 5284 #define EC(x) ((x) << 2) 5285 #define ACE(x) ((x) << 5) 5286 5287 #define HDMI_COLORIMETRY_NO_DATA 0x0 5288 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5289 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5290 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5291 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5292 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5293 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5294 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5295 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5296 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5297 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5298 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5299 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5300 5301 static const u32 hdmi_colorimetry_val[] = { 5302 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5303 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5304 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5305 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5306 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5307 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5308 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5309 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5310 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5311 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5312 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5313 }; 5314 5315 #undef C 5316 #undef EC 5317 #undef ACE 5318 5319 /** 5320 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5321 * colorspace information 5322 * @frame: HDMI AVI infoframe 5323 * @conn_state: connector state 5324 */ 5325 void 5326 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5327 const struct drm_connector_state *conn_state) 5328 { 5329 u32 colorimetry_val; 5330 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5331 5332 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5333 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5334 else 5335 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5336 5337 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5338 /* 5339 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5340 * structure and extend it in drivers/video/hdmi 5341 */ 5342 frame->extended_colorimetry = (colorimetry_val >> 2) & 5343 EXTENDED_COLORIMETRY_MASK; 5344 } 5345 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5346 5347 /** 5348 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5349 * quantization range information 5350 * @frame: HDMI AVI infoframe 5351 * @connector: the connector 5352 * @mode: DRM display mode 5353 * @rgb_quant_range: RGB quantization range (Q) 5354 */ 5355 void 5356 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5357 struct drm_connector *connector, 5358 const struct drm_display_mode *mode, 5359 enum hdmi_quantization_range rgb_quant_range) 5360 { 5361 const struct drm_display_info *info = &connector->display_info; 5362 5363 /* 5364 * CEA-861: 5365 * "A Source shall not send a non-zero Q value that does not correspond 5366 * to the default RGB Quantization Range for the transmitted Picture 5367 * unless the Sink indicates support for the Q bit in a Video 5368 * Capabilities Data Block." 5369 * 5370 * HDMI 2.0 recommends sending non-zero Q when it does match the 5371 * default RGB quantization range for the mode, even when QS=0. 5372 */ 5373 if (info->rgb_quant_range_selectable || 5374 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5375 frame->quantization_range = rgb_quant_range; 5376 else 5377 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5378 5379 /* 5380 * CEA-861-F: 5381 * "When transmitting any RGB colorimetry, the Source should set the 5382 * YQ-field to match the RGB Quantization Range being transmitted 5383 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5384 * set YQ=1) and the Sink shall ignore the YQ-field." 5385 * 5386 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5387 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5388 * good way to tell which version of CEA-861 the sink supports, so 5389 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5390 * on on CEA-861-F. 5391 */ 5392 if (!is_hdmi2_sink(connector) || 5393 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5394 frame->ycc_quantization_range = 5395 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5396 else 5397 frame->ycc_quantization_range = 5398 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5399 } 5400 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5401 5402 /** 5403 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5404 * bar information 5405 * @frame: HDMI AVI infoframe 5406 * @conn_state: connector state 5407 */ 5408 void 5409 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5410 const struct drm_connector_state *conn_state) 5411 { 5412 frame->right_bar = conn_state->tv.margins.right; 5413 frame->left_bar = conn_state->tv.margins.left; 5414 frame->top_bar = conn_state->tv.margins.top; 5415 frame->bottom_bar = conn_state->tv.margins.bottom; 5416 } 5417 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5418 5419 static enum hdmi_3d_structure 5420 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5421 { 5422 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5423 5424 switch (layout) { 5425 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5426 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5427 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5428 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5429 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5430 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5431 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5432 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5433 case DRM_MODE_FLAG_3D_L_DEPTH: 5434 return HDMI_3D_STRUCTURE_L_DEPTH; 5435 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5436 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5437 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5438 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5439 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5440 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5441 default: 5442 return HDMI_3D_STRUCTURE_INVALID; 5443 } 5444 } 5445 5446 /** 5447 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5448 * data from a DRM display mode 5449 * @frame: HDMI vendor infoframe 5450 * @connector: the connector 5451 * @mode: DRM display mode 5452 * 5453 * Note that there's is a need to send HDMI vendor infoframes only when using a 5454 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5455 * function will return -EINVAL, error that can be safely ignored. 5456 * 5457 * Return: 0 on success or a negative error code on failure. 5458 */ 5459 int 5460 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5461 struct drm_connector *connector, 5462 const struct drm_display_mode *mode) 5463 { 5464 /* 5465 * FIXME: sil-sii8620 doesn't have a connector around when 5466 * we need one, so we have to be prepared for a NULL connector. 5467 */ 5468 bool has_hdmi_infoframe = connector ? 5469 connector->display_info.has_hdmi_infoframe : false; 5470 int err; 5471 5472 if (!frame || !mode) 5473 return -EINVAL; 5474 5475 if (!has_hdmi_infoframe) 5476 return -EINVAL; 5477 5478 err = hdmi_vendor_infoframe_init(frame); 5479 if (err < 0) 5480 return err; 5481 5482 /* 5483 * Even if it's not absolutely necessary to send the infoframe 5484 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5485 * know that the sink can handle it. This is based on a 5486 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5487 * have trouble realizing that they shuld switch from 3D to 2D 5488 * mode if the source simply stops sending the infoframe when 5489 * it wants to switch from 3D to 2D. 5490 */ 5491 frame->vic = drm_mode_hdmi_vic(connector, mode); 5492 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5493 5494 return 0; 5495 } 5496 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5497 5498 static int drm_parse_tiled_block(struct drm_connector *connector, 5499 struct displayid_block *block) 5500 { 5501 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5502 u16 w, h; 5503 u8 tile_v_loc, tile_h_loc; 5504 u8 num_v_tile, num_h_tile; 5505 struct drm_tile_group *tg; 5506 5507 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5508 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5509 5510 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5511 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5512 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5513 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5514 5515 connector->has_tile = true; 5516 if (tile->tile_cap & 0x80) 5517 connector->tile_is_single_monitor = true; 5518 5519 connector->num_h_tile = num_h_tile + 1; 5520 connector->num_v_tile = num_v_tile + 1; 5521 connector->tile_h_loc = tile_h_loc; 5522 connector->tile_v_loc = tile_v_loc; 5523 connector->tile_h_size = w + 1; 5524 connector->tile_v_size = h + 1; 5525 5526 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5527 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5528 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5529 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5530 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5531 5532 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5533 if (!tg) { 5534 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5535 } 5536 if (!tg) 5537 return -ENOMEM; 5538 5539 if (connector->tile_group != tg) { 5540 /* if we haven't got a pointer, 5541 take the reference, drop ref to old tile group */ 5542 if (connector->tile_group) { 5543 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5544 } 5545 connector->tile_group = tg; 5546 } else 5547 /* if same tile group, then release the ref we just took. */ 5548 drm_mode_put_tile_group(connector->dev, tg); 5549 return 0; 5550 } 5551 5552 static int drm_parse_display_id(struct drm_connector *connector, 5553 u8 *displayid, int length, 5554 bool is_edid_extension) 5555 { 5556 /* if this is an EDID extension the first byte will be 0x70 */ 5557 int idx = 0; 5558 struct displayid_block *block; 5559 int ret; 5560 5561 if (is_edid_extension) 5562 idx = 1; 5563 5564 ret = validate_displayid(displayid, length, idx); 5565 if (ret) 5566 return ret; 5567 5568 idx += sizeof(struct displayid_hdr); 5569 for_each_displayid_db(displayid, block, idx, length) { 5570 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5571 block->tag, block->rev, block->num_bytes); 5572 5573 switch (block->tag) { 5574 case DATA_BLOCK_TILED_DISPLAY: 5575 ret = drm_parse_tiled_block(connector, block); 5576 if (ret) 5577 return ret; 5578 break; 5579 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5580 /* handled in mode gathering code. */ 5581 break; 5582 case DATA_BLOCK_CTA: 5583 /* handled in the cea parser code. */ 5584 break; 5585 default: 5586 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5587 break; 5588 } 5589 } 5590 return 0; 5591 } 5592 5593 static void drm_get_displayid(struct drm_connector *connector, 5594 struct edid *edid) 5595 { 5596 void *displayid = NULL; 5597 int ret; 5598 connector->has_tile = false; 5599 displayid = drm_find_displayid_extension(edid); 5600 if (!displayid) { 5601 /* drop reference to any tile group we had */ 5602 goto out_drop_ref; 5603 } 5604 5605 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5606 if (ret < 0) 5607 goto out_drop_ref; 5608 if (!connector->has_tile) 5609 goto out_drop_ref; 5610 return; 5611 out_drop_ref: 5612 if (connector->tile_group) { 5613 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5614 connector->tile_group = NULL; 5615 } 5616 return; 5617 } 5618