1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 int modes; 100 }; 101 102 #define LEVEL_DMT 0 103 #define LEVEL_GTF 1 104 #define LEVEL_GTF2 2 105 #define LEVEL_CVT 3 106 107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 108 { \ 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 110 product_id), \ 111 .quirks = _quirks \ 112 } 113 114 static const struct edid_quirk { 115 u32 panel_id; 116 u32 quirks; 117 } edid_quirk_list[] = { 118 /* Acer AL1706 */ 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 120 /* Acer F51 */ 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 122 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 125 126 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 127 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 128 129 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 131 132 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 134 135 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 137 138 /* Belinea 10 15 55 */ 139 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 140 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 141 142 /* Envision Peripherals, Inc. EN-7100e */ 143 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 144 /* Envision EN2028 */ 145 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 146 147 /* Funai Electronics PM36B */ 148 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 149 EDID_QUIRK_DETAILED_IN_CM), 150 151 /* LG 27GP950 */ 152 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 153 154 /* LG 27GN950 */ 155 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 156 157 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 158 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 159 160 /* LG Philips LCD LP154W01-A5 */ 161 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 162 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 163 164 /* Samsung SyncMaster 205BW. Note: irony */ 165 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 166 /* Samsung SyncMaster 22[5-6]BW */ 167 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 168 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 169 170 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 171 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 172 173 /* ViewSonic VA2026w */ 174 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 175 176 /* Medion MD 30217 PG */ 177 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 178 179 /* Lenovo G50 */ 180 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 181 182 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 183 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 184 185 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 186 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 187 188 /* Valve Index Headset */ 189 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 206 207 /* HTC Vive and Vive Pro VR Headsets */ 208 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 210 211 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 212 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 216 217 /* Windows Mixed Reality Headsets */ 218 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 224 225 /* Sony PlayStation VR Headset */ 226 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 227 228 /* Sensics VR Headsets */ 229 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 230 231 /* OSVR HDK and HDK2 VR Headsets */ 232 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 233 }; 234 235 /* 236 * Autogenerated from the DMT spec. 237 * This table is copied from xfree86/modes/xf86EdidModes.c. 238 */ 239 static const struct drm_display_mode drm_dmt_modes[] = { 240 /* 0x01 - 640x350@85Hz */ 241 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 242 736, 832, 0, 350, 382, 385, 445, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x02 - 640x400@85Hz */ 245 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 246 736, 832, 0, 400, 401, 404, 445, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 248 /* 0x03 - 720x400@85Hz */ 249 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 250 828, 936, 0, 400, 401, 404, 446, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x04 - 640x480@60Hz */ 253 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 254 752, 800, 0, 480, 490, 492, 525, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 256 /* 0x05 - 640x480@72Hz */ 257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 258 704, 832, 0, 480, 489, 492, 520, 0, 259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x06 - 640x480@75Hz */ 261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 262 720, 840, 0, 480, 481, 484, 500, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 264 /* 0x07 - 640x480@85Hz */ 265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 266 752, 832, 0, 480, 481, 484, 509, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x08 - 800x600@56Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 270 896, 1024, 0, 600, 601, 603, 625, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x09 - 800x600@60Hz */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 274 968, 1056, 0, 600, 601, 605, 628, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x0a - 800x600@72Hz */ 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 278 976, 1040, 0, 600, 637, 643, 666, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0b - 800x600@75Hz */ 281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 282 896, 1056, 0, 600, 601, 604, 625, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x0c - 800x600@85Hz */ 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 286 896, 1048, 0, 600, 601, 604, 631, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x0d - 800x600@120Hz RB */ 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 290 880, 960, 0, 600, 603, 607, 636, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 292 /* 0x0e - 848x480@60Hz */ 293 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 294 976, 1088, 0, 480, 486, 494, 517, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 296 /* 0x0f - 1024x768@43Hz, interlace */ 297 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 298 1208, 1264, 0, 768, 768, 776, 817, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 300 DRM_MODE_FLAG_INTERLACE) }, 301 /* 0x10 - 1024x768@60Hz */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 303 1184, 1344, 0, 768, 771, 777, 806, 0, 304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 305 /* 0x11 - 1024x768@70Hz */ 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 307 1184, 1328, 0, 768, 771, 777, 806, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x12 - 1024x768@75Hz */ 310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 311 1136, 1312, 0, 768, 769, 772, 800, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x13 - 1024x768@85Hz */ 314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 315 1168, 1376, 0, 768, 769, 772, 808, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x14 - 1024x768@120Hz RB */ 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 319 1104, 1184, 0, 768, 771, 775, 813, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 321 /* 0x15 - 1152x864@75Hz */ 322 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 323 1344, 1600, 0, 864, 865, 868, 900, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x55 - 1280x720@60Hz */ 326 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 327 1430, 1650, 0, 720, 725, 730, 750, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x16 - 1280x768@60Hz RB */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 331 1360, 1440, 0, 768, 771, 778, 790, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 0x17 - 1280x768@60Hz */ 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 335 1472, 1664, 0, 768, 771, 778, 798, 0, 336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 0x18 - 1280x768@75Hz */ 338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 339 1488, 1696, 0, 768, 771, 778, 805, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x19 - 1280x768@85Hz */ 342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 343 1496, 1712, 0, 768, 771, 778, 809, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x1a - 1280x768@120Hz RB */ 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 347 1360, 1440, 0, 768, 771, 778, 813, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 0x1b - 1280x800@60Hz RB */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 351 1360, 1440, 0, 800, 803, 809, 823, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x1c - 1280x800@60Hz */ 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 355 1480, 1680, 0, 800, 803, 809, 831, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x1d - 1280x800@75Hz */ 358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 359 1488, 1696, 0, 800, 803, 809, 838, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x1e - 1280x800@85Hz */ 362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 363 1496, 1712, 0, 800, 803, 809, 843, 0, 364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x1f - 1280x800@120Hz RB */ 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 367 1360, 1440, 0, 800, 803, 809, 847, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 369 /* 0x20 - 1280x960@60Hz */ 370 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 371 1488, 1800, 0, 960, 961, 964, 1000, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x21 - 1280x960@85Hz */ 374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 375 1504, 1728, 0, 960, 961, 964, 1011, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x22 - 1280x960@120Hz RB */ 378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 379 1360, 1440, 0, 960, 963, 967, 1017, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 381 /* 0x23 - 1280x1024@60Hz */ 382 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 383 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x24 - 1280x1024@75Hz */ 386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x25 - 1280x1024@85Hz */ 390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 391 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x26 - 1280x1024@120Hz RB */ 394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 395 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 0x27 - 1360x768@60Hz */ 398 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 399 1536, 1792, 0, 768, 771, 777, 795, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x28 - 1360x768@120Hz RB */ 402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 403 1440, 1520, 0, 768, 771, 776, 813, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 405 /* 0x51 - 1366x768@60Hz */ 406 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 407 1579, 1792, 0, 768, 771, 774, 798, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x56 - 1366x768@60Hz */ 410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 411 1436, 1500, 0, 768, 769, 772, 800, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x29 - 1400x1050@60Hz RB */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 415 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 0x2a - 1400x1050@60Hz */ 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 419 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 421 /* 0x2b - 1400x1050@75Hz */ 422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 423 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x2c - 1400x1050@85Hz */ 426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 427 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x2d - 1400x1050@120Hz RB */ 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 431 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 433 /* 0x2e - 1440x900@60Hz RB */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 435 1520, 1600, 0, 900, 903, 909, 926, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x2f - 1440x900@60Hz */ 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 439 1672, 1904, 0, 900, 903, 909, 934, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x30 - 1440x900@75Hz */ 442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 443 1688, 1936, 0, 900, 903, 909, 942, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x31 - 1440x900@85Hz */ 446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 447 1696, 1952, 0, 900, 903, 909, 948, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x32 - 1440x900@120Hz RB */ 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 451 1520, 1600, 0, 900, 903, 909, 953, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 453 /* 0x53 - 1600x900@60Hz */ 454 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 455 1704, 1800, 0, 900, 901, 904, 1000, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x33 - 1600x1200@60Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x34 - 1600x1200@65Hz */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x35 - 1600x1200@70Hz */ 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x36 - 1600x1200@75Hz */ 470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x37 - 1600x1200@85Hz */ 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x38 - 1600x1200@120Hz RB */ 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 479 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 481 /* 0x39 - 1680x1050@60Hz RB */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 483 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x3a - 1680x1050@60Hz */ 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 487 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x3b - 1680x1050@75Hz */ 490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 491 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x3c - 1680x1050@85Hz */ 494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 495 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x3d - 1680x1050@120Hz RB */ 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 499 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x3e - 1792x1344@60Hz */ 502 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 503 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x3f - 1792x1344@75Hz */ 506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 507 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x40 - 1792x1344@120Hz RB */ 510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 511 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 /* 0x41 - 1856x1392@60Hz */ 514 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 515 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 517 /* 0x42 - 1856x1392@75Hz */ 518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 519 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x43 - 1856x1392@120Hz RB */ 522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 523 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 525 /* 0x52 - 1920x1080@60Hz */ 526 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 527 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 529 /* 0x44 - 1920x1200@60Hz RB */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 531 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x45 - 1920x1200@60Hz */ 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 535 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x46 - 1920x1200@75Hz */ 538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 539 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x47 - 1920x1200@85Hz */ 542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 543 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 545 /* 0x48 - 1920x1200@120Hz RB */ 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 547 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 549 /* 0x49 - 1920x1440@60Hz */ 550 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 551 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 553 /* 0x4a - 1920x1440@75Hz */ 554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 555 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4b - 1920x1440@120Hz RB */ 558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 559 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 561 /* 0x54 - 2048x1152@60Hz */ 562 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 563 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x4c - 2560x1600@60Hz RB */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 567 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 569 /* 0x4d - 2560x1600@60Hz */ 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 571 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 573 /* 0x4e - 2560x1600@75Hz */ 574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 575 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 577 /* 0x4f - 2560x1600@85Hz */ 578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 579 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 581 /* 0x50 - 2560x1600@120Hz RB */ 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 583 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 585 /* 0x57 - 4096x2160@60Hz RB */ 586 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 587 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 589 /* 0x58 - 4096x2160@59.94Hz RB */ 590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 593 }; 594 595 /* 596 * These more or less come from the DMT spec. The 720x400 modes are 597 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 598 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 599 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 600 * mode. 601 * 602 * The DMT modes have been fact-checked; the rest are mild guesses. 603 */ 604 static const struct drm_display_mode edid_est_modes[] = { 605 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 606 968, 1056, 0, 600, 601, 605, 628, 0, 607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 608 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 609 896, 1024, 0, 600, 601, 603, 625, 0, 610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 612 720, 840, 0, 480, 481, 484, 500, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 615 704, 832, 0, 480, 489, 492, 520, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 617 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 618 768, 864, 0, 480, 483, 486, 525, 0, 619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 620 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 621 752, 800, 0, 480, 490, 492, 525, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 623 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 624 846, 900, 0, 400, 421, 423, 449, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 626 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 627 846, 900, 0, 400, 412, 414, 449, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 629 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 630 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 632 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 633 1136, 1312, 0, 768, 769, 772, 800, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 635 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 636 1184, 1328, 0, 768, 771, 777, 806, 0, 637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 638 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 639 1184, 1344, 0, 768, 771, 777, 806, 0, 640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 641 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 642 1208, 1264, 0, 768, 768, 776, 817, 0, 643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 644 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 645 928, 1152, 0, 624, 625, 628, 667, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 647 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 648 896, 1056, 0, 600, 601, 604, 625, 0, 649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 650 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 651 976, 1040, 0, 600, 637, 643, 666, 0, 652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 653 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 654 1344, 1600, 0, 864, 865, 868, 900, 0, 655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 656 }; 657 658 struct minimode { 659 short w; 660 short h; 661 short r; 662 short rb; 663 }; 664 665 static const struct minimode est3_modes[] = { 666 /* byte 6 */ 667 { 640, 350, 85, 0 }, 668 { 640, 400, 85, 0 }, 669 { 720, 400, 85, 0 }, 670 { 640, 480, 85, 0 }, 671 { 848, 480, 60, 0 }, 672 { 800, 600, 85, 0 }, 673 { 1024, 768, 85, 0 }, 674 { 1152, 864, 75, 0 }, 675 /* byte 7 */ 676 { 1280, 768, 60, 1 }, 677 { 1280, 768, 60, 0 }, 678 { 1280, 768, 75, 0 }, 679 { 1280, 768, 85, 0 }, 680 { 1280, 960, 60, 0 }, 681 { 1280, 960, 85, 0 }, 682 { 1280, 1024, 60, 0 }, 683 { 1280, 1024, 85, 0 }, 684 /* byte 8 */ 685 { 1360, 768, 60, 0 }, 686 { 1440, 900, 60, 1 }, 687 { 1440, 900, 60, 0 }, 688 { 1440, 900, 75, 0 }, 689 { 1440, 900, 85, 0 }, 690 { 1400, 1050, 60, 1 }, 691 { 1400, 1050, 60, 0 }, 692 { 1400, 1050, 75, 0 }, 693 /* byte 9 */ 694 { 1400, 1050, 85, 0 }, 695 { 1680, 1050, 60, 1 }, 696 { 1680, 1050, 60, 0 }, 697 { 1680, 1050, 75, 0 }, 698 { 1680, 1050, 85, 0 }, 699 { 1600, 1200, 60, 0 }, 700 { 1600, 1200, 65, 0 }, 701 { 1600, 1200, 70, 0 }, 702 /* byte 10 */ 703 { 1600, 1200, 75, 0 }, 704 { 1600, 1200, 85, 0 }, 705 { 1792, 1344, 60, 0 }, 706 { 1792, 1344, 75, 0 }, 707 { 1856, 1392, 60, 0 }, 708 { 1856, 1392, 75, 0 }, 709 { 1920, 1200, 60, 1 }, 710 { 1920, 1200, 60, 0 }, 711 /* byte 11 */ 712 { 1920, 1200, 75, 0 }, 713 { 1920, 1200, 85, 0 }, 714 { 1920, 1440, 60, 0 }, 715 { 1920, 1440, 75, 0 }, 716 }; 717 718 static const struct minimode extra_modes[] = { 719 { 1024, 576, 60, 0 }, 720 { 1366, 768, 60, 0 }, 721 { 1600, 900, 60, 0 }, 722 { 1680, 945, 60, 0 }, 723 { 1920, 1080, 60, 0 }, 724 { 2048, 1152, 60, 0 }, 725 { 2048, 1536, 60, 0 }, 726 }; 727 728 /* 729 * From CEA/CTA-861 spec. 730 * 731 * Do not access directly, instead always use cea_mode_for_vic(). 732 */ 733 static const struct drm_display_mode edid_cea_modes_1[] = { 734 /* 1 - 640x480@60Hz 4:3 */ 735 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 736 752, 800, 0, 480, 490, 492, 525, 0, 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 739 /* 2 - 720x480@60Hz 4:3 */ 740 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 741 798, 858, 0, 480, 489, 495, 525, 0, 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 744 /* 3 - 720x480@60Hz 16:9 */ 745 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 746 798, 858, 0, 480, 489, 495, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 748 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 749 /* 4 - 1280x720@60Hz 16:9 */ 750 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 751 1430, 1650, 0, 720, 725, 730, 750, 0, 752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 753 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 5 - 1920x1080i@60Hz 16:9 */ 755 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 756 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 758 DRM_MODE_FLAG_INTERLACE), 759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 760 /* 6 - 720(1440)x480i@60Hz 4:3 */ 761 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 762 801, 858, 0, 480, 488, 494, 525, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 764 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 765 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 766 /* 7 - 720(1440)x480i@60Hz 16:9 */ 767 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 768 801, 858, 0, 480, 488, 494, 525, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 770 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 771 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 772 /* 8 - 720(1440)x240@60Hz 4:3 */ 773 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 774 801, 858, 0, 240, 244, 247, 262, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 776 DRM_MODE_FLAG_DBLCLK), 777 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 778 /* 9 - 720(1440)x240@60Hz 16:9 */ 779 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 780 801, 858, 0, 240, 244, 247, 262, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_DBLCLK), 783 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 784 /* 10 - 2880x480i@60Hz 4:3 */ 785 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 786 3204, 3432, 0, 480, 488, 494, 525, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_INTERLACE), 789 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 790 /* 11 - 2880x480i@60Hz 16:9 */ 791 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 792 3204, 3432, 0, 480, 488, 494, 525, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 794 DRM_MODE_FLAG_INTERLACE), 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 796 /* 12 - 2880x240@60Hz 4:3 */ 797 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 798 3204, 3432, 0, 240, 244, 247, 262, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 801 /* 13 - 2880x240@60Hz 16:9 */ 802 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 803 3204, 3432, 0, 240, 244, 247, 262, 0, 804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 14 - 1440x480@60Hz 4:3 */ 807 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 808 1596, 1716, 0, 480, 489, 495, 525, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 15 - 1440x480@60Hz 16:9 */ 812 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 813 1596, 1716, 0, 480, 489, 495, 525, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 16 - 1920x1080@60Hz 16:9 */ 817 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 818 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 17 - 720x576@50Hz 4:3 */ 822 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 823 796, 864, 0, 576, 581, 586, 625, 0, 824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 826 /* 18 - 720x576@50Hz 16:9 */ 827 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 828 796, 864, 0, 576, 581, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 831 /* 19 - 1280x720@50Hz 16:9 */ 832 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 833 1760, 1980, 0, 720, 725, 730, 750, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 835 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 20 - 1920x1080i@50Hz 16:9 */ 837 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 838 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 840 DRM_MODE_FLAG_INTERLACE), 841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 842 /* 21 - 720(1440)x576i@50Hz 4:3 */ 843 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 844 795, 864, 0, 576, 580, 586, 625, 0, 845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 846 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 847 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 848 /* 22 - 720(1440)x576i@50Hz 16:9 */ 849 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 850 795, 864, 0, 576, 580, 586, 625, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 852 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 853 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 23 - 720(1440)x288@50Hz 4:3 */ 855 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 856 795, 864, 0, 288, 290, 293, 312, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 858 DRM_MODE_FLAG_DBLCLK), 859 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 860 /* 24 - 720(1440)x288@50Hz 16:9 */ 861 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 862 795, 864, 0, 288, 290, 293, 312, 0, 863 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 864 DRM_MODE_FLAG_DBLCLK), 865 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 25 - 2880x576i@50Hz 4:3 */ 867 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 868 3180, 3456, 0, 576, 580, 586, 625, 0, 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 870 DRM_MODE_FLAG_INTERLACE), 871 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 872 /* 26 - 2880x576i@50Hz 16:9 */ 873 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 874 3180, 3456, 0, 576, 580, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 876 DRM_MODE_FLAG_INTERLACE), 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 878 /* 27 - 2880x288@50Hz 4:3 */ 879 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 880 3180, 3456, 0, 288, 290, 293, 312, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 883 /* 28 - 2880x288@50Hz 16:9 */ 884 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 885 3180, 3456, 0, 288, 290, 293, 312, 0, 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 29 - 1440x576@50Hz 4:3 */ 889 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 890 1592, 1728, 0, 576, 581, 586, 625, 0, 891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 893 /* 30 - 1440x576@50Hz 16:9 */ 894 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 895 1592, 1728, 0, 576, 581, 586, 625, 0, 896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 31 - 1920x1080@50Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 900 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 32 - 1920x1080@24Hz 16:9 */ 904 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 905 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 908 /* 33 - 1920x1080@25Hz 16:9 */ 909 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 910 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 34 - 1920x1080@30Hz 16:9 */ 914 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 915 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 918 /* 35 - 2880x480@60Hz 4:3 */ 919 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 920 3192, 3432, 0, 480, 489, 495, 525, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 923 /* 36 - 2880x480@60Hz 16:9 */ 924 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 925 3192, 3432, 0, 480, 489, 495, 525, 0, 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 37 - 2880x576@50Hz 4:3 */ 929 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 930 3184, 3456, 0, 576, 581, 586, 625, 0, 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 932 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 933 /* 38 - 2880x576@50Hz 16:9 */ 934 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 935 3184, 3456, 0, 576, 581, 586, 625, 0, 936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 937 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 938 /* 39 - 1920x1080i@50Hz 16:9 */ 939 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 940 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 942 DRM_MODE_FLAG_INTERLACE), 943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 944 /* 40 - 1920x1080i@100Hz 16:9 */ 945 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 946 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 948 DRM_MODE_FLAG_INTERLACE), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 41 - 1280x720@100Hz 16:9 */ 951 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 952 1760, 1980, 0, 720, 725, 730, 750, 0, 953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 955 /* 42 - 720x576@100Hz 4:3 */ 956 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 957 796, 864, 0, 576, 581, 586, 625, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 960 /* 43 - 720x576@100Hz 16:9 */ 961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 962 796, 864, 0, 576, 581, 586, 625, 0, 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 964 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 965 /* 44 - 720(1440)x576i@100Hz 4:3 */ 966 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 967 795, 864, 0, 576, 580, 586, 625, 0, 968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 971 /* 45 - 720(1440)x576i@100Hz 16:9 */ 972 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 973 795, 864, 0, 576, 580, 586, 625, 0, 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 975 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 977 /* 46 - 1920x1080i@120Hz 16:9 */ 978 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 979 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 981 DRM_MODE_FLAG_INTERLACE), 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 47 - 1280x720@120Hz 16:9 */ 984 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 985 1430, 1650, 0, 720, 725, 730, 750, 0, 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 988 /* 48 - 720x480@120Hz 4:3 */ 989 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 990 798, 858, 0, 480, 489, 495, 525, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 993 /* 49 - 720x480@120Hz 16:9 */ 994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 995 798, 858, 0, 480, 489, 495, 525, 0, 996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 997 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 998 /* 50 - 720(1440)x480i@120Hz 4:3 */ 999 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1000 801, 858, 0, 480, 488, 494, 525, 0, 1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1004 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1005 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1006 801, 858, 0, 480, 488, 494, 525, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1010 /* 52 - 720x576@200Hz 4:3 */ 1011 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1012 796, 864, 0, 576, 581, 586, 625, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1015 /* 53 - 720x576@200Hz 16:9 */ 1016 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1017 796, 864, 0, 576, 581, 586, 625, 0, 1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1020 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1021 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1022 795, 864, 0, 576, 580, 586, 625, 0, 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1026 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1027 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1028 795, 864, 0, 576, 580, 586, 625, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1031 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1032 /* 56 - 720x480@240Hz 4:3 */ 1033 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1034 798, 858, 0, 480, 489, 495, 525, 0, 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1037 /* 57 - 720x480@240Hz 16:9 */ 1038 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1039 798, 858, 0, 480, 489, 495, 525, 0, 1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1042 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1043 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1044 801, 858, 0, 480, 488, 494, 525, 0, 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1048 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1049 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1050 801, 858, 0, 480, 488, 494, 525, 0, 1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1052 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 60 - 1280x720@24Hz 16:9 */ 1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1056 3080, 3300, 0, 720, 725, 730, 750, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 61 - 1280x720@25Hz 16:9 */ 1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1061 3740, 3960, 0, 720, 725, 730, 750, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 62 - 1280x720@30Hz 16:9 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1069 /* 63 - 1920x1080@120Hz 16:9 */ 1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1074 /* 64 - 1920x1080@100Hz 16:9 */ 1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1079 /* 65 - 1280x720@24Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1081 3080, 3300, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 66 - 1280x720@25Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1086 3740, 3960, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 67 - 1280x720@30Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1091 3080, 3300, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 68 - 1280x720@50Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1096 1760, 1980, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 69 - 1280x720@60Hz 64:27 */ 1100 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1101 1430, 1650, 0, 720, 725, 730, 750, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 70 - 1280x720@100Hz 64:27 */ 1105 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1106 1760, 1980, 0, 720, 725, 730, 750, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 71 - 1280x720@120Hz 64:27 */ 1110 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1111 1430, 1650, 0, 720, 725, 730, 750, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 72 - 1920x1080@24Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1116 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 73 - 1920x1080@25Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1121 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 74 - 1920x1080@30Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1126 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 75 - 1920x1080@50Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1131 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 76 - 1920x1080@60Hz 64:27 */ 1135 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1136 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 77 - 1920x1080@100Hz 64:27 */ 1140 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1141 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 78 - 1920x1080@120Hz 64:27 */ 1145 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1146 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 79 - 1680x720@24Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1151 3080, 3300, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 80 - 1680x720@25Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1156 2948, 3168, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 81 - 1680x720@30Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1161 2420, 2640, 0, 720, 725, 730, 750, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 82 - 1680x720@50Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1166 1980, 2200, 0, 720, 725, 730, 750, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 83 - 1680x720@60Hz 64:27 */ 1170 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1171 1980, 2200, 0, 720, 725, 730, 750, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 84 - 1680x720@100Hz 64:27 */ 1175 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1176 1780, 2000, 0, 720, 725, 730, 825, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 85 - 1680x720@120Hz 64:27 */ 1180 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1181 1780, 2000, 0, 720, 725, 730, 825, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 86 - 2560x1080@24Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1186 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 87 - 2560x1080@25Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1191 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 88 - 2560x1080@30Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1196 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 89 - 2560x1080@50Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 90 - 2560x1080@60Hz 64:27 */ 1205 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1206 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1209 /* 91 - 2560x1080@100Hz 64:27 */ 1210 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1211 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1214 /* 92 - 2560x1080@120Hz 64:27 */ 1215 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1216 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1219 /* 93 - 3840x2160@24Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1221 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 94 - 3840x2160@25Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1226 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 95 - 3840x2160@30Hz 16:9 */ 1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1231 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1234 /* 96 - 3840x2160@50Hz 16:9 */ 1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1236 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1239 /* 97 - 3840x2160@60Hz 16:9 */ 1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1241 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1244 /* 98 - 4096x2160@24Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1246 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 99 - 4096x2160@25Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1251 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 100 - 4096x2160@30Hz 256:135 */ 1255 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1256 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1259 /* 101 - 4096x2160@50Hz 256:135 */ 1260 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1261 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1264 /* 102 - 4096x2160@60Hz 256:135 */ 1265 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1266 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1269 /* 103 - 3840x2160@24Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1271 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 104 - 3840x2160@25Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1276 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 105 - 3840x2160@30Hz 64:27 */ 1280 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1281 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1284 /* 106 - 3840x2160@50Hz 64:27 */ 1285 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1286 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 107 - 3840x2160@60Hz 64:27 */ 1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1291 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 108 - 1280x720@48Hz 16:9 */ 1295 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1296 2280, 2500, 0, 720, 725, 730, 750, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 109 - 1280x720@48Hz 64:27 */ 1300 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1301 2280, 2500, 0, 720, 725, 730, 750, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 110 - 1680x720@48Hz 64:27 */ 1305 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1306 2530, 2750, 0, 720, 725, 730, 750, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 111 - 1920x1080@48Hz 16:9 */ 1310 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1311 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 112 - 1920x1080@48Hz 64:27 */ 1315 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1316 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1319 /* 113 - 2560x1080@48Hz 64:27 */ 1320 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1321 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 114 - 3840x2160@48Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1326 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 115 - 4096x2160@48Hz 256:135 */ 1330 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1331 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1334 /* 116 - 3840x2160@48Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1336 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 117 - 3840x2160@100Hz 16:9 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1341 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1344 /* 118 - 3840x2160@120Hz 16:9 */ 1345 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1346 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1349 /* 119 - 3840x2160@100Hz 64:27 */ 1350 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1351 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 120 - 3840x2160@120Hz 64:27 */ 1355 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1356 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 121 - 5120x2160@24Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1361 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 122 - 5120x2160@25Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1366 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 123 - 5120x2160@30Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1371 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 124 - 5120x2160@48Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1376 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 /* 125 - 5120x2160@50Hz 64:27 */ 1380 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1381 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1383 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1384 /* 126 - 5120x2160@60Hz 64:27 */ 1385 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1386 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1388 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1389 /* 127 - 5120x2160@100Hz 64:27 */ 1390 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1391 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1393 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1394 }; 1395 1396 /* 1397 * From CEA/CTA-861 spec. 1398 * 1399 * Do not access directly, instead always use cea_mode_for_vic(). 1400 */ 1401 static const struct drm_display_mode edid_cea_modes_193[] = { 1402 /* 193 - 5120x2160@120Hz 64:27 */ 1403 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1404 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1407 /* 194 - 7680x4320@24Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 195 - 7680x4320@25Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 196 - 7680x4320@30Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 197 - 7680x4320@48Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1424 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 198 - 7680x4320@50Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1429 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 199 - 7680x4320@60Hz 16:9 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1434 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1437 /* 200 - 7680x4320@100Hz 16:9 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1439 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1442 /* 201 - 7680x4320@120Hz 16:9 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1444 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1447 /* 202 - 7680x4320@24Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 203 - 7680x4320@25Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 204 - 7680x4320@30Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 205 - 7680x4320@48Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1464 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 206 - 7680x4320@50Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1469 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 207 - 7680x4320@60Hz 64:27 */ 1473 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1474 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 208 - 7680x4320@100Hz 64:27 */ 1478 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1479 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 209 - 7680x4320@120Hz 64:27 */ 1483 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1484 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 210 - 10240x4320@24Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 211 - 10240x4320@25Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 212 - 10240x4320@30Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 213 - 10240x4320@48Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1504 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 214 - 10240x4320@50Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1509 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 215 - 10240x4320@60Hz 64:27 */ 1513 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1514 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1517 /* 216 - 10240x4320@100Hz 64:27 */ 1518 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1519 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1522 /* 217 - 10240x4320@120Hz 64:27 */ 1523 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1524 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1526 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1527 /* 218 - 4096x2160@100Hz 256:135 */ 1528 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1529 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1531 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1532 /* 219 - 4096x2160@120Hz 256:135 */ 1533 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1534 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1537 }; 1538 1539 /* 1540 * HDMI 1.4 4k modes. Index using the VIC. 1541 */ 1542 static const struct drm_display_mode edid_4k_modes[] = { 1543 /* 0 - dummy, VICs start at 1 */ 1544 { }, 1545 /* 1 - 3840x2160@30Hz */ 1546 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1547 3840, 4016, 4104, 4400, 0, 1548 2160, 2168, 2178, 2250, 0, 1549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1550 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1551 /* 2 - 3840x2160@25Hz */ 1552 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1553 3840, 4896, 4984, 5280, 0, 1554 2160, 2168, 2178, 2250, 0, 1555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1556 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1557 /* 3 - 3840x2160@24Hz */ 1558 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1559 3840, 5116, 5204, 5500, 0, 1560 2160, 2168, 2178, 2250, 0, 1561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1562 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1563 /* 4 - 4096x2160@24Hz (SMPTE) */ 1564 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1565 4096, 5116, 5204, 5500, 0, 1566 2160, 2168, 2178, 2250, 0, 1567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1568 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1569 }; 1570 1571 /*** DDC fetch and block validation ***/ 1572 1573 /* 1574 * The opaque EDID type, internal to drm_edid.c. 1575 */ 1576 struct drm_edid { 1577 /* Size allocated for edid */ 1578 size_t size; 1579 const struct edid *edid; 1580 }; 1581 1582 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1583 1584 static int edid_hfeeodb_block_count(const struct edid *edid) 1585 { 1586 int eeodb = edid_hfeeodb_extension_block_count(edid); 1587 1588 return eeodb ? eeodb + 1 : 0; 1589 } 1590 1591 static int edid_extension_block_count(const struct edid *edid) 1592 { 1593 return edid->extensions; 1594 } 1595 1596 static int edid_block_count(const struct edid *edid) 1597 { 1598 return edid_extension_block_count(edid) + 1; 1599 } 1600 1601 static int edid_size_by_blocks(int num_blocks) 1602 { 1603 return num_blocks * EDID_LENGTH; 1604 } 1605 1606 static int edid_size(const struct edid *edid) 1607 { 1608 return edid_size_by_blocks(edid_block_count(edid)); 1609 } 1610 1611 static const void *edid_block_data(const struct edid *edid, int index) 1612 { 1613 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1614 1615 return edid + index; 1616 } 1617 1618 static const void *edid_extension_block_data(const struct edid *edid, int index) 1619 { 1620 return edid_block_data(edid, index + 1); 1621 } 1622 1623 /* EDID block count indicated in EDID, may exceed allocated size */ 1624 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1625 { 1626 int num_blocks; 1627 1628 /* Starting point */ 1629 num_blocks = edid_block_count(drm_edid->edid); 1630 1631 /* HF-EEODB override */ 1632 if (drm_edid->size >= edid_size_by_blocks(2)) { 1633 int eeodb; 1634 1635 /* 1636 * Note: HF-EEODB may specify a smaller extension count than the 1637 * regular one. Unlike in buffer allocation, here we can use it. 1638 */ 1639 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1640 if (eeodb) 1641 num_blocks = eeodb; 1642 } 1643 1644 return num_blocks; 1645 } 1646 1647 /* EDID block count, limited by allocated size */ 1648 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1649 { 1650 /* Limit by allocated size */ 1651 return min(__drm_edid_block_count(drm_edid), 1652 (int)drm_edid->size / EDID_LENGTH); 1653 } 1654 1655 /* EDID extension block count, limited by allocated size */ 1656 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1657 { 1658 return drm_edid_block_count(drm_edid) - 1; 1659 } 1660 1661 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1662 { 1663 return edid_block_data(drm_edid->edid, index); 1664 } 1665 1666 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1667 int index) 1668 { 1669 return edid_extension_block_data(drm_edid->edid, index); 1670 } 1671 1672 /* 1673 * Initializer helper for legacy interfaces, where we have no choice but to 1674 * trust edid size. Not for general purpose use. 1675 */ 1676 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1677 const struct edid *edid) 1678 { 1679 if (!edid) 1680 return NULL; 1681 1682 memset(drm_edid, 0, sizeof(*drm_edid)); 1683 1684 drm_edid->edid = edid; 1685 drm_edid->size = edid_size(edid); 1686 1687 return drm_edid; 1688 } 1689 1690 /* 1691 * EDID base and extension block iterator. 1692 * 1693 * struct drm_edid_iter iter; 1694 * const u8 *block; 1695 * 1696 * drm_edid_iter_begin(drm_edid, &iter); 1697 * drm_edid_iter_for_each(block, &iter) { 1698 * // do stuff with block 1699 * } 1700 * drm_edid_iter_end(&iter); 1701 */ 1702 struct drm_edid_iter { 1703 const struct drm_edid *drm_edid; 1704 1705 /* Current block index. */ 1706 int index; 1707 }; 1708 1709 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1710 struct drm_edid_iter *iter) 1711 { 1712 memset(iter, 0, sizeof(*iter)); 1713 1714 iter->drm_edid = drm_edid; 1715 } 1716 1717 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1718 { 1719 const void *block = NULL; 1720 1721 if (!iter->drm_edid) 1722 return NULL; 1723 1724 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1725 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1726 1727 return block; 1728 } 1729 1730 #define drm_edid_iter_for_each(__block, __iter) \ 1731 while (((__block) = __drm_edid_iter_next(__iter))) 1732 1733 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1734 { 1735 memset(iter, 0, sizeof(*iter)); 1736 } 1737 1738 static const u8 edid_header[] = { 1739 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1740 }; 1741 1742 static void edid_header_fix(void *edid) 1743 { 1744 memcpy(edid, edid_header, sizeof(edid_header)); 1745 } 1746 1747 /** 1748 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1749 * @_edid: pointer to raw base EDID block 1750 * 1751 * Sanity check the header of the base EDID block. 1752 * 1753 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1754 */ 1755 int drm_edid_header_is_valid(const void *_edid) 1756 { 1757 const struct edid *edid = _edid; 1758 int i, score = 0; 1759 1760 for (i = 0; i < sizeof(edid_header); i++) { 1761 if (edid->header[i] == edid_header[i]) 1762 score++; 1763 } 1764 1765 return score; 1766 } 1767 EXPORT_SYMBOL(drm_edid_header_is_valid); 1768 1769 static int edid_fixup __read_mostly = 6; 1770 module_param_named(edid_fixup, edid_fixup, int, 0400); 1771 MODULE_PARM_DESC(edid_fixup, 1772 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1773 1774 static int edid_block_compute_checksum(const void *_block) 1775 { 1776 const u8 *block = _block; 1777 int i; 1778 u8 csum = 0, crc = 0; 1779 1780 for (i = 0; i < EDID_LENGTH - 1; i++) 1781 csum += block[i]; 1782 1783 crc = 0x100 - csum; 1784 1785 return crc; 1786 } 1787 1788 static int edid_block_get_checksum(const void *_block) 1789 { 1790 const struct edid *block = _block; 1791 1792 return block->checksum; 1793 } 1794 1795 static int edid_block_tag(const void *_block) 1796 { 1797 const u8 *block = _block; 1798 1799 return block[0]; 1800 } 1801 1802 static bool edid_block_is_zero(const void *edid) 1803 { 1804 return !memchr_inv(edid, 0, EDID_LENGTH); 1805 } 1806 1807 /** 1808 * drm_edid_are_equal - compare two edid blobs. 1809 * @edid1: pointer to first blob 1810 * @edid2: pointer to second blob 1811 * This helper can be used during probing to determine if 1812 * edid had changed. 1813 */ 1814 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1815 { 1816 int edid1_len, edid2_len; 1817 bool edid1_present = edid1 != NULL; 1818 bool edid2_present = edid2 != NULL; 1819 1820 if (edid1_present != edid2_present) 1821 return false; 1822 1823 if (edid1) { 1824 edid1_len = edid_size(edid1); 1825 edid2_len = edid_size(edid2); 1826 1827 if (edid1_len != edid2_len) 1828 return false; 1829 1830 if (memcmp(edid1, edid2, edid1_len)) 1831 return false; 1832 } 1833 1834 return true; 1835 } 1836 EXPORT_SYMBOL(drm_edid_are_equal); 1837 1838 enum edid_block_status { 1839 EDID_BLOCK_OK = 0, 1840 EDID_BLOCK_READ_FAIL, 1841 EDID_BLOCK_NULL, 1842 EDID_BLOCK_ZERO, 1843 EDID_BLOCK_HEADER_CORRUPT, 1844 EDID_BLOCK_HEADER_REPAIR, 1845 EDID_BLOCK_HEADER_FIXED, 1846 EDID_BLOCK_CHECKSUM, 1847 EDID_BLOCK_VERSION, 1848 }; 1849 1850 static enum edid_block_status edid_block_check(const void *_block, 1851 bool is_base_block) 1852 { 1853 const struct edid *block = _block; 1854 1855 if (!block) 1856 return EDID_BLOCK_NULL; 1857 1858 if (is_base_block) { 1859 int score = drm_edid_header_is_valid(block); 1860 1861 if (score < clamp(edid_fixup, 0, 8)) { 1862 if (edid_block_is_zero(block)) 1863 return EDID_BLOCK_ZERO; 1864 else 1865 return EDID_BLOCK_HEADER_CORRUPT; 1866 } 1867 1868 if (score < 8) 1869 return EDID_BLOCK_HEADER_REPAIR; 1870 } 1871 1872 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1873 if (edid_block_is_zero(block)) 1874 return EDID_BLOCK_ZERO; 1875 else 1876 return EDID_BLOCK_CHECKSUM; 1877 } 1878 1879 if (is_base_block) { 1880 if (block->version != 1) 1881 return EDID_BLOCK_VERSION; 1882 } 1883 1884 return EDID_BLOCK_OK; 1885 } 1886 1887 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1888 { 1889 return status == EDID_BLOCK_OK || 1890 status == EDID_BLOCK_HEADER_FIXED || 1891 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1892 } 1893 1894 static bool edid_block_valid(const void *block, bool base) 1895 { 1896 return edid_block_status_valid(edid_block_check(block, base), 1897 edid_block_tag(block)); 1898 } 1899 1900 static void edid_block_status_print(enum edid_block_status status, 1901 const struct edid *block, 1902 int block_num) 1903 { 1904 switch (status) { 1905 case EDID_BLOCK_OK: 1906 break; 1907 case EDID_BLOCK_READ_FAIL: 1908 pr_debug("EDID block %d read failed\n", block_num); 1909 break; 1910 case EDID_BLOCK_NULL: 1911 pr_debug("EDID block %d pointer is NULL\n", block_num); 1912 break; 1913 case EDID_BLOCK_ZERO: 1914 pr_notice("EDID block %d is all zeroes\n", block_num); 1915 break; 1916 case EDID_BLOCK_HEADER_CORRUPT: 1917 pr_notice("EDID has corrupt header\n"); 1918 break; 1919 case EDID_BLOCK_HEADER_REPAIR: 1920 pr_debug("EDID corrupt header needs repair\n"); 1921 break; 1922 case EDID_BLOCK_HEADER_FIXED: 1923 pr_debug("EDID corrupt header fixed\n"); 1924 break; 1925 case EDID_BLOCK_CHECKSUM: 1926 if (edid_block_status_valid(status, edid_block_tag(block))) { 1927 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1928 block_num, edid_block_tag(block), 1929 edid_block_compute_checksum(block)); 1930 } else { 1931 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1932 block_num, edid_block_tag(block), 1933 edid_block_compute_checksum(block)); 1934 } 1935 break; 1936 case EDID_BLOCK_VERSION: 1937 pr_notice("EDID has major version %d, instead of 1\n", 1938 block->version); 1939 break; 1940 default: 1941 WARN(1, "EDID block %d unknown edid block status code %d\n", 1942 block_num, status); 1943 break; 1944 } 1945 } 1946 1947 static void edid_block_dump(const char *level, const void *block, int block_num) 1948 { 1949 enum edid_block_status status; 1950 char prefix[20]; 1951 1952 status = edid_block_check(block, block_num == 0); 1953 if (status == EDID_BLOCK_ZERO) 1954 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1955 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1956 sprintf(prefix, "\t[%02x] BAD ", block_num); 1957 else 1958 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1959 1960 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1961 block, EDID_LENGTH, false); 1962 } 1963 1964 /** 1965 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1966 * @_block: pointer to raw EDID block 1967 * @block_num: type of block to validate (0 for base, extension otherwise) 1968 * @print_bad_edid: if true, dump bad EDID blocks to the console 1969 * @edid_corrupt: if true, the header or checksum is invalid 1970 * 1971 * Validate a base or extension EDID block and optionally dump bad blocks to 1972 * the console. 1973 * 1974 * Return: True if the block is valid, false otherwise. 1975 */ 1976 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1977 bool *edid_corrupt) 1978 { 1979 struct edid *block = (struct edid *)_block; 1980 enum edid_block_status status; 1981 bool is_base_block = block_num == 0; 1982 bool valid; 1983 1984 if (WARN_ON(!block)) 1985 return false; 1986 1987 status = edid_block_check(block, is_base_block); 1988 if (status == EDID_BLOCK_HEADER_REPAIR) { 1989 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1990 edid_header_fix(block); 1991 1992 /* Retry with fixed header, update status if that worked. */ 1993 status = edid_block_check(block, is_base_block); 1994 if (status == EDID_BLOCK_OK) 1995 status = EDID_BLOCK_HEADER_FIXED; 1996 } 1997 1998 if (edid_corrupt) { 1999 /* 2000 * Unknown major version isn't corrupt but we can't use it. Only 2001 * the base block can reset edid_corrupt to false. 2002 */ 2003 if (is_base_block && 2004 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2005 *edid_corrupt = false; 2006 else if (status != EDID_BLOCK_OK) 2007 *edid_corrupt = true; 2008 } 2009 2010 edid_block_status_print(status, block, block_num); 2011 2012 /* Determine whether we can use this block with this status. */ 2013 valid = edid_block_status_valid(status, edid_block_tag(block)); 2014 2015 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2016 pr_notice("Raw EDID:\n"); 2017 edid_block_dump(KERN_NOTICE, block, block_num); 2018 } 2019 2020 return valid; 2021 } 2022 EXPORT_SYMBOL(drm_edid_block_valid); 2023 2024 /** 2025 * drm_edid_is_valid - sanity check EDID data 2026 * @edid: EDID data 2027 * 2028 * Sanity-check an entire EDID record (including extensions) 2029 * 2030 * Return: True if the EDID data is valid, false otherwise. 2031 */ 2032 bool drm_edid_is_valid(struct edid *edid) 2033 { 2034 int i; 2035 2036 if (!edid) 2037 return false; 2038 2039 for (i = 0; i < edid_block_count(edid); i++) { 2040 void *block = (void *)edid_block_data(edid, i); 2041 2042 if (!drm_edid_block_valid(block, i, true, NULL)) 2043 return false; 2044 } 2045 2046 return true; 2047 } 2048 EXPORT_SYMBOL(drm_edid_is_valid); 2049 2050 /** 2051 * drm_edid_valid - sanity check EDID data 2052 * @drm_edid: EDID data 2053 * 2054 * Sanity check an EDID. Cross check block count against allocated size and 2055 * checksum the blocks. 2056 * 2057 * Return: True if the EDID data is valid, false otherwise. 2058 */ 2059 bool drm_edid_valid(const struct drm_edid *drm_edid) 2060 { 2061 int i; 2062 2063 if (!drm_edid) 2064 return false; 2065 2066 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2067 return false; 2068 2069 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2070 const void *block = drm_edid_block_data(drm_edid, i); 2071 2072 if (!edid_block_valid(block, i == 0)) 2073 return false; 2074 } 2075 2076 return true; 2077 } 2078 EXPORT_SYMBOL(drm_edid_valid); 2079 2080 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2081 size_t *alloc_size) 2082 { 2083 struct edid *new; 2084 int i, valid_blocks = 0; 2085 2086 /* 2087 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2088 * back to regular extension count here. We don't want to start 2089 * modifying the HF-EEODB extension too. 2090 */ 2091 for (i = 0; i < edid_block_count(edid); i++) { 2092 const void *src_block = edid_block_data(edid, i); 2093 2094 if (edid_block_valid(src_block, i == 0)) { 2095 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2096 2097 memmove(dst_block, src_block, EDID_LENGTH); 2098 valid_blocks++; 2099 } 2100 } 2101 2102 /* We already trusted the base block to be valid here... */ 2103 if (WARN_ON(!valid_blocks)) { 2104 kfree(edid); 2105 return NULL; 2106 } 2107 2108 edid->extensions = valid_blocks - 1; 2109 edid->checksum = edid_block_compute_checksum(edid); 2110 2111 *alloc_size = edid_size_by_blocks(valid_blocks); 2112 2113 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2114 if (!new) 2115 kfree(edid); 2116 2117 return new; 2118 } 2119 2120 #define DDC_SEGMENT_ADDR 0x30 2121 /** 2122 * drm_do_probe_ddc_edid() - get EDID information via I2C 2123 * @data: I2C device adapter 2124 * @buf: EDID data buffer to be filled 2125 * @block: 128 byte EDID block to start fetching from 2126 * @len: EDID data buffer length to fetch 2127 * 2128 * Try to fetch EDID information by calling I2C driver functions. 2129 * 2130 * Return: 0 on success or -1 on failure. 2131 */ 2132 static int 2133 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2134 { 2135 struct i2c_adapter *adapter = data; 2136 unsigned char start = block * EDID_LENGTH; 2137 unsigned char segment = block >> 1; 2138 unsigned char xfers = segment ? 3 : 2; 2139 int ret, retries = 5; 2140 2141 /* 2142 * The core I2C driver will automatically retry the transfer if the 2143 * adapter reports EAGAIN. However, we find that bit-banging transfers 2144 * are susceptible to errors under a heavily loaded machine and 2145 * generate spurious NAKs and timeouts. Retrying the transfer 2146 * of the individual block a few times seems to overcome this. 2147 */ 2148 do { 2149 struct i2c_msg msgs[] = { 2150 { 2151 .addr = DDC_SEGMENT_ADDR, 2152 .flags = 0, 2153 .len = 1, 2154 .buf = &segment, 2155 }, { 2156 .addr = DDC_ADDR, 2157 .flags = 0, 2158 .len = 1, 2159 .buf = &start, 2160 }, { 2161 .addr = DDC_ADDR, 2162 .flags = I2C_M_RD, 2163 .len = len, 2164 .buf = buf, 2165 } 2166 }; 2167 2168 /* 2169 * Avoid sending the segment addr to not upset non-compliant 2170 * DDC monitors. 2171 */ 2172 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2173 2174 if (ret == -ENXIO) { 2175 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2176 adapter->name); 2177 break; 2178 } 2179 } while (ret != xfers && --retries); 2180 2181 return ret == xfers ? 0 : -1; 2182 } 2183 2184 static void connector_bad_edid(struct drm_connector *connector, 2185 const struct edid *edid, int num_blocks) 2186 { 2187 int i; 2188 u8 last_block; 2189 2190 /* 2191 * 0x7e in the EDID is the number of extension blocks. The EDID 2192 * is 1 (base block) + num_ext_blocks big. That means we can think 2193 * of 0x7e in the EDID of the _index_ of the last block in the 2194 * combined chunk of memory. 2195 */ 2196 last_block = edid->extensions; 2197 2198 /* Calculate real checksum for the last edid extension block data */ 2199 if (last_block < num_blocks) 2200 connector->real_edid_checksum = 2201 edid_block_compute_checksum(edid + last_block); 2202 2203 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2204 return; 2205 2206 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2207 connector->base.id, connector->name); 2208 for (i = 0; i < num_blocks; i++) 2209 edid_block_dump(KERN_DEBUG, edid + i, i); 2210 } 2211 2212 /* Get override or firmware EDID */ 2213 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2214 { 2215 const struct drm_edid *override = NULL; 2216 2217 mutex_lock(&connector->edid_override_mutex); 2218 2219 if (connector->edid_override) 2220 override = drm_edid_dup(connector->edid_override); 2221 2222 mutex_unlock(&connector->edid_override_mutex); 2223 2224 if (!override) 2225 override = drm_edid_load_firmware(connector); 2226 2227 return IS_ERR(override) ? NULL : override; 2228 } 2229 2230 /* For debugfs edid_override implementation */ 2231 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2232 { 2233 const struct drm_edid *drm_edid; 2234 2235 mutex_lock(&connector->edid_override_mutex); 2236 2237 drm_edid = connector->edid_override; 2238 if (drm_edid) 2239 seq_write(m, drm_edid->edid, drm_edid->size); 2240 2241 mutex_unlock(&connector->edid_override_mutex); 2242 2243 return 0; 2244 } 2245 2246 /* For debugfs edid_override implementation */ 2247 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2248 size_t size) 2249 { 2250 const struct drm_edid *drm_edid; 2251 2252 drm_edid = drm_edid_alloc(edid, size); 2253 if (!drm_edid_valid(drm_edid)) { 2254 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2255 connector->base.id, connector->name); 2256 drm_edid_free(drm_edid); 2257 return -EINVAL; 2258 } 2259 2260 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2261 connector->base.id, connector->name); 2262 2263 mutex_lock(&connector->edid_override_mutex); 2264 2265 drm_edid_free(connector->edid_override); 2266 connector->edid_override = drm_edid; 2267 2268 mutex_unlock(&connector->edid_override_mutex); 2269 2270 return 0; 2271 } 2272 2273 /* For debugfs edid_override implementation */ 2274 int drm_edid_override_reset(struct drm_connector *connector) 2275 { 2276 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2277 connector->base.id, connector->name); 2278 2279 mutex_lock(&connector->edid_override_mutex); 2280 2281 drm_edid_free(connector->edid_override); 2282 connector->edid_override = NULL; 2283 2284 mutex_unlock(&connector->edid_override_mutex); 2285 2286 return 0; 2287 } 2288 2289 /** 2290 * drm_edid_override_connector_update - add modes from override/firmware EDID 2291 * @connector: connector we're probing 2292 * 2293 * Add modes from the override/firmware EDID, if available. Only to be used from 2294 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2295 * failed during drm_get_edid() and caused the override/firmware EDID to be 2296 * skipped. 2297 * 2298 * Return: The number of modes added or 0 if we couldn't find any. 2299 */ 2300 int drm_edid_override_connector_update(struct drm_connector *connector) 2301 { 2302 const struct drm_edid *override; 2303 int num_modes = 0; 2304 2305 override = drm_edid_override_get(connector); 2306 if (override) { 2307 num_modes = drm_edid_connector_update(connector, override); 2308 2309 drm_edid_free(override); 2310 2311 drm_dbg_kms(connector->dev, 2312 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2313 connector->base.id, connector->name, num_modes); 2314 } 2315 2316 return num_modes; 2317 } 2318 EXPORT_SYMBOL(drm_edid_override_connector_update); 2319 2320 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2321 2322 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2323 read_block_fn read_block, 2324 void *context) 2325 { 2326 enum edid_block_status status; 2327 bool is_base_block = block_num == 0; 2328 int try; 2329 2330 for (try = 0; try < 4; try++) { 2331 if (read_block(context, block, block_num, EDID_LENGTH)) 2332 return EDID_BLOCK_READ_FAIL; 2333 2334 status = edid_block_check(block, is_base_block); 2335 if (status == EDID_BLOCK_HEADER_REPAIR) { 2336 edid_header_fix(block); 2337 2338 /* Retry with fixed header, update status if that worked. */ 2339 status = edid_block_check(block, is_base_block); 2340 if (status == EDID_BLOCK_OK) 2341 status = EDID_BLOCK_HEADER_FIXED; 2342 } 2343 2344 if (edid_block_status_valid(status, edid_block_tag(block))) 2345 break; 2346 2347 /* Fail early for unrepairable base block all zeros. */ 2348 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2349 break; 2350 } 2351 2352 return status; 2353 } 2354 2355 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2356 read_block_fn read_block, void *context, 2357 size_t *size) 2358 { 2359 enum edid_block_status status; 2360 int i, num_blocks, invalid_blocks = 0; 2361 const struct drm_edid *override; 2362 struct edid *edid, *new; 2363 size_t alloc_size = EDID_LENGTH; 2364 2365 override = drm_edid_override_get(connector); 2366 if (override) { 2367 alloc_size = override->size; 2368 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2369 drm_edid_free(override); 2370 if (!edid) 2371 return NULL; 2372 goto ok; 2373 } 2374 2375 edid = kmalloc(alloc_size, GFP_KERNEL); 2376 if (!edid) 2377 return NULL; 2378 2379 status = edid_block_read(edid, 0, read_block, context); 2380 2381 edid_block_status_print(status, edid, 0); 2382 2383 if (status == EDID_BLOCK_READ_FAIL) 2384 goto fail; 2385 2386 /* FIXME: Clarify what a corrupt EDID actually means. */ 2387 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2388 connector->edid_corrupt = false; 2389 else 2390 connector->edid_corrupt = true; 2391 2392 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2393 if (status == EDID_BLOCK_ZERO) 2394 connector->null_edid_counter++; 2395 2396 connector_bad_edid(connector, edid, 1); 2397 goto fail; 2398 } 2399 2400 if (!edid_extension_block_count(edid)) 2401 goto ok; 2402 2403 alloc_size = edid_size(edid); 2404 new = krealloc(edid, alloc_size, GFP_KERNEL); 2405 if (!new) 2406 goto fail; 2407 edid = new; 2408 2409 num_blocks = edid_block_count(edid); 2410 for (i = 1; i < num_blocks; i++) { 2411 void *block = (void *)edid_block_data(edid, i); 2412 2413 status = edid_block_read(block, i, read_block, context); 2414 2415 edid_block_status_print(status, block, i); 2416 2417 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2418 if (status == EDID_BLOCK_READ_FAIL) 2419 goto fail; 2420 invalid_blocks++; 2421 } else if (i == 1) { 2422 /* 2423 * If the first EDID extension is a CTA extension, and 2424 * the first Data Block is HF-EEODB, override the 2425 * extension block count. 2426 * 2427 * Note: HF-EEODB could specify a smaller extension 2428 * count too, but we can't risk allocating a smaller 2429 * amount. 2430 */ 2431 int eeodb = edid_hfeeodb_block_count(edid); 2432 2433 if (eeodb > num_blocks) { 2434 num_blocks = eeodb; 2435 alloc_size = edid_size_by_blocks(num_blocks); 2436 new = krealloc(edid, alloc_size, GFP_KERNEL); 2437 if (!new) 2438 goto fail; 2439 edid = new; 2440 } 2441 } 2442 } 2443 2444 if (invalid_blocks) { 2445 connector_bad_edid(connector, edid, num_blocks); 2446 2447 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2448 } 2449 2450 ok: 2451 if (size) 2452 *size = alloc_size; 2453 2454 return edid; 2455 2456 fail: 2457 kfree(edid); 2458 return NULL; 2459 } 2460 2461 /** 2462 * drm_do_get_edid - get EDID data using a custom EDID block read function 2463 * @connector: connector we're probing 2464 * @read_block: EDID block read function 2465 * @context: private data passed to the block read function 2466 * 2467 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2468 * exposes a different interface to read EDID blocks this function can be used 2469 * to get EDID data using a custom block read function. 2470 * 2471 * As in the general case the DDC bus is accessible by the kernel at the I2C 2472 * level, drivers must make all reasonable efforts to expose it as an I2C 2473 * adapter and use drm_get_edid() instead of abusing this function. 2474 * 2475 * The EDID may be overridden using debugfs override_edid or firmware EDID 2476 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2477 * order. Having either of them bypasses actual EDID reads. 2478 * 2479 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2480 */ 2481 struct edid *drm_do_get_edid(struct drm_connector *connector, 2482 read_block_fn read_block, 2483 void *context) 2484 { 2485 return _drm_do_get_edid(connector, read_block, context, NULL); 2486 } 2487 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2488 2489 /** 2490 * drm_edid_raw - Get a pointer to the raw EDID data. 2491 * @drm_edid: drm_edid container 2492 * 2493 * Get a pointer to the raw EDID data. 2494 * 2495 * This is for transition only. Avoid using this like the plague. 2496 * 2497 * Return: Pointer to raw EDID data. 2498 */ 2499 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2500 { 2501 if (!drm_edid || !drm_edid->size) 2502 return NULL; 2503 2504 /* 2505 * Do not return pointers where relying on EDID extension count would 2506 * lead to buffer overflow. 2507 */ 2508 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2509 return NULL; 2510 2511 return drm_edid->edid; 2512 } 2513 EXPORT_SYMBOL(drm_edid_raw); 2514 2515 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2516 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2517 { 2518 struct drm_edid *drm_edid; 2519 2520 if (!edid || !size || size < EDID_LENGTH) 2521 return NULL; 2522 2523 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2524 if (drm_edid) { 2525 drm_edid->edid = edid; 2526 drm_edid->size = size; 2527 } 2528 2529 return drm_edid; 2530 } 2531 2532 /** 2533 * drm_edid_alloc - Allocate a new drm_edid container 2534 * @edid: Pointer to raw EDID data 2535 * @size: Size of memory allocated for EDID 2536 * 2537 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2538 * the actual size that has been allocated for the data. There is no validation 2539 * of the raw EDID data against the size, but at least the EDID base block must 2540 * fit in the buffer. 2541 * 2542 * The returned pointer must be freed using drm_edid_free(). 2543 * 2544 * Return: drm_edid container, or NULL on errors 2545 */ 2546 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2547 { 2548 const struct drm_edid *drm_edid; 2549 2550 if (!edid || !size || size < EDID_LENGTH) 2551 return NULL; 2552 2553 edid = kmemdup(edid, size, GFP_KERNEL); 2554 if (!edid) 2555 return NULL; 2556 2557 drm_edid = _drm_edid_alloc(edid, size); 2558 if (!drm_edid) 2559 kfree(edid); 2560 2561 return drm_edid; 2562 } 2563 EXPORT_SYMBOL(drm_edid_alloc); 2564 2565 /** 2566 * drm_edid_dup - Duplicate a drm_edid container 2567 * @drm_edid: EDID to duplicate 2568 * 2569 * The returned pointer must be freed using drm_edid_free(). 2570 * 2571 * Returns: drm_edid container copy, or NULL on errors 2572 */ 2573 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2574 { 2575 if (!drm_edid) 2576 return NULL; 2577 2578 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2579 } 2580 EXPORT_SYMBOL(drm_edid_dup); 2581 2582 /** 2583 * drm_edid_free - Free the drm_edid container 2584 * @drm_edid: EDID to free 2585 */ 2586 void drm_edid_free(const struct drm_edid *drm_edid) 2587 { 2588 if (!drm_edid) 2589 return; 2590 2591 kfree(drm_edid->edid); 2592 kfree(drm_edid); 2593 } 2594 EXPORT_SYMBOL(drm_edid_free); 2595 2596 /** 2597 * drm_probe_ddc() - probe DDC presence 2598 * @adapter: I2C adapter to probe 2599 * 2600 * Return: True on success, false on failure. 2601 */ 2602 bool 2603 drm_probe_ddc(struct i2c_adapter *adapter) 2604 { 2605 unsigned char out; 2606 2607 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2608 } 2609 EXPORT_SYMBOL(drm_probe_ddc); 2610 2611 /** 2612 * drm_get_edid - get EDID data, if available 2613 * @connector: connector we're probing 2614 * @adapter: I2C adapter to use for DDC 2615 * 2616 * Poke the given I2C channel to grab EDID data if possible. If found, 2617 * attach it to the connector. 2618 * 2619 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2620 */ 2621 struct edid *drm_get_edid(struct drm_connector *connector, 2622 struct i2c_adapter *adapter) 2623 { 2624 struct edid *edid; 2625 2626 if (connector->force == DRM_FORCE_OFF) 2627 return NULL; 2628 2629 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2630 return NULL; 2631 2632 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2633 drm_connector_update_edid_property(connector, edid); 2634 return edid; 2635 } 2636 EXPORT_SYMBOL(drm_get_edid); 2637 2638 /** 2639 * drm_edid_read_custom - Read EDID data using given EDID block read function 2640 * @connector: Connector to use 2641 * @read_block: EDID block read function 2642 * @context: Private data passed to the block read function 2643 * 2644 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2645 * exposes a different interface to read EDID blocks this function can be used 2646 * to get EDID data using a custom block read function. 2647 * 2648 * As in the general case the DDC bus is accessible by the kernel at the I2C 2649 * level, drivers must make all reasonable efforts to expose it as an I2C 2650 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2651 * this function. 2652 * 2653 * The EDID may be overridden using debugfs override_edid or firmware EDID 2654 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2655 * order. Having either of them bypasses actual EDID reads. 2656 * 2657 * The returned pointer must be freed using drm_edid_free(). 2658 * 2659 * Return: Pointer to EDID, or NULL if probe/read failed. 2660 */ 2661 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2662 read_block_fn read_block, 2663 void *context) 2664 { 2665 const struct drm_edid *drm_edid; 2666 struct edid *edid; 2667 size_t size = 0; 2668 2669 edid = _drm_do_get_edid(connector, read_block, context, &size); 2670 if (!edid) 2671 return NULL; 2672 2673 /* Sanity check for now */ 2674 drm_WARN_ON(connector->dev, !size); 2675 2676 drm_edid = _drm_edid_alloc(edid, size); 2677 if (!drm_edid) 2678 kfree(edid); 2679 2680 return drm_edid; 2681 } 2682 EXPORT_SYMBOL(drm_edid_read_custom); 2683 2684 /** 2685 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2686 * @connector: Connector to use 2687 * @adapter: I2C adapter to use for DDC 2688 * 2689 * Read EDID using the given I2C adapter. 2690 * 2691 * The EDID may be overridden using debugfs override_edid or firmware EDID 2692 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2693 * order. Having either of them bypasses actual EDID reads. 2694 * 2695 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2696 * using drm_edid_read() instead of this function. 2697 * 2698 * The returned pointer must be freed using drm_edid_free(). 2699 * 2700 * Return: Pointer to EDID, or NULL if probe/read failed. 2701 */ 2702 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2703 struct i2c_adapter *adapter) 2704 { 2705 const struct drm_edid *drm_edid; 2706 2707 if (connector->force == DRM_FORCE_OFF) 2708 return NULL; 2709 2710 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2711 return NULL; 2712 2713 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2714 2715 /* Note: Do *not* call connector updates here. */ 2716 2717 return drm_edid; 2718 } 2719 EXPORT_SYMBOL(drm_edid_read_ddc); 2720 2721 /** 2722 * drm_edid_read - Read EDID data using connector's I2C adapter 2723 * @connector: Connector to use 2724 * 2725 * Read EDID using the connector's I2C adapter. 2726 * 2727 * The EDID may be overridden using debugfs override_edid or firmware EDID 2728 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2729 * order. Having either of them bypasses actual EDID reads. 2730 * 2731 * The returned pointer must be freed using drm_edid_free(). 2732 * 2733 * Return: Pointer to EDID, or NULL if probe/read failed. 2734 */ 2735 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2736 { 2737 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2738 return NULL; 2739 2740 return drm_edid_read_ddc(connector, connector->ddc); 2741 } 2742 EXPORT_SYMBOL(drm_edid_read); 2743 2744 static u32 edid_extract_panel_id(const struct edid *edid) 2745 { 2746 /* 2747 * We represent the ID as a 32-bit number so it can easily be compared 2748 * with "==". 2749 * 2750 * NOTE that we deal with endianness differently for the top half 2751 * of this ID than for the bottom half. The bottom half (the product 2752 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2753 * that's how everyone seems to interpret it. The top half (the mfg_id) 2754 * gets stored as big endian because that makes 2755 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2756 * to write (it's easier to extract the ASCII). It doesn't really 2757 * matter, though, as long as the number here is unique. 2758 */ 2759 return (u32)edid->mfg_id[0] << 24 | 2760 (u32)edid->mfg_id[1] << 16 | 2761 (u32)EDID_PRODUCT_ID(edid); 2762 } 2763 2764 /** 2765 * drm_edid_get_panel_id - Get a panel's ID through DDC 2766 * @adapter: I2C adapter to use for DDC 2767 * 2768 * This function reads the first block of the EDID of a panel and (assuming 2769 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2770 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2771 * supposed to be different for each different modem of panel. 2772 * 2773 * This function is intended to be used during early probing on devices where 2774 * more than one panel might be present. Because of its intended use it must 2775 * assume that the EDID of the panel is correct, at least as far as the ID 2776 * is concerned (in other words, we don't process any overrides here). 2777 * 2778 * NOTE: it's expected that this function and drm_do_get_edid() will both 2779 * be read the EDID, but there is no caching between them. Since we're only 2780 * reading the first block, hopefully this extra overhead won't be too big. 2781 * 2782 * Return: A 32-bit ID that should be different for each make/model of panel. 2783 * See the functions drm_edid_encode_panel_id() and 2784 * drm_edid_decode_panel_id() for some details on the structure of this 2785 * ID. 2786 */ 2787 2788 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2789 { 2790 enum edid_block_status status; 2791 void *base_block; 2792 u32 panel_id = 0; 2793 2794 /* 2795 * There are no manufacturer IDs of 0, so if there is a problem reading 2796 * the EDID then we'll just return 0. 2797 */ 2798 2799 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2800 if (!base_block) 2801 return 0; 2802 2803 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2804 2805 edid_block_status_print(status, base_block, 0); 2806 2807 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2808 panel_id = edid_extract_panel_id(base_block); 2809 else 2810 edid_block_dump(KERN_NOTICE, base_block, 0); 2811 2812 kfree(base_block); 2813 2814 return panel_id; 2815 } 2816 EXPORT_SYMBOL(drm_edid_get_panel_id); 2817 2818 /** 2819 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2820 * @connector: connector we're probing 2821 * @adapter: I2C adapter to use for DDC 2822 * 2823 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2824 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2825 * switch DDC to the GPU which is retrieving EDID. 2826 * 2827 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2828 */ 2829 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2830 struct i2c_adapter *adapter) 2831 { 2832 struct drm_device *dev = connector->dev; 2833 struct pci_dev *pdev = to_pci_dev(dev->dev); 2834 struct edid *edid; 2835 2836 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2837 return NULL; 2838 2839 vga_switcheroo_lock_ddc(pdev); 2840 edid = drm_get_edid(connector, adapter); 2841 vga_switcheroo_unlock_ddc(pdev); 2842 2843 return edid; 2844 } 2845 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2846 2847 /** 2848 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2849 * @connector: connector we're probing 2850 * @adapter: I2C adapter to use for DDC 2851 * 2852 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2853 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2854 * temporarily switch DDC to the GPU which is retrieving EDID. 2855 * 2856 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2857 */ 2858 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2859 struct i2c_adapter *adapter) 2860 { 2861 struct drm_device *dev = connector->dev; 2862 struct pci_dev *pdev = to_pci_dev(dev->dev); 2863 const struct drm_edid *drm_edid; 2864 2865 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2866 return NULL; 2867 2868 vga_switcheroo_lock_ddc(pdev); 2869 drm_edid = drm_edid_read_ddc(connector, adapter); 2870 vga_switcheroo_unlock_ddc(pdev); 2871 2872 return drm_edid; 2873 } 2874 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2875 2876 /** 2877 * drm_edid_duplicate - duplicate an EDID and the extensions 2878 * @edid: EDID to duplicate 2879 * 2880 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2881 */ 2882 struct edid *drm_edid_duplicate(const struct edid *edid) 2883 { 2884 if (!edid) 2885 return NULL; 2886 2887 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2888 } 2889 EXPORT_SYMBOL(drm_edid_duplicate); 2890 2891 /*** EDID parsing ***/ 2892 2893 /** 2894 * edid_get_quirks - return quirk flags for a given EDID 2895 * @drm_edid: EDID to process 2896 * 2897 * This tells subsequent routines what fixes they need to apply. 2898 */ 2899 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2900 { 2901 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2902 const struct edid_quirk *quirk; 2903 int i; 2904 2905 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2906 quirk = &edid_quirk_list[i]; 2907 if (quirk->panel_id == panel_id) 2908 return quirk->quirks; 2909 } 2910 2911 return 0; 2912 } 2913 2914 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2915 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2916 2917 /* 2918 * Walk the mode list for connector, clearing the preferred status on existing 2919 * modes and setting it anew for the right mode ala quirks. 2920 */ 2921 static void edid_fixup_preferred(struct drm_connector *connector) 2922 { 2923 const struct drm_display_info *info = &connector->display_info; 2924 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2925 int target_refresh = 0; 2926 int cur_vrefresh, preferred_vrefresh; 2927 2928 if (list_empty(&connector->probed_modes)) 2929 return; 2930 2931 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2932 target_refresh = 60; 2933 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2934 target_refresh = 75; 2935 2936 preferred_mode = list_first_entry(&connector->probed_modes, 2937 struct drm_display_mode, head); 2938 2939 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2940 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2941 2942 if (cur_mode == preferred_mode) 2943 continue; 2944 2945 /* Largest mode is preferred */ 2946 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2947 preferred_mode = cur_mode; 2948 2949 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2950 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2951 /* At a given size, try to get closest to target refresh */ 2952 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2953 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2954 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2955 preferred_mode = cur_mode; 2956 } 2957 } 2958 2959 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2960 } 2961 2962 static bool 2963 mode_is_rb(const struct drm_display_mode *mode) 2964 { 2965 return (mode->htotal - mode->hdisplay == 160) && 2966 (mode->hsync_end - mode->hdisplay == 80) && 2967 (mode->hsync_end - mode->hsync_start == 32) && 2968 (mode->vsync_start - mode->vdisplay == 3); 2969 } 2970 2971 /* 2972 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2973 * @dev: Device to duplicate against 2974 * @hsize: Mode width 2975 * @vsize: Mode height 2976 * @fresh: Mode refresh rate 2977 * @rb: Mode reduced-blanking-ness 2978 * 2979 * Walk the DMT mode list looking for a match for the given parameters. 2980 * 2981 * Return: A newly allocated copy of the mode, or NULL if not found. 2982 */ 2983 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2984 int hsize, int vsize, int fresh, 2985 bool rb) 2986 { 2987 int i; 2988 2989 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2990 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2991 2992 if (hsize != ptr->hdisplay) 2993 continue; 2994 if (vsize != ptr->vdisplay) 2995 continue; 2996 if (fresh != drm_mode_vrefresh(ptr)) 2997 continue; 2998 if (rb != mode_is_rb(ptr)) 2999 continue; 3000 3001 return drm_mode_duplicate(dev, ptr); 3002 } 3003 3004 return NULL; 3005 } 3006 EXPORT_SYMBOL(drm_mode_find_dmt); 3007 3008 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3009 { 3010 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3011 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3012 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3013 3014 return descriptor->pixel_clock == 0 && 3015 descriptor->data.other_data.pad1 == 0 && 3016 descriptor->data.other_data.type == type; 3017 } 3018 3019 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3020 { 3021 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3022 3023 return descriptor->pixel_clock != 0; 3024 } 3025 3026 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3027 3028 static void 3029 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3030 { 3031 int i, n; 3032 u8 d = ext[0x02]; 3033 const u8 *det_base = ext + d; 3034 3035 if (d < 4 || d > 127) 3036 return; 3037 3038 n = (127 - d) / 18; 3039 for (i = 0; i < n; i++) 3040 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3041 } 3042 3043 static void 3044 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3045 { 3046 unsigned int i, n = min((int)ext[0x02], 6); 3047 const u8 *det_base = ext + 5; 3048 3049 if (ext[0x01] != 1) 3050 return; /* unknown version */ 3051 3052 for (i = 0; i < n; i++) 3053 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3054 } 3055 3056 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3057 detailed_cb *cb, void *closure) 3058 { 3059 struct drm_edid_iter edid_iter; 3060 const u8 *ext; 3061 int i; 3062 3063 if (!drm_edid) 3064 return; 3065 3066 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3067 cb(&drm_edid->edid->detailed_timings[i], closure); 3068 3069 drm_edid_iter_begin(drm_edid, &edid_iter); 3070 drm_edid_iter_for_each(ext, &edid_iter) { 3071 switch (*ext) { 3072 case CEA_EXT: 3073 cea_for_each_detailed_block(ext, cb, closure); 3074 break; 3075 case VTB_EXT: 3076 vtb_for_each_detailed_block(ext, cb, closure); 3077 break; 3078 default: 3079 break; 3080 } 3081 } 3082 drm_edid_iter_end(&edid_iter); 3083 } 3084 3085 static void 3086 is_rb(const struct detailed_timing *descriptor, void *data) 3087 { 3088 bool *res = data; 3089 3090 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3091 return; 3092 3093 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3094 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3095 3096 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3097 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3098 *res = true; 3099 } 3100 3101 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3102 static bool 3103 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3104 { 3105 if (drm_edid->edid->revision >= 4) { 3106 bool ret = false; 3107 3108 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3109 return ret; 3110 } 3111 3112 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3113 } 3114 3115 static void 3116 find_gtf2(const struct detailed_timing *descriptor, void *data) 3117 { 3118 const struct detailed_timing **res = data; 3119 3120 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3121 return; 3122 3123 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3124 3125 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3126 *res = descriptor; 3127 } 3128 3129 /* Secondary GTF curve kicks in above some break frequency */ 3130 static int 3131 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3132 { 3133 const struct detailed_timing *descriptor = NULL; 3134 3135 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3136 3137 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3138 3139 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3140 } 3141 3142 static int 3143 drm_gtf2_2c(const struct drm_edid *drm_edid) 3144 { 3145 const struct detailed_timing *descriptor = NULL; 3146 3147 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3148 3149 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3150 3151 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3152 } 3153 3154 static int 3155 drm_gtf2_m(const struct drm_edid *drm_edid) 3156 { 3157 const struct detailed_timing *descriptor = NULL; 3158 3159 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3160 3161 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3162 3163 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3164 } 3165 3166 static int 3167 drm_gtf2_k(const struct drm_edid *drm_edid) 3168 { 3169 const struct detailed_timing *descriptor = NULL; 3170 3171 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3172 3173 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3174 3175 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3176 } 3177 3178 static int 3179 drm_gtf2_2j(const struct drm_edid *drm_edid) 3180 { 3181 const struct detailed_timing *descriptor = NULL; 3182 3183 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3184 3185 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3186 3187 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3188 } 3189 3190 static void 3191 get_timing_level(const struct detailed_timing *descriptor, void *data) 3192 { 3193 int *res = data; 3194 3195 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3196 return; 3197 3198 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3199 3200 switch (descriptor->data.other_data.data.range.flags) { 3201 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3202 *res = LEVEL_GTF; 3203 break; 3204 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3205 *res = LEVEL_GTF2; 3206 break; 3207 case DRM_EDID_CVT_SUPPORT_FLAG: 3208 *res = LEVEL_CVT; 3209 break; 3210 default: 3211 break; 3212 } 3213 } 3214 3215 /* Get standard timing level (CVT/GTF/DMT). */ 3216 static int standard_timing_level(const struct drm_edid *drm_edid) 3217 { 3218 const struct edid *edid = drm_edid->edid; 3219 3220 if (edid->revision >= 4) { 3221 /* 3222 * If the range descriptor doesn't 3223 * indicate otherwise default to CVT 3224 */ 3225 int ret = LEVEL_CVT; 3226 3227 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3228 3229 return ret; 3230 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3231 return LEVEL_GTF2; 3232 } else if (edid->revision >= 2) { 3233 return LEVEL_GTF; 3234 } else { 3235 return LEVEL_DMT; 3236 } 3237 } 3238 3239 /* 3240 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3241 * monitors fill with ascii space (0x20) instead. 3242 */ 3243 static int 3244 bad_std_timing(u8 a, u8 b) 3245 { 3246 return (a == 0x00 && b == 0x00) || 3247 (a == 0x01 && b == 0x01) || 3248 (a == 0x20 && b == 0x20); 3249 } 3250 3251 static int drm_mode_hsync(const struct drm_display_mode *mode) 3252 { 3253 if (mode->htotal <= 0) 3254 return 0; 3255 3256 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3257 } 3258 3259 static struct drm_display_mode * 3260 drm_gtf2_mode(struct drm_device *dev, 3261 const struct drm_edid *drm_edid, 3262 int hsize, int vsize, int vrefresh_rate) 3263 { 3264 struct drm_display_mode *mode; 3265 3266 /* 3267 * This is potentially wrong if there's ever a monitor with 3268 * more than one ranges section, each claiming a different 3269 * secondary GTF curve. Please don't do that. 3270 */ 3271 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3272 if (!mode) 3273 return NULL; 3274 3275 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3276 drm_mode_destroy(dev, mode); 3277 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3278 vrefresh_rate, 0, 0, 3279 drm_gtf2_m(drm_edid), 3280 drm_gtf2_2c(drm_edid), 3281 drm_gtf2_k(drm_edid), 3282 drm_gtf2_2j(drm_edid)); 3283 } 3284 3285 return mode; 3286 } 3287 3288 /* 3289 * Take the standard timing params (in this case width, aspect, and refresh) 3290 * and convert them into a real mode using CVT/GTF/DMT. 3291 */ 3292 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3293 const struct drm_edid *drm_edid, 3294 const struct std_timing *t) 3295 { 3296 struct drm_device *dev = connector->dev; 3297 struct drm_display_mode *m, *mode = NULL; 3298 int hsize, vsize; 3299 int vrefresh_rate; 3300 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3301 >> EDID_TIMING_ASPECT_SHIFT; 3302 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3303 >> EDID_TIMING_VFREQ_SHIFT; 3304 int timing_level = standard_timing_level(drm_edid); 3305 3306 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3307 return NULL; 3308 3309 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3310 hsize = t->hsize * 8 + 248; 3311 /* vrefresh_rate = vfreq + 60 */ 3312 vrefresh_rate = vfreq + 60; 3313 /* the vdisplay is calculated based on the aspect ratio */ 3314 if (aspect_ratio == 0) { 3315 if (drm_edid->edid->revision < 3) 3316 vsize = hsize; 3317 else 3318 vsize = (hsize * 10) / 16; 3319 } else if (aspect_ratio == 1) 3320 vsize = (hsize * 3) / 4; 3321 else if (aspect_ratio == 2) 3322 vsize = (hsize * 4) / 5; 3323 else 3324 vsize = (hsize * 9) / 16; 3325 3326 /* HDTV hack, part 1 */ 3327 if (vrefresh_rate == 60 && 3328 ((hsize == 1360 && vsize == 765) || 3329 (hsize == 1368 && vsize == 769))) { 3330 hsize = 1366; 3331 vsize = 768; 3332 } 3333 3334 /* 3335 * If this connector already has a mode for this size and refresh 3336 * rate (because it came from detailed or CVT info), use that 3337 * instead. This way we don't have to guess at interlace or 3338 * reduced blanking. 3339 */ 3340 list_for_each_entry(m, &connector->probed_modes, head) 3341 if (m->hdisplay == hsize && m->vdisplay == vsize && 3342 drm_mode_vrefresh(m) == vrefresh_rate) 3343 return NULL; 3344 3345 /* HDTV hack, part 2 */ 3346 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3347 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3348 false); 3349 if (!mode) 3350 return NULL; 3351 mode->hdisplay = 1366; 3352 mode->hsync_start = mode->hsync_start - 1; 3353 mode->hsync_end = mode->hsync_end - 1; 3354 return mode; 3355 } 3356 3357 /* check whether it can be found in default mode table */ 3358 if (drm_monitor_supports_rb(drm_edid)) { 3359 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3360 true); 3361 if (mode) 3362 return mode; 3363 } 3364 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3365 if (mode) 3366 return mode; 3367 3368 /* okay, generate it */ 3369 switch (timing_level) { 3370 case LEVEL_DMT: 3371 break; 3372 case LEVEL_GTF: 3373 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3374 break; 3375 case LEVEL_GTF2: 3376 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3377 break; 3378 case LEVEL_CVT: 3379 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3380 false); 3381 break; 3382 } 3383 return mode; 3384 } 3385 3386 /* 3387 * EDID is delightfully ambiguous about how interlaced modes are to be 3388 * encoded. Our internal representation is of frame height, but some 3389 * HDTV detailed timings are encoded as field height. 3390 * 3391 * The format list here is from CEA, in frame size. Technically we 3392 * should be checking refresh rate too. Whatever. 3393 */ 3394 static void 3395 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3396 const struct detailed_pixel_timing *pt) 3397 { 3398 int i; 3399 static const struct { 3400 int w, h; 3401 } cea_interlaced[] = { 3402 { 1920, 1080 }, 3403 { 720, 480 }, 3404 { 1440, 480 }, 3405 { 2880, 480 }, 3406 { 720, 576 }, 3407 { 1440, 576 }, 3408 { 2880, 576 }, 3409 }; 3410 3411 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3412 return; 3413 3414 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3415 if ((mode->hdisplay == cea_interlaced[i].w) && 3416 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3417 mode->vdisplay *= 2; 3418 mode->vsync_start *= 2; 3419 mode->vsync_end *= 2; 3420 mode->vtotal *= 2; 3421 mode->vtotal |= 1; 3422 } 3423 } 3424 3425 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3426 } 3427 3428 /* 3429 * Create a new mode from an EDID detailed timing section. An EDID detailed 3430 * timing block contains enough info for us to create and return a new struct 3431 * drm_display_mode. 3432 */ 3433 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3434 const struct drm_edid *drm_edid, 3435 const struct detailed_timing *timing) 3436 { 3437 const struct drm_display_info *info = &connector->display_info; 3438 struct drm_device *dev = connector->dev; 3439 struct drm_display_mode *mode; 3440 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3441 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3442 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3443 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3444 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3445 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3446 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3447 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3448 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3449 3450 /* ignore tiny modes */ 3451 if (hactive < 64 || vactive < 64) 3452 return NULL; 3453 3454 if (pt->misc & DRM_EDID_PT_STEREO) { 3455 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3456 connector->base.id, connector->name); 3457 return NULL; 3458 } 3459 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3460 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3461 connector->base.id, connector->name); 3462 } 3463 3464 /* it is incorrect if hsync/vsync width is zero */ 3465 if (!hsync_pulse_width || !vsync_pulse_width) { 3466 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3467 connector->base.id, connector->name); 3468 return NULL; 3469 } 3470 3471 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3472 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3473 if (!mode) 3474 return NULL; 3475 3476 goto set_size; 3477 } 3478 3479 mode = drm_mode_create(dev); 3480 if (!mode) 3481 return NULL; 3482 3483 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3484 mode->clock = 1088 * 10; 3485 else 3486 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3487 3488 mode->hdisplay = hactive; 3489 mode->hsync_start = mode->hdisplay + hsync_offset; 3490 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3491 mode->htotal = mode->hdisplay + hblank; 3492 3493 mode->vdisplay = vactive; 3494 mode->vsync_start = mode->vdisplay + vsync_offset; 3495 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3496 mode->vtotal = mode->vdisplay + vblank; 3497 3498 /* Some EDIDs have bogus h/vtotal values */ 3499 if (mode->hsync_end > mode->htotal) 3500 mode->htotal = mode->hsync_end + 1; 3501 if (mode->vsync_end > mode->vtotal) 3502 mode->vtotal = mode->vsync_end + 1; 3503 3504 drm_mode_do_interlace_quirk(mode, pt); 3505 3506 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3507 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3508 } else { 3509 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3510 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3511 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3512 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3513 } 3514 3515 set_size: 3516 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3517 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3518 3519 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3520 mode->width_mm *= 10; 3521 mode->height_mm *= 10; 3522 } 3523 3524 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3525 mode->width_mm = drm_edid->edid->width_cm * 10; 3526 mode->height_mm = drm_edid->edid->height_cm * 10; 3527 } 3528 3529 mode->type = DRM_MODE_TYPE_DRIVER; 3530 drm_mode_set_name(mode); 3531 3532 return mode; 3533 } 3534 3535 static bool 3536 mode_in_hsync_range(const struct drm_display_mode *mode, 3537 const struct edid *edid, const u8 *t) 3538 { 3539 int hsync, hmin, hmax; 3540 3541 hmin = t[7]; 3542 if (edid->revision >= 4) 3543 hmin += ((t[4] & 0x04) ? 255 : 0); 3544 hmax = t[8]; 3545 if (edid->revision >= 4) 3546 hmax += ((t[4] & 0x08) ? 255 : 0); 3547 hsync = drm_mode_hsync(mode); 3548 3549 return (hsync <= hmax && hsync >= hmin); 3550 } 3551 3552 static bool 3553 mode_in_vsync_range(const struct drm_display_mode *mode, 3554 const struct edid *edid, const u8 *t) 3555 { 3556 int vsync, vmin, vmax; 3557 3558 vmin = t[5]; 3559 if (edid->revision >= 4) 3560 vmin += ((t[4] & 0x01) ? 255 : 0); 3561 vmax = t[6]; 3562 if (edid->revision >= 4) 3563 vmax += ((t[4] & 0x02) ? 255 : 0); 3564 vsync = drm_mode_vrefresh(mode); 3565 3566 return (vsync <= vmax && vsync >= vmin); 3567 } 3568 3569 static u32 3570 range_pixel_clock(const struct edid *edid, const u8 *t) 3571 { 3572 /* unspecified */ 3573 if (t[9] == 0 || t[9] == 255) 3574 return 0; 3575 3576 /* 1.4 with CVT support gives us real precision, yay */ 3577 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3578 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3579 3580 /* 1.3 is pathetic, so fuzz up a bit */ 3581 return t[9] * 10000 + 5001; 3582 } 3583 3584 static bool mode_in_range(const struct drm_display_mode *mode, 3585 const struct drm_edid *drm_edid, 3586 const struct detailed_timing *timing) 3587 { 3588 const struct edid *edid = drm_edid->edid; 3589 u32 max_clock; 3590 const u8 *t = (const u8 *)timing; 3591 3592 if (!mode_in_hsync_range(mode, edid, t)) 3593 return false; 3594 3595 if (!mode_in_vsync_range(mode, edid, t)) 3596 return false; 3597 3598 if ((max_clock = range_pixel_clock(edid, t))) 3599 if (mode->clock > max_clock) 3600 return false; 3601 3602 /* 1.4 max horizontal check */ 3603 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3604 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3605 return false; 3606 3607 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3608 return false; 3609 3610 return true; 3611 } 3612 3613 static bool valid_inferred_mode(const struct drm_connector *connector, 3614 const struct drm_display_mode *mode) 3615 { 3616 const struct drm_display_mode *m; 3617 bool ok = false; 3618 3619 list_for_each_entry(m, &connector->probed_modes, head) { 3620 if (mode->hdisplay == m->hdisplay && 3621 mode->vdisplay == m->vdisplay && 3622 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3623 return false; /* duplicated */ 3624 if (mode->hdisplay <= m->hdisplay && 3625 mode->vdisplay <= m->vdisplay) 3626 ok = true; 3627 } 3628 return ok; 3629 } 3630 3631 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3632 const struct drm_edid *drm_edid, 3633 const struct detailed_timing *timing) 3634 { 3635 int i, modes = 0; 3636 struct drm_display_mode *newmode; 3637 struct drm_device *dev = connector->dev; 3638 3639 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3640 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3641 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3642 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3643 if (newmode) { 3644 drm_mode_probed_add(connector, newmode); 3645 modes++; 3646 } 3647 } 3648 } 3649 3650 return modes; 3651 } 3652 3653 /* fix up 1366x768 mode from 1368x768; 3654 * GFT/CVT can't express 1366 width which isn't dividable by 8 3655 */ 3656 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3657 { 3658 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3659 mode->hdisplay = 1366; 3660 mode->hsync_start--; 3661 mode->hsync_end--; 3662 drm_mode_set_name(mode); 3663 } 3664 } 3665 3666 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3667 const struct drm_edid *drm_edid, 3668 const struct detailed_timing *timing) 3669 { 3670 int i, modes = 0; 3671 struct drm_display_mode *newmode; 3672 struct drm_device *dev = connector->dev; 3673 3674 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3675 const struct minimode *m = &extra_modes[i]; 3676 3677 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3678 if (!newmode) 3679 return modes; 3680 3681 drm_mode_fixup_1366x768(newmode); 3682 if (!mode_in_range(newmode, drm_edid, timing) || 3683 !valid_inferred_mode(connector, newmode)) { 3684 drm_mode_destroy(dev, newmode); 3685 continue; 3686 } 3687 3688 drm_mode_probed_add(connector, newmode); 3689 modes++; 3690 } 3691 3692 return modes; 3693 } 3694 3695 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3696 const struct drm_edid *drm_edid, 3697 const struct detailed_timing *timing) 3698 { 3699 int i, modes = 0; 3700 struct drm_display_mode *newmode; 3701 struct drm_device *dev = connector->dev; 3702 3703 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3704 const struct minimode *m = &extra_modes[i]; 3705 3706 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3707 if (!newmode) 3708 return modes; 3709 3710 drm_mode_fixup_1366x768(newmode); 3711 if (!mode_in_range(newmode, drm_edid, timing) || 3712 !valid_inferred_mode(connector, newmode)) { 3713 drm_mode_destroy(dev, newmode); 3714 continue; 3715 } 3716 3717 drm_mode_probed_add(connector, newmode); 3718 modes++; 3719 } 3720 3721 return modes; 3722 } 3723 3724 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3725 const struct drm_edid *drm_edid, 3726 const struct detailed_timing *timing) 3727 { 3728 int i, modes = 0; 3729 struct drm_display_mode *newmode; 3730 struct drm_device *dev = connector->dev; 3731 bool rb = drm_monitor_supports_rb(drm_edid); 3732 3733 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3734 const struct minimode *m = &extra_modes[i]; 3735 3736 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3737 if (!newmode) 3738 return modes; 3739 3740 drm_mode_fixup_1366x768(newmode); 3741 if (!mode_in_range(newmode, drm_edid, timing) || 3742 !valid_inferred_mode(connector, newmode)) { 3743 drm_mode_destroy(dev, newmode); 3744 continue; 3745 } 3746 3747 drm_mode_probed_add(connector, newmode); 3748 modes++; 3749 } 3750 3751 return modes; 3752 } 3753 3754 static void 3755 do_inferred_modes(const struct detailed_timing *timing, void *c) 3756 { 3757 struct detailed_mode_closure *closure = c; 3758 const struct detailed_non_pixel *data = &timing->data.other_data; 3759 const struct detailed_data_monitor_range *range = &data->data.range; 3760 3761 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3762 return; 3763 3764 closure->modes += drm_dmt_modes_for_range(closure->connector, 3765 closure->drm_edid, 3766 timing); 3767 3768 if (closure->drm_edid->edid->revision < 2) 3769 return; /* GTF not defined yet */ 3770 3771 switch (range->flags) { 3772 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3773 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3774 closure->drm_edid, 3775 timing); 3776 break; 3777 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3778 closure->modes += drm_gtf_modes_for_range(closure->connector, 3779 closure->drm_edid, 3780 timing); 3781 break; 3782 case DRM_EDID_CVT_SUPPORT_FLAG: 3783 if (closure->drm_edid->edid->revision < 4) 3784 break; 3785 3786 closure->modes += drm_cvt_modes_for_range(closure->connector, 3787 closure->drm_edid, 3788 timing); 3789 break; 3790 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3791 default: 3792 break; 3793 } 3794 } 3795 3796 static int add_inferred_modes(struct drm_connector *connector, 3797 const struct drm_edid *drm_edid) 3798 { 3799 struct detailed_mode_closure closure = { 3800 .connector = connector, 3801 .drm_edid = drm_edid, 3802 }; 3803 3804 if (drm_edid->edid->revision >= 1) 3805 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3806 3807 return closure.modes; 3808 } 3809 3810 static int 3811 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3812 { 3813 int i, j, m, modes = 0; 3814 struct drm_display_mode *mode; 3815 const u8 *est = ((const u8 *)timing) + 6; 3816 3817 for (i = 0; i < 6; i++) { 3818 for (j = 7; j >= 0; j--) { 3819 m = (i * 8) + (7 - j); 3820 if (m >= ARRAY_SIZE(est3_modes)) 3821 break; 3822 if (est[i] & (1 << j)) { 3823 mode = drm_mode_find_dmt(connector->dev, 3824 est3_modes[m].w, 3825 est3_modes[m].h, 3826 est3_modes[m].r, 3827 est3_modes[m].rb); 3828 if (mode) { 3829 drm_mode_probed_add(connector, mode); 3830 modes++; 3831 } 3832 } 3833 } 3834 } 3835 3836 return modes; 3837 } 3838 3839 static void 3840 do_established_modes(const struct detailed_timing *timing, void *c) 3841 { 3842 struct detailed_mode_closure *closure = c; 3843 3844 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3845 return; 3846 3847 closure->modes += drm_est3_modes(closure->connector, timing); 3848 } 3849 3850 /* 3851 * Get established modes from EDID and add them. Each EDID block contains a 3852 * bitmap of the supported "established modes" list (defined above). Tease them 3853 * out and add them to the global modes list. 3854 */ 3855 static int add_established_modes(struct drm_connector *connector, 3856 const struct drm_edid *drm_edid) 3857 { 3858 struct drm_device *dev = connector->dev; 3859 const struct edid *edid = drm_edid->edid; 3860 unsigned long est_bits = edid->established_timings.t1 | 3861 (edid->established_timings.t2 << 8) | 3862 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3863 int i, modes = 0; 3864 struct detailed_mode_closure closure = { 3865 .connector = connector, 3866 .drm_edid = drm_edid, 3867 }; 3868 3869 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3870 if (est_bits & (1<<i)) { 3871 struct drm_display_mode *newmode; 3872 3873 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3874 if (newmode) { 3875 drm_mode_probed_add(connector, newmode); 3876 modes++; 3877 } 3878 } 3879 } 3880 3881 if (edid->revision >= 1) 3882 drm_for_each_detailed_block(drm_edid, do_established_modes, 3883 &closure); 3884 3885 return modes + closure.modes; 3886 } 3887 3888 static void 3889 do_standard_modes(const struct detailed_timing *timing, void *c) 3890 { 3891 struct detailed_mode_closure *closure = c; 3892 const struct detailed_non_pixel *data = &timing->data.other_data; 3893 struct drm_connector *connector = closure->connector; 3894 int i; 3895 3896 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3897 return; 3898 3899 for (i = 0; i < 6; i++) { 3900 const struct std_timing *std = &data->data.timings[i]; 3901 struct drm_display_mode *newmode; 3902 3903 newmode = drm_mode_std(connector, closure->drm_edid, std); 3904 if (newmode) { 3905 drm_mode_probed_add(connector, newmode); 3906 closure->modes++; 3907 } 3908 } 3909 } 3910 3911 /* 3912 * Get standard modes from EDID and add them. Standard modes can be calculated 3913 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3914 * add them to the list. 3915 */ 3916 static int add_standard_modes(struct drm_connector *connector, 3917 const struct drm_edid *drm_edid) 3918 { 3919 int i, modes = 0; 3920 struct detailed_mode_closure closure = { 3921 .connector = connector, 3922 .drm_edid = drm_edid, 3923 }; 3924 3925 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3926 struct drm_display_mode *newmode; 3927 3928 newmode = drm_mode_std(connector, drm_edid, 3929 &drm_edid->edid->standard_timings[i]); 3930 if (newmode) { 3931 drm_mode_probed_add(connector, newmode); 3932 modes++; 3933 } 3934 } 3935 3936 if (drm_edid->edid->revision >= 1) 3937 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3938 &closure); 3939 3940 /* XXX should also look for standard codes in VTB blocks */ 3941 3942 return modes + closure.modes; 3943 } 3944 3945 static int drm_cvt_modes(struct drm_connector *connector, 3946 const struct detailed_timing *timing) 3947 { 3948 int i, j, modes = 0; 3949 struct drm_display_mode *newmode; 3950 struct drm_device *dev = connector->dev; 3951 const struct cvt_timing *cvt; 3952 const int rates[] = { 60, 85, 75, 60, 50 }; 3953 const u8 empty[3] = { 0, 0, 0 }; 3954 3955 for (i = 0; i < 4; i++) { 3956 int width, height; 3957 3958 cvt = &(timing->data.other_data.data.cvt[i]); 3959 3960 if (!memcmp(cvt->code, empty, 3)) 3961 continue; 3962 3963 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3964 switch (cvt->code[1] & 0x0c) { 3965 /* default - because compiler doesn't see that we've enumerated all cases */ 3966 default: 3967 case 0x00: 3968 width = height * 4 / 3; 3969 break; 3970 case 0x04: 3971 width = height * 16 / 9; 3972 break; 3973 case 0x08: 3974 width = height * 16 / 10; 3975 break; 3976 case 0x0c: 3977 width = height * 15 / 9; 3978 break; 3979 } 3980 3981 for (j = 1; j < 5; j++) { 3982 if (cvt->code[2] & (1 << j)) { 3983 newmode = drm_cvt_mode(dev, width, height, 3984 rates[j], j == 0, 3985 false, false); 3986 if (newmode) { 3987 drm_mode_probed_add(connector, newmode); 3988 modes++; 3989 } 3990 } 3991 } 3992 } 3993 3994 return modes; 3995 } 3996 3997 static void 3998 do_cvt_mode(const struct detailed_timing *timing, void *c) 3999 { 4000 struct detailed_mode_closure *closure = c; 4001 4002 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4003 return; 4004 4005 closure->modes += drm_cvt_modes(closure->connector, timing); 4006 } 4007 4008 static int 4009 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4010 { 4011 struct detailed_mode_closure closure = { 4012 .connector = connector, 4013 .drm_edid = drm_edid, 4014 }; 4015 4016 if (drm_edid->edid->revision >= 3) 4017 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4018 4019 /* XXX should also look for CVT codes in VTB blocks */ 4020 4021 return closure.modes; 4022 } 4023 4024 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4025 struct drm_display_mode *mode); 4026 4027 static void 4028 do_detailed_mode(const struct detailed_timing *timing, void *c) 4029 { 4030 struct detailed_mode_closure *closure = c; 4031 struct drm_display_mode *newmode; 4032 4033 if (!is_detailed_timing_descriptor(timing)) 4034 return; 4035 4036 newmode = drm_mode_detailed(closure->connector, 4037 closure->drm_edid, timing); 4038 if (!newmode) 4039 return; 4040 4041 if (closure->preferred) 4042 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4043 4044 /* 4045 * Detailed modes are limited to 10kHz pixel clock resolution, 4046 * so fix up anything that looks like CEA/HDMI mode, but the clock 4047 * is just slightly off. 4048 */ 4049 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4050 4051 drm_mode_probed_add(closure->connector, newmode); 4052 closure->modes++; 4053 closure->preferred = false; 4054 } 4055 4056 /* 4057 * add_detailed_modes - Add modes from detailed timings 4058 * @connector: attached connector 4059 * @drm_edid: EDID block to scan 4060 */ 4061 static int add_detailed_modes(struct drm_connector *connector, 4062 const struct drm_edid *drm_edid) 4063 { 4064 struct detailed_mode_closure closure = { 4065 .connector = connector, 4066 .drm_edid = drm_edid, 4067 }; 4068 4069 if (drm_edid->edid->revision >= 4) 4070 closure.preferred = true; /* first detailed timing is always preferred */ 4071 else 4072 closure.preferred = 4073 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4074 4075 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4076 4077 return closure.modes; 4078 } 4079 4080 /* CTA-861-H Table 60 - CTA Tag Codes */ 4081 #define CTA_DB_AUDIO 1 4082 #define CTA_DB_VIDEO 2 4083 #define CTA_DB_VENDOR 3 4084 #define CTA_DB_SPEAKER 4 4085 #define CTA_DB_EXTENDED_TAG 7 4086 4087 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4088 #define CTA_EXT_DB_VIDEO_CAP 0 4089 #define CTA_EXT_DB_VENDOR 1 4090 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4091 #define CTA_EXT_DB_420_VIDEO_DATA 14 4092 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4093 #define CTA_EXT_DB_HF_EEODB 0x78 4094 #define CTA_EXT_DB_HF_SCDB 0x79 4095 4096 #define EDID_BASIC_AUDIO (1 << 6) 4097 #define EDID_CEA_YCRCB444 (1 << 5) 4098 #define EDID_CEA_YCRCB422 (1 << 4) 4099 #define EDID_CEA_VCDB_QS (1 << 6) 4100 4101 /* 4102 * Search EDID for CEA extension block. 4103 * 4104 * FIXME: Prefer not returning pointers to raw EDID data. 4105 */ 4106 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4107 int ext_id, int *ext_index) 4108 { 4109 const u8 *edid_ext = NULL; 4110 int i; 4111 4112 /* No EDID or EDID extensions */ 4113 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4114 return NULL; 4115 4116 /* Find CEA extension */ 4117 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4118 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4119 if (edid_block_tag(edid_ext) == ext_id) 4120 break; 4121 } 4122 4123 if (i >= drm_edid_extension_block_count(drm_edid)) 4124 return NULL; 4125 4126 *ext_index = i + 1; 4127 4128 return edid_ext; 4129 } 4130 4131 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4132 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4133 { 4134 const struct displayid_block *block; 4135 struct displayid_iter iter; 4136 int ext_index = 0; 4137 bool found = false; 4138 4139 /* Look for a top level CEA extension block */ 4140 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4141 return true; 4142 4143 /* CEA blocks can also be found embedded in a DisplayID block */ 4144 displayid_iter_edid_begin(drm_edid, &iter); 4145 displayid_iter_for_each(block, &iter) { 4146 if (block->tag == DATA_BLOCK_CTA) { 4147 found = true; 4148 break; 4149 } 4150 } 4151 displayid_iter_end(&iter); 4152 4153 return found; 4154 } 4155 4156 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4157 { 4158 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4159 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4160 4161 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4162 return &edid_cea_modes_1[vic - 1]; 4163 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4164 return &edid_cea_modes_193[vic - 193]; 4165 return NULL; 4166 } 4167 4168 static u8 cea_num_vics(void) 4169 { 4170 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4171 } 4172 4173 static u8 cea_next_vic(u8 vic) 4174 { 4175 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4176 vic = 193; 4177 return vic; 4178 } 4179 4180 /* 4181 * Calculate the alternate clock for the CEA mode 4182 * (60Hz vs. 59.94Hz etc.) 4183 */ 4184 static unsigned int 4185 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4186 { 4187 unsigned int clock = cea_mode->clock; 4188 4189 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4190 return clock; 4191 4192 /* 4193 * edid_cea_modes contains the 59.94Hz 4194 * variant for 240 and 480 line modes, 4195 * and the 60Hz variant otherwise. 4196 */ 4197 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4198 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4199 else 4200 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4201 4202 return clock; 4203 } 4204 4205 static bool 4206 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4207 { 4208 /* 4209 * For certain VICs the spec allows the vertical 4210 * front porch to vary by one or two lines. 4211 * 4212 * cea_modes[] stores the variant with the shortest 4213 * vertical front porch. We can adjust the mode to 4214 * get the other variants by simply increasing the 4215 * vertical front porch length. 4216 */ 4217 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4218 cea_mode_for_vic(9)->vtotal != 262 || 4219 cea_mode_for_vic(12)->vtotal != 262 || 4220 cea_mode_for_vic(13)->vtotal != 262 || 4221 cea_mode_for_vic(23)->vtotal != 312 || 4222 cea_mode_for_vic(24)->vtotal != 312 || 4223 cea_mode_for_vic(27)->vtotal != 312 || 4224 cea_mode_for_vic(28)->vtotal != 312); 4225 4226 if (((vic == 8 || vic == 9 || 4227 vic == 12 || vic == 13) && mode->vtotal < 263) || 4228 ((vic == 23 || vic == 24 || 4229 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4230 mode->vsync_start++; 4231 mode->vsync_end++; 4232 mode->vtotal++; 4233 4234 return true; 4235 } 4236 4237 return false; 4238 } 4239 4240 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4241 unsigned int clock_tolerance) 4242 { 4243 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4244 u8 vic; 4245 4246 if (!to_match->clock) 4247 return 0; 4248 4249 if (to_match->picture_aspect_ratio) 4250 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4251 4252 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4253 struct drm_display_mode cea_mode; 4254 unsigned int clock1, clock2; 4255 4256 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4257 4258 /* Check both 60Hz and 59.94Hz */ 4259 clock1 = cea_mode.clock; 4260 clock2 = cea_mode_alternate_clock(&cea_mode); 4261 4262 if (abs(to_match->clock - clock1) > clock_tolerance && 4263 abs(to_match->clock - clock2) > clock_tolerance) 4264 continue; 4265 4266 do { 4267 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4268 return vic; 4269 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4270 } 4271 4272 return 0; 4273 } 4274 4275 /** 4276 * drm_match_cea_mode - look for a CEA mode matching given mode 4277 * @to_match: display mode 4278 * 4279 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4280 * mode. 4281 */ 4282 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4283 { 4284 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4285 u8 vic; 4286 4287 if (!to_match->clock) 4288 return 0; 4289 4290 if (to_match->picture_aspect_ratio) 4291 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4292 4293 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4294 struct drm_display_mode cea_mode; 4295 unsigned int clock1, clock2; 4296 4297 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4298 4299 /* Check both 60Hz and 59.94Hz */ 4300 clock1 = cea_mode.clock; 4301 clock2 = cea_mode_alternate_clock(&cea_mode); 4302 4303 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4304 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4305 continue; 4306 4307 do { 4308 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4309 return vic; 4310 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4311 } 4312 4313 return 0; 4314 } 4315 EXPORT_SYMBOL(drm_match_cea_mode); 4316 4317 static bool drm_valid_cea_vic(u8 vic) 4318 { 4319 return cea_mode_for_vic(vic) != NULL; 4320 } 4321 4322 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4323 { 4324 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4325 4326 if (mode) 4327 return mode->picture_aspect_ratio; 4328 4329 return HDMI_PICTURE_ASPECT_NONE; 4330 } 4331 4332 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4333 { 4334 return edid_4k_modes[video_code].picture_aspect_ratio; 4335 } 4336 4337 /* 4338 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4339 * specific block). 4340 */ 4341 static unsigned int 4342 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4343 { 4344 return cea_mode_alternate_clock(hdmi_mode); 4345 } 4346 4347 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4348 unsigned int clock_tolerance) 4349 { 4350 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4351 u8 vic; 4352 4353 if (!to_match->clock) 4354 return 0; 4355 4356 if (to_match->picture_aspect_ratio) 4357 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4358 4359 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4360 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4361 unsigned int clock1, clock2; 4362 4363 /* Make sure to also match alternate clocks */ 4364 clock1 = hdmi_mode->clock; 4365 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4366 4367 if (abs(to_match->clock - clock1) > clock_tolerance && 4368 abs(to_match->clock - clock2) > clock_tolerance) 4369 continue; 4370 4371 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4372 return vic; 4373 } 4374 4375 return 0; 4376 } 4377 4378 /* 4379 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4380 * @to_match: display mode 4381 * 4382 * An HDMI mode is one defined in the HDMI vendor specific block. 4383 * 4384 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4385 */ 4386 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4387 { 4388 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4389 u8 vic; 4390 4391 if (!to_match->clock) 4392 return 0; 4393 4394 if (to_match->picture_aspect_ratio) 4395 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4396 4397 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4398 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4399 unsigned int clock1, clock2; 4400 4401 /* Make sure to also match alternate clocks */ 4402 clock1 = hdmi_mode->clock; 4403 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4404 4405 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4406 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4407 drm_mode_match(to_match, hdmi_mode, match_flags)) 4408 return vic; 4409 } 4410 return 0; 4411 } 4412 4413 static bool drm_valid_hdmi_vic(u8 vic) 4414 { 4415 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4416 } 4417 4418 static int add_alternate_cea_modes(struct drm_connector *connector, 4419 const struct drm_edid *drm_edid) 4420 { 4421 struct drm_device *dev = connector->dev; 4422 struct drm_display_mode *mode, *tmp; 4423 LIST_HEAD(list); 4424 int modes = 0; 4425 4426 /* Don't add CTA modes if the CTA extension block is missing */ 4427 if (!drm_edid_has_cta_extension(drm_edid)) 4428 return 0; 4429 4430 /* 4431 * Go through all probed modes and create a new mode 4432 * with the alternate clock for certain CEA modes. 4433 */ 4434 list_for_each_entry(mode, &connector->probed_modes, head) { 4435 const struct drm_display_mode *cea_mode = NULL; 4436 struct drm_display_mode *newmode; 4437 u8 vic = drm_match_cea_mode(mode); 4438 unsigned int clock1, clock2; 4439 4440 if (drm_valid_cea_vic(vic)) { 4441 cea_mode = cea_mode_for_vic(vic); 4442 clock2 = cea_mode_alternate_clock(cea_mode); 4443 } else { 4444 vic = drm_match_hdmi_mode(mode); 4445 if (drm_valid_hdmi_vic(vic)) { 4446 cea_mode = &edid_4k_modes[vic]; 4447 clock2 = hdmi_mode_alternate_clock(cea_mode); 4448 } 4449 } 4450 4451 if (!cea_mode) 4452 continue; 4453 4454 clock1 = cea_mode->clock; 4455 4456 if (clock1 == clock2) 4457 continue; 4458 4459 if (mode->clock != clock1 && mode->clock != clock2) 4460 continue; 4461 4462 newmode = drm_mode_duplicate(dev, cea_mode); 4463 if (!newmode) 4464 continue; 4465 4466 /* Carry over the stereo flags */ 4467 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4468 4469 /* 4470 * The current mode could be either variant. Make 4471 * sure to pick the "other" clock for the new mode. 4472 */ 4473 if (mode->clock != clock1) 4474 newmode->clock = clock1; 4475 else 4476 newmode->clock = clock2; 4477 4478 list_add_tail(&newmode->head, &list); 4479 } 4480 4481 list_for_each_entry_safe(mode, tmp, &list, head) { 4482 list_del(&mode->head); 4483 drm_mode_probed_add(connector, mode); 4484 modes++; 4485 } 4486 4487 return modes; 4488 } 4489 4490 static u8 svd_to_vic(u8 svd) 4491 { 4492 /* 0-6 bit vic, 7th bit native mode indicator */ 4493 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4494 return svd & 127; 4495 4496 return svd; 4497 } 4498 4499 /* 4500 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4501 * the EDID, or NULL on errors. 4502 */ 4503 static struct drm_display_mode * 4504 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4505 { 4506 const struct drm_display_info *info = &connector->display_info; 4507 struct drm_device *dev = connector->dev; 4508 4509 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4510 return NULL; 4511 4512 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4513 } 4514 4515 /* 4516 * do_y420vdb_modes - Parse YCBCR 420 only modes 4517 * @connector: connector corresponding to the HDMI sink 4518 * @svds: start of the data block of CEA YCBCR 420 VDB 4519 * @len: length of the CEA YCBCR 420 VDB 4520 * 4521 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4522 * which contains modes which can be supported in YCBCR 420 4523 * output format only. 4524 */ 4525 static int do_y420vdb_modes(struct drm_connector *connector, 4526 const u8 *svds, u8 svds_len) 4527 { 4528 struct drm_device *dev = connector->dev; 4529 int modes = 0, i; 4530 4531 for (i = 0; i < svds_len; i++) { 4532 u8 vic = svd_to_vic(svds[i]); 4533 struct drm_display_mode *newmode; 4534 4535 if (!drm_valid_cea_vic(vic)) 4536 continue; 4537 4538 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4539 if (!newmode) 4540 break; 4541 drm_mode_probed_add(connector, newmode); 4542 modes++; 4543 } 4544 4545 return modes; 4546 } 4547 4548 /** 4549 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4550 * @dev: DRM device 4551 * @video_code: CEA VIC of the mode 4552 * 4553 * Creates a new mode matching the specified CEA VIC. 4554 * 4555 * Returns: A new drm_display_mode on success or NULL on failure 4556 */ 4557 struct drm_display_mode * 4558 drm_display_mode_from_cea_vic(struct drm_device *dev, 4559 u8 video_code) 4560 { 4561 const struct drm_display_mode *cea_mode; 4562 struct drm_display_mode *newmode; 4563 4564 cea_mode = cea_mode_for_vic(video_code); 4565 if (!cea_mode) 4566 return NULL; 4567 4568 newmode = drm_mode_duplicate(dev, cea_mode); 4569 if (!newmode) 4570 return NULL; 4571 4572 return newmode; 4573 } 4574 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4575 4576 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4577 static int add_cta_vdb_modes(struct drm_connector *connector) 4578 { 4579 const struct drm_display_info *info = &connector->display_info; 4580 int i, modes = 0; 4581 4582 if (!info->vics) 4583 return 0; 4584 4585 for (i = 0; i < info->vics_len; i++) { 4586 struct drm_display_mode *mode; 4587 4588 mode = drm_display_mode_from_vic_index(connector, i); 4589 if (mode) { 4590 drm_mode_probed_add(connector, mode); 4591 modes++; 4592 } 4593 } 4594 4595 return modes; 4596 } 4597 4598 struct stereo_mandatory_mode { 4599 int width, height, vrefresh; 4600 unsigned int flags; 4601 }; 4602 4603 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4604 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4605 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4606 { 1920, 1080, 50, 4607 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4608 { 1920, 1080, 60, 4609 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4610 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4611 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4612 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4613 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4614 }; 4615 4616 static bool 4617 stereo_match_mandatory(const struct drm_display_mode *mode, 4618 const struct stereo_mandatory_mode *stereo_mode) 4619 { 4620 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4621 4622 return mode->hdisplay == stereo_mode->width && 4623 mode->vdisplay == stereo_mode->height && 4624 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4625 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4626 } 4627 4628 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4629 { 4630 struct drm_device *dev = connector->dev; 4631 const struct drm_display_mode *mode; 4632 struct list_head stereo_modes; 4633 int modes = 0, i; 4634 4635 INIT_LIST_HEAD(&stereo_modes); 4636 4637 list_for_each_entry(mode, &connector->probed_modes, head) { 4638 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4639 const struct stereo_mandatory_mode *mandatory; 4640 struct drm_display_mode *new_mode; 4641 4642 if (!stereo_match_mandatory(mode, 4643 &stereo_mandatory_modes[i])) 4644 continue; 4645 4646 mandatory = &stereo_mandatory_modes[i]; 4647 new_mode = drm_mode_duplicate(dev, mode); 4648 if (!new_mode) 4649 continue; 4650 4651 new_mode->flags |= mandatory->flags; 4652 list_add_tail(&new_mode->head, &stereo_modes); 4653 modes++; 4654 } 4655 } 4656 4657 list_splice_tail(&stereo_modes, &connector->probed_modes); 4658 4659 return modes; 4660 } 4661 4662 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4663 { 4664 struct drm_device *dev = connector->dev; 4665 struct drm_display_mode *newmode; 4666 4667 if (!drm_valid_hdmi_vic(vic)) { 4668 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4669 connector->base.id, connector->name, vic); 4670 return 0; 4671 } 4672 4673 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4674 if (!newmode) 4675 return 0; 4676 4677 drm_mode_probed_add(connector, newmode); 4678 4679 return 1; 4680 } 4681 4682 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4683 int vic_index) 4684 { 4685 struct drm_display_mode *newmode; 4686 int modes = 0; 4687 4688 if (structure & (1 << 0)) { 4689 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4690 if (newmode) { 4691 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4692 drm_mode_probed_add(connector, newmode); 4693 modes++; 4694 } 4695 } 4696 if (structure & (1 << 6)) { 4697 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4698 if (newmode) { 4699 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4700 drm_mode_probed_add(connector, newmode); 4701 modes++; 4702 } 4703 } 4704 if (structure & (1 << 8)) { 4705 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4706 if (newmode) { 4707 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4708 drm_mode_probed_add(connector, newmode); 4709 modes++; 4710 } 4711 } 4712 4713 return modes; 4714 } 4715 4716 static bool hdmi_vsdb_latency_present(const u8 *db) 4717 { 4718 return db[8] & BIT(7); 4719 } 4720 4721 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4722 { 4723 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4724 } 4725 4726 static int hdmi_vsdb_latency_length(const u8 *db) 4727 { 4728 if (hdmi_vsdb_i_latency_present(db)) 4729 return 4; 4730 else if (hdmi_vsdb_latency_present(db)) 4731 return 2; 4732 else 4733 return 0; 4734 } 4735 4736 /* 4737 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4738 * @connector: connector corresponding to the HDMI sink 4739 * @db: start of the CEA vendor specific block 4740 * @len: length of the CEA block payload, ie. one can access up to db[len] 4741 * 4742 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4743 * also adds the stereo 3d modes when applicable. 4744 */ 4745 static int 4746 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4747 { 4748 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4749 u8 vic_len, hdmi_3d_len = 0; 4750 u16 mask; 4751 u16 structure_all; 4752 4753 if (len < 8) 4754 goto out; 4755 4756 /* no HDMI_Video_Present */ 4757 if (!(db[8] & (1 << 5))) 4758 goto out; 4759 4760 offset += hdmi_vsdb_latency_length(db); 4761 4762 /* the declared length is not long enough for the 2 first bytes 4763 * of additional video format capabilities */ 4764 if (len < (8 + offset + 2)) 4765 goto out; 4766 4767 /* 3D_Present */ 4768 offset++; 4769 if (db[8 + offset] & (1 << 7)) { 4770 modes += add_hdmi_mandatory_stereo_modes(connector); 4771 4772 /* 3D_Multi_present */ 4773 multi_present = (db[8 + offset] & 0x60) >> 5; 4774 } 4775 4776 offset++; 4777 vic_len = db[8 + offset] >> 5; 4778 hdmi_3d_len = db[8 + offset] & 0x1f; 4779 4780 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4781 u8 vic; 4782 4783 vic = db[9 + offset + i]; 4784 modes += add_hdmi_mode(connector, vic); 4785 } 4786 offset += 1 + vic_len; 4787 4788 if (multi_present == 1) 4789 multi_len = 2; 4790 else if (multi_present == 2) 4791 multi_len = 4; 4792 else 4793 multi_len = 0; 4794 4795 if (len < (8 + offset + hdmi_3d_len - 1)) 4796 goto out; 4797 4798 if (hdmi_3d_len < multi_len) 4799 goto out; 4800 4801 if (multi_present == 1 || multi_present == 2) { 4802 /* 3D_Structure_ALL */ 4803 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4804 4805 /* check if 3D_MASK is present */ 4806 if (multi_present == 2) 4807 mask = (db[10 + offset] << 8) | db[11 + offset]; 4808 else 4809 mask = 0xffff; 4810 4811 for (i = 0; i < 16; i++) { 4812 if (mask & (1 << i)) 4813 modes += add_3d_struct_modes(connector, 4814 structure_all, i); 4815 } 4816 } 4817 4818 offset += multi_len; 4819 4820 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4821 int vic_index; 4822 struct drm_display_mode *newmode = NULL; 4823 unsigned int newflag = 0; 4824 bool detail_present; 4825 4826 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4827 4828 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4829 break; 4830 4831 /* 2D_VIC_order_X */ 4832 vic_index = db[8 + offset + i] >> 4; 4833 4834 /* 3D_Structure_X */ 4835 switch (db[8 + offset + i] & 0x0f) { 4836 case 0: 4837 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4838 break; 4839 case 6: 4840 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4841 break; 4842 case 8: 4843 /* 3D_Detail_X */ 4844 if ((db[9 + offset + i] >> 4) == 1) 4845 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4846 break; 4847 } 4848 4849 if (newflag != 0) { 4850 newmode = drm_display_mode_from_vic_index(connector, 4851 vic_index); 4852 4853 if (newmode) { 4854 newmode->flags |= newflag; 4855 drm_mode_probed_add(connector, newmode); 4856 modes++; 4857 } 4858 } 4859 4860 if (detail_present) 4861 i++; 4862 } 4863 4864 out: 4865 return modes; 4866 } 4867 4868 static int 4869 cea_revision(const u8 *cea) 4870 { 4871 /* 4872 * FIXME is this correct for the DispID variant? 4873 * The DispID spec doesn't really specify whether 4874 * this is the revision of the CEA extension or 4875 * the DispID CEA data block. And the only value 4876 * given as an example is 0. 4877 */ 4878 return cea[1]; 4879 } 4880 4881 /* 4882 * CTA Data Block iterator. 4883 * 4884 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4885 * CTA Data Blocks. 4886 * 4887 * struct cea_db *db: 4888 * struct cea_db_iter iter; 4889 * 4890 * cea_db_iter_edid_begin(edid, &iter); 4891 * cea_db_iter_for_each(db, &iter) { 4892 * // do stuff with db 4893 * } 4894 * cea_db_iter_end(&iter); 4895 */ 4896 struct cea_db_iter { 4897 struct drm_edid_iter edid_iter; 4898 struct displayid_iter displayid_iter; 4899 4900 /* Current Data Block Collection. */ 4901 const u8 *collection; 4902 4903 /* Current Data Block index in current collection. */ 4904 int index; 4905 4906 /* End index in current collection. */ 4907 int end; 4908 }; 4909 4910 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4911 struct cea_db { 4912 u8 tag_length; 4913 u8 data[]; 4914 } __packed; 4915 4916 static int cea_db_tag(const struct cea_db *db) 4917 { 4918 return db->tag_length >> 5; 4919 } 4920 4921 static int cea_db_payload_len(const void *_db) 4922 { 4923 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4924 const struct cea_db *db = _db; 4925 4926 return db->tag_length & 0x1f; 4927 } 4928 4929 static const void *cea_db_data(const struct cea_db *db) 4930 { 4931 return db->data; 4932 } 4933 4934 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4935 { 4936 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4937 cea_db_payload_len(db) >= 1 && 4938 db->data[0] == tag; 4939 } 4940 4941 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4942 { 4943 const u8 *data = cea_db_data(db); 4944 4945 return cea_db_tag(db) == CTA_DB_VENDOR && 4946 cea_db_payload_len(db) >= 3 && 4947 oui(data[2], data[1], data[0]) == vendor_oui; 4948 } 4949 4950 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4951 struct cea_db_iter *iter) 4952 { 4953 memset(iter, 0, sizeof(*iter)); 4954 4955 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4956 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4957 } 4958 4959 static const struct cea_db * 4960 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4961 { 4962 const struct cea_db *db; 4963 4964 if (!iter->collection) 4965 return NULL; 4966 4967 db = (const struct cea_db *)&iter->collection[iter->index]; 4968 4969 if (iter->index + sizeof(*db) <= iter->end && 4970 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4971 return db; 4972 4973 return NULL; 4974 } 4975 4976 /* 4977 * References: 4978 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4979 */ 4980 static int cea_db_collection_size(const u8 *cta) 4981 { 4982 u8 d = cta[2]; 4983 4984 if (d < 4 || d > 127) 4985 return 0; 4986 4987 return d - 4; 4988 } 4989 4990 /* 4991 * References: 4992 * - VESA E-EDID v1.4 4993 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4994 */ 4995 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4996 { 4997 const u8 *ext; 4998 4999 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5000 int size; 5001 5002 /* Only support CTA Extension revision 3+ */ 5003 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5004 continue; 5005 5006 size = cea_db_collection_size(ext); 5007 if (!size) 5008 continue; 5009 5010 iter->index = 4; 5011 iter->end = iter->index + size; 5012 5013 return ext; 5014 } 5015 5016 return NULL; 5017 } 5018 5019 /* 5020 * References: 5021 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5022 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5023 * 5024 * Note that the above do not specify any connection between DisplayID Data 5025 * Block revision and CTA Extension versions. 5026 */ 5027 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5028 { 5029 const struct displayid_block *block; 5030 5031 displayid_iter_for_each(block, &iter->displayid_iter) { 5032 if (block->tag != DATA_BLOCK_CTA) 5033 continue; 5034 5035 /* 5036 * The displayid iterator has already verified the block bounds 5037 * in displayid_iter_block(). 5038 */ 5039 iter->index = sizeof(*block); 5040 iter->end = iter->index + block->num_bytes; 5041 5042 return block; 5043 } 5044 5045 return NULL; 5046 } 5047 5048 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5049 { 5050 const struct cea_db *db; 5051 5052 if (iter->collection) { 5053 /* Current collection should always be valid. */ 5054 db = __cea_db_iter_current_block(iter); 5055 if (WARN_ON(!db)) { 5056 iter->collection = NULL; 5057 return NULL; 5058 } 5059 5060 /* Next block in CTA Data Block Collection */ 5061 iter->index += sizeof(*db) + cea_db_payload_len(db); 5062 5063 db = __cea_db_iter_current_block(iter); 5064 if (db) 5065 return db; 5066 } 5067 5068 for (;;) { 5069 /* 5070 * Find the next CTA Data Block Collection. First iterate all 5071 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5072 * 5073 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5074 * Extension, it's recommended that DisplayID extensions are 5075 * exposed after all of the CTA Extensions. 5076 */ 5077 iter->collection = __cea_db_iter_edid_next(iter); 5078 if (!iter->collection) 5079 iter->collection = __cea_db_iter_displayid_next(iter); 5080 5081 if (!iter->collection) 5082 return NULL; 5083 5084 db = __cea_db_iter_current_block(iter); 5085 if (db) 5086 return db; 5087 } 5088 } 5089 5090 #define cea_db_iter_for_each(__db, __iter) \ 5091 while (((__db) = __cea_db_iter_next(__iter))) 5092 5093 static void cea_db_iter_end(struct cea_db_iter *iter) 5094 { 5095 displayid_iter_end(&iter->displayid_iter); 5096 drm_edid_iter_end(&iter->edid_iter); 5097 5098 memset(iter, 0, sizeof(*iter)); 5099 } 5100 5101 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5102 { 5103 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5104 cea_db_payload_len(db) >= 5; 5105 } 5106 5107 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5108 { 5109 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5110 cea_db_payload_len(db) >= 7; 5111 } 5112 5113 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5114 { 5115 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5116 cea_db_payload_len(db) >= 2; 5117 } 5118 5119 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5120 { 5121 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5122 cea_db_payload_len(db) == 21; 5123 } 5124 5125 static bool cea_db_is_vcdb(const struct cea_db *db) 5126 { 5127 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5128 cea_db_payload_len(db) == 2; 5129 } 5130 5131 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5132 { 5133 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5134 cea_db_payload_len(db) >= 7; 5135 } 5136 5137 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5138 { 5139 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5140 } 5141 5142 static bool cea_db_is_y420vdb(const struct cea_db *db) 5143 { 5144 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5145 } 5146 5147 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5148 { 5149 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5150 cea_db_payload_len(db) >= 3; 5151 } 5152 5153 /* 5154 * Get the HF-EEODB override extension block count from EDID. 5155 * 5156 * The passed in EDID may be partially read, as long as it has at least two 5157 * blocks (base block and one extension block) if EDID extension count is > 0. 5158 * 5159 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5160 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5161 * iterators instead. 5162 * 5163 * References: 5164 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5165 */ 5166 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5167 { 5168 const u8 *cta; 5169 5170 /* No extensions according to base block, no HF-EEODB. */ 5171 if (!edid_extension_block_count(edid)) 5172 return 0; 5173 5174 /* HF-EEODB is always in the first EDID extension block only */ 5175 cta = edid_extension_block_data(edid, 0); 5176 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5177 return 0; 5178 5179 /* Need to have the data block collection, and at least 3 bytes. */ 5180 if (cea_db_collection_size(cta) < 3) 5181 return 0; 5182 5183 /* 5184 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5185 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5186 * through 6 of Block 1 of the E-EDID. 5187 */ 5188 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5189 return 0; 5190 5191 return cta[4 + 2]; 5192 } 5193 5194 /* 5195 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5196 * 5197 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5198 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5199 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5200 * support YCBCR420 output too. 5201 */ 5202 static void parse_cta_y420cmdb(struct drm_connector *connector, 5203 const struct cea_db *db, u64 *y420cmdb_map) 5204 { 5205 struct drm_display_info *info = &connector->display_info; 5206 int i, map_len = cea_db_payload_len(db) - 1; 5207 const u8 *data = cea_db_data(db) + 1; 5208 u64 map = 0; 5209 5210 if (map_len == 0) { 5211 /* All CEA modes support ycbcr420 sampling also.*/ 5212 map = U64_MAX; 5213 goto out; 5214 } 5215 5216 /* 5217 * This map indicates which of the existing CEA block modes 5218 * from VDB can support YCBCR420 output too. So if bit=0 is 5219 * set, first mode from VDB can support YCBCR420 output too. 5220 * We will parse and keep this map, before parsing VDB itself 5221 * to avoid going through the same block again and again. 5222 * 5223 * Spec is not clear about max possible size of this block. 5224 * Clamping max bitmap block size at 8 bytes. Every byte can 5225 * address 8 CEA modes, in this way this map can address 5226 * 8*8 = first 64 SVDs. 5227 */ 5228 if (WARN_ON_ONCE(map_len > 8)) 5229 map_len = 8; 5230 5231 for (i = 0; i < map_len; i++) 5232 map |= (u64)data[i] << (8 * i); 5233 5234 out: 5235 if (map) 5236 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5237 5238 *y420cmdb_map = map; 5239 } 5240 5241 static int add_cea_modes(struct drm_connector *connector, 5242 const struct drm_edid *drm_edid) 5243 { 5244 const struct cea_db *db; 5245 struct cea_db_iter iter; 5246 int modes; 5247 5248 /* CTA VDB block VICs parsed earlier */ 5249 modes = add_cta_vdb_modes(connector); 5250 5251 cea_db_iter_edid_begin(drm_edid, &iter); 5252 cea_db_iter_for_each(db, &iter) { 5253 if (cea_db_is_hdmi_vsdb(db)) { 5254 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5255 cea_db_payload_len(db)); 5256 } else if (cea_db_is_y420vdb(db)) { 5257 const u8 *vdb420 = cea_db_data(db) + 1; 5258 5259 /* Add 4:2:0(only) modes present in EDID */ 5260 modes += do_y420vdb_modes(connector, vdb420, 5261 cea_db_payload_len(db) - 1); 5262 } 5263 } 5264 cea_db_iter_end(&iter); 5265 5266 return modes; 5267 } 5268 5269 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5270 struct drm_display_mode *mode) 5271 { 5272 const struct drm_display_mode *cea_mode; 5273 int clock1, clock2, clock; 5274 u8 vic; 5275 const char *type; 5276 5277 /* 5278 * allow 5kHz clock difference either way to account for 5279 * the 10kHz clock resolution limit of detailed timings. 5280 */ 5281 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5282 if (drm_valid_cea_vic(vic)) { 5283 type = "CEA"; 5284 cea_mode = cea_mode_for_vic(vic); 5285 clock1 = cea_mode->clock; 5286 clock2 = cea_mode_alternate_clock(cea_mode); 5287 } else { 5288 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5289 if (drm_valid_hdmi_vic(vic)) { 5290 type = "HDMI"; 5291 cea_mode = &edid_4k_modes[vic]; 5292 clock1 = cea_mode->clock; 5293 clock2 = hdmi_mode_alternate_clock(cea_mode); 5294 } else { 5295 return; 5296 } 5297 } 5298 5299 /* pick whichever is closest */ 5300 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5301 clock = clock1; 5302 else 5303 clock = clock2; 5304 5305 if (mode->clock == clock) 5306 return; 5307 5308 drm_dbg_kms(connector->dev, 5309 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5310 connector->base.id, connector->name, 5311 type, vic, mode->clock, clock); 5312 mode->clock = clock; 5313 } 5314 5315 static void drm_calculate_luminance_range(struct drm_connector *connector) 5316 { 5317 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5318 struct drm_luminance_range_info *luminance_range = 5319 &connector->display_info.luminance_range; 5320 static const u8 pre_computed_values[] = { 5321 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5322 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5323 }; 5324 u32 max_avg, min_cll, max, min, q, r; 5325 5326 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5327 return; 5328 5329 max_avg = hdr_metadata->max_fall; 5330 min_cll = hdr_metadata->min_cll; 5331 5332 /* 5333 * From the specification (CTA-861-G), for calculating the maximum 5334 * luminance we need to use: 5335 * Luminance = 50*2**(CV/32) 5336 * Where CV is a one-byte value. 5337 * For calculating this expression we may need float point precision; 5338 * to avoid this complexity level, we take advantage that CV is divided 5339 * by a constant. From the Euclids division algorithm, we know that CV 5340 * can be written as: CV = 32*q + r. Next, we replace CV in the 5341 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5342 * need to pre-compute the value of r/32. For pre-computing the values 5343 * We just used the following Ruby line: 5344 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5345 * The results of the above expressions can be verified at 5346 * pre_computed_values. 5347 */ 5348 q = max_avg >> 5; 5349 r = max_avg % 32; 5350 max = (1 << q) * pre_computed_values[r]; 5351 5352 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5353 q = DIV_ROUND_CLOSEST(min_cll, 255); 5354 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5355 5356 luminance_range->min_luminance = min; 5357 luminance_range->max_luminance = max; 5358 } 5359 5360 static uint8_t eotf_supported(const u8 *edid_ext) 5361 { 5362 return edid_ext[2] & 5363 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5364 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5365 BIT(HDMI_EOTF_SMPTE_ST2084) | 5366 BIT(HDMI_EOTF_BT_2100_HLG)); 5367 } 5368 5369 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5370 { 5371 return edid_ext[3] & 5372 BIT(HDMI_STATIC_METADATA_TYPE1); 5373 } 5374 5375 static void 5376 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5377 { 5378 u16 len; 5379 5380 len = cea_db_payload_len(db); 5381 5382 connector->hdr_sink_metadata.hdmi_type1.eotf = 5383 eotf_supported(db); 5384 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5385 hdr_metadata_type(db); 5386 5387 if (len >= 4) 5388 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5389 if (len >= 5) 5390 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5391 if (len >= 6) { 5392 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5393 5394 /* Calculate only when all values are available */ 5395 drm_calculate_luminance_range(connector); 5396 } 5397 } 5398 5399 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5400 static void 5401 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5402 { 5403 u8 len = cea_db_payload_len(db); 5404 5405 if (len >= 6 && (db[6] & (1 << 7))) 5406 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5407 5408 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5409 connector->latency_present[0] = true; 5410 connector->video_latency[0] = db[9]; 5411 connector->audio_latency[0] = db[10]; 5412 } 5413 5414 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5415 connector->latency_present[1] = true; 5416 connector->video_latency[1] = db[11]; 5417 connector->audio_latency[1] = db[12]; 5418 } 5419 5420 drm_dbg_kms(connector->dev, 5421 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5422 connector->base.id, connector->name, 5423 connector->latency_present[0], connector->latency_present[1], 5424 connector->video_latency[0], connector->video_latency[1], 5425 connector->audio_latency[0], connector->audio_latency[1]); 5426 } 5427 5428 static void 5429 monitor_name(const struct detailed_timing *timing, void *data) 5430 { 5431 const char **res = data; 5432 5433 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5434 return; 5435 5436 *res = timing->data.other_data.data.str.str; 5437 } 5438 5439 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5440 { 5441 const char *edid_name = NULL; 5442 int mnl; 5443 5444 if (!drm_edid || !name) 5445 return 0; 5446 5447 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5448 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5449 if (edid_name[mnl] == 0x0a) 5450 break; 5451 5452 name[mnl] = edid_name[mnl]; 5453 } 5454 5455 return mnl; 5456 } 5457 5458 /** 5459 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5460 * @edid: monitor EDID information 5461 * @name: pointer to a character array to hold the name of the monitor 5462 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5463 * 5464 */ 5465 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5466 { 5467 int name_length = 0; 5468 5469 if (bufsize <= 0) 5470 return; 5471 5472 if (edid) { 5473 char buf[13]; 5474 struct drm_edid drm_edid = { 5475 .edid = edid, 5476 .size = edid_size(edid), 5477 }; 5478 5479 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5480 memcpy(name, buf, name_length); 5481 } 5482 5483 name[name_length] = '\0'; 5484 } 5485 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5486 5487 static void clear_eld(struct drm_connector *connector) 5488 { 5489 memset(connector->eld, 0, sizeof(connector->eld)); 5490 5491 connector->latency_present[0] = false; 5492 connector->latency_present[1] = false; 5493 connector->video_latency[0] = 0; 5494 connector->audio_latency[0] = 0; 5495 connector->video_latency[1] = 0; 5496 connector->audio_latency[1] = 0; 5497 } 5498 5499 /* 5500 * drm_edid_to_eld - build ELD from EDID 5501 * @connector: connector corresponding to the HDMI/DP sink 5502 * @drm_edid: EDID to parse 5503 * 5504 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5505 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5506 */ 5507 static void drm_edid_to_eld(struct drm_connector *connector, 5508 const struct drm_edid *drm_edid) 5509 { 5510 const struct drm_display_info *info = &connector->display_info; 5511 const struct cea_db *db; 5512 struct cea_db_iter iter; 5513 uint8_t *eld = connector->eld; 5514 int total_sad_count = 0; 5515 int mnl; 5516 5517 if (!drm_edid) 5518 return; 5519 5520 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5521 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5522 connector->base.id, connector->name, 5523 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5524 5525 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5526 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5527 5528 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5529 5530 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5531 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5532 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5533 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5534 5535 cea_db_iter_edid_begin(drm_edid, &iter); 5536 cea_db_iter_for_each(db, &iter) { 5537 const u8 *data = cea_db_data(db); 5538 int len = cea_db_payload_len(db); 5539 int sad_count; 5540 5541 switch (cea_db_tag(db)) { 5542 case CTA_DB_AUDIO: 5543 /* Audio Data Block, contains SADs */ 5544 sad_count = min(len / 3, 15 - total_sad_count); 5545 if (sad_count >= 1) 5546 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5547 data, sad_count * 3); 5548 total_sad_count += sad_count; 5549 break; 5550 case CTA_DB_SPEAKER: 5551 /* Speaker Allocation Data Block */ 5552 if (len >= 1) 5553 eld[DRM_ELD_SPEAKER] = data[0]; 5554 break; 5555 case CTA_DB_VENDOR: 5556 /* HDMI Vendor-Specific Data Block */ 5557 if (cea_db_is_hdmi_vsdb(db)) 5558 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5559 break; 5560 default: 5561 break; 5562 } 5563 } 5564 cea_db_iter_end(&iter); 5565 5566 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5567 5568 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5569 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5570 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5571 else 5572 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5573 5574 eld[DRM_ELD_BASELINE_ELD_LEN] = 5575 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5576 5577 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5578 connector->base.id, connector->name, 5579 drm_eld_size(eld), total_sad_count); 5580 } 5581 5582 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5583 struct cea_sad **sads) 5584 { 5585 const struct cea_db *db; 5586 struct cea_db_iter iter; 5587 int count = 0; 5588 5589 cea_db_iter_edid_begin(drm_edid, &iter); 5590 cea_db_iter_for_each(db, &iter) { 5591 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5592 int j; 5593 5594 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5595 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5596 if (!*sads) 5597 return -ENOMEM; 5598 for (j = 0; j < count; j++) { 5599 const u8 *sad = &db->data[j * 3]; 5600 5601 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5602 (*sads)[j].channels = sad[0] & 0x7; 5603 (*sads)[j].freq = sad[1] & 0x7F; 5604 (*sads)[j].byte2 = sad[2]; 5605 } 5606 break; 5607 } 5608 } 5609 cea_db_iter_end(&iter); 5610 5611 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5612 5613 return count; 5614 } 5615 5616 /** 5617 * drm_edid_to_sad - extracts SADs from EDID 5618 * @edid: EDID to parse 5619 * @sads: pointer that will be set to the extracted SADs 5620 * 5621 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5622 * 5623 * Note: The returned pointer needs to be freed using kfree(). 5624 * 5625 * Return: The number of found SADs or negative number on error. 5626 */ 5627 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5628 { 5629 struct drm_edid drm_edid; 5630 5631 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5632 } 5633 EXPORT_SYMBOL(drm_edid_to_sad); 5634 5635 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5636 u8 **sadb) 5637 { 5638 const struct cea_db *db; 5639 struct cea_db_iter iter; 5640 int count = 0; 5641 5642 cea_db_iter_edid_begin(drm_edid, &iter); 5643 cea_db_iter_for_each(db, &iter) { 5644 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5645 cea_db_payload_len(db) == 3) { 5646 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5647 GFP_KERNEL); 5648 if (!*sadb) 5649 return -ENOMEM; 5650 count = cea_db_payload_len(db); 5651 break; 5652 } 5653 } 5654 cea_db_iter_end(&iter); 5655 5656 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5657 5658 return count; 5659 } 5660 5661 /** 5662 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5663 * @edid: EDID to parse 5664 * @sadb: pointer to the speaker block 5665 * 5666 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5667 * 5668 * Note: The returned pointer needs to be freed using kfree(). 5669 * 5670 * Return: The number of found Speaker Allocation Blocks or negative number on 5671 * error. 5672 */ 5673 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5674 { 5675 struct drm_edid drm_edid; 5676 5677 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5678 sadb); 5679 } 5680 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5681 5682 /** 5683 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5684 * @connector: connector associated with the HDMI/DP sink 5685 * @mode: the display mode 5686 * 5687 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5688 * the sink doesn't support audio or video. 5689 */ 5690 int drm_av_sync_delay(struct drm_connector *connector, 5691 const struct drm_display_mode *mode) 5692 { 5693 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5694 int a, v; 5695 5696 if (!connector->latency_present[0]) 5697 return 0; 5698 if (!connector->latency_present[1]) 5699 i = 0; 5700 5701 a = connector->audio_latency[i]; 5702 v = connector->video_latency[i]; 5703 5704 /* 5705 * HDMI/DP sink doesn't support audio or video? 5706 */ 5707 if (a == 255 || v == 255) 5708 return 0; 5709 5710 /* 5711 * Convert raw EDID values to millisecond. 5712 * Treat unknown latency as 0ms. 5713 */ 5714 if (a) 5715 a = min(2 * (a - 1), 500); 5716 if (v) 5717 v = min(2 * (v - 1), 500); 5718 5719 return max(v - a, 0); 5720 } 5721 EXPORT_SYMBOL(drm_av_sync_delay); 5722 5723 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5724 { 5725 const struct cea_db *db; 5726 struct cea_db_iter iter; 5727 bool hdmi = false; 5728 5729 /* 5730 * Because HDMI identifier is in Vendor Specific Block, 5731 * search it from all data blocks of CEA extension. 5732 */ 5733 cea_db_iter_edid_begin(drm_edid, &iter); 5734 cea_db_iter_for_each(db, &iter) { 5735 if (cea_db_is_hdmi_vsdb(db)) { 5736 hdmi = true; 5737 break; 5738 } 5739 } 5740 cea_db_iter_end(&iter); 5741 5742 return hdmi; 5743 } 5744 5745 /** 5746 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5747 * @edid: monitor EDID information 5748 * 5749 * Parse the CEA extension according to CEA-861-B. 5750 * 5751 * Drivers that have added the modes parsed from EDID to drm_display_info 5752 * should use &drm_display_info.is_hdmi instead of calling this function. 5753 * 5754 * Return: True if the monitor is HDMI, false if not or unknown. 5755 */ 5756 bool drm_detect_hdmi_monitor(const struct edid *edid) 5757 { 5758 struct drm_edid drm_edid; 5759 5760 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5761 } 5762 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5763 5764 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5765 { 5766 struct drm_edid_iter edid_iter; 5767 const struct cea_db *db; 5768 struct cea_db_iter iter; 5769 const u8 *edid_ext; 5770 bool has_audio = false; 5771 5772 drm_edid_iter_begin(drm_edid, &edid_iter); 5773 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5774 if (edid_ext[0] == CEA_EXT) { 5775 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5776 if (has_audio) 5777 break; 5778 } 5779 } 5780 drm_edid_iter_end(&edid_iter); 5781 5782 if (has_audio) { 5783 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5784 goto end; 5785 } 5786 5787 cea_db_iter_edid_begin(drm_edid, &iter); 5788 cea_db_iter_for_each(db, &iter) { 5789 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5790 const u8 *data = cea_db_data(db); 5791 int i; 5792 5793 for (i = 0; i < cea_db_payload_len(db); i += 3) 5794 DRM_DEBUG_KMS("CEA audio format %d\n", 5795 (data[i] >> 3) & 0xf); 5796 has_audio = true; 5797 break; 5798 } 5799 } 5800 cea_db_iter_end(&iter); 5801 5802 end: 5803 return has_audio; 5804 } 5805 5806 /** 5807 * drm_detect_monitor_audio - check monitor audio capability 5808 * @edid: EDID block to scan 5809 * 5810 * Monitor should have CEA extension block. 5811 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5812 * audio' only. If there is any audio extension block and supported 5813 * audio format, assume at least 'basic audio' support, even if 'basic 5814 * audio' is not defined in EDID. 5815 * 5816 * Return: True if the monitor supports audio, false otherwise. 5817 */ 5818 bool drm_detect_monitor_audio(const struct edid *edid) 5819 { 5820 struct drm_edid drm_edid; 5821 5822 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5823 } 5824 EXPORT_SYMBOL(drm_detect_monitor_audio); 5825 5826 5827 /** 5828 * drm_default_rgb_quant_range - default RGB quantization range 5829 * @mode: display mode 5830 * 5831 * Determine the default RGB quantization range for the mode, 5832 * as specified in CEA-861. 5833 * 5834 * Return: The default RGB quantization range for the mode 5835 */ 5836 enum hdmi_quantization_range 5837 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5838 { 5839 /* All CEA modes other than VIC 1 use limited quantization range. */ 5840 return drm_match_cea_mode(mode) > 1 ? 5841 HDMI_QUANTIZATION_RANGE_LIMITED : 5842 HDMI_QUANTIZATION_RANGE_FULL; 5843 } 5844 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5845 5846 /* CTA-861 Video Data Block (CTA VDB) */ 5847 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5848 { 5849 struct drm_display_info *info = &connector->display_info; 5850 int i, vic_index, len = cea_db_payload_len(db); 5851 const u8 *svds = cea_db_data(db); 5852 u8 *vics; 5853 5854 if (!len) 5855 return; 5856 5857 /* Gracefully handle multiple VDBs, however unlikely that is */ 5858 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5859 if (!vics) 5860 return; 5861 5862 vic_index = info->vics_len; 5863 info->vics_len += len; 5864 info->vics = vics; 5865 5866 for (i = 0; i < len; i++) { 5867 u8 vic = svd_to_vic(svds[i]); 5868 5869 if (!drm_valid_cea_vic(vic)) 5870 vic = 0; 5871 5872 info->vics[vic_index++] = vic; 5873 } 5874 } 5875 5876 /* 5877 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5878 * 5879 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5880 * using the VICs themselves. 5881 */ 5882 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5883 { 5884 struct drm_display_info *info = &connector->display_info; 5885 struct drm_hdmi_info *hdmi = &info->hdmi; 5886 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5887 5888 for (i = 0; i < len; i++) { 5889 u8 vic = info->vics[i]; 5890 5891 if (vic && y420cmdb_map & BIT_ULL(i)) 5892 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5893 } 5894 } 5895 5896 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5897 { 5898 const struct drm_display_info *info = &connector->display_info; 5899 int i; 5900 5901 if (!vic || !info->vics) 5902 return false; 5903 5904 for (i = 0; i < info->vics_len; i++) { 5905 if (info->vics[i] == vic) 5906 return true; 5907 } 5908 5909 return false; 5910 } 5911 5912 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5913 static void parse_cta_y420vdb(struct drm_connector *connector, 5914 const struct cea_db *db) 5915 { 5916 struct drm_display_info *info = &connector->display_info; 5917 struct drm_hdmi_info *hdmi = &info->hdmi; 5918 const u8 *svds = cea_db_data(db) + 1; 5919 int i; 5920 5921 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5922 u8 vic = svd_to_vic(svds[i]); 5923 5924 if (!drm_valid_cea_vic(vic)) 5925 continue; 5926 5927 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5928 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5929 } 5930 } 5931 5932 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5933 { 5934 struct drm_display_info *info = &connector->display_info; 5935 5936 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5937 connector->base.id, connector->name, db[2]); 5938 5939 if (db[2] & EDID_CEA_VCDB_QS) 5940 info->rgb_quant_range_selectable = true; 5941 } 5942 5943 static 5944 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5945 { 5946 switch (max_frl_rate) { 5947 case 1: 5948 *max_lanes = 3; 5949 *max_rate_per_lane = 3; 5950 break; 5951 case 2: 5952 *max_lanes = 3; 5953 *max_rate_per_lane = 6; 5954 break; 5955 case 3: 5956 *max_lanes = 4; 5957 *max_rate_per_lane = 6; 5958 break; 5959 case 4: 5960 *max_lanes = 4; 5961 *max_rate_per_lane = 8; 5962 break; 5963 case 5: 5964 *max_lanes = 4; 5965 *max_rate_per_lane = 10; 5966 break; 5967 case 6: 5968 *max_lanes = 4; 5969 *max_rate_per_lane = 12; 5970 break; 5971 case 0: 5972 default: 5973 *max_lanes = 0; 5974 *max_rate_per_lane = 0; 5975 } 5976 } 5977 5978 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5979 const u8 *db) 5980 { 5981 u8 dc_mask; 5982 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5983 5984 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5985 hdmi->y420_dc_modes = dc_mask; 5986 } 5987 5988 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 5989 const u8 *hf_scds) 5990 { 5991 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5992 5993 if (!hdmi_dsc->v_1p2) 5994 return; 5995 5996 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5997 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5998 5999 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6000 hdmi_dsc->bpc_supported = 16; 6001 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6002 hdmi_dsc->bpc_supported = 12; 6003 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6004 hdmi_dsc->bpc_supported = 10; 6005 else 6006 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6007 hdmi_dsc->bpc_supported = 8; 6008 6009 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6010 u8 dsc_max_slices; 6011 u8 dsc_max_frl_rate; 6012 6013 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6014 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6015 &hdmi_dsc->max_frl_rate_per_lane); 6016 6017 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6018 6019 switch (dsc_max_slices) { 6020 case 1: 6021 hdmi_dsc->max_slices = 1; 6022 hdmi_dsc->clk_per_slice = 340; 6023 break; 6024 case 2: 6025 hdmi_dsc->max_slices = 2; 6026 hdmi_dsc->clk_per_slice = 340; 6027 break; 6028 case 3: 6029 hdmi_dsc->max_slices = 4; 6030 hdmi_dsc->clk_per_slice = 340; 6031 break; 6032 case 4: 6033 hdmi_dsc->max_slices = 8; 6034 hdmi_dsc->clk_per_slice = 340; 6035 break; 6036 case 5: 6037 hdmi_dsc->max_slices = 8; 6038 hdmi_dsc->clk_per_slice = 400; 6039 break; 6040 case 6: 6041 hdmi_dsc->max_slices = 12; 6042 hdmi_dsc->clk_per_slice = 400; 6043 break; 6044 case 7: 6045 hdmi_dsc->max_slices = 16; 6046 hdmi_dsc->clk_per_slice = 400; 6047 break; 6048 case 0: 6049 default: 6050 hdmi_dsc->max_slices = 0; 6051 hdmi_dsc->clk_per_slice = 0; 6052 } 6053 } 6054 6055 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6056 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6057 } 6058 6059 /* Sink Capability Data Structure */ 6060 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6061 const u8 *hf_scds) 6062 { 6063 struct drm_display_info *info = &connector->display_info; 6064 struct drm_hdmi_info *hdmi = &info->hdmi; 6065 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6066 int max_tmds_clock = 0; 6067 u8 max_frl_rate = 0; 6068 bool dsc_support = false; 6069 6070 info->has_hdmi_infoframe = true; 6071 6072 if (hf_scds[6] & 0x80) { 6073 hdmi->scdc.supported = true; 6074 if (hf_scds[6] & 0x40) 6075 hdmi->scdc.read_request = true; 6076 } 6077 6078 /* 6079 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6080 * And as per the spec, three factors confirm this: 6081 * * Availability of a HF-VSDB block in EDID (check) 6082 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6083 * * SCDC support available (let's check) 6084 * Lets check it out. 6085 */ 6086 6087 if (hf_scds[5]) { 6088 struct drm_scdc *scdc = &hdmi->scdc; 6089 6090 /* max clock is 5000 KHz times block value */ 6091 max_tmds_clock = hf_scds[5] * 5000; 6092 6093 if (max_tmds_clock > 340000) { 6094 info->max_tmds_clock = max_tmds_clock; 6095 } 6096 6097 if (scdc->supported) { 6098 scdc->scrambling.supported = true; 6099 6100 /* Few sinks support scrambling for clocks < 340M */ 6101 if ((hf_scds[6] & 0x8)) 6102 scdc->scrambling.low_rates = true; 6103 } 6104 } 6105 6106 if (hf_scds[7]) { 6107 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6108 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6109 &hdmi->max_frl_rate_per_lane); 6110 } 6111 6112 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6113 6114 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6115 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6116 dsc_support = true; 6117 } 6118 6119 drm_dbg_kms(connector->dev, 6120 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6121 connector->base.id, connector->name, 6122 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6123 } 6124 6125 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6126 const u8 *hdmi) 6127 { 6128 struct drm_display_info *info = &connector->display_info; 6129 unsigned int dc_bpc = 0; 6130 6131 /* HDMI supports at least 8 bpc */ 6132 info->bpc = 8; 6133 6134 if (cea_db_payload_len(hdmi) < 6) 6135 return; 6136 6137 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6138 dc_bpc = 10; 6139 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6140 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6141 connector->base.id, connector->name); 6142 } 6143 6144 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6145 dc_bpc = 12; 6146 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6147 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6148 connector->base.id, connector->name); 6149 } 6150 6151 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6152 dc_bpc = 16; 6153 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6154 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6155 connector->base.id, connector->name); 6156 } 6157 6158 if (dc_bpc == 0) { 6159 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6160 connector->base.id, connector->name); 6161 return; 6162 } 6163 6164 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6165 connector->base.id, connector->name, dc_bpc); 6166 info->bpc = dc_bpc; 6167 6168 /* YCRCB444 is optional according to spec. */ 6169 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6170 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6171 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6172 connector->base.id, connector->name); 6173 } 6174 6175 /* 6176 * Spec says that if any deep color mode is supported at all, 6177 * then deep color 36 bit must be supported. 6178 */ 6179 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6180 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6181 connector->base.id, connector->name); 6182 } 6183 } 6184 6185 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6186 static void 6187 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6188 { 6189 struct drm_display_info *info = &connector->display_info; 6190 u8 len = cea_db_payload_len(db); 6191 6192 info->is_hdmi = true; 6193 6194 if (len >= 6) 6195 info->dvi_dual = db[6] & 1; 6196 if (len >= 7) 6197 info->max_tmds_clock = db[7] * 5000; 6198 6199 /* 6200 * Try to infer whether the sink supports HDMI infoframes. 6201 * 6202 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6203 * supports infoframes if HDMI_Video_present is set. 6204 */ 6205 if (len >= 8 && db[8] & BIT(5)) 6206 info->has_hdmi_infoframe = true; 6207 6208 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6209 connector->base.id, connector->name, 6210 info->dvi_dual, info->max_tmds_clock); 6211 6212 drm_parse_hdmi_deep_color_info(connector, db); 6213 } 6214 6215 /* 6216 * See EDID extension for head-mounted and specialized monitors, specified at: 6217 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6218 */ 6219 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6220 const u8 *db) 6221 { 6222 struct drm_display_info *info = &connector->display_info; 6223 u8 version = db[4]; 6224 bool desktop_usage = db[5] & BIT(6); 6225 6226 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6227 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6228 info->non_desktop = true; 6229 6230 drm_dbg_kms(connector->dev, 6231 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6232 connector->base.id, connector->name, version, db[5]); 6233 } 6234 6235 static void drm_parse_cea_ext(struct drm_connector *connector, 6236 const struct drm_edid *drm_edid) 6237 { 6238 struct drm_display_info *info = &connector->display_info; 6239 struct drm_edid_iter edid_iter; 6240 const struct cea_db *db; 6241 struct cea_db_iter iter; 6242 const u8 *edid_ext; 6243 u64 y420cmdb_map = 0; 6244 6245 drm_edid_iter_begin(drm_edid, &edid_iter); 6246 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6247 if (edid_ext[0] != CEA_EXT) 6248 continue; 6249 6250 if (!info->cea_rev) 6251 info->cea_rev = edid_ext[1]; 6252 6253 if (info->cea_rev != edid_ext[1]) 6254 drm_dbg_kms(connector->dev, 6255 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6256 connector->base.id, connector->name, 6257 info->cea_rev, edid_ext[1]); 6258 6259 /* The existence of a CTA extension should imply RGB support */ 6260 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6261 if (edid_ext[3] & EDID_CEA_YCRCB444) 6262 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6263 if (edid_ext[3] & EDID_CEA_YCRCB422) 6264 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6265 if (edid_ext[3] & EDID_BASIC_AUDIO) 6266 info->has_audio = true; 6267 6268 } 6269 drm_edid_iter_end(&edid_iter); 6270 6271 cea_db_iter_edid_begin(drm_edid, &iter); 6272 cea_db_iter_for_each(db, &iter) { 6273 /* FIXME: convert parsers to use struct cea_db */ 6274 const u8 *data = (const u8 *)db; 6275 6276 if (cea_db_is_hdmi_vsdb(db)) 6277 drm_parse_hdmi_vsdb_video(connector, data); 6278 else if (cea_db_is_hdmi_forum_vsdb(db) || 6279 cea_db_is_hdmi_forum_scdb(db)) 6280 drm_parse_hdmi_forum_scds(connector, data); 6281 else if (cea_db_is_microsoft_vsdb(db)) 6282 drm_parse_microsoft_vsdb(connector, data); 6283 else if (cea_db_is_y420cmdb(db)) 6284 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6285 else if (cea_db_is_y420vdb(db)) 6286 parse_cta_y420vdb(connector, db); 6287 else if (cea_db_is_vcdb(db)) 6288 drm_parse_vcdb(connector, data); 6289 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6290 drm_parse_hdr_metadata_block(connector, data); 6291 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6292 parse_cta_vdb(connector, db); 6293 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6294 info->has_audio = true; 6295 } 6296 cea_db_iter_end(&iter); 6297 6298 if (y420cmdb_map) 6299 update_cta_y420cmdb(connector, y420cmdb_map); 6300 } 6301 6302 static 6303 void get_monitor_range(const struct detailed_timing *timing, void *c) 6304 { 6305 struct detailed_mode_closure *closure = c; 6306 struct drm_display_info *info = &closure->connector->display_info; 6307 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6308 const struct detailed_non_pixel *data = &timing->data.other_data; 6309 const struct detailed_data_monitor_range *range = &data->data.range; 6310 const struct edid *edid = closure->drm_edid->edid; 6311 6312 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6313 return; 6314 6315 /* 6316 * These limits are used to determine the VRR refresh 6317 * rate range. Only the "range limits only" variant 6318 * of the range descriptor seems to guarantee that 6319 * any and all timings are accepted by the sink, as 6320 * opposed to just timings conforming to the indicated 6321 * formula (GTF/GTF2/CVT). Thus other variants of the 6322 * range descriptor are not accepted here. 6323 */ 6324 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6325 return; 6326 6327 monitor_range->min_vfreq = range->min_vfreq; 6328 monitor_range->max_vfreq = range->max_vfreq; 6329 6330 if (edid->revision >= 4) { 6331 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6332 monitor_range->min_vfreq += 255; 6333 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6334 monitor_range->max_vfreq += 255; 6335 } 6336 } 6337 6338 static void drm_get_monitor_range(struct drm_connector *connector, 6339 const struct drm_edid *drm_edid) 6340 { 6341 const struct drm_display_info *info = &connector->display_info; 6342 struct detailed_mode_closure closure = { 6343 .connector = connector, 6344 .drm_edid = drm_edid, 6345 }; 6346 6347 if (drm_edid->edid->revision < 4) 6348 return; 6349 6350 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6351 return; 6352 6353 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6354 6355 drm_dbg_kms(connector->dev, 6356 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6357 connector->base.id, connector->name, 6358 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6359 } 6360 6361 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6362 const struct displayid_block *block) 6363 { 6364 struct displayid_vesa_vendor_specific_block *vesa = 6365 (struct displayid_vesa_vendor_specific_block *)block; 6366 struct drm_display_info *info = &connector->display_info; 6367 6368 if (block->num_bytes < 3) { 6369 drm_dbg_kms(connector->dev, 6370 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6371 connector->base.id, connector->name, block->num_bytes); 6372 return; 6373 } 6374 6375 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6376 return; 6377 6378 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6379 drm_dbg_kms(connector->dev, 6380 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6381 connector->base.id, connector->name); 6382 return; 6383 } 6384 6385 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6386 default: 6387 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6388 connector->base.id, connector->name); 6389 fallthrough; 6390 case 0: 6391 info->mso_stream_count = 0; 6392 break; 6393 case 1: 6394 info->mso_stream_count = 2; /* 2 or 4 links */ 6395 break; 6396 case 2: 6397 info->mso_stream_count = 4; /* 4 links */ 6398 break; 6399 } 6400 6401 if (!info->mso_stream_count) { 6402 info->mso_pixel_overlap = 0; 6403 return; 6404 } 6405 6406 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6407 if (info->mso_pixel_overlap > 8) { 6408 drm_dbg_kms(connector->dev, 6409 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6410 connector->base.id, connector->name, 6411 info->mso_pixel_overlap); 6412 info->mso_pixel_overlap = 8; 6413 } 6414 6415 drm_dbg_kms(connector->dev, 6416 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6417 connector->base.id, connector->name, 6418 info->mso_stream_count, info->mso_pixel_overlap); 6419 } 6420 6421 static void drm_update_mso(struct drm_connector *connector, 6422 const struct drm_edid *drm_edid) 6423 { 6424 const struct displayid_block *block; 6425 struct displayid_iter iter; 6426 6427 displayid_iter_edid_begin(drm_edid, &iter); 6428 displayid_iter_for_each(block, &iter) { 6429 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6430 drm_parse_vesa_mso_data(connector, block); 6431 } 6432 displayid_iter_end(&iter); 6433 } 6434 6435 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6436 * all of the values which would have been set from EDID 6437 */ 6438 static void drm_reset_display_info(struct drm_connector *connector) 6439 { 6440 struct drm_display_info *info = &connector->display_info; 6441 6442 info->width_mm = 0; 6443 info->height_mm = 0; 6444 6445 info->bpc = 0; 6446 info->color_formats = 0; 6447 info->cea_rev = 0; 6448 info->max_tmds_clock = 0; 6449 info->dvi_dual = false; 6450 info->is_hdmi = false; 6451 info->has_audio = false; 6452 info->has_hdmi_infoframe = false; 6453 info->rgb_quant_range_selectable = false; 6454 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6455 6456 info->edid_hdmi_rgb444_dc_modes = 0; 6457 info->edid_hdmi_ycbcr444_dc_modes = 0; 6458 6459 info->non_desktop = 0; 6460 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6461 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6462 6463 info->mso_stream_count = 0; 6464 info->mso_pixel_overlap = 0; 6465 info->max_dsc_bpp = 0; 6466 6467 kfree(info->vics); 6468 info->vics = NULL; 6469 info->vics_len = 0; 6470 6471 info->quirks = 0; 6472 } 6473 6474 static void update_displayid_info(struct drm_connector *connector, 6475 const struct drm_edid *drm_edid) 6476 { 6477 struct drm_display_info *info = &connector->display_info; 6478 const struct displayid_block *block; 6479 struct displayid_iter iter; 6480 6481 displayid_iter_edid_begin(drm_edid, &iter); 6482 displayid_iter_for_each(block, &iter) { 6483 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6484 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6485 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6486 info->non_desktop = true; 6487 6488 /* 6489 * We're only interested in the base section here, no need to 6490 * iterate further. 6491 */ 6492 break; 6493 } 6494 displayid_iter_end(&iter); 6495 } 6496 6497 static void update_display_info(struct drm_connector *connector, 6498 const struct drm_edid *drm_edid) 6499 { 6500 struct drm_display_info *info = &connector->display_info; 6501 const struct edid *edid; 6502 6503 drm_reset_display_info(connector); 6504 clear_eld(connector); 6505 6506 if (!drm_edid) 6507 return; 6508 6509 edid = drm_edid->edid; 6510 6511 info->quirks = edid_get_quirks(drm_edid); 6512 6513 info->width_mm = edid->width_cm * 10; 6514 info->height_mm = edid->height_cm * 10; 6515 6516 drm_get_monitor_range(connector, drm_edid); 6517 6518 if (edid->revision < 3) 6519 goto out; 6520 6521 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6522 goto out; 6523 6524 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6525 drm_parse_cea_ext(connector, drm_edid); 6526 6527 update_displayid_info(connector, drm_edid); 6528 6529 /* 6530 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6531 * 6532 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6533 * tells us to assume 8 bpc color depth if the EDID doesn't have 6534 * extensions which tell otherwise. 6535 */ 6536 if (info->bpc == 0 && edid->revision == 3 && 6537 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6538 info->bpc = 8; 6539 drm_dbg_kms(connector->dev, 6540 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6541 connector->base.id, connector->name, info->bpc); 6542 } 6543 6544 /* Only defined for 1.4 with digital displays */ 6545 if (edid->revision < 4) 6546 goto out; 6547 6548 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6549 case DRM_EDID_DIGITAL_DEPTH_6: 6550 info->bpc = 6; 6551 break; 6552 case DRM_EDID_DIGITAL_DEPTH_8: 6553 info->bpc = 8; 6554 break; 6555 case DRM_EDID_DIGITAL_DEPTH_10: 6556 info->bpc = 10; 6557 break; 6558 case DRM_EDID_DIGITAL_DEPTH_12: 6559 info->bpc = 12; 6560 break; 6561 case DRM_EDID_DIGITAL_DEPTH_14: 6562 info->bpc = 14; 6563 break; 6564 case DRM_EDID_DIGITAL_DEPTH_16: 6565 info->bpc = 16; 6566 break; 6567 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6568 default: 6569 info->bpc = 0; 6570 break; 6571 } 6572 6573 drm_dbg_kms(connector->dev, 6574 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6575 connector->base.id, connector->name, info->bpc); 6576 6577 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6578 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6579 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6580 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6581 6582 drm_update_mso(connector, drm_edid); 6583 6584 out: 6585 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6586 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6587 connector->base.id, connector->name, 6588 info->non_desktop ? " (redundant quirk)" : ""); 6589 info->non_desktop = true; 6590 } 6591 6592 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6593 info->max_dsc_bpp = 15; 6594 6595 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6596 info->bpc = 6; 6597 6598 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6599 info->bpc = 8; 6600 6601 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6602 info->bpc = 10; 6603 6604 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6605 info->bpc = 12; 6606 6607 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6608 drm_edid_to_eld(connector, drm_edid); 6609 } 6610 6611 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6612 struct displayid_detailed_timings_1 *timings, 6613 bool type_7) 6614 { 6615 struct drm_display_mode *mode; 6616 unsigned pixel_clock = (timings->pixel_clock[0] | 6617 (timings->pixel_clock[1] << 8) | 6618 (timings->pixel_clock[2] << 16)) + 1; 6619 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6620 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6621 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6622 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6623 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6624 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6625 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6626 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6627 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6628 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6629 6630 mode = drm_mode_create(dev); 6631 if (!mode) 6632 return NULL; 6633 6634 /* resolution is kHz for type VII, and 10 kHz for type I */ 6635 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6636 mode->hdisplay = hactive; 6637 mode->hsync_start = mode->hdisplay + hsync; 6638 mode->hsync_end = mode->hsync_start + hsync_width; 6639 mode->htotal = mode->hdisplay + hblank; 6640 6641 mode->vdisplay = vactive; 6642 mode->vsync_start = mode->vdisplay + vsync; 6643 mode->vsync_end = mode->vsync_start + vsync_width; 6644 mode->vtotal = mode->vdisplay + vblank; 6645 6646 mode->flags = 0; 6647 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6648 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6649 mode->type = DRM_MODE_TYPE_DRIVER; 6650 6651 if (timings->flags & 0x80) 6652 mode->type |= DRM_MODE_TYPE_PREFERRED; 6653 drm_mode_set_name(mode); 6654 6655 return mode; 6656 } 6657 6658 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6659 const struct displayid_block *block) 6660 { 6661 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6662 int i; 6663 int num_timings; 6664 struct drm_display_mode *newmode; 6665 int num_modes = 0; 6666 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6667 /* blocks must be multiple of 20 bytes length */ 6668 if (block->num_bytes % 20) 6669 return 0; 6670 6671 num_timings = block->num_bytes / 20; 6672 for (i = 0; i < num_timings; i++) { 6673 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6674 6675 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6676 if (!newmode) 6677 continue; 6678 6679 drm_mode_probed_add(connector, newmode); 6680 num_modes++; 6681 } 6682 return num_modes; 6683 } 6684 6685 static int add_displayid_detailed_modes(struct drm_connector *connector, 6686 const struct drm_edid *drm_edid) 6687 { 6688 const struct displayid_block *block; 6689 struct displayid_iter iter; 6690 int num_modes = 0; 6691 6692 displayid_iter_edid_begin(drm_edid, &iter); 6693 displayid_iter_for_each(block, &iter) { 6694 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6695 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6696 num_modes += add_displayid_detailed_1_modes(connector, block); 6697 } 6698 displayid_iter_end(&iter); 6699 6700 return num_modes; 6701 } 6702 6703 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6704 const struct drm_edid *drm_edid) 6705 { 6706 const struct drm_display_info *info = &connector->display_info; 6707 int num_modes = 0; 6708 6709 if (!drm_edid) 6710 return 0; 6711 6712 /* 6713 * EDID spec says modes should be preferred in this order: 6714 * - preferred detailed mode 6715 * - other detailed modes from base block 6716 * - detailed modes from extension blocks 6717 * - CVT 3-byte code modes 6718 * - standard timing codes 6719 * - established timing codes 6720 * - modes inferred from GTF or CVT range information 6721 * 6722 * We get this pretty much right. 6723 * 6724 * XXX order for additional mode types in extension blocks? 6725 */ 6726 num_modes += add_detailed_modes(connector, drm_edid); 6727 num_modes += add_cvt_modes(connector, drm_edid); 6728 num_modes += add_standard_modes(connector, drm_edid); 6729 num_modes += add_established_modes(connector, drm_edid); 6730 num_modes += add_cea_modes(connector, drm_edid); 6731 num_modes += add_alternate_cea_modes(connector, drm_edid); 6732 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6733 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6734 num_modes += add_inferred_modes(connector, drm_edid); 6735 6736 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6737 edid_fixup_preferred(connector); 6738 6739 return num_modes; 6740 } 6741 6742 static void _drm_update_tile_info(struct drm_connector *connector, 6743 const struct drm_edid *drm_edid); 6744 6745 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6746 const struct drm_edid *drm_edid) 6747 { 6748 struct drm_device *dev = connector->dev; 6749 int ret; 6750 6751 if (connector->edid_blob_ptr) { 6752 const struct edid *old_edid = connector->edid_blob_ptr->data; 6753 6754 if (old_edid) { 6755 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6756 connector->epoch_counter++; 6757 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6758 connector->base.id, connector->name, 6759 connector->epoch_counter); 6760 } 6761 } 6762 } 6763 6764 ret = drm_property_replace_global_blob(dev, 6765 &connector->edid_blob_ptr, 6766 drm_edid ? drm_edid->size : 0, 6767 drm_edid ? drm_edid->edid : NULL, 6768 &connector->base, 6769 dev->mode_config.edid_property); 6770 if (ret) { 6771 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6772 connector->base.id, connector->name, ret); 6773 goto out; 6774 } 6775 6776 ret = drm_object_property_set_value(&connector->base, 6777 dev->mode_config.non_desktop_property, 6778 connector->display_info.non_desktop); 6779 if (ret) { 6780 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6781 connector->base.id, connector->name, ret); 6782 goto out; 6783 } 6784 6785 ret = drm_connector_set_tile_property(connector); 6786 if (ret) { 6787 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6788 connector->base.id, connector->name, ret); 6789 goto out; 6790 } 6791 6792 out: 6793 return ret; 6794 } 6795 6796 /** 6797 * drm_edid_connector_update - Update connector information from EDID 6798 * @connector: Connector 6799 * @drm_edid: EDID 6800 * 6801 * Update the connector display info, ELD, HDR metadata, relevant properties, 6802 * etc. from the passed in EDID. 6803 * 6804 * If EDID is NULL, reset the information. 6805 * 6806 * Must be called before calling drm_edid_connector_add_modes(). 6807 * 6808 * Return: 0 on success, negative error on errors. 6809 */ 6810 int drm_edid_connector_update(struct drm_connector *connector, 6811 const struct drm_edid *drm_edid) 6812 { 6813 update_display_info(connector, drm_edid); 6814 6815 _drm_update_tile_info(connector, drm_edid); 6816 6817 return _drm_edid_connector_property_update(connector, drm_edid); 6818 } 6819 EXPORT_SYMBOL(drm_edid_connector_update); 6820 6821 /** 6822 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6823 * @connector: Connector 6824 * 6825 * Add the modes from the previously updated EDID property to the connector 6826 * probed modes list. 6827 * 6828 * drm_edid_connector_update() must have been called before this to update the 6829 * EDID property. 6830 * 6831 * Return: The number of modes added, or 0 if we couldn't find any. 6832 */ 6833 int drm_edid_connector_add_modes(struct drm_connector *connector) 6834 { 6835 const struct drm_edid *drm_edid = NULL; 6836 int count; 6837 6838 if (connector->edid_blob_ptr) 6839 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6840 connector->edid_blob_ptr->length); 6841 6842 count = _drm_edid_connector_add_modes(connector, drm_edid); 6843 6844 drm_edid_free(drm_edid); 6845 6846 return count; 6847 } 6848 EXPORT_SYMBOL(drm_edid_connector_add_modes); 6849 6850 /** 6851 * drm_connector_update_edid_property - update the edid property of a connector 6852 * @connector: drm connector 6853 * @edid: new value of the edid property 6854 * 6855 * This function creates a new blob modeset object and assigns its id to the 6856 * connector's edid property. 6857 * Since we also parse tile information from EDID's displayID block, we also 6858 * set the connector's tile property here. See drm_connector_set_tile_property() 6859 * for more details. 6860 * 6861 * This function is deprecated. Use drm_edid_connector_update() instead. 6862 * 6863 * Returns: 6864 * Zero on success, negative errno on failure. 6865 */ 6866 int drm_connector_update_edid_property(struct drm_connector *connector, 6867 const struct edid *edid) 6868 { 6869 struct drm_edid drm_edid; 6870 6871 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6872 } 6873 EXPORT_SYMBOL(drm_connector_update_edid_property); 6874 6875 /** 6876 * drm_add_edid_modes - add modes from EDID data, if available 6877 * @connector: connector we're probing 6878 * @edid: EDID data 6879 * 6880 * Add the specified modes to the connector's mode list. Also fills out the 6881 * &drm_display_info structure and ELD in @connector with any information which 6882 * can be derived from the edid. 6883 * 6884 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6885 * 6886 * Return: The number of modes added or 0 if we couldn't find any. 6887 */ 6888 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6889 { 6890 struct drm_edid _drm_edid; 6891 const struct drm_edid *drm_edid; 6892 6893 if (edid && !drm_edid_is_valid(edid)) { 6894 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6895 connector->base.id, connector->name); 6896 edid = NULL; 6897 } 6898 6899 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6900 6901 update_display_info(connector, drm_edid); 6902 6903 return _drm_edid_connector_add_modes(connector, drm_edid); 6904 } 6905 EXPORT_SYMBOL(drm_add_edid_modes); 6906 6907 /** 6908 * drm_add_modes_noedid - add modes for the connectors without EDID 6909 * @connector: connector we're probing 6910 * @hdisplay: the horizontal display limit 6911 * @vdisplay: the vertical display limit 6912 * 6913 * Add the specified modes to the connector's mode list. Only when the 6914 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6915 * 6916 * Return: The number of modes added or 0 if we couldn't find any. 6917 */ 6918 int drm_add_modes_noedid(struct drm_connector *connector, 6919 int hdisplay, int vdisplay) 6920 { 6921 int i, count, num_modes = 0; 6922 struct drm_display_mode *mode; 6923 struct drm_device *dev = connector->dev; 6924 6925 count = ARRAY_SIZE(drm_dmt_modes); 6926 if (hdisplay < 0) 6927 hdisplay = 0; 6928 if (vdisplay < 0) 6929 vdisplay = 0; 6930 6931 for (i = 0; i < count; i++) { 6932 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6933 6934 if (hdisplay && vdisplay) { 6935 /* 6936 * Only when two are valid, they will be used to check 6937 * whether the mode should be added to the mode list of 6938 * the connector. 6939 */ 6940 if (ptr->hdisplay > hdisplay || 6941 ptr->vdisplay > vdisplay) 6942 continue; 6943 } 6944 if (drm_mode_vrefresh(ptr) > 61) 6945 continue; 6946 mode = drm_mode_duplicate(dev, ptr); 6947 if (mode) { 6948 drm_mode_probed_add(connector, mode); 6949 num_modes++; 6950 } 6951 } 6952 return num_modes; 6953 } 6954 EXPORT_SYMBOL(drm_add_modes_noedid); 6955 6956 /** 6957 * drm_set_preferred_mode - Sets the preferred mode of a connector 6958 * @connector: connector whose mode list should be processed 6959 * @hpref: horizontal resolution of preferred mode 6960 * @vpref: vertical resolution of preferred mode 6961 * 6962 * Marks a mode as preferred if it matches the resolution specified by @hpref 6963 * and @vpref. 6964 */ 6965 void drm_set_preferred_mode(struct drm_connector *connector, 6966 int hpref, int vpref) 6967 { 6968 struct drm_display_mode *mode; 6969 6970 list_for_each_entry(mode, &connector->probed_modes, head) { 6971 if (mode->hdisplay == hpref && 6972 mode->vdisplay == vpref) 6973 mode->type |= DRM_MODE_TYPE_PREFERRED; 6974 } 6975 } 6976 EXPORT_SYMBOL(drm_set_preferred_mode); 6977 6978 static bool is_hdmi2_sink(const struct drm_connector *connector) 6979 { 6980 /* 6981 * FIXME: sil-sii8620 doesn't have a connector around when 6982 * we need one, so we have to be prepared for a NULL connector. 6983 */ 6984 if (!connector) 6985 return true; 6986 6987 return connector->display_info.hdmi.scdc.supported || 6988 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6989 } 6990 6991 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6992 const struct drm_display_mode *mode) 6993 { 6994 bool has_hdmi_infoframe = connector ? 6995 connector->display_info.has_hdmi_infoframe : false; 6996 6997 if (!has_hdmi_infoframe) 6998 return 0; 6999 7000 /* No HDMI VIC when signalling 3D video format */ 7001 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7002 return 0; 7003 7004 return drm_match_hdmi_mode(mode); 7005 } 7006 7007 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7008 const struct drm_display_mode *mode) 7009 { 7010 /* 7011 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7012 * we should send its VIC in vendor infoframes, else send the 7013 * VIC in AVI infoframes. Lets check if this mode is present in 7014 * HDMI 1.4b 4K modes 7015 */ 7016 if (drm_mode_hdmi_vic(connector, mode)) 7017 return 0; 7018 7019 return drm_match_cea_mode(mode); 7020 } 7021 7022 /* 7023 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7024 * conform to HDMI 1.4. 7025 * 7026 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7027 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7028 * 7029 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7030 * version. 7031 */ 7032 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7033 { 7034 if (!is_hdmi2_sink(connector) && vic > 64 && 7035 !cta_vdb_has_vic(connector, vic)) 7036 return 0; 7037 7038 return vic; 7039 } 7040 7041 /** 7042 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7043 * data from a DRM display mode 7044 * @frame: HDMI AVI infoframe 7045 * @connector: the connector 7046 * @mode: DRM display mode 7047 * 7048 * Return: 0 on success or a negative error code on failure. 7049 */ 7050 int 7051 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7052 const struct drm_connector *connector, 7053 const struct drm_display_mode *mode) 7054 { 7055 enum hdmi_picture_aspect picture_aspect; 7056 u8 vic, hdmi_vic; 7057 7058 if (!frame || !mode) 7059 return -EINVAL; 7060 7061 hdmi_avi_infoframe_init(frame); 7062 7063 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7064 frame->pixel_repeat = 1; 7065 7066 vic = drm_mode_cea_vic(connector, mode); 7067 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7068 7069 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7070 7071 /* 7072 * As some drivers don't support atomic, we can't use connector state. 7073 * So just initialize the frame with default values, just the same way 7074 * as it's done with other properties here. 7075 */ 7076 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7077 frame->itc = 0; 7078 7079 /* 7080 * Populate picture aspect ratio from either 7081 * user input (if specified) or from the CEA/HDMI mode lists. 7082 */ 7083 picture_aspect = mode->picture_aspect_ratio; 7084 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7085 if (vic) 7086 picture_aspect = drm_get_cea_aspect_ratio(vic); 7087 else if (hdmi_vic) 7088 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7089 } 7090 7091 /* 7092 * The infoframe can't convey anything but none, 4:3 7093 * and 16:9, so if the user has asked for anything else 7094 * we can only satisfy it by specifying the right VIC. 7095 */ 7096 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7097 if (vic) { 7098 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7099 return -EINVAL; 7100 } else if (hdmi_vic) { 7101 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7102 return -EINVAL; 7103 } else { 7104 return -EINVAL; 7105 } 7106 7107 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7108 } 7109 7110 frame->video_code = vic_for_avi_infoframe(connector, vic); 7111 frame->picture_aspect = picture_aspect; 7112 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7113 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7114 7115 return 0; 7116 } 7117 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7118 7119 /** 7120 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7121 * quantization range information 7122 * @frame: HDMI AVI infoframe 7123 * @connector: the connector 7124 * @mode: DRM display mode 7125 * @rgb_quant_range: RGB quantization range (Q) 7126 */ 7127 void 7128 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7129 const struct drm_connector *connector, 7130 const struct drm_display_mode *mode, 7131 enum hdmi_quantization_range rgb_quant_range) 7132 { 7133 const struct drm_display_info *info = &connector->display_info; 7134 7135 /* 7136 * CEA-861: 7137 * "A Source shall not send a non-zero Q value that does not correspond 7138 * to the default RGB Quantization Range for the transmitted Picture 7139 * unless the Sink indicates support for the Q bit in a Video 7140 * Capabilities Data Block." 7141 * 7142 * HDMI 2.0 recommends sending non-zero Q when it does match the 7143 * default RGB quantization range for the mode, even when QS=0. 7144 */ 7145 if (info->rgb_quant_range_selectable || 7146 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7147 frame->quantization_range = rgb_quant_range; 7148 else 7149 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7150 7151 /* 7152 * CEA-861-F: 7153 * "When transmitting any RGB colorimetry, the Source should set the 7154 * YQ-field to match the RGB Quantization Range being transmitted 7155 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7156 * set YQ=1) and the Sink shall ignore the YQ-field." 7157 * 7158 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7159 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7160 * good way to tell which version of CEA-861 the sink supports, so 7161 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7162 * on CEA-861-F. 7163 */ 7164 if (!is_hdmi2_sink(connector) || 7165 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7166 frame->ycc_quantization_range = 7167 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7168 else 7169 frame->ycc_quantization_range = 7170 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7171 } 7172 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7173 7174 static enum hdmi_3d_structure 7175 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7176 { 7177 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7178 7179 switch (layout) { 7180 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7181 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7182 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7183 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7184 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7185 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7186 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7187 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7188 case DRM_MODE_FLAG_3D_L_DEPTH: 7189 return HDMI_3D_STRUCTURE_L_DEPTH; 7190 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7191 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7192 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7193 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7194 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7195 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7196 default: 7197 return HDMI_3D_STRUCTURE_INVALID; 7198 } 7199 } 7200 7201 /** 7202 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7203 * data from a DRM display mode 7204 * @frame: HDMI vendor infoframe 7205 * @connector: the connector 7206 * @mode: DRM display mode 7207 * 7208 * Note that there's is a need to send HDMI vendor infoframes only when using a 7209 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7210 * function will return -EINVAL, error that can be safely ignored. 7211 * 7212 * Return: 0 on success or a negative error code on failure. 7213 */ 7214 int 7215 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7216 const struct drm_connector *connector, 7217 const struct drm_display_mode *mode) 7218 { 7219 /* 7220 * FIXME: sil-sii8620 doesn't have a connector around when 7221 * we need one, so we have to be prepared for a NULL connector. 7222 */ 7223 bool has_hdmi_infoframe = connector ? 7224 connector->display_info.has_hdmi_infoframe : false; 7225 int err; 7226 7227 if (!frame || !mode) 7228 return -EINVAL; 7229 7230 if (!has_hdmi_infoframe) 7231 return -EINVAL; 7232 7233 err = hdmi_vendor_infoframe_init(frame); 7234 if (err < 0) 7235 return err; 7236 7237 /* 7238 * Even if it's not absolutely necessary to send the infoframe 7239 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7240 * know that the sink can handle it. This is based on a 7241 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7242 * have trouble realizing that they should switch from 3D to 2D 7243 * mode if the source simply stops sending the infoframe when 7244 * it wants to switch from 3D to 2D. 7245 */ 7246 frame->vic = drm_mode_hdmi_vic(connector, mode); 7247 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7248 7249 return 0; 7250 } 7251 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7252 7253 static void drm_parse_tiled_block(struct drm_connector *connector, 7254 const struct displayid_block *block) 7255 { 7256 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7257 u16 w, h; 7258 u8 tile_v_loc, tile_h_loc; 7259 u8 num_v_tile, num_h_tile; 7260 struct drm_tile_group *tg; 7261 7262 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7263 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7264 7265 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7266 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7267 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7268 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7269 7270 connector->has_tile = true; 7271 if (tile->tile_cap & 0x80) 7272 connector->tile_is_single_monitor = true; 7273 7274 connector->num_h_tile = num_h_tile + 1; 7275 connector->num_v_tile = num_v_tile + 1; 7276 connector->tile_h_loc = tile_h_loc; 7277 connector->tile_v_loc = tile_v_loc; 7278 connector->tile_h_size = w + 1; 7279 connector->tile_v_size = h + 1; 7280 7281 drm_dbg_kms(connector->dev, 7282 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7283 connector->base.id, connector->name, 7284 tile->tile_cap, 7285 connector->tile_h_size, connector->tile_v_size, 7286 connector->num_h_tile, connector->num_v_tile, 7287 connector->tile_h_loc, connector->tile_v_loc, 7288 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7289 7290 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7291 if (!tg) 7292 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7293 if (!tg) 7294 return; 7295 7296 if (connector->tile_group != tg) { 7297 /* if we haven't got a pointer, 7298 take the reference, drop ref to old tile group */ 7299 if (connector->tile_group) 7300 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7301 connector->tile_group = tg; 7302 } else { 7303 /* if same tile group, then release the ref we just took. */ 7304 drm_mode_put_tile_group(connector->dev, tg); 7305 } 7306 } 7307 7308 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7309 const struct displayid_block *block) 7310 { 7311 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7312 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7313 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7314 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7315 } 7316 7317 static void _drm_update_tile_info(struct drm_connector *connector, 7318 const struct drm_edid *drm_edid) 7319 { 7320 const struct displayid_block *block; 7321 struct displayid_iter iter; 7322 7323 connector->has_tile = false; 7324 7325 displayid_iter_edid_begin(drm_edid, &iter); 7326 displayid_iter_for_each(block, &iter) { 7327 if (displayid_is_tiled_block(&iter, block)) 7328 drm_parse_tiled_block(connector, block); 7329 } 7330 displayid_iter_end(&iter); 7331 7332 if (!connector->has_tile && connector->tile_group) { 7333 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7334 connector->tile_group = NULL; 7335 } 7336 } 7337