1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_scdc_helper.h> 41 42 #include "drm_crtc_internal.h" 43 44 #define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48 #define EDID_EST_TIMINGS 16 49 #define EDID_STD_TIMINGS 8 50 #define EDID_DETAILED_TIMINGS 4 51 52 /* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59 /* First detailed mode wrong, use largest 60Hz mode */ 60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61 /* Reported 135MHz pixel clock is too high, needs adjustment */ 62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63 /* Prefer the largest mode at 75 Hz */ 64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65 /* Detail timing is in cm not mm */ 66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67 /* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71 /* Monitor forgot to set the first detailed is preferred bit. */ 72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 73 /* use +hsync +vsync for detailed mode */ 74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 75 /* Force reduced-blanking timings for detailed modes */ 76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 77 /* Force 8bpc */ 78 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 79 /* Force 12bpc */ 80 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 81 /* Force 6bpc */ 82 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 83 /* Force 10bpc */ 84 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 85 /* Non desktop display (i.e. HMD) */ 86 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 87 88 struct detailed_mode_closure { 89 struct drm_connector *connector; 90 struct edid *edid; 91 bool preferred; 92 u32 quirks; 93 int modes; 94 }; 95 96 #define LEVEL_DMT 0 97 #define LEVEL_GTF 1 98 #define LEVEL_GTF2 2 99 #define LEVEL_CVT 3 100 101 static const struct edid_quirk { 102 char vendor[4]; 103 int product_id; 104 u32 quirks; 105 } edid_quirk_list[] = { 106 /* Acer AL1706 */ 107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Acer F51 */ 109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Unknown Acer */ 111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 118 119 /* Belinea 10 15 55 */ 120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 122 123 /* Envision Peripherals, Inc. EN-7100e */ 124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 125 /* Envision EN2028 */ 126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 127 128 /* Funai Electronics PM36B */ 129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 130 EDID_QUIRK_DETAILED_IN_CM }, 131 132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 134 135 /* LG Philips LCD LP154W01-A5 */ 136 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 137 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 138 139 /* Philips 107p5 CRT */ 140 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 141 142 /* Proview AY765C */ 143 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 144 145 /* Samsung SyncMaster 205BW. Note: irony */ 146 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 147 /* Samsung SyncMaster 22[5-6]BW */ 148 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 149 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 150 151 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 152 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 153 154 /* ViewSonic VA2026w */ 155 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 156 157 /* Medion MD 30217 PG */ 158 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 159 160 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 161 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 162 163 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 164 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 165 166 /* HTC Vive and Vive Pro VR Headsets */ 167 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 168 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 169 170 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 171 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 172 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 173 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 174 175 /* Windows Mixed Reality Headsets */ 176 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 177 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 178 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 179 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 180 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 181 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 182 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 183 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 184 185 /* Sony PlayStation VR Headset */ 186 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 187 }; 188 189 /* 190 * Autogenerated from the DMT spec. 191 * This table is copied from xfree86/modes/xf86EdidModes.c. 192 */ 193 static const struct drm_display_mode drm_dmt_modes[] = { 194 /* 0x01 - 640x350@85Hz */ 195 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 196 736, 832, 0, 350, 382, 385, 445, 0, 197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 198 /* 0x02 - 640x400@85Hz */ 199 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 200 736, 832, 0, 400, 401, 404, 445, 0, 201 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 202 /* 0x03 - 720x400@85Hz */ 203 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 204 828, 936, 0, 400, 401, 404, 446, 0, 205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 206 /* 0x04 - 640x480@60Hz */ 207 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 208 752, 800, 0, 480, 490, 492, 525, 0, 209 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 210 /* 0x05 - 640x480@72Hz */ 211 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 212 704, 832, 0, 480, 489, 492, 520, 0, 213 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 214 /* 0x06 - 640x480@75Hz */ 215 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 216 720, 840, 0, 480, 481, 484, 500, 0, 217 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 218 /* 0x07 - 640x480@85Hz */ 219 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 220 752, 832, 0, 480, 481, 484, 509, 0, 221 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 222 /* 0x08 - 800x600@56Hz */ 223 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 224 896, 1024, 0, 600, 601, 603, 625, 0, 225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 226 /* 0x09 - 800x600@60Hz */ 227 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 228 968, 1056, 0, 600, 601, 605, 628, 0, 229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 230 /* 0x0a - 800x600@72Hz */ 231 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 232 976, 1040, 0, 600, 637, 643, 666, 0, 233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 234 /* 0x0b - 800x600@75Hz */ 235 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 236 896, 1056, 0, 600, 601, 604, 625, 0, 237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 238 /* 0x0c - 800x600@85Hz */ 239 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 240 896, 1048, 0, 600, 601, 604, 631, 0, 241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 242 /* 0x0d - 800x600@120Hz RB */ 243 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 244 880, 960, 0, 600, 603, 607, 636, 0, 245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 246 /* 0x0e - 848x480@60Hz */ 247 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 248 976, 1088, 0, 480, 486, 494, 517, 0, 249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 250 /* 0x0f - 1024x768@43Hz, interlace */ 251 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 252 1208, 1264, 0, 768, 768, 776, 817, 0, 253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 254 DRM_MODE_FLAG_INTERLACE) }, 255 /* 0x10 - 1024x768@60Hz */ 256 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 257 1184, 1344, 0, 768, 771, 777, 806, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 259 /* 0x11 - 1024x768@70Hz */ 260 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 261 1184, 1328, 0, 768, 771, 777, 806, 0, 262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 263 /* 0x12 - 1024x768@75Hz */ 264 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 265 1136, 1312, 0, 768, 769, 772, 800, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 267 /* 0x13 - 1024x768@85Hz */ 268 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 269 1168, 1376, 0, 768, 769, 772, 808, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 271 /* 0x14 - 1024x768@120Hz RB */ 272 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 273 1104, 1184, 0, 768, 771, 775, 813, 0, 274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 275 /* 0x15 - 1152x864@75Hz */ 276 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 277 1344, 1600, 0, 864, 865, 868, 900, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 0x55 - 1280x720@60Hz */ 280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 281 1430, 1650, 0, 720, 725, 730, 750, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 283 /* 0x16 - 1280x768@60Hz RB */ 284 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 285 1360, 1440, 0, 768, 771, 778, 790, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 287 /* 0x17 - 1280x768@60Hz */ 288 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 289 1472, 1664, 0, 768, 771, 778, 798, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 291 /* 0x18 - 1280x768@75Hz */ 292 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 293 1488, 1696, 0, 768, 771, 778, 805, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 295 /* 0x19 - 1280x768@85Hz */ 296 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 297 1496, 1712, 0, 768, 771, 778, 809, 0, 298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 299 /* 0x1a - 1280x768@120Hz RB */ 300 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 301 1360, 1440, 0, 768, 771, 778, 813, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 303 /* 0x1b - 1280x800@60Hz RB */ 304 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 305 1360, 1440, 0, 800, 803, 809, 823, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 307 /* 0x1c - 1280x800@60Hz */ 308 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 309 1480, 1680, 0, 800, 803, 809, 831, 0, 310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 0x1d - 1280x800@75Hz */ 312 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 313 1488, 1696, 0, 800, 803, 809, 838, 0, 314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 0x1e - 1280x800@85Hz */ 316 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 317 1496, 1712, 0, 800, 803, 809, 843, 0, 318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 319 /* 0x1f - 1280x800@120Hz RB */ 320 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 321 1360, 1440, 0, 800, 803, 809, 847, 0, 322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 323 /* 0x20 - 1280x960@60Hz */ 324 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 325 1488, 1800, 0, 960, 961, 964, 1000, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 0x21 - 1280x960@85Hz */ 328 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 329 1504, 1728, 0, 960, 961, 964, 1011, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 331 /* 0x22 - 1280x960@120Hz RB */ 332 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 333 1360, 1440, 0, 960, 963, 967, 1017, 0, 334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 335 /* 0x23 - 1280x1024@60Hz */ 336 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 337 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 339 /* 0x24 - 1280x1024@75Hz */ 340 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 341 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 0x25 - 1280x1024@85Hz */ 344 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 345 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 0x26 - 1280x1024@120Hz RB */ 348 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 349 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 351 /* 0x27 - 1360x768@60Hz */ 352 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 353 1536, 1792, 0, 768, 771, 777, 795, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 355 /* 0x28 - 1360x768@120Hz RB */ 356 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 357 1440, 1520, 0, 768, 771, 776, 813, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 359 /* 0x51 - 1366x768@60Hz */ 360 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 361 1579, 1792, 0, 768, 771, 774, 798, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 363 /* 0x56 - 1366x768@60Hz */ 364 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 365 1436, 1500, 0, 768, 769, 772, 800, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 367 /* 0x29 - 1400x1050@60Hz RB */ 368 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 369 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 371 /* 0x2a - 1400x1050@60Hz */ 372 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 373 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 0x2b - 1400x1050@75Hz */ 376 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 377 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 379 /* 0x2c - 1400x1050@85Hz */ 380 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 381 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 383 /* 0x2d - 1400x1050@120Hz RB */ 384 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 385 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 387 /* 0x2e - 1440x900@60Hz RB */ 388 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 389 1520, 1600, 0, 900, 903, 909, 926, 0, 390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 391 /* 0x2f - 1440x900@60Hz */ 392 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 393 1672, 1904, 0, 900, 903, 909, 934, 0, 394 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 395 /* 0x30 - 1440x900@75Hz */ 396 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 397 1688, 1936, 0, 900, 903, 909, 942, 0, 398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 0x31 - 1440x900@85Hz */ 400 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 401 1696, 1952, 0, 900, 903, 909, 948, 0, 402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 403 /* 0x32 - 1440x900@120Hz RB */ 404 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 405 1520, 1600, 0, 900, 903, 909, 953, 0, 406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 407 /* 0x53 - 1600x900@60Hz */ 408 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 409 1704, 1800, 0, 900, 901, 904, 1000, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 411 /* 0x33 - 1600x1200@60Hz */ 412 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 413 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 0x34 - 1600x1200@65Hz */ 416 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 417 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 419 /* 0x35 - 1600x1200@70Hz */ 420 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 421 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 423 /* 0x36 - 1600x1200@75Hz */ 424 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 425 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 427 /* 0x37 - 1600x1200@85Hz */ 428 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 429 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 0x38 - 1600x1200@120Hz RB */ 432 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 433 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 435 /* 0x39 - 1680x1050@60Hz RB */ 436 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 437 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 439 /* 0x3a - 1680x1050@60Hz */ 440 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 441 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 443 /* 0x3b - 1680x1050@75Hz */ 444 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 445 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 0x3c - 1680x1050@85Hz */ 448 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 449 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 451 /* 0x3d - 1680x1050@120Hz RB */ 452 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 453 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 455 /* 0x3e - 1792x1344@60Hz */ 456 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 457 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 0x3f - 1792x1344@75Hz */ 460 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 461 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 463 /* 0x40 - 1792x1344@120Hz RB */ 464 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 465 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 467 /* 0x41 - 1856x1392@60Hz */ 468 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 469 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 471 /* 0x42 - 1856x1392@75Hz */ 472 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 473 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 475 /* 0x43 - 1856x1392@120Hz RB */ 476 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 477 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 479 /* 0x52 - 1920x1080@60Hz */ 480 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 481 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 483 /* 0x44 - 1920x1200@60Hz RB */ 484 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 485 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 487 /* 0x45 - 1920x1200@60Hz */ 488 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 489 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 491 /* 0x46 - 1920x1200@75Hz */ 492 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 493 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 495 /* 0x47 - 1920x1200@85Hz */ 496 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 497 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 499 /* 0x48 - 1920x1200@120Hz RB */ 500 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 501 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 503 /* 0x49 - 1920x1440@60Hz */ 504 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 505 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 507 /* 0x4a - 1920x1440@75Hz */ 508 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 509 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 510 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 511 /* 0x4b - 1920x1440@120Hz RB */ 512 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 513 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 515 /* 0x54 - 2048x1152@60Hz */ 516 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 517 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 519 /* 0x4c - 2560x1600@60Hz RB */ 520 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 521 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 523 /* 0x4d - 2560x1600@60Hz */ 524 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 525 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 527 /* 0x4e - 2560x1600@75Hz */ 528 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 529 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 531 /* 0x4f - 2560x1600@85Hz */ 532 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 533 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 535 /* 0x50 - 2560x1600@120Hz RB */ 536 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 537 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 538 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 539 /* 0x57 - 4096x2160@60Hz RB */ 540 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 541 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 543 /* 0x58 - 4096x2160@59.94Hz RB */ 544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 545 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 547 }; 548 549 /* 550 * These more or less come from the DMT spec. The 720x400 modes are 551 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 552 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 553 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 554 * mode. 555 * 556 * The DMT modes have been fact-checked; the rest are mild guesses. 557 */ 558 static const struct drm_display_mode edid_est_modes[] = { 559 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 560 968, 1056, 0, 600, 601, 605, 628, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 563 896, 1024, 0, 600, 601, 603, 625, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 565 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 566 720, 840, 0, 480, 481, 484, 500, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 568 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 569 704, 832, 0, 480, 489, 492, 520, 0, 570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 571 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 572 768, 864, 0, 480, 483, 486, 525, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 574 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 575 752, 800, 0, 480, 490, 492, 525, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 577 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 578 846, 900, 0, 400, 421, 423, 449, 0, 579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 580 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 581 846, 900, 0, 400, 412, 414, 449, 0, 582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 583 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 584 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 586 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 587 1136, 1312, 0, 768, 769, 772, 800, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 589 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 590 1184, 1328, 0, 768, 771, 777, 806, 0, 591 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 592 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 593 1184, 1344, 0, 768, 771, 777, 806, 0, 594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 595 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 596 1208, 1264, 0, 768, 768, 776, 817, 0, 597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 598 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 599 928, 1152, 0, 624, 625, 628, 667, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 602 896, 1056, 0, 600, 601, 604, 625, 0, 603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 604 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 605 976, 1040, 0, 600, 637, 643, 666, 0, 606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 607 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 608 1344, 1600, 0, 864, 865, 868, 900, 0, 609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 610 }; 611 612 struct minimode { 613 short w; 614 short h; 615 short r; 616 short rb; 617 }; 618 619 static const struct minimode est3_modes[] = { 620 /* byte 6 */ 621 { 640, 350, 85, 0 }, 622 { 640, 400, 85, 0 }, 623 { 720, 400, 85, 0 }, 624 { 640, 480, 85, 0 }, 625 { 848, 480, 60, 0 }, 626 { 800, 600, 85, 0 }, 627 { 1024, 768, 85, 0 }, 628 { 1152, 864, 75, 0 }, 629 /* byte 7 */ 630 { 1280, 768, 60, 1 }, 631 { 1280, 768, 60, 0 }, 632 { 1280, 768, 75, 0 }, 633 { 1280, 768, 85, 0 }, 634 { 1280, 960, 60, 0 }, 635 { 1280, 960, 85, 0 }, 636 { 1280, 1024, 60, 0 }, 637 { 1280, 1024, 85, 0 }, 638 /* byte 8 */ 639 { 1360, 768, 60, 0 }, 640 { 1440, 900, 60, 1 }, 641 { 1440, 900, 60, 0 }, 642 { 1440, 900, 75, 0 }, 643 { 1440, 900, 85, 0 }, 644 { 1400, 1050, 60, 1 }, 645 { 1400, 1050, 60, 0 }, 646 { 1400, 1050, 75, 0 }, 647 /* byte 9 */ 648 { 1400, 1050, 85, 0 }, 649 { 1680, 1050, 60, 1 }, 650 { 1680, 1050, 60, 0 }, 651 { 1680, 1050, 75, 0 }, 652 { 1680, 1050, 85, 0 }, 653 { 1600, 1200, 60, 0 }, 654 { 1600, 1200, 65, 0 }, 655 { 1600, 1200, 70, 0 }, 656 /* byte 10 */ 657 { 1600, 1200, 75, 0 }, 658 { 1600, 1200, 85, 0 }, 659 { 1792, 1344, 60, 0 }, 660 { 1792, 1344, 75, 0 }, 661 { 1856, 1392, 60, 0 }, 662 { 1856, 1392, 75, 0 }, 663 { 1920, 1200, 60, 1 }, 664 { 1920, 1200, 60, 0 }, 665 /* byte 11 */ 666 { 1920, 1200, 75, 0 }, 667 { 1920, 1200, 85, 0 }, 668 { 1920, 1440, 60, 0 }, 669 { 1920, 1440, 75, 0 }, 670 }; 671 672 static const struct minimode extra_modes[] = { 673 { 1024, 576, 60, 0 }, 674 { 1366, 768, 60, 0 }, 675 { 1600, 900, 60, 0 }, 676 { 1680, 945, 60, 0 }, 677 { 1920, 1080, 60, 0 }, 678 { 2048, 1152, 60, 0 }, 679 { 2048, 1536, 60, 0 }, 680 }; 681 682 /* 683 * Probably taken from CEA-861 spec. 684 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 685 * 686 * Index using the VIC. 687 */ 688 static const struct drm_display_mode edid_cea_modes[] = { 689 /* 0 - dummy, VICs start at 1 */ 690 { }, 691 /* 1 - 640x480@60Hz 4:3 */ 692 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 693 752, 800, 0, 480, 490, 492, 525, 0, 694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 696 /* 2 - 720x480@60Hz 4:3 */ 697 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 698 798, 858, 0, 480, 489, 495, 525, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 701 /* 3 - 720x480@60Hz 16:9 */ 702 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 703 798, 858, 0, 480, 489, 495, 525, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 705 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 706 /* 4 - 1280x720@60Hz 16:9 */ 707 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 708 1430, 1650, 0, 720, 725, 730, 750, 0, 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 711 /* 5 - 1920x1080i@60Hz 16:9 */ 712 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 713 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 715 DRM_MODE_FLAG_INTERLACE), 716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 717 /* 6 - 720(1440)x480i@60Hz 4:3 */ 718 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 719 801, 858, 0, 480, 488, 494, 525, 0, 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 721 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 7 - 720(1440)x480i@60Hz 16:9 */ 724 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 725 801, 858, 0, 480, 488, 494, 525, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 727 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 729 /* 8 - 720(1440)x240@60Hz 4:3 */ 730 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 731 801, 858, 0, 240, 244, 247, 262, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 733 DRM_MODE_FLAG_DBLCLK), 734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 735 /* 9 - 720(1440)x240@60Hz 16:9 */ 736 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 737 801, 858, 0, 240, 244, 247, 262, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 739 DRM_MODE_FLAG_DBLCLK), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 10 - 2880x480i@60Hz 4:3 */ 742 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 743 3204, 3432, 0, 480, 488, 494, 525, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 745 DRM_MODE_FLAG_INTERLACE), 746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 747 /* 11 - 2880x480i@60Hz 16:9 */ 748 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 749 3204, 3432, 0, 480, 488, 494, 525, 0, 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 12 - 2880x240@60Hz 4:3 */ 754 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 755 3204, 3432, 0, 240, 244, 247, 262, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 757 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 758 /* 13 - 2880x240@60Hz 16:9 */ 759 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 760 3204, 3432, 0, 240, 244, 247, 262, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 762 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 763 /* 14 - 1440x480@60Hz 4:3 */ 764 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 765 1596, 1716, 0, 480, 489, 495, 525, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 768 /* 15 - 1440x480@60Hz 16:9 */ 769 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 770 1596, 1716, 0, 480, 489, 495, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 772 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 16 - 1920x1080@60Hz 16:9 */ 774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 775 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 777 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 17 - 720x576@50Hz 4:3 */ 779 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 780 796, 864, 0, 576, 581, 586, 625, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 18 - 720x576@50Hz 16:9 */ 784 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 785 796, 864, 0, 576, 581, 586, 625, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 787 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 19 - 1280x720@50Hz 16:9 */ 789 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 790 1760, 1980, 0, 720, 725, 730, 750, 0, 791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 20 - 1920x1080i@50Hz 16:9 */ 794 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 795 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 797 DRM_MODE_FLAG_INTERLACE), 798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 21 - 720(1440)x576i@50Hz 4:3 */ 800 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 801 795, 864, 0, 576, 580, 586, 625, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 803 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 804 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 22 - 720(1440)x576i@50Hz 16:9 */ 806 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 807 795, 864, 0, 576, 580, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 809 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 811 /* 23 - 720(1440)x288@50Hz 4:3 */ 812 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 813 795, 864, 0, 288, 290, 293, 312, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 815 DRM_MODE_FLAG_DBLCLK), 816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 817 /* 24 - 720(1440)x288@50Hz 16:9 */ 818 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 819 795, 864, 0, 288, 290, 293, 312, 0, 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 821 DRM_MODE_FLAG_DBLCLK), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 25 - 2880x576i@50Hz 4:3 */ 824 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 825 3180, 3456, 0, 576, 580, 586, 625, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 827 DRM_MODE_FLAG_INTERLACE), 828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 829 /* 26 - 2880x576i@50Hz 16:9 */ 830 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 831 3180, 3456, 0, 576, 580, 586, 625, 0, 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 833 DRM_MODE_FLAG_INTERLACE), 834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 27 - 2880x288@50Hz 4:3 */ 836 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 837 3180, 3456, 0, 288, 290, 293, 312, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 839 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 840 /* 28 - 2880x288@50Hz 16:9 */ 841 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 842 3180, 3456, 0, 288, 290, 293, 312, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 845 /* 29 - 1440x576@50Hz 4:3 */ 846 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 847 1592, 1728, 0, 576, 581, 586, 625, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 850 /* 30 - 1440x576@50Hz 16:9 */ 851 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 852 1592, 1728, 0, 576, 581, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 854 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 31 - 1920x1080@50Hz 16:9 */ 856 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 857 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 859 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 860 /* 32 - 1920x1080@24Hz 16:9 */ 861 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 862 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 864 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 33 - 1920x1080@25Hz 16:9 */ 866 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 867 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 869 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 34 - 1920x1080@30Hz 16:9 */ 871 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 872 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 874 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 35 - 2880x480@60Hz 4:3 */ 876 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 877 3192, 3432, 0, 480, 489, 495, 525, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 880 /* 36 - 2880x480@60Hz 16:9 */ 881 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 882 3192, 3432, 0, 480, 489, 495, 525, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 37 - 2880x576@50Hz 4:3 */ 886 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 887 3184, 3456, 0, 576, 581, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 38 - 2880x576@50Hz 16:9 */ 891 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 892 3184, 3456, 0, 576, 581, 586, 625, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 39 - 1920x1080i@50Hz 16:9 */ 896 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 897 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 899 DRM_MODE_FLAG_INTERLACE), 900 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 40 - 1920x1080i@100Hz 16:9 */ 902 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 903 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 905 DRM_MODE_FLAG_INTERLACE), 906 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 41 - 1280x720@100Hz 16:9 */ 908 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 909 1760, 1980, 0, 720, 725, 730, 750, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 911 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 42 - 720x576@100Hz 4:3 */ 913 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 914 796, 864, 0, 576, 581, 586, 625, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 917 /* 43 - 720x576@100Hz 16:9 */ 918 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 919 796, 864, 0, 576, 581, 586, 625, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 44 - 720(1440)x576i@100Hz 4:3 */ 923 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 924 795, 864, 0, 576, 580, 586, 625, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 926 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 927 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 928 /* 45 - 720(1440)x576i@100Hz 16:9 */ 929 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 930 795, 864, 0, 576, 580, 586, 625, 0, 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 46 - 1920x1080i@120Hz 16:9 */ 935 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 936 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 938 DRM_MODE_FLAG_INTERLACE), 939 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 47 - 1280x720@120Hz 16:9 */ 941 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 942 1430, 1650, 0, 720, 725, 730, 750, 0, 943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 944 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 48 - 720x480@120Hz 4:3 */ 946 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 947 798, 858, 0, 480, 489, 495, 525, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 950 /* 49 - 720x480@120Hz 16:9 */ 951 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 952 798, 858, 0, 480, 489, 495, 525, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 954 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 955 /* 50 - 720(1440)x480i@120Hz 4:3 */ 956 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 957 801, 858, 0, 480, 488, 494, 525, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 960 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 961 /* 51 - 720(1440)x480i@120Hz 16:9 */ 962 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 963 801, 858, 0, 480, 488, 494, 525, 0, 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 965 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 967 /* 52 - 720x576@200Hz 4:3 */ 968 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 969 796, 864, 0, 576, 581, 586, 625, 0, 970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 971 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 972 /* 53 - 720x576@200Hz 16:9 */ 973 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 974 796, 864, 0, 576, 581, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 977 /* 54 - 720(1440)x576i@200Hz 4:3 */ 978 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 979 795, 864, 0, 576, 580, 586, 625, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 981 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 982 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 983 /* 55 - 720(1440)x576i@200Hz 16:9 */ 984 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 985 795, 864, 0, 576, 580, 586, 625, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 56 - 720x480@240Hz 4:3 */ 990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 991 798, 858, 0, 480, 489, 495, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 993 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 994 /* 57 - 720x480@240Hz 16:9 */ 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 996 798, 858, 0, 480, 489, 495, 525, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1001 801, 858, 0, 480, 488, 494, 525, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1004 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1005 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1007 801, 858, 0, 480, 488, 494, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 60 - 1280x720@24Hz 16:9 */ 1012 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1013 3080, 3300, 0, 720, 725, 730, 750, 0, 1014 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1015 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1016 /* 61 - 1280x720@25Hz 16:9 */ 1017 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1018 3740, 3960, 0, 720, 725, 730, 750, 0, 1019 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1020 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1021 /* 62 - 1280x720@30Hz 16:9 */ 1022 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1023 3080, 3300, 0, 720, 725, 730, 750, 0, 1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1025 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 63 - 1920x1080@120Hz 16:9 */ 1027 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1028 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1030 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1031 /* 64 - 1920x1080@100Hz 16:9 */ 1032 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1033 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1034 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1035 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 65 - 1280x720@24Hz 64:27 */ 1037 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1038 3080, 3300, 0, 720, 725, 730, 750, 0, 1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1040 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1041 /* 66 - 1280x720@25Hz 64:27 */ 1042 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1043 3740, 3960, 0, 720, 725, 730, 750, 0, 1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1045 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1046 /* 67 - 1280x720@30Hz 64:27 */ 1047 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1048 3080, 3300, 0, 720, 725, 730, 750, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1050 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1051 /* 68 - 1280x720@50Hz 64:27 */ 1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1053 1760, 1980, 0, 720, 725, 730, 750, 0, 1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1055 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1056 /* 69 - 1280x720@60Hz 64:27 */ 1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1058 1430, 1650, 0, 720, 725, 730, 750, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1060 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1061 /* 70 - 1280x720@100Hz 64:27 */ 1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1063 1760, 1980, 0, 720, 725, 730, 750, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1066 /* 71 - 1280x720@120Hz 64:27 */ 1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1068 1430, 1650, 0, 720, 725, 730, 750, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1071 /* 72 - 1920x1080@24Hz 64:27 */ 1072 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1073 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1076 /* 73 - 1920x1080@25Hz 64:27 */ 1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1078 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1081 /* 74 - 1920x1080@30Hz 64:27 */ 1082 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1083 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1086 /* 75 - 1920x1080@50Hz 64:27 */ 1087 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1088 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 76 - 1920x1080@60Hz 64:27 */ 1092 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1093 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 77 - 1920x1080@100Hz 64:27 */ 1097 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1098 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 78 - 1920x1080@120Hz 64:27 */ 1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1103 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 79 - 1680x720@24Hz 64:27 */ 1107 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1108 3080, 3300, 0, 720, 725, 730, 750, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 80 - 1680x720@25Hz 64:27 */ 1112 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1113 2948, 3168, 0, 720, 725, 730, 750, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 81 - 1680x720@30Hz 64:27 */ 1117 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1118 2420, 2640, 0, 720, 725, 730, 750, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 82 - 1680x720@50Hz 64:27 */ 1122 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1123 1980, 2200, 0, 720, 725, 730, 750, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 83 - 1680x720@60Hz 64:27 */ 1127 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1128 1980, 2200, 0, 720, 725, 730, 750, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 84 - 1680x720@100Hz 64:27 */ 1132 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1133 1780, 2000, 0, 720, 725, 730, 825, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 85 - 1680x720@120Hz 64:27 */ 1137 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1138 1780, 2000, 0, 720, 725, 730, 825, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 86 - 2560x1080@24Hz 64:27 */ 1142 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1143 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 87 - 2560x1080@25Hz 64:27 */ 1147 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1148 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 88 - 2560x1080@30Hz 64:27 */ 1152 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1153 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 89 - 2560x1080@50Hz 64:27 */ 1157 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1158 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 90 - 2560x1080@60Hz 64:27 */ 1162 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1163 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 91 - 2560x1080@100Hz 64:27 */ 1167 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1168 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 92 - 2560x1080@120Hz 64:27 */ 1172 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1173 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 93 - 3840x2160@24Hz 16:9 */ 1177 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1178 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1181 /* 94 - 3840x2160@25Hz 16:9 */ 1182 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1183 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1186 /* 95 - 3840x2160@30Hz 16:9 */ 1187 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1188 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1191 /* 96 - 3840x2160@50Hz 16:9 */ 1192 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1193 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1196 /* 97 - 3840x2160@60Hz 16:9 */ 1197 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1198 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1201 /* 98 - 4096x2160@24Hz 256:135 */ 1202 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1203 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1206 /* 99 - 4096x2160@25Hz 256:135 */ 1207 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1208 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1211 /* 100 - 4096x2160@30Hz 256:135 */ 1212 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1213 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1216 /* 101 - 4096x2160@50Hz 256:135 */ 1217 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1218 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1221 /* 102 - 4096x2160@60Hz 256:135 */ 1222 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1223 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1226 /* 103 - 3840x2160@24Hz 64:27 */ 1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1228 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1231 /* 104 - 3840x2160@25Hz 64:27 */ 1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1236 /* 105 - 3840x2160@30Hz 64:27 */ 1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1241 /* 106 - 3840x2160@50Hz 64:27 */ 1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1243 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1246 /* 107 - 3840x2160@60Hz 64:27 */ 1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1248 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1251 }; 1252 1253 /* 1254 * HDMI 1.4 4k modes. Index using the VIC. 1255 */ 1256 static const struct drm_display_mode edid_4k_modes[] = { 1257 /* 0 - dummy, VICs start at 1 */ 1258 { }, 1259 /* 1 - 3840x2160@30Hz */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1261 3840, 4016, 4104, 4400, 0, 1262 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .vrefresh = 30, }, 1265 /* 2 - 3840x2160@25Hz */ 1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1267 3840, 4896, 4984, 5280, 0, 1268 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .vrefresh = 25, }, 1271 /* 3 - 3840x2160@24Hz */ 1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1273 3840, 5116, 5204, 5500, 0, 1274 2160, 2168, 2178, 2250, 0, 1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1276 .vrefresh = 24, }, 1277 /* 4 - 4096x2160@24Hz (SMPTE) */ 1278 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1279 4096, 5116, 5204, 5500, 0, 1280 2160, 2168, 2178, 2250, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .vrefresh = 24, }, 1283 }; 1284 1285 /*** DDC fetch and block validation ***/ 1286 1287 static const u8 edid_header[] = { 1288 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1289 }; 1290 1291 /** 1292 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1293 * @raw_edid: pointer to raw base EDID block 1294 * 1295 * Sanity check the header of the base EDID block. 1296 * 1297 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1298 */ 1299 int drm_edid_header_is_valid(const u8 *raw_edid) 1300 { 1301 int i, score = 0; 1302 1303 for (i = 0; i < sizeof(edid_header); i++) 1304 if (raw_edid[i] == edid_header[i]) 1305 score++; 1306 1307 return score; 1308 } 1309 EXPORT_SYMBOL(drm_edid_header_is_valid); 1310 1311 static int edid_fixup __read_mostly = 6; 1312 module_param_named(edid_fixup, edid_fixup, int, 0400); 1313 MODULE_PARM_DESC(edid_fixup, 1314 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1315 1316 static void drm_get_displayid(struct drm_connector *connector, 1317 struct edid *edid); 1318 1319 static int drm_edid_block_checksum(const u8 *raw_edid) 1320 { 1321 int i; 1322 u8 csum = 0; 1323 for (i = 0; i < EDID_LENGTH; i++) 1324 csum += raw_edid[i]; 1325 1326 return csum; 1327 } 1328 1329 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1330 { 1331 if (memchr_inv(in_edid, 0, length)) 1332 return false; 1333 1334 return true; 1335 } 1336 1337 /** 1338 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1339 * @raw_edid: pointer to raw EDID block 1340 * @block: type of block to validate (0 for base, extension otherwise) 1341 * @print_bad_edid: if true, dump bad EDID blocks to the console 1342 * @edid_corrupt: if true, the header or checksum is invalid 1343 * 1344 * Validate a base or extension EDID block and optionally dump bad blocks to 1345 * the console. 1346 * 1347 * Return: True if the block is valid, false otherwise. 1348 */ 1349 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1350 bool *edid_corrupt) 1351 { 1352 u8 csum; 1353 struct edid *edid = (struct edid *)raw_edid; 1354 1355 if (WARN_ON(!raw_edid)) 1356 return false; 1357 1358 if (edid_fixup > 8 || edid_fixup < 0) 1359 edid_fixup = 6; 1360 1361 if (block == 0) { 1362 int score = drm_edid_header_is_valid(raw_edid); 1363 if (score == 8) { 1364 if (edid_corrupt) 1365 *edid_corrupt = false; 1366 } else if (score >= edid_fixup) { 1367 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1368 * The corrupt flag needs to be set here otherwise, the 1369 * fix-up code here will correct the problem, the 1370 * checksum is correct and the test fails 1371 */ 1372 if (edid_corrupt) 1373 *edid_corrupt = true; 1374 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1375 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1376 } else { 1377 if (edid_corrupt) 1378 *edid_corrupt = true; 1379 goto bad; 1380 } 1381 } 1382 1383 csum = drm_edid_block_checksum(raw_edid); 1384 if (csum) { 1385 if (edid_corrupt) 1386 *edid_corrupt = true; 1387 1388 /* allow CEA to slide through, switches mangle this */ 1389 if (raw_edid[0] == CEA_EXT) { 1390 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1391 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1392 } else { 1393 if (print_bad_edid) 1394 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1395 1396 goto bad; 1397 } 1398 } 1399 1400 /* per-block-type checks */ 1401 switch (raw_edid[0]) { 1402 case 0: /* base */ 1403 if (edid->version != 1) { 1404 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1405 goto bad; 1406 } 1407 1408 if (edid->revision > 4) 1409 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1410 break; 1411 1412 default: 1413 break; 1414 } 1415 1416 return true; 1417 1418 bad: 1419 if (print_bad_edid) { 1420 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1421 pr_notice("EDID block is all zeroes\n"); 1422 } else { 1423 pr_notice("Raw EDID:\n"); 1424 print_hex_dump(KERN_NOTICE, 1425 " \t", DUMP_PREFIX_NONE, 16, 1, 1426 raw_edid, EDID_LENGTH, false); 1427 } 1428 } 1429 return false; 1430 } 1431 EXPORT_SYMBOL(drm_edid_block_valid); 1432 1433 /** 1434 * drm_edid_is_valid - sanity check EDID data 1435 * @edid: EDID data 1436 * 1437 * Sanity-check an entire EDID record (including extensions) 1438 * 1439 * Return: True if the EDID data is valid, false otherwise. 1440 */ 1441 bool drm_edid_is_valid(struct edid *edid) 1442 { 1443 int i; 1444 u8 *raw = (u8 *)edid; 1445 1446 if (!edid) 1447 return false; 1448 1449 for (i = 0; i <= edid->extensions; i++) 1450 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1451 return false; 1452 1453 return true; 1454 } 1455 EXPORT_SYMBOL(drm_edid_is_valid); 1456 1457 #define DDC_SEGMENT_ADDR 0x30 1458 /** 1459 * drm_do_probe_ddc_edid() - get EDID information via I2C 1460 * @data: I2C device adapter 1461 * @buf: EDID data buffer to be filled 1462 * @block: 128 byte EDID block to start fetching from 1463 * @len: EDID data buffer length to fetch 1464 * 1465 * Try to fetch EDID information by calling I2C driver functions. 1466 * 1467 * Return: 0 on success or -1 on failure. 1468 */ 1469 static int 1470 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1471 { 1472 struct i2c_adapter *adapter = data; 1473 unsigned char start = block * EDID_LENGTH; 1474 unsigned char segment = block >> 1; 1475 unsigned char xfers = segment ? 3 : 2; 1476 int ret, retries = 5; 1477 1478 /* 1479 * The core I2C driver will automatically retry the transfer if the 1480 * adapter reports EAGAIN. However, we find that bit-banging transfers 1481 * are susceptible to errors under a heavily loaded machine and 1482 * generate spurious NAKs and timeouts. Retrying the transfer 1483 * of the individual block a few times seems to overcome this. 1484 */ 1485 do { 1486 struct i2c_msg msgs[] = { 1487 { 1488 .addr = DDC_SEGMENT_ADDR, 1489 .flags = 0, 1490 .len = 1, 1491 .buf = &segment, 1492 }, { 1493 .addr = DDC_ADDR, 1494 .flags = 0, 1495 .len = 1, 1496 .buf = &start, 1497 }, { 1498 .addr = DDC_ADDR, 1499 .flags = I2C_M_RD, 1500 .len = len, 1501 .buf = buf, 1502 } 1503 }; 1504 1505 /* 1506 * Avoid sending the segment addr to not upset non-compliant 1507 * DDC monitors. 1508 */ 1509 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1510 1511 if (ret == -ENXIO) { 1512 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1513 adapter->name); 1514 break; 1515 } 1516 } while (ret != xfers && --retries); 1517 1518 return ret == xfers ? 0 : -1; 1519 } 1520 1521 static void connector_bad_edid(struct drm_connector *connector, 1522 u8 *edid, int num_blocks) 1523 { 1524 int i; 1525 1526 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1527 return; 1528 1529 dev_warn(connector->dev->dev, 1530 "%s: EDID is invalid:\n", 1531 connector->name); 1532 for (i = 0; i < num_blocks; i++) { 1533 u8 *block = edid + i * EDID_LENGTH; 1534 char prefix[20]; 1535 1536 if (drm_edid_is_zero(block, EDID_LENGTH)) 1537 sprintf(prefix, "\t[%02x] ZERO ", i); 1538 else if (!drm_edid_block_valid(block, i, false, NULL)) 1539 sprintf(prefix, "\t[%02x] BAD ", i); 1540 else 1541 sprintf(prefix, "\t[%02x] GOOD ", i); 1542 1543 print_hex_dump(KERN_WARNING, 1544 prefix, DUMP_PREFIX_NONE, 16, 1, 1545 block, EDID_LENGTH, false); 1546 } 1547 } 1548 1549 /** 1550 * drm_do_get_edid - get EDID data using a custom EDID block read function 1551 * @connector: connector we're probing 1552 * @get_edid_block: EDID block read function 1553 * @data: private data passed to the block read function 1554 * 1555 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1556 * exposes a different interface to read EDID blocks this function can be used 1557 * to get EDID data using a custom block read function. 1558 * 1559 * As in the general case the DDC bus is accessible by the kernel at the I2C 1560 * level, drivers must make all reasonable efforts to expose it as an I2C 1561 * adapter and use drm_get_edid() instead of abusing this function. 1562 * 1563 * The EDID may be overridden using debugfs override_edid or firmare EDID 1564 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1565 * order. Having either of them bypasses actual EDID reads. 1566 * 1567 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1568 */ 1569 struct edid *drm_do_get_edid(struct drm_connector *connector, 1570 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1571 size_t len), 1572 void *data) 1573 { 1574 int i, j = 0, valid_extensions = 0; 1575 u8 *edid, *new; 1576 struct edid *override = NULL; 1577 1578 if (connector->override_edid) 1579 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1580 1581 if (!override) 1582 override = drm_load_edid_firmware(connector); 1583 1584 if (!IS_ERR_OR_NULL(override)) 1585 return override; 1586 1587 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1588 return NULL; 1589 1590 /* base block fetch */ 1591 for (i = 0; i < 4; i++) { 1592 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1593 goto out; 1594 if (drm_edid_block_valid(edid, 0, false, 1595 &connector->edid_corrupt)) 1596 break; 1597 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1598 connector->null_edid_counter++; 1599 goto carp; 1600 } 1601 } 1602 if (i == 4) 1603 goto carp; 1604 1605 /* if there's no extensions, we're done */ 1606 valid_extensions = edid[0x7e]; 1607 if (valid_extensions == 0) 1608 return (struct edid *)edid; 1609 1610 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1611 if (!new) 1612 goto out; 1613 edid = new; 1614 1615 for (j = 1; j <= edid[0x7e]; j++) { 1616 u8 *block = edid + j * EDID_LENGTH; 1617 1618 for (i = 0; i < 4; i++) { 1619 if (get_edid_block(data, block, j, EDID_LENGTH)) 1620 goto out; 1621 if (drm_edid_block_valid(block, j, false, NULL)) 1622 break; 1623 } 1624 1625 if (i == 4) 1626 valid_extensions--; 1627 } 1628 1629 if (valid_extensions != edid[0x7e]) { 1630 u8 *base; 1631 1632 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1633 1634 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1635 edid[0x7e] = valid_extensions; 1636 1637 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1638 GFP_KERNEL); 1639 if (!new) 1640 goto out; 1641 1642 base = new; 1643 for (i = 0; i <= edid[0x7e]; i++) { 1644 u8 *block = edid + i * EDID_LENGTH; 1645 1646 if (!drm_edid_block_valid(block, i, false, NULL)) 1647 continue; 1648 1649 memcpy(base, block, EDID_LENGTH); 1650 base += EDID_LENGTH; 1651 } 1652 1653 kfree(edid); 1654 edid = new; 1655 } 1656 1657 return (struct edid *)edid; 1658 1659 carp: 1660 connector_bad_edid(connector, edid, 1); 1661 out: 1662 kfree(edid); 1663 return NULL; 1664 } 1665 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1666 1667 /** 1668 * drm_probe_ddc() - probe DDC presence 1669 * @adapter: I2C adapter to probe 1670 * 1671 * Return: True on success, false on failure. 1672 */ 1673 bool 1674 drm_probe_ddc(struct i2c_adapter *adapter) 1675 { 1676 unsigned char out; 1677 1678 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1679 } 1680 EXPORT_SYMBOL(drm_probe_ddc); 1681 1682 /** 1683 * drm_get_edid - get EDID data, if available 1684 * @connector: connector we're probing 1685 * @adapter: I2C adapter to use for DDC 1686 * 1687 * Poke the given I2C channel to grab EDID data if possible. If found, 1688 * attach it to the connector. 1689 * 1690 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1691 */ 1692 struct edid *drm_get_edid(struct drm_connector *connector, 1693 struct i2c_adapter *adapter) 1694 { 1695 struct edid *edid; 1696 1697 if (connector->force == DRM_FORCE_OFF) 1698 return NULL; 1699 1700 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1701 return NULL; 1702 1703 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1704 if (edid) 1705 drm_get_displayid(connector, edid); 1706 return edid; 1707 } 1708 EXPORT_SYMBOL(drm_get_edid); 1709 1710 /** 1711 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1712 * @connector: connector we're probing 1713 * @adapter: I2C adapter to use for DDC 1714 * 1715 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1716 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1717 * switch DDC to the GPU which is retrieving EDID. 1718 * 1719 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1720 */ 1721 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1722 struct i2c_adapter *adapter) 1723 { 1724 struct pci_dev *pdev = connector->dev->pdev; 1725 struct edid *edid; 1726 1727 vga_switcheroo_lock_ddc(pdev); 1728 edid = drm_get_edid(connector, adapter); 1729 vga_switcheroo_unlock_ddc(pdev); 1730 1731 return edid; 1732 } 1733 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1734 1735 /** 1736 * drm_edid_duplicate - duplicate an EDID and the extensions 1737 * @edid: EDID to duplicate 1738 * 1739 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1740 */ 1741 struct edid *drm_edid_duplicate(const struct edid *edid) 1742 { 1743 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1744 } 1745 EXPORT_SYMBOL(drm_edid_duplicate); 1746 1747 /*** EDID parsing ***/ 1748 1749 /** 1750 * edid_vendor - match a string against EDID's obfuscated vendor field 1751 * @edid: EDID to match 1752 * @vendor: vendor string 1753 * 1754 * Returns true if @vendor is in @edid, false otherwise 1755 */ 1756 static bool edid_vendor(const struct edid *edid, const char *vendor) 1757 { 1758 char edid_vendor[3]; 1759 1760 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1761 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1762 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1763 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1764 1765 return !strncmp(edid_vendor, vendor, 3); 1766 } 1767 1768 /** 1769 * edid_get_quirks - return quirk flags for a given EDID 1770 * @edid: EDID to process 1771 * 1772 * This tells subsequent routines what fixes they need to apply. 1773 */ 1774 static u32 edid_get_quirks(const struct edid *edid) 1775 { 1776 const struct edid_quirk *quirk; 1777 int i; 1778 1779 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1780 quirk = &edid_quirk_list[i]; 1781 1782 if (edid_vendor(edid, quirk->vendor) && 1783 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1784 return quirk->quirks; 1785 } 1786 1787 return 0; 1788 } 1789 1790 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1791 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1792 1793 /** 1794 * edid_fixup_preferred - set preferred modes based on quirk list 1795 * @connector: has mode list to fix up 1796 * @quirks: quirks list 1797 * 1798 * Walk the mode list for @connector, clearing the preferred status 1799 * on existing modes and setting it anew for the right mode ala @quirks. 1800 */ 1801 static void edid_fixup_preferred(struct drm_connector *connector, 1802 u32 quirks) 1803 { 1804 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1805 int target_refresh = 0; 1806 int cur_vrefresh, preferred_vrefresh; 1807 1808 if (list_empty(&connector->probed_modes)) 1809 return; 1810 1811 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1812 target_refresh = 60; 1813 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1814 target_refresh = 75; 1815 1816 preferred_mode = list_first_entry(&connector->probed_modes, 1817 struct drm_display_mode, head); 1818 1819 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1820 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1821 1822 if (cur_mode == preferred_mode) 1823 continue; 1824 1825 /* Largest mode is preferred */ 1826 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1827 preferred_mode = cur_mode; 1828 1829 cur_vrefresh = cur_mode->vrefresh ? 1830 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1831 preferred_vrefresh = preferred_mode->vrefresh ? 1832 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1833 /* At a given size, try to get closest to target refresh */ 1834 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1835 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1836 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1837 preferred_mode = cur_mode; 1838 } 1839 } 1840 1841 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1842 } 1843 1844 static bool 1845 mode_is_rb(const struct drm_display_mode *mode) 1846 { 1847 return (mode->htotal - mode->hdisplay == 160) && 1848 (mode->hsync_end - mode->hdisplay == 80) && 1849 (mode->hsync_end - mode->hsync_start == 32) && 1850 (mode->vsync_start - mode->vdisplay == 3); 1851 } 1852 1853 /* 1854 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1855 * @dev: Device to duplicate against 1856 * @hsize: Mode width 1857 * @vsize: Mode height 1858 * @fresh: Mode refresh rate 1859 * @rb: Mode reduced-blanking-ness 1860 * 1861 * Walk the DMT mode list looking for a match for the given parameters. 1862 * 1863 * Return: A newly allocated copy of the mode, or NULL if not found. 1864 */ 1865 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1866 int hsize, int vsize, int fresh, 1867 bool rb) 1868 { 1869 int i; 1870 1871 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1872 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1873 if (hsize != ptr->hdisplay) 1874 continue; 1875 if (vsize != ptr->vdisplay) 1876 continue; 1877 if (fresh != drm_mode_vrefresh(ptr)) 1878 continue; 1879 if (rb != mode_is_rb(ptr)) 1880 continue; 1881 1882 return drm_mode_duplicate(dev, ptr); 1883 } 1884 1885 return NULL; 1886 } 1887 EXPORT_SYMBOL(drm_mode_find_dmt); 1888 1889 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1890 1891 static void 1892 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1893 { 1894 int i, n = 0; 1895 u8 d = ext[0x02]; 1896 u8 *det_base = ext + d; 1897 1898 n = (127 - d) / 18; 1899 for (i = 0; i < n; i++) 1900 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1901 } 1902 1903 static void 1904 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1905 { 1906 unsigned int i, n = min((int)ext[0x02], 6); 1907 u8 *det_base = ext + 5; 1908 1909 if (ext[0x01] != 1) 1910 return; /* unknown version */ 1911 1912 for (i = 0; i < n; i++) 1913 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1914 } 1915 1916 static void 1917 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1918 { 1919 int i; 1920 struct edid *edid = (struct edid *)raw_edid; 1921 1922 if (edid == NULL) 1923 return; 1924 1925 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1926 cb(&(edid->detailed_timings[i]), closure); 1927 1928 for (i = 1; i <= raw_edid[0x7e]; i++) { 1929 u8 *ext = raw_edid + (i * EDID_LENGTH); 1930 switch (*ext) { 1931 case CEA_EXT: 1932 cea_for_each_detailed_block(ext, cb, closure); 1933 break; 1934 case VTB_EXT: 1935 vtb_for_each_detailed_block(ext, cb, closure); 1936 break; 1937 default: 1938 break; 1939 } 1940 } 1941 } 1942 1943 static void 1944 is_rb(struct detailed_timing *t, void *data) 1945 { 1946 u8 *r = (u8 *)t; 1947 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1948 if (r[15] & 0x10) 1949 *(bool *)data = true; 1950 } 1951 1952 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1953 static bool 1954 drm_monitor_supports_rb(struct edid *edid) 1955 { 1956 if (edid->revision >= 4) { 1957 bool ret = false; 1958 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1959 return ret; 1960 } 1961 1962 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1963 } 1964 1965 static void 1966 find_gtf2(struct detailed_timing *t, void *data) 1967 { 1968 u8 *r = (u8 *)t; 1969 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1970 *(u8 **)data = r; 1971 } 1972 1973 /* Secondary GTF curve kicks in above some break frequency */ 1974 static int 1975 drm_gtf2_hbreak(struct edid *edid) 1976 { 1977 u8 *r = NULL; 1978 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1979 return r ? (r[12] * 2) : 0; 1980 } 1981 1982 static int 1983 drm_gtf2_2c(struct edid *edid) 1984 { 1985 u8 *r = NULL; 1986 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1987 return r ? r[13] : 0; 1988 } 1989 1990 static int 1991 drm_gtf2_m(struct edid *edid) 1992 { 1993 u8 *r = NULL; 1994 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1995 return r ? (r[15] << 8) + r[14] : 0; 1996 } 1997 1998 static int 1999 drm_gtf2_k(struct edid *edid) 2000 { 2001 u8 *r = NULL; 2002 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2003 return r ? r[16] : 0; 2004 } 2005 2006 static int 2007 drm_gtf2_2j(struct edid *edid) 2008 { 2009 u8 *r = NULL; 2010 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2011 return r ? r[17] : 0; 2012 } 2013 2014 /** 2015 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2016 * @edid: EDID block to scan 2017 */ 2018 static int standard_timing_level(struct edid *edid) 2019 { 2020 if (edid->revision >= 2) { 2021 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2022 return LEVEL_CVT; 2023 if (drm_gtf2_hbreak(edid)) 2024 return LEVEL_GTF2; 2025 return LEVEL_GTF; 2026 } 2027 return LEVEL_DMT; 2028 } 2029 2030 /* 2031 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2032 * monitors fill with ascii space (0x20) instead. 2033 */ 2034 static int 2035 bad_std_timing(u8 a, u8 b) 2036 { 2037 return (a == 0x00 && b == 0x00) || 2038 (a == 0x01 && b == 0x01) || 2039 (a == 0x20 && b == 0x20); 2040 } 2041 2042 /** 2043 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2044 * @connector: connector of for the EDID block 2045 * @edid: EDID block to scan 2046 * @t: standard timing params 2047 * 2048 * Take the standard timing params (in this case width, aspect, and refresh) 2049 * and convert them into a real mode using CVT/GTF/DMT. 2050 */ 2051 static struct drm_display_mode * 2052 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2053 struct std_timing *t) 2054 { 2055 struct drm_device *dev = connector->dev; 2056 struct drm_display_mode *m, *mode = NULL; 2057 int hsize, vsize; 2058 int vrefresh_rate; 2059 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2060 >> EDID_TIMING_ASPECT_SHIFT; 2061 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2062 >> EDID_TIMING_VFREQ_SHIFT; 2063 int timing_level = standard_timing_level(edid); 2064 2065 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2066 return NULL; 2067 2068 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2069 hsize = t->hsize * 8 + 248; 2070 /* vrefresh_rate = vfreq + 60 */ 2071 vrefresh_rate = vfreq + 60; 2072 /* the vdisplay is calculated based on the aspect ratio */ 2073 if (aspect_ratio == 0) { 2074 if (edid->revision < 3) 2075 vsize = hsize; 2076 else 2077 vsize = (hsize * 10) / 16; 2078 } else if (aspect_ratio == 1) 2079 vsize = (hsize * 3) / 4; 2080 else if (aspect_ratio == 2) 2081 vsize = (hsize * 4) / 5; 2082 else 2083 vsize = (hsize * 9) / 16; 2084 2085 /* HDTV hack, part 1 */ 2086 if (vrefresh_rate == 60 && 2087 ((hsize == 1360 && vsize == 765) || 2088 (hsize == 1368 && vsize == 769))) { 2089 hsize = 1366; 2090 vsize = 768; 2091 } 2092 2093 /* 2094 * If this connector already has a mode for this size and refresh 2095 * rate (because it came from detailed or CVT info), use that 2096 * instead. This way we don't have to guess at interlace or 2097 * reduced blanking. 2098 */ 2099 list_for_each_entry(m, &connector->probed_modes, head) 2100 if (m->hdisplay == hsize && m->vdisplay == vsize && 2101 drm_mode_vrefresh(m) == vrefresh_rate) 2102 return NULL; 2103 2104 /* HDTV hack, part 2 */ 2105 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2106 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2107 false); 2108 if (!mode) 2109 return NULL; 2110 mode->hdisplay = 1366; 2111 mode->hsync_start = mode->hsync_start - 1; 2112 mode->hsync_end = mode->hsync_end - 1; 2113 return mode; 2114 } 2115 2116 /* check whether it can be found in default mode table */ 2117 if (drm_monitor_supports_rb(edid)) { 2118 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2119 true); 2120 if (mode) 2121 return mode; 2122 } 2123 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2124 if (mode) 2125 return mode; 2126 2127 /* okay, generate it */ 2128 switch (timing_level) { 2129 case LEVEL_DMT: 2130 break; 2131 case LEVEL_GTF: 2132 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2133 break; 2134 case LEVEL_GTF2: 2135 /* 2136 * This is potentially wrong if there's ever a monitor with 2137 * more than one ranges section, each claiming a different 2138 * secondary GTF curve. Please don't do that. 2139 */ 2140 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2141 if (!mode) 2142 return NULL; 2143 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2144 drm_mode_destroy(dev, mode); 2145 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2146 vrefresh_rate, 0, 0, 2147 drm_gtf2_m(edid), 2148 drm_gtf2_2c(edid), 2149 drm_gtf2_k(edid), 2150 drm_gtf2_2j(edid)); 2151 } 2152 break; 2153 case LEVEL_CVT: 2154 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2155 false); 2156 break; 2157 } 2158 return mode; 2159 } 2160 2161 /* 2162 * EDID is delightfully ambiguous about how interlaced modes are to be 2163 * encoded. Our internal representation is of frame height, but some 2164 * HDTV detailed timings are encoded as field height. 2165 * 2166 * The format list here is from CEA, in frame size. Technically we 2167 * should be checking refresh rate too. Whatever. 2168 */ 2169 static void 2170 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2171 struct detailed_pixel_timing *pt) 2172 { 2173 int i; 2174 static const struct { 2175 int w, h; 2176 } cea_interlaced[] = { 2177 { 1920, 1080 }, 2178 { 720, 480 }, 2179 { 1440, 480 }, 2180 { 2880, 480 }, 2181 { 720, 576 }, 2182 { 1440, 576 }, 2183 { 2880, 576 }, 2184 }; 2185 2186 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2187 return; 2188 2189 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2190 if ((mode->hdisplay == cea_interlaced[i].w) && 2191 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2192 mode->vdisplay *= 2; 2193 mode->vsync_start *= 2; 2194 mode->vsync_end *= 2; 2195 mode->vtotal *= 2; 2196 mode->vtotal |= 1; 2197 } 2198 } 2199 2200 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2201 } 2202 2203 /** 2204 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2205 * @dev: DRM device (needed to create new mode) 2206 * @edid: EDID block 2207 * @timing: EDID detailed timing info 2208 * @quirks: quirks to apply 2209 * 2210 * An EDID detailed timing block contains enough info for us to create and 2211 * return a new struct drm_display_mode. 2212 */ 2213 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2214 struct edid *edid, 2215 struct detailed_timing *timing, 2216 u32 quirks) 2217 { 2218 struct drm_display_mode *mode; 2219 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2220 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2221 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2222 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2223 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2224 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2225 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2226 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2227 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2228 2229 /* ignore tiny modes */ 2230 if (hactive < 64 || vactive < 64) 2231 return NULL; 2232 2233 if (pt->misc & DRM_EDID_PT_STEREO) { 2234 DRM_DEBUG_KMS("stereo mode not supported\n"); 2235 return NULL; 2236 } 2237 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2238 DRM_DEBUG_KMS("composite sync not supported\n"); 2239 } 2240 2241 /* it is incorrect if hsync/vsync width is zero */ 2242 if (!hsync_pulse_width || !vsync_pulse_width) { 2243 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2244 "Wrong Hsync/Vsync pulse width\n"); 2245 return NULL; 2246 } 2247 2248 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2249 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2250 if (!mode) 2251 return NULL; 2252 2253 goto set_size; 2254 } 2255 2256 mode = drm_mode_create(dev); 2257 if (!mode) 2258 return NULL; 2259 2260 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2261 timing->pixel_clock = cpu_to_le16(1088); 2262 2263 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2264 2265 mode->hdisplay = hactive; 2266 mode->hsync_start = mode->hdisplay + hsync_offset; 2267 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2268 mode->htotal = mode->hdisplay + hblank; 2269 2270 mode->vdisplay = vactive; 2271 mode->vsync_start = mode->vdisplay + vsync_offset; 2272 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2273 mode->vtotal = mode->vdisplay + vblank; 2274 2275 /* Some EDIDs have bogus h/vtotal values */ 2276 if (mode->hsync_end > mode->htotal) 2277 mode->htotal = mode->hsync_end + 1; 2278 if (mode->vsync_end > mode->vtotal) 2279 mode->vtotal = mode->vsync_end + 1; 2280 2281 drm_mode_do_interlace_quirk(mode, pt); 2282 2283 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2284 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2285 } 2286 2287 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2288 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2289 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2290 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2291 2292 set_size: 2293 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2294 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2295 2296 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2297 mode->width_mm *= 10; 2298 mode->height_mm *= 10; 2299 } 2300 2301 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2302 mode->width_mm = edid->width_cm * 10; 2303 mode->height_mm = edid->height_cm * 10; 2304 } 2305 2306 mode->type = DRM_MODE_TYPE_DRIVER; 2307 mode->vrefresh = drm_mode_vrefresh(mode); 2308 drm_mode_set_name(mode); 2309 2310 return mode; 2311 } 2312 2313 static bool 2314 mode_in_hsync_range(const struct drm_display_mode *mode, 2315 struct edid *edid, u8 *t) 2316 { 2317 int hsync, hmin, hmax; 2318 2319 hmin = t[7]; 2320 if (edid->revision >= 4) 2321 hmin += ((t[4] & 0x04) ? 255 : 0); 2322 hmax = t[8]; 2323 if (edid->revision >= 4) 2324 hmax += ((t[4] & 0x08) ? 255 : 0); 2325 hsync = drm_mode_hsync(mode); 2326 2327 return (hsync <= hmax && hsync >= hmin); 2328 } 2329 2330 static bool 2331 mode_in_vsync_range(const struct drm_display_mode *mode, 2332 struct edid *edid, u8 *t) 2333 { 2334 int vsync, vmin, vmax; 2335 2336 vmin = t[5]; 2337 if (edid->revision >= 4) 2338 vmin += ((t[4] & 0x01) ? 255 : 0); 2339 vmax = t[6]; 2340 if (edid->revision >= 4) 2341 vmax += ((t[4] & 0x02) ? 255 : 0); 2342 vsync = drm_mode_vrefresh(mode); 2343 2344 return (vsync <= vmax && vsync >= vmin); 2345 } 2346 2347 static u32 2348 range_pixel_clock(struct edid *edid, u8 *t) 2349 { 2350 /* unspecified */ 2351 if (t[9] == 0 || t[9] == 255) 2352 return 0; 2353 2354 /* 1.4 with CVT support gives us real precision, yay */ 2355 if (edid->revision >= 4 && t[10] == 0x04) 2356 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2357 2358 /* 1.3 is pathetic, so fuzz up a bit */ 2359 return t[9] * 10000 + 5001; 2360 } 2361 2362 static bool 2363 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2364 struct detailed_timing *timing) 2365 { 2366 u32 max_clock; 2367 u8 *t = (u8 *)timing; 2368 2369 if (!mode_in_hsync_range(mode, edid, t)) 2370 return false; 2371 2372 if (!mode_in_vsync_range(mode, edid, t)) 2373 return false; 2374 2375 if ((max_clock = range_pixel_clock(edid, t))) 2376 if (mode->clock > max_clock) 2377 return false; 2378 2379 /* 1.4 max horizontal check */ 2380 if (edid->revision >= 4 && t[10] == 0x04) 2381 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2382 return false; 2383 2384 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2385 return false; 2386 2387 return true; 2388 } 2389 2390 static bool valid_inferred_mode(const struct drm_connector *connector, 2391 const struct drm_display_mode *mode) 2392 { 2393 const struct drm_display_mode *m; 2394 bool ok = false; 2395 2396 list_for_each_entry(m, &connector->probed_modes, head) { 2397 if (mode->hdisplay == m->hdisplay && 2398 mode->vdisplay == m->vdisplay && 2399 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2400 return false; /* duplicated */ 2401 if (mode->hdisplay <= m->hdisplay && 2402 mode->vdisplay <= m->vdisplay) 2403 ok = true; 2404 } 2405 return ok; 2406 } 2407 2408 static int 2409 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2410 struct detailed_timing *timing) 2411 { 2412 int i, modes = 0; 2413 struct drm_display_mode *newmode; 2414 struct drm_device *dev = connector->dev; 2415 2416 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2417 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2418 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2419 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2420 if (newmode) { 2421 drm_mode_probed_add(connector, newmode); 2422 modes++; 2423 } 2424 } 2425 } 2426 2427 return modes; 2428 } 2429 2430 /* fix up 1366x768 mode from 1368x768; 2431 * GFT/CVT can't express 1366 width which isn't dividable by 8 2432 */ 2433 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2434 { 2435 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2436 mode->hdisplay = 1366; 2437 mode->hsync_start--; 2438 mode->hsync_end--; 2439 drm_mode_set_name(mode); 2440 } 2441 } 2442 2443 static int 2444 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2445 struct detailed_timing *timing) 2446 { 2447 int i, modes = 0; 2448 struct drm_display_mode *newmode; 2449 struct drm_device *dev = connector->dev; 2450 2451 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2452 const struct minimode *m = &extra_modes[i]; 2453 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2454 if (!newmode) 2455 return modes; 2456 2457 drm_mode_fixup_1366x768(newmode); 2458 if (!mode_in_range(newmode, edid, timing) || 2459 !valid_inferred_mode(connector, newmode)) { 2460 drm_mode_destroy(dev, newmode); 2461 continue; 2462 } 2463 2464 drm_mode_probed_add(connector, newmode); 2465 modes++; 2466 } 2467 2468 return modes; 2469 } 2470 2471 static int 2472 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2473 struct detailed_timing *timing) 2474 { 2475 int i, modes = 0; 2476 struct drm_display_mode *newmode; 2477 struct drm_device *dev = connector->dev; 2478 bool rb = drm_monitor_supports_rb(edid); 2479 2480 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2481 const struct minimode *m = &extra_modes[i]; 2482 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2483 if (!newmode) 2484 return modes; 2485 2486 drm_mode_fixup_1366x768(newmode); 2487 if (!mode_in_range(newmode, edid, timing) || 2488 !valid_inferred_mode(connector, newmode)) { 2489 drm_mode_destroy(dev, newmode); 2490 continue; 2491 } 2492 2493 drm_mode_probed_add(connector, newmode); 2494 modes++; 2495 } 2496 2497 return modes; 2498 } 2499 2500 static void 2501 do_inferred_modes(struct detailed_timing *timing, void *c) 2502 { 2503 struct detailed_mode_closure *closure = c; 2504 struct detailed_non_pixel *data = &timing->data.other_data; 2505 struct detailed_data_monitor_range *range = &data->data.range; 2506 2507 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2508 return; 2509 2510 closure->modes += drm_dmt_modes_for_range(closure->connector, 2511 closure->edid, 2512 timing); 2513 2514 if (!version_greater(closure->edid, 1, 1)) 2515 return; /* GTF not defined yet */ 2516 2517 switch (range->flags) { 2518 case 0x02: /* secondary gtf, XXX could do more */ 2519 case 0x00: /* default gtf */ 2520 closure->modes += drm_gtf_modes_for_range(closure->connector, 2521 closure->edid, 2522 timing); 2523 break; 2524 case 0x04: /* cvt, only in 1.4+ */ 2525 if (!version_greater(closure->edid, 1, 3)) 2526 break; 2527 2528 closure->modes += drm_cvt_modes_for_range(closure->connector, 2529 closure->edid, 2530 timing); 2531 break; 2532 case 0x01: /* just the ranges, no formula */ 2533 default: 2534 break; 2535 } 2536 } 2537 2538 static int 2539 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2540 { 2541 struct detailed_mode_closure closure = { 2542 .connector = connector, 2543 .edid = edid, 2544 }; 2545 2546 if (version_greater(edid, 1, 0)) 2547 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2548 &closure); 2549 2550 return closure.modes; 2551 } 2552 2553 static int 2554 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2555 { 2556 int i, j, m, modes = 0; 2557 struct drm_display_mode *mode; 2558 u8 *est = ((u8 *)timing) + 6; 2559 2560 for (i = 0; i < 6; i++) { 2561 for (j = 7; j >= 0; j--) { 2562 m = (i * 8) + (7 - j); 2563 if (m >= ARRAY_SIZE(est3_modes)) 2564 break; 2565 if (est[i] & (1 << j)) { 2566 mode = drm_mode_find_dmt(connector->dev, 2567 est3_modes[m].w, 2568 est3_modes[m].h, 2569 est3_modes[m].r, 2570 est3_modes[m].rb); 2571 if (mode) { 2572 drm_mode_probed_add(connector, mode); 2573 modes++; 2574 } 2575 } 2576 } 2577 } 2578 2579 return modes; 2580 } 2581 2582 static void 2583 do_established_modes(struct detailed_timing *timing, void *c) 2584 { 2585 struct detailed_mode_closure *closure = c; 2586 struct detailed_non_pixel *data = &timing->data.other_data; 2587 2588 if (data->type == EDID_DETAIL_EST_TIMINGS) 2589 closure->modes += drm_est3_modes(closure->connector, timing); 2590 } 2591 2592 /** 2593 * add_established_modes - get est. modes from EDID and add them 2594 * @connector: connector to add mode(s) to 2595 * @edid: EDID block to scan 2596 * 2597 * Each EDID block contains a bitmap of the supported "established modes" list 2598 * (defined above). Tease them out and add them to the global modes list. 2599 */ 2600 static int 2601 add_established_modes(struct drm_connector *connector, struct edid *edid) 2602 { 2603 struct drm_device *dev = connector->dev; 2604 unsigned long est_bits = edid->established_timings.t1 | 2605 (edid->established_timings.t2 << 8) | 2606 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2607 int i, modes = 0; 2608 struct detailed_mode_closure closure = { 2609 .connector = connector, 2610 .edid = edid, 2611 }; 2612 2613 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2614 if (est_bits & (1<<i)) { 2615 struct drm_display_mode *newmode; 2616 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2617 if (newmode) { 2618 drm_mode_probed_add(connector, newmode); 2619 modes++; 2620 } 2621 } 2622 } 2623 2624 if (version_greater(edid, 1, 0)) 2625 drm_for_each_detailed_block((u8 *)edid, 2626 do_established_modes, &closure); 2627 2628 return modes + closure.modes; 2629 } 2630 2631 static void 2632 do_standard_modes(struct detailed_timing *timing, void *c) 2633 { 2634 struct detailed_mode_closure *closure = c; 2635 struct detailed_non_pixel *data = &timing->data.other_data; 2636 struct drm_connector *connector = closure->connector; 2637 struct edid *edid = closure->edid; 2638 2639 if (data->type == EDID_DETAIL_STD_MODES) { 2640 int i; 2641 for (i = 0; i < 6; i++) { 2642 struct std_timing *std; 2643 struct drm_display_mode *newmode; 2644 2645 std = &data->data.timings[i]; 2646 newmode = drm_mode_std(connector, edid, std); 2647 if (newmode) { 2648 drm_mode_probed_add(connector, newmode); 2649 closure->modes++; 2650 } 2651 } 2652 } 2653 } 2654 2655 /** 2656 * add_standard_modes - get std. modes from EDID and add them 2657 * @connector: connector to add mode(s) to 2658 * @edid: EDID block to scan 2659 * 2660 * Standard modes can be calculated using the appropriate standard (DMT, 2661 * GTF or CVT. Grab them from @edid and add them to the list. 2662 */ 2663 static int 2664 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2665 { 2666 int i, modes = 0; 2667 struct detailed_mode_closure closure = { 2668 .connector = connector, 2669 .edid = edid, 2670 }; 2671 2672 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2673 struct drm_display_mode *newmode; 2674 2675 newmode = drm_mode_std(connector, edid, 2676 &edid->standard_timings[i]); 2677 if (newmode) { 2678 drm_mode_probed_add(connector, newmode); 2679 modes++; 2680 } 2681 } 2682 2683 if (version_greater(edid, 1, 0)) 2684 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2685 &closure); 2686 2687 /* XXX should also look for standard codes in VTB blocks */ 2688 2689 return modes + closure.modes; 2690 } 2691 2692 static int drm_cvt_modes(struct drm_connector *connector, 2693 struct detailed_timing *timing) 2694 { 2695 int i, j, modes = 0; 2696 struct drm_display_mode *newmode; 2697 struct drm_device *dev = connector->dev; 2698 struct cvt_timing *cvt; 2699 const int rates[] = { 60, 85, 75, 60, 50 }; 2700 const u8 empty[3] = { 0, 0, 0 }; 2701 2702 for (i = 0; i < 4; i++) { 2703 int uninitialized_var(width), height; 2704 cvt = &(timing->data.other_data.data.cvt[i]); 2705 2706 if (!memcmp(cvt->code, empty, 3)) 2707 continue; 2708 2709 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2710 switch (cvt->code[1] & 0x0c) { 2711 case 0x00: 2712 width = height * 4 / 3; 2713 break; 2714 case 0x04: 2715 width = height * 16 / 9; 2716 break; 2717 case 0x08: 2718 width = height * 16 / 10; 2719 break; 2720 case 0x0c: 2721 width = height * 15 / 9; 2722 break; 2723 } 2724 2725 for (j = 1; j < 5; j++) { 2726 if (cvt->code[2] & (1 << j)) { 2727 newmode = drm_cvt_mode(dev, width, height, 2728 rates[j], j == 0, 2729 false, false); 2730 if (newmode) { 2731 drm_mode_probed_add(connector, newmode); 2732 modes++; 2733 } 2734 } 2735 } 2736 } 2737 2738 return modes; 2739 } 2740 2741 static void 2742 do_cvt_mode(struct detailed_timing *timing, void *c) 2743 { 2744 struct detailed_mode_closure *closure = c; 2745 struct detailed_non_pixel *data = &timing->data.other_data; 2746 2747 if (data->type == EDID_DETAIL_CVT_3BYTE) 2748 closure->modes += drm_cvt_modes(closure->connector, timing); 2749 } 2750 2751 static int 2752 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2753 { 2754 struct detailed_mode_closure closure = { 2755 .connector = connector, 2756 .edid = edid, 2757 }; 2758 2759 if (version_greater(edid, 1, 2)) 2760 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2761 2762 /* XXX should also look for CVT codes in VTB blocks */ 2763 2764 return closure.modes; 2765 } 2766 2767 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2768 2769 static void 2770 do_detailed_mode(struct detailed_timing *timing, void *c) 2771 { 2772 struct detailed_mode_closure *closure = c; 2773 struct drm_display_mode *newmode; 2774 2775 if (timing->pixel_clock) { 2776 newmode = drm_mode_detailed(closure->connector->dev, 2777 closure->edid, timing, 2778 closure->quirks); 2779 if (!newmode) 2780 return; 2781 2782 if (closure->preferred) 2783 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2784 2785 /* 2786 * Detailed modes are limited to 10kHz pixel clock resolution, 2787 * so fix up anything that looks like CEA/HDMI mode, but the clock 2788 * is just slightly off. 2789 */ 2790 fixup_detailed_cea_mode_clock(newmode); 2791 2792 drm_mode_probed_add(closure->connector, newmode); 2793 closure->modes++; 2794 closure->preferred = false; 2795 } 2796 } 2797 2798 /* 2799 * add_detailed_modes - Add modes from detailed timings 2800 * @connector: attached connector 2801 * @edid: EDID block to scan 2802 * @quirks: quirks to apply 2803 */ 2804 static int 2805 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2806 u32 quirks) 2807 { 2808 struct detailed_mode_closure closure = { 2809 .connector = connector, 2810 .edid = edid, 2811 .preferred = true, 2812 .quirks = quirks, 2813 }; 2814 2815 if (closure.preferred && !version_greater(edid, 1, 3)) 2816 closure.preferred = 2817 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2818 2819 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2820 2821 return closure.modes; 2822 } 2823 2824 #define AUDIO_BLOCK 0x01 2825 #define VIDEO_BLOCK 0x02 2826 #define VENDOR_BLOCK 0x03 2827 #define SPEAKER_BLOCK 0x04 2828 #define USE_EXTENDED_TAG 0x07 2829 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2830 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2831 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2832 #define EDID_BASIC_AUDIO (1 << 6) 2833 #define EDID_CEA_YCRCB444 (1 << 5) 2834 #define EDID_CEA_YCRCB422 (1 << 4) 2835 #define EDID_CEA_VCDB_QS (1 << 6) 2836 2837 /* 2838 * Search EDID for CEA extension block. 2839 */ 2840 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2841 { 2842 u8 *edid_ext = NULL; 2843 int i; 2844 2845 /* No EDID or EDID extensions */ 2846 if (edid == NULL || edid->extensions == 0) 2847 return NULL; 2848 2849 /* Find CEA extension */ 2850 for (i = 0; i < edid->extensions; i++) { 2851 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2852 if (edid_ext[0] == ext_id) 2853 break; 2854 } 2855 2856 if (i == edid->extensions) 2857 return NULL; 2858 2859 return edid_ext; 2860 } 2861 2862 static u8 *drm_find_cea_extension(const struct edid *edid) 2863 { 2864 return drm_find_edid_extension(edid, CEA_EXT); 2865 } 2866 2867 static u8 *drm_find_displayid_extension(const struct edid *edid) 2868 { 2869 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2870 } 2871 2872 /* 2873 * Calculate the alternate clock for the CEA mode 2874 * (60Hz vs. 59.94Hz etc.) 2875 */ 2876 static unsigned int 2877 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2878 { 2879 unsigned int clock = cea_mode->clock; 2880 2881 if (cea_mode->vrefresh % 6 != 0) 2882 return clock; 2883 2884 /* 2885 * edid_cea_modes contains the 59.94Hz 2886 * variant for 240 and 480 line modes, 2887 * and the 60Hz variant otherwise. 2888 */ 2889 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2890 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2891 else 2892 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2893 2894 return clock; 2895 } 2896 2897 static bool 2898 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2899 { 2900 /* 2901 * For certain VICs the spec allows the vertical 2902 * front porch to vary by one or two lines. 2903 * 2904 * cea_modes[] stores the variant with the shortest 2905 * vertical front porch. We can adjust the mode to 2906 * get the other variants by simply increasing the 2907 * vertical front porch length. 2908 */ 2909 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2910 edid_cea_modes[9].vtotal != 262 || 2911 edid_cea_modes[12].vtotal != 262 || 2912 edid_cea_modes[13].vtotal != 262 || 2913 edid_cea_modes[23].vtotal != 312 || 2914 edid_cea_modes[24].vtotal != 312 || 2915 edid_cea_modes[27].vtotal != 312 || 2916 edid_cea_modes[28].vtotal != 312); 2917 2918 if (((vic == 8 || vic == 9 || 2919 vic == 12 || vic == 13) && mode->vtotal < 263) || 2920 ((vic == 23 || vic == 24 || 2921 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2922 mode->vsync_start++; 2923 mode->vsync_end++; 2924 mode->vtotal++; 2925 2926 return true; 2927 } 2928 2929 return false; 2930 } 2931 2932 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2933 unsigned int clock_tolerance) 2934 { 2935 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2936 u8 vic; 2937 2938 if (!to_match->clock) 2939 return 0; 2940 2941 if (to_match->picture_aspect_ratio) 2942 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2943 2944 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2945 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2946 unsigned int clock1, clock2; 2947 2948 /* Check both 60Hz and 59.94Hz */ 2949 clock1 = cea_mode.clock; 2950 clock2 = cea_mode_alternate_clock(&cea_mode); 2951 2952 if (abs(to_match->clock - clock1) > clock_tolerance && 2953 abs(to_match->clock - clock2) > clock_tolerance) 2954 continue; 2955 2956 do { 2957 if (drm_mode_match(to_match, &cea_mode, match_flags)) 2958 return vic; 2959 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2960 } 2961 2962 return 0; 2963 } 2964 2965 /** 2966 * drm_match_cea_mode - look for a CEA mode matching given mode 2967 * @to_match: display mode 2968 * 2969 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2970 * mode. 2971 */ 2972 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2973 { 2974 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2975 u8 vic; 2976 2977 if (!to_match->clock) 2978 return 0; 2979 2980 if (to_match->picture_aspect_ratio) 2981 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2982 2983 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2984 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2985 unsigned int clock1, clock2; 2986 2987 /* Check both 60Hz and 59.94Hz */ 2988 clock1 = cea_mode.clock; 2989 clock2 = cea_mode_alternate_clock(&cea_mode); 2990 2991 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 2992 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 2993 continue; 2994 2995 do { 2996 if (drm_mode_match(to_match, &cea_mode, match_flags)) 2997 return vic; 2998 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2999 } 3000 3001 return 0; 3002 } 3003 EXPORT_SYMBOL(drm_match_cea_mode); 3004 3005 static bool drm_valid_cea_vic(u8 vic) 3006 { 3007 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3008 } 3009 3010 /** 3011 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3012 * the input VIC from the CEA mode list 3013 * @video_code: ID given to each of the CEA modes 3014 * 3015 * Returns picture aspect ratio 3016 */ 3017 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3018 { 3019 return edid_cea_modes[video_code].picture_aspect_ratio; 3020 } 3021 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3022 3023 /* 3024 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3025 * specific block). 3026 * 3027 * It's almost like cea_mode_alternate_clock(), we just need to add an 3028 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3029 * one. 3030 */ 3031 static unsigned int 3032 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3033 { 3034 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3035 return hdmi_mode->clock; 3036 3037 return cea_mode_alternate_clock(hdmi_mode); 3038 } 3039 3040 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3041 unsigned int clock_tolerance) 3042 { 3043 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3044 u8 vic; 3045 3046 if (!to_match->clock) 3047 return 0; 3048 3049 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3050 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3051 unsigned int clock1, clock2; 3052 3053 /* Make sure to also match alternate clocks */ 3054 clock1 = hdmi_mode->clock; 3055 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3056 3057 if (abs(to_match->clock - clock1) > clock_tolerance && 3058 abs(to_match->clock - clock2) > clock_tolerance) 3059 continue; 3060 3061 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3062 return vic; 3063 } 3064 3065 return 0; 3066 } 3067 3068 /* 3069 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3070 * @to_match: display mode 3071 * 3072 * An HDMI mode is one defined in the HDMI vendor specific block. 3073 * 3074 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3075 */ 3076 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3077 { 3078 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3079 u8 vic; 3080 3081 if (!to_match->clock) 3082 return 0; 3083 3084 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3085 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3086 unsigned int clock1, clock2; 3087 3088 /* Make sure to also match alternate clocks */ 3089 clock1 = hdmi_mode->clock; 3090 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3091 3092 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3093 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3094 drm_mode_match(to_match, hdmi_mode, match_flags)) 3095 return vic; 3096 } 3097 return 0; 3098 } 3099 3100 static bool drm_valid_hdmi_vic(u8 vic) 3101 { 3102 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3103 } 3104 3105 static int 3106 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3107 { 3108 struct drm_device *dev = connector->dev; 3109 struct drm_display_mode *mode, *tmp; 3110 LIST_HEAD(list); 3111 int modes = 0; 3112 3113 /* Don't add CEA modes if the CEA extension block is missing */ 3114 if (!drm_find_cea_extension(edid)) 3115 return 0; 3116 3117 /* 3118 * Go through all probed modes and create a new mode 3119 * with the alternate clock for certain CEA modes. 3120 */ 3121 list_for_each_entry(mode, &connector->probed_modes, head) { 3122 const struct drm_display_mode *cea_mode = NULL; 3123 struct drm_display_mode *newmode; 3124 u8 vic = drm_match_cea_mode(mode); 3125 unsigned int clock1, clock2; 3126 3127 if (drm_valid_cea_vic(vic)) { 3128 cea_mode = &edid_cea_modes[vic]; 3129 clock2 = cea_mode_alternate_clock(cea_mode); 3130 } else { 3131 vic = drm_match_hdmi_mode(mode); 3132 if (drm_valid_hdmi_vic(vic)) { 3133 cea_mode = &edid_4k_modes[vic]; 3134 clock2 = hdmi_mode_alternate_clock(cea_mode); 3135 } 3136 } 3137 3138 if (!cea_mode) 3139 continue; 3140 3141 clock1 = cea_mode->clock; 3142 3143 if (clock1 == clock2) 3144 continue; 3145 3146 if (mode->clock != clock1 && mode->clock != clock2) 3147 continue; 3148 3149 newmode = drm_mode_duplicate(dev, cea_mode); 3150 if (!newmode) 3151 continue; 3152 3153 /* Carry over the stereo flags */ 3154 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3155 3156 /* 3157 * The current mode could be either variant. Make 3158 * sure to pick the "other" clock for the new mode. 3159 */ 3160 if (mode->clock != clock1) 3161 newmode->clock = clock1; 3162 else 3163 newmode->clock = clock2; 3164 3165 list_add_tail(&newmode->head, &list); 3166 } 3167 3168 list_for_each_entry_safe(mode, tmp, &list, head) { 3169 list_del(&mode->head); 3170 drm_mode_probed_add(connector, mode); 3171 modes++; 3172 } 3173 3174 return modes; 3175 } 3176 3177 static u8 svd_to_vic(u8 svd) 3178 { 3179 /* 0-6 bit vic, 7th bit native mode indicator */ 3180 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3181 return svd & 127; 3182 3183 return svd; 3184 } 3185 3186 static struct drm_display_mode * 3187 drm_display_mode_from_vic_index(struct drm_connector *connector, 3188 const u8 *video_db, u8 video_len, 3189 u8 video_index) 3190 { 3191 struct drm_device *dev = connector->dev; 3192 struct drm_display_mode *newmode; 3193 u8 vic; 3194 3195 if (video_db == NULL || video_index >= video_len) 3196 return NULL; 3197 3198 /* CEA modes are numbered 1..127 */ 3199 vic = svd_to_vic(video_db[video_index]); 3200 if (!drm_valid_cea_vic(vic)) 3201 return NULL; 3202 3203 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3204 if (!newmode) 3205 return NULL; 3206 3207 newmode->vrefresh = 0; 3208 3209 return newmode; 3210 } 3211 3212 /* 3213 * do_y420vdb_modes - Parse YCBCR 420 only modes 3214 * @connector: connector corresponding to the HDMI sink 3215 * @svds: start of the data block of CEA YCBCR 420 VDB 3216 * @len: length of the CEA YCBCR 420 VDB 3217 * 3218 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3219 * which contains modes which can be supported in YCBCR 420 3220 * output format only. 3221 */ 3222 static int do_y420vdb_modes(struct drm_connector *connector, 3223 const u8 *svds, u8 svds_len) 3224 { 3225 int modes = 0, i; 3226 struct drm_device *dev = connector->dev; 3227 struct drm_display_info *info = &connector->display_info; 3228 struct drm_hdmi_info *hdmi = &info->hdmi; 3229 3230 for (i = 0; i < svds_len; i++) { 3231 u8 vic = svd_to_vic(svds[i]); 3232 struct drm_display_mode *newmode; 3233 3234 if (!drm_valid_cea_vic(vic)) 3235 continue; 3236 3237 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3238 if (!newmode) 3239 break; 3240 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3241 drm_mode_probed_add(connector, newmode); 3242 modes++; 3243 } 3244 3245 if (modes > 0) 3246 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3247 return modes; 3248 } 3249 3250 /* 3251 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3252 * @connector: connector corresponding to the HDMI sink 3253 * @vic: CEA vic for the video mode to be added in the map 3254 * 3255 * Makes an entry for a videomode in the YCBCR 420 bitmap 3256 */ 3257 static void 3258 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3259 { 3260 u8 vic = svd_to_vic(svd); 3261 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3262 3263 if (!drm_valid_cea_vic(vic)) 3264 return; 3265 3266 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3267 } 3268 3269 static int 3270 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3271 { 3272 int i, modes = 0; 3273 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3274 3275 for (i = 0; i < len; i++) { 3276 struct drm_display_mode *mode; 3277 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3278 if (mode) { 3279 /* 3280 * YCBCR420 capability block contains a bitmap which 3281 * gives the index of CEA modes from CEA VDB, which 3282 * can support YCBCR 420 sampling output also (apart 3283 * from RGB/YCBCR444 etc). 3284 * For example, if the bit 0 in bitmap is set, 3285 * first mode in VDB can support YCBCR420 output too. 3286 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3287 */ 3288 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3289 drm_add_cmdb_modes(connector, db[i]); 3290 3291 drm_mode_probed_add(connector, mode); 3292 modes++; 3293 } 3294 } 3295 3296 return modes; 3297 } 3298 3299 struct stereo_mandatory_mode { 3300 int width, height, vrefresh; 3301 unsigned int flags; 3302 }; 3303 3304 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3305 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3306 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3307 { 1920, 1080, 50, 3308 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3309 { 1920, 1080, 60, 3310 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3311 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3312 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3313 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3314 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3315 }; 3316 3317 static bool 3318 stereo_match_mandatory(const struct drm_display_mode *mode, 3319 const struct stereo_mandatory_mode *stereo_mode) 3320 { 3321 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3322 3323 return mode->hdisplay == stereo_mode->width && 3324 mode->vdisplay == stereo_mode->height && 3325 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3326 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3327 } 3328 3329 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3330 { 3331 struct drm_device *dev = connector->dev; 3332 const struct drm_display_mode *mode; 3333 struct list_head stereo_modes; 3334 int modes = 0, i; 3335 3336 INIT_LIST_HEAD(&stereo_modes); 3337 3338 list_for_each_entry(mode, &connector->probed_modes, head) { 3339 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3340 const struct stereo_mandatory_mode *mandatory; 3341 struct drm_display_mode *new_mode; 3342 3343 if (!stereo_match_mandatory(mode, 3344 &stereo_mandatory_modes[i])) 3345 continue; 3346 3347 mandatory = &stereo_mandatory_modes[i]; 3348 new_mode = drm_mode_duplicate(dev, mode); 3349 if (!new_mode) 3350 continue; 3351 3352 new_mode->flags |= mandatory->flags; 3353 list_add_tail(&new_mode->head, &stereo_modes); 3354 modes++; 3355 } 3356 } 3357 3358 list_splice_tail(&stereo_modes, &connector->probed_modes); 3359 3360 return modes; 3361 } 3362 3363 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3364 { 3365 struct drm_device *dev = connector->dev; 3366 struct drm_display_mode *newmode; 3367 3368 if (!drm_valid_hdmi_vic(vic)) { 3369 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3370 return 0; 3371 } 3372 3373 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3374 if (!newmode) 3375 return 0; 3376 3377 drm_mode_probed_add(connector, newmode); 3378 3379 return 1; 3380 } 3381 3382 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3383 const u8 *video_db, u8 video_len, u8 video_index) 3384 { 3385 struct drm_display_mode *newmode; 3386 int modes = 0; 3387 3388 if (structure & (1 << 0)) { 3389 newmode = drm_display_mode_from_vic_index(connector, video_db, 3390 video_len, 3391 video_index); 3392 if (newmode) { 3393 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3394 drm_mode_probed_add(connector, newmode); 3395 modes++; 3396 } 3397 } 3398 if (structure & (1 << 6)) { 3399 newmode = drm_display_mode_from_vic_index(connector, video_db, 3400 video_len, 3401 video_index); 3402 if (newmode) { 3403 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3404 drm_mode_probed_add(connector, newmode); 3405 modes++; 3406 } 3407 } 3408 if (structure & (1 << 8)) { 3409 newmode = drm_display_mode_from_vic_index(connector, video_db, 3410 video_len, 3411 video_index); 3412 if (newmode) { 3413 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3414 drm_mode_probed_add(connector, newmode); 3415 modes++; 3416 } 3417 } 3418 3419 return modes; 3420 } 3421 3422 /* 3423 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3424 * @connector: connector corresponding to the HDMI sink 3425 * @db: start of the CEA vendor specific block 3426 * @len: length of the CEA block payload, ie. one can access up to db[len] 3427 * 3428 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3429 * also adds the stereo 3d modes when applicable. 3430 */ 3431 static int 3432 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3433 const u8 *video_db, u8 video_len) 3434 { 3435 struct drm_display_info *info = &connector->display_info; 3436 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3437 u8 vic_len, hdmi_3d_len = 0; 3438 u16 mask; 3439 u16 structure_all; 3440 3441 if (len < 8) 3442 goto out; 3443 3444 /* no HDMI_Video_Present */ 3445 if (!(db[8] & (1 << 5))) 3446 goto out; 3447 3448 /* Latency_Fields_Present */ 3449 if (db[8] & (1 << 7)) 3450 offset += 2; 3451 3452 /* I_Latency_Fields_Present */ 3453 if (db[8] & (1 << 6)) 3454 offset += 2; 3455 3456 /* the declared length is not long enough for the 2 first bytes 3457 * of additional video format capabilities */ 3458 if (len < (8 + offset + 2)) 3459 goto out; 3460 3461 /* 3D_Present */ 3462 offset++; 3463 if (db[8 + offset] & (1 << 7)) { 3464 modes += add_hdmi_mandatory_stereo_modes(connector); 3465 3466 /* 3D_Multi_present */ 3467 multi_present = (db[8 + offset] & 0x60) >> 5; 3468 } 3469 3470 offset++; 3471 vic_len = db[8 + offset] >> 5; 3472 hdmi_3d_len = db[8 + offset] & 0x1f; 3473 3474 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3475 u8 vic; 3476 3477 vic = db[9 + offset + i]; 3478 modes += add_hdmi_mode(connector, vic); 3479 } 3480 offset += 1 + vic_len; 3481 3482 if (multi_present == 1) 3483 multi_len = 2; 3484 else if (multi_present == 2) 3485 multi_len = 4; 3486 else 3487 multi_len = 0; 3488 3489 if (len < (8 + offset + hdmi_3d_len - 1)) 3490 goto out; 3491 3492 if (hdmi_3d_len < multi_len) 3493 goto out; 3494 3495 if (multi_present == 1 || multi_present == 2) { 3496 /* 3D_Structure_ALL */ 3497 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3498 3499 /* check if 3D_MASK is present */ 3500 if (multi_present == 2) 3501 mask = (db[10 + offset] << 8) | db[11 + offset]; 3502 else 3503 mask = 0xffff; 3504 3505 for (i = 0; i < 16; i++) { 3506 if (mask & (1 << i)) 3507 modes += add_3d_struct_modes(connector, 3508 structure_all, 3509 video_db, 3510 video_len, i); 3511 } 3512 } 3513 3514 offset += multi_len; 3515 3516 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3517 int vic_index; 3518 struct drm_display_mode *newmode = NULL; 3519 unsigned int newflag = 0; 3520 bool detail_present; 3521 3522 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3523 3524 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3525 break; 3526 3527 /* 2D_VIC_order_X */ 3528 vic_index = db[8 + offset + i] >> 4; 3529 3530 /* 3D_Structure_X */ 3531 switch (db[8 + offset + i] & 0x0f) { 3532 case 0: 3533 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3534 break; 3535 case 6: 3536 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3537 break; 3538 case 8: 3539 /* 3D_Detail_X */ 3540 if ((db[9 + offset + i] >> 4) == 1) 3541 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3542 break; 3543 } 3544 3545 if (newflag != 0) { 3546 newmode = drm_display_mode_from_vic_index(connector, 3547 video_db, 3548 video_len, 3549 vic_index); 3550 3551 if (newmode) { 3552 newmode->flags |= newflag; 3553 drm_mode_probed_add(connector, newmode); 3554 modes++; 3555 } 3556 } 3557 3558 if (detail_present) 3559 i++; 3560 } 3561 3562 out: 3563 if (modes > 0) 3564 info->has_hdmi_infoframe = true; 3565 return modes; 3566 } 3567 3568 static int 3569 cea_db_payload_len(const u8 *db) 3570 { 3571 return db[0] & 0x1f; 3572 } 3573 3574 static int 3575 cea_db_extended_tag(const u8 *db) 3576 { 3577 return db[1]; 3578 } 3579 3580 static int 3581 cea_db_tag(const u8 *db) 3582 { 3583 return db[0] >> 5; 3584 } 3585 3586 static int 3587 cea_revision(const u8 *cea) 3588 { 3589 return cea[1]; 3590 } 3591 3592 static int 3593 cea_db_offsets(const u8 *cea, int *start, int *end) 3594 { 3595 /* Data block offset in CEA extension block */ 3596 *start = 4; 3597 *end = cea[2]; 3598 if (*end == 0) 3599 *end = 127; 3600 if (*end < 4 || *end > 127) 3601 return -ERANGE; 3602 return 0; 3603 } 3604 3605 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3606 { 3607 int hdmi_id; 3608 3609 if (cea_db_tag(db) != VENDOR_BLOCK) 3610 return false; 3611 3612 if (cea_db_payload_len(db) < 5) 3613 return false; 3614 3615 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3616 3617 return hdmi_id == HDMI_IEEE_OUI; 3618 } 3619 3620 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3621 { 3622 unsigned int oui; 3623 3624 if (cea_db_tag(db) != VENDOR_BLOCK) 3625 return false; 3626 3627 if (cea_db_payload_len(db) < 7) 3628 return false; 3629 3630 oui = db[3] << 16 | db[2] << 8 | db[1]; 3631 3632 return oui == HDMI_FORUM_IEEE_OUI; 3633 } 3634 3635 static bool cea_db_is_y420cmdb(const u8 *db) 3636 { 3637 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3638 return false; 3639 3640 if (!cea_db_payload_len(db)) 3641 return false; 3642 3643 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3644 return false; 3645 3646 return true; 3647 } 3648 3649 static bool cea_db_is_y420vdb(const u8 *db) 3650 { 3651 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3652 return false; 3653 3654 if (!cea_db_payload_len(db)) 3655 return false; 3656 3657 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3658 return false; 3659 3660 return true; 3661 } 3662 3663 #define for_each_cea_db(cea, i, start, end) \ 3664 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3665 3666 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3667 const u8 *db) 3668 { 3669 struct drm_display_info *info = &connector->display_info; 3670 struct drm_hdmi_info *hdmi = &info->hdmi; 3671 u8 map_len = cea_db_payload_len(db) - 1; 3672 u8 count; 3673 u64 map = 0; 3674 3675 if (map_len == 0) { 3676 /* All CEA modes support ycbcr420 sampling also.*/ 3677 hdmi->y420_cmdb_map = U64_MAX; 3678 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3679 return; 3680 } 3681 3682 /* 3683 * This map indicates which of the existing CEA block modes 3684 * from VDB can support YCBCR420 output too. So if bit=0 is 3685 * set, first mode from VDB can support YCBCR420 output too. 3686 * We will parse and keep this map, before parsing VDB itself 3687 * to avoid going through the same block again and again. 3688 * 3689 * Spec is not clear about max possible size of this block. 3690 * Clamping max bitmap block size at 8 bytes. Every byte can 3691 * address 8 CEA modes, in this way this map can address 3692 * 8*8 = first 64 SVDs. 3693 */ 3694 if (WARN_ON_ONCE(map_len > 8)) 3695 map_len = 8; 3696 3697 for (count = 0; count < map_len; count++) 3698 map |= (u64)db[2 + count] << (8 * count); 3699 3700 if (map) 3701 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3702 3703 hdmi->y420_cmdb_map = map; 3704 } 3705 3706 static int 3707 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3708 { 3709 const u8 *cea = drm_find_cea_extension(edid); 3710 const u8 *db, *hdmi = NULL, *video = NULL; 3711 u8 dbl, hdmi_len, video_len = 0; 3712 int modes = 0; 3713 3714 if (cea && cea_revision(cea) >= 3) { 3715 int i, start, end; 3716 3717 if (cea_db_offsets(cea, &start, &end)) 3718 return 0; 3719 3720 for_each_cea_db(cea, i, start, end) { 3721 db = &cea[i]; 3722 dbl = cea_db_payload_len(db); 3723 3724 if (cea_db_tag(db) == VIDEO_BLOCK) { 3725 video = db + 1; 3726 video_len = dbl; 3727 modes += do_cea_modes(connector, video, dbl); 3728 } else if (cea_db_is_hdmi_vsdb(db)) { 3729 hdmi = db; 3730 hdmi_len = dbl; 3731 } else if (cea_db_is_y420vdb(db)) { 3732 const u8 *vdb420 = &db[2]; 3733 3734 /* Add 4:2:0(only) modes present in EDID */ 3735 modes += do_y420vdb_modes(connector, 3736 vdb420, 3737 dbl - 1); 3738 } 3739 } 3740 } 3741 3742 /* 3743 * We parse the HDMI VSDB after having added the cea modes as we will 3744 * be patching their flags when the sink supports stereo 3D. 3745 */ 3746 if (hdmi) 3747 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3748 video_len); 3749 3750 return modes; 3751 } 3752 3753 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3754 { 3755 const struct drm_display_mode *cea_mode; 3756 int clock1, clock2, clock; 3757 u8 vic; 3758 const char *type; 3759 3760 /* 3761 * allow 5kHz clock difference either way to account for 3762 * the 10kHz clock resolution limit of detailed timings. 3763 */ 3764 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3765 if (drm_valid_cea_vic(vic)) { 3766 type = "CEA"; 3767 cea_mode = &edid_cea_modes[vic]; 3768 clock1 = cea_mode->clock; 3769 clock2 = cea_mode_alternate_clock(cea_mode); 3770 } else { 3771 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3772 if (drm_valid_hdmi_vic(vic)) { 3773 type = "HDMI"; 3774 cea_mode = &edid_4k_modes[vic]; 3775 clock1 = cea_mode->clock; 3776 clock2 = hdmi_mode_alternate_clock(cea_mode); 3777 } else { 3778 return; 3779 } 3780 } 3781 3782 /* pick whichever is closest */ 3783 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3784 clock = clock1; 3785 else 3786 clock = clock2; 3787 3788 if (mode->clock == clock) 3789 return; 3790 3791 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3792 type, vic, mode->clock, clock); 3793 mode->clock = clock; 3794 } 3795 3796 static void 3797 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3798 { 3799 u8 len = cea_db_payload_len(db); 3800 3801 if (len >= 6 && (db[6] & (1 << 7))) 3802 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3803 if (len >= 8) { 3804 connector->latency_present[0] = db[8] >> 7; 3805 connector->latency_present[1] = (db[8] >> 6) & 1; 3806 } 3807 if (len >= 9) 3808 connector->video_latency[0] = db[9]; 3809 if (len >= 10) 3810 connector->audio_latency[0] = db[10]; 3811 if (len >= 11) 3812 connector->video_latency[1] = db[11]; 3813 if (len >= 12) 3814 connector->audio_latency[1] = db[12]; 3815 3816 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3817 "video latency %d %d, " 3818 "audio latency %d %d\n", 3819 connector->latency_present[0], 3820 connector->latency_present[1], 3821 connector->video_latency[0], 3822 connector->video_latency[1], 3823 connector->audio_latency[0], 3824 connector->audio_latency[1]); 3825 } 3826 3827 static void 3828 monitor_name(struct detailed_timing *t, void *data) 3829 { 3830 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3831 *(u8 **)data = t->data.other_data.data.str.str; 3832 } 3833 3834 static int get_monitor_name(struct edid *edid, char name[13]) 3835 { 3836 char *edid_name = NULL; 3837 int mnl; 3838 3839 if (!edid || !name) 3840 return 0; 3841 3842 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3843 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3844 if (edid_name[mnl] == 0x0a) 3845 break; 3846 3847 name[mnl] = edid_name[mnl]; 3848 } 3849 3850 return mnl; 3851 } 3852 3853 /** 3854 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3855 * @edid: monitor EDID information 3856 * @name: pointer to a character array to hold the name of the monitor 3857 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3858 * 3859 */ 3860 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3861 { 3862 int name_length; 3863 char buf[13]; 3864 3865 if (bufsize <= 0) 3866 return; 3867 3868 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3869 memcpy(name, buf, name_length); 3870 name[name_length] = '\0'; 3871 } 3872 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3873 3874 static void clear_eld(struct drm_connector *connector) 3875 { 3876 memset(connector->eld, 0, sizeof(connector->eld)); 3877 3878 connector->latency_present[0] = false; 3879 connector->latency_present[1] = false; 3880 connector->video_latency[0] = 0; 3881 connector->audio_latency[0] = 0; 3882 connector->video_latency[1] = 0; 3883 connector->audio_latency[1] = 0; 3884 } 3885 3886 /* 3887 * drm_edid_to_eld - build ELD from EDID 3888 * @connector: connector corresponding to the HDMI/DP sink 3889 * @edid: EDID to parse 3890 * 3891 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3892 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3893 */ 3894 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3895 { 3896 uint8_t *eld = connector->eld; 3897 u8 *cea; 3898 u8 *db; 3899 int total_sad_count = 0; 3900 int mnl; 3901 int dbl; 3902 3903 clear_eld(connector); 3904 3905 if (!edid) 3906 return; 3907 3908 cea = drm_find_cea_extension(edid); 3909 if (!cea) { 3910 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3911 return; 3912 } 3913 3914 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 3915 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 3916 3917 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 3918 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 3919 3920 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 3921 3922 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 3923 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 3924 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 3925 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 3926 3927 if (cea_revision(cea) >= 3) { 3928 int i, start, end; 3929 3930 if (cea_db_offsets(cea, &start, &end)) { 3931 start = 0; 3932 end = 0; 3933 } 3934 3935 for_each_cea_db(cea, i, start, end) { 3936 db = &cea[i]; 3937 dbl = cea_db_payload_len(db); 3938 3939 switch (cea_db_tag(db)) { 3940 int sad_count; 3941 3942 case AUDIO_BLOCK: 3943 /* Audio Data Block, contains SADs */ 3944 sad_count = min(dbl / 3, 15 - total_sad_count); 3945 if (sad_count >= 1) 3946 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 3947 &db[1], sad_count * 3); 3948 total_sad_count += sad_count; 3949 break; 3950 case SPEAKER_BLOCK: 3951 /* Speaker Allocation Data Block */ 3952 if (dbl >= 1) 3953 eld[DRM_ELD_SPEAKER] = db[1]; 3954 break; 3955 case VENDOR_BLOCK: 3956 /* HDMI Vendor-Specific Data Block */ 3957 if (cea_db_is_hdmi_vsdb(db)) 3958 drm_parse_hdmi_vsdb_audio(connector, db); 3959 break; 3960 default: 3961 break; 3962 } 3963 } 3964 } 3965 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 3966 3967 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3968 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3969 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 3970 else 3971 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 3972 3973 eld[DRM_ELD_BASELINE_ELD_LEN] = 3974 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3975 3976 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3977 drm_eld_size(eld), total_sad_count); 3978 } 3979 3980 /** 3981 * drm_edid_to_sad - extracts SADs from EDID 3982 * @edid: EDID to parse 3983 * @sads: pointer that will be set to the extracted SADs 3984 * 3985 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3986 * 3987 * Note: The returned pointer needs to be freed using kfree(). 3988 * 3989 * Return: The number of found SADs or negative number on error. 3990 */ 3991 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3992 { 3993 int count = 0; 3994 int i, start, end, dbl; 3995 u8 *cea; 3996 3997 cea = drm_find_cea_extension(edid); 3998 if (!cea) { 3999 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4000 return -ENOENT; 4001 } 4002 4003 if (cea_revision(cea) < 3) { 4004 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4005 return -ENOTSUPP; 4006 } 4007 4008 if (cea_db_offsets(cea, &start, &end)) { 4009 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4010 return -EPROTO; 4011 } 4012 4013 for_each_cea_db(cea, i, start, end) { 4014 u8 *db = &cea[i]; 4015 4016 if (cea_db_tag(db) == AUDIO_BLOCK) { 4017 int j; 4018 dbl = cea_db_payload_len(db); 4019 4020 count = dbl / 3; /* SAD is 3B */ 4021 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4022 if (!*sads) 4023 return -ENOMEM; 4024 for (j = 0; j < count; j++) { 4025 u8 *sad = &db[1 + j * 3]; 4026 4027 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4028 (*sads)[j].channels = sad[0] & 0x7; 4029 (*sads)[j].freq = sad[1] & 0x7F; 4030 (*sads)[j].byte2 = sad[2]; 4031 } 4032 break; 4033 } 4034 } 4035 4036 return count; 4037 } 4038 EXPORT_SYMBOL(drm_edid_to_sad); 4039 4040 /** 4041 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4042 * @edid: EDID to parse 4043 * @sadb: pointer to the speaker block 4044 * 4045 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4046 * 4047 * Note: The returned pointer needs to be freed using kfree(). 4048 * 4049 * Return: The number of found Speaker Allocation Blocks or negative number on 4050 * error. 4051 */ 4052 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4053 { 4054 int count = 0; 4055 int i, start, end, dbl; 4056 const u8 *cea; 4057 4058 cea = drm_find_cea_extension(edid); 4059 if (!cea) { 4060 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4061 return -ENOENT; 4062 } 4063 4064 if (cea_revision(cea) < 3) { 4065 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4066 return -ENOTSUPP; 4067 } 4068 4069 if (cea_db_offsets(cea, &start, &end)) { 4070 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4071 return -EPROTO; 4072 } 4073 4074 for_each_cea_db(cea, i, start, end) { 4075 const u8 *db = &cea[i]; 4076 4077 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4078 dbl = cea_db_payload_len(db); 4079 4080 /* Speaker Allocation Data Block */ 4081 if (dbl == 3) { 4082 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4083 if (!*sadb) 4084 return -ENOMEM; 4085 count = dbl; 4086 break; 4087 } 4088 } 4089 } 4090 4091 return count; 4092 } 4093 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4094 4095 /** 4096 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4097 * @connector: connector associated with the HDMI/DP sink 4098 * @mode: the display mode 4099 * 4100 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4101 * the sink doesn't support audio or video. 4102 */ 4103 int drm_av_sync_delay(struct drm_connector *connector, 4104 const struct drm_display_mode *mode) 4105 { 4106 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4107 int a, v; 4108 4109 if (!connector->latency_present[0]) 4110 return 0; 4111 if (!connector->latency_present[1]) 4112 i = 0; 4113 4114 a = connector->audio_latency[i]; 4115 v = connector->video_latency[i]; 4116 4117 /* 4118 * HDMI/DP sink doesn't support audio or video? 4119 */ 4120 if (a == 255 || v == 255) 4121 return 0; 4122 4123 /* 4124 * Convert raw EDID values to millisecond. 4125 * Treat unknown latency as 0ms. 4126 */ 4127 if (a) 4128 a = min(2 * (a - 1), 500); 4129 if (v) 4130 v = min(2 * (v - 1), 500); 4131 4132 return max(v - a, 0); 4133 } 4134 EXPORT_SYMBOL(drm_av_sync_delay); 4135 4136 /** 4137 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4138 * @edid: monitor EDID information 4139 * 4140 * Parse the CEA extension according to CEA-861-B. 4141 * 4142 * Return: True if the monitor is HDMI, false if not or unknown. 4143 */ 4144 bool drm_detect_hdmi_monitor(struct edid *edid) 4145 { 4146 u8 *edid_ext; 4147 int i; 4148 int start_offset, end_offset; 4149 4150 edid_ext = drm_find_cea_extension(edid); 4151 if (!edid_ext) 4152 return false; 4153 4154 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4155 return false; 4156 4157 /* 4158 * Because HDMI identifier is in Vendor Specific Block, 4159 * search it from all data blocks of CEA extension. 4160 */ 4161 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4162 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4163 return true; 4164 } 4165 4166 return false; 4167 } 4168 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4169 4170 /** 4171 * drm_detect_monitor_audio - check monitor audio capability 4172 * @edid: EDID block to scan 4173 * 4174 * Monitor should have CEA extension block. 4175 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4176 * audio' only. If there is any audio extension block and supported 4177 * audio format, assume at least 'basic audio' support, even if 'basic 4178 * audio' is not defined in EDID. 4179 * 4180 * Return: True if the monitor supports audio, false otherwise. 4181 */ 4182 bool drm_detect_monitor_audio(struct edid *edid) 4183 { 4184 u8 *edid_ext; 4185 int i, j; 4186 bool has_audio = false; 4187 int start_offset, end_offset; 4188 4189 edid_ext = drm_find_cea_extension(edid); 4190 if (!edid_ext) 4191 goto end; 4192 4193 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4194 4195 if (has_audio) { 4196 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4197 goto end; 4198 } 4199 4200 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4201 goto end; 4202 4203 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4204 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4205 has_audio = true; 4206 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4207 DRM_DEBUG_KMS("CEA audio format %d\n", 4208 (edid_ext[i + j] >> 3) & 0xf); 4209 goto end; 4210 } 4211 } 4212 end: 4213 return has_audio; 4214 } 4215 EXPORT_SYMBOL(drm_detect_monitor_audio); 4216 4217 /** 4218 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 4219 * @edid: EDID block to scan 4220 * 4221 * Check whether the monitor reports the RGB quantization range selection 4222 * as supported. The AVI infoframe can then be used to inform the monitor 4223 * which quantization range (full or limited) is used. 4224 * 4225 * Return: True if the RGB quantization range is selectable, false otherwise. 4226 */ 4227 bool drm_rgb_quant_range_selectable(struct edid *edid) 4228 { 4229 u8 *edid_ext; 4230 int i, start, end; 4231 4232 edid_ext = drm_find_cea_extension(edid); 4233 if (!edid_ext) 4234 return false; 4235 4236 if (cea_db_offsets(edid_ext, &start, &end)) 4237 return false; 4238 4239 for_each_cea_db(edid_ext, i, start, end) { 4240 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG && 4241 cea_db_payload_len(&edid_ext[i]) == 2 && 4242 cea_db_extended_tag(&edid_ext[i]) == 4243 EXT_VIDEO_CAPABILITY_BLOCK) { 4244 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 4245 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 4246 } 4247 } 4248 4249 return false; 4250 } 4251 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 4252 4253 /** 4254 * drm_default_rgb_quant_range - default RGB quantization range 4255 * @mode: display mode 4256 * 4257 * Determine the default RGB quantization range for the mode, 4258 * as specified in CEA-861. 4259 * 4260 * Return: The default RGB quantization range for the mode 4261 */ 4262 enum hdmi_quantization_range 4263 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4264 { 4265 /* All CEA modes other than VIC 1 use limited quantization range. */ 4266 return drm_match_cea_mode(mode) > 1 ? 4267 HDMI_QUANTIZATION_RANGE_LIMITED : 4268 HDMI_QUANTIZATION_RANGE_FULL; 4269 } 4270 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4271 4272 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4273 const u8 *db) 4274 { 4275 u8 dc_mask; 4276 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4277 4278 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4279 hdmi->y420_dc_modes |= dc_mask; 4280 } 4281 4282 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4283 const u8 *hf_vsdb) 4284 { 4285 struct drm_display_info *display = &connector->display_info; 4286 struct drm_hdmi_info *hdmi = &display->hdmi; 4287 4288 display->has_hdmi_infoframe = true; 4289 4290 if (hf_vsdb[6] & 0x80) { 4291 hdmi->scdc.supported = true; 4292 if (hf_vsdb[6] & 0x40) 4293 hdmi->scdc.read_request = true; 4294 } 4295 4296 /* 4297 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4298 * And as per the spec, three factors confirm this: 4299 * * Availability of a HF-VSDB block in EDID (check) 4300 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4301 * * SCDC support available (let's check) 4302 * Lets check it out. 4303 */ 4304 4305 if (hf_vsdb[5]) { 4306 /* max clock is 5000 KHz times block value */ 4307 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4308 struct drm_scdc *scdc = &hdmi->scdc; 4309 4310 if (max_tmds_clock > 340000) { 4311 display->max_tmds_clock = max_tmds_clock; 4312 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4313 display->max_tmds_clock); 4314 } 4315 4316 if (scdc->supported) { 4317 scdc->scrambling.supported = true; 4318 4319 /* Few sinks support scrambling for cloks < 340M */ 4320 if ((hf_vsdb[6] & 0x8)) 4321 scdc->scrambling.low_rates = true; 4322 } 4323 } 4324 4325 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4326 } 4327 4328 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4329 const u8 *hdmi) 4330 { 4331 struct drm_display_info *info = &connector->display_info; 4332 unsigned int dc_bpc = 0; 4333 4334 /* HDMI supports at least 8 bpc */ 4335 info->bpc = 8; 4336 4337 if (cea_db_payload_len(hdmi) < 6) 4338 return; 4339 4340 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4341 dc_bpc = 10; 4342 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4343 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4344 connector->name); 4345 } 4346 4347 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4348 dc_bpc = 12; 4349 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4350 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4351 connector->name); 4352 } 4353 4354 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4355 dc_bpc = 16; 4356 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4357 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4358 connector->name); 4359 } 4360 4361 if (dc_bpc == 0) { 4362 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4363 connector->name); 4364 return; 4365 } 4366 4367 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4368 connector->name, dc_bpc); 4369 info->bpc = dc_bpc; 4370 4371 /* 4372 * Deep color support mandates RGB444 support for all video 4373 * modes and forbids YCRCB422 support for all video modes per 4374 * HDMI 1.3 spec. 4375 */ 4376 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4377 4378 /* YCRCB444 is optional according to spec. */ 4379 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4380 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4381 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4382 connector->name); 4383 } 4384 4385 /* 4386 * Spec says that if any deep color mode is supported at all, 4387 * then deep color 36 bit must be supported. 4388 */ 4389 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4390 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4391 connector->name); 4392 } 4393 } 4394 4395 static void 4396 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4397 { 4398 struct drm_display_info *info = &connector->display_info; 4399 u8 len = cea_db_payload_len(db); 4400 4401 if (len >= 6) 4402 info->dvi_dual = db[6] & 1; 4403 if (len >= 7) 4404 info->max_tmds_clock = db[7] * 5000; 4405 4406 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4407 "max TMDS clock %d kHz\n", 4408 info->dvi_dual, 4409 info->max_tmds_clock); 4410 4411 drm_parse_hdmi_deep_color_info(connector, db); 4412 } 4413 4414 static void drm_parse_cea_ext(struct drm_connector *connector, 4415 const struct edid *edid) 4416 { 4417 struct drm_display_info *info = &connector->display_info; 4418 const u8 *edid_ext; 4419 int i, start, end; 4420 4421 edid_ext = drm_find_cea_extension(edid); 4422 if (!edid_ext) 4423 return; 4424 4425 info->cea_rev = edid_ext[1]; 4426 4427 /* The existence of a CEA block should imply RGB support */ 4428 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4429 if (edid_ext[3] & EDID_CEA_YCRCB444) 4430 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4431 if (edid_ext[3] & EDID_CEA_YCRCB422) 4432 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4433 4434 if (cea_db_offsets(edid_ext, &start, &end)) 4435 return; 4436 4437 for_each_cea_db(edid_ext, i, start, end) { 4438 const u8 *db = &edid_ext[i]; 4439 4440 if (cea_db_is_hdmi_vsdb(db)) 4441 drm_parse_hdmi_vsdb_video(connector, db); 4442 if (cea_db_is_hdmi_forum_vsdb(db)) 4443 drm_parse_hdmi_forum_vsdb(connector, db); 4444 if (cea_db_is_y420cmdb(db)) 4445 drm_parse_y420cmdb_bitmap(connector, db); 4446 } 4447 } 4448 4449 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4450 * all of the values which would have been set from EDID 4451 */ 4452 void 4453 drm_reset_display_info(struct drm_connector *connector) 4454 { 4455 struct drm_display_info *info = &connector->display_info; 4456 4457 info->width_mm = 0; 4458 info->height_mm = 0; 4459 4460 info->bpc = 0; 4461 info->color_formats = 0; 4462 info->cea_rev = 0; 4463 info->max_tmds_clock = 0; 4464 info->dvi_dual = false; 4465 info->has_hdmi_infoframe = false; 4466 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4467 4468 info->non_desktop = 0; 4469 } 4470 4471 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4472 { 4473 struct drm_display_info *info = &connector->display_info; 4474 4475 u32 quirks = edid_get_quirks(edid); 4476 4477 drm_reset_display_info(connector); 4478 4479 info->width_mm = edid->width_cm * 10; 4480 info->height_mm = edid->height_cm * 10; 4481 4482 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4483 4484 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4485 4486 if (edid->revision < 3) 4487 return quirks; 4488 4489 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4490 return quirks; 4491 4492 drm_parse_cea_ext(connector, edid); 4493 4494 /* 4495 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4496 * 4497 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4498 * tells us to assume 8 bpc color depth if the EDID doesn't have 4499 * extensions which tell otherwise. 4500 */ 4501 if ((info->bpc == 0) && (edid->revision < 4) && 4502 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4503 info->bpc = 8; 4504 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4505 connector->name, info->bpc); 4506 } 4507 4508 /* Only defined for 1.4 with digital displays */ 4509 if (edid->revision < 4) 4510 return quirks; 4511 4512 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4513 case DRM_EDID_DIGITAL_DEPTH_6: 4514 info->bpc = 6; 4515 break; 4516 case DRM_EDID_DIGITAL_DEPTH_8: 4517 info->bpc = 8; 4518 break; 4519 case DRM_EDID_DIGITAL_DEPTH_10: 4520 info->bpc = 10; 4521 break; 4522 case DRM_EDID_DIGITAL_DEPTH_12: 4523 info->bpc = 12; 4524 break; 4525 case DRM_EDID_DIGITAL_DEPTH_14: 4526 info->bpc = 14; 4527 break; 4528 case DRM_EDID_DIGITAL_DEPTH_16: 4529 info->bpc = 16; 4530 break; 4531 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4532 default: 4533 info->bpc = 0; 4534 break; 4535 } 4536 4537 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4538 connector->name, info->bpc); 4539 4540 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4541 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4542 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4543 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4544 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4545 return quirks; 4546 } 4547 4548 static int validate_displayid(u8 *displayid, int length, int idx) 4549 { 4550 int i; 4551 u8 csum = 0; 4552 struct displayid_hdr *base; 4553 4554 base = (struct displayid_hdr *)&displayid[idx]; 4555 4556 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4557 base->rev, base->bytes, base->prod_id, base->ext_count); 4558 4559 if (base->bytes + 5 > length - idx) 4560 return -EINVAL; 4561 for (i = idx; i <= base->bytes + 5; i++) { 4562 csum += displayid[i]; 4563 } 4564 if (csum) { 4565 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4566 return -EINVAL; 4567 } 4568 return 0; 4569 } 4570 4571 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4572 struct displayid_detailed_timings_1 *timings) 4573 { 4574 struct drm_display_mode *mode; 4575 unsigned pixel_clock = (timings->pixel_clock[0] | 4576 (timings->pixel_clock[1] << 8) | 4577 (timings->pixel_clock[2] << 16)); 4578 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4579 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4580 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4581 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4582 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4583 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4584 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4585 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4586 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4587 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4588 mode = drm_mode_create(dev); 4589 if (!mode) 4590 return NULL; 4591 4592 mode->clock = pixel_clock * 10; 4593 mode->hdisplay = hactive; 4594 mode->hsync_start = mode->hdisplay + hsync; 4595 mode->hsync_end = mode->hsync_start + hsync_width; 4596 mode->htotal = mode->hdisplay + hblank; 4597 4598 mode->vdisplay = vactive; 4599 mode->vsync_start = mode->vdisplay + vsync; 4600 mode->vsync_end = mode->vsync_start + vsync_width; 4601 mode->vtotal = mode->vdisplay + vblank; 4602 4603 mode->flags = 0; 4604 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4605 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4606 mode->type = DRM_MODE_TYPE_DRIVER; 4607 4608 if (timings->flags & 0x80) 4609 mode->type |= DRM_MODE_TYPE_PREFERRED; 4610 mode->vrefresh = drm_mode_vrefresh(mode); 4611 drm_mode_set_name(mode); 4612 4613 return mode; 4614 } 4615 4616 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4617 struct displayid_block *block) 4618 { 4619 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4620 int i; 4621 int num_timings; 4622 struct drm_display_mode *newmode; 4623 int num_modes = 0; 4624 /* blocks must be multiple of 20 bytes length */ 4625 if (block->num_bytes % 20) 4626 return 0; 4627 4628 num_timings = block->num_bytes / 20; 4629 for (i = 0; i < num_timings; i++) { 4630 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4631 4632 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4633 if (!newmode) 4634 continue; 4635 4636 drm_mode_probed_add(connector, newmode); 4637 num_modes++; 4638 } 4639 return num_modes; 4640 } 4641 4642 static int add_displayid_detailed_modes(struct drm_connector *connector, 4643 struct edid *edid) 4644 { 4645 u8 *displayid; 4646 int ret; 4647 int idx = 1; 4648 int length = EDID_LENGTH; 4649 struct displayid_block *block; 4650 int num_modes = 0; 4651 4652 displayid = drm_find_displayid_extension(edid); 4653 if (!displayid) 4654 return 0; 4655 4656 ret = validate_displayid(displayid, length, idx); 4657 if (ret) 4658 return 0; 4659 4660 idx += sizeof(struct displayid_hdr); 4661 while (block = (struct displayid_block *)&displayid[idx], 4662 idx + sizeof(struct displayid_block) <= length && 4663 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4664 block->num_bytes > 0) { 4665 idx += block->num_bytes + sizeof(struct displayid_block); 4666 switch (block->tag) { 4667 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4668 num_modes += add_displayid_detailed_1_modes(connector, block); 4669 break; 4670 } 4671 } 4672 return num_modes; 4673 } 4674 4675 /** 4676 * drm_add_edid_modes - add modes from EDID data, if available 4677 * @connector: connector we're probing 4678 * @edid: EDID data 4679 * 4680 * Add the specified modes to the connector's mode list. Also fills out the 4681 * &drm_display_info structure and ELD in @connector with any information which 4682 * can be derived from the edid. 4683 * 4684 * Return: The number of modes added or 0 if we couldn't find any. 4685 */ 4686 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4687 { 4688 int num_modes = 0; 4689 u32 quirks; 4690 4691 if (edid == NULL) { 4692 clear_eld(connector); 4693 return 0; 4694 } 4695 if (!drm_edid_is_valid(edid)) { 4696 clear_eld(connector); 4697 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4698 connector->name); 4699 return 0; 4700 } 4701 4702 drm_edid_to_eld(connector, edid); 4703 4704 /* 4705 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4706 * To avoid multiple parsing of same block, lets parse that map 4707 * from sink info, before parsing CEA modes. 4708 */ 4709 quirks = drm_add_display_info(connector, edid); 4710 4711 /* 4712 * EDID spec says modes should be preferred in this order: 4713 * - preferred detailed mode 4714 * - other detailed modes from base block 4715 * - detailed modes from extension blocks 4716 * - CVT 3-byte code modes 4717 * - standard timing codes 4718 * - established timing codes 4719 * - modes inferred from GTF or CVT range information 4720 * 4721 * We get this pretty much right. 4722 * 4723 * XXX order for additional mode types in extension blocks? 4724 */ 4725 num_modes += add_detailed_modes(connector, edid, quirks); 4726 num_modes += add_cvt_modes(connector, edid); 4727 num_modes += add_standard_modes(connector, edid); 4728 num_modes += add_established_modes(connector, edid); 4729 num_modes += add_cea_modes(connector, edid); 4730 num_modes += add_alternate_cea_modes(connector, edid); 4731 num_modes += add_displayid_detailed_modes(connector, edid); 4732 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4733 num_modes += add_inferred_modes(connector, edid); 4734 4735 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4736 edid_fixup_preferred(connector, quirks); 4737 4738 if (quirks & EDID_QUIRK_FORCE_6BPC) 4739 connector->display_info.bpc = 6; 4740 4741 if (quirks & EDID_QUIRK_FORCE_8BPC) 4742 connector->display_info.bpc = 8; 4743 4744 if (quirks & EDID_QUIRK_FORCE_10BPC) 4745 connector->display_info.bpc = 10; 4746 4747 if (quirks & EDID_QUIRK_FORCE_12BPC) 4748 connector->display_info.bpc = 12; 4749 4750 return num_modes; 4751 } 4752 EXPORT_SYMBOL(drm_add_edid_modes); 4753 4754 /** 4755 * drm_add_modes_noedid - add modes for the connectors without EDID 4756 * @connector: connector we're probing 4757 * @hdisplay: the horizontal display limit 4758 * @vdisplay: the vertical display limit 4759 * 4760 * Add the specified modes to the connector's mode list. Only when the 4761 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4762 * 4763 * Return: The number of modes added or 0 if we couldn't find any. 4764 */ 4765 int drm_add_modes_noedid(struct drm_connector *connector, 4766 int hdisplay, int vdisplay) 4767 { 4768 int i, count, num_modes = 0; 4769 struct drm_display_mode *mode; 4770 struct drm_device *dev = connector->dev; 4771 4772 count = ARRAY_SIZE(drm_dmt_modes); 4773 if (hdisplay < 0) 4774 hdisplay = 0; 4775 if (vdisplay < 0) 4776 vdisplay = 0; 4777 4778 for (i = 0; i < count; i++) { 4779 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4780 if (hdisplay && vdisplay) { 4781 /* 4782 * Only when two are valid, they will be used to check 4783 * whether the mode should be added to the mode list of 4784 * the connector. 4785 */ 4786 if (ptr->hdisplay > hdisplay || 4787 ptr->vdisplay > vdisplay) 4788 continue; 4789 } 4790 if (drm_mode_vrefresh(ptr) > 61) 4791 continue; 4792 mode = drm_mode_duplicate(dev, ptr); 4793 if (mode) { 4794 drm_mode_probed_add(connector, mode); 4795 num_modes++; 4796 } 4797 } 4798 return num_modes; 4799 } 4800 EXPORT_SYMBOL(drm_add_modes_noedid); 4801 4802 /** 4803 * drm_set_preferred_mode - Sets the preferred mode of a connector 4804 * @connector: connector whose mode list should be processed 4805 * @hpref: horizontal resolution of preferred mode 4806 * @vpref: vertical resolution of preferred mode 4807 * 4808 * Marks a mode as preferred if it matches the resolution specified by @hpref 4809 * and @vpref. 4810 */ 4811 void drm_set_preferred_mode(struct drm_connector *connector, 4812 int hpref, int vpref) 4813 { 4814 struct drm_display_mode *mode; 4815 4816 list_for_each_entry(mode, &connector->probed_modes, head) { 4817 if (mode->hdisplay == hpref && 4818 mode->vdisplay == vpref) 4819 mode->type |= DRM_MODE_TYPE_PREFERRED; 4820 } 4821 } 4822 EXPORT_SYMBOL(drm_set_preferred_mode); 4823 4824 /** 4825 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4826 * data from a DRM display mode 4827 * @frame: HDMI AVI infoframe 4828 * @mode: DRM display mode 4829 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant 4830 * 4831 * Return: 0 on success or a negative error code on failure. 4832 */ 4833 int 4834 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4835 const struct drm_display_mode *mode, 4836 bool is_hdmi2_sink) 4837 { 4838 enum hdmi_picture_aspect picture_aspect; 4839 int err; 4840 4841 if (!frame || !mode) 4842 return -EINVAL; 4843 4844 err = hdmi_avi_infoframe_init(frame); 4845 if (err < 0) 4846 return err; 4847 4848 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4849 frame->pixel_repeat = 1; 4850 4851 frame->video_code = drm_match_cea_mode(mode); 4852 4853 /* 4854 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4855 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4856 * have to make sure we dont break HDMI 1.4 sinks. 4857 */ 4858 if (!is_hdmi2_sink && frame->video_code > 64) 4859 frame->video_code = 0; 4860 4861 /* 4862 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 4863 * we should send its VIC in vendor infoframes, else send the 4864 * VIC in AVI infoframes. Lets check if this mode is present in 4865 * HDMI 1.4b 4K modes 4866 */ 4867 if (frame->video_code) { 4868 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 4869 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 4870 4871 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 4872 frame->video_code = 0; 4873 } 4874 4875 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4876 4877 /* 4878 * As some drivers don't support atomic, we can't use connector state. 4879 * So just initialize the frame with default values, just the same way 4880 * as it's done with other properties here. 4881 */ 4882 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 4883 frame->itc = 0; 4884 4885 /* 4886 * Populate picture aspect ratio from either 4887 * user input (if specified) or from the CEA mode list. 4888 */ 4889 picture_aspect = mode->picture_aspect_ratio; 4890 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 4891 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 4892 4893 /* 4894 * The infoframe can't convey anything but none, 4:3 4895 * and 16:9, so if the user has asked for anything else 4896 * we can only satisfy it by specifying the right VIC. 4897 */ 4898 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 4899 if (picture_aspect != 4900 drm_get_cea_aspect_ratio(frame->video_code)) 4901 return -EINVAL; 4902 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4903 } 4904 4905 frame->picture_aspect = picture_aspect; 4906 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4907 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4908 4909 return 0; 4910 } 4911 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4912 4913 /** 4914 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4915 * quantization range information 4916 * @frame: HDMI AVI infoframe 4917 * @mode: DRM display mode 4918 * @rgb_quant_range: RGB quantization range (Q) 4919 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 4920 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations 4921 * 4922 * Note that @is_hdmi2_sink can be derived by looking at the 4923 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc, 4924 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info. 4925 */ 4926 void 4927 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 4928 const struct drm_display_mode *mode, 4929 enum hdmi_quantization_range rgb_quant_range, 4930 bool rgb_quant_range_selectable, 4931 bool is_hdmi2_sink) 4932 { 4933 /* 4934 * CEA-861: 4935 * "A Source shall not send a non-zero Q value that does not correspond 4936 * to the default RGB Quantization Range for the transmitted Picture 4937 * unless the Sink indicates support for the Q bit in a Video 4938 * Capabilities Data Block." 4939 * 4940 * HDMI 2.0 recommends sending non-zero Q when it does match the 4941 * default RGB quantization range for the mode, even when QS=0. 4942 */ 4943 if (rgb_quant_range_selectable || 4944 rgb_quant_range == drm_default_rgb_quant_range(mode)) 4945 frame->quantization_range = rgb_quant_range; 4946 else 4947 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 4948 4949 /* 4950 * CEA-861-F: 4951 * "When transmitting any RGB colorimetry, the Source should set the 4952 * YQ-field to match the RGB Quantization Range being transmitted 4953 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 4954 * set YQ=1) and the Sink shall ignore the YQ-field." 4955 * 4956 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 4957 * by non-zero YQ when receiving RGB. There doesn't seem to be any 4958 * good way to tell which version of CEA-861 the sink supports, so 4959 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 4960 * on on CEA-861-F. 4961 */ 4962 if (!is_hdmi2_sink || 4963 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4964 frame->ycc_quantization_range = 4965 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 4966 else 4967 frame->ycc_quantization_range = 4968 HDMI_YCC_QUANTIZATION_RANGE_FULL; 4969 } 4970 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 4971 4972 static enum hdmi_3d_structure 4973 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4974 { 4975 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4976 4977 switch (layout) { 4978 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4979 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4980 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4981 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4982 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4983 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4984 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4985 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4986 case DRM_MODE_FLAG_3D_L_DEPTH: 4987 return HDMI_3D_STRUCTURE_L_DEPTH; 4988 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4989 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4990 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4991 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4992 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4993 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4994 default: 4995 return HDMI_3D_STRUCTURE_INVALID; 4996 } 4997 } 4998 4999 /** 5000 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5001 * data from a DRM display mode 5002 * @frame: HDMI vendor infoframe 5003 * @connector: the connector 5004 * @mode: DRM display mode 5005 * 5006 * Note that there's is a need to send HDMI vendor infoframes only when using a 5007 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5008 * function will return -EINVAL, error that can be safely ignored. 5009 * 5010 * Return: 0 on success or a negative error code on failure. 5011 */ 5012 int 5013 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5014 struct drm_connector *connector, 5015 const struct drm_display_mode *mode) 5016 { 5017 /* 5018 * FIXME: sil-sii8620 doesn't have a connector around when 5019 * we need one, so we have to be prepared for a NULL connector. 5020 */ 5021 bool has_hdmi_infoframe = connector ? 5022 connector->display_info.has_hdmi_infoframe : false; 5023 int err; 5024 u32 s3d_flags; 5025 u8 vic; 5026 5027 if (!frame || !mode) 5028 return -EINVAL; 5029 5030 if (!has_hdmi_infoframe) 5031 return -EINVAL; 5032 5033 vic = drm_match_hdmi_mode(mode); 5034 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5035 5036 /* 5037 * Even if it's not absolutely necessary to send the infoframe 5038 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5039 * know that the sink can handle it. This is based on a 5040 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5041 * have trouble realizing that they shuld switch from 3D to 2D 5042 * mode if the source simply stops sending the infoframe when 5043 * it wants to switch from 3D to 2D. 5044 */ 5045 5046 if (vic && s3d_flags) 5047 return -EINVAL; 5048 5049 err = hdmi_vendor_infoframe_init(frame); 5050 if (err < 0) 5051 return err; 5052 5053 frame->vic = vic; 5054 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5055 5056 return 0; 5057 } 5058 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5059 5060 static int drm_parse_tiled_block(struct drm_connector *connector, 5061 struct displayid_block *block) 5062 { 5063 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5064 u16 w, h; 5065 u8 tile_v_loc, tile_h_loc; 5066 u8 num_v_tile, num_h_tile; 5067 struct drm_tile_group *tg; 5068 5069 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5070 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5071 5072 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5073 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5074 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5075 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5076 5077 connector->has_tile = true; 5078 if (tile->tile_cap & 0x80) 5079 connector->tile_is_single_monitor = true; 5080 5081 connector->num_h_tile = num_h_tile + 1; 5082 connector->num_v_tile = num_v_tile + 1; 5083 connector->tile_h_loc = tile_h_loc; 5084 connector->tile_v_loc = tile_v_loc; 5085 connector->tile_h_size = w + 1; 5086 connector->tile_v_size = h + 1; 5087 5088 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5089 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5090 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5091 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5092 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5093 5094 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5095 if (!tg) { 5096 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5097 } 5098 if (!tg) 5099 return -ENOMEM; 5100 5101 if (connector->tile_group != tg) { 5102 /* if we haven't got a pointer, 5103 take the reference, drop ref to old tile group */ 5104 if (connector->tile_group) { 5105 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5106 } 5107 connector->tile_group = tg; 5108 } else 5109 /* if same tile group, then release the ref we just took. */ 5110 drm_mode_put_tile_group(connector->dev, tg); 5111 return 0; 5112 } 5113 5114 static int drm_parse_display_id(struct drm_connector *connector, 5115 u8 *displayid, int length, 5116 bool is_edid_extension) 5117 { 5118 /* if this is an EDID extension the first byte will be 0x70 */ 5119 int idx = 0; 5120 struct displayid_block *block; 5121 int ret; 5122 5123 if (is_edid_extension) 5124 idx = 1; 5125 5126 ret = validate_displayid(displayid, length, idx); 5127 if (ret) 5128 return ret; 5129 5130 idx += sizeof(struct displayid_hdr); 5131 while (block = (struct displayid_block *)&displayid[idx], 5132 idx + sizeof(struct displayid_block) <= length && 5133 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5134 block->num_bytes > 0) { 5135 idx += block->num_bytes + sizeof(struct displayid_block); 5136 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5137 block->tag, block->rev, block->num_bytes); 5138 5139 switch (block->tag) { 5140 case DATA_BLOCK_TILED_DISPLAY: 5141 ret = drm_parse_tiled_block(connector, block); 5142 if (ret) 5143 return ret; 5144 break; 5145 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5146 /* handled in mode gathering code. */ 5147 break; 5148 default: 5149 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5150 break; 5151 } 5152 } 5153 return 0; 5154 } 5155 5156 static void drm_get_displayid(struct drm_connector *connector, 5157 struct edid *edid) 5158 { 5159 void *displayid = NULL; 5160 int ret; 5161 connector->has_tile = false; 5162 displayid = drm_find_displayid_extension(edid); 5163 if (!displayid) { 5164 /* drop reference to any tile group we had */ 5165 goto out_drop_ref; 5166 } 5167 5168 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5169 if (ret < 0) 5170 goto out_drop_ref; 5171 if (!connector->has_tile) 5172 goto out_drop_ref; 5173 return; 5174 out_drop_ref: 5175 if (connector->tile_group) { 5176 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5177 connector->tile_group = NULL; 5178 } 5179 return; 5180 } 5181