1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 #include <linux/vga_switcheroo.h> 38 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_encoder.h> 43 #include <drm/drm_print.h> 44 #include <drm/drm_scdc_helper.h> 45 46 #include "drm_crtc_internal.h" 47 48 #define version_greater(edid, maj, min) \ 49 (((edid)->version > (maj)) || \ 50 ((edid)->version == (maj) && (edid)->revision > (min))) 51 52 #define EDID_EST_TIMINGS 16 53 #define EDID_STD_TIMINGS 8 54 #define EDID_DETAILED_TIMINGS 4 55 56 /* 57 * EDID blocks out in the wild have a variety of bugs, try to collect 58 * them here (note that userspace may work around broken monitors first, 59 * but fixes should make their way here so that the kernel "just works" 60 * on as many displays as possible). 61 */ 62 63 /* First detailed mode wrong, use largest 60Hz mode */ 64 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 65 /* Reported 135MHz pixel clock is too high, needs adjustment */ 66 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 67 /* Prefer the largest mode at 75 Hz */ 68 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 69 /* Detail timing is in cm not mm */ 70 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 71 /* Detailed timing descriptors have bogus size values, so just take the 72 * maximum size and use that. 73 */ 74 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 75 /* use +hsync +vsync for detailed mode */ 76 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 77 /* Force reduced-blanking timings for detailed modes */ 78 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 79 /* Force 8bpc */ 80 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 81 /* Force 12bpc */ 82 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 83 /* Force 6bpc */ 84 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 85 /* Force 10bpc */ 86 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 87 /* Non desktop display (i.e. HMD) */ 88 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 89 90 struct detailed_mode_closure { 91 struct drm_connector *connector; 92 struct edid *edid; 93 bool preferred; 94 u32 quirks; 95 int modes; 96 }; 97 98 #define LEVEL_DMT 0 99 #define LEVEL_GTF 1 100 #define LEVEL_GTF2 2 101 #define LEVEL_CVT 3 102 103 static const struct edid_quirk { 104 char vendor[4]; 105 int product_id; 106 u32 quirks; 107 } edid_quirk_list[] = { 108 /* Acer AL1706 */ 109 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Acer F51 */ 111 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 118 119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 121 122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 124 125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 127 128 /* Belinea 10 15 55 */ 129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 131 132 /* Envision Peripherals, Inc. EN-7100e */ 133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 134 /* Envision EN2028 */ 135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 136 137 /* Funai Electronics PM36B */ 138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 139 EDID_QUIRK_DETAILED_IN_CM }, 140 141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 143 144 /* LG Philips LCD LP154W01-A5 */ 145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 147 148 /* Samsung SyncMaster 205BW. Note: irony */ 149 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 150 /* Samsung SyncMaster 22[5-6]BW */ 151 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 152 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 153 154 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 155 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 156 157 /* ViewSonic VA2026w */ 158 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 159 160 /* Medion MD 30217 PG */ 161 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 162 163 /* Lenovo G50 */ 164 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 165 166 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 167 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 168 169 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 170 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 171 172 /* Valve Index Headset */ 173 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 189 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 190 191 /* HTC Vive and Vive Pro VR Headsets */ 192 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 193 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 194 195 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 196 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 199 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 200 201 /* Windows Mixed Reality Headsets */ 202 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 203 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 205 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 206 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 207 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 208 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 209 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 210 211 /* Sony PlayStation VR Headset */ 212 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 213 214 /* Sensics VR Headsets */ 215 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 216 217 /* OSVR HDK and HDK2 VR Headsets */ 218 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 219 }; 220 221 /* 222 * Autogenerated from the DMT spec. 223 * This table is copied from xfree86/modes/xf86EdidModes.c. 224 */ 225 static const struct drm_display_mode drm_dmt_modes[] = { 226 /* 0x01 - 640x350@85Hz */ 227 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 228 736, 832, 0, 350, 382, 385, 445, 0, 229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 230 /* 0x02 - 640x400@85Hz */ 231 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 232 736, 832, 0, 400, 401, 404, 445, 0, 233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 234 /* 0x03 - 720x400@85Hz */ 235 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 236 828, 936, 0, 400, 401, 404, 446, 0, 237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 238 /* 0x04 - 640x480@60Hz */ 239 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 240 752, 800, 0, 480, 490, 492, 525, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 242 /* 0x05 - 640x480@72Hz */ 243 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 244 704, 832, 0, 480, 489, 492, 520, 0, 245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 246 /* 0x06 - 640x480@75Hz */ 247 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 248 720, 840, 0, 480, 481, 484, 500, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 250 /* 0x07 - 640x480@85Hz */ 251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 252 752, 832, 0, 480, 481, 484, 509, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 254 /* 0x08 - 800x600@56Hz */ 255 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 256 896, 1024, 0, 600, 601, 603, 625, 0, 257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 258 /* 0x09 - 800x600@60Hz */ 259 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 260 968, 1056, 0, 600, 601, 605, 628, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 262 /* 0x0a - 800x600@72Hz */ 263 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 264 976, 1040, 0, 600, 637, 643, 666, 0, 265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 266 /* 0x0b - 800x600@75Hz */ 267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 268 896, 1056, 0, 600, 601, 604, 625, 0, 269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 270 /* 0x0c - 800x600@85Hz */ 271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 272 896, 1048, 0, 600, 601, 604, 631, 0, 273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x0d - 800x600@120Hz RB */ 275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 276 880, 960, 0, 600, 603, 607, 636, 0, 277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 278 /* 0x0e - 848x480@60Hz */ 279 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 280 976, 1088, 0, 480, 486, 494, 517, 0, 281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x0f - 1024x768@43Hz, interlace */ 283 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 284 1208, 1264, 0, 768, 768, 776, 817, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 286 DRM_MODE_FLAG_INTERLACE) }, 287 /* 0x10 - 1024x768@60Hz */ 288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 289 1184, 1344, 0, 768, 771, 777, 806, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 291 /* 0x11 - 1024x768@70Hz */ 292 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 293 1184, 1328, 0, 768, 771, 777, 806, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 295 /* 0x12 - 1024x768@75Hz */ 296 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 297 1136, 1312, 0, 768, 769, 772, 800, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 299 /* 0x13 - 1024x768@85Hz */ 300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 301 1168, 1376, 0, 768, 769, 772, 808, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 303 /* 0x14 - 1024x768@120Hz RB */ 304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 305 1104, 1184, 0, 768, 771, 775, 813, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 307 /* 0x15 - 1152x864@75Hz */ 308 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 309 1344, 1600, 0, 864, 865, 868, 900, 0, 310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 0x55 - 1280x720@60Hz */ 312 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 313 1430, 1650, 0, 720, 725, 730, 750, 0, 314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 0x16 - 1280x768@60Hz RB */ 316 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 317 1360, 1440, 0, 768, 771, 778, 790, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 319 /* 0x17 - 1280x768@60Hz */ 320 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 321 1472, 1664, 0, 768, 771, 778, 798, 0, 322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 323 /* 0x18 - 1280x768@75Hz */ 324 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 325 1488, 1696, 0, 768, 771, 778, 805, 0, 326 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 0x19 - 1280x768@85Hz */ 328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 329 1496, 1712, 0, 768, 771, 778, 809, 0, 330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 331 /* 0x1a - 1280x768@120Hz RB */ 332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 333 1360, 1440, 0, 768, 771, 778, 813, 0, 334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 335 /* 0x1b - 1280x800@60Hz RB */ 336 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 337 1360, 1440, 0, 800, 803, 809, 823, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 339 /* 0x1c - 1280x800@60Hz */ 340 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 341 1480, 1680, 0, 800, 803, 809, 831, 0, 342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 0x1d - 1280x800@75Hz */ 344 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 345 1488, 1696, 0, 800, 803, 809, 838, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 0x1e - 1280x800@85Hz */ 348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 349 1496, 1712, 0, 800, 803, 809, 843, 0, 350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 351 /* 0x1f - 1280x800@120Hz RB */ 352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 353 1360, 1440, 0, 800, 803, 809, 847, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 355 /* 0x20 - 1280x960@60Hz */ 356 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 357 1488, 1800, 0, 960, 961, 964, 1000, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 0x21 - 1280x960@85Hz */ 360 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 361 1504, 1728, 0, 960, 961, 964, 1011, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 363 /* 0x22 - 1280x960@120Hz RB */ 364 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 365 1360, 1440, 0, 960, 963, 967, 1017, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 367 /* 0x23 - 1280x1024@60Hz */ 368 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 369 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 0x24 - 1280x1024@75Hz */ 372 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 373 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 0x25 - 1280x1024@85Hz */ 376 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 377 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 379 /* 0x26 - 1280x1024@120Hz RB */ 380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 381 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 383 /* 0x27 - 1360x768@60Hz */ 384 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 385 1536, 1792, 0, 768, 771, 777, 795, 0, 386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 0x28 - 1360x768@120Hz RB */ 388 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 389 1440, 1520, 0, 768, 771, 776, 813, 0, 390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 391 /* 0x51 - 1366x768@60Hz */ 392 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 393 1579, 1792, 0, 768, 771, 774, 798, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 395 /* 0x56 - 1366x768@60Hz */ 396 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 397 1436, 1500, 0, 768, 769, 772, 800, 0, 398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 0x29 - 1400x1050@60Hz RB */ 400 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 401 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 403 /* 0x2a - 1400x1050@60Hz */ 404 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 405 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 407 /* 0x2b - 1400x1050@75Hz */ 408 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 409 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 411 /* 0x2c - 1400x1050@85Hz */ 412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 413 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 0x2d - 1400x1050@120Hz RB */ 416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 417 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 419 /* 0x2e - 1440x900@60Hz RB */ 420 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 421 1520, 1600, 0, 900, 903, 909, 926, 0, 422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 423 /* 0x2f - 1440x900@60Hz */ 424 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 425 1672, 1904, 0, 900, 903, 909, 934, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 427 /* 0x30 - 1440x900@75Hz */ 428 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 429 1688, 1936, 0, 900, 903, 909, 942, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 0x31 - 1440x900@85Hz */ 432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 433 1696, 1952, 0, 900, 903, 909, 948, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 435 /* 0x32 - 1440x900@120Hz RB */ 436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 437 1520, 1600, 0, 900, 903, 909, 953, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 439 /* 0x53 - 1600x900@60Hz */ 440 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 441 1704, 1800, 0, 900, 901, 904, 1000, 0, 442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 443 /* 0x33 - 1600x1200@60Hz */ 444 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 445 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 0x34 - 1600x1200@65Hz */ 448 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 449 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 451 /* 0x35 - 1600x1200@70Hz */ 452 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 453 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 0x36 - 1600x1200@75Hz */ 456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 0x37 - 1600x1200@85Hz */ 460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 463 /* 0x38 - 1600x1200@120Hz RB */ 464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 465 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 467 /* 0x39 - 1680x1050@60Hz RB */ 468 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 469 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 471 /* 0x3a - 1680x1050@60Hz */ 472 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 473 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 475 /* 0x3b - 1680x1050@75Hz */ 476 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 477 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 479 /* 0x3c - 1680x1050@85Hz */ 480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 481 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 483 /* 0x3d - 1680x1050@120Hz RB */ 484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 485 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 487 /* 0x3e - 1792x1344@60Hz */ 488 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 489 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 491 /* 0x3f - 1792x1344@75Hz */ 492 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 493 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 495 /* 0x40 - 1792x1344@120Hz RB */ 496 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 497 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 499 /* 0x41 - 1856x1392@60Hz */ 500 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 501 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 503 /* 0x42 - 1856x1392@75Hz */ 504 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 505 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 507 /* 0x43 - 1856x1392@120Hz RB */ 508 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 509 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 511 /* 0x52 - 1920x1080@60Hz */ 512 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 513 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 515 /* 0x44 - 1920x1200@60Hz RB */ 516 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 517 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 519 /* 0x45 - 1920x1200@60Hz */ 520 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 521 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 523 /* 0x46 - 1920x1200@75Hz */ 524 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 525 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 527 /* 0x47 - 1920x1200@85Hz */ 528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 529 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 531 /* 0x48 - 1920x1200@120Hz RB */ 532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 533 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 535 /* 0x49 - 1920x1440@60Hz */ 536 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 537 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 539 /* 0x4a - 1920x1440@75Hz */ 540 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 541 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 543 /* 0x4b - 1920x1440@120Hz RB */ 544 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 545 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 547 /* 0x54 - 2048x1152@60Hz */ 548 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 549 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 551 /* 0x4c - 2560x1600@60Hz RB */ 552 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 553 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 555 /* 0x4d - 2560x1600@60Hz */ 556 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 557 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 559 /* 0x4e - 2560x1600@75Hz */ 560 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 561 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 563 /* 0x4f - 2560x1600@85Hz */ 564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 565 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 567 /* 0x50 - 2560x1600@120Hz RB */ 568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 569 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 571 /* 0x57 - 4096x2160@60Hz RB */ 572 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 573 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 575 /* 0x58 - 4096x2160@59.94Hz RB */ 576 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 577 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 579 }; 580 581 /* 582 * These more or less come from the DMT spec. The 720x400 modes are 583 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 584 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 585 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 586 * mode. 587 * 588 * The DMT modes have been fact-checked; the rest are mild guesses. 589 */ 590 static const struct drm_display_mode edid_est_modes[] = { 591 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 592 968, 1056, 0, 600, 601, 605, 628, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 594 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 595 896, 1024, 0, 600, 601, 603, 625, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 597 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 598 720, 840, 0, 480, 481, 484, 500, 0, 599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 600 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 601 704, 832, 0, 480, 489, 492, 520, 0, 602 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 603 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 604 768, 864, 0, 480, 483, 486, 525, 0, 605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 606 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 607 752, 800, 0, 480, 490, 492, 525, 0, 608 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 609 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 610 846, 900, 0, 400, 421, 423, 449, 0, 611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 612 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 613 846, 900, 0, 400, 412, 414, 449, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 615 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 616 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 618 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 619 1136, 1312, 0, 768, 769, 772, 800, 0, 620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 621 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 622 1184, 1328, 0, 768, 771, 777, 806, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 625 1184, 1344, 0, 768, 771, 777, 806, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 627 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 628 1208, 1264, 0, 768, 768, 776, 817, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 630 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 631 928, 1152, 0, 624, 625, 628, 667, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 633 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 634 896, 1056, 0, 600, 601, 604, 625, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 636 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 637 976, 1040, 0, 600, 637, 643, 666, 0, 638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 639 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 640 1344, 1600, 0, 864, 865, 868, 900, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 642 }; 643 644 struct minimode { 645 short w; 646 short h; 647 short r; 648 short rb; 649 }; 650 651 static const struct minimode est3_modes[] = { 652 /* byte 6 */ 653 { 640, 350, 85, 0 }, 654 { 640, 400, 85, 0 }, 655 { 720, 400, 85, 0 }, 656 { 640, 480, 85, 0 }, 657 { 848, 480, 60, 0 }, 658 { 800, 600, 85, 0 }, 659 { 1024, 768, 85, 0 }, 660 { 1152, 864, 75, 0 }, 661 /* byte 7 */ 662 { 1280, 768, 60, 1 }, 663 { 1280, 768, 60, 0 }, 664 { 1280, 768, 75, 0 }, 665 { 1280, 768, 85, 0 }, 666 { 1280, 960, 60, 0 }, 667 { 1280, 960, 85, 0 }, 668 { 1280, 1024, 60, 0 }, 669 { 1280, 1024, 85, 0 }, 670 /* byte 8 */ 671 { 1360, 768, 60, 0 }, 672 { 1440, 900, 60, 1 }, 673 { 1440, 900, 60, 0 }, 674 { 1440, 900, 75, 0 }, 675 { 1440, 900, 85, 0 }, 676 { 1400, 1050, 60, 1 }, 677 { 1400, 1050, 60, 0 }, 678 { 1400, 1050, 75, 0 }, 679 /* byte 9 */ 680 { 1400, 1050, 85, 0 }, 681 { 1680, 1050, 60, 1 }, 682 { 1680, 1050, 60, 0 }, 683 { 1680, 1050, 75, 0 }, 684 { 1680, 1050, 85, 0 }, 685 { 1600, 1200, 60, 0 }, 686 { 1600, 1200, 65, 0 }, 687 { 1600, 1200, 70, 0 }, 688 /* byte 10 */ 689 { 1600, 1200, 75, 0 }, 690 { 1600, 1200, 85, 0 }, 691 { 1792, 1344, 60, 0 }, 692 { 1792, 1344, 75, 0 }, 693 { 1856, 1392, 60, 0 }, 694 { 1856, 1392, 75, 0 }, 695 { 1920, 1200, 60, 1 }, 696 { 1920, 1200, 60, 0 }, 697 /* byte 11 */ 698 { 1920, 1200, 75, 0 }, 699 { 1920, 1200, 85, 0 }, 700 { 1920, 1440, 60, 0 }, 701 { 1920, 1440, 75, 0 }, 702 }; 703 704 static const struct minimode extra_modes[] = { 705 { 1024, 576, 60, 0 }, 706 { 1366, 768, 60, 0 }, 707 { 1600, 900, 60, 0 }, 708 { 1680, 945, 60, 0 }, 709 { 1920, 1080, 60, 0 }, 710 { 2048, 1152, 60, 0 }, 711 { 2048, 1536, 60, 0 }, 712 }; 713 714 /* 715 * From CEA/CTA-861 spec. 716 * 717 * Do not access directly, instead always use cea_mode_for_vic(). 718 */ 719 static const struct drm_display_mode edid_cea_modes_1[] = { 720 /* 1 - 640x480@60Hz 4:3 */ 721 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 722 752, 800, 0, 480, 490, 492, 525, 0, 723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 724 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 725 /* 2 - 720x480@60Hz 4:3 */ 726 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 727 798, 858, 0, 480, 489, 495, 525, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 729 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 730 /* 3 - 720x480@60Hz 16:9 */ 731 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 732 798, 858, 0, 480, 489, 495, 525, 0, 733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 734 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 735 /* 4 - 1280x720@60Hz 16:9 */ 736 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 737 1430, 1650, 0, 720, 725, 730, 750, 0, 738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 740 /* 5 - 1920x1080i@60Hz 16:9 */ 741 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 742 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 744 DRM_MODE_FLAG_INTERLACE), 745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 6 - 720(1440)x480i@60Hz 4:3 */ 747 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 748 801, 858, 0, 480, 488, 494, 525, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 750 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 752 /* 7 - 720(1440)x480i@60Hz 16:9 */ 753 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 754 801, 858, 0, 480, 488, 494, 525, 0, 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 756 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 8 - 720(1440)x240@60Hz 4:3 */ 759 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 760 801, 858, 0, 240, 244, 247, 262, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 762 DRM_MODE_FLAG_DBLCLK), 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 764 /* 9 - 720(1440)x240@60Hz 16:9 */ 765 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 240, 244, 247, 262, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_DBLCLK), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 770 /* 10 - 2880x480i@60Hz 4:3 */ 771 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 772 3204, 3432, 0, 480, 488, 494, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_INTERLACE), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 776 /* 11 - 2880x480i@60Hz 16:9 */ 777 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 778 3204, 3432, 0, 480, 488, 494, 525, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_INTERLACE), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 782 /* 12 - 2880x240@60Hz 4:3 */ 783 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 784 3204, 3432, 0, 240, 244, 247, 262, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 787 /* 13 - 2880x240@60Hz 16:9 */ 788 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 789 3204, 3432, 0, 240, 244, 247, 262, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 792 /* 14 - 1440x480@60Hz 4:3 */ 793 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 794 1596, 1716, 0, 480, 489, 495, 525, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 797 /* 15 - 1440x480@60Hz 16:9 */ 798 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 799 1596, 1716, 0, 480, 489, 495, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 802 /* 16 - 1920x1080@60Hz 16:9 */ 803 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 804 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 17 - 720x576@50Hz 4:3 */ 808 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 809 796, 864, 0, 576, 581, 586, 625, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 18 - 720x576@50Hz 16:9 */ 813 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 814 796, 864, 0, 576, 581, 586, 625, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 19 - 1280x720@50Hz 16:9 */ 818 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 819 1760, 1980, 0, 720, 725, 730, 750, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 20 - 1920x1080i@50Hz 16:9 */ 823 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 824 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 826 DRM_MODE_FLAG_INTERLACE), 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 21 - 720(1440)x576i@50Hz 4:3 */ 829 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 830 795, 864, 0, 576, 580, 586, 625, 0, 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 832 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 834 /* 22 - 720(1440)x576i@50Hz 16:9 */ 835 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 836 795, 864, 0, 576, 580, 586, 625, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 838 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 23 - 720(1440)x288@50Hz 4:3 */ 841 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 842 795, 864, 0, 288, 290, 293, 312, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 844 DRM_MODE_FLAG_DBLCLK), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 846 /* 24 - 720(1440)x288@50Hz 16:9 */ 847 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 288, 290, 293, 312, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_DBLCLK), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 852 /* 25 - 2880x576i@50Hz 4:3 */ 853 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 854 3180, 3456, 0, 576, 580, 586, 625, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_INTERLACE), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 858 /* 26 - 2880x576i@50Hz 16:9 */ 859 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 860 3180, 3456, 0, 576, 580, 586, 625, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_INTERLACE), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 27 - 2880x288@50Hz 4:3 */ 865 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 866 3180, 3456, 0, 288, 290, 293, 312, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 869 /* 28 - 2880x288@50Hz 16:9 */ 870 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 871 3180, 3456, 0, 288, 290, 293, 312, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 29 - 1440x576@50Hz 4:3 */ 875 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 876 1592, 1728, 0, 576, 581, 586, 625, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 879 /* 30 - 1440x576@50Hz 16:9 */ 880 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 881 1592, 1728, 0, 576, 581, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 884 /* 31 - 1920x1080@50Hz 16:9 */ 885 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 886 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 32 - 1920x1080@24Hz 16:9 */ 890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 891 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 33 - 1920x1080@25Hz 16:9 */ 895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 896 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 34 - 1920x1080@30Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 901 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 35 - 2880x480@60Hz 4:3 */ 905 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 906 3192, 3432, 0, 480, 489, 495, 525, 0, 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 909 /* 36 - 2880x480@60Hz 16:9 */ 910 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 911 3192, 3432, 0, 480, 489, 495, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 37 - 2880x576@50Hz 4:3 */ 915 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 916 3184, 3456, 0, 576, 581, 586, 625, 0, 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 919 /* 38 - 2880x576@50Hz 16:9 */ 920 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 921 3184, 3456, 0, 576, 581, 586, 625, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 924 /* 39 - 1920x1080i@50Hz 16:9 */ 925 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 926 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 928 DRM_MODE_FLAG_INTERLACE), 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 40 - 1920x1080i@100Hz 16:9 */ 931 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 932 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 934 DRM_MODE_FLAG_INTERLACE), 935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 41 - 1280x720@100Hz 16:9 */ 937 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 938 1760, 1980, 0, 720, 725, 730, 750, 0, 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 42 - 720x576@100Hz 4:3 */ 942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 943 796, 864, 0, 576, 581, 586, 625, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 946 /* 43 - 720x576@100Hz 16:9 */ 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 948 796, 864, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 44 - 720(1440)x576i@100Hz 4:3 */ 952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 953 795, 864, 0, 576, 580, 586, 625, 0, 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 957 /* 45 - 720(1440)x576i@100Hz 16:9 */ 958 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 959 795, 864, 0, 576, 580, 586, 625, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 963 /* 46 - 1920x1080i@120Hz 16:9 */ 964 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 965 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 967 DRM_MODE_FLAG_INTERLACE), 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 47 - 1280x720@120Hz 16:9 */ 970 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 971 1430, 1650, 0, 720, 725, 730, 750, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 48 - 720x480@120Hz 4:3 */ 975 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 976 798, 858, 0, 480, 489, 495, 525, 0, 977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 978 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 979 /* 49 - 720x480@120Hz 16:9 */ 980 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 981 798, 858, 0, 480, 489, 495, 525, 0, 982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 50 - 720(1440)x480i@120Hz 4:3 */ 985 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 986 801, 858, 0, 480, 488, 494, 525, 0, 987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 988 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 990 /* 51 - 720(1440)x480i@120Hz 16:9 */ 991 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 992 801, 858, 0, 480, 488, 494, 525, 0, 993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 994 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 996 /* 52 - 720x576@200Hz 4:3 */ 997 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 998 796, 864, 0, 576, 581, 586, 625, 0, 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1001 /* 53 - 720x576@200Hz 16:9 */ 1002 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1003 796, 864, 0, 576, 581, 586, 625, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1005 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1006 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1007 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1008 795, 864, 0, 576, 580, 586, 625, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1010 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1012 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1013 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1014 795, 864, 0, 576, 580, 586, 625, 0, 1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1016 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1018 /* 56 - 720x480@240Hz 4:3 */ 1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1020 798, 858, 0, 480, 489, 495, 525, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1023 /* 57 - 720x480@240Hz 16:9 */ 1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1025 798, 858, 0, 480, 489, 495, 525, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1028 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1029 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1030 801, 858, 0, 480, 488, 494, 525, 0, 1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1034 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1035 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1036 801, 858, 0, 480, 488, 494, 525, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1040 /* 60 - 1280x720@24Hz 16:9 */ 1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1042 3080, 3300, 0, 720, 725, 730, 750, 0, 1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1045 /* 61 - 1280x720@25Hz 16:9 */ 1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1047 3740, 3960, 0, 720, 725, 730, 750, 0, 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1050 /* 62 - 1280x720@30Hz 16:9 */ 1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1052 3080, 3300, 0, 720, 725, 730, 750, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 63 - 1920x1080@120Hz 16:9 */ 1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1057 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 64 - 1920x1080@100Hz 16:9 */ 1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1062 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 65 - 1280x720@24Hz 64:27 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1067 3080, 3300, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1070 /* 66 - 1280x720@25Hz 64:27 */ 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1072 3740, 3960, 0, 720, 725, 730, 750, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1075 /* 67 - 1280x720@30Hz 64:27 */ 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1077 3080, 3300, 0, 720, 725, 730, 750, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1080 /* 68 - 1280x720@50Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1082 1760, 1980, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 69 - 1280x720@60Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1087 1430, 1650, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 70 - 1280x720@100Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1092 1760, 1980, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 71 - 1280x720@120Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1097 1430, 1650, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 72 - 1920x1080@24Hz 64:27 */ 1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1102 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 73 - 1920x1080@25Hz 64:27 */ 1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1107 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 74 - 1920x1080@30Hz 64:27 */ 1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1112 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 75 - 1920x1080@50Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1117 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 76 - 1920x1080@60Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1122 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 77 - 1920x1080@100Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1127 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 78 - 1920x1080@120Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1132 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 79 - 1680x720@24Hz 64:27 */ 1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1137 3080, 3300, 0, 720, 725, 730, 750, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 80 - 1680x720@25Hz 64:27 */ 1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1142 2948, 3168, 0, 720, 725, 730, 750, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 81 - 1680x720@30Hz 64:27 */ 1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1147 2420, 2640, 0, 720, 725, 730, 750, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 82 - 1680x720@50Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1152 1980, 2200, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 83 - 1680x720@60Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1157 1980, 2200, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 84 - 1680x720@100Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1162 1780, 2000, 0, 720, 725, 730, 825, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 85 - 1680x720@120Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1167 1780, 2000, 0, 720, 725, 730, 825, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 86 - 2560x1080@24Hz 64:27 */ 1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1172 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 87 - 2560x1080@25Hz 64:27 */ 1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1177 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 88 - 2560x1080@30Hz 64:27 */ 1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1182 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 89 - 2560x1080@50Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1187 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 90 - 2560x1080@60Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1192 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 91 - 2560x1080@100Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1197 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 92 - 2560x1080@120Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1202 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 93 - 3840x2160@24Hz 16:9 */ 1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1207 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1210 /* 94 - 3840x2160@25Hz 16:9 */ 1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1212 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1215 /* 95 - 3840x2160@30Hz 16:9 */ 1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1217 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1220 /* 96 - 3840x2160@50Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1222 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 97 - 3840x2160@60Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1227 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 98 - 4096x2160@24Hz 256:135 */ 1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1232 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1235 /* 99 - 4096x2160@25Hz 256:135 */ 1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1237 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1240 /* 100 - 4096x2160@30Hz 256:135 */ 1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1242 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1245 /* 101 - 4096x2160@50Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1247 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 102 - 4096x2160@60Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1252 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 103 - 3840x2160@24Hz 64:27 */ 1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1257 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1260 /* 104 - 3840x2160@25Hz 64:27 */ 1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1262 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1265 /* 105 - 3840x2160@30Hz 64:27 */ 1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1267 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1270 /* 106 - 3840x2160@50Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1272 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 107 - 3840x2160@60Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1277 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 108 - 1280x720@48Hz 16:9 */ 1281 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1282 2280, 2500, 0, 720, 725, 730, 750, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1285 /* 109 - 1280x720@48Hz 64:27 */ 1286 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1287 2280, 2500, 0, 720, 725, 730, 750, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 110 - 1680x720@48Hz 64:27 */ 1291 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1292 2530, 2750, 0, 720, 725, 730, 750, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 111 - 1920x1080@48Hz 16:9 */ 1296 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1297 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1300 /* 112 - 1920x1080@48Hz 64:27 */ 1301 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1302 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 113 - 2560x1080@48Hz 64:27 */ 1306 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1307 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 114 - 3840x2160@48Hz 16:9 */ 1311 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1312 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 115 - 4096x2160@48Hz 256:135 */ 1316 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1317 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1320 /* 116 - 3840x2160@48Hz 64:27 */ 1321 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1322 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 117 - 3840x2160@100Hz 16:9 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1327 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 118 - 3840x2160@120Hz 16:9 */ 1331 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1332 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1335 /* 119 - 3840x2160@100Hz 64:27 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1337 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 120 - 3840x2160@120Hz 64:27 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1342 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1345 /* 121 - 5120x2160@24Hz 64:27 */ 1346 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1347 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1350 /* 122 - 5120x2160@25Hz 64:27 */ 1351 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1352 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 123 - 5120x2160@30Hz 64:27 */ 1356 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1357 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 124 - 5120x2160@48Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1362 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 125 - 5120x2160@50Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1367 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 126 - 5120x2160@60Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1372 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 127 - 5120x2160@100Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1377 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 }; 1381 1382 /* 1383 * From CEA/CTA-861 spec. 1384 * 1385 * Do not access directly, instead always use cea_mode_for_vic(). 1386 */ 1387 static const struct drm_display_mode edid_cea_modes_193[] = { 1388 /* 193 - 5120x2160@120Hz 64:27 */ 1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1393 /* 194 - 7680x4320@24Hz 16:9 */ 1394 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1395 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1398 /* 195 - 7680x4320@25Hz 16:9 */ 1399 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1400 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1402 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1403 /* 196 - 7680x4320@30Hz 16:9 */ 1404 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1405 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1408 /* 197 - 7680x4320@48Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 198 - 7680x4320@50Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 199 - 7680x4320@60Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 200 - 7680x4320@100Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1425 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 201 - 7680x4320@120Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1430 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 202 - 7680x4320@24Hz 64:27 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1435 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1438 /* 203 - 7680x4320@25Hz 64:27 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1440 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1443 /* 204 - 7680x4320@30Hz 64:27 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1445 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1448 /* 205 - 7680x4320@48Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 206 - 7680x4320@50Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 207 - 7680x4320@60Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 208 - 7680x4320@100Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1465 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 209 - 7680x4320@120Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1470 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 210 - 10240x4320@24Hz 64:27 */ 1474 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1475 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 211 - 10240x4320@25Hz 64:27 */ 1479 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1480 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 212 - 10240x4320@30Hz 64:27 */ 1484 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1485 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 213 - 10240x4320@48Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 214 - 10240x4320@50Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 215 - 10240x4320@60Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 216 - 10240x4320@100Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1505 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 217 - 10240x4320@120Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1510 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 218 - 4096x2160@100Hz 256:135 */ 1514 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1515 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1518 /* 219 - 4096x2160@120Hz 256:135 */ 1519 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1520 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1523 }; 1524 1525 /* 1526 * HDMI 1.4 4k modes. Index using the VIC. 1527 */ 1528 static const struct drm_display_mode edid_4k_modes[] = { 1529 /* 0 - dummy, VICs start at 1 */ 1530 { }, 1531 /* 1 - 3840x2160@30Hz */ 1532 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1533 3840, 4016, 4104, 4400, 0, 1534 2160, 2168, 2178, 2250, 0, 1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1537 /* 2 - 3840x2160@25Hz */ 1538 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1539 3840, 4896, 4984, 5280, 0, 1540 2160, 2168, 2178, 2250, 0, 1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1543 /* 3 - 3840x2160@24Hz */ 1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1545 3840, 5116, 5204, 5500, 0, 1546 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1549 /* 4 - 4096x2160@24Hz (SMPTE) */ 1550 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 4096, 5116, 5204, 5500, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1555 }; 1556 1557 /*** DDC fetch and block validation ***/ 1558 1559 static const u8 edid_header[] = { 1560 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1561 }; 1562 1563 /** 1564 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1565 * @raw_edid: pointer to raw base EDID block 1566 * 1567 * Sanity check the header of the base EDID block. 1568 * 1569 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1570 */ 1571 int drm_edid_header_is_valid(const u8 *raw_edid) 1572 { 1573 int i, score = 0; 1574 1575 for (i = 0; i < sizeof(edid_header); i++) 1576 if (raw_edid[i] == edid_header[i]) 1577 score++; 1578 1579 return score; 1580 } 1581 EXPORT_SYMBOL(drm_edid_header_is_valid); 1582 1583 static int edid_fixup __read_mostly = 6; 1584 module_param_named(edid_fixup, edid_fixup, int, 0400); 1585 MODULE_PARM_DESC(edid_fixup, 1586 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1587 1588 static int validate_displayid(u8 *displayid, int length, int idx); 1589 1590 static int drm_edid_block_checksum(const u8 *raw_edid) 1591 { 1592 int i; 1593 u8 csum = 0, crc = 0; 1594 1595 for (i = 0; i < EDID_LENGTH - 1; i++) 1596 csum += raw_edid[i]; 1597 1598 crc = 0x100 - csum; 1599 1600 return crc; 1601 } 1602 1603 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1604 { 1605 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1606 return true; 1607 else 1608 return false; 1609 } 1610 1611 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1612 { 1613 if (memchr_inv(in_edid, 0, length)) 1614 return false; 1615 1616 return true; 1617 } 1618 1619 /** 1620 * drm_edid_are_equal - compare two edid blobs. 1621 * @edid1: pointer to first blob 1622 * @edid2: pointer to second blob 1623 * This helper can be used during probing to determine if 1624 * edid had changed. 1625 */ 1626 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1627 { 1628 int edid1_len, edid2_len; 1629 bool edid1_present = edid1 != NULL; 1630 bool edid2_present = edid2 != NULL; 1631 1632 if (edid1_present != edid2_present) 1633 return false; 1634 1635 if (edid1) { 1636 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1637 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1638 1639 if (edid1_len != edid2_len) 1640 return false; 1641 1642 if (memcmp(edid1, edid2, edid1_len)) 1643 return false; 1644 } 1645 1646 return true; 1647 } 1648 EXPORT_SYMBOL(drm_edid_are_equal); 1649 1650 /** 1651 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1652 * @raw_edid: pointer to raw EDID block 1653 * @block: type of block to validate (0 for base, extension otherwise) 1654 * @print_bad_edid: if true, dump bad EDID blocks to the console 1655 * @edid_corrupt: if true, the header or checksum is invalid 1656 * 1657 * Validate a base or extension EDID block and optionally dump bad blocks to 1658 * the console. 1659 * 1660 * Return: True if the block is valid, false otherwise. 1661 */ 1662 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1663 bool *edid_corrupt) 1664 { 1665 u8 csum; 1666 struct edid *edid = (struct edid *)raw_edid; 1667 1668 if (WARN_ON(!raw_edid)) 1669 return false; 1670 1671 if (edid_fixup > 8 || edid_fixup < 0) 1672 edid_fixup = 6; 1673 1674 if (block == 0) { 1675 int score = drm_edid_header_is_valid(raw_edid); 1676 1677 if (score == 8) { 1678 if (edid_corrupt) 1679 *edid_corrupt = false; 1680 } else if (score >= edid_fixup) { 1681 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1682 * The corrupt flag needs to be set here otherwise, the 1683 * fix-up code here will correct the problem, the 1684 * checksum is correct and the test fails 1685 */ 1686 if (edid_corrupt) 1687 *edid_corrupt = true; 1688 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1689 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1690 } else { 1691 if (edid_corrupt) 1692 *edid_corrupt = true; 1693 goto bad; 1694 } 1695 } 1696 1697 csum = drm_edid_block_checksum(raw_edid); 1698 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1699 if (edid_corrupt) 1700 *edid_corrupt = true; 1701 1702 /* allow CEA to slide through, switches mangle this */ 1703 if (raw_edid[0] == CEA_EXT) { 1704 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1705 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1706 } else { 1707 if (print_bad_edid) 1708 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1709 1710 goto bad; 1711 } 1712 } 1713 1714 /* per-block-type checks */ 1715 switch (raw_edid[0]) { 1716 case 0: /* base */ 1717 if (edid->version != 1) { 1718 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1719 goto bad; 1720 } 1721 1722 if (edid->revision > 4) 1723 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1724 break; 1725 1726 default: 1727 break; 1728 } 1729 1730 return true; 1731 1732 bad: 1733 if (print_bad_edid) { 1734 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1735 pr_notice("EDID block is all zeroes\n"); 1736 } else { 1737 pr_notice("Raw EDID:\n"); 1738 print_hex_dump(KERN_NOTICE, 1739 " \t", DUMP_PREFIX_NONE, 16, 1, 1740 raw_edid, EDID_LENGTH, false); 1741 } 1742 } 1743 return false; 1744 } 1745 EXPORT_SYMBOL(drm_edid_block_valid); 1746 1747 /** 1748 * drm_edid_is_valid - sanity check EDID data 1749 * @edid: EDID data 1750 * 1751 * Sanity-check an entire EDID record (including extensions) 1752 * 1753 * Return: True if the EDID data is valid, false otherwise. 1754 */ 1755 bool drm_edid_is_valid(struct edid *edid) 1756 { 1757 int i; 1758 u8 *raw = (u8 *)edid; 1759 1760 if (!edid) 1761 return false; 1762 1763 for (i = 0; i <= edid->extensions; i++) 1764 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1765 return false; 1766 1767 return true; 1768 } 1769 EXPORT_SYMBOL(drm_edid_is_valid); 1770 1771 #define DDC_SEGMENT_ADDR 0x30 1772 /** 1773 * drm_do_probe_ddc_edid() - get EDID information via I2C 1774 * @data: I2C device adapter 1775 * @buf: EDID data buffer to be filled 1776 * @block: 128 byte EDID block to start fetching from 1777 * @len: EDID data buffer length to fetch 1778 * 1779 * Try to fetch EDID information by calling I2C driver functions. 1780 * 1781 * Return: 0 on success or -1 on failure. 1782 */ 1783 static int 1784 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1785 { 1786 struct i2c_adapter *adapter = data; 1787 unsigned char start = block * EDID_LENGTH; 1788 unsigned char segment = block >> 1; 1789 unsigned char xfers = segment ? 3 : 2; 1790 int ret, retries = 5; 1791 1792 /* 1793 * The core I2C driver will automatically retry the transfer if the 1794 * adapter reports EAGAIN. However, we find that bit-banging transfers 1795 * are susceptible to errors under a heavily loaded machine and 1796 * generate spurious NAKs and timeouts. Retrying the transfer 1797 * of the individual block a few times seems to overcome this. 1798 */ 1799 do { 1800 struct i2c_msg msgs[] = { 1801 { 1802 .addr = DDC_SEGMENT_ADDR, 1803 .flags = 0, 1804 .len = 1, 1805 .buf = &segment, 1806 }, { 1807 .addr = DDC_ADDR, 1808 .flags = 0, 1809 .len = 1, 1810 .buf = &start, 1811 }, { 1812 .addr = DDC_ADDR, 1813 .flags = I2C_M_RD, 1814 .len = len, 1815 .buf = buf, 1816 } 1817 }; 1818 1819 /* 1820 * Avoid sending the segment addr to not upset non-compliant 1821 * DDC monitors. 1822 */ 1823 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1824 1825 if (ret == -ENXIO) { 1826 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1827 adapter->name); 1828 break; 1829 } 1830 } while (ret != xfers && --retries); 1831 1832 return ret == xfers ? 0 : -1; 1833 } 1834 1835 static void connector_bad_edid(struct drm_connector *connector, 1836 u8 *edid, int num_blocks) 1837 { 1838 int i; 1839 u8 num_of_ext = edid[0x7e]; 1840 1841 /* Calculate real checksum for the last edid extension block data */ 1842 connector->real_edid_checksum = 1843 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1844 1845 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1846 return; 1847 1848 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 1849 for (i = 0; i < num_blocks; i++) { 1850 u8 *block = edid + i * EDID_LENGTH; 1851 char prefix[20]; 1852 1853 if (drm_edid_is_zero(block, EDID_LENGTH)) 1854 sprintf(prefix, "\t[%02x] ZERO ", i); 1855 else if (!drm_edid_block_valid(block, i, false, NULL)) 1856 sprintf(prefix, "\t[%02x] BAD ", i); 1857 else 1858 sprintf(prefix, "\t[%02x] GOOD ", i); 1859 1860 print_hex_dump(KERN_DEBUG, 1861 prefix, DUMP_PREFIX_NONE, 16, 1, 1862 block, EDID_LENGTH, false); 1863 } 1864 } 1865 1866 /* Get override or firmware EDID */ 1867 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1868 { 1869 struct edid *override = NULL; 1870 1871 if (connector->override_edid) 1872 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1873 1874 if (!override) 1875 override = drm_load_edid_firmware(connector); 1876 1877 return IS_ERR(override) ? NULL : override; 1878 } 1879 1880 /** 1881 * drm_add_override_edid_modes - add modes from override/firmware EDID 1882 * @connector: connector we're probing 1883 * 1884 * Add modes from the override/firmware EDID, if available. Only to be used from 1885 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1886 * failed during drm_get_edid() and caused the override/firmware EDID to be 1887 * skipped. 1888 * 1889 * Return: The number of modes added or 0 if we couldn't find any. 1890 */ 1891 int drm_add_override_edid_modes(struct drm_connector *connector) 1892 { 1893 struct edid *override; 1894 int num_modes = 0; 1895 1896 override = drm_get_override_edid(connector); 1897 if (override) { 1898 drm_connector_update_edid_property(connector, override); 1899 num_modes = drm_add_edid_modes(connector, override); 1900 kfree(override); 1901 1902 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1903 connector->base.id, connector->name, num_modes); 1904 } 1905 1906 return num_modes; 1907 } 1908 EXPORT_SYMBOL(drm_add_override_edid_modes); 1909 1910 /** 1911 * drm_do_get_edid - get EDID data using a custom EDID block read function 1912 * @connector: connector we're probing 1913 * @get_edid_block: EDID block read function 1914 * @data: private data passed to the block read function 1915 * 1916 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1917 * exposes a different interface to read EDID blocks this function can be used 1918 * to get EDID data using a custom block read function. 1919 * 1920 * As in the general case the DDC bus is accessible by the kernel at the I2C 1921 * level, drivers must make all reasonable efforts to expose it as an I2C 1922 * adapter and use drm_get_edid() instead of abusing this function. 1923 * 1924 * The EDID may be overridden using debugfs override_edid or firmare EDID 1925 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1926 * order. Having either of them bypasses actual EDID reads. 1927 * 1928 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1929 */ 1930 struct edid *drm_do_get_edid(struct drm_connector *connector, 1931 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1932 size_t len), 1933 void *data) 1934 { 1935 int i, j = 0, valid_extensions = 0; 1936 u8 *edid, *new; 1937 struct edid *override; 1938 1939 override = drm_get_override_edid(connector); 1940 if (override) 1941 return override; 1942 1943 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1944 return NULL; 1945 1946 /* base block fetch */ 1947 for (i = 0; i < 4; i++) { 1948 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1949 goto out; 1950 if (drm_edid_block_valid(edid, 0, false, 1951 &connector->edid_corrupt)) 1952 break; 1953 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1954 connector->null_edid_counter++; 1955 goto carp; 1956 } 1957 } 1958 if (i == 4) 1959 goto carp; 1960 1961 /* if there's no extensions, we're done */ 1962 valid_extensions = edid[0x7e]; 1963 if (valid_extensions == 0) 1964 return (struct edid *)edid; 1965 1966 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1967 if (!new) 1968 goto out; 1969 edid = new; 1970 1971 for (j = 1; j <= edid[0x7e]; j++) { 1972 u8 *block = edid + j * EDID_LENGTH; 1973 1974 for (i = 0; i < 4; i++) { 1975 if (get_edid_block(data, block, j, EDID_LENGTH)) 1976 goto out; 1977 if (drm_edid_block_valid(block, j, false, NULL)) 1978 break; 1979 } 1980 1981 if (i == 4) 1982 valid_extensions--; 1983 } 1984 1985 if (valid_extensions != edid[0x7e]) { 1986 u8 *base; 1987 1988 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1989 1990 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1991 edid[0x7e] = valid_extensions; 1992 1993 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1994 GFP_KERNEL); 1995 if (!new) 1996 goto out; 1997 1998 base = new; 1999 for (i = 0; i <= edid[0x7e]; i++) { 2000 u8 *block = edid + i * EDID_LENGTH; 2001 2002 if (!drm_edid_block_valid(block, i, false, NULL)) 2003 continue; 2004 2005 memcpy(base, block, EDID_LENGTH); 2006 base += EDID_LENGTH; 2007 } 2008 2009 kfree(edid); 2010 edid = new; 2011 } 2012 2013 return (struct edid *)edid; 2014 2015 carp: 2016 connector_bad_edid(connector, edid, 1); 2017 out: 2018 kfree(edid); 2019 return NULL; 2020 } 2021 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2022 2023 /** 2024 * drm_probe_ddc() - probe DDC presence 2025 * @adapter: I2C adapter to probe 2026 * 2027 * Return: True on success, false on failure. 2028 */ 2029 bool 2030 drm_probe_ddc(struct i2c_adapter *adapter) 2031 { 2032 unsigned char out; 2033 2034 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2035 } 2036 EXPORT_SYMBOL(drm_probe_ddc); 2037 2038 /** 2039 * drm_get_edid - get EDID data, if available 2040 * @connector: connector we're probing 2041 * @adapter: I2C adapter to use for DDC 2042 * 2043 * Poke the given I2C channel to grab EDID data if possible. If found, 2044 * attach it to the connector. 2045 * 2046 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2047 */ 2048 struct edid *drm_get_edid(struct drm_connector *connector, 2049 struct i2c_adapter *adapter) 2050 { 2051 struct edid *edid; 2052 2053 if (connector->force == DRM_FORCE_OFF) 2054 return NULL; 2055 2056 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2057 return NULL; 2058 2059 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2060 drm_connector_update_edid_property(connector, edid); 2061 return edid; 2062 } 2063 EXPORT_SYMBOL(drm_get_edid); 2064 2065 /** 2066 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2067 * @connector: connector we're probing 2068 * @adapter: I2C adapter to use for DDC 2069 * 2070 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2071 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2072 * switch DDC to the GPU which is retrieving EDID. 2073 * 2074 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2075 */ 2076 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2077 struct i2c_adapter *adapter) 2078 { 2079 struct drm_device *dev = connector->dev; 2080 struct pci_dev *pdev = to_pci_dev(dev->dev); 2081 struct edid *edid; 2082 2083 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2084 return NULL; 2085 2086 vga_switcheroo_lock_ddc(pdev); 2087 edid = drm_get_edid(connector, adapter); 2088 vga_switcheroo_unlock_ddc(pdev); 2089 2090 return edid; 2091 } 2092 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2093 2094 /** 2095 * drm_edid_duplicate - duplicate an EDID and the extensions 2096 * @edid: EDID to duplicate 2097 * 2098 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2099 */ 2100 struct edid *drm_edid_duplicate(const struct edid *edid) 2101 { 2102 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2103 } 2104 EXPORT_SYMBOL(drm_edid_duplicate); 2105 2106 /*** EDID parsing ***/ 2107 2108 /** 2109 * edid_vendor - match a string against EDID's obfuscated vendor field 2110 * @edid: EDID to match 2111 * @vendor: vendor string 2112 * 2113 * Returns true if @vendor is in @edid, false otherwise 2114 */ 2115 static bool edid_vendor(const struct edid *edid, const char *vendor) 2116 { 2117 char edid_vendor[3]; 2118 2119 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2120 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2121 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2122 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2123 2124 return !strncmp(edid_vendor, vendor, 3); 2125 } 2126 2127 /** 2128 * edid_get_quirks - return quirk flags for a given EDID 2129 * @edid: EDID to process 2130 * 2131 * This tells subsequent routines what fixes they need to apply. 2132 */ 2133 static u32 edid_get_quirks(const struct edid *edid) 2134 { 2135 const struct edid_quirk *quirk; 2136 int i; 2137 2138 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2139 quirk = &edid_quirk_list[i]; 2140 2141 if (edid_vendor(edid, quirk->vendor) && 2142 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2143 return quirk->quirks; 2144 } 2145 2146 return 0; 2147 } 2148 2149 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2150 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2151 2152 /** 2153 * edid_fixup_preferred - set preferred modes based on quirk list 2154 * @connector: has mode list to fix up 2155 * @quirks: quirks list 2156 * 2157 * Walk the mode list for @connector, clearing the preferred status 2158 * on existing modes and setting it anew for the right mode ala @quirks. 2159 */ 2160 static void edid_fixup_preferred(struct drm_connector *connector, 2161 u32 quirks) 2162 { 2163 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2164 int target_refresh = 0; 2165 int cur_vrefresh, preferred_vrefresh; 2166 2167 if (list_empty(&connector->probed_modes)) 2168 return; 2169 2170 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2171 target_refresh = 60; 2172 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2173 target_refresh = 75; 2174 2175 preferred_mode = list_first_entry(&connector->probed_modes, 2176 struct drm_display_mode, head); 2177 2178 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2179 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2180 2181 if (cur_mode == preferred_mode) 2182 continue; 2183 2184 /* Largest mode is preferred */ 2185 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2186 preferred_mode = cur_mode; 2187 2188 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2189 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2190 /* At a given size, try to get closest to target refresh */ 2191 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2192 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2193 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2194 preferred_mode = cur_mode; 2195 } 2196 } 2197 2198 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2199 } 2200 2201 static bool 2202 mode_is_rb(const struct drm_display_mode *mode) 2203 { 2204 return (mode->htotal - mode->hdisplay == 160) && 2205 (mode->hsync_end - mode->hdisplay == 80) && 2206 (mode->hsync_end - mode->hsync_start == 32) && 2207 (mode->vsync_start - mode->vdisplay == 3); 2208 } 2209 2210 /* 2211 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2212 * @dev: Device to duplicate against 2213 * @hsize: Mode width 2214 * @vsize: Mode height 2215 * @fresh: Mode refresh rate 2216 * @rb: Mode reduced-blanking-ness 2217 * 2218 * Walk the DMT mode list looking for a match for the given parameters. 2219 * 2220 * Return: A newly allocated copy of the mode, or NULL if not found. 2221 */ 2222 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2223 int hsize, int vsize, int fresh, 2224 bool rb) 2225 { 2226 int i; 2227 2228 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2229 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2230 2231 if (hsize != ptr->hdisplay) 2232 continue; 2233 if (vsize != ptr->vdisplay) 2234 continue; 2235 if (fresh != drm_mode_vrefresh(ptr)) 2236 continue; 2237 if (rb != mode_is_rb(ptr)) 2238 continue; 2239 2240 return drm_mode_duplicate(dev, ptr); 2241 } 2242 2243 return NULL; 2244 } 2245 EXPORT_SYMBOL(drm_mode_find_dmt); 2246 2247 static bool is_display_descriptor(const u8 d[18], u8 tag) 2248 { 2249 return d[0] == 0x00 && d[1] == 0x00 && 2250 d[2] == 0x00 && d[3] == tag; 2251 } 2252 2253 static bool is_detailed_timing_descriptor(const u8 d[18]) 2254 { 2255 return d[0] != 0x00 || d[1] != 0x00; 2256 } 2257 2258 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2259 2260 static void 2261 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2262 { 2263 int i, n; 2264 u8 d = ext[0x02]; 2265 u8 *det_base = ext + d; 2266 2267 if (d < 4 || d > 127) 2268 return; 2269 2270 n = (127 - d) / 18; 2271 for (i = 0; i < n; i++) 2272 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2273 } 2274 2275 static void 2276 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2277 { 2278 unsigned int i, n = min((int)ext[0x02], 6); 2279 u8 *det_base = ext + 5; 2280 2281 if (ext[0x01] != 1) 2282 return; /* unknown version */ 2283 2284 for (i = 0; i < n; i++) 2285 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2286 } 2287 2288 static void 2289 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2290 { 2291 int i; 2292 struct edid *edid = (struct edid *)raw_edid; 2293 2294 if (edid == NULL) 2295 return; 2296 2297 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2298 cb(&(edid->detailed_timings[i]), closure); 2299 2300 for (i = 1; i <= raw_edid[0x7e]; i++) { 2301 u8 *ext = raw_edid + (i * EDID_LENGTH); 2302 2303 switch (*ext) { 2304 case CEA_EXT: 2305 cea_for_each_detailed_block(ext, cb, closure); 2306 break; 2307 case VTB_EXT: 2308 vtb_for_each_detailed_block(ext, cb, closure); 2309 break; 2310 default: 2311 break; 2312 } 2313 } 2314 } 2315 2316 static void 2317 is_rb(struct detailed_timing *t, void *data) 2318 { 2319 u8 *r = (u8 *)t; 2320 2321 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2322 return; 2323 2324 if (r[15] & 0x10) 2325 *(bool *)data = true; 2326 } 2327 2328 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2329 static bool 2330 drm_monitor_supports_rb(struct edid *edid) 2331 { 2332 if (edid->revision >= 4) { 2333 bool ret = false; 2334 2335 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2336 return ret; 2337 } 2338 2339 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2340 } 2341 2342 static void 2343 find_gtf2(struct detailed_timing *t, void *data) 2344 { 2345 u8 *r = (u8 *)t; 2346 2347 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2348 return; 2349 2350 if (r[10] == 0x02) 2351 *(u8 **)data = r; 2352 } 2353 2354 /* Secondary GTF curve kicks in above some break frequency */ 2355 static int 2356 drm_gtf2_hbreak(struct edid *edid) 2357 { 2358 u8 *r = NULL; 2359 2360 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2361 return r ? (r[12] * 2) : 0; 2362 } 2363 2364 static int 2365 drm_gtf2_2c(struct edid *edid) 2366 { 2367 u8 *r = NULL; 2368 2369 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2370 return r ? r[13] : 0; 2371 } 2372 2373 static int 2374 drm_gtf2_m(struct edid *edid) 2375 { 2376 u8 *r = NULL; 2377 2378 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2379 return r ? (r[15] << 8) + r[14] : 0; 2380 } 2381 2382 static int 2383 drm_gtf2_k(struct edid *edid) 2384 { 2385 u8 *r = NULL; 2386 2387 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2388 return r ? r[16] : 0; 2389 } 2390 2391 static int 2392 drm_gtf2_2j(struct edid *edid) 2393 { 2394 u8 *r = NULL; 2395 2396 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2397 return r ? r[17] : 0; 2398 } 2399 2400 /** 2401 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2402 * @edid: EDID block to scan 2403 */ 2404 static int standard_timing_level(struct edid *edid) 2405 { 2406 if (edid->revision >= 2) { 2407 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2408 return LEVEL_CVT; 2409 if (drm_gtf2_hbreak(edid)) 2410 return LEVEL_GTF2; 2411 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2412 return LEVEL_GTF; 2413 } 2414 return LEVEL_DMT; 2415 } 2416 2417 /* 2418 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2419 * monitors fill with ascii space (0x20) instead. 2420 */ 2421 static int 2422 bad_std_timing(u8 a, u8 b) 2423 { 2424 return (a == 0x00 && b == 0x00) || 2425 (a == 0x01 && b == 0x01) || 2426 (a == 0x20 && b == 0x20); 2427 } 2428 2429 static int drm_mode_hsync(const struct drm_display_mode *mode) 2430 { 2431 if (mode->htotal <= 0) 2432 return 0; 2433 2434 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2435 } 2436 2437 /** 2438 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2439 * @connector: connector of for the EDID block 2440 * @edid: EDID block to scan 2441 * @t: standard timing params 2442 * 2443 * Take the standard timing params (in this case width, aspect, and refresh) 2444 * and convert them into a real mode using CVT/GTF/DMT. 2445 */ 2446 static struct drm_display_mode * 2447 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2448 struct std_timing *t) 2449 { 2450 struct drm_device *dev = connector->dev; 2451 struct drm_display_mode *m, *mode = NULL; 2452 int hsize, vsize; 2453 int vrefresh_rate; 2454 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2455 >> EDID_TIMING_ASPECT_SHIFT; 2456 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2457 >> EDID_TIMING_VFREQ_SHIFT; 2458 int timing_level = standard_timing_level(edid); 2459 2460 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2461 return NULL; 2462 2463 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2464 hsize = t->hsize * 8 + 248; 2465 /* vrefresh_rate = vfreq + 60 */ 2466 vrefresh_rate = vfreq + 60; 2467 /* the vdisplay is calculated based on the aspect ratio */ 2468 if (aspect_ratio == 0) { 2469 if (edid->revision < 3) 2470 vsize = hsize; 2471 else 2472 vsize = (hsize * 10) / 16; 2473 } else if (aspect_ratio == 1) 2474 vsize = (hsize * 3) / 4; 2475 else if (aspect_ratio == 2) 2476 vsize = (hsize * 4) / 5; 2477 else 2478 vsize = (hsize * 9) / 16; 2479 2480 /* HDTV hack, part 1 */ 2481 if (vrefresh_rate == 60 && 2482 ((hsize == 1360 && vsize == 765) || 2483 (hsize == 1368 && vsize == 769))) { 2484 hsize = 1366; 2485 vsize = 768; 2486 } 2487 2488 /* 2489 * If this connector already has a mode for this size and refresh 2490 * rate (because it came from detailed or CVT info), use that 2491 * instead. This way we don't have to guess at interlace or 2492 * reduced blanking. 2493 */ 2494 list_for_each_entry(m, &connector->probed_modes, head) 2495 if (m->hdisplay == hsize && m->vdisplay == vsize && 2496 drm_mode_vrefresh(m) == vrefresh_rate) 2497 return NULL; 2498 2499 /* HDTV hack, part 2 */ 2500 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2501 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2502 false); 2503 if (!mode) 2504 return NULL; 2505 mode->hdisplay = 1366; 2506 mode->hsync_start = mode->hsync_start - 1; 2507 mode->hsync_end = mode->hsync_end - 1; 2508 return mode; 2509 } 2510 2511 /* check whether it can be found in default mode table */ 2512 if (drm_monitor_supports_rb(edid)) { 2513 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2514 true); 2515 if (mode) 2516 return mode; 2517 } 2518 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2519 if (mode) 2520 return mode; 2521 2522 /* okay, generate it */ 2523 switch (timing_level) { 2524 case LEVEL_DMT: 2525 break; 2526 case LEVEL_GTF: 2527 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2528 break; 2529 case LEVEL_GTF2: 2530 /* 2531 * This is potentially wrong if there's ever a monitor with 2532 * more than one ranges section, each claiming a different 2533 * secondary GTF curve. Please don't do that. 2534 */ 2535 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2536 if (!mode) 2537 return NULL; 2538 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2539 drm_mode_destroy(dev, mode); 2540 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2541 vrefresh_rate, 0, 0, 2542 drm_gtf2_m(edid), 2543 drm_gtf2_2c(edid), 2544 drm_gtf2_k(edid), 2545 drm_gtf2_2j(edid)); 2546 } 2547 break; 2548 case LEVEL_CVT: 2549 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2550 false); 2551 break; 2552 } 2553 return mode; 2554 } 2555 2556 /* 2557 * EDID is delightfully ambiguous about how interlaced modes are to be 2558 * encoded. Our internal representation is of frame height, but some 2559 * HDTV detailed timings are encoded as field height. 2560 * 2561 * The format list here is from CEA, in frame size. Technically we 2562 * should be checking refresh rate too. Whatever. 2563 */ 2564 static void 2565 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2566 struct detailed_pixel_timing *pt) 2567 { 2568 int i; 2569 static const struct { 2570 int w, h; 2571 } cea_interlaced[] = { 2572 { 1920, 1080 }, 2573 { 720, 480 }, 2574 { 1440, 480 }, 2575 { 2880, 480 }, 2576 { 720, 576 }, 2577 { 1440, 576 }, 2578 { 2880, 576 }, 2579 }; 2580 2581 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2582 return; 2583 2584 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2585 if ((mode->hdisplay == cea_interlaced[i].w) && 2586 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2587 mode->vdisplay *= 2; 2588 mode->vsync_start *= 2; 2589 mode->vsync_end *= 2; 2590 mode->vtotal *= 2; 2591 mode->vtotal |= 1; 2592 } 2593 } 2594 2595 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2596 } 2597 2598 /** 2599 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2600 * @dev: DRM device (needed to create new mode) 2601 * @edid: EDID block 2602 * @timing: EDID detailed timing info 2603 * @quirks: quirks to apply 2604 * 2605 * An EDID detailed timing block contains enough info for us to create and 2606 * return a new struct drm_display_mode. 2607 */ 2608 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2609 struct edid *edid, 2610 struct detailed_timing *timing, 2611 u32 quirks) 2612 { 2613 struct drm_display_mode *mode; 2614 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2615 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2616 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2617 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2618 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2619 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2620 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2621 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2622 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2623 2624 /* ignore tiny modes */ 2625 if (hactive < 64 || vactive < 64) 2626 return NULL; 2627 2628 if (pt->misc & DRM_EDID_PT_STEREO) { 2629 DRM_DEBUG_KMS("stereo mode not supported\n"); 2630 return NULL; 2631 } 2632 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2633 DRM_DEBUG_KMS("composite sync not supported\n"); 2634 } 2635 2636 /* it is incorrect if hsync/vsync width is zero */ 2637 if (!hsync_pulse_width || !vsync_pulse_width) { 2638 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2639 "Wrong Hsync/Vsync pulse width\n"); 2640 return NULL; 2641 } 2642 2643 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2644 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2645 if (!mode) 2646 return NULL; 2647 2648 goto set_size; 2649 } 2650 2651 mode = drm_mode_create(dev); 2652 if (!mode) 2653 return NULL; 2654 2655 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2656 timing->pixel_clock = cpu_to_le16(1088); 2657 2658 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2659 2660 mode->hdisplay = hactive; 2661 mode->hsync_start = mode->hdisplay + hsync_offset; 2662 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2663 mode->htotal = mode->hdisplay + hblank; 2664 2665 mode->vdisplay = vactive; 2666 mode->vsync_start = mode->vdisplay + vsync_offset; 2667 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2668 mode->vtotal = mode->vdisplay + vblank; 2669 2670 /* Some EDIDs have bogus h/vtotal values */ 2671 if (mode->hsync_end > mode->htotal) 2672 mode->htotal = mode->hsync_end + 1; 2673 if (mode->vsync_end > mode->vtotal) 2674 mode->vtotal = mode->vsync_end + 1; 2675 2676 drm_mode_do_interlace_quirk(mode, pt); 2677 2678 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2679 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2680 } 2681 2682 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2683 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2684 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2685 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2686 2687 set_size: 2688 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2689 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2690 2691 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2692 mode->width_mm *= 10; 2693 mode->height_mm *= 10; 2694 } 2695 2696 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2697 mode->width_mm = edid->width_cm * 10; 2698 mode->height_mm = edid->height_cm * 10; 2699 } 2700 2701 mode->type = DRM_MODE_TYPE_DRIVER; 2702 drm_mode_set_name(mode); 2703 2704 return mode; 2705 } 2706 2707 static bool 2708 mode_in_hsync_range(const struct drm_display_mode *mode, 2709 struct edid *edid, u8 *t) 2710 { 2711 int hsync, hmin, hmax; 2712 2713 hmin = t[7]; 2714 if (edid->revision >= 4) 2715 hmin += ((t[4] & 0x04) ? 255 : 0); 2716 hmax = t[8]; 2717 if (edid->revision >= 4) 2718 hmax += ((t[4] & 0x08) ? 255 : 0); 2719 hsync = drm_mode_hsync(mode); 2720 2721 return (hsync <= hmax && hsync >= hmin); 2722 } 2723 2724 static bool 2725 mode_in_vsync_range(const struct drm_display_mode *mode, 2726 struct edid *edid, u8 *t) 2727 { 2728 int vsync, vmin, vmax; 2729 2730 vmin = t[5]; 2731 if (edid->revision >= 4) 2732 vmin += ((t[4] & 0x01) ? 255 : 0); 2733 vmax = t[6]; 2734 if (edid->revision >= 4) 2735 vmax += ((t[4] & 0x02) ? 255 : 0); 2736 vsync = drm_mode_vrefresh(mode); 2737 2738 return (vsync <= vmax && vsync >= vmin); 2739 } 2740 2741 static u32 2742 range_pixel_clock(struct edid *edid, u8 *t) 2743 { 2744 /* unspecified */ 2745 if (t[9] == 0 || t[9] == 255) 2746 return 0; 2747 2748 /* 1.4 with CVT support gives us real precision, yay */ 2749 if (edid->revision >= 4 && t[10] == 0x04) 2750 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2751 2752 /* 1.3 is pathetic, so fuzz up a bit */ 2753 return t[9] * 10000 + 5001; 2754 } 2755 2756 static bool 2757 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2758 struct detailed_timing *timing) 2759 { 2760 u32 max_clock; 2761 u8 *t = (u8 *)timing; 2762 2763 if (!mode_in_hsync_range(mode, edid, t)) 2764 return false; 2765 2766 if (!mode_in_vsync_range(mode, edid, t)) 2767 return false; 2768 2769 if ((max_clock = range_pixel_clock(edid, t))) 2770 if (mode->clock > max_clock) 2771 return false; 2772 2773 /* 1.4 max horizontal check */ 2774 if (edid->revision >= 4 && t[10] == 0x04) 2775 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2776 return false; 2777 2778 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2779 return false; 2780 2781 return true; 2782 } 2783 2784 static bool valid_inferred_mode(const struct drm_connector *connector, 2785 const struct drm_display_mode *mode) 2786 { 2787 const struct drm_display_mode *m; 2788 bool ok = false; 2789 2790 list_for_each_entry(m, &connector->probed_modes, head) { 2791 if (mode->hdisplay == m->hdisplay && 2792 mode->vdisplay == m->vdisplay && 2793 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2794 return false; /* duplicated */ 2795 if (mode->hdisplay <= m->hdisplay && 2796 mode->vdisplay <= m->vdisplay) 2797 ok = true; 2798 } 2799 return ok; 2800 } 2801 2802 static int 2803 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2804 struct detailed_timing *timing) 2805 { 2806 int i, modes = 0; 2807 struct drm_display_mode *newmode; 2808 struct drm_device *dev = connector->dev; 2809 2810 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2811 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2812 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2813 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2814 if (newmode) { 2815 drm_mode_probed_add(connector, newmode); 2816 modes++; 2817 } 2818 } 2819 } 2820 2821 return modes; 2822 } 2823 2824 /* fix up 1366x768 mode from 1368x768; 2825 * GFT/CVT can't express 1366 width which isn't dividable by 8 2826 */ 2827 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2828 { 2829 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2830 mode->hdisplay = 1366; 2831 mode->hsync_start--; 2832 mode->hsync_end--; 2833 drm_mode_set_name(mode); 2834 } 2835 } 2836 2837 static int 2838 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2839 struct detailed_timing *timing) 2840 { 2841 int i, modes = 0; 2842 struct drm_display_mode *newmode; 2843 struct drm_device *dev = connector->dev; 2844 2845 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2846 const struct minimode *m = &extra_modes[i]; 2847 2848 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2849 if (!newmode) 2850 return modes; 2851 2852 drm_mode_fixup_1366x768(newmode); 2853 if (!mode_in_range(newmode, edid, timing) || 2854 !valid_inferred_mode(connector, newmode)) { 2855 drm_mode_destroy(dev, newmode); 2856 continue; 2857 } 2858 2859 drm_mode_probed_add(connector, newmode); 2860 modes++; 2861 } 2862 2863 return modes; 2864 } 2865 2866 static int 2867 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2868 struct detailed_timing *timing) 2869 { 2870 int i, modes = 0; 2871 struct drm_display_mode *newmode; 2872 struct drm_device *dev = connector->dev; 2873 bool rb = drm_monitor_supports_rb(edid); 2874 2875 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2876 const struct minimode *m = &extra_modes[i]; 2877 2878 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2879 if (!newmode) 2880 return modes; 2881 2882 drm_mode_fixup_1366x768(newmode); 2883 if (!mode_in_range(newmode, edid, timing) || 2884 !valid_inferred_mode(connector, newmode)) { 2885 drm_mode_destroy(dev, newmode); 2886 continue; 2887 } 2888 2889 drm_mode_probed_add(connector, newmode); 2890 modes++; 2891 } 2892 2893 return modes; 2894 } 2895 2896 static void 2897 do_inferred_modes(struct detailed_timing *timing, void *c) 2898 { 2899 struct detailed_mode_closure *closure = c; 2900 struct detailed_non_pixel *data = &timing->data.other_data; 2901 struct detailed_data_monitor_range *range = &data->data.range; 2902 2903 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2904 return; 2905 2906 closure->modes += drm_dmt_modes_for_range(closure->connector, 2907 closure->edid, 2908 timing); 2909 2910 if (!version_greater(closure->edid, 1, 1)) 2911 return; /* GTF not defined yet */ 2912 2913 switch (range->flags) { 2914 case 0x02: /* secondary gtf, XXX could do more */ 2915 case 0x00: /* default gtf */ 2916 closure->modes += drm_gtf_modes_for_range(closure->connector, 2917 closure->edid, 2918 timing); 2919 break; 2920 case 0x04: /* cvt, only in 1.4+ */ 2921 if (!version_greater(closure->edid, 1, 3)) 2922 break; 2923 2924 closure->modes += drm_cvt_modes_for_range(closure->connector, 2925 closure->edid, 2926 timing); 2927 break; 2928 case 0x01: /* just the ranges, no formula */ 2929 default: 2930 break; 2931 } 2932 } 2933 2934 static int 2935 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2936 { 2937 struct detailed_mode_closure closure = { 2938 .connector = connector, 2939 .edid = edid, 2940 }; 2941 2942 if (version_greater(edid, 1, 0)) 2943 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2944 &closure); 2945 2946 return closure.modes; 2947 } 2948 2949 static int 2950 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2951 { 2952 int i, j, m, modes = 0; 2953 struct drm_display_mode *mode; 2954 u8 *est = ((u8 *)timing) + 6; 2955 2956 for (i = 0; i < 6; i++) { 2957 for (j = 7; j >= 0; j--) { 2958 m = (i * 8) + (7 - j); 2959 if (m >= ARRAY_SIZE(est3_modes)) 2960 break; 2961 if (est[i] & (1 << j)) { 2962 mode = drm_mode_find_dmt(connector->dev, 2963 est3_modes[m].w, 2964 est3_modes[m].h, 2965 est3_modes[m].r, 2966 est3_modes[m].rb); 2967 if (mode) { 2968 drm_mode_probed_add(connector, mode); 2969 modes++; 2970 } 2971 } 2972 } 2973 } 2974 2975 return modes; 2976 } 2977 2978 static void 2979 do_established_modes(struct detailed_timing *timing, void *c) 2980 { 2981 struct detailed_mode_closure *closure = c; 2982 2983 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2984 return; 2985 2986 closure->modes += drm_est3_modes(closure->connector, timing); 2987 } 2988 2989 /** 2990 * add_established_modes - get est. modes from EDID and add them 2991 * @connector: connector to add mode(s) to 2992 * @edid: EDID block to scan 2993 * 2994 * Each EDID block contains a bitmap of the supported "established modes" list 2995 * (defined above). Tease them out and add them to the global modes list. 2996 */ 2997 static int 2998 add_established_modes(struct drm_connector *connector, struct edid *edid) 2999 { 3000 struct drm_device *dev = connector->dev; 3001 unsigned long est_bits = edid->established_timings.t1 | 3002 (edid->established_timings.t2 << 8) | 3003 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3004 int i, modes = 0; 3005 struct detailed_mode_closure closure = { 3006 .connector = connector, 3007 .edid = edid, 3008 }; 3009 3010 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3011 if (est_bits & (1<<i)) { 3012 struct drm_display_mode *newmode; 3013 3014 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3015 if (newmode) { 3016 drm_mode_probed_add(connector, newmode); 3017 modes++; 3018 } 3019 } 3020 } 3021 3022 if (version_greater(edid, 1, 0)) 3023 drm_for_each_detailed_block((u8 *)edid, 3024 do_established_modes, &closure); 3025 3026 return modes + closure.modes; 3027 } 3028 3029 static void 3030 do_standard_modes(struct detailed_timing *timing, void *c) 3031 { 3032 struct detailed_mode_closure *closure = c; 3033 struct detailed_non_pixel *data = &timing->data.other_data; 3034 struct drm_connector *connector = closure->connector; 3035 struct edid *edid = closure->edid; 3036 int i; 3037 3038 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3039 return; 3040 3041 for (i = 0; i < 6; i++) { 3042 struct std_timing *std = &data->data.timings[i]; 3043 struct drm_display_mode *newmode; 3044 3045 newmode = drm_mode_std(connector, edid, std); 3046 if (newmode) { 3047 drm_mode_probed_add(connector, newmode); 3048 closure->modes++; 3049 } 3050 } 3051 } 3052 3053 /** 3054 * add_standard_modes - get std. modes from EDID and add them 3055 * @connector: connector to add mode(s) to 3056 * @edid: EDID block to scan 3057 * 3058 * Standard modes can be calculated using the appropriate standard (DMT, 3059 * GTF or CVT. Grab them from @edid and add them to the list. 3060 */ 3061 static int 3062 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3063 { 3064 int i, modes = 0; 3065 struct detailed_mode_closure closure = { 3066 .connector = connector, 3067 .edid = edid, 3068 }; 3069 3070 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3071 struct drm_display_mode *newmode; 3072 3073 newmode = drm_mode_std(connector, edid, 3074 &edid->standard_timings[i]); 3075 if (newmode) { 3076 drm_mode_probed_add(connector, newmode); 3077 modes++; 3078 } 3079 } 3080 3081 if (version_greater(edid, 1, 0)) 3082 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3083 &closure); 3084 3085 /* XXX should also look for standard codes in VTB blocks */ 3086 3087 return modes + closure.modes; 3088 } 3089 3090 static int drm_cvt_modes(struct drm_connector *connector, 3091 struct detailed_timing *timing) 3092 { 3093 int i, j, modes = 0; 3094 struct drm_display_mode *newmode; 3095 struct drm_device *dev = connector->dev; 3096 struct cvt_timing *cvt; 3097 const int rates[] = { 60, 85, 75, 60, 50 }; 3098 const u8 empty[3] = { 0, 0, 0 }; 3099 3100 for (i = 0; i < 4; i++) { 3101 int width, height; 3102 3103 cvt = &(timing->data.other_data.data.cvt[i]); 3104 3105 if (!memcmp(cvt->code, empty, 3)) 3106 continue; 3107 3108 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3109 switch (cvt->code[1] & 0x0c) { 3110 /* default - because compiler doesn't see that we've enumerated all cases */ 3111 default: 3112 case 0x00: 3113 width = height * 4 / 3; 3114 break; 3115 case 0x04: 3116 width = height * 16 / 9; 3117 break; 3118 case 0x08: 3119 width = height * 16 / 10; 3120 break; 3121 case 0x0c: 3122 width = height * 15 / 9; 3123 break; 3124 } 3125 3126 for (j = 1; j < 5; j++) { 3127 if (cvt->code[2] & (1 << j)) { 3128 newmode = drm_cvt_mode(dev, width, height, 3129 rates[j], j == 0, 3130 false, false); 3131 if (newmode) { 3132 drm_mode_probed_add(connector, newmode); 3133 modes++; 3134 } 3135 } 3136 } 3137 } 3138 3139 return modes; 3140 } 3141 3142 static void 3143 do_cvt_mode(struct detailed_timing *timing, void *c) 3144 { 3145 struct detailed_mode_closure *closure = c; 3146 3147 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3148 return; 3149 3150 closure->modes += drm_cvt_modes(closure->connector, timing); 3151 } 3152 3153 static int 3154 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3155 { 3156 struct detailed_mode_closure closure = { 3157 .connector = connector, 3158 .edid = edid, 3159 }; 3160 3161 if (version_greater(edid, 1, 2)) 3162 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3163 3164 /* XXX should also look for CVT codes in VTB blocks */ 3165 3166 return closure.modes; 3167 } 3168 3169 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3170 3171 static void 3172 do_detailed_mode(struct detailed_timing *timing, void *c) 3173 { 3174 struct detailed_mode_closure *closure = c; 3175 struct drm_display_mode *newmode; 3176 3177 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3178 return; 3179 3180 newmode = drm_mode_detailed(closure->connector->dev, 3181 closure->edid, timing, 3182 closure->quirks); 3183 if (!newmode) 3184 return; 3185 3186 if (closure->preferred) 3187 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3188 3189 /* 3190 * Detailed modes are limited to 10kHz pixel clock resolution, 3191 * so fix up anything that looks like CEA/HDMI mode, but the clock 3192 * is just slightly off. 3193 */ 3194 fixup_detailed_cea_mode_clock(newmode); 3195 3196 drm_mode_probed_add(closure->connector, newmode); 3197 closure->modes++; 3198 closure->preferred = false; 3199 } 3200 3201 /* 3202 * add_detailed_modes - Add modes from detailed timings 3203 * @connector: attached connector 3204 * @edid: EDID block to scan 3205 * @quirks: quirks to apply 3206 */ 3207 static int 3208 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3209 u32 quirks) 3210 { 3211 struct detailed_mode_closure closure = { 3212 .connector = connector, 3213 .edid = edid, 3214 .preferred = true, 3215 .quirks = quirks, 3216 }; 3217 3218 if (closure.preferred && !version_greater(edid, 1, 3)) 3219 closure.preferred = 3220 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3221 3222 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3223 3224 return closure.modes; 3225 } 3226 3227 #define AUDIO_BLOCK 0x01 3228 #define VIDEO_BLOCK 0x02 3229 #define VENDOR_BLOCK 0x03 3230 #define SPEAKER_BLOCK 0x04 3231 #define HDR_STATIC_METADATA_BLOCK 0x6 3232 #define USE_EXTENDED_TAG 0x07 3233 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3234 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3235 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3236 #define EDID_BASIC_AUDIO (1 << 6) 3237 #define EDID_CEA_YCRCB444 (1 << 5) 3238 #define EDID_CEA_YCRCB422 (1 << 4) 3239 #define EDID_CEA_VCDB_QS (1 << 6) 3240 3241 /* 3242 * Search EDID for CEA extension block. 3243 */ 3244 static u8 *drm_find_edid_extension(const struct edid *edid, 3245 int ext_id, int *ext_index) 3246 { 3247 u8 *edid_ext = NULL; 3248 int i; 3249 3250 /* No EDID or EDID extensions */ 3251 if (edid == NULL || edid->extensions == 0) 3252 return NULL; 3253 3254 /* Find CEA extension */ 3255 for (i = *ext_index; i < edid->extensions; i++) { 3256 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3257 if (edid_ext[0] == ext_id) 3258 break; 3259 } 3260 3261 if (i >= edid->extensions) 3262 return NULL; 3263 3264 *ext_index = i + 1; 3265 3266 return edid_ext; 3267 } 3268 3269 3270 static u8 *drm_find_displayid_extension(const struct edid *edid, 3271 int *length, int *idx, 3272 int *ext_index) 3273 { 3274 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index); 3275 struct displayid_hdr *base; 3276 int ret; 3277 3278 if (!displayid) 3279 return NULL; 3280 3281 /* EDID extensions block checksum isn't for us */ 3282 *length = EDID_LENGTH - 1; 3283 *idx = 1; 3284 3285 ret = validate_displayid(displayid, *length, *idx); 3286 if (ret) 3287 return NULL; 3288 3289 base = (struct displayid_hdr *)&displayid[*idx]; 3290 *length = *idx + sizeof(*base) + base->bytes; 3291 3292 return displayid; 3293 } 3294 3295 static u8 *drm_find_cea_extension(const struct edid *edid) 3296 { 3297 int length, idx; 3298 struct displayid_block *block; 3299 u8 *cea; 3300 u8 *displayid; 3301 int ext_index; 3302 3303 /* Look for a top level CEA extension block */ 3304 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3305 ext_index = 0; 3306 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3307 if (cea) 3308 return cea; 3309 3310 /* CEA blocks can also be found embedded in a DisplayID block */ 3311 ext_index = 0; 3312 for (;;) { 3313 displayid = drm_find_displayid_extension(edid, &length, &idx, 3314 &ext_index); 3315 if (!displayid) 3316 return NULL; 3317 3318 idx += sizeof(struct displayid_hdr); 3319 for_each_displayid_db(displayid, block, idx, length) { 3320 if (block->tag == DATA_BLOCK_CTA) 3321 return (u8 *)block; 3322 } 3323 } 3324 3325 return NULL; 3326 } 3327 3328 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3329 { 3330 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3331 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3332 3333 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3334 return &edid_cea_modes_1[vic - 1]; 3335 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3336 return &edid_cea_modes_193[vic - 193]; 3337 return NULL; 3338 } 3339 3340 static u8 cea_num_vics(void) 3341 { 3342 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3343 } 3344 3345 static u8 cea_next_vic(u8 vic) 3346 { 3347 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3348 vic = 193; 3349 return vic; 3350 } 3351 3352 /* 3353 * Calculate the alternate clock for the CEA mode 3354 * (60Hz vs. 59.94Hz etc.) 3355 */ 3356 static unsigned int 3357 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3358 { 3359 unsigned int clock = cea_mode->clock; 3360 3361 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3362 return clock; 3363 3364 /* 3365 * edid_cea_modes contains the 59.94Hz 3366 * variant for 240 and 480 line modes, 3367 * and the 60Hz variant otherwise. 3368 */ 3369 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3370 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3371 else 3372 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3373 3374 return clock; 3375 } 3376 3377 static bool 3378 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3379 { 3380 /* 3381 * For certain VICs the spec allows the vertical 3382 * front porch to vary by one or two lines. 3383 * 3384 * cea_modes[] stores the variant with the shortest 3385 * vertical front porch. We can adjust the mode to 3386 * get the other variants by simply increasing the 3387 * vertical front porch length. 3388 */ 3389 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3390 cea_mode_for_vic(9)->vtotal != 262 || 3391 cea_mode_for_vic(12)->vtotal != 262 || 3392 cea_mode_for_vic(13)->vtotal != 262 || 3393 cea_mode_for_vic(23)->vtotal != 312 || 3394 cea_mode_for_vic(24)->vtotal != 312 || 3395 cea_mode_for_vic(27)->vtotal != 312 || 3396 cea_mode_for_vic(28)->vtotal != 312); 3397 3398 if (((vic == 8 || vic == 9 || 3399 vic == 12 || vic == 13) && mode->vtotal < 263) || 3400 ((vic == 23 || vic == 24 || 3401 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3402 mode->vsync_start++; 3403 mode->vsync_end++; 3404 mode->vtotal++; 3405 3406 return true; 3407 } 3408 3409 return false; 3410 } 3411 3412 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3413 unsigned int clock_tolerance) 3414 { 3415 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3416 u8 vic; 3417 3418 if (!to_match->clock) 3419 return 0; 3420 3421 if (to_match->picture_aspect_ratio) 3422 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3423 3424 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3425 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3426 unsigned int clock1, clock2; 3427 3428 /* Check both 60Hz and 59.94Hz */ 3429 clock1 = cea_mode.clock; 3430 clock2 = cea_mode_alternate_clock(&cea_mode); 3431 3432 if (abs(to_match->clock - clock1) > clock_tolerance && 3433 abs(to_match->clock - clock2) > clock_tolerance) 3434 continue; 3435 3436 do { 3437 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3438 return vic; 3439 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3440 } 3441 3442 return 0; 3443 } 3444 3445 /** 3446 * drm_match_cea_mode - look for a CEA mode matching given mode 3447 * @to_match: display mode 3448 * 3449 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3450 * mode. 3451 */ 3452 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3453 { 3454 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3455 u8 vic; 3456 3457 if (!to_match->clock) 3458 return 0; 3459 3460 if (to_match->picture_aspect_ratio) 3461 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3462 3463 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3464 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3465 unsigned int clock1, clock2; 3466 3467 /* Check both 60Hz and 59.94Hz */ 3468 clock1 = cea_mode.clock; 3469 clock2 = cea_mode_alternate_clock(&cea_mode); 3470 3471 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3472 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3473 continue; 3474 3475 do { 3476 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3477 return vic; 3478 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3479 } 3480 3481 return 0; 3482 } 3483 EXPORT_SYMBOL(drm_match_cea_mode); 3484 3485 static bool drm_valid_cea_vic(u8 vic) 3486 { 3487 return cea_mode_for_vic(vic) != NULL; 3488 } 3489 3490 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3491 { 3492 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3493 3494 if (mode) 3495 return mode->picture_aspect_ratio; 3496 3497 return HDMI_PICTURE_ASPECT_NONE; 3498 } 3499 3500 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3501 { 3502 return edid_4k_modes[video_code].picture_aspect_ratio; 3503 } 3504 3505 /* 3506 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3507 * specific block). 3508 */ 3509 static unsigned int 3510 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3511 { 3512 return cea_mode_alternate_clock(hdmi_mode); 3513 } 3514 3515 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3516 unsigned int clock_tolerance) 3517 { 3518 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3519 u8 vic; 3520 3521 if (!to_match->clock) 3522 return 0; 3523 3524 if (to_match->picture_aspect_ratio) 3525 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3526 3527 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3528 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3529 unsigned int clock1, clock2; 3530 3531 /* Make sure to also match alternate clocks */ 3532 clock1 = hdmi_mode->clock; 3533 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3534 3535 if (abs(to_match->clock - clock1) > clock_tolerance && 3536 abs(to_match->clock - clock2) > clock_tolerance) 3537 continue; 3538 3539 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3540 return vic; 3541 } 3542 3543 return 0; 3544 } 3545 3546 /* 3547 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3548 * @to_match: display mode 3549 * 3550 * An HDMI mode is one defined in the HDMI vendor specific block. 3551 * 3552 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3553 */ 3554 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3555 { 3556 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3557 u8 vic; 3558 3559 if (!to_match->clock) 3560 return 0; 3561 3562 if (to_match->picture_aspect_ratio) 3563 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3564 3565 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3566 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3567 unsigned int clock1, clock2; 3568 3569 /* Make sure to also match alternate clocks */ 3570 clock1 = hdmi_mode->clock; 3571 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3572 3573 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3574 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3575 drm_mode_match(to_match, hdmi_mode, match_flags)) 3576 return vic; 3577 } 3578 return 0; 3579 } 3580 3581 static bool drm_valid_hdmi_vic(u8 vic) 3582 { 3583 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3584 } 3585 3586 static int 3587 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3588 { 3589 struct drm_device *dev = connector->dev; 3590 struct drm_display_mode *mode, *tmp; 3591 LIST_HEAD(list); 3592 int modes = 0; 3593 3594 /* Don't add CEA modes if the CEA extension block is missing */ 3595 if (!drm_find_cea_extension(edid)) 3596 return 0; 3597 3598 /* 3599 * Go through all probed modes and create a new mode 3600 * with the alternate clock for certain CEA modes. 3601 */ 3602 list_for_each_entry(mode, &connector->probed_modes, head) { 3603 const struct drm_display_mode *cea_mode = NULL; 3604 struct drm_display_mode *newmode; 3605 u8 vic = drm_match_cea_mode(mode); 3606 unsigned int clock1, clock2; 3607 3608 if (drm_valid_cea_vic(vic)) { 3609 cea_mode = cea_mode_for_vic(vic); 3610 clock2 = cea_mode_alternate_clock(cea_mode); 3611 } else { 3612 vic = drm_match_hdmi_mode(mode); 3613 if (drm_valid_hdmi_vic(vic)) { 3614 cea_mode = &edid_4k_modes[vic]; 3615 clock2 = hdmi_mode_alternate_clock(cea_mode); 3616 } 3617 } 3618 3619 if (!cea_mode) 3620 continue; 3621 3622 clock1 = cea_mode->clock; 3623 3624 if (clock1 == clock2) 3625 continue; 3626 3627 if (mode->clock != clock1 && mode->clock != clock2) 3628 continue; 3629 3630 newmode = drm_mode_duplicate(dev, cea_mode); 3631 if (!newmode) 3632 continue; 3633 3634 /* Carry over the stereo flags */ 3635 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3636 3637 /* 3638 * The current mode could be either variant. Make 3639 * sure to pick the "other" clock for the new mode. 3640 */ 3641 if (mode->clock != clock1) 3642 newmode->clock = clock1; 3643 else 3644 newmode->clock = clock2; 3645 3646 list_add_tail(&newmode->head, &list); 3647 } 3648 3649 list_for_each_entry_safe(mode, tmp, &list, head) { 3650 list_del(&mode->head); 3651 drm_mode_probed_add(connector, mode); 3652 modes++; 3653 } 3654 3655 return modes; 3656 } 3657 3658 static u8 svd_to_vic(u8 svd) 3659 { 3660 /* 0-6 bit vic, 7th bit native mode indicator */ 3661 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3662 return svd & 127; 3663 3664 return svd; 3665 } 3666 3667 static struct drm_display_mode * 3668 drm_display_mode_from_vic_index(struct drm_connector *connector, 3669 const u8 *video_db, u8 video_len, 3670 u8 video_index) 3671 { 3672 struct drm_device *dev = connector->dev; 3673 struct drm_display_mode *newmode; 3674 u8 vic; 3675 3676 if (video_db == NULL || video_index >= video_len) 3677 return NULL; 3678 3679 /* CEA modes are numbered 1..127 */ 3680 vic = svd_to_vic(video_db[video_index]); 3681 if (!drm_valid_cea_vic(vic)) 3682 return NULL; 3683 3684 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3685 if (!newmode) 3686 return NULL; 3687 3688 return newmode; 3689 } 3690 3691 /* 3692 * do_y420vdb_modes - Parse YCBCR 420 only modes 3693 * @connector: connector corresponding to the HDMI sink 3694 * @svds: start of the data block of CEA YCBCR 420 VDB 3695 * @len: length of the CEA YCBCR 420 VDB 3696 * 3697 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3698 * which contains modes which can be supported in YCBCR 420 3699 * output format only. 3700 */ 3701 static int do_y420vdb_modes(struct drm_connector *connector, 3702 const u8 *svds, u8 svds_len) 3703 { 3704 int modes = 0, i; 3705 struct drm_device *dev = connector->dev; 3706 struct drm_display_info *info = &connector->display_info; 3707 struct drm_hdmi_info *hdmi = &info->hdmi; 3708 3709 for (i = 0; i < svds_len; i++) { 3710 u8 vic = svd_to_vic(svds[i]); 3711 struct drm_display_mode *newmode; 3712 3713 if (!drm_valid_cea_vic(vic)) 3714 continue; 3715 3716 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3717 if (!newmode) 3718 break; 3719 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3720 drm_mode_probed_add(connector, newmode); 3721 modes++; 3722 } 3723 3724 if (modes > 0) 3725 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3726 return modes; 3727 } 3728 3729 /* 3730 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3731 * @connector: connector corresponding to the HDMI sink 3732 * @vic: CEA vic for the video mode to be added in the map 3733 * 3734 * Makes an entry for a videomode in the YCBCR 420 bitmap 3735 */ 3736 static void 3737 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3738 { 3739 u8 vic = svd_to_vic(svd); 3740 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3741 3742 if (!drm_valid_cea_vic(vic)) 3743 return; 3744 3745 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3746 } 3747 3748 /** 3749 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3750 * @dev: DRM device 3751 * @video_code: CEA VIC of the mode 3752 * 3753 * Creates a new mode matching the specified CEA VIC. 3754 * 3755 * Returns: A new drm_display_mode on success or NULL on failure 3756 */ 3757 struct drm_display_mode * 3758 drm_display_mode_from_cea_vic(struct drm_device *dev, 3759 u8 video_code) 3760 { 3761 const struct drm_display_mode *cea_mode; 3762 struct drm_display_mode *newmode; 3763 3764 cea_mode = cea_mode_for_vic(video_code); 3765 if (!cea_mode) 3766 return NULL; 3767 3768 newmode = drm_mode_duplicate(dev, cea_mode); 3769 if (!newmode) 3770 return NULL; 3771 3772 return newmode; 3773 } 3774 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3775 3776 static int 3777 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3778 { 3779 int i, modes = 0; 3780 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3781 3782 for (i = 0; i < len; i++) { 3783 struct drm_display_mode *mode; 3784 3785 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3786 if (mode) { 3787 /* 3788 * YCBCR420 capability block contains a bitmap which 3789 * gives the index of CEA modes from CEA VDB, which 3790 * can support YCBCR 420 sampling output also (apart 3791 * from RGB/YCBCR444 etc). 3792 * For example, if the bit 0 in bitmap is set, 3793 * first mode in VDB can support YCBCR420 output too. 3794 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3795 */ 3796 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3797 drm_add_cmdb_modes(connector, db[i]); 3798 3799 drm_mode_probed_add(connector, mode); 3800 modes++; 3801 } 3802 } 3803 3804 return modes; 3805 } 3806 3807 struct stereo_mandatory_mode { 3808 int width, height, vrefresh; 3809 unsigned int flags; 3810 }; 3811 3812 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3813 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3814 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3815 { 1920, 1080, 50, 3816 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3817 { 1920, 1080, 60, 3818 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3819 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3820 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3821 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3822 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3823 }; 3824 3825 static bool 3826 stereo_match_mandatory(const struct drm_display_mode *mode, 3827 const struct stereo_mandatory_mode *stereo_mode) 3828 { 3829 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3830 3831 return mode->hdisplay == stereo_mode->width && 3832 mode->vdisplay == stereo_mode->height && 3833 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3834 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3835 } 3836 3837 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3838 { 3839 struct drm_device *dev = connector->dev; 3840 const struct drm_display_mode *mode; 3841 struct list_head stereo_modes; 3842 int modes = 0, i; 3843 3844 INIT_LIST_HEAD(&stereo_modes); 3845 3846 list_for_each_entry(mode, &connector->probed_modes, head) { 3847 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3848 const struct stereo_mandatory_mode *mandatory; 3849 struct drm_display_mode *new_mode; 3850 3851 if (!stereo_match_mandatory(mode, 3852 &stereo_mandatory_modes[i])) 3853 continue; 3854 3855 mandatory = &stereo_mandatory_modes[i]; 3856 new_mode = drm_mode_duplicate(dev, mode); 3857 if (!new_mode) 3858 continue; 3859 3860 new_mode->flags |= mandatory->flags; 3861 list_add_tail(&new_mode->head, &stereo_modes); 3862 modes++; 3863 } 3864 } 3865 3866 list_splice_tail(&stereo_modes, &connector->probed_modes); 3867 3868 return modes; 3869 } 3870 3871 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3872 { 3873 struct drm_device *dev = connector->dev; 3874 struct drm_display_mode *newmode; 3875 3876 if (!drm_valid_hdmi_vic(vic)) { 3877 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3878 return 0; 3879 } 3880 3881 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3882 if (!newmode) 3883 return 0; 3884 3885 drm_mode_probed_add(connector, newmode); 3886 3887 return 1; 3888 } 3889 3890 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3891 const u8 *video_db, u8 video_len, u8 video_index) 3892 { 3893 struct drm_display_mode *newmode; 3894 int modes = 0; 3895 3896 if (structure & (1 << 0)) { 3897 newmode = drm_display_mode_from_vic_index(connector, video_db, 3898 video_len, 3899 video_index); 3900 if (newmode) { 3901 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3902 drm_mode_probed_add(connector, newmode); 3903 modes++; 3904 } 3905 } 3906 if (structure & (1 << 6)) { 3907 newmode = drm_display_mode_from_vic_index(connector, video_db, 3908 video_len, 3909 video_index); 3910 if (newmode) { 3911 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3912 drm_mode_probed_add(connector, newmode); 3913 modes++; 3914 } 3915 } 3916 if (structure & (1 << 8)) { 3917 newmode = drm_display_mode_from_vic_index(connector, video_db, 3918 video_len, 3919 video_index); 3920 if (newmode) { 3921 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3922 drm_mode_probed_add(connector, newmode); 3923 modes++; 3924 } 3925 } 3926 3927 return modes; 3928 } 3929 3930 /* 3931 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3932 * @connector: connector corresponding to the HDMI sink 3933 * @db: start of the CEA vendor specific block 3934 * @len: length of the CEA block payload, ie. one can access up to db[len] 3935 * 3936 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3937 * also adds the stereo 3d modes when applicable. 3938 */ 3939 static int 3940 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3941 const u8 *video_db, u8 video_len) 3942 { 3943 struct drm_display_info *info = &connector->display_info; 3944 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3945 u8 vic_len, hdmi_3d_len = 0; 3946 u16 mask; 3947 u16 structure_all; 3948 3949 if (len < 8) 3950 goto out; 3951 3952 /* no HDMI_Video_Present */ 3953 if (!(db[8] & (1 << 5))) 3954 goto out; 3955 3956 /* Latency_Fields_Present */ 3957 if (db[8] & (1 << 7)) 3958 offset += 2; 3959 3960 /* I_Latency_Fields_Present */ 3961 if (db[8] & (1 << 6)) 3962 offset += 2; 3963 3964 /* the declared length is not long enough for the 2 first bytes 3965 * of additional video format capabilities */ 3966 if (len < (8 + offset + 2)) 3967 goto out; 3968 3969 /* 3D_Present */ 3970 offset++; 3971 if (db[8 + offset] & (1 << 7)) { 3972 modes += add_hdmi_mandatory_stereo_modes(connector); 3973 3974 /* 3D_Multi_present */ 3975 multi_present = (db[8 + offset] & 0x60) >> 5; 3976 } 3977 3978 offset++; 3979 vic_len = db[8 + offset] >> 5; 3980 hdmi_3d_len = db[8 + offset] & 0x1f; 3981 3982 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3983 u8 vic; 3984 3985 vic = db[9 + offset + i]; 3986 modes += add_hdmi_mode(connector, vic); 3987 } 3988 offset += 1 + vic_len; 3989 3990 if (multi_present == 1) 3991 multi_len = 2; 3992 else if (multi_present == 2) 3993 multi_len = 4; 3994 else 3995 multi_len = 0; 3996 3997 if (len < (8 + offset + hdmi_3d_len - 1)) 3998 goto out; 3999 4000 if (hdmi_3d_len < multi_len) 4001 goto out; 4002 4003 if (multi_present == 1 || multi_present == 2) { 4004 /* 3D_Structure_ALL */ 4005 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4006 4007 /* check if 3D_MASK is present */ 4008 if (multi_present == 2) 4009 mask = (db[10 + offset] << 8) | db[11 + offset]; 4010 else 4011 mask = 0xffff; 4012 4013 for (i = 0; i < 16; i++) { 4014 if (mask & (1 << i)) 4015 modes += add_3d_struct_modes(connector, 4016 structure_all, 4017 video_db, 4018 video_len, i); 4019 } 4020 } 4021 4022 offset += multi_len; 4023 4024 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4025 int vic_index; 4026 struct drm_display_mode *newmode = NULL; 4027 unsigned int newflag = 0; 4028 bool detail_present; 4029 4030 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4031 4032 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4033 break; 4034 4035 /* 2D_VIC_order_X */ 4036 vic_index = db[8 + offset + i] >> 4; 4037 4038 /* 3D_Structure_X */ 4039 switch (db[8 + offset + i] & 0x0f) { 4040 case 0: 4041 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4042 break; 4043 case 6: 4044 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4045 break; 4046 case 8: 4047 /* 3D_Detail_X */ 4048 if ((db[9 + offset + i] >> 4) == 1) 4049 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4050 break; 4051 } 4052 4053 if (newflag != 0) { 4054 newmode = drm_display_mode_from_vic_index(connector, 4055 video_db, 4056 video_len, 4057 vic_index); 4058 4059 if (newmode) { 4060 newmode->flags |= newflag; 4061 drm_mode_probed_add(connector, newmode); 4062 modes++; 4063 } 4064 } 4065 4066 if (detail_present) 4067 i++; 4068 } 4069 4070 out: 4071 if (modes > 0) 4072 info->has_hdmi_infoframe = true; 4073 return modes; 4074 } 4075 4076 static int 4077 cea_db_payload_len(const u8 *db) 4078 { 4079 return db[0] & 0x1f; 4080 } 4081 4082 static int 4083 cea_db_extended_tag(const u8 *db) 4084 { 4085 return db[1]; 4086 } 4087 4088 static int 4089 cea_db_tag(const u8 *db) 4090 { 4091 return db[0] >> 5; 4092 } 4093 4094 static int 4095 cea_revision(const u8 *cea) 4096 { 4097 /* 4098 * FIXME is this correct for the DispID variant? 4099 * The DispID spec doesn't really specify whether 4100 * this is the revision of the CEA extension or 4101 * the DispID CEA data block. And the only value 4102 * given as an example is 0. 4103 */ 4104 return cea[1]; 4105 } 4106 4107 static int 4108 cea_db_offsets(const u8 *cea, int *start, int *end) 4109 { 4110 /* DisplayID CTA extension blocks and top-level CEA EDID 4111 * block header definitions differ in the following bytes: 4112 * 1) Byte 2 of the header specifies length differently, 4113 * 2) Byte 3 is only present in the CEA top level block. 4114 * 4115 * The different definitions for byte 2 follow. 4116 * 4117 * DisplayID CTA extension block defines byte 2 as: 4118 * Number of payload bytes 4119 * 4120 * CEA EDID block defines byte 2 as: 4121 * Byte number (decimal) within this block where the 18-byte 4122 * DTDs begin. If no non-DTD data is present in this extension 4123 * block, the value should be set to 04h (the byte after next). 4124 * If set to 00h, there are no DTDs present in this block and 4125 * no non-DTD data. 4126 */ 4127 if (cea[0] == DATA_BLOCK_CTA) { 4128 /* 4129 * for_each_displayid_db() has already verified 4130 * that these stay within expected bounds. 4131 */ 4132 *start = 3; 4133 *end = *start + cea[2]; 4134 } else if (cea[0] == CEA_EXT) { 4135 /* Data block offset in CEA extension block */ 4136 *start = 4; 4137 *end = cea[2]; 4138 if (*end == 0) 4139 *end = 127; 4140 if (*end < 4 || *end > 127) 4141 return -ERANGE; 4142 } else { 4143 return -EOPNOTSUPP; 4144 } 4145 4146 return 0; 4147 } 4148 4149 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4150 { 4151 int hdmi_id; 4152 4153 if (cea_db_tag(db) != VENDOR_BLOCK) 4154 return false; 4155 4156 if (cea_db_payload_len(db) < 5) 4157 return false; 4158 4159 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4160 4161 return hdmi_id == HDMI_IEEE_OUI; 4162 } 4163 4164 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4165 { 4166 unsigned int oui; 4167 4168 if (cea_db_tag(db) != VENDOR_BLOCK) 4169 return false; 4170 4171 if (cea_db_payload_len(db) < 7) 4172 return false; 4173 4174 oui = db[3] << 16 | db[2] << 8 | db[1]; 4175 4176 return oui == HDMI_FORUM_IEEE_OUI; 4177 } 4178 4179 static bool cea_db_is_vcdb(const u8 *db) 4180 { 4181 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4182 return false; 4183 4184 if (cea_db_payload_len(db) != 2) 4185 return false; 4186 4187 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4188 return false; 4189 4190 return true; 4191 } 4192 4193 static bool cea_db_is_y420cmdb(const u8 *db) 4194 { 4195 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4196 return false; 4197 4198 if (!cea_db_payload_len(db)) 4199 return false; 4200 4201 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4202 return false; 4203 4204 return true; 4205 } 4206 4207 static bool cea_db_is_y420vdb(const u8 *db) 4208 { 4209 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4210 return false; 4211 4212 if (!cea_db_payload_len(db)) 4213 return false; 4214 4215 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4216 return false; 4217 4218 return true; 4219 } 4220 4221 #define for_each_cea_db(cea, i, start, end) \ 4222 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4223 4224 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4225 const u8 *db) 4226 { 4227 struct drm_display_info *info = &connector->display_info; 4228 struct drm_hdmi_info *hdmi = &info->hdmi; 4229 u8 map_len = cea_db_payload_len(db) - 1; 4230 u8 count; 4231 u64 map = 0; 4232 4233 if (map_len == 0) { 4234 /* All CEA modes support ycbcr420 sampling also.*/ 4235 hdmi->y420_cmdb_map = U64_MAX; 4236 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4237 return; 4238 } 4239 4240 /* 4241 * This map indicates which of the existing CEA block modes 4242 * from VDB can support YCBCR420 output too. So if bit=0 is 4243 * set, first mode from VDB can support YCBCR420 output too. 4244 * We will parse and keep this map, before parsing VDB itself 4245 * to avoid going through the same block again and again. 4246 * 4247 * Spec is not clear about max possible size of this block. 4248 * Clamping max bitmap block size at 8 bytes. Every byte can 4249 * address 8 CEA modes, in this way this map can address 4250 * 8*8 = first 64 SVDs. 4251 */ 4252 if (WARN_ON_ONCE(map_len > 8)) 4253 map_len = 8; 4254 4255 for (count = 0; count < map_len; count++) 4256 map |= (u64)db[2 + count] << (8 * count); 4257 4258 if (map) 4259 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4260 4261 hdmi->y420_cmdb_map = map; 4262 } 4263 4264 static int 4265 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4266 { 4267 const u8 *cea = drm_find_cea_extension(edid); 4268 const u8 *db, *hdmi = NULL, *video = NULL; 4269 u8 dbl, hdmi_len, video_len = 0; 4270 int modes = 0; 4271 4272 if (cea && cea_revision(cea) >= 3) { 4273 int i, start, end; 4274 4275 if (cea_db_offsets(cea, &start, &end)) 4276 return 0; 4277 4278 for_each_cea_db(cea, i, start, end) { 4279 db = &cea[i]; 4280 dbl = cea_db_payload_len(db); 4281 4282 if (cea_db_tag(db) == VIDEO_BLOCK) { 4283 video = db + 1; 4284 video_len = dbl; 4285 modes += do_cea_modes(connector, video, dbl); 4286 } else if (cea_db_is_hdmi_vsdb(db)) { 4287 hdmi = db; 4288 hdmi_len = dbl; 4289 } else if (cea_db_is_y420vdb(db)) { 4290 const u8 *vdb420 = &db[2]; 4291 4292 /* Add 4:2:0(only) modes present in EDID */ 4293 modes += do_y420vdb_modes(connector, 4294 vdb420, 4295 dbl - 1); 4296 } 4297 } 4298 } 4299 4300 /* 4301 * We parse the HDMI VSDB after having added the cea modes as we will 4302 * be patching their flags when the sink supports stereo 3D. 4303 */ 4304 if (hdmi) 4305 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4306 video_len); 4307 4308 return modes; 4309 } 4310 4311 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4312 { 4313 const struct drm_display_mode *cea_mode; 4314 int clock1, clock2, clock; 4315 u8 vic; 4316 const char *type; 4317 4318 /* 4319 * allow 5kHz clock difference either way to account for 4320 * the 10kHz clock resolution limit of detailed timings. 4321 */ 4322 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4323 if (drm_valid_cea_vic(vic)) { 4324 type = "CEA"; 4325 cea_mode = cea_mode_for_vic(vic); 4326 clock1 = cea_mode->clock; 4327 clock2 = cea_mode_alternate_clock(cea_mode); 4328 } else { 4329 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4330 if (drm_valid_hdmi_vic(vic)) { 4331 type = "HDMI"; 4332 cea_mode = &edid_4k_modes[vic]; 4333 clock1 = cea_mode->clock; 4334 clock2 = hdmi_mode_alternate_clock(cea_mode); 4335 } else { 4336 return; 4337 } 4338 } 4339 4340 /* pick whichever is closest */ 4341 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4342 clock = clock1; 4343 else 4344 clock = clock2; 4345 4346 if (mode->clock == clock) 4347 return; 4348 4349 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4350 type, vic, mode->clock, clock); 4351 mode->clock = clock; 4352 } 4353 4354 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4355 { 4356 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4357 return false; 4358 4359 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4360 return false; 4361 4362 if (cea_db_payload_len(db) < 3) 4363 return false; 4364 4365 return true; 4366 } 4367 4368 static uint8_t eotf_supported(const u8 *edid_ext) 4369 { 4370 return edid_ext[2] & 4371 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4372 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4373 BIT(HDMI_EOTF_SMPTE_ST2084) | 4374 BIT(HDMI_EOTF_BT_2100_HLG)); 4375 } 4376 4377 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4378 { 4379 return edid_ext[3] & 4380 BIT(HDMI_STATIC_METADATA_TYPE1); 4381 } 4382 4383 static void 4384 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4385 { 4386 u16 len; 4387 4388 len = cea_db_payload_len(db); 4389 4390 connector->hdr_sink_metadata.hdmi_type1.eotf = 4391 eotf_supported(db); 4392 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4393 hdr_metadata_type(db); 4394 4395 if (len >= 4) 4396 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4397 if (len >= 5) 4398 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4399 if (len >= 6) 4400 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4401 } 4402 4403 static void 4404 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4405 { 4406 u8 len = cea_db_payload_len(db); 4407 4408 if (len >= 6 && (db[6] & (1 << 7))) 4409 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4410 if (len >= 8) { 4411 connector->latency_present[0] = db[8] >> 7; 4412 connector->latency_present[1] = (db[8] >> 6) & 1; 4413 } 4414 if (len >= 9) 4415 connector->video_latency[0] = db[9]; 4416 if (len >= 10) 4417 connector->audio_latency[0] = db[10]; 4418 if (len >= 11) 4419 connector->video_latency[1] = db[11]; 4420 if (len >= 12) 4421 connector->audio_latency[1] = db[12]; 4422 4423 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4424 "video latency %d %d, " 4425 "audio latency %d %d\n", 4426 connector->latency_present[0], 4427 connector->latency_present[1], 4428 connector->video_latency[0], 4429 connector->video_latency[1], 4430 connector->audio_latency[0], 4431 connector->audio_latency[1]); 4432 } 4433 4434 static void 4435 monitor_name(struct detailed_timing *t, void *data) 4436 { 4437 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4438 return; 4439 4440 *(u8 **)data = t->data.other_data.data.str.str; 4441 } 4442 4443 static int get_monitor_name(struct edid *edid, char name[13]) 4444 { 4445 char *edid_name = NULL; 4446 int mnl; 4447 4448 if (!edid || !name) 4449 return 0; 4450 4451 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4452 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4453 if (edid_name[mnl] == 0x0a) 4454 break; 4455 4456 name[mnl] = edid_name[mnl]; 4457 } 4458 4459 return mnl; 4460 } 4461 4462 /** 4463 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4464 * @edid: monitor EDID information 4465 * @name: pointer to a character array to hold the name of the monitor 4466 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4467 * 4468 */ 4469 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4470 { 4471 int name_length; 4472 char buf[13]; 4473 4474 if (bufsize <= 0) 4475 return; 4476 4477 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4478 memcpy(name, buf, name_length); 4479 name[name_length] = '\0'; 4480 } 4481 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4482 4483 static void clear_eld(struct drm_connector *connector) 4484 { 4485 memset(connector->eld, 0, sizeof(connector->eld)); 4486 4487 connector->latency_present[0] = false; 4488 connector->latency_present[1] = false; 4489 connector->video_latency[0] = 0; 4490 connector->audio_latency[0] = 0; 4491 connector->video_latency[1] = 0; 4492 connector->audio_latency[1] = 0; 4493 } 4494 4495 /* 4496 * drm_edid_to_eld - build ELD from EDID 4497 * @connector: connector corresponding to the HDMI/DP sink 4498 * @edid: EDID to parse 4499 * 4500 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4501 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4502 */ 4503 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4504 { 4505 uint8_t *eld = connector->eld; 4506 u8 *cea; 4507 u8 *db; 4508 int total_sad_count = 0; 4509 int mnl; 4510 int dbl; 4511 4512 clear_eld(connector); 4513 4514 if (!edid) 4515 return; 4516 4517 cea = drm_find_cea_extension(edid); 4518 if (!cea) { 4519 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4520 return; 4521 } 4522 4523 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4524 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4525 4526 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4527 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4528 4529 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4530 4531 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4532 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4533 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4534 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4535 4536 if (cea_revision(cea) >= 3) { 4537 int i, start, end; 4538 int sad_count; 4539 4540 if (cea_db_offsets(cea, &start, &end)) { 4541 start = 0; 4542 end = 0; 4543 } 4544 4545 for_each_cea_db(cea, i, start, end) { 4546 db = &cea[i]; 4547 dbl = cea_db_payload_len(db); 4548 4549 switch (cea_db_tag(db)) { 4550 case AUDIO_BLOCK: 4551 /* Audio Data Block, contains SADs */ 4552 sad_count = min(dbl / 3, 15 - total_sad_count); 4553 if (sad_count >= 1) 4554 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4555 &db[1], sad_count * 3); 4556 total_sad_count += sad_count; 4557 break; 4558 case SPEAKER_BLOCK: 4559 /* Speaker Allocation Data Block */ 4560 if (dbl >= 1) 4561 eld[DRM_ELD_SPEAKER] = db[1]; 4562 break; 4563 case VENDOR_BLOCK: 4564 /* HDMI Vendor-Specific Data Block */ 4565 if (cea_db_is_hdmi_vsdb(db)) 4566 drm_parse_hdmi_vsdb_audio(connector, db); 4567 break; 4568 default: 4569 break; 4570 } 4571 } 4572 } 4573 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4574 4575 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4576 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4577 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4578 else 4579 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4580 4581 eld[DRM_ELD_BASELINE_ELD_LEN] = 4582 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4583 4584 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4585 drm_eld_size(eld), total_sad_count); 4586 } 4587 4588 /** 4589 * drm_edid_to_sad - extracts SADs from EDID 4590 * @edid: EDID to parse 4591 * @sads: pointer that will be set to the extracted SADs 4592 * 4593 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4594 * 4595 * Note: The returned pointer needs to be freed using kfree(). 4596 * 4597 * Return: The number of found SADs or negative number on error. 4598 */ 4599 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4600 { 4601 int count = 0; 4602 int i, start, end, dbl; 4603 u8 *cea; 4604 4605 cea = drm_find_cea_extension(edid); 4606 if (!cea) { 4607 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4608 return 0; 4609 } 4610 4611 if (cea_revision(cea) < 3) { 4612 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4613 return 0; 4614 } 4615 4616 if (cea_db_offsets(cea, &start, &end)) { 4617 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4618 return -EPROTO; 4619 } 4620 4621 for_each_cea_db(cea, i, start, end) { 4622 u8 *db = &cea[i]; 4623 4624 if (cea_db_tag(db) == AUDIO_BLOCK) { 4625 int j; 4626 4627 dbl = cea_db_payload_len(db); 4628 4629 count = dbl / 3; /* SAD is 3B */ 4630 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4631 if (!*sads) 4632 return -ENOMEM; 4633 for (j = 0; j < count; j++) { 4634 u8 *sad = &db[1 + j * 3]; 4635 4636 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4637 (*sads)[j].channels = sad[0] & 0x7; 4638 (*sads)[j].freq = sad[1] & 0x7F; 4639 (*sads)[j].byte2 = sad[2]; 4640 } 4641 break; 4642 } 4643 } 4644 4645 return count; 4646 } 4647 EXPORT_SYMBOL(drm_edid_to_sad); 4648 4649 /** 4650 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4651 * @edid: EDID to parse 4652 * @sadb: pointer to the speaker block 4653 * 4654 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4655 * 4656 * Note: The returned pointer needs to be freed using kfree(). 4657 * 4658 * Return: The number of found Speaker Allocation Blocks or negative number on 4659 * error. 4660 */ 4661 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4662 { 4663 int count = 0; 4664 int i, start, end, dbl; 4665 const u8 *cea; 4666 4667 cea = drm_find_cea_extension(edid); 4668 if (!cea) { 4669 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4670 return 0; 4671 } 4672 4673 if (cea_revision(cea) < 3) { 4674 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4675 return 0; 4676 } 4677 4678 if (cea_db_offsets(cea, &start, &end)) { 4679 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4680 return -EPROTO; 4681 } 4682 4683 for_each_cea_db(cea, i, start, end) { 4684 const u8 *db = &cea[i]; 4685 4686 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4687 dbl = cea_db_payload_len(db); 4688 4689 /* Speaker Allocation Data Block */ 4690 if (dbl == 3) { 4691 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4692 if (!*sadb) 4693 return -ENOMEM; 4694 count = dbl; 4695 break; 4696 } 4697 } 4698 } 4699 4700 return count; 4701 } 4702 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4703 4704 /** 4705 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4706 * @connector: connector associated with the HDMI/DP sink 4707 * @mode: the display mode 4708 * 4709 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4710 * the sink doesn't support audio or video. 4711 */ 4712 int drm_av_sync_delay(struct drm_connector *connector, 4713 const struct drm_display_mode *mode) 4714 { 4715 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4716 int a, v; 4717 4718 if (!connector->latency_present[0]) 4719 return 0; 4720 if (!connector->latency_present[1]) 4721 i = 0; 4722 4723 a = connector->audio_latency[i]; 4724 v = connector->video_latency[i]; 4725 4726 /* 4727 * HDMI/DP sink doesn't support audio or video? 4728 */ 4729 if (a == 255 || v == 255) 4730 return 0; 4731 4732 /* 4733 * Convert raw EDID values to millisecond. 4734 * Treat unknown latency as 0ms. 4735 */ 4736 if (a) 4737 a = min(2 * (a - 1), 500); 4738 if (v) 4739 v = min(2 * (v - 1), 500); 4740 4741 return max(v - a, 0); 4742 } 4743 EXPORT_SYMBOL(drm_av_sync_delay); 4744 4745 /** 4746 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4747 * @edid: monitor EDID information 4748 * 4749 * Parse the CEA extension according to CEA-861-B. 4750 * 4751 * Drivers that have added the modes parsed from EDID to drm_display_info 4752 * should use &drm_display_info.is_hdmi instead of calling this function. 4753 * 4754 * Return: True if the monitor is HDMI, false if not or unknown. 4755 */ 4756 bool drm_detect_hdmi_monitor(struct edid *edid) 4757 { 4758 u8 *edid_ext; 4759 int i; 4760 int start_offset, end_offset; 4761 4762 edid_ext = drm_find_cea_extension(edid); 4763 if (!edid_ext) 4764 return false; 4765 4766 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4767 return false; 4768 4769 /* 4770 * Because HDMI identifier is in Vendor Specific Block, 4771 * search it from all data blocks of CEA extension. 4772 */ 4773 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4774 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4775 return true; 4776 } 4777 4778 return false; 4779 } 4780 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4781 4782 /** 4783 * drm_detect_monitor_audio - check monitor audio capability 4784 * @edid: EDID block to scan 4785 * 4786 * Monitor should have CEA extension block. 4787 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4788 * audio' only. If there is any audio extension block and supported 4789 * audio format, assume at least 'basic audio' support, even if 'basic 4790 * audio' is not defined in EDID. 4791 * 4792 * Return: True if the monitor supports audio, false otherwise. 4793 */ 4794 bool drm_detect_monitor_audio(struct edid *edid) 4795 { 4796 u8 *edid_ext; 4797 int i, j; 4798 bool has_audio = false; 4799 int start_offset, end_offset; 4800 4801 edid_ext = drm_find_cea_extension(edid); 4802 if (!edid_ext) 4803 goto end; 4804 4805 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4806 4807 if (has_audio) { 4808 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4809 goto end; 4810 } 4811 4812 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4813 goto end; 4814 4815 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4816 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4817 has_audio = true; 4818 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4819 DRM_DEBUG_KMS("CEA audio format %d\n", 4820 (edid_ext[i + j] >> 3) & 0xf); 4821 goto end; 4822 } 4823 } 4824 end: 4825 return has_audio; 4826 } 4827 EXPORT_SYMBOL(drm_detect_monitor_audio); 4828 4829 4830 /** 4831 * drm_default_rgb_quant_range - default RGB quantization range 4832 * @mode: display mode 4833 * 4834 * Determine the default RGB quantization range for the mode, 4835 * as specified in CEA-861. 4836 * 4837 * Return: The default RGB quantization range for the mode 4838 */ 4839 enum hdmi_quantization_range 4840 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4841 { 4842 /* All CEA modes other than VIC 1 use limited quantization range. */ 4843 return drm_match_cea_mode(mode) > 1 ? 4844 HDMI_QUANTIZATION_RANGE_LIMITED : 4845 HDMI_QUANTIZATION_RANGE_FULL; 4846 } 4847 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4848 4849 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4850 { 4851 struct drm_display_info *info = &connector->display_info; 4852 4853 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4854 4855 if (db[2] & EDID_CEA_VCDB_QS) 4856 info->rgb_quant_range_selectable = true; 4857 } 4858 4859 static 4860 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 4861 { 4862 switch (max_frl_rate) { 4863 case 1: 4864 *max_lanes = 3; 4865 *max_rate_per_lane = 3; 4866 break; 4867 case 2: 4868 *max_lanes = 3; 4869 *max_rate_per_lane = 6; 4870 break; 4871 case 3: 4872 *max_lanes = 4; 4873 *max_rate_per_lane = 6; 4874 break; 4875 case 4: 4876 *max_lanes = 4; 4877 *max_rate_per_lane = 8; 4878 break; 4879 case 5: 4880 *max_lanes = 4; 4881 *max_rate_per_lane = 10; 4882 break; 4883 case 6: 4884 *max_lanes = 4; 4885 *max_rate_per_lane = 12; 4886 break; 4887 case 0: 4888 default: 4889 *max_lanes = 0; 4890 *max_rate_per_lane = 0; 4891 } 4892 } 4893 4894 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4895 const u8 *db) 4896 { 4897 u8 dc_mask; 4898 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4899 4900 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4901 hdmi->y420_dc_modes = dc_mask; 4902 } 4903 4904 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4905 const u8 *hf_vsdb) 4906 { 4907 struct drm_display_info *display = &connector->display_info; 4908 struct drm_hdmi_info *hdmi = &display->hdmi; 4909 4910 display->has_hdmi_infoframe = true; 4911 4912 if (hf_vsdb[6] & 0x80) { 4913 hdmi->scdc.supported = true; 4914 if (hf_vsdb[6] & 0x40) 4915 hdmi->scdc.read_request = true; 4916 } 4917 4918 /* 4919 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4920 * And as per the spec, three factors confirm this: 4921 * * Availability of a HF-VSDB block in EDID (check) 4922 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4923 * * SCDC support available (let's check) 4924 * Lets check it out. 4925 */ 4926 4927 if (hf_vsdb[5]) { 4928 /* max clock is 5000 KHz times block value */ 4929 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4930 struct drm_scdc *scdc = &hdmi->scdc; 4931 4932 if (max_tmds_clock > 340000) { 4933 display->max_tmds_clock = max_tmds_clock; 4934 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4935 display->max_tmds_clock); 4936 } 4937 4938 if (scdc->supported) { 4939 scdc->scrambling.supported = true; 4940 4941 /* Few sinks support scrambling for clocks < 340M */ 4942 if ((hf_vsdb[6] & 0x8)) 4943 scdc->scrambling.low_rates = true; 4944 } 4945 } 4946 4947 if (hf_vsdb[7]) { 4948 u8 max_frl_rate; 4949 u8 dsc_max_frl_rate; 4950 u8 dsc_max_slices; 4951 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 4952 4953 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 4954 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 4955 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 4956 &hdmi->max_frl_rate_per_lane); 4957 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 4958 4959 if (hdmi_dsc->v_1p2) { 4960 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 4961 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 4962 4963 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 4964 hdmi_dsc->bpc_supported = 16; 4965 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 4966 hdmi_dsc->bpc_supported = 12; 4967 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 4968 hdmi_dsc->bpc_supported = 10; 4969 else 4970 hdmi_dsc->bpc_supported = 0; 4971 4972 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 4973 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 4974 &hdmi_dsc->max_frl_rate_per_lane); 4975 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 4976 4977 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 4978 switch (dsc_max_slices) { 4979 case 1: 4980 hdmi_dsc->max_slices = 1; 4981 hdmi_dsc->clk_per_slice = 340; 4982 break; 4983 case 2: 4984 hdmi_dsc->max_slices = 2; 4985 hdmi_dsc->clk_per_slice = 340; 4986 break; 4987 case 3: 4988 hdmi_dsc->max_slices = 4; 4989 hdmi_dsc->clk_per_slice = 340; 4990 break; 4991 case 4: 4992 hdmi_dsc->max_slices = 8; 4993 hdmi_dsc->clk_per_slice = 340; 4994 break; 4995 case 5: 4996 hdmi_dsc->max_slices = 8; 4997 hdmi_dsc->clk_per_slice = 400; 4998 break; 4999 case 6: 5000 hdmi_dsc->max_slices = 12; 5001 hdmi_dsc->clk_per_slice = 400; 5002 break; 5003 case 7: 5004 hdmi_dsc->max_slices = 16; 5005 hdmi_dsc->clk_per_slice = 400; 5006 break; 5007 case 0: 5008 default: 5009 hdmi_dsc->max_slices = 0; 5010 hdmi_dsc->clk_per_slice = 0; 5011 } 5012 } 5013 } 5014 5015 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 5016 } 5017 5018 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5019 const u8 *hdmi) 5020 { 5021 struct drm_display_info *info = &connector->display_info; 5022 unsigned int dc_bpc = 0; 5023 5024 /* HDMI supports at least 8 bpc */ 5025 info->bpc = 8; 5026 5027 if (cea_db_payload_len(hdmi) < 6) 5028 return; 5029 5030 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5031 dc_bpc = 10; 5032 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 5033 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5034 connector->name); 5035 } 5036 5037 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5038 dc_bpc = 12; 5039 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 5040 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5041 connector->name); 5042 } 5043 5044 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5045 dc_bpc = 16; 5046 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 5047 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5048 connector->name); 5049 } 5050 5051 if (dc_bpc == 0) { 5052 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5053 connector->name); 5054 return; 5055 } 5056 5057 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5058 connector->name, dc_bpc); 5059 info->bpc = dc_bpc; 5060 5061 /* 5062 * Deep color support mandates RGB444 support for all video 5063 * modes and forbids YCRCB422 support for all video modes per 5064 * HDMI 1.3 spec. 5065 */ 5066 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5067 5068 /* YCRCB444 is optional according to spec. */ 5069 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5070 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5071 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5072 connector->name); 5073 } 5074 5075 /* 5076 * Spec says that if any deep color mode is supported at all, 5077 * then deep color 36 bit must be supported. 5078 */ 5079 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5080 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5081 connector->name); 5082 } 5083 } 5084 5085 static void 5086 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5087 { 5088 struct drm_display_info *info = &connector->display_info; 5089 u8 len = cea_db_payload_len(db); 5090 5091 info->is_hdmi = true; 5092 5093 if (len >= 6) 5094 info->dvi_dual = db[6] & 1; 5095 if (len >= 7) 5096 info->max_tmds_clock = db[7] * 5000; 5097 5098 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5099 "max TMDS clock %d kHz\n", 5100 info->dvi_dual, 5101 info->max_tmds_clock); 5102 5103 drm_parse_hdmi_deep_color_info(connector, db); 5104 } 5105 5106 static void drm_parse_cea_ext(struct drm_connector *connector, 5107 const struct edid *edid) 5108 { 5109 struct drm_display_info *info = &connector->display_info; 5110 const u8 *edid_ext; 5111 int i, start, end; 5112 5113 edid_ext = drm_find_cea_extension(edid); 5114 if (!edid_ext) 5115 return; 5116 5117 info->cea_rev = edid_ext[1]; 5118 5119 /* The existence of a CEA block should imply RGB support */ 5120 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5121 if (edid_ext[3] & EDID_CEA_YCRCB444) 5122 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5123 if (edid_ext[3] & EDID_CEA_YCRCB422) 5124 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5125 5126 if (cea_db_offsets(edid_ext, &start, &end)) 5127 return; 5128 5129 for_each_cea_db(edid_ext, i, start, end) { 5130 const u8 *db = &edid_ext[i]; 5131 5132 if (cea_db_is_hdmi_vsdb(db)) 5133 drm_parse_hdmi_vsdb_video(connector, db); 5134 if (cea_db_is_hdmi_forum_vsdb(db)) 5135 drm_parse_hdmi_forum_vsdb(connector, db); 5136 if (cea_db_is_y420cmdb(db)) 5137 drm_parse_y420cmdb_bitmap(connector, db); 5138 if (cea_db_is_vcdb(db)) 5139 drm_parse_vcdb(connector, db); 5140 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5141 drm_parse_hdr_metadata_block(connector, db); 5142 } 5143 } 5144 5145 static 5146 void get_monitor_range(struct detailed_timing *timing, 5147 void *info_monitor_range) 5148 { 5149 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5150 const struct detailed_non_pixel *data = &timing->data.other_data; 5151 const struct detailed_data_monitor_range *range = &data->data.range; 5152 5153 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 5154 return; 5155 5156 /* 5157 * Check for flag range limits only. If flag == 1 then 5158 * no additional timing information provided. 5159 * Default GTF, GTF Secondary curve and CVT are not 5160 * supported 5161 */ 5162 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5163 return; 5164 5165 monitor_range->min_vfreq = range->min_vfreq; 5166 monitor_range->max_vfreq = range->max_vfreq; 5167 } 5168 5169 static 5170 void drm_get_monitor_range(struct drm_connector *connector, 5171 const struct edid *edid) 5172 { 5173 struct drm_display_info *info = &connector->display_info; 5174 5175 if (!version_greater(edid, 1, 1)) 5176 return; 5177 5178 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 5179 &info->monitor_range); 5180 5181 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5182 info->monitor_range.min_vfreq, 5183 info->monitor_range.max_vfreq); 5184 } 5185 5186 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5187 * all of the values which would have been set from EDID 5188 */ 5189 void 5190 drm_reset_display_info(struct drm_connector *connector) 5191 { 5192 struct drm_display_info *info = &connector->display_info; 5193 5194 info->width_mm = 0; 5195 info->height_mm = 0; 5196 5197 info->bpc = 0; 5198 info->color_formats = 0; 5199 info->cea_rev = 0; 5200 info->max_tmds_clock = 0; 5201 info->dvi_dual = false; 5202 info->is_hdmi = false; 5203 info->has_hdmi_infoframe = false; 5204 info->rgb_quant_range_selectable = false; 5205 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5206 5207 info->non_desktop = 0; 5208 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5209 } 5210 5211 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5212 { 5213 struct drm_display_info *info = &connector->display_info; 5214 5215 u32 quirks = edid_get_quirks(edid); 5216 5217 drm_reset_display_info(connector); 5218 5219 info->width_mm = edid->width_cm * 10; 5220 info->height_mm = edid->height_cm * 10; 5221 5222 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5223 5224 drm_get_monitor_range(connector, edid); 5225 5226 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5227 5228 if (edid->revision < 3) 5229 return quirks; 5230 5231 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5232 return quirks; 5233 5234 drm_parse_cea_ext(connector, edid); 5235 5236 /* 5237 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5238 * 5239 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5240 * tells us to assume 8 bpc color depth if the EDID doesn't have 5241 * extensions which tell otherwise. 5242 */ 5243 if (info->bpc == 0 && edid->revision == 3 && 5244 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5245 info->bpc = 8; 5246 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5247 connector->name, info->bpc); 5248 } 5249 5250 /* Only defined for 1.4 with digital displays */ 5251 if (edid->revision < 4) 5252 return quirks; 5253 5254 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5255 case DRM_EDID_DIGITAL_DEPTH_6: 5256 info->bpc = 6; 5257 break; 5258 case DRM_EDID_DIGITAL_DEPTH_8: 5259 info->bpc = 8; 5260 break; 5261 case DRM_EDID_DIGITAL_DEPTH_10: 5262 info->bpc = 10; 5263 break; 5264 case DRM_EDID_DIGITAL_DEPTH_12: 5265 info->bpc = 12; 5266 break; 5267 case DRM_EDID_DIGITAL_DEPTH_14: 5268 info->bpc = 14; 5269 break; 5270 case DRM_EDID_DIGITAL_DEPTH_16: 5271 info->bpc = 16; 5272 break; 5273 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5274 default: 5275 info->bpc = 0; 5276 break; 5277 } 5278 5279 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5280 connector->name, info->bpc); 5281 5282 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5283 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5284 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5285 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5286 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5287 return quirks; 5288 } 5289 5290 static int validate_displayid(u8 *displayid, int length, int idx) 5291 { 5292 int i, dispid_length; 5293 u8 csum = 0; 5294 struct displayid_hdr *base; 5295 5296 base = (struct displayid_hdr *)&displayid[idx]; 5297 5298 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5299 base->rev, base->bytes, base->prod_id, base->ext_count); 5300 5301 /* +1 for DispID checksum */ 5302 dispid_length = sizeof(*base) + base->bytes + 1; 5303 if (dispid_length > length - idx) 5304 return -EINVAL; 5305 5306 for (i = 0; i < dispid_length; i++) 5307 csum += displayid[idx + i]; 5308 if (csum) { 5309 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5310 return -EINVAL; 5311 } 5312 5313 return 0; 5314 } 5315 5316 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5317 struct displayid_detailed_timings_1 *timings) 5318 { 5319 struct drm_display_mode *mode; 5320 unsigned pixel_clock = (timings->pixel_clock[0] | 5321 (timings->pixel_clock[1] << 8) | 5322 (timings->pixel_clock[2] << 16)) + 1; 5323 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5324 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5325 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5326 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5327 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5328 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5329 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5330 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5331 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5332 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5333 5334 mode = drm_mode_create(dev); 5335 if (!mode) 5336 return NULL; 5337 5338 mode->clock = pixel_clock * 10; 5339 mode->hdisplay = hactive; 5340 mode->hsync_start = mode->hdisplay + hsync; 5341 mode->hsync_end = mode->hsync_start + hsync_width; 5342 mode->htotal = mode->hdisplay + hblank; 5343 5344 mode->vdisplay = vactive; 5345 mode->vsync_start = mode->vdisplay + vsync; 5346 mode->vsync_end = mode->vsync_start + vsync_width; 5347 mode->vtotal = mode->vdisplay + vblank; 5348 5349 mode->flags = 0; 5350 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5351 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5352 mode->type = DRM_MODE_TYPE_DRIVER; 5353 5354 if (timings->flags & 0x80) 5355 mode->type |= DRM_MODE_TYPE_PREFERRED; 5356 drm_mode_set_name(mode); 5357 5358 return mode; 5359 } 5360 5361 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5362 struct displayid_block *block) 5363 { 5364 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5365 int i; 5366 int num_timings; 5367 struct drm_display_mode *newmode; 5368 int num_modes = 0; 5369 /* blocks must be multiple of 20 bytes length */ 5370 if (block->num_bytes % 20) 5371 return 0; 5372 5373 num_timings = block->num_bytes / 20; 5374 for (i = 0; i < num_timings; i++) { 5375 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5376 5377 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5378 if (!newmode) 5379 continue; 5380 5381 drm_mode_probed_add(connector, newmode); 5382 num_modes++; 5383 } 5384 return num_modes; 5385 } 5386 5387 static int add_displayid_detailed_modes(struct drm_connector *connector, 5388 struct edid *edid) 5389 { 5390 u8 *displayid; 5391 int length, idx; 5392 struct displayid_block *block; 5393 int num_modes = 0; 5394 int ext_index = 0; 5395 5396 for (;;) { 5397 displayid = drm_find_displayid_extension(edid, &length, &idx, 5398 &ext_index); 5399 if (!displayid) 5400 break; 5401 5402 idx += sizeof(struct displayid_hdr); 5403 for_each_displayid_db(displayid, block, idx, length) { 5404 switch (block->tag) { 5405 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5406 num_modes += add_displayid_detailed_1_modes(connector, block); 5407 break; 5408 } 5409 } 5410 } 5411 5412 return num_modes; 5413 } 5414 5415 /** 5416 * drm_add_edid_modes - add modes from EDID data, if available 5417 * @connector: connector we're probing 5418 * @edid: EDID data 5419 * 5420 * Add the specified modes to the connector's mode list. Also fills out the 5421 * &drm_display_info structure and ELD in @connector with any information which 5422 * can be derived from the edid. 5423 * 5424 * Return: The number of modes added or 0 if we couldn't find any. 5425 */ 5426 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5427 { 5428 int num_modes = 0; 5429 u32 quirks; 5430 5431 if (edid == NULL) { 5432 clear_eld(connector); 5433 return 0; 5434 } 5435 if (!drm_edid_is_valid(edid)) { 5436 clear_eld(connector); 5437 drm_warn(connector->dev, "%s: EDID invalid.\n", 5438 connector->name); 5439 return 0; 5440 } 5441 5442 drm_edid_to_eld(connector, edid); 5443 5444 /* 5445 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5446 * To avoid multiple parsing of same block, lets parse that map 5447 * from sink info, before parsing CEA modes. 5448 */ 5449 quirks = drm_add_display_info(connector, edid); 5450 5451 /* 5452 * EDID spec says modes should be preferred in this order: 5453 * - preferred detailed mode 5454 * - other detailed modes from base block 5455 * - detailed modes from extension blocks 5456 * - CVT 3-byte code modes 5457 * - standard timing codes 5458 * - established timing codes 5459 * - modes inferred from GTF or CVT range information 5460 * 5461 * We get this pretty much right. 5462 * 5463 * XXX order for additional mode types in extension blocks? 5464 */ 5465 num_modes += add_detailed_modes(connector, edid, quirks); 5466 num_modes += add_cvt_modes(connector, edid); 5467 num_modes += add_standard_modes(connector, edid); 5468 num_modes += add_established_modes(connector, edid); 5469 num_modes += add_cea_modes(connector, edid); 5470 num_modes += add_alternate_cea_modes(connector, edid); 5471 num_modes += add_displayid_detailed_modes(connector, edid); 5472 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5473 num_modes += add_inferred_modes(connector, edid); 5474 5475 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5476 edid_fixup_preferred(connector, quirks); 5477 5478 if (quirks & EDID_QUIRK_FORCE_6BPC) 5479 connector->display_info.bpc = 6; 5480 5481 if (quirks & EDID_QUIRK_FORCE_8BPC) 5482 connector->display_info.bpc = 8; 5483 5484 if (quirks & EDID_QUIRK_FORCE_10BPC) 5485 connector->display_info.bpc = 10; 5486 5487 if (quirks & EDID_QUIRK_FORCE_12BPC) 5488 connector->display_info.bpc = 12; 5489 5490 return num_modes; 5491 } 5492 EXPORT_SYMBOL(drm_add_edid_modes); 5493 5494 /** 5495 * drm_add_modes_noedid - add modes for the connectors without EDID 5496 * @connector: connector we're probing 5497 * @hdisplay: the horizontal display limit 5498 * @vdisplay: the vertical display limit 5499 * 5500 * Add the specified modes to the connector's mode list. Only when the 5501 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5502 * 5503 * Return: The number of modes added or 0 if we couldn't find any. 5504 */ 5505 int drm_add_modes_noedid(struct drm_connector *connector, 5506 int hdisplay, int vdisplay) 5507 { 5508 int i, count, num_modes = 0; 5509 struct drm_display_mode *mode; 5510 struct drm_device *dev = connector->dev; 5511 5512 count = ARRAY_SIZE(drm_dmt_modes); 5513 if (hdisplay < 0) 5514 hdisplay = 0; 5515 if (vdisplay < 0) 5516 vdisplay = 0; 5517 5518 for (i = 0; i < count; i++) { 5519 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5520 5521 if (hdisplay && vdisplay) { 5522 /* 5523 * Only when two are valid, they will be used to check 5524 * whether the mode should be added to the mode list of 5525 * the connector. 5526 */ 5527 if (ptr->hdisplay > hdisplay || 5528 ptr->vdisplay > vdisplay) 5529 continue; 5530 } 5531 if (drm_mode_vrefresh(ptr) > 61) 5532 continue; 5533 mode = drm_mode_duplicate(dev, ptr); 5534 if (mode) { 5535 drm_mode_probed_add(connector, mode); 5536 num_modes++; 5537 } 5538 } 5539 return num_modes; 5540 } 5541 EXPORT_SYMBOL(drm_add_modes_noedid); 5542 5543 /** 5544 * drm_set_preferred_mode - Sets the preferred mode of a connector 5545 * @connector: connector whose mode list should be processed 5546 * @hpref: horizontal resolution of preferred mode 5547 * @vpref: vertical resolution of preferred mode 5548 * 5549 * Marks a mode as preferred if it matches the resolution specified by @hpref 5550 * and @vpref. 5551 */ 5552 void drm_set_preferred_mode(struct drm_connector *connector, 5553 int hpref, int vpref) 5554 { 5555 struct drm_display_mode *mode; 5556 5557 list_for_each_entry(mode, &connector->probed_modes, head) { 5558 if (mode->hdisplay == hpref && 5559 mode->vdisplay == vpref) 5560 mode->type |= DRM_MODE_TYPE_PREFERRED; 5561 } 5562 } 5563 EXPORT_SYMBOL(drm_set_preferred_mode); 5564 5565 static bool is_hdmi2_sink(const struct drm_connector *connector) 5566 { 5567 /* 5568 * FIXME: sil-sii8620 doesn't have a connector around when 5569 * we need one, so we have to be prepared for a NULL connector. 5570 */ 5571 if (!connector) 5572 return true; 5573 5574 return connector->display_info.hdmi.scdc.supported || 5575 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5576 } 5577 5578 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5579 { 5580 return sink_eotf & BIT(output_eotf); 5581 } 5582 5583 /** 5584 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5585 * HDR metadata from userspace 5586 * @frame: HDMI DRM infoframe 5587 * @conn_state: Connector state containing HDR metadata 5588 * 5589 * Return: 0 on success or a negative error code on failure. 5590 */ 5591 int 5592 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5593 const struct drm_connector_state *conn_state) 5594 { 5595 struct drm_connector *connector; 5596 struct hdr_output_metadata *hdr_metadata; 5597 int err; 5598 5599 if (!frame || !conn_state) 5600 return -EINVAL; 5601 5602 connector = conn_state->connector; 5603 5604 if (!conn_state->hdr_output_metadata) 5605 return -EINVAL; 5606 5607 hdr_metadata = conn_state->hdr_output_metadata->data; 5608 5609 if (!hdr_metadata || !connector) 5610 return -EINVAL; 5611 5612 /* Sink EOTF is Bit map while infoframe is absolute values */ 5613 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5614 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5615 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5616 return -EINVAL; 5617 } 5618 5619 err = hdmi_drm_infoframe_init(frame); 5620 if (err < 0) 5621 return err; 5622 5623 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5624 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5625 5626 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5627 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5628 BUILD_BUG_ON(sizeof(frame->white_point) != 5629 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5630 5631 memcpy(&frame->display_primaries, 5632 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5633 sizeof(frame->display_primaries)); 5634 5635 memcpy(&frame->white_point, 5636 &hdr_metadata->hdmi_metadata_type1.white_point, 5637 sizeof(frame->white_point)); 5638 5639 frame->max_display_mastering_luminance = 5640 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5641 frame->min_display_mastering_luminance = 5642 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5643 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5644 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5645 5646 return 0; 5647 } 5648 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5649 5650 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5651 const struct drm_display_mode *mode) 5652 { 5653 bool has_hdmi_infoframe = connector ? 5654 connector->display_info.has_hdmi_infoframe : false; 5655 5656 if (!has_hdmi_infoframe) 5657 return 0; 5658 5659 /* No HDMI VIC when signalling 3D video format */ 5660 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5661 return 0; 5662 5663 return drm_match_hdmi_mode(mode); 5664 } 5665 5666 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5667 const struct drm_display_mode *mode) 5668 { 5669 u8 vic; 5670 5671 /* 5672 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5673 * we should send its VIC in vendor infoframes, else send the 5674 * VIC in AVI infoframes. Lets check if this mode is present in 5675 * HDMI 1.4b 4K modes 5676 */ 5677 if (drm_mode_hdmi_vic(connector, mode)) 5678 return 0; 5679 5680 vic = drm_match_cea_mode(mode); 5681 5682 /* 5683 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5684 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5685 * have to make sure we dont break HDMI 1.4 sinks. 5686 */ 5687 if (!is_hdmi2_sink(connector) && vic > 64) 5688 return 0; 5689 5690 return vic; 5691 } 5692 5693 /** 5694 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5695 * data from a DRM display mode 5696 * @frame: HDMI AVI infoframe 5697 * @connector: the connector 5698 * @mode: DRM display mode 5699 * 5700 * Return: 0 on success or a negative error code on failure. 5701 */ 5702 int 5703 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5704 const struct drm_connector *connector, 5705 const struct drm_display_mode *mode) 5706 { 5707 enum hdmi_picture_aspect picture_aspect; 5708 u8 vic, hdmi_vic; 5709 5710 if (!frame || !mode) 5711 return -EINVAL; 5712 5713 hdmi_avi_infoframe_init(frame); 5714 5715 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5716 frame->pixel_repeat = 1; 5717 5718 vic = drm_mode_cea_vic(connector, mode); 5719 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5720 5721 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5722 5723 /* 5724 * As some drivers don't support atomic, we can't use connector state. 5725 * So just initialize the frame with default values, just the same way 5726 * as it's done with other properties here. 5727 */ 5728 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5729 frame->itc = 0; 5730 5731 /* 5732 * Populate picture aspect ratio from either 5733 * user input (if specified) or from the CEA/HDMI mode lists. 5734 */ 5735 picture_aspect = mode->picture_aspect_ratio; 5736 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5737 if (vic) 5738 picture_aspect = drm_get_cea_aspect_ratio(vic); 5739 else if (hdmi_vic) 5740 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5741 } 5742 5743 /* 5744 * The infoframe can't convey anything but none, 4:3 5745 * and 16:9, so if the user has asked for anything else 5746 * we can only satisfy it by specifying the right VIC. 5747 */ 5748 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5749 if (vic) { 5750 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5751 return -EINVAL; 5752 } else if (hdmi_vic) { 5753 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5754 return -EINVAL; 5755 } else { 5756 return -EINVAL; 5757 } 5758 5759 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5760 } 5761 5762 frame->video_code = vic; 5763 frame->picture_aspect = picture_aspect; 5764 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5765 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5766 5767 return 0; 5768 } 5769 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5770 5771 /* HDMI Colorspace Spec Definitions */ 5772 #define FULL_COLORIMETRY_MASK 0x1FF 5773 #define NORMAL_COLORIMETRY_MASK 0x3 5774 #define EXTENDED_COLORIMETRY_MASK 0x7 5775 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5776 5777 #define C(x) ((x) << 0) 5778 #define EC(x) ((x) << 2) 5779 #define ACE(x) ((x) << 5) 5780 5781 #define HDMI_COLORIMETRY_NO_DATA 0x0 5782 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5783 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5784 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5785 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5786 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5787 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5788 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5789 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5790 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5791 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5792 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5793 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5794 5795 static const u32 hdmi_colorimetry_val[] = { 5796 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5797 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5798 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5799 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5800 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5801 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5802 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5803 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5804 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5805 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5806 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5807 }; 5808 5809 #undef C 5810 #undef EC 5811 #undef ACE 5812 5813 /** 5814 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5815 * colorspace information 5816 * @frame: HDMI AVI infoframe 5817 * @conn_state: connector state 5818 */ 5819 void 5820 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5821 const struct drm_connector_state *conn_state) 5822 { 5823 u32 colorimetry_val; 5824 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5825 5826 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5827 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5828 else 5829 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5830 5831 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5832 /* 5833 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5834 * structure and extend it in drivers/video/hdmi 5835 */ 5836 frame->extended_colorimetry = (colorimetry_val >> 2) & 5837 EXTENDED_COLORIMETRY_MASK; 5838 } 5839 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5840 5841 /** 5842 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5843 * quantization range information 5844 * @frame: HDMI AVI infoframe 5845 * @connector: the connector 5846 * @mode: DRM display mode 5847 * @rgb_quant_range: RGB quantization range (Q) 5848 */ 5849 void 5850 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5851 const struct drm_connector *connector, 5852 const struct drm_display_mode *mode, 5853 enum hdmi_quantization_range rgb_quant_range) 5854 { 5855 const struct drm_display_info *info = &connector->display_info; 5856 5857 /* 5858 * CEA-861: 5859 * "A Source shall not send a non-zero Q value that does not correspond 5860 * to the default RGB Quantization Range for the transmitted Picture 5861 * unless the Sink indicates support for the Q bit in a Video 5862 * Capabilities Data Block." 5863 * 5864 * HDMI 2.0 recommends sending non-zero Q when it does match the 5865 * default RGB quantization range for the mode, even when QS=0. 5866 */ 5867 if (info->rgb_quant_range_selectable || 5868 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5869 frame->quantization_range = rgb_quant_range; 5870 else 5871 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5872 5873 /* 5874 * CEA-861-F: 5875 * "When transmitting any RGB colorimetry, the Source should set the 5876 * YQ-field to match the RGB Quantization Range being transmitted 5877 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5878 * set YQ=1) and the Sink shall ignore the YQ-field." 5879 * 5880 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5881 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5882 * good way to tell which version of CEA-861 the sink supports, so 5883 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5884 * on on CEA-861-F. 5885 */ 5886 if (!is_hdmi2_sink(connector) || 5887 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5888 frame->ycc_quantization_range = 5889 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5890 else 5891 frame->ycc_quantization_range = 5892 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5893 } 5894 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5895 5896 /** 5897 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5898 * bar information 5899 * @frame: HDMI AVI infoframe 5900 * @conn_state: connector state 5901 */ 5902 void 5903 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5904 const struct drm_connector_state *conn_state) 5905 { 5906 frame->right_bar = conn_state->tv.margins.right; 5907 frame->left_bar = conn_state->tv.margins.left; 5908 frame->top_bar = conn_state->tv.margins.top; 5909 frame->bottom_bar = conn_state->tv.margins.bottom; 5910 } 5911 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5912 5913 static enum hdmi_3d_structure 5914 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5915 { 5916 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5917 5918 switch (layout) { 5919 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5920 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5921 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5922 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5923 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5924 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5925 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5926 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5927 case DRM_MODE_FLAG_3D_L_DEPTH: 5928 return HDMI_3D_STRUCTURE_L_DEPTH; 5929 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5930 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5931 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5932 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5933 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5934 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5935 default: 5936 return HDMI_3D_STRUCTURE_INVALID; 5937 } 5938 } 5939 5940 /** 5941 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5942 * data from a DRM display mode 5943 * @frame: HDMI vendor infoframe 5944 * @connector: the connector 5945 * @mode: DRM display mode 5946 * 5947 * Note that there's is a need to send HDMI vendor infoframes only when using a 5948 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5949 * function will return -EINVAL, error that can be safely ignored. 5950 * 5951 * Return: 0 on success or a negative error code on failure. 5952 */ 5953 int 5954 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5955 const struct drm_connector *connector, 5956 const struct drm_display_mode *mode) 5957 { 5958 /* 5959 * FIXME: sil-sii8620 doesn't have a connector around when 5960 * we need one, so we have to be prepared for a NULL connector. 5961 */ 5962 bool has_hdmi_infoframe = connector ? 5963 connector->display_info.has_hdmi_infoframe : false; 5964 int err; 5965 5966 if (!frame || !mode) 5967 return -EINVAL; 5968 5969 if (!has_hdmi_infoframe) 5970 return -EINVAL; 5971 5972 err = hdmi_vendor_infoframe_init(frame); 5973 if (err < 0) 5974 return err; 5975 5976 /* 5977 * Even if it's not absolutely necessary to send the infoframe 5978 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5979 * know that the sink can handle it. This is based on a 5980 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5981 * have trouble realizing that they shuld switch from 3D to 2D 5982 * mode if the source simply stops sending the infoframe when 5983 * it wants to switch from 3D to 2D. 5984 */ 5985 frame->vic = drm_mode_hdmi_vic(connector, mode); 5986 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5987 5988 return 0; 5989 } 5990 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5991 5992 static void drm_parse_tiled_block(struct drm_connector *connector, 5993 const struct displayid_block *block) 5994 { 5995 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5996 u16 w, h; 5997 u8 tile_v_loc, tile_h_loc; 5998 u8 num_v_tile, num_h_tile; 5999 struct drm_tile_group *tg; 6000 6001 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6002 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6003 6004 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6005 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6006 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6007 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6008 6009 connector->has_tile = true; 6010 if (tile->tile_cap & 0x80) 6011 connector->tile_is_single_monitor = true; 6012 6013 connector->num_h_tile = num_h_tile + 1; 6014 connector->num_v_tile = num_v_tile + 1; 6015 connector->tile_h_loc = tile_h_loc; 6016 connector->tile_v_loc = tile_v_loc; 6017 connector->tile_h_size = w + 1; 6018 connector->tile_v_size = h + 1; 6019 6020 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6021 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6022 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6023 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6024 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6025 6026 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6027 if (!tg) 6028 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6029 if (!tg) 6030 return; 6031 6032 if (connector->tile_group != tg) { 6033 /* if we haven't got a pointer, 6034 take the reference, drop ref to old tile group */ 6035 if (connector->tile_group) 6036 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6037 connector->tile_group = tg; 6038 } else { 6039 /* if same tile group, then release the ref we just took. */ 6040 drm_mode_put_tile_group(connector->dev, tg); 6041 } 6042 } 6043 6044 static void drm_displayid_parse_tiled(struct drm_connector *connector, 6045 const u8 *displayid, int length, int idx) 6046 { 6047 const struct displayid_block *block; 6048 6049 idx += sizeof(struct displayid_hdr); 6050 for_each_displayid_db(displayid, block, idx, length) { 6051 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 6052 block->tag, block->rev, block->num_bytes); 6053 6054 switch (block->tag) { 6055 case DATA_BLOCK_TILED_DISPLAY: 6056 drm_parse_tiled_block(connector, block); 6057 break; 6058 default: 6059 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 6060 break; 6061 } 6062 } 6063 } 6064 6065 void drm_update_tile_info(struct drm_connector *connector, 6066 const struct edid *edid) 6067 { 6068 const void *displayid = NULL; 6069 int ext_index = 0; 6070 int length, idx; 6071 6072 connector->has_tile = false; 6073 for (;;) { 6074 displayid = drm_find_displayid_extension(edid, &length, &idx, 6075 &ext_index); 6076 if (!displayid) 6077 break; 6078 6079 drm_displayid_parse_tiled(connector, displayid, length, idx); 6080 } 6081 6082 if (!connector->has_tile && connector->tile_group) { 6083 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6084 connector->tile_group = NULL; 6085 } 6086 } 6087