1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 163 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 164 165 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 166 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Valve Index Headset */ 169 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 170 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 171 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 172 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 186 187 /* HTC Vive and Vive Pro VR Headsets */ 188 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 189 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 190 191 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 192 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 193 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 194 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 195 196 /* Windows Mixed Reality Headsets */ 197 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 198 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 199 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 200 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 201 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 202 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 203 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 204 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 205 206 /* Sony PlayStation VR Headset */ 207 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 208 209 /* Sensics VR Headsets */ 210 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 211 212 /* OSVR HDK and HDK2 VR Headsets */ 213 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 214 }; 215 216 /* 217 * Autogenerated from the DMT spec. 218 * This table is copied from xfree86/modes/xf86EdidModes.c. 219 */ 220 static const struct drm_display_mode drm_dmt_modes[] = { 221 /* 0x01 - 640x350@85Hz */ 222 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 223 736, 832, 0, 350, 382, 385, 445, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 225 /* 0x02 - 640x400@85Hz */ 226 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 400, 401, 404, 445, 0, 228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 229 /* 0x03 - 720x400@85Hz */ 230 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 231 828, 936, 0, 400, 401, 404, 446, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x04 - 640x480@60Hz */ 234 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 235 752, 800, 0, 480, 490, 492, 525, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 0x05 - 640x480@72Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 239 704, 832, 0, 480, 489, 492, 520, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x06 - 640x480@75Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 243 720, 840, 0, 480, 481, 484, 500, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x07 - 640x480@85Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 247 752, 832, 0, 480, 481, 484, 509, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x08 - 800x600@56Hz */ 250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 251 896, 1024, 0, 600, 601, 603, 625, 0, 252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x09 - 800x600@60Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 255 968, 1056, 0, 600, 601, 605, 628, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x0a - 800x600@72Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 259 976, 1040, 0, 600, 637, 643, 666, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0b - 800x600@75Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 263 896, 1056, 0, 600, 601, 604, 625, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0c - 800x600@85Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 267 896, 1048, 0, 600, 601, 604, 631, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0d - 800x600@120Hz RB */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 271 880, 960, 0, 600, 603, 607, 636, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 273 /* 0x0e - 848x480@60Hz */ 274 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 275 976, 1088, 0, 480, 486, 494, 517, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0f - 1024x768@43Hz, interlace */ 278 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 279 1208, 1264, 0, 768, 768, 776, 817, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 281 DRM_MODE_FLAG_INTERLACE) }, 282 /* 0x10 - 1024x768@60Hz */ 283 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 284 1184, 1344, 0, 768, 771, 777, 806, 0, 285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 286 /* 0x11 - 1024x768@70Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 288 1184, 1328, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x12 - 1024x768@75Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 292 1136, 1312, 0, 768, 769, 772, 800, 0, 293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x13 - 1024x768@85Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 296 1168, 1376, 0, 768, 769, 772, 808, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x14 - 1024x768@120Hz RB */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 300 1104, 1184, 0, 768, 771, 775, 813, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 302 /* 0x15 - 1152x864@75Hz */ 303 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 304 1344, 1600, 0, 864, 865, 868, 900, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x55 - 1280x720@60Hz */ 307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 308 1430, 1650, 0, 720, 725, 730, 750, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x16 - 1280x768@60Hz RB */ 311 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 312 1360, 1440, 0, 768, 771, 778, 790, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x17 - 1280x768@60Hz */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 316 1472, 1664, 0, 768, 771, 778, 798, 0, 317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x18 - 1280x768@75Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 320 1488, 1696, 0, 768, 771, 778, 805, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x19 - 1280x768@85Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 324 1496, 1712, 0, 768, 771, 778, 809, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x1a - 1280x768@120Hz RB */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 328 1360, 1440, 0, 768, 771, 778, 813, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 330 /* 0x1b - 1280x800@60Hz RB */ 331 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 332 1360, 1440, 0, 800, 803, 809, 823, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1c - 1280x800@60Hz */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 336 1480, 1680, 0, 800, 803, 809, 831, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x1d - 1280x800@75Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 340 1488, 1696, 0, 800, 803, 809, 838, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1e - 1280x800@85Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 344 1496, 1712, 0, 800, 803, 809, 843, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1f - 1280x800@120Hz RB */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 348 1360, 1440, 0, 800, 803, 809, 847, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x20 - 1280x960@60Hz */ 351 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 352 1488, 1800, 0, 960, 961, 964, 1000, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x21 - 1280x960@85Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 356 1504, 1728, 0, 960, 961, 964, 1011, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x22 - 1280x960@120Hz RB */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 360 1360, 1440, 0, 960, 963, 967, 1017, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x23 - 1280x1024@60Hz */ 363 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 364 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x24 - 1280x1024@75Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x25 - 1280x1024@85Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 372 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x26 - 1280x1024@120Hz RB */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 376 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 378 /* 0x27 - 1360x768@60Hz */ 379 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 380 1536, 1792, 0, 768, 771, 777, 795, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x28 - 1360x768@120Hz RB */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 384 1440, 1520, 0, 768, 771, 776, 813, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 386 /* 0x51 - 1366x768@60Hz */ 387 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 388 1579, 1792, 0, 768, 771, 774, 798, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x56 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 392 1436, 1500, 0, 768, 769, 772, 800, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x29 - 1400x1050@60Hz RB */ 395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 396 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x2a - 1400x1050@60Hz */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 400 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x2b - 1400x1050@75Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 404 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2c - 1400x1050@85Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 408 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2d - 1400x1050@120Hz RB */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 412 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 414 /* 0x2e - 1440x900@60Hz RB */ 415 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 416 1520, 1600, 0, 900, 903, 909, 926, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2f - 1440x900@60Hz */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 420 1672, 1904, 0, 900, 903, 909, 934, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x30 - 1440x900@75Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 424 1688, 1936, 0, 900, 903, 909, 942, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x31 - 1440x900@85Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 428 1696, 1952, 0, 900, 903, 909, 948, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x32 - 1440x900@120Hz RB */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 432 1520, 1600, 0, 900, 903, 909, 953, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x53 - 1600x900@60Hz */ 435 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 436 1704, 1800, 0, 900, 901, 904, 1000, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x33 - 1600x1200@60Hz */ 439 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 440 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x34 - 1600x1200@65Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x35 - 1600x1200@70Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x36 - 1600x1200@75Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x37 - 1600x1200@85Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x38 - 1600x1200@120Hz RB */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 460 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 462 /* 0x39 - 1680x1050@60Hz RB */ 463 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 464 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x3a - 1680x1050@60Hz */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 468 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x3b - 1680x1050@75Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 472 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3c - 1680x1050@85Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 476 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3d - 1680x1050@120Hz RB */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 480 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x3e - 1792x1344@60Hz */ 483 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 484 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x3f - 1792x1344@75Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 488 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x40 - 1792x1344@120Hz RB */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 492 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 494 /* 0x41 - 1856x1392@60Hz */ 495 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 496 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x42 - 1856x1392@75Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 500 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x43 - 1856x1392@120Hz RB */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 504 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x52 - 1920x1080@60Hz */ 507 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 508 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x44 - 1920x1200@60Hz RB */ 511 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 512 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x45 - 1920x1200@60Hz */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 516 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x46 - 1920x1200@75Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 520 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x47 - 1920x1200@85Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 524 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x48 - 1920x1200@120Hz RB */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 528 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x49 - 1920x1440@60Hz */ 531 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 532 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x4a - 1920x1440@75Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 536 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4b - 1920x1440@120Hz RB */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 540 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 542 /* 0x54 - 2048x1152@60Hz */ 543 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 544 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x4c - 2560x1600@60Hz RB */ 547 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 548 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x4d - 2560x1600@60Hz */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 552 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4e - 2560x1600@75Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 556 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4f - 2560x1600@85Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x50 - 2560x1600@120Hz RB */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 564 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 566 /* 0x57 - 4096x2160@60Hz RB */ 567 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 568 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x58 - 4096x2160@59.94Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 }; 575 576 /* 577 * These more or less come from the DMT spec. The 720x400 modes are 578 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 579 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 580 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 581 * mode. 582 * 583 * The DMT modes have been fact-checked; the rest are mild guesses. 584 */ 585 static const struct drm_display_mode edid_est_modes[] = { 586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 587 968, 1056, 0, 600, 601, 605, 628, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 590 896, 1024, 0, 600, 601, 603, 625, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 593 720, 840, 0, 480, 481, 484, 500, 0, 594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 596 704, 832, 0, 480, 489, 492, 520, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 599 768, 864, 0, 480, 483, 486, 525, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 602 752, 800, 0, 480, 490, 492, 525, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 605 846, 900, 0, 400, 421, 423, 449, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 608 846, 900, 0, 400, 412, 414, 449, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 610 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 611 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 614 1136, 1312, 0, 768, 769, 772, 800, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 617 1184, 1328, 0, 768, 771, 777, 806, 0, 618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 620 1184, 1344, 0, 768, 771, 777, 806, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 622 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 623 1208, 1264, 0, 768, 768, 776, 817, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 625 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 626 928, 1152, 0, 624, 625, 628, 667, 0, 627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 629 896, 1056, 0, 600, 601, 604, 625, 0, 630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 632 976, 1040, 0, 600, 637, 643, 666, 0, 633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 634 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 635 1344, 1600, 0, 864, 865, 868, 900, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 637 }; 638 639 struct minimode { 640 short w; 641 short h; 642 short r; 643 short rb; 644 }; 645 646 static const struct minimode est3_modes[] = { 647 /* byte 6 */ 648 { 640, 350, 85, 0 }, 649 { 640, 400, 85, 0 }, 650 { 720, 400, 85, 0 }, 651 { 640, 480, 85, 0 }, 652 { 848, 480, 60, 0 }, 653 { 800, 600, 85, 0 }, 654 { 1024, 768, 85, 0 }, 655 { 1152, 864, 75, 0 }, 656 /* byte 7 */ 657 { 1280, 768, 60, 1 }, 658 { 1280, 768, 60, 0 }, 659 { 1280, 768, 75, 0 }, 660 { 1280, 768, 85, 0 }, 661 { 1280, 960, 60, 0 }, 662 { 1280, 960, 85, 0 }, 663 { 1280, 1024, 60, 0 }, 664 { 1280, 1024, 85, 0 }, 665 /* byte 8 */ 666 { 1360, 768, 60, 0 }, 667 { 1440, 900, 60, 1 }, 668 { 1440, 900, 60, 0 }, 669 { 1440, 900, 75, 0 }, 670 { 1440, 900, 85, 0 }, 671 { 1400, 1050, 60, 1 }, 672 { 1400, 1050, 60, 0 }, 673 { 1400, 1050, 75, 0 }, 674 /* byte 9 */ 675 { 1400, 1050, 85, 0 }, 676 { 1680, 1050, 60, 1 }, 677 { 1680, 1050, 60, 0 }, 678 { 1680, 1050, 75, 0 }, 679 { 1680, 1050, 85, 0 }, 680 { 1600, 1200, 60, 0 }, 681 { 1600, 1200, 65, 0 }, 682 { 1600, 1200, 70, 0 }, 683 /* byte 10 */ 684 { 1600, 1200, 75, 0 }, 685 { 1600, 1200, 85, 0 }, 686 { 1792, 1344, 60, 0 }, 687 { 1792, 1344, 75, 0 }, 688 { 1856, 1392, 60, 0 }, 689 { 1856, 1392, 75, 0 }, 690 { 1920, 1200, 60, 1 }, 691 { 1920, 1200, 60, 0 }, 692 /* byte 11 */ 693 { 1920, 1200, 75, 0 }, 694 { 1920, 1200, 85, 0 }, 695 { 1920, 1440, 60, 0 }, 696 { 1920, 1440, 75, 0 }, 697 }; 698 699 static const struct minimode extra_modes[] = { 700 { 1024, 576, 60, 0 }, 701 { 1366, 768, 60, 0 }, 702 { 1600, 900, 60, 0 }, 703 { 1680, 945, 60, 0 }, 704 { 1920, 1080, 60, 0 }, 705 { 2048, 1152, 60, 0 }, 706 { 2048, 1536, 60, 0 }, 707 }; 708 709 /* 710 * Probably taken from CEA-861 spec. 711 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 712 * 713 * Index using the VIC. 714 */ 715 static const struct drm_display_mode edid_cea_modes[] = { 716 /* 0 - dummy, VICs start at 1 */ 717 { }, 718 /* 1 - 640x480@60Hz 4:3 */ 719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 720 752, 800, 0, 480, 490, 492, 525, 0, 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 2 - 720x480@60Hz 4:3 */ 724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 725 798, 858, 0, 480, 489, 495, 525, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 3 - 720x480@60Hz 16:9 */ 729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 730 798, 858, 0, 480, 489, 495, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 733 /* 4 - 1280x720@60Hz 16:9 */ 734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 735 1430, 1650, 0, 720, 725, 730, 750, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 738 /* 5 - 1920x1080i@60Hz 16:9 */ 739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 742 DRM_MODE_FLAG_INTERLACE), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 6 - 720(1440)x480i@60Hz 4:3 */ 745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 746 801, 858, 0, 480, 488, 494, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 750 /* 7 - 720(1440)x480i@60Hz 16:9 */ 751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 752 801, 858, 0, 480, 488, 494, 525, 0, 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 8 - 720(1440)x240@60Hz 4:3 */ 757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 758 801, 858, 0, 240, 244, 247, 262, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 760 DRM_MODE_FLAG_DBLCLK), 761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 762 /* 9 - 720(1440)x240@60Hz 16:9 */ 763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 764 801, 858, 0, 240, 244, 247, 262, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 766 DRM_MODE_FLAG_DBLCLK), 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 768 /* 10 - 2880x480i@60Hz 4:3 */ 769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 770 3204, 3432, 0, 480, 488, 494, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 772 DRM_MODE_FLAG_INTERLACE), 773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 774 /* 11 - 2880x480i@60Hz 16:9 */ 775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 776 3204, 3432, 0, 480, 488, 494, 525, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 778 DRM_MODE_FLAG_INTERLACE), 779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 12 - 2880x240@60Hz 4:3 */ 781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 782 3204, 3432, 0, 240, 244, 247, 262, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 785 /* 13 - 2880x240@60Hz 16:9 */ 786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 240, 244, 247, 262, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 14 - 1440x480@60Hz 4:3 */ 791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 792 1596, 1716, 0, 480, 489, 495, 525, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 15 - 1440x480@60Hz 16:9 */ 796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 797 1596, 1716, 0, 480, 489, 495, 525, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 16 - 1920x1080@60Hz 16:9 */ 801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 805 /* 17 - 720x576@50Hz 4:3 */ 806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 807 796, 864, 0, 576, 581, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 18 - 720x576@50Hz 16:9 */ 811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 812 796, 864, 0, 576, 581, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 19 - 1280x720@50Hz 16:9 */ 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 817 1760, 1980, 0, 720, 725, 730, 750, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 20 - 1920x1080i@50Hz 16:9 */ 821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 824 DRM_MODE_FLAG_INTERLACE), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 21 - 720(1440)x576i@50Hz 4:3 */ 827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 828 795, 864, 0, 576, 580, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 832 /* 22 - 720(1440)x576i@50Hz 16:9 */ 833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 834 795, 864, 0, 576, 580, 586, 625, 0, 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 23 - 720(1440)x288@50Hz 4:3 */ 839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 840 795, 864, 0, 288, 290, 293, 312, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 842 DRM_MODE_FLAG_DBLCLK), 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 24 - 720(1440)x288@50Hz 16:9 */ 845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 846 795, 864, 0, 288, 290, 293, 312, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 848 DRM_MODE_FLAG_DBLCLK), 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 850 /* 25 - 2880x576i@50Hz 4:3 */ 851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 852 3180, 3456, 0, 576, 580, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 854 DRM_MODE_FLAG_INTERLACE), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 856 /* 26 - 2880x576i@50Hz 16:9 */ 857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 858 3180, 3456, 0, 576, 580, 586, 625, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 27 - 2880x288@50Hz 4:3 */ 863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 864 3180, 3456, 0, 288, 290, 293, 312, 0, 865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 867 /* 28 - 2880x288@50Hz 16:9 */ 868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 288, 290, 293, 312, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 872 /* 29 - 1440x576@50Hz 4:3 */ 873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 874 1592, 1728, 0, 576, 581, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 877 /* 30 - 1440x576@50Hz 16:9 */ 878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 879 1592, 1728, 0, 576, 581, 586, 625, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 31 - 1920x1080@50Hz 16:9 */ 883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 887 /* 32 - 1920x1080@24Hz 16:9 */ 888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 33 - 1920x1080@25Hz 16:9 */ 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 34 - 1920x1080@30Hz 16:9 */ 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 35 - 2880x480@60Hz 4:3 */ 903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 904 3192, 3432, 0, 480, 489, 495, 525, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 907 /* 36 - 2880x480@60Hz 16:9 */ 908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 909 3192, 3432, 0, 480, 489, 495, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 37 - 2880x576@50Hz 4:3 */ 913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 914 3184, 3456, 0, 576, 581, 586, 625, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 917 /* 38 - 2880x576@50Hz 16:9 */ 918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 919 3184, 3456, 0, 576, 581, 586, 625, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 39 - 1920x1080i@50Hz 16:9 */ 923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 926 DRM_MODE_FLAG_INTERLACE), 927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 40 - 1920x1080i@100Hz 16:9 */ 929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 932 DRM_MODE_FLAG_INTERLACE), 933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 41 - 1280x720@100Hz 16:9 */ 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 936 1760, 1980, 0, 720, 725, 730, 750, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 42 - 720x576@100Hz 4:3 */ 940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 941 796, 864, 0, 576, 581, 586, 625, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 944 /* 43 - 720x576@100Hz 16:9 */ 945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 946 796, 864, 0, 576, 581, 586, 625, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 44 - 720(1440)x576i@100Hz 4:3 */ 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 951 795, 864, 0, 576, 580, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 955 /* 45 - 720(1440)x576i@100Hz 16:9 */ 956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 957 795, 864, 0, 576, 580, 586, 625, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 961 /* 46 - 1920x1080i@120Hz 16:9 */ 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 965 DRM_MODE_FLAG_INTERLACE), 966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 967 /* 47 - 1280x720@120Hz 16:9 */ 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 969 1430, 1650, 0, 720, 725, 730, 750, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 48 - 720x480@120Hz 4:3 */ 973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 974 798, 858, 0, 480, 489, 495, 525, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 977 /* 49 - 720x480@120Hz 16:9 */ 978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 979 798, 858, 0, 480, 489, 495, 525, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 50 - 720(1440)x480i@120Hz 4:3 */ 983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 984 801, 858, 0, 480, 488, 494, 525, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 988 /* 51 - 720(1440)x480i@120Hz 16:9 */ 989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 990 801, 858, 0, 480, 488, 494, 525, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 52 - 720x576@200Hz 4:3 */ 995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 996 796, 864, 0, 576, 581, 586, 625, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 999 /* 53 - 720x576@200Hz 16:9 */ 1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1001 796, 864, 0, 576, 581, 586, 625, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1006 795, 864, 0, 576, 580, 586, 625, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1010 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1012 795, 864, 0, 576, 580, 586, 625, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1016 /* 56 - 720x480@240Hz 4:3 */ 1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1018 798, 858, 0, 480, 489, 495, 525, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1021 /* 57 - 720x480@240Hz 16:9 */ 1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1023 798, 858, 0, 480, 489, 495, 525, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1028 801, 858, 0, 480, 488, 494, 525, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1032 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1034 801, 858, 0, 480, 488, 494, 525, 0, 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1038 /* 60 - 1280x720@24Hz 16:9 */ 1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1040 3080, 3300, 0, 720, 725, 730, 750, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 61 - 1280x720@25Hz 16:9 */ 1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1045 3740, 3960, 0, 720, 725, 730, 750, 0, 1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1048 /* 62 - 1280x720@30Hz 16:9 */ 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1050 3080, 3300, 0, 720, 725, 730, 750, 0, 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1053 /* 63 - 1920x1080@120Hz 16:9 */ 1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 64 - 1920x1080@100Hz 16:9 */ 1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 65 - 1280x720@24Hz 64:27 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1065 3080, 3300, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1068 /* 66 - 1280x720@25Hz 64:27 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1070 3740, 3960, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1073 /* 67 - 1280x720@30Hz 64:27 */ 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1075 3080, 3300, 0, 720, 725, 730, 750, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1078 /* 68 - 1280x720@50Hz 64:27 */ 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1080 1760, 1980, 0, 720, 725, 730, 750, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1083 /* 69 - 1280x720@60Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 70 - 1280x720@100Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1090 1760, 1980, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 71 - 1280x720@120Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1095 1430, 1650, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 72 - 1920x1080@24Hz 64:27 */ 1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 73 - 1920x1080@25Hz 64:27 */ 1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 74 - 1920x1080@30Hz 64:27 */ 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 75 - 1920x1080@50Hz 64:27 */ 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 76 - 1920x1080@60Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 77 - 1920x1080@100Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 78 - 1920x1080@120Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 79 - 1680x720@24Hz 64:27 */ 1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1135 3080, 3300, 0, 720, 725, 730, 750, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 80 - 1680x720@25Hz 64:27 */ 1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1140 2948, 3168, 0, 720, 725, 730, 750, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 81 - 1680x720@30Hz 64:27 */ 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1145 2420, 2640, 0, 720, 725, 730, 750, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 82 - 1680x720@50Hz 64:27 */ 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1150 1980, 2200, 0, 720, 725, 730, 750, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 83 - 1680x720@60Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1155 1980, 2200, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 84 - 1680x720@100Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1160 1780, 2000, 0, 720, 725, 730, 825, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 85 - 1680x720@120Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1165 1780, 2000, 0, 720, 725, 730, 825, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 86 - 2560x1080@24Hz 64:27 */ 1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 87 - 2560x1080@25Hz 64:27 */ 1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 88 - 2560x1080@30Hz 64:27 */ 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 89 - 2560x1080@50Hz 64:27 */ 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 90 - 2560x1080@60Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 91 - 2560x1080@100Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 92 - 2560x1080@120Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 93 - 3840x2160@24Hz 16:9 */ 1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1208 /* 94 - 3840x2160@25Hz 16:9 */ 1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1213 /* 95 - 3840x2160@30Hz 16:9 */ 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1218 /* 96 - 3840x2160@50Hz 16:9 */ 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1223 /* 97 - 3840x2160@60Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 98 - 4096x2160@24Hz 256:135 */ 1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1233 /* 99 - 4096x2160@25Hz 256:135 */ 1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1238 /* 100 - 4096x2160@30Hz 256:135 */ 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1243 /* 101 - 4096x2160@50Hz 256:135 */ 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1248 /* 102 - 4096x2160@60Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 103 - 3840x2160@24Hz 64:27 */ 1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1258 /* 104 - 3840x2160@25Hz 64:27 */ 1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1263 /* 105 - 3840x2160@30Hz 64:27 */ 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1268 /* 106 - 3840x2160@50Hz 64:27 */ 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1273 /* 107 - 3840x2160@60Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 }; 1279 1280 /* 1281 * HDMI 1.4 4k modes. Index using the VIC. 1282 */ 1283 static const struct drm_display_mode edid_4k_modes[] = { 1284 /* 0 - dummy, VICs start at 1 */ 1285 { }, 1286 /* 1 - 3840x2160@30Hz */ 1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1288 3840, 4016, 4104, 4400, 0, 1289 2160, 2168, 2178, 2250, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .vrefresh = 30, }, 1292 /* 2 - 3840x2160@25Hz */ 1293 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1294 3840, 4896, 4984, 5280, 0, 1295 2160, 2168, 2178, 2250, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .vrefresh = 25, }, 1298 /* 3 - 3840x2160@24Hz */ 1299 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1300 3840, 5116, 5204, 5500, 0, 1301 2160, 2168, 2178, 2250, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .vrefresh = 24, }, 1304 /* 4 - 4096x2160@24Hz (SMPTE) */ 1305 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1306 4096, 5116, 5204, 5500, 0, 1307 2160, 2168, 2178, 2250, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .vrefresh = 24, }, 1310 }; 1311 1312 /*** DDC fetch and block validation ***/ 1313 1314 static const u8 edid_header[] = { 1315 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1316 }; 1317 1318 /** 1319 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1320 * @raw_edid: pointer to raw base EDID block 1321 * 1322 * Sanity check the header of the base EDID block. 1323 * 1324 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1325 */ 1326 int drm_edid_header_is_valid(const u8 *raw_edid) 1327 { 1328 int i, score = 0; 1329 1330 for (i = 0; i < sizeof(edid_header); i++) 1331 if (raw_edid[i] == edid_header[i]) 1332 score++; 1333 1334 return score; 1335 } 1336 EXPORT_SYMBOL(drm_edid_header_is_valid); 1337 1338 static int edid_fixup __read_mostly = 6; 1339 module_param_named(edid_fixup, edid_fixup, int, 0400); 1340 MODULE_PARM_DESC(edid_fixup, 1341 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1342 1343 static void drm_get_displayid(struct drm_connector *connector, 1344 struct edid *edid); 1345 1346 static int drm_edid_block_checksum(const u8 *raw_edid) 1347 { 1348 int i; 1349 u8 csum = 0; 1350 for (i = 0; i < EDID_LENGTH; i++) 1351 csum += raw_edid[i]; 1352 1353 return csum; 1354 } 1355 1356 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1357 { 1358 if (memchr_inv(in_edid, 0, length)) 1359 return false; 1360 1361 return true; 1362 } 1363 1364 /** 1365 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1366 * @raw_edid: pointer to raw EDID block 1367 * @block: type of block to validate (0 for base, extension otherwise) 1368 * @print_bad_edid: if true, dump bad EDID blocks to the console 1369 * @edid_corrupt: if true, the header or checksum is invalid 1370 * 1371 * Validate a base or extension EDID block and optionally dump bad blocks to 1372 * the console. 1373 * 1374 * Return: True if the block is valid, false otherwise. 1375 */ 1376 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1377 bool *edid_corrupt) 1378 { 1379 u8 csum; 1380 struct edid *edid = (struct edid *)raw_edid; 1381 1382 if (WARN_ON(!raw_edid)) 1383 return false; 1384 1385 if (edid_fixup > 8 || edid_fixup < 0) 1386 edid_fixup = 6; 1387 1388 if (block == 0) { 1389 int score = drm_edid_header_is_valid(raw_edid); 1390 if (score == 8) { 1391 if (edid_corrupt) 1392 *edid_corrupt = false; 1393 } else if (score >= edid_fixup) { 1394 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1395 * The corrupt flag needs to be set here otherwise, the 1396 * fix-up code here will correct the problem, the 1397 * checksum is correct and the test fails 1398 */ 1399 if (edid_corrupt) 1400 *edid_corrupt = true; 1401 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1402 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1403 } else { 1404 if (edid_corrupt) 1405 *edid_corrupt = true; 1406 goto bad; 1407 } 1408 } 1409 1410 csum = drm_edid_block_checksum(raw_edid); 1411 if (csum) { 1412 if (edid_corrupt) 1413 *edid_corrupt = true; 1414 1415 /* allow CEA to slide through, switches mangle this */ 1416 if (raw_edid[0] == CEA_EXT) { 1417 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1418 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1419 } else { 1420 if (print_bad_edid) 1421 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1422 1423 goto bad; 1424 } 1425 } 1426 1427 /* per-block-type checks */ 1428 switch (raw_edid[0]) { 1429 case 0: /* base */ 1430 if (edid->version != 1) { 1431 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1432 goto bad; 1433 } 1434 1435 if (edid->revision > 4) 1436 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1437 break; 1438 1439 default: 1440 break; 1441 } 1442 1443 return true; 1444 1445 bad: 1446 if (print_bad_edid) { 1447 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1448 pr_notice("EDID block is all zeroes\n"); 1449 } else { 1450 pr_notice("Raw EDID:\n"); 1451 print_hex_dump(KERN_NOTICE, 1452 " \t", DUMP_PREFIX_NONE, 16, 1, 1453 raw_edid, EDID_LENGTH, false); 1454 } 1455 } 1456 return false; 1457 } 1458 EXPORT_SYMBOL(drm_edid_block_valid); 1459 1460 /** 1461 * drm_edid_is_valid - sanity check EDID data 1462 * @edid: EDID data 1463 * 1464 * Sanity-check an entire EDID record (including extensions) 1465 * 1466 * Return: True if the EDID data is valid, false otherwise. 1467 */ 1468 bool drm_edid_is_valid(struct edid *edid) 1469 { 1470 int i; 1471 u8 *raw = (u8 *)edid; 1472 1473 if (!edid) 1474 return false; 1475 1476 for (i = 0; i <= edid->extensions; i++) 1477 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1478 return false; 1479 1480 return true; 1481 } 1482 EXPORT_SYMBOL(drm_edid_is_valid); 1483 1484 #define DDC_SEGMENT_ADDR 0x30 1485 /** 1486 * drm_do_probe_ddc_edid() - get EDID information via I2C 1487 * @data: I2C device adapter 1488 * @buf: EDID data buffer to be filled 1489 * @block: 128 byte EDID block to start fetching from 1490 * @len: EDID data buffer length to fetch 1491 * 1492 * Try to fetch EDID information by calling I2C driver functions. 1493 * 1494 * Return: 0 on success or -1 on failure. 1495 */ 1496 static int 1497 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1498 { 1499 struct i2c_adapter *adapter = data; 1500 unsigned char start = block * EDID_LENGTH; 1501 unsigned char segment = block >> 1; 1502 unsigned char xfers = segment ? 3 : 2; 1503 int ret, retries = 5; 1504 1505 /* 1506 * The core I2C driver will automatically retry the transfer if the 1507 * adapter reports EAGAIN. However, we find that bit-banging transfers 1508 * are susceptible to errors under a heavily loaded machine and 1509 * generate spurious NAKs and timeouts. Retrying the transfer 1510 * of the individual block a few times seems to overcome this. 1511 */ 1512 do { 1513 struct i2c_msg msgs[] = { 1514 { 1515 .addr = DDC_SEGMENT_ADDR, 1516 .flags = 0, 1517 .len = 1, 1518 .buf = &segment, 1519 }, { 1520 .addr = DDC_ADDR, 1521 .flags = 0, 1522 .len = 1, 1523 .buf = &start, 1524 }, { 1525 .addr = DDC_ADDR, 1526 .flags = I2C_M_RD, 1527 .len = len, 1528 .buf = buf, 1529 } 1530 }; 1531 1532 /* 1533 * Avoid sending the segment addr to not upset non-compliant 1534 * DDC monitors. 1535 */ 1536 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1537 1538 if (ret == -ENXIO) { 1539 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1540 adapter->name); 1541 break; 1542 } 1543 } while (ret != xfers && --retries); 1544 1545 return ret == xfers ? 0 : -1; 1546 } 1547 1548 static void connector_bad_edid(struct drm_connector *connector, 1549 u8 *edid, int num_blocks) 1550 { 1551 int i; 1552 1553 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1554 return; 1555 1556 dev_warn(connector->dev->dev, 1557 "%s: EDID is invalid:\n", 1558 connector->name); 1559 for (i = 0; i < num_blocks; i++) { 1560 u8 *block = edid + i * EDID_LENGTH; 1561 char prefix[20]; 1562 1563 if (drm_edid_is_zero(block, EDID_LENGTH)) 1564 sprintf(prefix, "\t[%02x] ZERO ", i); 1565 else if (!drm_edid_block_valid(block, i, false, NULL)) 1566 sprintf(prefix, "\t[%02x] BAD ", i); 1567 else 1568 sprintf(prefix, "\t[%02x] GOOD ", i); 1569 1570 print_hex_dump(KERN_WARNING, 1571 prefix, DUMP_PREFIX_NONE, 16, 1, 1572 block, EDID_LENGTH, false); 1573 } 1574 } 1575 1576 /** 1577 * drm_do_get_edid - get EDID data using a custom EDID block read function 1578 * @connector: connector we're probing 1579 * @get_edid_block: EDID block read function 1580 * @data: private data passed to the block read function 1581 * 1582 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1583 * exposes a different interface to read EDID blocks this function can be used 1584 * to get EDID data using a custom block read function. 1585 * 1586 * As in the general case the DDC bus is accessible by the kernel at the I2C 1587 * level, drivers must make all reasonable efforts to expose it as an I2C 1588 * adapter and use drm_get_edid() instead of abusing this function. 1589 * 1590 * The EDID may be overridden using debugfs override_edid or firmare EDID 1591 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1592 * order. Having either of them bypasses actual EDID reads. 1593 * 1594 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1595 */ 1596 struct edid *drm_do_get_edid(struct drm_connector *connector, 1597 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1598 size_t len), 1599 void *data) 1600 { 1601 int i, j = 0, valid_extensions = 0; 1602 u8 *edid, *new; 1603 struct edid *override = NULL; 1604 1605 if (connector->override_edid) 1606 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1607 1608 if (!override) 1609 override = drm_load_edid_firmware(connector); 1610 1611 if (!IS_ERR_OR_NULL(override)) 1612 return override; 1613 1614 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1615 return NULL; 1616 1617 /* base block fetch */ 1618 for (i = 0; i < 4; i++) { 1619 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1620 goto out; 1621 if (drm_edid_block_valid(edid, 0, false, 1622 &connector->edid_corrupt)) 1623 break; 1624 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1625 connector->null_edid_counter++; 1626 goto carp; 1627 } 1628 } 1629 if (i == 4) 1630 goto carp; 1631 1632 /* if there's no extensions, we're done */ 1633 valid_extensions = edid[0x7e]; 1634 if (valid_extensions == 0) 1635 return (struct edid *)edid; 1636 1637 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1638 if (!new) 1639 goto out; 1640 edid = new; 1641 1642 for (j = 1; j <= edid[0x7e]; j++) { 1643 u8 *block = edid + j * EDID_LENGTH; 1644 1645 for (i = 0; i < 4; i++) { 1646 if (get_edid_block(data, block, j, EDID_LENGTH)) 1647 goto out; 1648 if (drm_edid_block_valid(block, j, false, NULL)) 1649 break; 1650 } 1651 1652 if (i == 4) 1653 valid_extensions--; 1654 } 1655 1656 if (valid_extensions != edid[0x7e]) { 1657 u8 *base; 1658 1659 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1660 1661 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1662 edid[0x7e] = valid_extensions; 1663 1664 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1665 GFP_KERNEL); 1666 if (!new) 1667 goto out; 1668 1669 base = new; 1670 for (i = 0; i <= edid[0x7e]; i++) { 1671 u8 *block = edid + i * EDID_LENGTH; 1672 1673 if (!drm_edid_block_valid(block, i, false, NULL)) 1674 continue; 1675 1676 memcpy(base, block, EDID_LENGTH); 1677 base += EDID_LENGTH; 1678 } 1679 1680 kfree(edid); 1681 edid = new; 1682 } 1683 1684 return (struct edid *)edid; 1685 1686 carp: 1687 connector_bad_edid(connector, edid, 1); 1688 out: 1689 kfree(edid); 1690 return NULL; 1691 } 1692 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1693 1694 /** 1695 * drm_probe_ddc() - probe DDC presence 1696 * @adapter: I2C adapter to probe 1697 * 1698 * Return: True on success, false on failure. 1699 */ 1700 bool 1701 drm_probe_ddc(struct i2c_adapter *adapter) 1702 { 1703 unsigned char out; 1704 1705 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1706 } 1707 EXPORT_SYMBOL(drm_probe_ddc); 1708 1709 /** 1710 * drm_get_edid - get EDID data, if available 1711 * @connector: connector we're probing 1712 * @adapter: I2C adapter to use for DDC 1713 * 1714 * Poke the given I2C channel to grab EDID data if possible. If found, 1715 * attach it to the connector. 1716 * 1717 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1718 */ 1719 struct edid *drm_get_edid(struct drm_connector *connector, 1720 struct i2c_adapter *adapter) 1721 { 1722 struct edid *edid; 1723 1724 if (connector->force == DRM_FORCE_OFF) 1725 return NULL; 1726 1727 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1728 return NULL; 1729 1730 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1731 if (edid) 1732 drm_get_displayid(connector, edid); 1733 return edid; 1734 } 1735 EXPORT_SYMBOL(drm_get_edid); 1736 1737 /** 1738 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1739 * @connector: connector we're probing 1740 * @adapter: I2C adapter to use for DDC 1741 * 1742 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1743 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1744 * switch DDC to the GPU which is retrieving EDID. 1745 * 1746 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1747 */ 1748 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1749 struct i2c_adapter *adapter) 1750 { 1751 struct pci_dev *pdev = connector->dev->pdev; 1752 struct edid *edid; 1753 1754 vga_switcheroo_lock_ddc(pdev); 1755 edid = drm_get_edid(connector, adapter); 1756 vga_switcheroo_unlock_ddc(pdev); 1757 1758 return edid; 1759 } 1760 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1761 1762 /** 1763 * drm_edid_duplicate - duplicate an EDID and the extensions 1764 * @edid: EDID to duplicate 1765 * 1766 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1767 */ 1768 struct edid *drm_edid_duplicate(const struct edid *edid) 1769 { 1770 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1771 } 1772 EXPORT_SYMBOL(drm_edid_duplicate); 1773 1774 /*** EDID parsing ***/ 1775 1776 /** 1777 * edid_vendor - match a string against EDID's obfuscated vendor field 1778 * @edid: EDID to match 1779 * @vendor: vendor string 1780 * 1781 * Returns true if @vendor is in @edid, false otherwise 1782 */ 1783 static bool edid_vendor(const struct edid *edid, const char *vendor) 1784 { 1785 char edid_vendor[3]; 1786 1787 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1788 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1789 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1790 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1791 1792 return !strncmp(edid_vendor, vendor, 3); 1793 } 1794 1795 /** 1796 * edid_get_quirks - return quirk flags for a given EDID 1797 * @edid: EDID to process 1798 * 1799 * This tells subsequent routines what fixes they need to apply. 1800 */ 1801 static u32 edid_get_quirks(const struct edid *edid) 1802 { 1803 const struct edid_quirk *quirk; 1804 int i; 1805 1806 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1807 quirk = &edid_quirk_list[i]; 1808 1809 if (edid_vendor(edid, quirk->vendor) && 1810 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1811 return quirk->quirks; 1812 } 1813 1814 return 0; 1815 } 1816 1817 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1818 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1819 1820 /** 1821 * edid_fixup_preferred - set preferred modes based on quirk list 1822 * @connector: has mode list to fix up 1823 * @quirks: quirks list 1824 * 1825 * Walk the mode list for @connector, clearing the preferred status 1826 * on existing modes and setting it anew for the right mode ala @quirks. 1827 */ 1828 static void edid_fixup_preferred(struct drm_connector *connector, 1829 u32 quirks) 1830 { 1831 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1832 int target_refresh = 0; 1833 int cur_vrefresh, preferred_vrefresh; 1834 1835 if (list_empty(&connector->probed_modes)) 1836 return; 1837 1838 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1839 target_refresh = 60; 1840 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1841 target_refresh = 75; 1842 1843 preferred_mode = list_first_entry(&connector->probed_modes, 1844 struct drm_display_mode, head); 1845 1846 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1847 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1848 1849 if (cur_mode == preferred_mode) 1850 continue; 1851 1852 /* Largest mode is preferred */ 1853 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1854 preferred_mode = cur_mode; 1855 1856 cur_vrefresh = cur_mode->vrefresh ? 1857 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1858 preferred_vrefresh = preferred_mode->vrefresh ? 1859 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1860 /* At a given size, try to get closest to target refresh */ 1861 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1862 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1863 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1864 preferred_mode = cur_mode; 1865 } 1866 } 1867 1868 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1869 } 1870 1871 static bool 1872 mode_is_rb(const struct drm_display_mode *mode) 1873 { 1874 return (mode->htotal - mode->hdisplay == 160) && 1875 (mode->hsync_end - mode->hdisplay == 80) && 1876 (mode->hsync_end - mode->hsync_start == 32) && 1877 (mode->vsync_start - mode->vdisplay == 3); 1878 } 1879 1880 /* 1881 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1882 * @dev: Device to duplicate against 1883 * @hsize: Mode width 1884 * @vsize: Mode height 1885 * @fresh: Mode refresh rate 1886 * @rb: Mode reduced-blanking-ness 1887 * 1888 * Walk the DMT mode list looking for a match for the given parameters. 1889 * 1890 * Return: A newly allocated copy of the mode, or NULL if not found. 1891 */ 1892 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1893 int hsize, int vsize, int fresh, 1894 bool rb) 1895 { 1896 int i; 1897 1898 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1899 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1900 if (hsize != ptr->hdisplay) 1901 continue; 1902 if (vsize != ptr->vdisplay) 1903 continue; 1904 if (fresh != drm_mode_vrefresh(ptr)) 1905 continue; 1906 if (rb != mode_is_rb(ptr)) 1907 continue; 1908 1909 return drm_mode_duplicate(dev, ptr); 1910 } 1911 1912 return NULL; 1913 } 1914 EXPORT_SYMBOL(drm_mode_find_dmt); 1915 1916 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1917 1918 static void 1919 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1920 { 1921 int i, n = 0; 1922 u8 d = ext[0x02]; 1923 u8 *det_base = ext + d; 1924 1925 n = (127 - d) / 18; 1926 for (i = 0; i < n; i++) 1927 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1928 } 1929 1930 static void 1931 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1932 { 1933 unsigned int i, n = min((int)ext[0x02], 6); 1934 u8 *det_base = ext + 5; 1935 1936 if (ext[0x01] != 1) 1937 return; /* unknown version */ 1938 1939 for (i = 0; i < n; i++) 1940 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1941 } 1942 1943 static void 1944 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1945 { 1946 int i; 1947 struct edid *edid = (struct edid *)raw_edid; 1948 1949 if (edid == NULL) 1950 return; 1951 1952 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1953 cb(&(edid->detailed_timings[i]), closure); 1954 1955 for (i = 1; i <= raw_edid[0x7e]; i++) { 1956 u8 *ext = raw_edid + (i * EDID_LENGTH); 1957 switch (*ext) { 1958 case CEA_EXT: 1959 cea_for_each_detailed_block(ext, cb, closure); 1960 break; 1961 case VTB_EXT: 1962 vtb_for_each_detailed_block(ext, cb, closure); 1963 break; 1964 default: 1965 break; 1966 } 1967 } 1968 } 1969 1970 static void 1971 is_rb(struct detailed_timing *t, void *data) 1972 { 1973 u8 *r = (u8 *)t; 1974 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1975 if (r[15] & 0x10) 1976 *(bool *)data = true; 1977 } 1978 1979 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1980 static bool 1981 drm_monitor_supports_rb(struct edid *edid) 1982 { 1983 if (edid->revision >= 4) { 1984 bool ret = false; 1985 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1986 return ret; 1987 } 1988 1989 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1990 } 1991 1992 static void 1993 find_gtf2(struct detailed_timing *t, void *data) 1994 { 1995 u8 *r = (u8 *)t; 1996 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1997 *(u8 **)data = r; 1998 } 1999 2000 /* Secondary GTF curve kicks in above some break frequency */ 2001 static int 2002 drm_gtf2_hbreak(struct edid *edid) 2003 { 2004 u8 *r = NULL; 2005 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2006 return r ? (r[12] * 2) : 0; 2007 } 2008 2009 static int 2010 drm_gtf2_2c(struct edid *edid) 2011 { 2012 u8 *r = NULL; 2013 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2014 return r ? r[13] : 0; 2015 } 2016 2017 static int 2018 drm_gtf2_m(struct edid *edid) 2019 { 2020 u8 *r = NULL; 2021 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2022 return r ? (r[15] << 8) + r[14] : 0; 2023 } 2024 2025 static int 2026 drm_gtf2_k(struct edid *edid) 2027 { 2028 u8 *r = NULL; 2029 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2030 return r ? r[16] : 0; 2031 } 2032 2033 static int 2034 drm_gtf2_2j(struct edid *edid) 2035 { 2036 u8 *r = NULL; 2037 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2038 return r ? r[17] : 0; 2039 } 2040 2041 /** 2042 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2043 * @edid: EDID block to scan 2044 */ 2045 static int standard_timing_level(struct edid *edid) 2046 { 2047 if (edid->revision >= 2) { 2048 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2049 return LEVEL_CVT; 2050 if (drm_gtf2_hbreak(edid)) 2051 return LEVEL_GTF2; 2052 return LEVEL_GTF; 2053 } 2054 return LEVEL_DMT; 2055 } 2056 2057 /* 2058 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2059 * monitors fill with ascii space (0x20) instead. 2060 */ 2061 static int 2062 bad_std_timing(u8 a, u8 b) 2063 { 2064 return (a == 0x00 && b == 0x00) || 2065 (a == 0x01 && b == 0x01) || 2066 (a == 0x20 && b == 0x20); 2067 } 2068 2069 /** 2070 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2071 * @connector: connector of for the EDID block 2072 * @edid: EDID block to scan 2073 * @t: standard timing params 2074 * 2075 * Take the standard timing params (in this case width, aspect, and refresh) 2076 * and convert them into a real mode using CVT/GTF/DMT. 2077 */ 2078 static struct drm_display_mode * 2079 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2080 struct std_timing *t) 2081 { 2082 struct drm_device *dev = connector->dev; 2083 struct drm_display_mode *m, *mode = NULL; 2084 int hsize, vsize; 2085 int vrefresh_rate; 2086 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2087 >> EDID_TIMING_ASPECT_SHIFT; 2088 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2089 >> EDID_TIMING_VFREQ_SHIFT; 2090 int timing_level = standard_timing_level(edid); 2091 2092 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2093 return NULL; 2094 2095 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2096 hsize = t->hsize * 8 + 248; 2097 /* vrefresh_rate = vfreq + 60 */ 2098 vrefresh_rate = vfreq + 60; 2099 /* the vdisplay is calculated based on the aspect ratio */ 2100 if (aspect_ratio == 0) { 2101 if (edid->revision < 3) 2102 vsize = hsize; 2103 else 2104 vsize = (hsize * 10) / 16; 2105 } else if (aspect_ratio == 1) 2106 vsize = (hsize * 3) / 4; 2107 else if (aspect_ratio == 2) 2108 vsize = (hsize * 4) / 5; 2109 else 2110 vsize = (hsize * 9) / 16; 2111 2112 /* HDTV hack, part 1 */ 2113 if (vrefresh_rate == 60 && 2114 ((hsize == 1360 && vsize == 765) || 2115 (hsize == 1368 && vsize == 769))) { 2116 hsize = 1366; 2117 vsize = 768; 2118 } 2119 2120 /* 2121 * If this connector already has a mode for this size and refresh 2122 * rate (because it came from detailed or CVT info), use that 2123 * instead. This way we don't have to guess at interlace or 2124 * reduced blanking. 2125 */ 2126 list_for_each_entry(m, &connector->probed_modes, head) 2127 if (m->hdisplay == hsize && m->vdisplay == vsize && 2128 drm_mode_vrefresh(m) == vrefresh_rate) 2129 return NULL; 2130 2131 /* HDTV hack, part 2 */ 2132 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2133 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2134 false); 2135 if (!mode) 2136 return NULL; 2137 mode->hdisplay = 1366; 2138 mode->hsync_start = mode->hsync_start - 1; 2139 mode->hsync_end = mode->hsync_end - 1; 2140 return mode; 2141 } 2142 2143 /* check whether it can be found in default mode table */ 2144 if (drm_monitor_supports_rb(edid)) { 2145 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2146 true); 2147 if (mode) 2148 return mode; 2149 } 2150 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2151 if (mode) 2152 return mode; 2153 2154 /* okay, generate it */ 2155 switch (timing_level) { 2156 case LEVEL_DMT: 2157 break; 2158 case LEVEL_GTF: 2159 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2160 break; 2161 case LEVEL_GTF2: 2162 /* 2163 * This is potentially wrong if there's ever a monitor with 2164 * more than one ranges section, each claiming a different 2165 * secondary GTF curve. Please don't do that. 2166 */ 2167 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2168 if (!mode) 2169 return NULL; 2170 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2171 drm_mode_destroy(dev, mode); 2172 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2173 vrefresh_rate, 0, 0, 2174 drm_gtf2_m(edid), 2175 drm_gtf2_2c(edid), 2176 drm_gtf2_k(edid), 2177 drm_gtf2_2j(edid)); 2178 } 2179 break; 2180 case LEVEL_CVT: 2181 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2182 false); 2183 break; 2184 } 2185 return mode; 2186 } 2187 2188 /* 2189 * EDID is delightfully ambiguous about how interlaced modes are to be 2190 * encoded. Our internal representation is of frame height, but some 2191 * HDTV detailed timings are encoded as field height. 2192 * 2193 * The format list here is from CEA, in frame size. Technically we 2194 * should be checking refresh rate too. Whatever. 2195 */ 2196 static void 2197 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2198 struct detailed_pixel_timing *pt) 2199 { 2200 int i; 2201 static const struct { 2202 int w, h; 2203 } cea_interlaced[] = { 2204 { 1920, 1080 }, 2205 { 720, 480 }, 2206 { 1440, 480 }, 2207 { 2880, 480 }, 2208 { 720, 576 }, 2209 { 1440, 576 }, 2210 { 2880, 576 }, 2211 }; 2212 2213 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2214 return; 2215 2216 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2217 if ((mode->hdisplay == cea_interlaced[i].w) && 2218 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2219 mode->vdisplay *= 2; 2220 mode->vsync_start *= 2; 2221 mode->vsync_end *= 2; 2222 mode->vtotal *= 2; 2223 mode->vtotal |= 1; 2224 } 2225 } 2226 2227 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2228 } 2229 2230 /** 2231 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2232 * @dev: DRM device (needed to create new mode) 2233 * @edid: EDID block 2234 * @timing: EDID detailed timing info 2235 * @quirks: quirks to apply 2236 * 2237 * An EDID detailed timing block contains enough info for us to create and 2238 * return a new struct drm_display_mode. 2239 */ 2240 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2241 struct edid *edid, 2242 struct detailed_timing *timing, 2243 u32 quirks) 2244 { 2245 struct drm_display_mode *mode; 2246 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2247 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2248 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2249 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2250 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2251 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2252 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2253 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2254 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2255 2256 /* ignore tiny modes */ 2257 if (hactive < 64 || vactive < 64) 2258 return NULL; 2259 2260 if (pt->misc & DRM_EDID_PT_STEREO) { 2261 DRM_DEBUG_KMS("stereo mode not supported\n"); 2262 return NULL; 2263 } 2264 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2265 DRM_DEBUG_KMS("composite sync not supported\n"); 2266 } 2267 2268 /* it is incorrect if hsync/vsync width is zero */ 2269 if (!hsync_pulse_width || !vsync_pulse_width) { 2270 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2271 "Wrong Hsync/Vsync pulse width\n"); 2272 return NULL; 2273 } 2274 2275 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2276 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2277 if (!mode) 2278 return NULL; 2279 2280 goto set_size; 2281 } 2282 2283 mode = drm_mode_create(dev); 2284 if (!mode) 2285 return NULL; 2286 2287 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2288 timing->pixel_clock = cpu_to_le16(1088); 2289 2290 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2291 2292 mode->hdisplay = hactive; 2293 mode->hsync_start = mode->hdisplay + hsync_offset; 2294 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2295 mode->htotal = mode->hdisplay + hblank; 2296 2297 mode->vdisplay = vactive; 2298 mode->vsync_start = mode->vdisplay + vsync_offset; 2299 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2300 mode->vtotal = mode->vdisplay + vblank; 2301 2302 /* Some EDIDs have bogus h/vtotal values */ 2303 if (mode->hsync_end > mode->htotal) 2304 mode->htotal = mode->hsync_end + 1; 2305 if (mode->vsync_end > mode->vtotal) 2306 mode->vtotal = mode->vsync_end + 1; 2307 2308 drm_mode_do_interlace_quirk(mode, pt); 2309 2310 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2311 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2312 } 2313 2314 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2315 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2316 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2317 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2318 2319 set_size: 2320 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2321 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2322 2323 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2324 mode->width_mm *= 10; 2325 mode->height_mm *= 10; 2326 } 2327 2328 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2329 mode->width_mm = edid->width_cm * 10; 2330 mode->height_mm = edid->height_cm * 10; 2331 } 2332 2333 mode->type = DRM_MODE_TYPE_DRIVER; 2334 mode->vrefresh = drm_mode_vrefresh(mode); 2335 drm_mode_set_name(mode); 2336 2337 return mode; 2338 } 2339 2340 static bool 2341 mode_in_hsync_range(const struct drm_display_mode *mode, 2342 struct edid *edid, u8 *t) 2343 { 2344 int hsync, hmin, hmax; 2345 2346 hmin = t[7]; 2347 if (edid->revision >= 4) 2348 hmin += ((t[4] & 0x04) ? 255 : 0); 2349 hmax = t[8]; 2350 if (edid->revision >= 4) 2351 hmax += ((t[4] & 0x08) ? 255 : 0); 2352 hsync = drm_mode_hsync(mode); 2353 2354 return (hsync <= hmax && hsync >= hmin); 2355 } 2356 2357 static bool 2358 mode_in_vsync_range(const struct drm_display_mode *mode, 2359 struct edid *edid, u8 *t) 2360 { 2361 int vsync, vmin, vmax; 2362 2363 vmin = t[5]; 2364 if (edid->revision >= 4) 2365 vmin += ((t[4] & 0x01) ? 255 : 0); 2366 vmax = t[6]; 2367 if (edid->revision >= 4) 2368 vmax += ((t[4] & 0x02) ? 255 : 0); 2369 vsync = drm_mode_vrefresh(mode); 2370 2371 return (vsync <= vmax && vsync >= vmin); 2372 } 2373 2374 static u32 2375 range_pixel_clock(struct edid *edid, u8 *t) 2376 { 2377 /* unspecified */ 2378 if (t[9] == 0 || t[9] == 255) 2379 return 0; 2380 2381 /* 1.4 with CVT support gives us real precision, yay */ 2382 if (edid->revision >= 4 && t[10] == 0x04) 2383 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2384 2385 /* 1.3 is pathetic, so fuzz up a bit */ 2386 return t[9] * 10000 + 5001; 2387 } 2388 2389 static bool 2390 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2391 struct detailed_timing *timing) 2392 { 2393 u32 max_clock; 2394 u8 *t = (u8 *)timing; 2395 2396 if (!mode_in_hsync_range(mode, edid, t)) 2397 return false; 2398 2399 if (!mode_in_vsync_range(mode, edid, t)) 2400 return false; 2401 2402 if ((max_clock = range_pixel_clock(edid, t))) 2403 if (mode->clock > max_clock) 2404 return false; 2405 2406 /* 1.4 max horizontal check */ 2407 if (edid->revision >= 4 && t[10] == 0x04) 2408 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2409 return false; 2410 2411 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2412 return false; 2413 2414 return true; 2415 } 2416 2417 static bool valid_inferred_mode(const struct drm_connector *connector, 2418 const struct drm_display_mode *mode) 2419 { 2420 const struct drm_display_mode *m; 2421 bool ok = false; 2422 2423 list_for_each_entry(m, &connector->probed_modes, head) { 2424 if (mode->hdisplay == m->hdisplay && 2425 mode->vdisplay == m->vdisplay && 2426 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2427 return false; /* duplicated */ 2428 if (mode->hdisplay <= m->hdisplay && 2429 mode->vdisplay <= m->vdisplay) 2430 ok = true; 2431 } 2432 return ok; 2433 } 2434 2435 static int 2436 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2437 struct detailed_timing *timing) 2438 { 2439 int i, modes = 0; 2440 struct drm_display_mode *newmode; 2441 struct drm_device *dev = connector->dev; 2442 2443 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2444 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2445 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2446 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2447 if (newmode) { 2448 drm_mode_probed_add(connector, newmode); 2449 modes++; 2450 } 2451 } 2452 } 2453 2454 return modes; 2455 } 2456 2457 /* fix up 1366x768 mode from 1368x768; 2458 * GFT/CVT can't express 1366 width which isn't dividable by 8 2459 */ 2460 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2461 { 2462 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2463 mode->hdisplay = 1366; 2464 mode->hsync_start--; 2465 mode->hsync_end--; 2466 drm_mode_set_name(mode); 2467 } 2468 } 2469 2470 static int 2471 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2472 struct detailed_timing *timing) 2473 { 2474 int i, modes = 0; 2475 struct drm_display_mode *newmode; 2476 struct drm_device *dev = connector->dev; 2477 2478 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2479 const struct minimode *m = &extra_modes[i]; 2480 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2481 if (!newmode) 2482 return modes; 2483 2484 drm_mode_fixup_1366x768(newmode); 2485 if (!mode_in_range(newmode, edid, timing) || 2486 !valid_inferred_mode(connector, newmode)) { 2487 drm_mode_destroy(dev, newmode); 2488 continue; 2489 } 2490 2491 drm_mode_probed_add(connector, newmode); 2492 modes++; 2493 } 2494 2495 return modes; 2496 } 2497 2498 static int 2499 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2500 struct detailed_timing *timing) 2501 { 2502 int i, modes = 0; 2503 struct drm_display_mode *newmode; 2504 struct drm_device *dev = connector->dev; 2505 bool rb = drm_monitor_supports_rb(edid); 2506 2507 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2508 const struct minimode *m = &extra_modes[i]; 2509 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2510 if (!newmode) 2511 return modes; 2512 2513 drm_mode_fixup_1366x768(newmode); 2514 if (!mode_in_range(newmode, edid, timing) || 2515 !valid_inferred_mode(connector, newmode)) { 2516 drm_mode_destroy(dev, newmode); 2517 continue; 2518 } 2519 2520 drm_mode_probed_add(connector, newmode); 2521 modes++; 2522 } 2523 2524 return modes; 2525 } 2526 2527 static void 2528 do_inferred_modes(struct detailed_timing *timing, void *c) 2529 { 2530 struct detailed_mode_closure *closure = c; 2531 struct detailed_non_pixel *data = &timing->data.other_data; 2532 struct detailed_data_monitor_range *range = &data->data.range; 2533 2534 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2535 return; 2536 2537 closure->modes += drm_dmt_modes_for_range(closure->connector, 2538 closure->edid, 2539 timing); 2540 2541 if (!version_greater(closure->edid, 1, 1)) 2542 return; /* GTF not defined yet */ 2543 2544 switch (range->flags) { 2545 case 0x02: /* secondary gtf, XXX could do more */ 2546 case 0x00: /* default gtf */ 2547 closure->modes += drm_gtf_modes_for_range(closure->connector, 2548 closure->edid, 2549 timing); 2550 break; 2551 case 0x04: /* cvt, only in 1.4+ */ 2552 if (!version_greater(closure->edid, 1, 3)) 2553 break; 2554 2555 closure->modes += drm_cvt_modes_for_range(closure->connector, 2556 closure->edid, 2557 timing); 2558 break; 2559 case 0x01: /* just the ranges, no formula */ 2560 default: 2561 break; 2562 } 2563 } 2564 2565 static int 2566 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2567 { 2568 struct detailed_mode_closure closure = { 2569 .connector = connector, 2570 .edid = edid, 2571 }; 2572 2573 if (version_greater(edid, 1, 0)) 2574 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2575 &closure); 2576 2577 return closure.modes; 2578 } 2579 2580 static int 2581 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2582 { 2583 int i, j, m, modes = 0; 2584 struct drm_display_mode *mode; 2585 u8 *est = ((u8 *)timing) + 6; 2586 2587 for (i = 0; i < 6; i++) { 2588 for (j = 7; j >= 0; j--) { 2589 m = (i * 8) + (7 - j); 2590 if (m >= ARRAY_SIZE(est3_modes)) 2591 break; 2592 if (est[i] & (1 << j)) { 2593 mode = drm_mode_find_dmt(connector->dev, 2594 est3_modes[m].w, 2595 est3_modes[m].h, 2596 est3_modes[m].r, 2597 est3_modes[m].rb); 2598 if (mode) { 2599 drm_mode_probed_add(connector, mode); 2600 modes++; 2601 } 2602 } 2603 } 2604 } 2605 2606 return modes; 2607 } 2608 2609 static void 2610 do_established_modes(struct detailed_timing *timing, void *c) 2611 { 2612 struct detailed_mode_closure *closure = c; 2613 struct detailed_non_pixel *data = &timing->data.other_data; 2614 2615 if (data->type == EDID_DETAIL_EST_TIMINGS) 2616 closure->modes += drm_est3_modes(closure->connector, timing); 2617 } 2618 2619 /** 2620 * add_established_modes - get est. modes from EDID and add them 2621 * @connector: connector to add mode(s) to 2622 * @edid: EDID block to scan 2623 * 2624 * Each EDID block contains a bitmap of the supported "established modes" list 2625 * (defined above). Tease them out and add them to the global modes list. 2626 */ 2627 static int 2628 add_established_modes(struct drm_connector *connector, struct edid *edid) 2629 { 2630 struct drm_device *dev = connector->dev; 2631 unsigned long est_bits = edid->established_timings.t1 | 2632 (edid->established_timings.t2 << 8) | 2633 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2634 int i, modes = 0; 2635 struct detailed_mode_closure closure = { 2636 .connector = connector, 2637 .edid = edid, 2638 }; 2639 2640 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2641 if (est_bits & (1<<i)) { 2642 struct drm_display_mode *newmode; 2643 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2644 if (newmode) { 2645 drm_mode_probed_add(connector, newmode); 2646 modes++; 2647 } 2648 } 2649 } 2650 2651 if (version_greater(edid, 1, 0)) 2652 drm_for_each_detailed_block((u8 *)edid, 2653 do_established_modes, &closure); 2654 2655 return modes + closure.modes; 2656 } 2657 2658 static void 2659 do_standard_modes(struct detailed_timing *timing, void *c) 2660 { 2661 struct detailed_mode_closure *closure = c; 2662 struct detailed_non_pixel *data = &timing->data.other_data; 2663 struct drm_connector *connector = closure->connector; 2664 struct edid *edid = closure->edid; 2665 2666 if (data->type == EDID_DETAIL_STD_MODES) { 2667 int i; 2668 for (i = 0; i < 6; i++) { 2669 struct std_timing *std; 2670 struct drm_display_mode *newmode; 2671 2672 std = &data->data.timings[i]; 2673 newmode = drm_mode_std(connector, edid, std); 2674 if (newmode) { 2675 drm_mode_probed_add(connector, newmode); 2676 closure->modes++; 2677 } 2678 } 2679 } 2680 } 2681 2682 /** 2683 * add_standard_modes - get std. modes from EDID and add them 2684 * @connector: connector to add mode(s) to 2685 * @edid: EDID block to scan 2686 * 2687 * Standard modes can be calculated using the appropriate standard (DMT, 2688 * GTF or CVT. Grab them from @edid and add them to the list. 2689 */ 2690 static int 2691 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2692 { 2693 int i, modes = 0; 2694 struct detailed_mode_closure closure = { 2695 .connector = connector, 2696 .edid = edid, 2697 }; 2698 2699 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2700 struct drm_display_mode *newmode; 2701 2702 newmode = drm_mode_std(connector, edid, 2703 &edid->standard_timings[i]); 2704 if (newmode) { 2705 drm_mode_probed_add(connector, newmode); 2706 modes++; 2707 } 2708 } 2709 2710 if (version_greater(edid, 1, 0)) 2711 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2712 &closure); 2713 2714 /* XXX should also look for standard codes in VTB blocks */ 2715 2716 return modes + closure.modes; 2717 } 2718 2719 static int drm_cvt_modes(struct drm_connector *connector, 2720 struct detailed_timing *timing) 2721 { 2722 int i, j, modes = 0; 2723 struct drm_display_mode *newmode; 2724 struct drm_device *dev = connector->dev; 2725 struct cvt_timing *cvt; 2726 const int rates[] = { 60, 85, 75, 60, 50 }; 2727 const u8 empty[3] = { 0, 0, 0 }; 2728 2729 for (i = 0; i < 4; i++) { 2730 int uninitialized_var(width), height; 2731 cvt = &(timing->data.other_data.data.cvt[i]); 2732 2733 if (!memcmp(cvt->code, empty, 3)) 2734 continue; 2735 2736 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2737 switch (cvt->code[1] & 0x0c) { 2738 case 0x00: 2739 width = height * 4 / 3; 2740 break; 2741 case 0x04: 2742 width = height * 16 / 9; 2743 break; 2744 case 0x08: 2745 width = height * 16 / 10; 2746 break; 2747 case 0x0c: 2748 width = height * 15 / 9; 2749 break; 2750 } 2751 2752 for (j = 1; j < 5; j++) { 2753 if (cvt->code[2] & (1 << j)) { 2754 newmode = drm_cvt_mode(dev, width, height, 2755 rates[j], j == 0, 2756 false, false); 2757 if (newmode) { 2758 drm_mode_probed_add(connector, newmode); 2759 modes++; 2760 } 2761 } 2762 } 2763 } 2764 2765 return modes; 2766 } 2767 2768 static void 2769 do_cvt_mode(struct detailed_timing *timing, void *c) 2770 { 2771 struct detailed_mode_closure *closure = c; 2772 struct detailed_non_pixel *data = &timing->data.other_data; 2773 2774 if (data->type == EDID_DETAIL_CVT_3BYTE) 2775 closure->modes += drm_cvt_modes(closure->connector, timing); 2776 } 2777 2778 static int 2779 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2780 { 2781 struct detailed_mode_closure closure = { 2782 .connector = connector, 2783 .edid = edid, 2784 }; 2785 2786 if (version_greater(edid, 1, 2)) 2787 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2788 2789 /* XXX should also look for CVT codes in VTB blocks */ 2790 2791 return closure.modes; 2792 } 2793 2794 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2795 2796 static void 2797 do_detailed_mode(struct detailed_timing *timing, void *c) 2798 { 2799 struct detailed_mode_closure *closure = c; 2800 struct drm_display_mode *newmode; 2801 2802 if (timing->pixel_clock) { 2803 newmode = drm_mode_detailed(closure->connector->dev, 2804 closure->edid, timing, 2805 closure->quirks); 2806 if (!newmode) 2807 return; 2808 2809 if (closure->preferred) 2810 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2811 2812 /* 2813 * Detailed modes are limited to 10kHz pixel clock resolution, 2814 * so fix up anything that looks like CEA/HDMI mode, but the clock 2815 * is just slightly off. 2816 */ 2817 fixup_detailed_cea_mode_clock(newmode); 2818 2819 drm_mode_probed_add(closure->connector, newmode); 2820 closure->modes++; 2821 closure->preferred = false; 2822 } 2823 } 2824 2825 /* 2826 * add_detailed_modes - Add modes from detailed timings 2827 * @connector: attached connector 2828 * @edid: EDID block to scan 2829 * @quirks: quirks to apply 2830 */ 2831 static int 2832 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2833 u32 quirks) 2834 { 2835 struct detailed_mode_closure closure = { 2836 .connector = connector, 2837 .edid = edid, 2838 .preferred = true, 2839 .quirks = quirks, 2840 }; 2841 2842 if (closure.preferred && !version_greater(edid, 1, 3)) 2843 closure.preferred = 2844 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2845 2846 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2847 2848 return closure.modes; 2849 } 2850 2851 #define AUDIO_BLOCK 0x01 2852 #define VIDEO_BLOCK 0x02 2853 #define VENDOR_BLOCK 0x03 2854 #define SPEAKER_BLOCK 0x04 2855 #define HDR_STATIC_METADATA_BLOCK 0x6 2856 #define USE_EXTENDED_TAG 0x07 2857 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2858 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2859 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2860 #define EDID_BASIC_AUDIO (1 << 6) 2861 #define EDID_CEA_YCRCB444 (1 << 5) 2862 #define EDID_CEA_YCRCB422 (1 << 4) 2863 #define EDID_CEA_VCDB_QS (1 << 6) 2864 2865 /* 2866 * Search EDID for CEA extension block. 2867 */ 2868 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2869 { 2870 u8 *edid_ext = NULL; 2871 int i; 2872 2873 /* No EDID or EDID extensions */ 2874 if (edid == NULL || edid->extensions == 0) 2875 return NULL; 2876 2877 /* Find CEA extension */ 2878 for (i = 0; i < edid->extensions; i++) { 2879 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2880 if (edid_ext[0] == ext_id) 2881 break; 2882 } 2883 2884 if (i == edid->extensions) 2885 return NULL; 2886 2887 return edid_ext; 2888 } 2889 2890 static u8 *drm_find_cea_extension(const struct edid *edid) 2891 { 2892 return drm_find_edid_extension(edid, CEA_EXT); 2893 } 2894 2895 static u8 *drm_find_displayid_extension(const struct edid *edid) 2896 { 2897 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2898 } 2899 2900 /* 2901 * Calculate the alternate clock for the CEA mode 2902 * (60Hz vs. 59.94Hz etc.) 2903 */ 2904 static unsigned int 2905 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2906 { 2907 unsigned int clock = cea_mode->clock; 2908 2909 if (cea_mode->vrefresh % 6 != 0) 2910 return clock; 2911 2912 /* 2913 * edid_cea_modes contains the 59.94Hz 2914 * variant for 240 and 480 line modes, 2915 * and the 60Hz variant otherwise. 2916 */ 2917 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2918 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2919 else 2920 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2921 2922 return clock; 2923 } 2924 2925 static bool 2926 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2927 { 2928 /* 2929 * For certain VICs the spec allows the vertical 2930 * front porch to vary by one or two lines. 2931 * 2932 * cea_modes[] stores the variant with the shortest 2933 * vertical front porch. We can adjust the mode to 2934 * get the other variants by simply increasing the 2935 * vertical front porch length. 2936 */ 2937 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2938 edid_cea_modes[9].vtotal != 262 || 2939 edid_cea_modes[12].vtotal != 262 || 2940 edid_cea_modes[13].vtotal != 262 || 2941 edid_cea_modes[23].vtotal != 312 || 2942 edid_cea_modes[24].vtotal != 312 || 2943 edid_cea_modes[27].vtotal != 312 || 2944 edid_cea_modes[28].vtotal != 312); 2945 2946 if (((vic == 8 || vic == 9 || 2947 vic == 12 || vic == 13) && mode->vtotal < 263) || 2948 ((vic == 23 || vic == 24 || 2949 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2950 mode->vsync_start++; 2951 mode->vsync_end++; 2952 mode->vtotal++; 2953 2954 return true; 2955 } 2956 2957 return false; 2958 } 2959 2960 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2961 unsigned int clock_tolerance) 2962 { 2963 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2964 u8 vic; 2965 2966 if (!to_match->clock) 2967 return 0; 2968 2969 if (to_match->picture_aspect_ratio) 2970 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2971 2972 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2973 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2974 unsigned int clock1, clock2; 2975 2976 /* Check both 60Hz and 59.94Hz */ 2977 clock1 = cea_mode.clock; 2978 clock2 = cea_mode_alternate_clock(&cea_mode); 2979 2980 if (abs(to_match->clock - clock1) > clock_tolerance && 2981 abs(to_match->clock - clock2) > clock_tolerance) 2982 continue; 2983 2984 do { 2985 if (drm_mode_match(to_match, &cea_mode, match_flags)) 2986 return vic; 2987 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2988 } 2989 2990 return 0; 2991 } 2992 2993 /** 2994 * drm_match_cea_mode - look for a CEA mode matching given mode 2995 * @to_match: display mode 2996 * 2997 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2998 * mode. 2999 */ 3000 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3001 { 3002 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3003 u8 vic; 3004 3005 if (!to_match->clock) 3006 return 0; 3007 3008 if (to_match->picture_aspect_ratio) 3009 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3010 3011 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3012 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 3013 unsigned int clock1, clock2; 3014 3015 /* Check both 60Hz and 59.94Hz */ 3016 clock1 = cea_mode.clock; 3017 clock2 = cea_mode_alternate_clock(&cea_mode); 3018 3019 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3020 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3021 continue; 3022 3023 do { 3024 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3025 return vic; 3026 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3027 } 3028 3029 return 0; 3030 } 3031 EXPORT_SYMBOL(drm_match_cea_mode); 3032 3033 static bool drm_valid_cea_vic(u8 vic) 3034 { 3035 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3036 } 3037 3038 /** 3039 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3040 * the input VIC from the CEA mode list 3041 * @video_code: ID given to each of the CEA modes 3042 * 3043 * Returns picture aspect ratio 3044 */ 3045 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3046 { 3047 return edid_cea_modes[video_code].picture_aspect_ratio; 3048 } 3049 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3050 3051 /* 3052 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3053 * specific block). 3054 * 3055 * It's almost like cea_mode_alternate_clock(), we just need to add an 3056 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3057 * one. 3058 */ 3059 static unsigned int 3060 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3061 { 3062 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3063 return hdmi_mode->clock; 3064 3065 return cea_mode_alternate_clock(hdmi_mode); 3066 } 3067 3068 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3069 unsigned int clock_tolerance) 3070 { 3071 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3072 u8 vic; 3073 3074 if (!to_match->clock) 3075 return 0; 3076 3077 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3078 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3079 unsigned int clock1, clock2; 3080 3081 /* Make sure to also match alternate clocks */ 3082 clock1 = hdmi_mode->clock; 3083 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3084 3085 if (abs(to_match->clock - clock1) > clock_tolerance && 3086 abs(to_match->clock - clock2) > clock_tolerance) 3087 continue; 3088 3089 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3090 return vic; 3091 } 3092 3093 return 0; 3094 } 3095 3096 /* 3097 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3098 * @to_match: display mode 3099 * 3100 * An HDMI mode is one defined in the HDMI vendor specific block. 3101 * 3102 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3103 */ 3104 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3105 { 3106 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3107 u8 vic; 3108 3109 if (!to_match->clock) 3110 return 0; 3111 3112 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3113 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3114 unsigned int clock1, clock2; 3115 3116 /* Make sure to also match alternate clocks */ 3117 clock1 = hdmi_mode->clock; 3118 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3119 3120 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3121 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3122 drm_mode_match(to_match, hdmi_mode, match_flags)) 3123 return vic; 3124 } 3125 return 0; 3126 } 3127 3128 static bool drm_valid_hdmi_vic(u8 vic) 3129 { 3130 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3131 } 3132 3133 static int 3134 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3135 { 3136 struct drm_device *dev = connector->dev; 3137 struct drm_display_mode *mode, *tmp; 3138 LIST_HEAD(list); 3139 int modes = 0; 3140 3141 /* Don't add CEA modes if the CEA extension block is missing */ 3142 if (!drm_find_cea_extension(edid)) 3143 return 0; 3144 3145 /* 3146 * Go through all probed modes and create a new mode 3147 * with the alternate clock for certain CEA modes. 3148 */ 3149 list_for_each_entry(mode, &connector->probed_modes, head) { 3150 const struct drm_display_mode *cea_mode = NULL; 3151 struct drm_display_mode *newmode; 3152 u8 vic = drm_match_cea_mode(mode); 3153 unsigned int clock1, clock2; 3154 3155 if (drm_valid_cea_vic(vic)) { 3156 cea_mode = &edid_cea_modes[vic]; 3157 clock2 = cea_mode_alternate_clock(cea_mode); 3158 } else { 3159 vic = drm_match_hdmi_mode(mode); 3160 if (drm_valid_hdmi_vic(vic)) { 3161 cea_mode = &edid_4k_modes[vic]; 3162 clock2 = hdmi_mode_alternate_clock(cea_mode); 3163 } 3164 } 3165 3166 if (!cea_mode) 3167 continue; 3168 3169 clock1 = cea_mode->clock; 3170 3171 if (clock1 == clock2) 3172 continue; 3173 3174 if (mode->clock != clock1 && mode->clock != clock2) 3175 continue; 3176 3177 newmode = drm_mode_duplicate(dev, cea_mode); 3178 if (!newmode) 3179 continue; 3180 3181 /* Carry over the stereo flags */ 3182 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3183 3184 /* 3185 * The current mode could be either variant. Make 3186 * sure to pick the "other" clock for the new mode. 3187 */ 3188 if (mode->clock != clock1) 3189 newmode->clock = clock1; 3190 else 3191 newmode->clock = clock2; 3192 3193 list_add_tail(&newmode->head, &list); 3194 } 3195 3196 list_for_each_entry_safe(mode, tmp, &list, head) { 3197 list_del(&mode->head); 3198 drm_mode_probed_add(connector, mode); 3199 modes++; 3200 } 3201 3202 return modes; 3203 } 3204 3205 static u8 svd_to_vic(u8 svd) 3206 { 3207 /* 0-6 bit vic, 7th bit native mode indicator */ 3208 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3209 return svd & 127; 3210 3211 return svd; 3212 } 3213 3214 static struct drm_display_mode * 3215 drm_display_mode_from_vic_index(struct drm_connector *connector, 3216 const u8 *video_db, u8 video_len, 3217 u8 video_index) 3218 { 3219 struct drm_device *dev = connector->dev; 3220 struct drm_display_mode *newmode; 3221 u8 vic; 3222 3223 if (video_db == NULL || video_index >= video_len) 3224 return NULL; 3225 3226 /* CEA modes are numbered 1..127 */ 3227 vic = svd_to_vic(video_db[video_index]); 3228 if (!drm_valid_cea_vic(vic)) 3229 return NULL; 3230 3231 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3232 if (!newmode) 3233 return NULL; 3234 3235 newmode->vrefresh = 0; 3236 3237 return newmode; 3238 } 3239 3240 /* 3241 * do_y420vdb_modes - Parse YCBCR 420 only modes 3242 * @connector: connector corresponding to the HDMI sink 3243 * @svds: start of the data block of CEA YCBCR 420 VDB 3244 * @len: length of the CEA YCBCR 420 VDB 3245 * 3246 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3247 * which contains modes which can be supported in YCBCR 420 3248 * output format only. 3249 */ 3250 static int do_y420vdb_modes(struct drm_connector *connector, 3251 const u8 *svds, u8 svds_len) 3252 { 3253 int modes = 0, i; 3254 struct drm_device *dev = connector->dev; 3255 struct drm_display_info *info = &connector->display_info; 3256 struct drm_hdmi_info *hdmi = &info->hdmi; 3257 3258 for (i = 0; i < svds_len; i++) { 3259 u8 vic = svd_to_vic(svds[i]); 3260 struct drm_display_mode *newmode; 3261 3262 if (!drm_valid_cea_vic(vic)) 3263 continue; 3264 3265 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3266 if (!newmode) 3267 break; 3268 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3269 drm_mode_probed_add(connector, newmode); 3270 modes++; 3271 } 3272 3273 if (modes > 0) 3274 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3275 return modes; 3276 } 3277 3278 /* 3279 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3280 * @connector: connector corresponding to the HDMI sink 3281 * @vic: CEA vic for the video mode to be added in the map 3282 * 3283 * Makes an entry for a videomode in the YCBCR 420 bitmap 3284 */ 3285 static void 3286 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3287 { 3288 u8 vic = svd_to_vic(svd); 3289 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3290 3291 if (!drm_valid_cea_vic(vic)) 3292 return; 3293 3294 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3295 } 3296 3297 static int 3298 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3299 { 3300 int i, modes = 0; 3301 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3302 3303 for (i = 0; i < len; i++) { 3304 struct drm_display_mode *mode; 3305 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3306 if (mode) { 3307 /* 3308 * YCBCR420 capability block contains a bitmap which 3309 * gives the index of CEA modes from CEA VDB, which 3310 * can support YCBCR 420 sampling output also (apart 3311 * from RGB/YCBCR444 etc). 3312 * For example, if the bit 0 in bitmap is set, 3313 * first mode in VDB can support YCBCR420 output too. 3314 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3315 */ 3316 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3317 drm_add_cmdb_modes(connector, db[i]); 3318 3319 drm_mode_probed_add(connector, mode); 3320 modes++; 3321 } 3322 } 3323 3324 return modes; 3325 } 3326 3327 struct stereo_mandatory_mode { 3328 int width, height, vrefresh; 3329 unsigned int flags; 3330 }; 3331 3332 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3333 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3334 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3335 { 1920, 1080, 50, 3336 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3337 { 1920, 1080, 60, 3338 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3339 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3340 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3341 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3342 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3343 }; 3344 3345 static bool 3346 stereo_match_mandatory(const struct drm_display_mode *mode, 3347 const struct stereo_mandatory_mode *stereo_mode) 3348 { 3349 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3350 3351 return mode->hdisplay == stereo_mode->width && 3352 mode->vdisplay == stereo_mode->height && 3353 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3354 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3355 } 3356 3357 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3358 { 3359 struct drm_device *dev = connector->dev; 3360 const struct drm_display_mode *mode; 3361 struct list_head stereo_modes; 3362 int modes = 0, i; 3363 3364 INIT_LIST_HEAD(&stereo_modes); 3365 3366 list_for_each_entry(mode, &connector->probed_modes, head) { 3367 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3368 const struct stereo_mandatory_mode *mandatory; 3369 struct drm_display_mode *new_mode; 3370 3371 if (!stereo_match_mandatory(mode, 3372 &stereo_mandatory_modes[i])) 3373 continue; 3374 3375 mandatory = &stereo_mandatory_modes[i]; 3376 new_mode = drm_mode_duplicate(dev, mode); 3377 if (!new_mode) 3378 continue; 3379 3380 new_mode->flags |= mandatory->flags; 3381 list_add_tail(&new_mode->head, &stereo_modes); 3382 modes++; 3383 } 3384 } 3385 3386 list_splice_tail(&stereo_modes, &connector->probed_modes); 3387 3388 return modes; 3389 } 3390 3391 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3392 { 3393 struct drm_device *dev = connector->dev; 3394 struct drm_display_mode *newmode; 3395 3396 if (!drm_valid_hdmi_vic(vic)) { 3397 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3398 return 0; 3399 } 3400 3401 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3402 if (!newmode) 3403 return 0; 3404 3405 drm_mode_probed_add(connector, newmode); 3406 3407 return 1; 3408 } 3409 3410 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3411 const u8 *video_db, u8 video_len, u8 video_index) 3412 { 3413 struct drm_display_mode *newmode; 3414 int modes = 0; 3415 3416 if (structure & (1 << 0)) { 3417 newmode = drm_display_mode_from_vic_index(connector, video_db, 3418 video_len, 3419 video_index); 3420 if (newmode) { 3421 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3422 drm_mode_probed_add(connector, newmode); 3423 modes++; 3424 } 3425 } 3426 if (structure & (1 << 6)) { 3427 newmode = drm_display_mode_from_vic_index(connector, video_db, 3428 video_len, 3429 video_index); 3430 if (newmode) { 3431 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3432 drm_mode_probed_add(connector, newmode); 3433 modes++; 3434 } 3435 } 3436 if (structure & (1 << 8)) { 3437 newmode = drm_display_mode_from_vic_index(connector, video_db, 3438 video_len, 3439 video_index); 3440 if (newmode) { 3441 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3442 drm_mode_probed_add(connector, newmode); 3443 modes++; 3444 } 3445 } 3446 3447 return modes; 3448 } 3449 3450 /* 3451 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3452 * @connector: connector corresponding to the HDMI sink 3453 * @db: start of the CEA vendor specific block 3454 * @len: length of the CEA block payload, ie. one can access up to db[len] 3455 * 3456 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3457 * also adds the stereo 3d modes when applicable. 3458 */ 3459 static int 3460 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3461 const u8 *video_db, u8 video_len) 3462 { 3463 struct drm_display_info *info = &connector->display_info; 3464 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3465 u8 vic_len, hdmi_3d_len = 0; 3466 u16 mask; 3467 u16 structure_all; 3468 3469 if (len < 8) 3470 goto out; 3471 3472 /* no HDMI_Video_Present */ 3473 if (!(db[8] & (1 << 5))) 3474 goto out; 3475 3476 /* Latency_Fields_Present */ 3477 if (db[8] & (1 << 7)) 3478 offset += 2; 3479 3480 /* I_Latency_Fields_Present */ 3481 if (db[8] & (1 << 6)) 3482 offset += 2; 3483 3484 /* the declared length is not long enough for the 2 first bytes 3485 * of additional video format capabilities */ 3486 if (len < (8 + offset + 2)) 3487 goto out; 3488 3489 /* 3D_Present */ 3490 offset++; 3491 if (db[8 + offset] & (1 << 7)) { 3492 modes += add_hdmi_mandatory_stereo_modes(connector); 3493 3494 /* 3D_Multi_present */ 3495 multi_present = (db[8 + offset] & 0x60) >> 5; 3496 } 3497 3498 offset++; 3499 vic_len = db[8 + offset] >> 5; 3500 hdmi_3d_len = db[8 + offset] & 0x1f; 3501 3502 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3503 u8 vic; 3504 3505 vic = db[9 + offset + i]; 3506 modes += add_hdmi_mode(connector, vic); 3507 } 3508 offset += 1 + vic_len; 3509 3510 if (multi_present == 1) 3511 multi_len = 2; 3512 else if (multi_present == 2) 3513 multi_len = 4; 3514 else 3515 multi_len = 0; 3516 3517 if (len < (8 + offset + hdmi_3d_len - 1)) 3518 goto out; 3519 3520 if (hdmi_3d_len < multi_len) 3521 goto out; 3522 3523 if (multi_present == 1 || multi_present == 2) { 3524 /* 3D_Structure_ALL */ 3525 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3526 3527 /* check if 3D_MASK is present */ 3528 if (multi_present == 2) 3529 mask = (db[10 + offset] << 8) | db[11 + offset]; 3530 else 3531 mask = 0xffff; 3532 3533 for (i = 0; i < 16; i++) { 3534 if (mask & (1 << i)) 3535 modes += add_3d_struct_modes(connector, 3536 structure_all, 3537 video_db, 3538 video_len, i); 3539 } 3540 } 3541 3542 offset += multi_len; 3543 3544 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3545 int vic_index; 3546 struct drm_display_mode *newmode = NULL; 3547 unsigned int newflag = 0; 3548 bool detail_present; 3549 3550 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3551 3552 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3553 break; 3554 3555 /* 2D_VIC_order_X */ 3556 vic_index = db[8 + offset + i] >> 4; 3557 3558 /* 3D_Structure_X */ 3559 switch (db[8 + offset + i] & 0x0f) { 3560 case 0: 3561 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3562 break; 3563 case 6: 3564 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3565 break; 3566 case 8: 3567 /* 3D_Detail_X */ 3568 if ((db[9 + offset + i] >> 4) == 1) 3569 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3570 break; 3571 } 3572 3573 if (newflag != 0) { 3574 newmode = drm_display_mode_from_vic_index(connector, 3575 video_db, 3576 video_len, 3577 vic_index); 3578 3579 if (newmode) { 3580 newmode->flags |= newflag; 3581 drm_mode_probed_add(connector, newmode); 3582 modes++; 3583 } 3584 } 3585 3586 if (detail_present) 3587 i++; 3588 } 3589 3590 out: 3591 if (modes > 0) 3592 info->has_hdmi_infoframe = true; 3593 return modes; 3594 } 3595 3596 static int 3597 cea_db_payload_len(const u8 *db) 3598 { 3599 return db[0] & 0x1f; 3600 } 3601 3602 static int 3603 cea_db_extended_tag(const u8 *db) 3604 { 3605 return db[1]; 3606 } 3607 3608 static int 3609 cea_db_tag(const u8 *db) 3610 { 3611 return db[0] >> 5; 3612 } 3613 3614 static int 3615 cea_revision(const u8 *cea) 3616 { 3617 return cea[1]; 3618 } 3619 3620 static int 3621 cea_db_offsets(const u8 *cea, int *start, int *end) 3622 { 3623 /* Data block offset in CEA extension block */ 3624 *start = 4; 3625 *end = cea[2]; 3626 if (*end == 0) 3627 *end = 127; 3628 if (*end < 4 || *end > 127) 3629 return -ERANGE; 3630 return 0; 3631 } 3632 3633 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3634 { 3635 int hdmi_id; 3636 3637 if (cea_db_tag(db) != VENDOR_BLOCK) 3638 return false; 3639 3640 if (cea_db_payload_len(db) < 5) 3641 return false; 3642 3643 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3644 3645 return hdmi_id == HDMI_IEEE_OUI; 3646 } 3647 3648 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3649 { 3650 unsigned int oui; 3651 3652 if (cea_db_tag(db) != VENDOR_BLOCK) 3653 return false; 3654 3655 if (cea_db_payload_len(db) < 7) 3656 return false; 3657 3658 oui = db[3] << 16 | db[2] << 8 | db[1]; 3659 3660 return oui == HDMI_FORUM_IEEE_OUI; 3661 } 3662 3663 static bool cea_db_is_vcdb(const u8 *db) 3664 { 3665 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3666 return false; 3667 3668 if (cea_db_payload_len(db) != 2) 3669 return false; 3670 3671 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 3672 return false; 3673 3674 return true; 3675 } 3676 3677 static bool cea_db_is_y420cmdb(const u8 *db) 3678 { 3679 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3680 return false; 3681 3682 if (!cea_db_payload_len(db)) 3683 return false; 3684 3685 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3686 return false; 3687 3688 return true; 3689 } 3690 3691 static bool cea_db_is_y420vdb(const u8 *db) 3692 { 3693 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3694 return false; 3695 3696 if (!cea_db_payload_len(db)) 3697 return false; 3698 3699 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3700 return false; 3701 3702 return true; 3703 } 3704 3705 #define for_each_cea_db(cea, i, start, end) \ 3706 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3707 3708 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3709 const u8 *db) 3710 { 3711 struct drm_display_info *info = &connector->display_info; 3712 struct drm_hdmi_info *hdmi = &info->hdmi; 3713 u8 map_len = cea_db_payload_len(db) - 1; 3714 u8 count; 3715 u64 map = 0; 3716 3717 if (map_len == 0) { 3718 /* All CEA modes support ycbcr420 sampling also.*/ 3719 hdmi->y420_cmdb_map = U64_MAX; 3720 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3721 return; 3722 } 3723 3724 /* 3725 * This map indicates which of the existing CEA block modes 3726 * from VDB can support YCBCR420 output too. So if bit=0 is 3727 * set, first mode from VDB can support YCBCR420 output too. 3728 * We will parse and keep this map, before parsing VDB itself 3729 * to avoid going through the same block again and again. 3730 * 3731 * Spec is not clear about max possible size of this block. 3732 * Clamping max bitmap block size at 8 bytes. Every byte can 3733 * address 8 CEA modes, in this way this map can address 3734 * 8*8 = first 64 SVDs. 3735 */ 3736 if (WARN_ON_ONCE(map_len > 8)) 3737 map_len = 8; 3738 3739 for (count = 0; count < map_len; count++) 3740 map |= (u64)db[2 + count] << (8 * count); 3741 3742 if (map) 3743 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3744 3745 hdmi->y420_cmdb_map = map; 3746 } 3747 3748 static int 3749 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3750 { 3751 const u8 *cea = drm_find_cea_extension(edid); 3752 const u8 *db, *hdmi = NULL, *video = NULL; 3753 u8 dbl, hdmi_len, video_len = 0; 3754 int modes = 0; 3755 3756 if (cea && cea_revision(cea) >= 3) { 3757 int i, start, end; 3758 3759 if (cea_db_offsets(cea, &start, &end)) 3760 return 0; 3761 3762 for_each_cea_db(cea, i, start, end) { 3763 db = &cea[i]; 3764 dbl = cea_db_payload_len(db); 3765 3766 if (cea_db_tag(db) == VIDEO_BLOCK) { 3767 video = db + 1; 3768 video_len = dbl; 3769 modes += do_cea_modes(connector, video, dbl); 3770 } else if (cea_db_is_hdmi_vsdb(db)) { 3771 hdmi = db; 3772 hdmi_len = dbl; 3773 } else if (cea_db_is_y420vdb(db)) { 3774 const u8 *vdb420 = &db[2]; 3775 3776 /* Add 4:2:0(only) modes present in EDID */ 3777 modes += do_y420vdb_modes(connector, 3778 vdb420, 3779 dbl - 1); 3780 } 3781 } 3782 } 3783 3784 /* 3785 * We parse the HDMI VSDB after having added the cea modes as we will 3786 * be patching their flags when the sink supports stereo 3D. 3787 */ 3788 if (hdmi) 3789 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3790 video_len); 3791 3792 return modes; 3793 } 3794 3795 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3796 { 3797 const struct drm_display_mode *cea_mode; 3798 int clock1, clock2, clock; 3799 u8 vic; 3800 const char *type; 3801 3802 /* 3803 * allow 5kHz clock difference either way to account for 3804 * the 10kHz clock resolution limit of detailed timings. 3805 */ 3806 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3807 if (drm_valid_cea_vic(vic)) { 3808 type = "CEA"; 3809 cea_mode = &edid_cea_modes[vic]; 3810 clock1 = cea_mode->clock; 3811 clock2 = cea_mode_alternate_clock(cea_mode); 3812 } else { 3813 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3814 if (drm_valid_hdmi_vic(vic)) { 3815 type = "HDMI"; 3816 cea_mode = &edid_4k_modes[vic]; 3817 clock1 = cea_mode->clock; 3818 clock2 = hdmi_mode_alternate_clock(cea_mode); 3819 } else { 3820 return; 3821 } 3822 } 3823 3824 /* pick whichever is closest */ 3825 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3826 clock = clock1; 3827 else 3828 clock = clock2; 3829 3830 if (mode->clock == clock) 3831 return; 3832 3833 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3834 type, vic, mode->clock, clock); 3835 mode->clock = clock; 3836 } 3837 3838 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 3839 { 3840 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3841 return false; 3842 3843 if (db[1] != HDR_STATIC_METADATA_BLOCK) 3844 return false; 3845 3846 if (cea_db_payload_len(db) < 3) 3847 return false; 3848 3849 return true; 3850 } 3851 3852 static uint8_t eotf_supported(const u8 *edid_ext) 3853 { 3854 return edid_ext[2] & 3855 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 3856 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 3857 BIT(HDMI_EOTF_SMPTE_ST2084) | 3858 BIT(HDMI_EOTF_BT_2100_HLG)); 3859 } 3860 3861 static uint8_t hdr_metadata_type(const u8 *edid_ext) 3862 { 3863 return edid_ext[3] & 3864 BIT(HDMI_STATIC_METADATA_TYPE1); 3865 } 3866 3867 static void 3868 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 3869 { 3870 u16 len; 3871 3872 len = cea_db_payload_len(db); 3873 3874 connector->hdr_sink_metadata.hdmi_type1.eotf = 3875 eotf_supported(db); 3876 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 3877 hdr_metadata_type(db); 3878 3879 if (len >= 4) 3880 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 3881 if (len >= 5) 3882 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 3883 if (len >= 6) 3884 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 3885 } 3886 3887 static void 3888 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3889 { 3890 u8 len = cea_db_payload_len(db); 3891 3892 if (len >= 6 && (db[6] & (1 << 7))) 3893 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3894 if (len >= 8) { 3895 connector->latency_present[0] = db[8] >> 7; 3896 connector->latency_present[1] = (db[8] >> 6) & 1; 3897 } 3898 if (len >= 9) 3899 connector->video_latency[0] = db[9]; 3900 if (len >= 10) 3901 connector->audio_latency[0] = db[10]; 3902 if (len >= 11) 3903 connector->video_latency[1] = db[11]; 3904 if (len >= 12) 3905 connector->audio_latency[1] = db[12]; 3906 3907 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3908 "video latency %d %d, " 3909 "audio latency %d %d\n", 3910 connector->latency_present[0], 3911 connector->latency_present[1], 3912 connector->video_latency[0], 3913 connector->video_latency[1], 3914 connector->audio_latency[0], 3915 connector->audio_latency[1]); 3916 } 3917 3918 static void 3919 monitor_name(struct detailed_timing *t, void *data) 3920 { 3921 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3922 *(u8 **)data = t->data.other_data.data.str.str; 3923 } 3924 3925 static int get_monitor_name(struct edid *edid, char name[13]) 3926 { 3927 char *edid_name = NULL; 3928 int mnl; 3929 3930 if (!edid || !name) 3931 return 0; 3932 3933 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3934 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3935 if (edid_name[mnl] == 0x0a) 3936 break; 3937 3938 name[mnl] = edid_name[mnl]; 3939 } 3940 3941 return mnl; 3942 } 3943 3944 /** 3945 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3946 * @edid: monitor EDID information 3947 * @name: pointer to a character array to hold the name of the monitor 3948 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3949 * 3950 */ 3951 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3952 { 3953 int name_length; 3954 char buf[13]; 3955 3956 if (bufsize <= 0) 3957 return; 3958 3959 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3960 memcpy(name, buf, name_length); 3961 name[name_length] = '\0'; 3962 } 3963 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3964 3965 static void clear_eld(struct drm_connector *connector) 3966 { 3967 memset(connector->eld, 0, sizeof(connector->eld)); 3968 3969 connector->latency_present[0] = false; 3970 connector->latency_present[1] = false; 3971 connector->video_latency[0] = 0; 3972 connector->audio_latency[0] = 0; 3973 connector->video_latency[1] = 0; 3974 connector->audio_latency[1] = 0; 3975 } 3976 3977 /* 3978 * drm_edid_to_eld - build ELD from EDID 3979 * @connector: connector corresponding to the HDMI/DP sink 3980 * @edid: EDID to parse 3981 * 3982 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3983 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3984 */ 3985 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3986 { 3987 uint8_t *eld = connector->eld; 3988 u8 *cea; 3989 u8 *db; 3990 int total_sad_count = 0; 3991 int mnl; 3992 int dbl; 3993 3994 clear_eld(connector); 3995 3996 if (!edid) 3997 return; 3998 3999 cea = drm_find_cea_extension(edid); 4000 if (!cea) { 4001 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4002 return; 4003 } 4004 4005 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4006 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4007 4008 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4009 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4010 4011 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4012 4013 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4014 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4015 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4016 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4017 4018 if (cea_revision(cea) >= 3) { 4019 int i, start, end; 4020 4021 if (cea_db_offsets(cea, &start, &end)) { 4022 start = 0; 4023 end = 0; 4024 } 4025 4026 for_each_cea_db(cea, i, start, end) { 4027 db = &cea[i]; 4028 dbl = cea_db_payload_len(db); 4029 4030 switch (cea_db_tag(db)) { 4031 int sad_count; 4032 4033 case AUDIO_BLOCK: 4034 /* Audio Data Block, contains SADs */ 4035 sad_count = min(dbl / 3, 15 - total_sad_count); 4036 if (sad_count >= 1) 4037 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4038 &db[1], sad_count * 3); 4039 total_sad_count += sad_count; 4040 break; 4041 case SPEAKER_BLOCK: 4042 /* Speaker Allocation Data Block */ 4043 if (dbl >= 1) 4044 eld[DRM_ELD_SPEAKER] = db[1]; 4045 break; 4046 case VENDOR_BLOCK: 4047 /* HDMI Vendor-Specific Data Block */ 4048 if (cea_db_is_hdmi_vsdb(db)) 4049 drm_parse_hdmi_vsdb_audio(connector, db); 4050 break; 4051 default: 4052 break; 4053 } 4054 } 4055 } 4056 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4057 4058 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4059 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4060 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4061 else 4062 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4063 4064 eld[DRM_ELD_BASELINE_ELD_LEN] = 4065 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4066 4067 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4068 drm_eld_size(eld), total_sad_count); 4069 } 4070 4071 /** 4072 * drm_edid_to_sad - extracts SADs from EDID 4073 * @edid: EDID to parse 4074 * @sads: pointer that will be set to the extracted SADs 4075 * 4076 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4077 * 4078 * Note: The returned pointer needs to be freed using kfree(). 4079 * 4080 * Return: The number of found SADs or negative number on error. 4081 */ 4082 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4083 { 4084 int count = 0; 4085 int i, start, end, dbl; 4086 u8 *cea; 4087 4088 cea = drm_find_cea_extension(edid); 4089 if (!cea) { 4090 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4091 return -ENOENT; 4092 } 4093 4094 if (cea_revision(cea) < 3) { 4095 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4096 return -ENOTSUPP; 4097 } 4098 4099 if (cea_db_offsets(cea, &start, &end)) { 4100 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4101 return -EPROTO; 4102 } 4103 4104 for_each_cea_db(cea, i, start, end) { 4105 u8 *db = &cea[i]; 4106 4107 if (cea_db_tag(db) == AUDIO_BLOCK) { 4108 int j; 4109 dbl = cea_db_payload_len(db); 4110 4111 count = dbl / 3; /* SAD is 3B */ 4112 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4113 if (!*sads) 4114 return -ENOMEM; 4115 for (j = 0; j < count; j++) { 4116 u8 *sad = &db[1 + j * 3]; 4117 4118 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4119 (*sads)[j].channels = sad[0] & 0x7; 4120 (*sads)[j].freq = sad[1] & 0x7F; 4121 (*sads)[j].byte2 = sad[2]; 4122 } 4123 break; 4124 } 4125 } 4126 4127 return count; 4128 } 4129 EXPORT_SYMBOL(drm_edid_to_sad); 4130 4131 /** 4132 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4133 * @edid: EDID to parse 4134 * @sadb: pointer to the speaker block 4135 * 4136 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4137 * 4138 * Note: The returned pointer needs to be freed using kfree(). 4139 * 4140 * Return: The number of found Speaker Allocation Blocks or negative number on 4141 * error. 4142 */ 4143 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4144 { 4145 int count = 0; 4146 int i, start, end, dbl; 4147 const u8 *cea; 4148 4149 cea = drm_find_cea_extension(edid); 4150 if (!cea) { 4151 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4152 return -ENOENT; 4153 } 4154 4155 if (cea_revision(cea) < 3) { 4156 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4157 return -ENOTSUPP; 4158 } 4159 4160 if (cea_db_offsets(cea, &start, &end)) { 4161 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4162 return -EPROTO; 4163 } 4164 4165 for_each_cea_db(cea, i, start, end) { 4166 const u8 *db = &cea[i]; 4167 4168 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4169 dbl = cea_db_payload_len(db); 4170 4171 /* Speaker Allocation Data Block */ 4172 if (dbl == 3) { 4173 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4174 if (!*sadb) 4175 return -ENOMEM; 4176 count = dbl; 4177 break; 4178 } 4179 } 4180 } 4181 4182 return count; 4183 } 4184 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4185 4186 /** 4187 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4188 * @connector: connector associated with the HDMI/DP sink 4189 * @mode: the display mode 4190 * 4191 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4192 * the sink doesn't support audio or video. 4193 */ 4194 int drm_av_sync_delay(struct drm_connector *connector, 4195 const struct drm_display_mode *mode) 4196 { 4197 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4198 int a, v; 4199 4200 if (!connector->latency_present[0]) 4201 return 0; 4202 if (!connector->latency_present[1]) 4203 i = 0; 4204 4205 a = connector->audio_latency[i]; 4206 v = connector->video_latency[i]; 4207 4208 /* 4209 * HDMI/DP sink doesn't support audio or video? 4210 */ 4211 if (a == 255 || v == 255) 4212 return 0; 4213 4214 /* 4215 * Convert raw EDID values to millisecond. 4216 * Treat unknown latency as 0ms. 4217 */ 4218 if (a) 4219 a = min(2 * (a - 1), 500); 4220 if (v) 4221 v = min(2 * (v - 1), 500); 4222 4223 return max(v - a, 0); 4224 } 4225 EXPORT_SYMBOL(drm_av_sync_delay); 4226 4227 /** 4228 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4229 * @edid: monitor EDID information 4230 * 4231 * Parse the CEA extension according to CEA-861-B. 4232 * 4233 * Return: True if the monitor is HDMI, false if not or unknown. 4234 */ 4235 bool drm_detect_hdmi_monitor(struct edid *edid) 4236 { 4237 u8 *edid_ext; 4238 int i; 4239 int start_offset, end_offset; 4240 4241 edid_ext = drm_find_cea_extension(edid); 4242 if (!edid_ext) 4243 return false; 4244 4245 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4246 return false; 4247 4248 /* 4249 * Because HDMI identifier is in Vendor Specific Block, 4250 * search it from all data blocks of CEA extension. 4251 */ 4252 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4253 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4254 return true; 4255 } 4256 4257 return false; 4258 } 4259 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4260 4261 /** 4262 * drm_detect_monitor_audio - check monitor audio capability 4263 * @edid: EDID block to scan 4264 * 4265 * Monitor should have CEA extension block. 4266 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4267 * audio' only. If there is any audio extension block and supported 4268 * audio format, assume at least 'basic audio' support, even if 'basic 4269 * audio' is not defined in EDID. 4270 * 4271 * Return: True if the monitor supports audio, false otherwise. 4272 */ 4273 bool drm_detect_monitor_audio(struct edid *edid) 4274 { 4275 u8 *edid_ext; 4276 int i, j; 4277 bool has_audio = false; 4278 int start_offset, end_offset; 4279 4280 edid_ext = drm_find_cea_extension(edid); 4281 if (!edid_ext) 4282 goto end; 4283 4284 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4285 4286 if (has_audio) { 4287 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4288 goto end; 4289 } 4290 4291 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4292 goto end; 4293 4294 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4295 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4296 has_audio = true; 4297 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4298 DRM_DEBUG_KMS("CEA audio format %d\n", 4299 (edid_ext[i + j] >> 3) & 0xf); 4300 goto end; 4301 } 4302 } 4303 end: 4304 return has_audio; 4305 } 4306 EXPORT_SYMBOL(drm_detect_monitor_audio); 4307 4308 4309 /** 4310 * drm_default_rgb_quant_range - default RGB quantization range 4311 * @mode: display mode 4312 * 4313 * Determine the default RGB quantization range for the mode, 4314 * as specified in CEA-861. 4315 * 4316 * Return: The default RGB quantization range for the mode 4317 */ 4318 enum hdmi_quantization_range 4319 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4320 { 4321 /* All CEA modes other than VIC 1 use limited quantization range. */ 4322 return drm_match_cea_mode(mode) > 1 ? 4323 HDMI_QUANTIZATION_RANGE_LIMITED : 4324 HDMI_QUANTIZATION_RANGE_FULL; 4325 } 4326 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4327 4328 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4329 { 4330 struct drm_display_info *info = &connector->display_info; 4331 4332 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4333 4334 if (db[2] & EDID_CEA_VCDB_QS) 4335 info->rgb_quant_range_selectable = true; 4336 } 4337 4338 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4339 const u8 *db) 4340 { 4341 u8 dc_mask; 4342 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4343 4344 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4345 hdmi->y420_dc_modes = dc_mask; 4346 } 4347 4348 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4349 const u8 *hf_vsdb) 4350 { 4351 struct drm_display_info *display = &connector->display_info; 4352 struct drm_hdmi_info *hdmi = &display->hdmi; 4353 4354 display->has_hdmi_infoframe = true; 4355 4356 if (hf_vsdb[6] & 0x80) { 4357 hdmi->scdc.supported = true; 4358 if (hf_vsdb[6] & 0x40) 4359 hdmi->scdc.read_request = true; 4360 } 4361 4362 /* 4363 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4364 * And as per the spec, three factors confirm this: 4365 * * Availability of a HF-VSDB block in EDID (check) 4366 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4367 * * SCDC support available (let's check) 4368 * Lets check it out. 4369 */ 4370 4371 if (hf_vsdb[5]) { 4372 /* max clock is 5000 KHz times block value */ 4373 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4374 struct drm_scdc *scdc = &hdmi->scdc; 4375 4376 if (max_tmds_clock > 340000) { 4377 display->max_tmds_clock = max_tmds_clock; 4378 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4379 display->max_tmds_clock); 4380 } 4381 4382 if (scdc->supported) { 4383 scdc->scrambling.supported = true; 4384 4385 /* Few sinks support scrambling for cloks < 340M */ 4386 if ((hf_vsdb[6] & 0x8)) 4387 scdc->scrambling.low_rates = true; 4388 } 4389 } 4390 4391 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4392 } 4393 4394 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4395 const u8 *hdmi) 4396 { 4397 struct drm_display_info *info = &connector->display_info; 4398 unsigned int dc_bpc = 0; 4399 4400 /* HDMI supports at least 8 bpc */ 4401 info->bpc = 8; 4402 4403 if (cea_db_payload_len(hdmi) < 6) 4404 return; 4405 4406 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4407 dc_bpc = 10; 4408 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4409 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4410 connector->name); 4411 } 4412 4413 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4414 dc_bpc = 12; 4415 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4416 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4417 connector->name); 4418 } 4419 4420 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4421 dc_bpc = 16; 4422 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4423 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4424 connector->name); 4425 } 4426 4427 if (dc_bpc == 0) { 4428 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4429 connector->name); 4430 return; 4431 } 4432 4433 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4434 connector->name, dc_bpc); 4435 info->bpc = dc_bpc; 4436 4437 /* 4438 * Deep color support mandates RGB444 support for all video 4439 * modes and forbids YCRCB422 support for all video modes per 4440 * HDMI 1.3 spec. 4441 */ 4442 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4443 4444 /* YCRCB444 is optional according to spec. */ 4445 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4446 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4447 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4448 connector->name); 4449 } 4450 4451 /* 4452 * Spec says that if any deep color mode is supported at all, 4453 * then deep color 36 bit must be supported. 4454 */ 4455 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4456 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4457 connector->name); 4458 } 4459 } 4460 4461 static void 4462 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4463 { 4464 struct drm_display_info *info = &connector->display_info; 4465 u8 len = cea_db_payload_len(db); 4466 4467 if (len >= 6) 4468 info->dvi_dual = db[6] & 1; 4469 if (len >= 7) 4470 info->max_tmds_clock = db[7] * 5000; 4471 4472 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4473 "max TMDS clock %d kHz\n", 4474 info->dvi_dual, 4475 info->max_tmds_clock); 4476 4477 drm_parse_hdmi_deep_color_info(connector, db); 4478 } 4479 4480 static void drm_parse_cea_ext(struct drm_connector *connector, 4481 const struct edid *edid) 4482 { 4483 struct drm_display_info *info = &connector->display_info; 4484 const u8 *edid_ext; 4485 int i, start, end; 4486 4487 edid_ext = drm_find_cea_extension(edid); 4488 if (!edid_ext) 4489 return; 4490 4491 info->cea_rev = edid_ext[1]; 4492 4493 /* The existence of a CEA block should imply RGB support */ 4494 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4495 if (edid_ext[3] & EDID_CEA_YCRCB444) 4496 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4497 if (edid_ext[3] & EDID_CEA_YCRCB422) 4498 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4499 4500 if (cea_db_offsets(edid_ext, &start, &end)) 4501 return; 4502 4503 for_each_cea_db(edid_ext, i, start, end) { 4504 const u8 *db = &edid_ext[i]; 4505 4506 if (cea_db_is_hdmi_vsdb(db)) 4507 drm_parse_hdmi_vsdb_video(connector, db); 4508 if (cea_db_is_hdmi_forum_vsdb(db)) 4509 drm_parse_hdmi_forum_vsdb(connector, db); 4510 if (cea_db_is_y420cmdb(db)) 4511 drm_parse_y420cmdb_bitmap(connector, db); 4512 if (cea_db_is_vcdb(db)) 4513 drm_parse_vcdb(connector, db); 4514 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4515 drm_parse_hdr_metadata_block(connector, db); 4516 } 4517 } 4518 4519 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4520 * all of the values which would have been set from EDID 4521 */ 4522 void 4523 drm_reset_display_info(struct drm_connector *connector) 4524 { 4525 struct drm_display_info *info = &connector->display_info; 4526 4527 info->width_mm = 0; 4528 info->height_mm = 0; 4529 4530 info->bpc = 0; 4531 info->color_formats = 0; 4532 info->cea_rev = 0; 4533 info->max_tmds_clock = 0; 4534 info->dvi_dual = false; 4535 info->has_hdmi_infoframe = false; 4536 info->rgb_quant_range_selectable = false; 4537 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4538 4539 info->non_desktop = 0; 4540 } 4541 4542 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4543 { 4544 struct drm_display_info *info = &connector->display_info; 4545 4546 u32 quirks = edid_get_quirks(edid); 4547 4548 drm_reset_display_info(connector); 4549 4550 info->width_mm = edid->width_cm * 10; 4551 info->height_mm = edid->height_cm * 10; 4552 4553 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4554 4555 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4556 4557 if (edid->revision < 3) 4558 return quirks; 4559 4560 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4561 return quirks; 4562 4563 drm_parse_cea_ext(connector, edid); 4564 4565 /* 4566 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4567 * 4568 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4569 * tells us to assume 8 bpc color depth if the EDID doesn't have 4570 * extensions which tell otherwise. 4571 */ 4572 if ((info->bpc == 0) && (edid->revision < 4) && 4573 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4574 info->bpc = 8; 4575 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4576 connector->name, info->bpc); 4577 } 4578 4579 /* Only defined for 1.4 with digital displays */ 4580 if (edid->revision < 4) 4581 return quirks; 4582 4583 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4584 case DRM_EDID_DIGITAL_DEPTH_6: 4585 info->bpc = 6; 4586 break; 4587 case DRM_EDID_DIGITAL_DEPTH_8: 4588 info->bpc = 8; 4589 break; 4590 case DRM_EDID_DIGITAL_DEPTH_10: 4591 info->bpc = 10; 4592 break; 4593 case DRM_EDID_DIGITAL_DEPTH_12: 4594 info->bpc = 12; 4595 break; 4596 case DRM_EDID_DIGITAL_DEPTH_14: 4597 info->bpc = 14; 4598 break; 4599 case DRM_EDID_DIGITAL_DEPTH_16: 4600 info->bpc = 16; 4601 break; 4602 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4603 default: 4604 info->bpc = 0; 4605 break; 4606 } 4607 4608 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4609 connector->name, info->bpc); 4610 4611 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4612 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4613 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4614 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4615 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4616 return quirks; 4617 } 4618 4619 static int validate_displayid(u8 *displayid, int length, int idx) 4620 { 4621 int i; 4622 u8 csum = 0; 4623 struct displayid_hdr *base; 4624 4625 base = (struct displayid_hdr *)&displayid[idx]; 4626 4627 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4628 base->rev, base->bytes, base->prod_id, base->ext_count); 4629 4630 if (base->bytes + 5 > length - idx) 4631 return -EINVAL; 4632 for (i = idx; i <= base->bytes + 5; i++) { 4633 csum += displayid[i]; 4634 } 4635 if (csum) { 4636 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4637 return -EINVAL; 4638 } 4639 return 0; 4640 } 4641 4642 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4643 struct displayid_detailed_timings_1 *timings) 4644 { 4645 struct drm_display_mode *mode; 4646 unsigned pixel_clock = (timings->pixel_clock[0] | 4647 (timings->pixel_clock[1] << 8) | 4648 (timings->pixel_clock[2] << 16)); 4649 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4650 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4651 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4652 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4653 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4654 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4655 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4656 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4657 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4658 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4659 mode = drm_mode_create(dev); 4660 if (!mode) 4661 return NULL; 4662 4663 mode->clock = pixel_clock * 10; 4664 mode->hdisplay = hactive; 4665 mode->hsync_start = mode->hdisplay + hsync; 4666 mode->hsync_end = mode->hsync_start + hsync_width; 4667 mode->htotal = mode->hdisplay + hblank; 4668 4669 mode->vdisplay = vactive; 4670 mode->vsync_start = mode->vdisplay + vsync; 4671 mode->vsync_end = mode->vsync_start + vsync_width; 4672 mode->vtotal = mode->vdisplay + vblank; 4673 4674 mode->flags = 0; 4675 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4676 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4677 mode->type = DRM_MODE_TYPE_DRIVER; 4678 4679 if (timings->flags & 0x80) 4680 mode->type |= DRM_MODE_TYPE_PREFERRED; 4681 mode->vrefresh = drm_mode_vrefresh(mode); 4682 drm_mode_set_name(mode); 4683 4684 return mode; 4685 } 4686 4687 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4688 struct displayid_block *block) 4689 { 4690 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4691 int i; 4692 int num_timings; 4693 struct drm_display_mode *newmode; 4694 int num_modes = 0; 4695 /* blocks must be multiple of 20 bytes length */ 4696 if (block->num_bytes % 20) 4697 return 0; 4698 4699 num_timings = block->num_bytes / 20; 4700 for (i = 0; i < num_timings; i++) { 4701 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4702 4703 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4704 if (!newmode) 4705 continue; 4706 4707 drm_mode_probed_add(connector, newmode); 4708 num_modes++; 4709 } 4710 return num_modes; 4711 } 4712 4713 static int add_displayid_detailed_modes(struct drm_connector *connector, 4714 struct edid *edid) 4715 { 4716 u8 *displayid; 4717 int ret; 4718 int idx = 1; 4719 int length = EDID_LENGTH; 4720 struct displayid_block *block; 4721 int num_modes = 0; 4722 4723 displayid = drm_find_displayid_extension(edid); 4724 if (!displayid) 4725 return 0; 4726 4727 ret = validate_displayid(displayid, length, idx); 4728 if (ret) 4729 return 0; 4730 4731 idx += sizeof(struct displayid_hdr); 4732 while (block = (struct displayid_block *)&displayid[idx], 4733 idx + sizeof(struct displayid_block) <= length && 4734 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4735 block->num_bytes > 0) { 4736 idx += block->num_bytes + sizeof(struct displayid_block); 4737 switch (block->tag) { 4738 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4739 num_modes += add_displayid_detailed_1_modes(connector, block); 4740 break; 4741 } 4742 } 4743 return num_modes; 4744 } 4745 4746 /** 4747 * drm_add_edid_modes - add modes from EDID data, if available 4748 * @connector: connector we're probing 4749 * @edid: EDID data 4750 * 4751 * Add the specified modes to the connector's mode list. Also fills out the 4752 * &drm_display_info structure and ELD in @connector with any information which 4753 * can be derived from the edid. 4754 * 4755 * Return: The number of modes added or 0 if we couldn't find any. 4756 */ 4757 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4758 { 4759 int num_modes = 0; 4760 u32 quirks; 4761 4762 if (edid == NULL) { 4763 clear_eld(connector); 4764 return 0; 4765 } 4766 if (!drm_edid_is_valid(edid)) { 4767 clear_eld(connector); 4768 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4769 connector->name); 4770 return 0; 4771 } 4772 4773 drm_edid_to_eld(connector, edid); 4774 4775 /* 4776 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4777 * To avoid multiple parsing of same block, lets parse that map 4778 * from sink info, before parsing CEA modes. 4779 */ 4780 quirks = drm_add_display_info(connector, edid); 4781 4782 /* 4783 * EDID spec says modes should be preferred in this order: 4784 * - preferred detailed mode 4785 * - other detailed modes from base block 4786 * - detailed modes from extension blocks 4787 * - CVT 3-byte code modes 4788 * - standard timing codes 4789 * - established timing codes 4790 * - modes inferred from GTF or CVT range information 4791 * 4792 * We get this pretty much right. 4793 * 4794 * XXX order for additional mode types in extension blocks? 4795 */ 4796 num_modes += add_detailed_modes(connector, edid, quirks); 4797 num_modes += add_cvt_modes(connector, edid); 4798 num_modes += add_standard_modes(connector, edid); 4799 num_modes += add_established_modes(connector, edid); 4800 num_modes += add_cea_modes(connector, edid); 4801 num_modes += add_alternate_cea_modes(connector, edid); 4802 num_modes += add_displayid_detailed_modes(connector, edid); 4803 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4804 num_modes += add_inferred_modes(connector, edid); 4805 4806 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4807 edid_fixup_preferred(connector, quirks); 4808 4809 if (quirks & EDID_QUIRK_FORCE_6BPC) 4810 connector->display_info.bpc = 6; 4811 4812 if (quirks & EDID_QUIRK_FORCE_8BPC) 4813 connector->display_info.bpc = 8; 4814 4815 if (quirks & EDID_QUIRK_FORCE_10BPC) 4816 connector->display_info.bpc = 10; 4817 4818 if (quirks & EDID_QUIRK_FORCE_12BPC) 4819 connector->display_info.bpc = 12; 4820 4821 return num_modes; 4822 } 4823 EXPORT_SYMBOL(drm_add_edid_modes); 4824 4825 /** 4826 * drm_add_modes_noedid - add modes for the connectors without EDID 4827 * @connector: connector we're probing 4828 * @hdisplay: the horizontal display limit 4829 * @vdisplay: the vertical display limit 4830 * 4831 * Add the specified modes to the connector's mode list. Only when the 4832 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4833 * 4834 * Return: The number of modes added or 0 if we couldn't find any. 4835 */ 4836 int drm_add_modes_noedid(struct drm_connector *connector, 4837 int hdisplay, int vdisplay) 4838 { 4839 int i, count, num_modes = 0; 4840 struct drm_display_mode *mode; 4841 struct drm_device *dev = connector->dev; 4842 4843 count = ARRAY_SIZE(drm_dmt_modes); 4844 if (hdisplay < 0) 4845 hdisplay = 0; 4846 if (vdisplay < 0) 4847 vdisplay = 0; 4848 4849 for (i = 0; i < count; i++) { 4850 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4851 if (hdisplay && vdisplay) { 4852 /* 4853 * Only when two are valid, they will be used to check 4854 * whether the mode should be added to the mode list of 4855 * the connector. 4856 */ 4857 if (ptr->hdisplay > hdisplay || 4858 ptr->vdisplay > vdisplay) 4859 continue; 4860 } 4861 if (drm_mode_vrefresh(ptr) > 61) 4862 continue; 4863 mode = drm_mode_duplicate(dev, ptr); 4864 if (mode) { 4865 drm_mode_probed_add(connector, mode); 4866 num_modes++; 4867 } 4868 } 4869 return num_modes; 4870 } 4871 EXPORT_SYMBOL(drm_add_modes_noedid); 4872 4873 /** 4874 * drm_set_preferred_mode - Sets the preferred mode of a connector 4875 * @connector: connector whose mode list should be processed 4876 * @hpref: horizontal resolution of preferred mode 4877 * @vpref: vertical resolution of preferred mode 4878 * 4879 * Marks a mode as preferred if it matches the resolution specified by @hpref 4880 * and @vpref. 4881 */ 4882 void drm_set_preferred_mode(struct drm_connector *connector, 4883 int hpref, int vpref) 4884 { 4885 struct drm_display_mode *mode; 4886 4887 list_for_each_entry(mode, &connector->probed_modes, head) { 4888 if (mode->hdisplay == hpref && 4889 mode->vdisplay == vpref) 4890 mode->type |= DRM_MODE_TYPE_PREFERRED; 4891 } 4892 } 4893 EXPORT_SYMBOL(drm_set_preferred_mode); 4894 4895 static bool is_hdmi2_sink(struct drm_connector *connector) 4896 { 4897 /* 4898 * FIXME: sil-sii8620 doesn't have a connector around when 4899 * we need one, so we have to be prepared for a NULL connector. 4900 */ 4901 if (!connector) 4902 return true; 4903 4904 return connector->display_info.hdmi.scdc.supported || 4905 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 4906 } 4907 4908 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 4909 { 4910 return sink_eotf & BIT(output_eotf); 4911 } 4912 4913 /** 4914 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 4915 * HDR metadata from userspace 4916 * @frame: HDMI DRM infoframe 4917 * @conn_state: Connector state containing HDR metadata 4918 * 4919 * Return: 0 on success or a negative error code on failure. 4920 */ 4921 int 4922 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 4923 const struct drm_connector_state *conn_state) 4924 { 4925 struct drm_connector *connector; 4926 struct hdr_output_metadata *hdr_metadata; 4927 int err; 4928 4929 if (!frame || !conn_state) 4930 return -EINVAL; 4931 4932 connector = conn_state->connector; 4933 4934 if (!conn_state->hdr_output_metadata) 4935 return -EINVAL; 4936 4937 hdr_metadata = conn_state->hdr_output_metadata->data; 4938 4939 if (!hdr_metadata || !connector) 4940 return -EINVAL; 4941 4942 /* Sink EOTF is Bit map while infoframe is absolute values */ 4943 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 4944 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 4945 DRM_DEBUG_KMS("EOTF Not Supported\n"); 4946 return -EINVAL; 4947 } 4948 4949 err = hdmi_drm_infoframe_init(frame); 4950 if (err < 0) 4951 return err; 4952 4953 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 4954 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 4955 4956 BUILD_BUG_ON(sizeof(frame->display_primaries) != 4957 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 4958 BUILD_BUG_ON(sizeof(frame->white_point) != 4959 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 4960 4961 memcpy(&frame->display_primaries, 4962 &hdr_metadata->hdmi_metadata_type1.display_primaries, 4963 sizeof(frame->display_primaries)); 4964 4965 memcpy(&frame->white_point, 4966 &hdr_metadata->hdmi_metadata_type1.white_point, 4967 sizeof(frame->white_point)); 4968 4969 frame->max_display_mastering_luminance = 4970 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 4971 frame->min_display_mastering_luminance = 4972 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 4973 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 4974 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 4975 4976 return 0; 4977 } 4978 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 4979 4980 /** 4981 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4982 * data from a DRM display mode 4983 * @frame: HDMI AVI infoframe 4984 * @connector: the connector 4985 * @mode: DRM display mode 4986 * 4987 * Return: 0 on success or a negative error code on failure. 4988 */ 4989 int 4990 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4991 struct drm_connector *connector, 4992 const struct drm_display_mode *mode) 4993 { 4994 enum hdmi_picture_aspect picture_aspect; 4995 int err; 4996 4997 if (!frame || !mode) 4998 return -EINVAL; 4999 5000 err = hdmi_avi_infoframe_init(frame); 5001 if (err < 0) 5002 return err; 5003 5004 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5005 frame->pixel_repeat = 1; 5006 5007 frame->video_code = drm_match_cea_mode(mode); 5008 5009 /* 5010 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5011 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5012 * have to make sure we dont break HDMI 1.4 sinks. 5013 */ 5014 if (!is_hdmi2_sink(connector) && frame->video_code > 64) 5015 frame->video_code = 0; 5016 5017 /* 5018 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5019 * we should send its VIC in vendor infoframes, else send the 5020 * VIC in AVI infoframes. Lets check if this mode is present in 5021 * HDMI 1.4b 4K modes 5022 */ 5023 if (frame->video_code) { 5024 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5025 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5026 5027 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5028 frame->video_code = 0; 5029 } 5030 5031 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5032 5033 /* 5034 * As some drivers don't support atomic, we can't use connector state. 5035 * So just initialize the frame with default values, just the same way 5036 * as it's done with other properties here. 5037 */ 5038 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5039 frame->itc = 0; 5040 5041 /* 5042 * Populate picture aspect ratio from either 5043 * user input (if specified) or from the CEA mode list. 5044 */ 5045 picture_aspect = mode->picture_aspect_ratio; 5046 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 5047 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 5048 5049 /* 5050 * The infoframe can't convey anything but none, 4:3 5051 * and 16:9, so if the user has asked for anything else 5052 * we can only satisfy it by specifying the right VIC. 5053 */ 5054 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5055 if (picture_aspect != 5056 drm_get_cea_aspect_ratio(frame->video_code)) 5057 return -EINVAL; 5058 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5059 } 5060 5061 frame->picture_aspect = picture_aspect; 5062 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5063 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5064 5065 return 0; 5066 } 5067 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5068 5069 /* HDMI Colorspace Spec Definitions */ 5070 #define FULL_COLORIMETRY_MASK 0x1FF 5071 #define NORMAL_COLORIMETRY_MASK 0x3 5072 #define EXTENDED_COLORIMETRY_MASK 0x7 5073 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5074 5075 #define C(x) ((x) << 0) 5076 #define EC(x) ((x) << 2) 5077 #define ACE(x) ((x) << 5) 5078 5079 #define HDMI_COLORIMETRY_NO_DATA 0x0 5080 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5081 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5082 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5083 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5084 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5085 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5086 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5087 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5088 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5089 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5090 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5091 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5092 5093 static const u32 hdmi_colorimetry_val[] = { 5094 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5095 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5096 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5097 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5098 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5099 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5100 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5101 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5102 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5103 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5104 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5105 }; 5106 5107 #undef C 5108 #undef EC 5109 #undef ACE 5110 5111 /** 5112 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5113 * colorspace information 5114 * @frame: HDMI AVI infoframe 5115 * @conn_state: connector state 5116 */ 5117 void 5118 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5119 const struct drm_connector_state *conn_state) 5120 { 5121 u32 colorimetry_val; 5122 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5123 5124 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5125 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5126 else 5127 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5128 5129 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5130 /* 5131 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5132 * structure and extend it in drivers/video/hdmi 5133 */ 5134 frame->extended_colorimetry = (colorimetry_val >> 2) & 5135 EXTENDED_COLORIMETRY_MASK; 5136 } 5137 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5138 5139 /** 5140 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5141 * quantization range information 5142 * @frame: HDMI AVI infoframe 5143 * @connector: the connector 5144 * @mode: DRM display mode 5145 * @rgb_quant_range: RGB quantization range (Q) 5146 */ 5147 void 5148 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5149 struct drm_connector *connector, 5150 const struct drm_display_mode *mode, 5151 enum hdmi_quantization_range rgb_quant_range) 5152 { 5153 const struct drm_display_info *info = &connector->display_info; 5154 5155 /* 5156 * CEA-861: 5157 * "A Source shall not send a non-zero Q value that does not correspond 5158 * to the default RGB Quantization Range for the transmitted Picture 5159 * unless the Sink indicates support for the Q bit in a Video 5160 * Capabilities Data Block." 5161 * 5162 * HDMI 2.0 recommends sending non-zero Q when it does match the 5163 * default RGB quantization range for the mode, even when QS=0. 5164 */ 5165 if (info->rgb_quant_range_selectable || 5166 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5167 frame->quantization_range = rgb_quant_range; 5168 else 5169 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5170 5171 /* 5172 * CEA-861-F: 5173 * "When transmitting any RGB colorimetry, the Source should set the 5174 * YQ-field to match the RGB Quantization Range being transmitted 5175 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5176 * set YQ=1) and the Sink shall ignore the YQ-field." 5177 * 5178 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5179 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5180 * good way to tell which version of CEA-861 the sink supports, so 5181 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5182 * on on CEA-861-F. 5183 */ 5184 if (!is_hdmi2_sink(connector) || 5185 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5186 frame->ycc_quantization_range = 5187 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5188 else 5189 frame->ycc_quantization_range = 5190 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5191 } 5192 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5193 5194 static enum hdmi_3d_structure 5195 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5196 { 5197 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5198 5199 switch (layout) { 5200 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5201 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5202 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5203 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5204 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5205 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5206 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5207 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5208 case DRM_MODE_FLAG_3D_L_DEPTH: 5209 return HDMI_3D_STRUCTURE_L_DEPTH; 5210 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5211 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5212 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5213 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5214 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5215 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5216 default: 5217 return HDMI_3D_STRUCTURE_INVALID; 5218 } 5219 } 5220 5221 /** 5222 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5223 * data from a DRM display mode 5224 * @frame: HDMI vendor infoframe 5225 * @connector: the connector 5226 * @mode: DRM display mode 5227 * 5228 * Note that there's is a need to send HDMI vendor infoframes only when using a 5229 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5230 * function will return -EINVAL, error that can be safely ignored. 5231 * 5232 * Return: 0 on success or a negative error code on failure. 5233 */ 5234 int 5235 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5236 struct drm_connector *connector, 5237 const struct drm_display_mode *mode) 5238 { 5239 /* 5240 * FIXME: sil-sii8620 doesn't have a connector around when 5241 * we need one, so we have to be prepared for a NULL connector. 5242 */ 5243 bool has_hdmi_infoframe = connector ? 5244 connector->display_info.has_hdmi_infoframe : false; 5245 int err; 5246 u32 s3d_flags; 5247 u8 vic; 5248 5249 if (!frame || !mode) 5250 return -EINVAL; 5251 5252 if (!has_hdmi_infoframe) 5253 return -EINVAL; 5254 5255 vic = drm_match_hdmi_mode(mode); 5256 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5257 5258 /* 5259 * Even if it's not absolutely necessary to send the infoframe 5260 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5261 * know that the sink can handle it. This is based on a 5262 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5263 * have trouble realizing that they shuld switch from 3D to 2D 5264 * mode if the source simply stops sending the infoframe when 5265 * it wants to switch from 3D to 2D. 5266 */ 5267 5268 if (vic && s3d_flags) 5269 return -EINVAL; 5270 5271 err = hdmi_vendor_infoframe_init(frame); 5272 if (err < 0) 5273 return err; 5274 5275 frame->vic = vic; 5276 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5277 5278 return 0; 5279 } 5280 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5281 5282 static int drm_parse_tiled_block(struct drm_connector *connector, 5283 struct displayid_block *block) 5284 { 5285 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5286 u16 w, h; 5287 u8 tile_v_loc, tile_h_loc; 5288 u8 num_v_tile, num_h_tile; 5289 struct drm_tile_group *tg; 5290 5291 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5292 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5293 5294 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5295 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5296 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5297 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5298 5299 connector->has_tile = true; 5300 if (tile->tile_cap & 0x80) 5301 connector->tile_is_single_monitor = true; 5302 5303 connector->num_h_tile = num_h_tile + 1; 5304 connector->num_v_tile = num_v_tile + 1; 5305 connector->tile_h_loc = tile_h_loc; 5306 connector->tile_v_loc = tile_v_loc; 5307 connector->tile_h_size = w + 1; 5308 connector->tile_v_size = h + 1; 5309 5310 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5311 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5312 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5313 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5314 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5315 5316 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5317 if (!tg) { 5318 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5319 } 5320 if (!tg) 5321 return -ENOMEM; 5322 5323 if (connector->tile_group != tg) { 5324 /* if we haven't got a pointer, 5325 take the reference, drop ref to old tile group */ 5326 if (connector->tile_group) { 5327 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5328 } 5329 connector->tile_group = tg; 5330 } else 5331 /* if same tile group, then release the ref we just took. */ 5332 drm_mode_put_tile_group(connector->dev, tg); 5333 return 0; 5334 } 5335 5336 static int drm_parse_display_id(struct drm_connector *connector, 5337 u8 *displayid, int length, 5338 bool is_edid_extension) 5339 { 5340 /* if this is an EDID extension the first byte will be 0x70 */ 5341 int idx = 0; 5342 struct displayid_block *block; 5343 int ret; 5344 5345 if (is_edid_extension) 5346 idx = 1; 5347 5348 ret = validate_displayid(displayid, length, idx); 5349 if (ret) 5350 return ret; 5351 5352 idx += sizeof(struct displayid_hdr); 5353 while (block = (struct displayid_block *)&displayid[idx], 5354 idx + sizeof(struct displayid_block) <= length && 5355 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5356 block->num_bytes > 0) { 5357 idx += block->num_bytes + sizeof(struct displayid_block); 5358 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5359 block->tag, block->rev, block->num_bytes); 5360 5361 switch (block->tag) { 5362 case DATA_BLOCK_TILED_DISPLAY: 5363 ret = drm_parse_tiled_block(connector, block); 5364 if (ret) 5365 return ret; 5366 break; 5367 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5368 /* handled in mode gathering code. */ 5369 break; 5370 default: 5371 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5372 break; 5373 } 5374 } 5375 return 0; 5376 } 5377 5378 static void drm_get_displayid(struct drm_connector *connector, 5379 struct edid *edid) 5380 { 5381 void *displayid = NULL; 5382 int ret; 5383 connector->has_tile = false; 5384 displayid = drm_find_displayid_extension(edid); 5385 if (!displayid) { 5386 /* drop reference to any tile group we had */ 5387 goto out_drop_ref; 5388 } 5389 5390 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5391 if (ret < 0) 5392 goto out_drop_ref; 5393 if (!connector->has_tile) 5394 goto out_drop_ref; 5395 return; 5396 out_drop_ref: 5397 if (connector->tile_group) { 5398 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5399 connector->tile_group = NULL; 5400 } 5401 return; 5402 } 5403