1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static void drm_get_displayid(struct drm_connector *connector, 1588 struct edid *edid); 1589 static int validate_displayid(u8 *displayid, int length, int idx); 1590 1591 static int drm_edid_block_checksum(const u8 *raw_edid) 1592 { 1593 int i; 1594 u8 csum = 0, crc = 0; 1595 1596 for (i = 0; i < EDID_LENGTH - 1; i++) 1597 csum += raw_edid[i]; 1598 1599 crc = 0x100 - csum; 1600 1601 return crc; 1602 } 1603 1604 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1605 { 1606 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1607 return true; 1608 else 1609 return false; 1610 } 1611 1612 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1613 { 1614 if (memchr_inv(in_edid, 0, length)) 1615 return false; 1616 1617 return true; 1618 } 1619 1620 /** 1621 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1622 * @raw_edid: pointer to raw EDID block 1623 * @block: type of block to validate (0 for base, extension otherwise) 1624 * @print_bad_edid: if true, dump bad EDID blocks to the console 1625 * @edid_corrupt: if true, the header or checksum is invalid 1626 * 1627 * Validate a base or extension EDID block and optionally dump bad blocks to 1628 * the console. 1629 * 1630 * Return: True if the block is valid, false otherwise. 1631 */ 1632 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1633 bool *edid_corrupt) 1634 { 1635 u8 csum; 1636 struct edid *edid = (struct edid *)raw_edid; 1637 1638 if (WARN_ON(!raw_edid)) 1639 return false; 1640 1641 if (edid_fixup > 8 || edid_fixup < 0) 1642 edid_fixup = 6; 1643 1644 if (block == 0) { 1645 int score = drm_edid_header_is_valid(raw_edid); 1646 if (score == 8) { 1647 if (edid_corrupt) 1648 *edid_corrupt = false; 1649 } else if (score >= edid_fixup) { 1650 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1651 * The corrupt flag needs to be set here otherwise, the 1652 * fix-up code here will correct the problem, the 1653 * checksum is correct and the test fails 1654 */ 1655 if (edid_corrupt) 1656 *edid_corrupt = true; 1657 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1658 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1659 } else { 1660 if (edid_corrupt) 1661 *edid_corrupt = true; 1662 goto bad; 1663 } 1664 } 1665 1666 csum = drm_edid_block_checksum(raw_edid); 1667 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1668 if (edid_corrupt) 1669 *edid_corrupt = true; 1670 1671 /* allow CEA to slide through, switches mangle this */ 1672 if (raw_edid[0] == CEA_EXT) { 1673 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1674 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1675 } else { 1676 if (print_bad_edid) 1677 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1678 1679 goto bad; 1680 } 1681 } 1682 1683 /* per-block-type checks */ 1684 switch (raw_edid[0]) { 1685 case 0: /* base */ 1686 if (edid->version != 1) { 1687 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1688 goto bad; 1689 } 1690 1691 if (edid->revision > 4) 1692 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1693 break; 1694 1695 default: 1696 break; 1697 } 1698 1699 return true; 1700 1701 bad: 1702 if (print_bad_edid) { 1703 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1704 pr_notice("EDID block is all zeroes\n"); 1705 } else { 1706 pr_notice("Raw EDID:\n"); 1707 print_hex_dump(KERN_NOTICE, 1708 " \t", DUMP_PREFIX_NONE, 16, 1, 1709 raw_edid, EDID_LENGTH, false); 1710 } 1711 } 1712 return false; 1713 } 1714 EXPORT_SYMBOL(drm_edid_block_valid); 1715 1716 /** 1717 * drm_edid_is_valid - sanity check EDID data 1718 * @edid: EDID data 1719 * 1720 * Sanity-check an entire EDID record (including extensions) 1721 * 1722 * Return: True if the EDID data is valid, false otherwise. 1723 */ 1724 bool drm_edid_is_valid(struct edid *edid) 1725 { 1726 int i; 1727 u8 *raw = (u8 *)edid; 1728 1729 if (!edid) 1730 return false; 1731 1732 for (i = 0; i <= edid->extensions; i++) 1733 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1734 return false; 1735 1736 return true; 1737 } 1738 EXPORT_SYMBOL(drm_edid_is_valid); 1739 1740 #define DDC_SEGMENT_ADDR 0x30 1741 /** 1742 * drm_do_probe_ddc_edid() - get EDID information via I2C 1743 * @data: I2C device adapter 1744 * @buf: EDID data buffer to be filled 1745 * @block: 128 byte EDID block to start fetching from 1746 * @len: EDID data buffer length to fetch 1747 * 1748 * Try to fetch EDID information by calling I2C driver functions. 1749 * 1750 * Return: 0 on success or -1 on failure. 1751 */ 1752 static int 1753 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1754 { 1755 struct i2c_adapter *adapter = data; 1756 unsigned char start = block * EDID_LENGTH; 1757 unsigned char segment = block >> 1; 1758 unsigned char xfers = segment ? 3 : 2; 1759 int ret, retries = 5; 1760 1761 /* 1762 * The core I2C driver will automatically retry the transfer if the 1763 * adapter reports EAGAIN. However, we find that bit-banging transfers 1764 * are susceptible to errors under a heavily loaded machine and 1765 * generate spurious NAKs and timeouts. Retrying the transfer 1766 * of the individual block a few times seems to overcome this. 1767 */ 1768 do { 1769 struct i2c_msg msgs[] = { 1770 { 1771 .addr = DDC_SEGMENT_ADDR, 1772 .flags = 0, 1773 .len = 1, 1774 .buf = &segment, 1775 }, { 1776 .addr = DDC_ADDR, 1777 .flags = 0, 1778 .len = 1, 1779 .buf = &start, 1780 }, { 1781 .addr = DDC_ADDR, 1782 .flags = I2C_M_RD, 1783 .len = len, 1784 .buf = buf, 1785 } 1786 }; 1787 1788 /* 1789 * Avoid sending the segment addr to not upset non-compliant 1790 * DDC monitors. 1791 */ 1792 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1793 1794 if (ret == -ENXIO) { 1795 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1796 adapter->name); 1797 break; 1798 } 1799 } while (ret != xfers && --retries); 1800 1801 return ret == xfers ? 0 : -1; 1802 } 1803 1804 static void connector_bad_edid(struct drm_connector *connector, 1805 u8 *edid, int num_blocks) 1806 { 1807 int i; 1808 u8 num_of_ext = edid[0x7e]; 1809 1810 /* Calculate real checksum for the last edid extension block data */ 1811 connector->real_edid_checksum = 1812 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1813 1814 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1815 return; 1816 1817 dev_warn(connector->dev->dev, 1818 "%s: EDID is invalid:\n", 1819 connector->name); 1820 for (i = 0; i < num_blocks; i++) { 1821 u8 *block = edid + i * EDID_LENGTH; 1822 char prefix[20]; 1823 1824 if (drm_edid_is_zero(block, EDID_LENGTH)) 1825 sprintf(prefix, "\t[%02x] ZERO ", i); 1826 else if (!drm_edid_block_valid(block, i, false, NULL)) 1827 sprintf(prefix, "\t[%02x] BAD ", i); 1828 else 1829 sprintf(prefix, "\t[%02x] GOOD ", i); 1830 1831 print_hex_dump(KERN_WARNING, 1832 prefix, DUMP_PREFIX_NONE, 16, 1, 1833 block, EDID_LENGTH, false); 1834 } 1835 } 1836 1837 /* Get override or firmware EDID */ 1838 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1839 { 1840 struct edid *override = NULL; 1841 1842 if (connector->override_edid) 1843 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1844 1845 if (!override) 1846 override = drm_load_edid_firmware(connector); 1847 1848 return IS_ERR(override) ? NULL : override; 1849 } 1850 1851 /** 1852 * drm_add_override_edid_modes - add modes from override/firmware EDID 1853 * @connector: connector we're probing 1854 * 1855 * Add modes from the override/firmware EDID, if available. Only to be used from 1856 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1857 * failed during drm_get_edid() and caused the override/firmware EDID to be 1858 * skipped. 1859 * 1860 * Return: The number of modes added or 0 if we couldn't find any. 1861 */ 1862 int drm_add_override_edid_modes(struct drm_connector *connector) 1863 { 1864 struct edid *override; 1865 int num_modes = 0; 1866 1867 override = drm_get_override_edid(connector); 1868 if (override) { 1869 drm_connector_update_edid_property(connector, override); 1870 num_modes = drm_add_edid_modes(connector, override); 1871 kfree(override); 1872 1873 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1874 connector->base.id, connector->name, num_modes); 1875 } 1876 1877 return num_modes; 1878 } 1879 EXPORT_SYMBOL(drm_add_override_edid_modes); 1880 1881 /** 1882 * drm_do_get_edid - get EDID data using a custom EDID block read function 1883 * @connector: connector we're probing 1884 * @get_edid_block: EDID block read function 1885 * @data: private data passed to the block read function 1886 * 1887 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1888 * exposes a different interface to read EDID blocks this function can be used 1889 * to get EDID data using a custom block read function. 1890 * 1891 * As in the general case the DDC bus is accessible by the kernel at the I2C 1892 * level, drivers must make all reasonable efforts to expose it as an I2C 1893 * adapter and use drm_get_edid() instead of abusing this function. 1894 * 1895 * The EDID may be overridden using debugfs override_edid or firmare EDID 1896 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1897 * order. Having either of them bypasses actual EDID reads. 1898 * 1899 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1900 */ 1901 struct edid *drm_do_get_edid(struct drm_connector *connector, 1902 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1903 size_t len), 1904 void *data) 1905 { 1906 int i, j = 0, valid_extensions = 0; 1907 u8 *edid, *new; 1908 struct edid *override; 1909 1910 override = drm_get_override_edid(connector); 1911 if (override) 1912 return override; 1913 1914 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1915 return NULL; 1916 1917 /* base block fetch */ 1918 for (i = 0; i < 4; i++) { 1919 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1920 goto out; 1921 if (drm_edid_block_valid(edid, 0, false, 1922 &connector->edid_corrupt)) 1923 break; 1924 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1925 connector->null_edid_counter++; 1926 goto carp; 1927 } 1928 } 1929 if (i == 4) 1930 goto carp; 1931 1932 /* if there's no extensions, we're done */ 1933 valid_extensions = edid[0x7e]; 1934 if (valid_extensions == 0) 1935 return (struct edid *)edid; 1936 1937 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1938 if (!new) 1939 goto out; 1940 edid = new; 1941 1942 for (j = 1; j <= edid[0x7e]; j++) { 1943 u8 *block = edid + j * EDID_LENGTH; 1944 1945 for (i = 0; i < 4; i++) { 1946 if (get_edid_block(data, block, j, EDID_LENGTH)) 1947 goto out; 1948 if (drm_edid_block_valid(block, j, false, NULL)) 1949 break; 1950 } 1951 1952 if (i == 4) 1953 valid_extensions--; 1954 } 1955 1956 if (valid_extensions != edid[0x7e]) { 1957 u8 *base; 1958 1959 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1960 1961 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1962 edid[0x7e] = valid_extensions; 1963 1964 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1965 GFP_KERNEL); 1966 if (!new) 1967 goto out; 1968 1969 base = new; 1970 for (i = 0; i <= edid[0x7e]; i++) { 1971 u8 *block = edid + i * EDID_LENGTH; 1972 1973 if (!drm_edid_block_valid(block, i, false, NULL)) 1974 continue; 1975 1976 memcpy(base, block, EDID_LENGTH); 1977 base += EDID_LENGTH; 1978 } 1979 1980 kfree(edid); 1981 edid = new; 1982 } 1983 1984 return (struct edid *)edid; 1985 1986 carp: 1987 connector_bad_edid(connector, edid, 1); 1988 out: 1989 kfree(edid); 1990 return NULL; 1991 } 1992 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1993 1994 /** 1995 * drm_probe_ddc() - probe DDC presence 1996 * @adapter: I2C adapter to probe 1997 * 1998 * Return: True on success, false on failure. 1999 */ 2000 bool 2001 drm_probe_ddc(struct i2c_adapter *adapter) 2002 { 2003 unsigned char out; 2004 2005 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2006 } 2007 EXPORT_SYMBOL(drm_probe_ddc); 2008 2009 /** 2010 * drm_get_edid - get EDID data, if available 2011 * @connector: connector we're probing 2012 * @adapter: I2C adapter to use for DDC 2013 * 2014 * Poke the given I2C channel to grab EDID data if possible. If found, 2015 * attach it to the connector. 2016 * 2017 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2018 */ 2019 struct edid *drm_get_edid(struct drm_connector *connector, 2020 struct i2c_adapter *adapter) 2021 { 2022 struct edid *edid; 2023 2024 if (connector->force == DRM_FORCE_OFF) 2025 return NULL; 2026 2027 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2028 return NULL; 2029 2030 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2031 if (edid) 2032 drm_get_displayid(connector, edid); 2033 return edid; 2034 } 2035 EXPORT_SYMBOL(drm_get_edid); 2036 2037 /** 2038 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2039 * @connector: connector we're probing 2040 * @adapter: I2C adapter to use for DDC 2041 * 2042 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2043 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2044 * switch DDC to the GPU which is retrieving EDID. 2045 * 2046 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2047 */ 2048 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2049 struct i2c_adapter *adapter) 2050 { 2051 struct pci_dev *pdev = connector->dev->pdev; 2052 struct edid *edid; 2053 2054 vga_switcheroo_lock_ddc(pdev); 2055 edid = drm_get_edid(connector, adapter); 2056 vga_switcheroo_unlock_ddc(pdev); 2057 2058 return edid; 2059 } 2060 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2061 2062 /** 2063 * drm_edid_duplicate - duplicate an EDID and the extensions 2064 * @edid: EDID to duplicate 2065 * 2066 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2067 */ 2068 struct edid *drm_edid_duplicate(const struct edid *edid) 2069 { 2070 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2071 } 2072 EXPORT_SYMBOL(drm_edid_duplicate); 2073 2074 /*** EDID parsing ***/ 2075 2076 /** 2077 * edid_vendor - match a string against EDID's obfuscated vendor field 2078 * @edid: EDID to match 2079 * @vendor: vendor string 2080 * 2081 * Returns true if @vendor is in @edid, false otherwise 2082 */ 2083 static bool edid_vendor(const struct edid *edid, const char *vendor) 2084 { 2085 char edid_vendor[3]; 2086 2087 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2088 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2089 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2090 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2091 2092 return !strncmp(edid_vendor, vendor, 3); 2093 } 2094 2095 /** 2096 * edid_get_quirks - return quirk flags for a given EDID 2097 * @edid: EDID to process 2098 * 2099 * This tells subsequent routines what fixes they need to apply. 2100 */ 2101 static u32 edid_get_quirks(const struct edid *edid) 2102 { 2103 const struct edid_quirk *quirk; 2104 int i; 2105 2106 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2107 quirk = &edid_quirk_list[i]; 2108 2109 if (edid_vendor(edid, quirk->vendor) && 2110 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2111 return quirk->quirks; 2112 } 2113 2114 return 0; 2115 } 2116 2117 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2118 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2119 2120 /** 2121 * edid_fixup_preferred - set preferred modes based on quirk list 2122 * @connector: has mode list to fix up 2123 * @quirks: quirks list 2124 * 2125 * Walk the mode list for @connector, clearing the preferred status 2126 * on existing modes and setting it anew for the right mode ala @quirks. 2127 */ 2128 static void edid_fixup_preferred(struct drm_connector *connector, 2129 u32 quirks) 2130 { 2131 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2132 int target_refresh = 0; 2133 int cur_vrefresh, preferred_vrefresh; 2134 2135 if (list_empty(&connector->probed_modes)) 2136 return; 2137 2138 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2139 target_refresh = 60; 2140 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2141 target_refresh = 75; 2142 2143 preferred_mode = list_first_entry(&connector->probed_modes, 2144 struct drm_display_mode, head); 2145 2146 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2147 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2148 2149 if (cur_mode == preferred_mode) 2150 continue; 2151 2152 /* Largest mode is preferred */ 2153 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2154 preferred_mode = cur_mode; 2155 2156 cur_vrefresh = cur_mode->vrefresh ? 2157 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 2158 preferred_vrefresh = preferred_mode->vrefresh ? 2159 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 2160 /* At a given size, try to get closest to target refresh */ 2161 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2162 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2163 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2164 preferred_mode = cur_mode; 2165 } 2166 } 2167 2168 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2169 } 2170 2171 static bool 2172 mode_is_rb(const struct drm_display_mode *mode) 2173 { 2174 return (mode->htotal - mode->hdisplay == 160) && 2175 (mode->hsync_end - mode->hdisplay == 80) && 2176 (mode->hsync_end - mode->hsync_start == 32) && 2177 (mode->vsync_start - mode->vdisplay == 3); 2178 } 2179 2180 /* 2181 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2182 * @dev: Device to duplicate against 2183 * @hsize: Mode width 2184 * @vsize: Mode height 2185 * @fresh: Mode refresh rate 2186 * @rb: Mode reduced-blanking-ness 2187 * 2188 * Walk the DMT mode list looking for a match for the given parameters. 2189 * 2190 * Return: A newly allocated copy of the mode, or NULL if not found. 2191 */ 2192 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2193 int hsize, int vsize, int fresh, 2194 bool rb) 2195 { 2196 int i; 2197 2198 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2199 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2200 if (hsize != ptr->hdisplay) 2201 continue; 2202 if (vsize != ptr->vdisplay) 2203 continue; 2204 if (fresh != drm_mode_vrefresh(ptr)) 2205 continue; 2206 if (rb != mode_is_rb(ptr)) 2207 continue; 2208 2209 return drm_mode_duplicate(dev, ptr); 2210 } 2211 2212 return NULL; 2213 } 2214 EXPORT_SYMBOL(drm_mode_find_dmt); 2215 2216 static bool is_display_descriptor(const u8 d[18], u8 tag) 2217 { 2218 return d[0] == 0x00 && d[1] == 0x00 && 2219 d[2] == 0x00 && d[3] == tag; 2220 } 2221 2222 static bool is_detailed_timing_descriptor(const u8 d[18]) 2223 { 2224 return d[0] != 0x00 || d[1] != 0x00; 2225 } 2226 2227 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2228 2229 static void 2230 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2231 { 2232 int i, n; 2233 u8 d = ext[0x02]; 2234 u8 *det_base = ext + d; 2235 2236 if (d < 4 || d > 127) 2237 return; 2238 2239 n = (127 - d) / 18; 2240 for (i = 0; i < n; i++) 2241 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2242 } 2243 2244 static void 2245 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2246 { 2247 unsigned int i, n = min((int)ext[0x02], 6); 2248 u8 *det_base = ext + 5; 2249 2250 if (ext[0x01] != 1) 2251 return; /* unknown version */ 2252 2253 for (i = 0; i < n; i++) 2254 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2255 } 2256 2257 static void 2258 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2259 { 2260 int i; 2261 struct edid *edid = (struct edid *)raw_edid; 2262 2263 if (edid == NULL) 2264 return; 2265 2266 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2267 cb(&(edid->detailed_timings[i]), closure); 2268 2269 for (i = 1; i <= raw_edid[0x7e]; i++) { 2270 u8 *ext = raw_edid + (i * EDID_LENGTH); 2271 switch (*ext) { 2272 case CEA_EXT: 2273 cea_for_each_detailed_block(ext, cb, closure); 2274 break; 2275 case VTB_EXT: 2276 vtb_for_each_detailed_block(ext, cb, closure); 2277 break; 2278 default: 2279 break; 2280 } 2281 } 2282 } 2283 2284 static void 2285 is_rb(struct detailed_timing *t, void *data) 2286 { 2287 u8 *r = (u8 *)t; 2288 2289 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2290 return; 2291 2292 if (r[15] & 0x10) 2293 *(bool *)data = true; 2294 } 2295 2296 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2297 static bool 2298 drm_monitor_supports_rb(struct edid *edid) 2299 { 2300 if (edid->revision >= 4) { 2301 bool ret = false; 2302 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2303 return ret; 2304 } 2305 2306 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2307 } 2308 2309 static void 2310 find_gtf2(struct detailed_timing *t, void *data) 2311 { 2312 u8 *r = (u8 *)t; 2313 2314 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2315 return; 2316 2317 if (r[10] == 0x02) 2318 *(u8 **)data = r; 2319 } 2320 2321 /* Secondary GTF curve kicks in above some break frequency */ 2322 static int 2323 drm_gtf2_hbreak(struct edid *edid) 2324 { 2325 u8 *r = NULL; 2326 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2327 return r ? (r[12] * 2) : 0; 2328 } 2329 2330 static int 2331 drm_gtf2_2c(struct edid *edid) 2332 { 2333 u8 *r = NULL; 2334 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2335 return r ? r[13] : 0; 2336 } 2337 2338 static int 2339 drm_gtf2_m(struct edid *edid) 2340 { 2341 u8 *r = NULL; 2342 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2343 return r ? (r[15] << 8) + r[14] : 0; 2344 } 2345 2346 static int 2347 drm_gtf2_k(struct edid *edid) 2348 { 2349 u8 *r = NULL; 2350 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2351 return r ? r[16] : 0; 2352 } 2353 2354 static int 2355 drm_gtf2_2j(struct edid *edid) 2356 { 2357 u8 *r = NULL; 2358 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2359 return r ? r[17] : 0; 2360 } 2361 2362 /** 2363 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2364 * @edid: EDID block to scan 2365 */ 2366 static int standard_timing_level(struct edid *edid) 2367 { 2368 if (edid->revision >= 2) { 2369 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2370 return LEVEL_CVT; 2371 if (drm_gtf2_hbreak(edid)) 2372 return LEVEL_GTF2; 2373 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2374 return LEVEL_GTF; 2375 } 2376 return LEVEL_DMT; 2377 } 2378 2379 /* 2380 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2381 * monitors fill with ascii space (0x20) instead. 2382 */ 2383 static int 2384 bad_std_timing(u8 a, u8 b) 2385 { 2386 return (a == 0x00 && b == 0x00) || 2387 (a == 0x01 && b == 0x01) || 2388 (a == 0x20 && b == 0x20); 2389 } 2390 2391 /** 2392 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2393 * @connector: connector of for the EDID block 2394 * @edid: EDID block to scan 2395 * @t: standard timing params 2396 * 2397 * Take the standard timing params (in this case width, aspect, and refresh) 2398 * and convert them into a real mode using CVT/GTF/DMT. 2399 */ 2400 static struct drm_display_mode * 2401 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2402 struct std_timing *t) 2403 { 2404 struct drm_device *dev = connector->dev; 2405 struct drm_display_mode *m, *mode = NULL; 2406 int hsize, vsize; 2407 int vrefresh_rate; 2408 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2409 >> EDID_TIMING_ASPECT_SHIFT; 2410 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2411 >> EDID_TIMING_VFREQ_SHIFT; 2412 int timing_level = standard_timing_level(edid); 2413 2414 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2415 return NULL; 2416 2417 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2418 hsize = t->hsize * 8 + 248; 2419 /* vrefresh_rate = vfreq + 60 */ 2420 vrefresh_rate = vfreq + 60; 2421 /* the vdisplay is calculated based on the aspect ratio */ 2422 if (aspect_ratio == 0) { 2423 if (edid->revision < 3) 2424 vsize = hsize; 2425 else 2426 vsize = (hsize * 10) / 16; 2427 } else if (aspect_ratio == 1) 2428 vsize = (hsize * 3) / 4; 2429 else if (aspect_ratio == 2) 2430 vsize = (hsize * 4) / 5; 2431 else 2432 vsize = (hsize * 9) / 16; 2433 2434 /* HDTV hack, part 1 */ 2435 if (vrefresh_rate == 60 && 2436 ((hsize == 1360 && vsize == 765) || 2437 (hsize == 1368 && vsize == 769))) { 2438 hsize = 1366; 2439 vsize = 768; 2440 } 2441 2442 /* 2443 * If this connector already has a mode for this size and refresh 2444 * rate (because it came from detailed or CVT info), use that 2445 * instead. This way we don't have to guess at interlace or 2446 * reduced blanking. 2447 */ 2448 list_for_each_entry(m, &connector->probed_modes, head) 2449 if (m->hdisplay == hsize && m->vdisplay == vsize && 2450 drm_mode_vrefresh(m) == vrefresh_rate) 2451 return NULL; 2452 2453 /* HDTV hack, part 2 */ 2454 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2455 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2456 false); 2457 if (!mode) 2458 return NULL; 2459 mode->hdisplay = 1366; 2460 mode->hsync_start = mode->hsync_start - 1; 2461 mode->hsync_end = mode->hsync_end - 1; 2462 return mode; 2463 } 2464 2465 /* check whether it can be found in default mode table */ 2466 if (drm_monitor_supports_rb(edid)) { 2467 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2468 true); 2469 if (mode) 2470 return mode; 2471 } 2472 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2473 if (mode) 2474 return mode; 2475 2476 /* okay, generate it */ 2477 switch (timing_level) { 2478 case LEVEL_DMT: 2479 break; 2480 case LEVEL_GTF: 2481 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2482 break; 2483 case LEVEL_GTF2: 2484 /* 2485 * This is potentially wrong if there's ever a monitor with 2486 * more than one ranges section, each claiming a different 2487 * secondary GTF curve. Please don't do that. 2488 */ 2489 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2490 if (!mode) 2491 return NULL; 2492 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2493 drm_mode_destroy(dev, mode); 2494 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2495 vrefresh_rate, 0, 0, 2496 drm_gtf2_m(edid), 2497 drm_gtf2_2c(edid), 2498 drm_gtf2_k(edid), 2499 drm_gtf2_2j(edid)); 2500 } 2501 break; 2502 case LEVEL_CVT: 2503 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2504 false); 2505 break; 2506 } 2507 return mode; 2508 } 2509 2510 /* 2511 * EDID is delightfully ambiguous about how interlaced modes are to be 2512 * encoded. Our internal representation is of frame height, but some 2513 * HDTV detailed timings are encoded as field height. 2514 * 2515 * The format list here is from CEA, in frame size. Technically we 2516 * should be checking refresh rate too. Whatever. 2517 */ 2518 static void 2519 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2520 struct detailed_pixel_timing *pt) 2521 { 2522 int i; 2523 static const struct { 2524 int w, h; 2525 } cea_interlaced[] = { 2526 { 1920, 1080 }, 2527 { 720, 480 }, 2528 { 1440, 480 }, 2529 { 2880, 480 }, 2530 { 720, 576 }, 2531 { 1440, 576 }, 2532 { 2880, 576 }, 2533 }; 2534 2535 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2536 return; 2537 2538 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2539 if ((mode->hdisplay == cea_interlaced[i].w) && 2540 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2541 mode->vdisplay *= 2; 2542 mode->vsync_start *= 2; 2543 mode->vsync_end *= 2; 2544 mode->vtotal *= 2; 2545 mode->vtotal |= 1; 2546 } 2547 } 2548 2549 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2550 } 2551 2552 /** 2553 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2554 * @dev: DRM device (needed to create new mode) 2555 * @edid: EDID block 2556 * @timing: EDID detailed timing info 2557 * @quirks: quirks to apply 2558 * 2559 * An EDID detailed timing block contains enough info for us to create and 2560 * return a new struct drm_display_mode. 2561 */ 2562 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2563 struct edid *edid, 2564 struct detailed_timing *timing, 2565 u32 quirks) 2566 { 2567 struct drm_display_mode *mode; 2568 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2569 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2570 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2571 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2572 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2573 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2574 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2575 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2576 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2577 2578 /* ignore tiny modes */ 2579 if (hactive < 64 || vactive < 64) 2580 return NULL; 2581 2582 if (pt->misc & DRM_EDID_PT_STEREO) { 2583 DRM_DEBUG_KMS("stereo mode not supported\n"); 2584 return NULL; 2585 } 2586 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2587 DRM_DEBUG_KMS("composite sync not supported\n"); 2588 } 2589 2590 /* it is incorrect if hsync/vsync width is zero */ 2591 if (!hsync_pulse_width || !vsync_pulse_width) { 2592 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2593 "Wrong Hsync/Vsync pulse width\n"); 2594 return NULL; 2595 } 2596 2597 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2598 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2599 if (!mode) 2600 return NULL; 2601 2602 goto set_size; 2603 } 2604 2605 mode = drm_mode_create(dev); 2606 if (!mode) 2607 return NULL; 2608 2609 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2610 timing->pixel_clock = cpu_to_le16(1088); 2611 2612 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2613 2614 mode->hdisplay = hactive; 2615 mode->hsync_start = mode->hdisplay + hsync_offset; 2616 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2617 mode->htotal = mode->hdisplay + hblank; 2618 2619 mode->vdisplay = vactive; 2620 mode->vsync_start = mode->vdisplay + vsync_offset; 2621 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2622 mode->vtotal = mode->vdisplay + vblank; 2623 2624 /* Some EDIDs have bogus h/vtotal values */ 2625 if (mode->hsync_end > mode->htotal) 2626 mode->htotal = mode->hsync_end + 1; 2627 if (mode->vsync_end > mode->vtotal) 2628 mode->vtotal = mode->vsync_end + 1; 2629 2630 drm_mode_do_interlace_quirk(mode, pt); 2631 2632 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2633 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2634 } 2635 2636 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2637 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2638 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2639 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2640 2641 set_size: 2642 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2643 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2644 2645 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2646 mode->width_mm *= 10; 2647 mode->height_mm *= 10; 2648 } 2649 2650 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2651 mode->width_mm = edid->width_cm * 10; 2652 mode->height_mm = edid->height_cm * 10; 2653 } 2654 2655 mode->type = DRM_MODE_TYPE_DRIVER; 2656 mode->vrefresh = drm_mode_vrefresh(mode); 2657 drm_mode_set_name(mode); 2658 2659 return mode; 2660 } 2661 2662 static bool 2663 mode_in_hsync_range(const struct drm_display_mode *mode, 2664 struct edid *edid, u8 *t) 2665 { 2666 int hsync, hmin, hmax; 2667 2668 hmin = t[7]; 2669 if (edid->revision >= 4) 2670 hmin += ((t[4] & 0x04) ? 255 : 0); 2671 hmax = t[8]; 2672 if (edid->revision >= 4) 2673 hmax += ((t[4] & 0x08) ? 255 : 0); 2674 hsync = drm_mode_hsync(mode); 2675 2676 return (hsync <= hmax && hsync >= hmin); 2677 } 2678 2679 static bool 2680 mode_in_vsync_range(const struct drm_display_mode *mode, 2681 struct edid *edid, u8 *t) 2682 { 2683 int vsync, vmin, vmax; 2684 2685 vmin = t[5]; 2686 if (edid->revision >= 4) 2687 vmin += ((t[4] & 0x01) ? 255 : 0); 2688 vmax = t[6]; 2689 if (edid->revision >= 4) 2690 vmax += ((t[4] & 0x02) ? 255 : 0); 2691 vsync = drm_mode_vrefresh(mode); 2692 2693 return (vsync <= vmax && vsync >= vmin); 2694 } 2695 2696 static u32 2697 range_pixel_clock(struct edid *edid, u8 *t) 2698 { 2699 /* unspecified */ 2700 if (t[9] == 0 || t[9] == 255) 2701 return 0; 2702 2703 /* 1.4 with CVT support gives us real precision, yay */ 2704 if (edid->revision >= 4 && t[10] == 0x04) 2705 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2706 2707 /* 1.3 is pathetic, so fuzz up a bit */ 2708 return t[9] * 10000 + 5001; 2709 } 2710 2711 static bool 2712 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2713 struct detailed_timing *timing) 2714 { 2715 u32 max_clock; 2716 u8 *t = (u8 *)timing; 2717 2718 if (!mode_in_hsync_range(mode, edid, t)) 2719 return false; 2720 2721 if (!mode_in_vsync_range(mode, edid, t)) 2722 return false; 2723 2724 if ((max_clock = range_pixel_clock(edid, t))) 2725 if (mode->clock > max_clock) 2726 return false; 2727 2728 /* 1.4 max horizontal check */ 2729 if (edid->revision >= 4 && t[10] == 0x04) 2730 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2731 return false; 2732 2733 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2734 return false; 2735 2736 return true; 2737 } 2738 2739 static bool valid_inferred_mode(const struct drm_connector *connector, 2740 const struct drm_display_mode *mode) 2741 { 2742 const struct drm_display_mode *m; 2743 bool ok = false; 2744 2745 list_for_each_entry(m, &connector->probed_modes, head) { 2746 if (mode->hdisplay == m->hdisplay && 2747 mode->vdisplay == m->vdisplay && 2748 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2749 return false; /* duplicated */ 2750 if (mode->hdisplay <= m->hdisplay && 2751 mode->vdisplay <= m->vdisplay) 2752 ok = true; 2753 } 2754 return ok; 2755 } 2756 2757 static int 2758 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2759 struct detailed_timing *timing) 2760 { 2761 int i, modes = 0; 2762 struct drm_display_mode *newmode; 2763 struct drm_device *dev = connector->dev; 2764 2765 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2766 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2767 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2768 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2769 if (newmode) { 2770 drm_mode_probed_add(connector, newmode); 2771 modes++; 2772 } 2773 } 2774 } 2775 2776 return modes; 2777 } 2778 2779 /* fix up 1366x768 mode from 1368x768; 2780 * GFT/CVT can't express 1366 width which isn't dividable by 8 2781 */ 2782 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2783 { 2784 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2785 mode->hdisplay = 1366; 2786 mode->hsync_start--; 2787 mode->hsync_end--; 2788 drm_mode_set_name(mode); 2789 } 2790 } 2791 2792 static int 2793 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2794 struct detailed_timing *timing) 2795 { 2796 int i, modes = 0; 2797 struct drm_display_mode *newmode; 2798 struct drm_device *dev = connector->dev; 2799 2800 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2801 const struct minimode *m = &extra_modes[i]; 2802 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2803 if (!newmode) 2804 return modes; 2805 2806 drm_mode_fixup_1366x768(newmode); 2807 if (!mode_in_range(newmode, edid, timing) || 2808 !valid_inferred_mode(connector, newmode)) { 2809 drm_mode_destroy(dev, newmode); 2810 continue; 2811 } 2812 2813 drm_mode_probed_add(connector, newmode); 2814 modes++; 2815 } 2816 2817 return modes; 2818 } 2819 2820 static int 2821 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2822 struct detailed_timing *timing) 2823 { 2824 int i, modes = 0; 2825 struct drm_display_mode *newmode; 2826 struct drm_device *dev = connector->dev; 2827 bool rb = drm_monitor_supports_rb(edid); 2828 2829 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2830 const struct minimode *m = &extra_modes[i]; 2831 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2832 if (!newmode) 2833 return modes; 2834 2835 drm_mode_fixup_1366x768(newmode); 2836 if (!mode_in_range(newmode, edid, timing) || 2837 !valid_inferred_mode(connector, newmode)) { 2838 drm_mode_destroy(dev, newmode); 2839 continue; 2840 } 2841 2842 drm_mode_probed_add(connector, newmode); 2843 modes++; 2844 } 2845 2846 return modes; 2847 } 2848 2849 static void 2850 do_inferred_modes(struct detailed_timing *timing, void *c) 2851 { 2852 struct detailed_mode_closure *closure = c; 2853 struct detailed_non_pixel *data = &timing->data.other_data; 2854 struct detailed_data_monitor_range *range = &data->data.range; 2855 2856 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2857 return; 2858 2859 closure->modes += drm_dmt_modes_for_range(closure->connector, 2860 closure->edid, 2861 timing); 2862 2863 if (!version_greater(closure->edid, 1, 1)) 2864 return; /* GTF not defined yet */ 2865 2866 switch (range->flags) { 2867 case 0x02: /* secondary gtf, XXX could do more */ 2868 case 0x00: /* default gtf */ 2869 closure->modes += drm_gtf_modes_for_range(closure->connector, 2870 closure->edid, 2871 timing); 2872 break; 2873 case 0x04: /* cvt, only in 1.4+ */ 2874 if (!version_greater(closure->edid, 1, 3)) 2875 break; 2876 2877 closure->modes += drm_cvt_modes_for_range(closure->connector, 2878 closure->edid, 2879 timing); 2880 break; 2881 case 0x01: /* just the ranges, no formula */ 2882 default: 2883 break; 2884 } 2885 } 2886 2887 static int 2888 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2889 { 2890 struct detailed_mode_closure closure = { 2891 .connector = connector, 2892 .edid = edid, 2893 }; 2894 2895 if (version_greater(edid, 1, 0)) 2896 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2897 &closure); 2898 2899 return closure.modes; 2900 } 2901 2902 static int 2903 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2904 { 2905 int i, j, m, modes = 0; 2906 struct drm_display_mode *mode; 2907 u8 *est = ((u8 *)timing) + 6; 2908 2909 for (i = 0; i < 6; i++) { 2910 for (j = 7; j >= 0; j--) { 2911 m = (i * 8) + (7 - j); 2912 if (m >= ARRAY_SIZE(est3_modes)) 2913 break; 2914 if (est[i] & (1 << j)) { 2915 mode = drm_mode_find_dmt(connector->dev, 2916 est3_modes[m].w, 2917 est3_modes[m].h, 2918 est3_modes[m].r, 2919 est3_modes[m].rb); 2920 if (mode) { 2921 drm_mode_probed_add(connector, mode); 2922 modes++; 2923 } 2924 } 2925 } 2926 } 2927 2928 return modes; 2929 } 2930 2931 static void 2932 do_established_modes(struct detailed_timing *timing, void *c) 2933 { 2934 struct detailed_mode_closure *closure = c; 2935 2936 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2937 return; 2938 2939 closure->modes += drm_est3_modes(closure->connector, timing); 2940 } 2941 2942 /** 2943 * add_established_modes - get est. modes from EDID and add them 2944 * @connector: connector to add mode(s) to 2945 * @edid: EDID block to scan 2946 * 2947 * Each EDID block contains a bitmap of the supported "established modes" list 2948 * (defined above). Tease them out and add them to the global modes list. 2949 */ 2950 static int 2951 add_established_modes(struct drm_connector *connector, struct edid *edid) 2952 { 2953 struct drm_device *dev = connector->dev; 2954 unsigned long est_bits = edid->established_timings.t1 | 2955 (edid->established_timings.t2 << 8) | 2956 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2957 int i, modes = 0; 2958 struct detailed_mode_closure closure = { 2959 .connector = connector, 2960 .edid = edid, 2961 }; 2962 2963 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2964 if (est_bits & (1<<i)) { 2965 struct drm_display_mode *newmode; 2966 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2967 if (newmode) { 2968 drm_mode_probed_add(connector, newmode); 2969 modes++; 2970 } 2971 } 2972 } 2973 2974 if (version_greater(edid, 1, 0)) 2975 drm_for_each_detailed_block((u8 *)edid, 2976 do_established_modes, &closure); 2977 2978 return modes + closure.modes; 2979 } 2980 2981 static void 2982 do_standard_modes(struct detailed_timing *timing, void *c) 2983 { 2984 struct detailed_mode_closure *closure = c; 2985 struct detailed_non_pixel *data = &timing->data.other_data; 2986 struct drm_connector *connector = closure->connector; 2987 struct edid *edid = closure->edid; 2988 int i; 2989 2990 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 2991 return; 2992 2993 for (i = 0; i < 6; i++) { 2994 struct std_timing *std = &data->data.timings[i]; 2995 struct drm_display_mode *newmode; 2996 2997 newmode = drm_mode_std(connector, edid, std); 2998 if (newmode) { 2999 drm_mode_probed_add(connector, newmode); 3000 closure->modes++; 3001 } 3002 } 3003 } 3004 3005 /** 3006 * add_standard_modes - get std. modes from EDID and add them 3007 * @connector: connector to add mode(s) to 3008 * @edid: EDID block to scan 3009 * 3010 * Standard modes can be calculated using the appropriate standard (DMT, 3011 * GTF or CVT. Grab them from @edid and add them to the list. 3012 */ 3013 static int 3014 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3015 { 3016 int i, modes = 0; 3017 struct detailed_mode_closure closure = { 3018 .connector = connector, 3019 .edid = edid, 3020 }; 3021 3022 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3023 struct drm_display_mode *newmode; 3024 3025 newmode = drm_mode_std(connector, edid, 3026 &edid->standard_timings[i]); 3027 if (newmode) { 3028 drm_mode_probed_add(connector, newmode); 3029 modes++; 3030 } 3031 } 3032 3033 if (version_greater(edid, 1, 0)) 3034 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3035 &closure); 3036 3037 /* XXX should also look for standard codes in VTB blocks */ 3038 3039 return modes + closure.modes; 3040 } 3041 3042 static int drm_cvt_modes(struct drm_connector *connector, 3043 struct detailed_timing *timing) 3044 { 3045 int i, j, modes = 0; 3046 struct drm_display_mode *newmode; 3047 struct drm_device *dev = connector->dev; 3048 struct cvt_timing *cvt; 3049 const int rates[] = { 60, 85, 75, 60, 50 }; 3050 const u8 empty[3] = { 0, 0, 0 }; 3051 3052 for (i = 0; i < 4; i++) { 3053 int uninitialized_var(width), height; 3054 cvt = &(timing->data.other_data.data.cvt[i]); 3055 3056 if (!memcmp(cvt->code, empty, 3)) 3057 continue; 3058 3059 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3060 switch (cvt->code[1] & 0x0c) { 3061 case 0x00: 3062 width = height * 4 / 3; 3063 break; 3064 case 0x04: 3065 width = height * 16 / 9; 3066 break; 3067 case 0x08: 3068 width = height * 16 / 10; 3069 break; 3070 case 0x0c: 3071 width = height * 15 / 9; 3072 break; 3073 } 3074 3075 for (j = 1; j < 5; j++) { 3076 if (cvt->code[2] & (1 << j)) { 3077 newmode = drm_cvt_mode(dev, width, height, 3078 rates[j], j == 0, 3079 false, false); 3080 if (newmode) { 3081 drm_mode_probed_add(connector, newmode); 3082 modes++; 3083 } 3084 } 3085 } 3086 } 3087 3088 return modes; 3089 } 3090 3091 static void 3092 do_cvt_mode(struct detailed_timing *timing, void *c) 3093 { 3094 struct detailed_mode_closure *closure = c; 3095 3096 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3097 return; 3098 3099 closure->modes += drm_cvt_modes(closure->connector, timing); 3100 } 3101 3102 static int 3103 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3104 { 3105 struct detailed_mode_closure closure = { 3106 .connector = connector, 3107 .edid = edid, 3108 }; 3109 3110 if (version_greater(edid, 1, 2)) 3111 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3112 3113 /* XXX should also look for CVT codes in VTB blocks */ 3114 3115 return closure.modes; 3116 } 3117 3118 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3119 3120 static void 3121 do_detailed_mode(struct detailed_timing *timing, void *c) 3122 { 3123 struct detailed_mode_closure *closure = c; 3124 struct drm_display_mode *newmode; 3125 3126 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3127 return; 3128 3129 newmode = drm_mode_detailed(closure->connector->dev, 3130 closure->edid, timing, 3131 closure->quirks); 3132 if (!newmode) 3133 return; 3134 3135 if (closure->preferred) 3136 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3137 3138 /* 3139 * Detailed modes are limited to 10kHz pixel clock resolution, 3140 * so fix up anything that looks like CEA/HDMI mode, but the clock 3141 * is just slightly off. 3142 */ 3143 fixup_detailed_cea_mode_clock(newmode); 3144 3145 drm_mode_probed_add(closure->connector, newmode); 3146 closure->modes++; 3147 closure->preferred = false; 3148 } 3149 3150 /* 3151 * add_detailed_modes - Add modes from detailed timings 3152 * @connector: attached connector 3153 * @edid: EDID block to scan 3154 * @quirks: quirks to apply 3155 */ 3156 static int 3157 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3158 u32 quirks) 3159 { 3160 struct detailed_mode_closure closure = { 3161 .connector = connector, 3162 .edid = edid, 3163 .preferred = true, 3164 .quirks = quirks, 3165 }; 3166 3167 if (closure.preferred && !version_greater(edid, 1, 3)) 3168 closure.preferred = 3169 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3170 3171 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3172 3173 return closure.modes; 3174 } 3175 3176 #define AUDIO_BLOCK 0x01 3177 #define VIDEO_BLOCK 0x02 3178 #define VENDOR_BLOCK 0x03 3179 #define SPEAKER_BLOCK 0x04 3180 #define HDR_STATIC_METADATA_BLOCK 0x6 3181 #define USE_EXTENDED_TAG 0x07 3182 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3183 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3184 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3185 #define EDID_BASIC_AUDIO (1 << 6) 3186 #define EDID_CEA_YCRCB444 (1 << 5) 3187 #define EDID_CEA_YCRCB422 (1 << 4) 3188 #define EDID_CEA_VCDB_QS (1 << 6) 3189 3190 /* 3191 * Search EDID for CEA extension block. 3192 */ 3193 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3194 { 3195 u8 *edid_ext = NULL; 3196 int i; 3197 3198 /* No EDID or EDID extensions */ 3199 if (edid == NULL || edid->extensions == 0) 3200 return NULL; 3201 3202 /* Find CEA extension */ 3203 for (i = 0; i < edid->extensions; i++) { 3204 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3205 if (edid_ext[0] == ext_id) 3206 break; 3207 } 3208 3209 if (i == edid->extensions) 3210 return NULL; 3211 3212 return edid_ext; 3213 } 3214 3215 3216 static u8 *drm_find_displayid_extension(const struct edid *edid) 3217 { 3218 return drm_find_edid_extension(edid, DISPLAYID_EXT); 3219 } 3220 3221 static u8 *drm_find_cea_extension(const struct edid *edid) 3222 { 3223 int ret; 3224 int idx = 1; 3225 int length = EDID_LENGTH; 3226 struct displayid_block *block; 3227 u8 *cea; 3228 u8 *displayid; 3229 3230 /* Look for a top level CEA extension block */ 3231 cea = drm_find_edid_extension(edid, CEA_EXT); 3232 if (cea) 3233 return cea; 3234 3235 /* CEA blocks can also be found embedded in a DisplayID block */ 3236 displayid = drm_find_displayid_extension(edid); 3237 if (!displayid) 3238 return NULL; 3239 3240 ret = validate_displayid(displayid, length, idx); 3241 if (ret) 3242 return NULL; 3243 3244 idx += sizeof(struct displayid_hdr); 3245 for_each_displayid_db(displayid, block, idx, length) { 3246 if (block->tag == DATA_BLOCK_CTA) { 3247 cea = (u8 *)block; 3248 break; 3249 } 3250 } 3251 3252 return cea; 3253 } 3254 3255 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3256 { 3257 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3258 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3259 3260 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3261 return &edid_cea_modes_1[vic - 1]; 3262 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3263 return &edid_cea_modes_193[vic - 193]; 3264 return NULL; 3265 } 3266 3267 static u8 cea_num_vics(void) 3268 { 3269 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3270 } 3271 3272 static u8 cea_next_vic(u8 vic) 3273 { 3274 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3275 vic = 193; 3276 return vic; 3277 } 3278 3279 /* 3280 * Calculate the alternate clock for the CEA mode 3281 * (60Hz vs. 59.94Hz etc.) 3282 */ 3283 static unsigned int 3284 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3285 { 3286 unsigned int clock = cea_mode->clock; 3287 3288 if (cea_mode->vrefresh % 6 != 0) 3289 return clock; 3290 3291 /* 3292 * edid_cea_modes contains the 59.94Hz 3293 * variant for 240 and 480 line modes, 3294 * and the 60Hz variant otherwise. 3295 */ 3296 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3297 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3298 else 3299 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3300 3301 return clock; 3302 } 3303 3304 static bool 3305 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3306 { 3307 /* 3308 * For certain VICs the spec allows the vertical 3309 * front porch to vary by one or two lines. 3310 * 3311 * cea_modes[] stores the variant with the shortest 3312 * vertical front porch. We can adjust the mode to 3313 * get the other variants by simply increasing the 3314 * vertical front porch length. 3315 */ 3316 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3317 cea_mode_for_vic(9)->vtotal != 262 || 3318 cea_mode_for_vic(12)->vtotal != 262 || 3319 cea_mode_for_vic(13)->vtotal != 262 || 3320 cea_mode_for_vic(23)->vtotal != 312 || 3321 cea_mode_for_vic(24)->vtotal != 312 || 3322 cea_mode_for_vic(27)->vtotal != 312 || 3323 cea_mode_for_vic(28)->vtotal != 312); 3324 3325 if (((vic == 8 || vic == 9 || 3326 vic == 12 || vic == 13) && mode->vtotal < 263) || 3327 ((vic == 23 || vic == 24 || 3328 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3329 mode->vsync_start++; 3330 mode->vsync_end++; 3331 mode->vtotal++; 3332 3333 return true; 3334 } 3335 3336 return false; 3337 } 3338 3339 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3340 unsigned int clock_tolerance) 3341 { 3342 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3343 u8 vic; 3344 3345 if (!to_match->clock) 3346 return 0; 3347 3348 if (to_match->picture_aspect_ratio) 3349 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3350 3351 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3352 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3353 unsigned int clock1, clock2; 3354 3355 /* Check both 60Hz and 59.94Hz */ 3356 clock1 = cea_mode.clock; 3357 clock2 = cea_mode_alternate_clock(&cea_mode); 3358 3359 if (abs(to_match->clock - clock1) > clock_tolerance && 3360 abs(to_match->clock - clock2) > clock_tolerance) 3361 continue; 3362 3363 do { 3364 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3365 return vic; 3366 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3367 } 3368 3369 return 0; 3370 } 3371 3372 /** 3373 * drm_match_cea_mode - look for a CEA mode matching given mode 3374 * @to_match: display mode 3375 * 3376 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3377 * mode. 3378 */ 3379 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3380 { 3381 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3382 u8 vic; 3383 3384 if (!to_match->clock) 3385 return 0; 3386 3387 if (to_match->picture_aspect_ratio) 3388 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3389 3390 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3391 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3392 unsigned int clock1, clock2; 3393 3394 /* Check both 60Hz and 59.94Hz */ 3395 clock1 = cea_mode.clock; 3396 clock2 = cea_mode_alternate_clock(&cea_mode); 3397 3398 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3399 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3400 continue; 3401 3402 do { 3403 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3404 return vic; 3405 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3406 } 3407 3408 return 0; 3409 } 3410 EXPORT_SYMBOL(drm_match_cea_mode); 3411 3412 static bool drm_valid_cea_vic(u8 vic) 3413 { 3414 return cea_mode_for_vic(vic) != NULL; 3415 } 3416 3417 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3418 { 3419 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3420 3421 if (mode) 3422 return mode->picture_aspect_ratio; 3423 3424 return HDMI_PICTURE_ASPECT_NONE; 3425 } 3426 3427 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3428 { 3429 return edid_4k_modes[video_code].picture_aspect_ratio; 3430 } 3431 3432 /* 3433 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3434 * specific block). 3435 */ 3436 static unsigned int 3437 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3438 { 3439 return cea_mode_alternate_clock(hdmi_mode); 3440 } 3441 3442 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3443 unsigned int clock_tolerance) 3444 { 3445 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3446 u8 vic; 3447 3448 if (!to_match->clock) 3449 return 0; 3450 3451 if (to_match->picture_aspect_ratio) 3452 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3453 3454 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3455 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3456 unsigned int clock1, clock2; 3457 3458 /* Make sure to also match alternate clocks */ 3459 clock1 = hdmi_mode->clock; 3460 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3461 3462 if (abs(to_match->clock - clock1) > clock_tolerance && 3463 abs(to_match->clock - clock2) > clock_tolerance) 3464 continue; 3465 3466 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3467 return vic; 3468 } 3469 3470 return 0; 3471 } 3472 3473 /* 3474 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3475 * @to_match: display mode 3476 * 3477 * An HDMI mode is one defined in the HDMI vendor specific block. 3478 * 3479 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3480 */ 3481 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3482 { 3483 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3484 u8 vic; 3485 3486 if (!to_match->clock) 3487 return 0; 3488 3489 if (to_match->picture_aspect_ratio) 3490 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3491 3492 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3493 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3494 unsigned int clock1, clock2; 3495 3496 /* Make sure to also match alternate clocks */ 3497 clock1 = hdmi_mode->clock; 3498 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3499 3500 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3501 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3502 drm_mode_match(to_match, hdmi_mode, match_flags)) 3503 return vic; 3504 } 3505 return 0; 3506 } 3507 3508 static bool drm_valid_hdmi_vic(u8 vic) 3509 { 3510 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3511 } 3512 3513 static int 3514 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3515 { 3516 struct drm_device *dev = connector->dev; 3517 struct drm_display_mode *mode, *tmp; 3518 LIST_HEAD(list); 3519 int modes = 0; 3520 3521 /* Don't add CEA modes if the CEA extension block is missing */ 3522 if (!drm_find_cea_extension(edid)) 3523 return 0; 3524 3525 /* 3526 * Go through all probed modes and create a new mode 3527 * with the alternate clock for certain CEA modes. 3528 */ 3529 list_for_each_entry(mode, &connector->probed_modes, head) { 3530 const struct drm_display_mode *cea_mode = NULL; 3531 struct drm_display_mode *newmode; 3532 u8 vic = drm_match_cea_mode(mode); 3533 unsigned int clock1, clock2; 3534 3535 if (drm_valid_cea_vic(vic)) { 3536 cea_mode = cea_mode_for_vic(vic); 3537 clock2 = cea_mode_alternate_clock(cea_mode); 3538 } else { 3539 vic = drm_match_hdmi_mode(mode); 3540 if (drm_valid_hdmi_vic(vic)) { 3541 cea_mode = &edid_4k_modes[vic]; 3542 clock2 = hdmi_mode_alternate_clock(cea_mode); 3543 } 3544 } 3545 3546 if (!cea_mode) 3547 continue; 3548 3549 clock1 = cea_mode->clock; 3550 3551 if (clock1 == clock2) 3552 continue; 3553 3554 if (mode->clock != clock1 && mode->clock != clock2) 3555 continue; 3556 3557 newmode = drm_mode_duplicate(dev, cea_mode); 3558 if (!newmode) 3559 continue; 3560 3561 /* Carry over the stereo flags */ 3562 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3563 3564 /* 3565 * The current mode could be either variant. Make 3566 * sure to pick the "other" clock for the new mode. 3567 */ 3568 if (mode->clock != clock1) 3569 newmode->clock = clock1; 3570 else 3571 newmode->clock = clock2; 3572 3573 list_add_tail(&newmode->head, &list); 3574 } 3575 3576 list_for_each_entry_safe(mode, tmp, &list, head) { 3577 list_del(&mode->head); 3578 drm_mode_probed_add(connector, mode); 3579 modes++; 3580 } 3581 3582 return modes; 3583 } 3584 3585 static u8 svd_to_vic(u8 svd) 3586 { 3587 /* 0-6 bit vic, 7th bit native mode indicator */ 3588 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3589 return svd & 127; 3590 3591 return svd; 3592 } 3593 3594 static struct drm_display_mode * 3595 drm_display_mode_from_vic_index(struct drm_connector *connector, 3596 const u8 *video_db, u8 video_len, 3597 u8 video_index) 3598 { 3599 struct drm_device *dev = connector->dev; 3600 struct drm_display_mode *newmode; 3601 u8 vic; 3602 3603 if (video_db == NULL || video_index >= video_len) 3604 return NULL; 3605 3606 /* CEA modes are numbered 1..127 */ 3607 vic = svd_to_vic(video_db[video_index]); 3608 if (!drm_valid_cea_vic(vic)) 3609 return NULL; 3610 3611 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3612 if (!newmode) 3613 return NULL; 3614 3615 newmode->vrefresh = 0; 3616 3617 return newmode; 3618 } 3619 3620 /* 3621 * do_y420vdb_modes - Parse YCBCR 420 only modes 3622 * @connector: connector corresponding to the HDMI sink 3623 * @svds: start of the data block of CEA YCBCR 420 VDB 3624 * @len: length of the CEA YCBCR 420 VDB 3625 * 3626 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3627 * which contains modes which can be supported in YCBCR 420 3628 * output format only. 3629 */ 3630 static int do_y420vdb_modes(struct drm_connector *connector, 3631 const u8 *svds, u8 svds_len) 3632 { 3633 int modes = 0, i; 3634 struct drm_device *dev = connector->dev; 3635 struct drm_display_info *info = &connector->display_info; 3636 struct drm_hdmi_info *hdmi = &info->hdmi; 3637 3638 for (i = 0; i < svds_len; i++) { 3639 u8 vic = svd_to_vic(svds[i]); 3640 struct drm_display_mode *newmode; 3641 3642 if (!drm_valid_cea_vic(vic)) 3643 continue; 3644 3645 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3646 if (!newmode) 3647 break; 3648 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3649 drm_mode_probed_add(connector, newmode); 3650 modes++; 3651 } 3652 3653 if (modes > 0) 3654 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3655 return modes; 3656 } 3657 3658 /* 3659 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3660 * @connector: connector corresponding to the HDMI sink 3661 * @vic: CEA vic for the video mode to be added in the map 3662 * 3663 * Makes an entry for a videomode in the YCBCR 420 bitmap 3664 */ 3665 static void 3666 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3667 { 3668 u8 vic = svd_to_vic(svd); 3669 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3670 3671 if (!drm_valid_cea_vic(vic)) 3672 return; 3673 3674 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3675 } 3676 3677 static int 3678 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3679 { 3680 int i, modes = 0; 3681 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3682 3683 for (i = 0; i < len; i++) { 3684 struct drm_display_mode *mode; 3685 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3686 if (mode) { 3687 /* 3688 * YCBCR420 capability block contains a bitmap which 3689 * gives the index of CEA modes from CEA VDB, which 3690 * can support YCBCR 420 sampling output also (apart 3691 * from RGB/YCBCR444 etc). 3692 * For example, if the bit 0 in bitmap is set, 3693 * first mode in VDB can support YCBCR420 output too. 3694 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3695 */ 3696 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3697 drm_add_cmdb_modes(connector, db[i]); 3698 3699 drm_mode_probed_add(connector, mode); 3700 modes++; 3701 } 3702 } 3703 3704 return modes; 3705 } 3706 3707 struct stereo_mandatory_mode { 3708 int width, height, vrefresh; 3709 unsigned int flags; 3710 }; 3711 3712 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3713 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3714 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3715 { 1920, 1080, 50, 3716 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3717 { 1920, 1080, 60, 3718 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3719 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3720 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3721 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3722 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3723 }; 3724 3725 static bool 3726 stereo_match_mandatory(const struct drm_display_mode *mode, 3727 const struct stereo_mandatory_mode *stereo_mode) 3728 { 3729 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3730 3731 return mode->hdisplay == stereo_mode->width && 3732 mode->vdisplay == stereo_mode->height && 3733 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3734 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3735 } 3736 3737 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3738 { 3739 struct drm_device *dev = connector->dev; 3740 const struct drm_display_mode *mode; 3741 struct list_head stereo_modes; 3742 int modes = 0, i; 3743 3744 INIT_LIST_HEAD(&stereo_modes); 3745 3746 list_for_each_entry(mode, &connector->probed_modes, head) { 3747 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3748 const struct stereo_mandatory_mode *mandatory; 3749 struct drm_display_mode *new_mode; 3750 3751 if (!stereo_match_mandatory(mode, 3752 &stereo_mandatory_modes[i])) 3753 continue; 3754 3755 mandatory = &stereo_mandatory_modes[i]; 3756 new_mode = drm_mode_duplicate(dev, mode); 3757 if (!new_mode) 3758 continue; 3759 3760 new_mode->flags |= mandatory->flags; 3761 list_add_tail(&new_mode->head, &stereo_modes); 3762 modes++; 3763 } 3764 } 3765 3766 list_splice_tail(&stereo_modes, &connector->probed_modes); 3767 3768 return modes; 3769 } 3770 3771 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3772 { 3773 struct drm_device *dev = connector->dev; 3774 struct drm_display_mode *newmode; 3775 3776 if (!drm_valid_hdmi_vic(vic)) { 3777 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3778 return 0; 3779 } 3780 3781 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3782 if (!newmode) 3783 return 0; 3784 3785 drm_mode_probed_add(connector, newmode); 3786 3787 return 1; 3788 } 3789 3790 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3791 const u8 *video_db, u8 video_len, u8 video_index) 3792 { 3793 struct drm_display_mode *newmode; 3794 int modes = 0; 3795 3796 if (structure & (1 << 0)) { 3797 newmode = drm_display_mode_from_vic_index(connector, video_db, 3798 video_len, 3799 video_index); 3800 if (newmode) { 3801 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3802 drm_mode_probed_add(connector, newmode); 3803 modes++; 3804 } 3805 } 3806 if (structure & (1 << 6)) { 3807 newmode = drm_display_mode_from_vic_index(connector, video_db, 3808 video_len, 3809 video_index); 3810 if (newmode) { 3811 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3812 drm_mode_probed_add(connector, newmode); 3813 modes++; 3814 } 3815 } 3816 if (structure & (1 << 8)) { 3817 newmode = drm_display_mode_from_vic_index(connector, video_db, 3818 video_len, 3819 video_index); 3820 if (newmode) { 3821 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3822 drm_mode_probed_add(connector, newmode); 3823 modes++; 3824 } 3825 } 3826 3827 return modes; 3828 } 3829 3830 /* 3831 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3832 * @connector: connector corresponding to the HDMI sink 3833 * @db: start of the CEA vendor specific block 3834 * @len: length of the CEA block payload, ie. one can access up to db[len] 3835 * 3836 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3837 * also adds the stereo 3d modes when applicable. 3838 */ 3839 static int 3840 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3841 const u8 *video_db, u8 video_len) 3842 { 3843 struct drm_display_info *info = &connector->display_info; 3844 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3845 u8 vic_len, hdmi_3d_len = 0; 3846 u16 mask; 3847 u16 structure_all; 3848 3849 if (len < 8) 3850 goto out; 3851 3852 /* no HDMI_Video_Present */ 3853 if (!(db[8] & (1 << 5))) 3854 goto out; 3855 3856 /* Latency_Fields_Present */ 3857 if (db[8] & (1 << 7)) 3858 offset += 2; 3859 3860 /* I_Latency_Fields_Present */ 3861 if (db[8] & (1 << 6)) 3862 offset += 2; 3863 3864 /* the declared length is not long enough for the 2 first bytes 3865 * of additional video format capabilities */ 3866 if (len < (8 + offset + 2)) 3867 goto out; 3868 3869 /* 3D_Present */ 3870 offset++; 3871 if (db[8 + offset] & (1 << 7)) { 3872 modes += add_hdmi_mandatory_stereo_modes(connector); 3873 3874 /* 3D_Multi_present */ 3875 multi_present = (db[8 + offset] & 0x60) >> 5; 3876 } 3877 3878 offset++; 3879 vic_len = db[8 + offset] >> 5; 3880 hdmi_3d_len = db[8 + offset] & 0x1f; 3881 3882 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3883 u8 vic; 3884 3885 vic = db[9 + offset + i]; 3886 modes += add_hdmi_mode(connector, vic); 3887 } 3888 offset += 1 + vic_len; 3889 3890 if (multi_present == 1) 3891 multi_len = 2; 3892 else if (multi_present == 2) 3893 multi_len = 4; 3894 else 3895 multi_len = 0; 3896 3897 if (len < (8 + offset + hdmi_3d_len - 1)) 3898 goto out; 3899 3900 if (hdmi_3d_len < multi_len) 3901 goto out; 3902 3903 if (multi_present == 1 || multi_present == 2) { 3904 /* 3D_Structure_ALL */ 3905 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3906 3907 /* check if 3D_MASK is present */ 3908 if (multi_present == 2) 3909 mask = (db[10 + offset] << 8) | db[11 + offset]; 3910 else 3911 mask = 0xffff; 3912 3913 for (i = 0; i < 16; i++) { 3914 if (mask & (1 << i)) 3915 modes += add_3d_struct_modes(connector, 3916 structure_all, 3917 video_db, 3918 video_len, i); 3919 } 3920 } 3921 3922 offset += multi_len; 3923 3924 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3925 int vic_index; 3926 struct drm_display_mode *newmode = NULL; 3927 unsigned int newflag = 0; 3928 bool detail_present; 3929 3930 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3931 3932 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3933 break; 3934 3935 /* 2D_VIC_order_X */ 3936 vic_index = db[8 + offset + i] >> 4; 3937 3938 /* 3D_Structure_X */ 3939 switch (db[8 + offset + i] & 0x0f) { 3940 case 0: 3941 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3942 break; 3943 case 6: 3944 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3945 break; 3946 case 8: 3947 /* 3D_Detail_X */ 3948 if ((db[9 + offset + i] >> 4) == 1) 3949 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3950 break; 3951 } 3952 3953 if (newflag != 0) { 3954 newmode = drm_display_mode_from_vic_index(connector, 3955 video_db, 3956 video_len, 3957 vic_index); 3958 3959 if (newmode) { 3960 newmode->flags |= newflag; 3961 drm_mode_probed_add(connector, newmode); 3962 modes++; 3963 } 3964 } 3965 3966 if (detail_present) 3967 i++; 3968 } 3969 3970 out: 3971 if (modes > 0) 3972 info->has_hdmi_infoframe = true; 3973 return modes; 3974 } 3975 3976 static int 3977 cea_db_payload_len(const u8 *db) 3978 { 3979 return db[0] & 0x1f; 3980 } 3981 3982 static int 3983 cea_db_extended_tag(const u8 *db) 3984 { 3985 return db[1]; 3986 } 3987 3988 static int 3989 cea_db_tag(const u8 *db) 3990 { 3991 return db[0] >> 5; 3992 } 3993 3994 static int 3995 cea_revision(const u8 *cea) 3996 { 3997 /* 3998 * FIXME is this correct for the DispID variant? 3999 * The DispID spec doesn't really specify whether 4000 * this is the revision of the CEA extension or 4001 * the DispID CEA data block. And the only value 4002 * given as an example is 0. 4003 */ 4004 return cea[1]; 4005 } 4006 4007 static int 4008 cea_db_offsets(const u8 *cea, int *start, int *end) 4009 { 4010 /* DisplayID CTA extension blocks and top-level CEA EDID 4011 * block header definitions differ in the following bytes: 4012 * 1) Byte 2 of the header specifies length differently, 4013 * 2) Byte 3 is only present in the CEA top level block. 4014 * 4015 * The different definitions for byte 2 follow. 4016 * 4017 * DisplayID CTA extension block defines byte 2 as: 4018 * Number of payload bytes 4019 * 4020 * CEA EDID block defines byte 2 as: 4021 * Byte number (decimal) within this block where the 18-byte 4022 * DTDs begin. If no non-DTD data is present in this extension 4023 * block, the value should be set to 04h (the byte after next). 4024 * If set to 00h, there are no DTDs present in this block and 4025 * no non-DTD data. 4026 */ 4027 if (cea[0] == DATA_BLOCK_CTA) { 4028 /* 4029 * for_each_displayid_db() has already verified 4030 * that these stay within expected bounds. 4031 */ 4032 *start = 3; 4033 *end = *start + cea[2]; 4034 } else if (cea[0] == CEA_EXT) { 4035 /* Data block offset in CEA extension block */ 4036 *start = 4; 4037 *end = cea[2]; 4038 if (*end == 0) 4039 *end = 127; 4040 if (*end < 4 || *end > 127) 4041 return -ERANGE; 4042 } else { 4043 return -EOPNOTSUPP; 4044 } 4045 4046 return 0; 4047 } 4048 4049 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4050 { 4051 int hdmi_id; 4052 4053 if (cea_db_tag(db) != VENDOR_BLOCK) 4054 return false; 4055 4056 if (cea_db_payload_len(db) < 5) 4057 return false; 4058 4059 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4060 4061 return hdmi_id == HDMI_IEEE_OUI; 4062 } 4063 4064 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4065 { 4066 unsigned int oui; 4067 4068 if (cea_db_tag(db) != VENDOR_BLOCK) 4069 return false; 4070 4071 if (cea_db_payload_len(db) < 7) 4072 return false; 4073 4074 oui = db[3] << 16 | db[2] << 8 | db[1]; 4075 4076 return oui == HDMI_FORUM_IEEE_OUI; 4077 } 4078 4079 static bool cea_db_is_vcdb(const u8 *db) 4080 { 4081 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4082 return false; 4083 4084 if (cea_db_payload_len(db) != 2) 4085 return false; 4086 4087 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4088 return false; 4089 4090 return true; 4091 } 4092 4093 static bool cea_db_is_y420cmdb(const u8 *db) 4094 { 4095 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4096 return false; 4097 4098 if (!cea_db_payload_len(db)) 4099 return false; 4100 4101 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4102 return false; 4103 4104 return true; 4105 } 4106 4107 static bool cea_db_is_y420vdb(const u8 *db) 4108 { 4109 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4110 return false; 4111 4112 if (!cea_db_payload_len(db)) 4113 return false; 4114 4115 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4116 return false; 4117 4118 return true; 4119 } 4120 4121 #define for_each_cea_db(cea, i, start, end) \ 4122 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4123 4124 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4125 const u8 *db) 4126 { 4127 struct drm_display_info *info = &connector->display_info; 4128 struct drm_hdmi_info *hdmi = &info->hdmi; 4129 u8 map_len = cea_db_payload_len(db) - 1; 4130 u8 count; 4131 u64 map = 0; 4132 4133 if (map_len == 0) { 4134 /* All CEA modes support ycbcr420 sampling also.*/ 4135 hdmi->y420_cmdb_map = U64_MAX; 4136 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4137 return; 4138 } 4139 4140 /* 4141 * This map indicates which of the existing CEA block modes 4142 * from VDB can support YCBCR420 output too. So if bit=0 is 4143 * set, first mode from VDB can support YCBCR420 output too. 4144 * We will parse and keep this map, before parsing VDB itself 4145 * to avoid going through the same block again and again. 4146 * 4147 * Spec is not clear about max possible size of this block. 4148 * Clamping max bitmap block size at 8 bytes. Every byte can 4149 * address 8 CEA modes, in this way this map can address 4150 * 8*8 = first 64 SVDs. 4151 */ 4152 if (WARN_ON_ONCE(map_len > 8)) 4153 map_len = 8; 4154 4155 for (count = 0; count < map_len; count++) 4156 map |= (u64)db[2 + count] << (8 * count); 4157 4158 if (map) 4159 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4160 4161 hdmi->y420_cmdb_map = map; 4162 } 4163 4164 static int 4165 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4166 { 4167 const u8 *cea = drm_find_cea_extension(edid); 4168 const u8 *db, *hdmi = NULL, *video = NULL; 4169 u8 dbl, hdmi_len, video_len = 0; 4170 int modes = 0; 4171 4172 if (cea && cea_revision(cea) >= 3) { 4173 int i, start, end; 4174 4175 if (cea_db_offsets(cea, &start, &end)) 4176 return 0; 4177 4178 for_each_cea_db(cea, i, start, end) { 4179 db = &cea[i]; 4180 dbl = cea_db_payload_len(db); 4181 4182 if (cea_db_tag(db) == VIDEO_BLOCK) { 4183 video = db + 1; 4184 video_len = dbl; 4185 modes += do_cea_modes(connector, video, dbl); 4186 } else if (cea_db_is_hdmi_vsdb(db)) { 4187 hdmi = db; 4188 hdmi_len = dbl; 4189 } else if (cea_db_is_y420vdb(db)) { 4190 const u8 *vdb420 = &db[2]; 4191 4192 /* Add 4:2:0(only) modes present in EDID */ 4193 modes += do_y420vdb_modes(connector, 4194 vdb420, 4195 dbl - 1); 4196 } 4197 } 4198 } 4199 4200 /* 4201 * We parse the HDMI VSDB after having added the cea modes as we will 4202 * be patching their flags when the sink supports stereo 3D. 4203 */ 4204 if (hdmi) 4205 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4206 video_len); 4207 4208 return modes; 4209 } 4210 4211 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4212 { 4213 const struct drm_display_mode *cea_mode; 4214 int clock1, clock2, clock; 4215 u8 vic; 4216 const char *type; 4217 4218 /* 4219 * allow 5kHz clock difference either way to account for 4220 * the 10kHz clock resolution limit of detailed timings. 4221 */ 4222 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4223 if (drm_valid_cea_vic(vic)) { 4224 type = "CEA"; 4225 cea_mode = cea_mode_for_vic(vic); 4226 clock1 = cea_mode->clock; 4227 clock2 = cea_mode_alternate_clock(cea_mode); 4228 } else { 4229 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4230 if (drm_valid_hdmi_vic(vic)) { 4231 type = "HDMI"; 4232 cea_mode = &edid_4k_modes[vic]; 4233 clock1 = cea_mode->clock; 4234 clock2 = hdmi_mode_alternate_clock(cea_mode); 4235 } else { 4236 return; 4237 } 4238 } 4239 4240 /* pick whichever is closest */ 4241 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4242 clock = clock1; 4243 else 4244 clock = clock2; 4245 4246 if (mode->clock == clock) 4247 return; 4248 4249 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4250 type, vic, mode->clock, clock); 4251 mode->clock = clock; 4252 } 4253 4254 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4255 { 4256 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4257 return false; 4258 4259 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4260 return false; 4261 4262 if (cea_db_payload_len(db) < 3) 4263 return false; 4264 4265 return true; 4266 } 4267 4268 static uint8_t eotf_supported(const u8 *edid_ext) 4269 { 4270 return edid_ext[2] & 4271 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4272 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4273 BIT(HDMI_EOTF_SMPTE_ST2084) | 4274 BIT(HDMI_EOTF_BT_2100_HLG)); 4275 } 4276 4277 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4278 { 4279 return edid_ext[3] & 4280 BIT(HDMI_STATIC_METADATA_TYPE1); 4281 } 4282 4283 static void 4284 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4285 { 4286 u16 len; 4287 4288 len = cea_db_payload_len(db); 4289 4290 connector->hdr_sink_metadata.hdmi_type1.eotf = 4291 eotf_supported(db); 4292 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4293 hdr_metadata_type(db); 4294 4295 if (len >= 4) 4296 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4297 if (len >= 5) 4298 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4299 if (len >= 6) 4300 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4301 } 4302 4303 static void 4304 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4305 { 4306 u8 len = cea_db_payload_len(db); 4307 4308 if (len >= 6 && (db[6] & (1 << 7))) 4309 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4310 if (len >= 8) { 4311 connector->latency_present[0] = db[8] >> 7; 4312 connector->latency_present[1] = (db[8] >> 6) & 1; 4313 } 4314 if (len >= 9) 4315 connector->video_latency[0] = db[9]; 4316 if (len >= 10) 4317 connector->audio_latency[0] = db[10]; 4318 if (len >= 11) 4319 connector->video_latency[1] = db[11]; 4320 if (len >= 12) 4321 connector->audio_latency[1] = db[12]; 4322 4323 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4324 "video latency %d %d, " 4325 "audio latency %d %d\n", 4326 connector->latency_present[0], 4327 connector->latency_present[1], 4328 connector->video_latency[0], 4329 connector->video_latency[1], 4330 connector->audio_latency[0], 4331 connector->audio_latency[1]); 4332 } 4333 4334 static void 4335 monitor_name(struct detailed_timing *t, void *data) 4336 { 4337 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4338 return; 4339 4340 *(u8 **)data = t->data.other_data.data.str.str; 4341 } 4342 4343 static int get_monitor_name(struct edid *edid, char name[13]) 4344 { 4345 char *edid_name = NULL; 4346 int mnl; 4347 4348 if (!edid || !name) 4349 return 0; 4350 4351 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4352 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4353 if (edid_name[mnl] == 0x0a) 4354 break; 4355 4356 name[mnl] = edid_name[mnl]; 4357 } 4358 4359 return mnl; 4360 } 4361 4362 /** 4363 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4364 * @edid: monitor EDID information 4365 * @name: pointer to a character array to hold the name of the monitor 4366 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4367 * 4368 */ 4369 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4370 { 4371 int name_length; 4372 char buf[13]; 4373 4374 if (bufsize <= 0) 4375 return; 4376 4377 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4378 memcpy(name, buf, name_length); 4379 name[name_length] = '\0'; 4380 } 4381 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4382 4383 static void clear_eld(struct drm_connector *connector) 4384 { 4385 memset(connector->eld, 0, sizeof(connector->eld)); 4386 4387 connector->latency_present[0] = false; 4388 connector->latency_present[1] = false; 4389 connector->video_latency[0] = 0; 4390 connector->audio_latency[0] = 0; 4391 connector->video_latency[1] = 0; 4392 connector->audio_latency[1] = 0; 4393 } 4394 4395 /* 4396 * drm_edid_to_eld - build ELD from EDID 4397 * @connector: connector corresponding to the HDMI/DP sink 4398 * @edid: EDID to parse 4399 * 4400 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4401 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4402 */ 4403 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4404 { 4405 uint8_t *eld = connector->eld; 4406 u8 *cea; 4407 u8 *db; 4408 int total_sad_count = 0; 4409 int mnl; 4410 int dbl; 4411 4412 clear_eld(connector); 4413 4414 if (!edid) 4415 return; 4416 4417 cea = drm_find_cea_extension(edid); 4418 if (!cea) { 4419 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4420 return; 4421 } 4422 4423 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4424 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4425 4426 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4427 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4428 4429 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4430 4431 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4432 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4433 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4434 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4435 4436 if (cea_revision(cea) >= 3) { 4437 int i, start, end; 4438 int sad_count; 4439 4440 if (cea_db_offsets(cea, &start, &end)) { 4441 start = 0; 4442 end = 0; 4443 } 4444 4445 for_each_cea_db(cea, i, start, end) { 4446 db = &cea[i]; 4447 dbl = cea_db_payload_len(db); 4448 4449 switch (cea_db_tag(db)) { 4450 case AUDIO_BLOCK: 4451 /* Audio Data Block, contains SADs */ 4452 sad_count = min(dbl / 3, 15 - total_sad_count); 4453 if (sad_count >= 1) 4454 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4455 &db[1], sad_count * 3); 4456 total_sad_count += sad_count; 4457 break; 4458 case SPEAKER_BLOCK: 4459 /* Speaker Allocation Data Block */ 4460 if (dbl >= 1) 4461 eld[DRM_ELD_SPEAKER] = db[1]; 4462 break; 4463 case VENDOR_BLOCK: 4464 /* HDMI Vendor-Specific Data Block */ 4465 if (cea_db_is_hdmi_vsdb(db)) 4466 drm_parse_hdmi_vsdb_audio(connector, db); 4467 break; 4468 default: 4469 break; 4470 } 4471 } 4472 } 4473 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4474 4475 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4476 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4477 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4478 else 4479 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4480 4481 eld[DRM_ELD_BASELINE_ELD_LEN] = 4482 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4483 4484 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4485 drm_eld_size(eld), total_sad_count); 4486 } 4487 4488 /** 4489 * drm_edid_to_sad - extracts SADs from EDID 4490 * @edid: EDID to parse 4491 * @sads: pointer that will be set to the extracted SADs 4492 * 4493 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4494 * 4495 * Note: The returned pointer needs to be freed using kfree(). 4496 * 4497 * Return: The number of found SADs or negative number on error. 4498 */ 4499 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4500 { 4501 int count = 0; 4502 int i, start, end, dbl; 4503 u8 *cea; 4504 4505 cea = drm_find_cea_extension(edid); 4506 if (!cea) { 4507 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4508 return 0; 4509 } 4510 4511 if (cea_revision(cea) < 3) { 4512 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4513 return 0; 4514 } 4515 4516 if (cea_db_offsets(cea, &start, &end)) { 4517 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4518 return -EPROTO; 4519 } 4520 4521 for_each_cea_db(cea, i, start, end) { 4522 u8 *db = &cea[i]; 4523 4524 if (cea_db_tag(db) == AUDIO_BLOCK) { 4525 int j; 4526 dbl = cea_db_payload_len(db); 4527 4528 count = dbl / 3; /* SAD is 3B */ 4529 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4530 if (!*sads) 4531 return -ENOMEM; 4532 for (j = 0; j < count; j++) { 4533 u8 *sad = &db[1 + j * 3]; 4534 4535 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4536 (*sads)[j].channels = sad[0] & 0x7; 4537 (*sads)[j].freq = sad[1] & 0x7F; 4538 (*sads)[j].byte2 = sad[2]; 4539 } 4540 break; 4541 } 4542 } 4543 4544 return count; 4545 } 4546 EXPORT_SYMBOL(drm_edid_to_sad); 4547 4548 /** 4549 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4550 * @edid: EDID to parse 4551 * @sadb: pointer to the speaker block 4552 * 4553 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4554 * 4555 * Note: The returned pointer needs to be freed using kfree(). 4556 * 4557 * Return: The number of found Speaker Allocation Blocks or negative number on 4558 * error. 4559 */ 4560 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4561 { 4562 int count = 0; 4563 int i, start, end, dbl; 4564 const u8 *cea; 4565 4566 cea = drm_find_cea_extension(edid); 4567 if (!cea) { 4568 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4569 return 0; 4570 } 4571 4572 if (cea_revision(cea) < 3) { 4573 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4574 return 0; 4575 } 4576 4577 if (cea_db_offsets(cea, &start, &end)) { 4578 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4579 return -EPROTO; 4580 } 4581 4582 for_each_cea_db(cea, i, start, end) { 4583 const u8 *db = &cea[i]; 4584 4585 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4586 dbl = cea_db_payload_len(db); 4587 4588 /* Speaker Allocation Data Block */ 4589 if (dbl == 3) { 4590 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4591 if (!*sadb) 4592 return -ENOMEM; 4593 count = dbl; 4594 break; 4595 } 4596 } 4597 } 4598 4599 return count; 4600 } 4601 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4602 4603 /** 4604 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4605 * @connector: connector associated with the HDMI/DP sink 4606 * @mode: the display mode 4607 * 4608 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4609 * the sink doesn't support audio or video. 4610 */ 4611 int drm_av_sync_delay(struct drm_connector *connector, 4612 const struct drm_display_mode *mode) 4613 { 4614 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4615 int a, v; 4616 4617 if (!connector->latency_present[0]) 4618 return 0; 4619 if (!connector->latency_present[1]) 4620 i = 0; 4621 4622 a = connector->audio_latency[i]; 4623 v = connector->video_latency[i]; 4624 4625 /* 4626 * HDMI/DP sink doesn't support audio or video? 4627 */ 4628 if (a == 255 || v == 255) 4629 return 0; 4630 4631 /* 4632 * Convert raw EDID values to millisecond. 4633 * Treat unknown latency as 0ms. 4634 */ 4635 if (a) 4636 a = min(2 * (a - 1), 500); 4637 if (v) 4638 v = min(2 * (v - 1), 500); 4639 4640 return max(v - a, 0); 4641 } 4642 EXPORT_SYMBOL(drm_av_sync_delay); 4643 4644 /** 4645 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4646 * @edid: monitor EDID information 4647 * 4648 * Parse the CEA extension according to CEA-861-B. 4649 * 4650 * Drivers that have added the modes parsed from EDID to drm_display_info 4651 * should use &drm_display_info.is_hdmi instead of calling this function. 4652 * 4653 * Return: True if the monitor is HDMI, false if not or unknown. 4654 */ 4655 bool drm_detect_hdmi_monitor(struct edid *edid) 4656 { 4657 u8 *edid_ext; 4658 int i; 4659 int start_offset, end_offset; 4660 4661 edid_ext = drm_find_cea_extension(edid); 4662 if (!edid_ext) 4663 return false; 4664 4665 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4666 return false; 4667 4668 /* 4669 * Because HDMI identifier is in Vendor Specific Block, 4670 * search it from all data blocks of CEA extension. 4671 */ 4672 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4673 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4674 return true; 4675 } 4676 4677 return false; 4678 } 4679 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4680 4681 /** 4682 * drm_detect_monitor_audio - check monitor audio capability 4683 * @edid: EDID block to scan 4684 * 4685 * Monitor should have CEA extension block. 4686 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4687 * audio' only. If there is any audio extension block and supported 4688 * audio format, assume at least 'basic audio' support, even if 'basic 4689 * audio' is not defined in EDID. 4690 * 4691 * Return: True if the monitor supports audio, false otherwise. 4692 */ 4693 bool drm_detect_monitor_audio(struct edid *edid) 4694 { 4695 u8 *edid_ext; 4696 int i, j; 4697 bool has_audio = false; 4698 int start_offset, end_offset; 4699 4700 edid_ext = drm_find_cea_extension(edid); 4701 if (!edid_ext) 4702 goto end; 4703 4704 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4705 4706 if (has_audio) { 4707 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4708 goto end; 4709 } 4710 4711 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4712 goto end; 4713 4714 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4715 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4716 has_audio = true; 4717 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4718 DRM_DEBUG_KMS("CEA audio format %d\n", 4719 (edid_ext[i + j] >> 3) & 0xf); 4720 goto end; 4721 } 4722 } 4723 end: 4724 return has_audio; 4725 } 4726 EXPORT_SYMBOL(drm_detect_monitor_audio); 4727 4728 4729 /** 4730 * drm_default_rgb_quant_range - default RGB quantization range 4731 * @mode: display mode 4732 * 4733 * Determine the default RGB quantization range for the mode, 4734 * as specified in CEA-861. 4735 * 4736 * Return: The default RGB quantization range for the mode 4737 */ 4738 enum hdmi_quantization_range 4739 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4740 { 4741 /* All CEA modes other than VIC 1 use limited quantization range. */ 4742 return drm_match_cea_mode(mode) > 1 ? 4743 HDMI_QUANTIZATION_RANGE_LIMITED : 4744 HDMI_QUANTIZATION_RANGE_FULL; 4745 } 4746 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4747 4748 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4749 { 4750 struct drm_display_info *info = &connector->display_info; 4751 4752 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4753 4754 if (db[2] & EDID_CEA_VCDB_QS) 4755 info->rgb_quant_range_selectable = true; 4756 } 4757 4758 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4759 const u8 *db) 4760 { 4761 u8 dc_mask; 4762 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4763 4764 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4765 hdmi->y420_dc_modes = dc_mask; 4766 } 4767 4768 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4769 const u8 *hf_vsdb) 4770 { 4771 struct drm_display_info *display = &connector->display_info; 4772 struct drm_hdmi_info *hdmi = &display->hdmi; 4773 4774 display->has_hdmi_infoframe = true; 4775 4776 if (hf_vsdb[6] & 0x80) { 4777 hdmi->scdc.supported = true; 4778 if (hf_vsdb[6] & 0x40) 4779 hdmi->scdc.read_request = true; 4780 } 4781 4782 /* 4783 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4784 * And as per the spec, three factors confirm this: 4785 * * Availability of a HF-VSDB block in EDID (check) 4786 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4787 * * SCDC support available (let's check) 4788 * Lets check it out. 4789 */ 4790 4791 if (hf_vsdb[5]) { 4792 /* max clock is 5000 KHz times block value */ 4793 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4794 struct drm_scdc *scdc = &hdmi->scdc; 4795 4796 if (max_tmds_clock > 340000) { 4797 display->max_tmds_clock = max_tmds_clock; 4798 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4799 display->max_tmds_clock); 4800 } 4801 4802 if (scdc->supported) { 4803 scdc->scrambling.supported = true; 4804 4805 /* Few sinks support scrambling for clocks < 340M */ 4806 if ((hf_vsdb[6] & 0x8)) 4807 scdc->scrambling.low_rates = true; 4808 } 4809 } 4810 4811 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4812 } 4813 4814 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4815 const u8 *hdmi) 4816 { 4817 struct drm_display_info *info = &connector->display_info; 4818 unsigned int dc_bpc = 0; 4819 4820 /* HDMI supports at least 8 bpc */ 4821 info->bpc = 8; 4822 4823 if (cea_db_payload_len(hdmi) < 6) 4824 return; 4825 4826 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4827 dc_bpc = 10; 4828 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4829 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4830 connector->name); 4831 } 4832 4833 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4834 dc_bpc = 12; 4835 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4836 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4837 connector->name); 4838 } 4839 4840 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4841 dc_bpc = 16; 4842 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4843 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4844 connector->name); 4845 } 4846 4847 if (dc_bpc == 0) { 4848 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4849 connector->name); 4850 return; 4851 } 4852 4853 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4854 connector->name, dc_bpc); 4855 info->bpc = dc_bpc; 4856 4857 /* 4858 * Deep color support mandates RGB444 support for all video 4859 * modes and forbids YCRCB422 support for all video modes per 4860 * HDMI 1.3 spec. 4861 */ 4862 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4863 4864 /* YCRCB444 is optional according to spec. */ 4865 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4866 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4867 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4868 connector->name); 4869 } 4870 4871 /* 4872 * Spec says that if any deep color mode is supported at all, 4873 * then deep color 36 bit must be supported. 4874 */ 4875 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4876 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4877 connector->name); 4878 } 4879 } 4880 4881 static void 4882 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4883 { 4884 struct drm_display_info *info = &connector->display_info; 4885 u8 len = cea_db_payload_len(db); 4886 4887 info->is_hdmi = true; 4888 4889 if (len >= 6) 4890 info->dvi_dual = db[6] & 1; 4891 if (len >= 7) 4892 info->max_tmds_clock = db[7] * 5000; 4893 4894 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4895 "max TMDS clock %d kHz\n", 4896 info->dvi_dual, 4897 info->max_tmds_clock); 4898 4899 drm_parse_hdmi_deep_color_info(connector, db); 4900 } 4901 4902 static void drm_parse_cea_ext(struct drm_connector *connector, 4903 const struct edid *edid) 4904 { 4905 struct drm_display_info *info = &connector->display_info; 4906 const u8 *edid_ext; 4907 int i, start, end; 4908 4909 edid_ext = drm_find_cea_extension(edid); 4910 if (!edid_ext) 4911 return; 4912 4913 info->cea_rev = edid_ext[1]; 4914 4915 /* The existence of a CEA block should imply RGB support */ 4916 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4917 if (edid_ext[3] & EDID_CEA_YCRCB444) 4918 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4919 if (edid_ext[3] & EDID_CEA_YCRCB422) 4920 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4921 4922 if (cea_db_offsets(edid_ext, &start, &end)) 4923 return; 4924 4925 for_each_cea_db(edid_ext, i, start, end) { 4926 const u8 *db = &edid_ext[i]; 4927 4928 if (cea_db_is_hdmi_vsdb(db)) 4929 drm_parse_hdmi_vsdb_video(connector, db); 4930 if (cea_db_is_hdmi_forum_vsdb(db)) 4931 drm_parse_hdmi_forum_vsdb(connector, db); 4932 if (cea_db_is_y420cmdb(db)) 4933 drm_parse_y420cmdb_bitmap(connector, db); 4934 if (cea_db_is_vcdb(db)) 4935 drm_parse_vcdb(connector, db); 4936 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4937 drm_parse_hdr_metadata_block(connector, db); 4938 } 4939 } 4940 4941 static 4942 void get_monitor_range(struct detailed_timing *timing, 4943 void *info_monitor_range) 4944 { 4945 struct drm_monitor_range_info *monitor_range = info_monitor_range; 4946 const struct detailed_non_pixel *data = &timing->data.other_data; 4947 const struct detailed_data_monitor_range *range = &data->data.range; 4948 4949 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 4950 return; 4951 4952 /* 4953 * Check for flag range limits only. If flag == 1 then 4954 * no additional timing information provided. 4955 * Default GTF, GTF Secondary curve and CVT are not 4956 * supported 4957 */ 4958 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 4959 return; 4960 4961 monitor_range->min_vfreq = range->min_vfreq; 4962 monitor_range->max_vfreq = range->max_vfreq; 4963 } 4964 4965 static 4966 void drm_get_monitor_range(struct drm_connector *connector, 4967 const struct edid *edid) 4968 { 4969 struct drm_display_info *info = &connector->display_info; 4970 4971 if (!version_greater(edid, 1, 1)) 4972 return; 4973 4974 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 4975 &info->monitor_range); 4976 4977 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 4978 info->monitor_range.min_vfreq, 4979 info->monitor_range.max_vfreq); 4980 } 4981 4982 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4983 * all of the values which would have been set from EDID 4984 */ 4985 void 4986 drm_reset_display_info(struct drm_connector *connector) 4987 { 4988 struct drm_display_info *info = &connector->display_info; 4989 4990 info->width_mm = 0; 4991 info->height_mm = 0; 4992 4993 info->bpc = 0; 4994 info->color_formats = 0; 4995 info->cea_rev = 0; 4996 info->max_tmds_clock = 0; 4997 info->dvi_dual = false; 4998 info->is_hdmi = false; 4999 info->has_hdmi_infoframe = false; 5000 info->rgb_quant_range_selectable = false; 5001 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5002 5003 info->non_desktop = 0; 5004 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5005 } 5006 5007 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5008 { 5009 struct drm_display_info *info = &connector->display_info; 5010 5011 u32 quirks = edid_get_quirks(edid); 5012 5013 drm_reset_display_info(connector); 5014 5015 info->width_mm = edid->width_cm * 10; 5016 info->height_mm = edid->height_cm * 10; 5017 5018 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5019 5020 drm_get_monitor_range(connector, edid); 5021 5022 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5023 5024 if (edid->revision < 3) 5025 return quirks; 5026 5027 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5028 return quirks; 5029 5030 drm_parse_cea_ext(connector, edid); 5031 5032 /* 5033 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5034 * 5035 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5036 * tells us to assume 8 bpc color depth if the EDID doesn't have 5037 * extensions which tell otherwise. 5038 */ 5039 if (info->bpc == 0 && edid->revision == 3 && 5040 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5041 info->bpc = 8; 5042 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5043 connector->name, info->bpc); 5044 } 5045 5046 /* Only defined for 1.4 with digital displays */ 5047 if (edid->revision < 4) 5048 return quirks; 5049 5050 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5051 case DRM_EDID_DIGITAL_DEPTH_6: 5052 info->bpc = 6; 5053 break; 5054 case DRM_EDID_DIGITAL_DEPTH_8: 5055 info->bpc = 8; 5056 break; 5057 case DRM_EDID_DIGITAL_DEPTH_10: 5058 info->bpc = 10; 5059 break; 5060 case DRM_EDID_DIGITAL_DEPTH_12: 5061 info->bpc = 12; 5062 break; 5063 case DRM_EDID_DIGITAL_DEPTH_14: 5064 info->bpc = 14; 5065 break; 5066 case DRM_EDID_DIGITAL_DEPTH_16: 5067 info->bpc = 16; 5068 break; 5069 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5070 default: 5071 info->bpc = 0; 5072 break; 5073 } 5074 5075 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5076 connector->name, info->bpc); 5077 5078 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5079 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5080 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5081 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5082 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5083 return quirks; 5084 } 5085 5086 static int validate_displayid(u8 *displayid, int length, int idx) 5087 { 5088 int i; 5089 u8 csum = 0; 5090 struct displayid_hdr *base; 5091 5092 base = (struct displayid_hdr *)&displayid[idx]; 5093 5094 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5095 base->rev, base->bytes, base->prod_id, base->ext_count); 5096 5097 if (base->bytes + 5 > length - idx) 5098 return -EINVAL; 5099 for (i = idx; i <= base->bytes + 5; i++) { 5100 csum += displayid[i]; 5101 } 5102 if (csum) { 5103 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5104 return -EINVAL; 5105 } 5106 return 0; 5107 } 5108 5109 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5110 struct displayid_detailed_timings_1 *timings) 5111 { 5112 struct drm_display_mode *mode; 5113 unsigned pixel_clock = (timings->pixel_clock[0] | 5114 (timings->pixel_clock[1] << 8) | 5115 (timings->pixel_clock[2] << 16)) + 1; 5116 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5117 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5118 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5119 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5120 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5121 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5122 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5123 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5124 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5125 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5126 mode = drm_mode_create(dev); 5127 if (!mode) 5128 return NULL; 5129 5130 mode->clock = pixel_clock * 10; 5131 mode->hdisplay = hactive; 5132 mode->hsync_start = mode->hdisplay + hsync; 5133 mode->hsync_end = mode->hsync_start + hsync_width; 5134 mode->htotal = mode->hdisplay + hblank; 5135 5136 mode->vdisplay = vactive; 5137 mode->vsync_start = mode->vdisplay + vsync; 5138 mode->vsync_end = mode->vsync_start + vsync_width; 5139 mode->vtotal = mode->vdisplay + vblank; 5140 5141 mode->flags = 0; 5142 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5143 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5144 mode->type = DRM_MODE_TYPE_DRIVER; 5145 5146 if (timings->flags & 0x80) 5147 mode->type |= DRM_MODE_TYPE_PREFERRED; 5148 mode->vrefresh = drm_mode_vrefresh(mode); 5149 drm_mode_set_name(mode); 5150 5151 return mode; 5152 } 5153 5154 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5155 struct displayid_block *block) 5156 { 5157 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5158 int i; 5159 int num_timings; 5160 struct drm_display_mode *newmode; 5161 int num_modes = 0; 5162 /* blocks must be multiple of 20 bytes length */ 5163 if (block->num_bytes % 20) 5164 return 0; 5165 5166 num_timings = block->num_bytes / 20; 5167 for (i = 0; i < num_timings; i++) { 5168 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5169 5170 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5171 if (!newmode) 5172 continue; 5173 5174 drm_mode_probed_add(connector, newmode); 5175 num_modes++; 5176 } 5177 return num_modes; 5178 } 5179 5180 static int add_displayid_detailed_modes(struct drm_connector *connector, 5181 struct edid *edid) 5182 { 5183 u8 *displayid; 5184 int ret; 5185 int idx = 1; 5186 int length = EDID_LENGTH; 5187 struct displayid_block *block; 5188 int num_modes = 0; 5189 5190 displayid = drm_find_displayid_extension(edid); 5191 if (!displayid) 5192 return 0; 5193 5194 ret = validate_displayid(displayid, length, idx); 5195 if (ret) 5196 return 0; 5197 5198 idx += sizeof(struct displayid_hdr); 5199 for_each_displayid_db(displayid, block, idx, length) { 5200 switch (block->tag) { 5201 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5202 num_modes += add_displayid_detailed_1_modes(connector, block); 5203 break; 5204 } 5205 } 5206 return num_modes; 5207 } 5208 5209 /** 5210 * drm_add_edid_modes - add modes from EDID data, if available 5211 * @connector: connector we're probing 5212 * @edid: EDID data 5213 * 5214 * Add the specified modes to the connector's mode list. Also fills out the 5215 * &drm_display_info structure and ELD in @connector with any information which 5216 * can be derived from the edid. 5217 * 5218 * Return: The number of modes added or 0 if we couldn't find any. 5219 */ 5220 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5221 { 5222 int num_modes = 0; 5223 u32 quirks; 5224 5225 if (edid == NULL) { 5226 clear_eld(connector); 5227 return 0; 5228 } 5229 if (!drm_edid_is_valid(edid)) { 5230 clear_eld(connector); 5231 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5232 connector->name); 5233 return 0; 5234 } 5235 5236 drm_edid_to_eld(connector, edid); 5237 5238 /* 5239 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5240 * To avoid multiple parsing of same block, lets parse that map 5241 * from sink info, before parsing CEA modes. 5242 */ 5243 quirks = drm_add_display_info(connector, edid); 5244 5245 /* 5246 * EDID spec says modes should be preferred in this order: 5247 * - preferred detailed mode 5248 * - other detailed modes from base block 5249 * - detailed modes from extension blocks 5250 * - CVT 3-byte code modes 5251 * - standard timing codes 5252 * - established timing codes 5253 * - modes inferred from GTF or CVT range information 5254 * 5255 * We get this pretty much right. 5256 * 5257 * XXX order for additional mode types in extension blocks? 5258 */ 5259 num_modes += add_detailed_modes(connector, edid, quirks); 5260 num_modes += add_cvt_modes(connector, edid); 5261 num_modes += add_standard_modes(connector, edid); 5262 num_modes += add_established_modes(connector, edid); 5263 num_modes += add_cea_modes(connector, edid); 5264 num_modes += add_alternate_cea_modes(connector, edid); 5265 num_modes += add_displayid_detailed_modes(connector, edid); 5266 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5267 num_modes += add_inferred_modes(connector, edid); 5268 5269 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5270 edid_fixup_preferred(connector, quirks); 5271 5272 if (quirks & EDID_QUIRK_FORCE_6BPC) 5273 connector->display_info.bpc = 6; 5274 5275 if (quirks & EDID_QUIRK_FORCE_8BPC) 5276 connector->display_info.bpc = 8; 5277 5278 if (quirks & EDID_QUIRK_FORCE_10BPC) 5279 connector->display_info.bpc = 10; 5280 5281 if (quirks & EDID_QUIRK_FORCE_12BPC) 5282 connector->display_info.bpc = 12; 5283 5284 return num_modes; 5285 } 5286 EXPORT_SYMBOL(drm_add_edid_modes); 5287 5288 /** 5289 * drm_add_modes_noedid - add modes for the connectors without EDID 5290 * @connector: connector we're probing 5291 * @hdisplay: the horizontal display limit 5292 * @vdisplay: the vertical display limit 5293 * 5294 * Add the specified modes to the connector's mode list. Only when the 5295 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5296 * 5297 * Return: The number of modes added or 0 if we couldn't find any. 5298 */ 5299 int drm_add_modes_noedid(struct drm_connector *connector, 5300 int hdisplay, int vdisplay) 5301 { 5302 int i, count, num_modes = 0; 5303 struct drm_display_mode *mode; 5304 struct drm_device *dev = connector->dev; 5305 5306 count = ARRAY_SIZE(drm_dmt_modes); 5307 if (hdisplay < 0) 5308 hdisplay = 0; 5309 if (vdisplay < 0) 5310 vdisplay = 0; 5311 5312 for (i = 0; i < count; i++) { 5313 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5314 if (hdisplay && vdisplay) { 5315 /* 5316 * Only when two are valid, they will be used to check 5317 * whether the mode should be added to the mode list of 5318 * the connector. 5319 */ 5320 if (ptr->hdisplay > hdisplay || 5321 ptr->vdisplay > vdisplay) 5322 continue; 5323 } 5324 if (drm_mode_vrefresh(ptr) > 61) 5325 continue; 5326 mode = drm_mode_duplicate(dev, ptr); 5327 if (mode) { 5328 drm_mode_probed_add(connector, mode); 5329 num_modes++; 5330 } 5331 } 5332 return num_modes; 5333 } 5334 EXPORT_SYMBOL(drm_add_modes_noedid); 5335 5336 /** 5337 * drm_set_preferred_mode - Sets the preferred mode of a connector 5338 * @connector: connector whose mode list should be processed 5339 * @hpref: horizontal resolution of preferred mode 5340 * @vpref: vertical resolution of preferred mode 5341 * 5342 * Marks a mode as preferred if it matches the resolution specified by @hpref 5343 * and @vpref. 5344 */ 5345 void drm_set_preferred_mode(struct drm_connector *connector, 5346 int hpref, int vpref) 5347 { 5348 struct drm_display_mode *mode; 5349 5350 list_for_each_entry(mode, &connector->probed_modes, head) { 5351 if (mode->hdisplay == hpref && 5352 mode->vdisplay == vpref) 5353 mode->type |= DRM_MODE_TYPE_PREFERRED; 5354 } 5355 } 5356 EXPORT_SYMBOL(drm_set_preferred_mode); 5357 5358 static bool is_hdmi2_sink(struct drm_connector *connector) 5359 { 5360 /* 5361 * FIXME: sil-sii8620 doesn't have a connector around when 5362 * we need one, so we have to be prepared for a NULL connector. 5363 */ 5364 if (!connector) 5365 return true; 5366 5367 return connector->display_info.hdmi.scdc.supported || 5368 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5369 } 5370 5371 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5372 { 5373 return sink_eotf & BIT(output_eotf); 5374 } 5375 5376 /** 5377 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5378 * HDR metadata from userspace 5379 * @frame: HDMI DRM infoframe 5380 * @conn_state: Connector state containing HDR metadata 5381 * 5382 * Return: 0 on success or a negative error code on failure. 5383 */ 5384 int 5385 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5386 const struct drm_connector_state *conn_state) 5387 { 5388 struct drm_connector *connector; 5389 struct hdr_output_metadata *hdr_metadata; 5390 int err; 5391 5392 if (!frame || !conn_state) 5393 return -EINVAL; 5394 5395 connector = conn_state->connector; 5396 5397 if (!conn_state->hdr_output_metadata) 5398 return -EINVAL; 5399 5400 hdr_metadata = conn_state->hdr_output_metadata->data; 5401 5402 if (!hdr_metadata || !connector) 5403 return -EINVAL; 5404 5405 /* Sink EOTF is Bit map while infoframe is absolute values */ 5406 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5407 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5408 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5409 return -EINVAL; 5410 } 5411 5412 err = hdmi_drm_infoframe_init(frame); 5413 if (err < 0) 5414 return err; 5415 5416 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5417 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5418 5419 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5420 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5421 BUILD_BUG_ON(sizeof(frame->white_point) != 5422 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5423 5424 memcpy(&frame->display_primaries, 5425 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5426 sizeof(frame->display_primaries)); 5427 5428 memcpy(&frame->white_point, 5429 &hdr_metadata->hdmi_metadata_type1.white_point, 5430 sizeof(frame->white_point)); 5431 5432 frame->max_display_mastering_luminance = 5433 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5434 frame->min_display_mastering_luminance = 5435 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5436 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5437 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5438 5439 return 0; 5440 } 5441 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5442 5443 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5444 const struct drm_display_mode *mode) 5445 { 5446 bool has_hdmi_infoframe = connector ? 5447 connector->display_info.has_hdmi_infoframe : false; 5448 5449 if (!has_hdmi_infoframe) 5450 return 0; 5451 5452 /* No HDMI VIC when signalling 3D video format */ 5453 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5454 return 0; 5455 5456 return drm_match_hdmi_mode(mode); 5457 } 5458 5459 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5460 const struct drm_display_mode *mode) 5461 { 5462 u8 vic; 5463 5464 /* 5465 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5466 * we should send its VIC in vendor infoframes, else send the 5467 * VIC in AVI infoframes. Lets check if this mode is present in 5468 * HDMI 1.4b 4K modes 5469 */ 5470 if (drm_mode_hdmi_vic(connector, mode)) 5471 return 0; 5472 5473 vic = drm_match_cea_mode(mode); 5474 5475 /* 5476 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5477 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5478 * have to make sure we dont break HDMI 1.4 sinks. 5479 */ 5480 if (!is_hdmi2_sink(connector) && vic > 64) 5481 return 0; 5482 5483 return vic; 5484 } 5485 5486 /** 5487 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5488 * data from a DRM display mode 5489 * @frame: HDMI AVI infoframe 5490 * @connector: the connector 5491 * @mode: DRM display mode 5492 * 5493 * Return: 0 on success or a negative error code on failure. 5494 */ 5495 int 5496 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5497 struct drm_connector *connector, 5498 const struct drm_display_mode *mode) 5499 { 5500 enum hdmi_picture_aspect picture_aspect; 5501 u8 vic, hdmi_vic; 5502 5503 if (!frame || !mode) 5504 return -EINVAL; 5505 5506 hdmi_avi_infoframe_init(frame); 5507 5508 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5509 frame->pixel_repeat = 1; 5510 5511 vic = drm_mode_cea_vic(connector, mode); 5512 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5513 5514 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5515 5516 /* 5517 * As some drivers don't support atomic, we can't use connector state. 5518 * So just initialize the frame with default values, just the same way 5519 * as it's done with other properties here. 5520 */ 5521 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5522 frame->itc = 0; 5523 5524 /* 5525 * Populate picture aspect ratio from either 5526 * user input (if specified) or from the CEA/HDMI mode lists. 5527 */ 5528 picture_aspect = mode->picture_aspect_ratio; 5529 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5530 if (vic) 5531 picture_aspect = drm_get_cea_aspect_ratio(vic); 5532 else if (hdmi_vic) 5533 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5534 } 5535 5536 /* 5537 * The infoframe can't convey anything but none, 4:3 5538 * and 16:9, so if the user has asked for anything else 5539 * we can only satisfy it by specifying the right VIC. 5540 */ 5541 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5542 if (vic) { 5543 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5544 return -EINVAL; 5545 } else if (hdmi_vic) { 5546 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5547 return -EINVAL; 5548 } else { 5549 return -EINVAL; 5550 } 5551 5552 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5553 } 5554 5555 frame->video_code = vic; 5556 frame->picture_aspect = picture_aspect; 5557 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5558 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5559 5560 return 0; 5561 } 5562 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5563 5564 /* HDMI Colorspace Spec Definitions */ 5565 #define FULL_COLORIMETRY_MASK 0x1FF 5566 #define NORMAL_COLORIMETRY_MASK 0x3 5567 #define EXTENDED_COLORIMETRY_MASK 0x7 5568 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5569 5570 #define C(x) ((x) << 0) 5571 #define EC(x) ((x) << 2) 5572 #define ACE(x) ((x) << 5) 5573 5574 #define HDMI_COLORIMETRY_NO_DATA 0x0 5575 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5576 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5577 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5578 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5579 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5580 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5581 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5582 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5583 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5584 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5585 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5586 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5587 5588 static const u32 hdmi_colorimetry_val[] = { 5589 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5590 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5591 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5592 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5593 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5594 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5595 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5596 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5597 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5598 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5599 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5600 }; 5601 5602 #undef C 5603 #undef EC 5604 #undef ACE 5605 5606 /** 5607 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5608 * colorspace information 5609 * @frame: HDMI AVI infoframe 5610 * @conn_state: connector state 5611 */ 5612 void 5613 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5614 const struct drm_connector_state *conn_state) 5615 { 5616 u32 colorimetry_val; 5617 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5618 5619 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5620 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5621 else 5622 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5623 5624 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5625 /* 5626 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5627 * structure and extend it in drivers/video/hdmi 5628 */ 5629 frame->extended_colorimetry = (colorimetry_val >> 2) & 5630 EXTENDED_COLORIMETRY_MASK; 5631 } 5632 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5633 5634 /** 5635 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5636 * quantization range information 5637 * @frame: HDMI AVI infoframe 5638 * @connector: the connector 5639 * @mode: DRM display mode 5640 * @rgb_quant_range: RGB quantization range (Q) 5641 */ 5642 void 5643 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5644 struct drm_connector *connector, 5645 const struct drm_display_mode *mode, 5646 enum hdmi_quantization_range rgb_quant_range) 5647 { 5648 const struct drm_display_info *info = &connector->display_info; 5649 5650 /* 5651 * CEA-861: 5652 * "A Source shall not send a non-zero Q value that does not correspond 5653 * to the default RGB Quantization Range for the transmitted Picture 5654 * unless the Sink indicates support for the Q bit in a Video 5655 * Capabilities Data Block." 5656 * 5657 * HDMI 2.0 recommends sending non-zero Q when it does match the 5658 * default RGB quantization range for the mode, even when QS=0. 5659 */ 5660 if (info->rgb_quant_range_selectable || 5661 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5662 frame->quantization_range = rgb_quant_range; 5663 else 5664 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5665 5666 /* 5667 * CEA-861-F: 5668 * "When transmitting any RGB colorimetry, the Source should set the 5669 * YQ-field to match the RGB Quantization Range being transmitted 5670 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5671 * set YQ=1) and the Sink shall ignore the YQ-field." 5672 * 5673 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5674 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5675 * good way to tell which version of CEA-861 the sink supports, so 5676 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5677 * on on CEA-861-F. 5678 */ 5679 if (!is_hdmi2_sink(connector) || 5680 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5681 frame->ycc_quantization_range = 5682 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5683 else 5684 frame->ycc_quantization_range = 5685 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5686 } 5687 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5688 5689 /** 5690 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5691 * bar information 5692 * @frame: HDMI AVI infoframe 5693 * @conn_state: connector state 5694 */ 5695 void 5696 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5697 const struct drm_connector_state *conn_state) 5698 { 5699 frame->right_bar = conn_state->tv.margins.right; 5700 frame->left_bar = conn_state->tv.margins.left; 5701 frame->top_bar = conn_state->tv.margins.top; 5702 frame->bottom_bar = conn_state->tv.margins.bottom; 5703 } 5704 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5705 5706 static enum hdmi_3d_structure 5707 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5708 { 5709 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5710 5711 switch (layout) { 5712 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5713 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5714 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5715 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5716 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5717 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5718 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5719 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5720 case DRM_MODE_FLAG_3D_L_DEPTH: 5721 return HDMI_3D_STRUCTURE_L_DEPTH; 5722 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5723 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5724 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5725 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5726 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5727 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5728 default: 5729 return HDMI_3D_STRUCTURE_INVALID; 5730 } 5731 } 5732 5733 /** 5734 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5735 * data from a DRM display mode 5736 * @frame: HDMI vendor infoframe 5737 * @connector: the connector 5738 * @mode: DRM display mode 5739 * 5740 * Note that there's is a need to send HDMI vendor infoframes only when using a 5741 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5742 * function will return -EINVAL, error that can be safely ignored. 5743 * 5744 * Return: 0 on success or a negative error code on failure. 5745 */ 5746 int 5747 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5748 struct drm_connector *connector, 5749 const struct drm_display_mode *mode) 5750 { 5751 /* 5752 * FIXME: sil-sii8620 doesn't have a connector around when 5753 * we need one, so we have to be prepared for a NULL connector. 5754 */ 5755 bool has_hdmi_infoframe = connector ? 5756 connector->display_info.has_hdmi_infoframe : false; 5757 int err; 5758 5759 if (!frame || !mode) 5760 return -EINVAL; 5761 5762 if (!has_hdmi_infoframe) 5763 return -EINVAL; 5764 5765 err = hdmi_vendor_infoframe_init(frame); 5766 if (err < 0) 5767 return err; 5768 5769 /* 5770 * Even if it's not absolutely necessary to send the infoframe 5771 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5772 * know that the sink can handle it. This is based on a 5773 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5774 * have trouble realizing that they shuld switch from 3D to 2D 5775 * mode if the source simply stops sending the infoframe when 5776 * it wants to switch from 3D to 2D. 5777 */ 5778 frame->vic = drm_mode_hdmi_vic(connector, mode); 5779 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5780 5781 return 0; 5782 } 5783 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5784 5785 static int drm_parse_tiled_block(struct drm_connector *connector, 5786 struct displayid_block *block) 5787 { 5788 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5789 u16 w, h; 5790 u8 tile_v_loc, tile_h_loc; 5791 u8 num_v_tile, num_h_tile; 5792 struct drm_tile_group *tg; 5793 5794 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5795 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5796 5797 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5798 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5799 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5800 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5801 5802 connector->has_tile = true; 5803 if (tile->tile_cap & 0x80) 5804 connector->tile_is_single_monitor = true; 5805 5806 connector->num_h_tile = num_h_tile + 1; 5807 connector->num_v_tile = num_v_tile + 1; 5808 connector->tile_h_loc = tile_h_loc; 5809 connector->tile_v_loc = tile_v_loc; 5810 connector->tile_h_size = w + 1; 5811 connector->tile_v_size = h + 1; 5812 5813 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5814 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5815 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5816 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5817 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5818 5819 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5820 if (!tg) { 5821 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5822 } 5823 if (!tg) 5824 return -ENOMEM; 5825 5826 if (connector->tile_group != tg) { 5827 /* if we haven't got a pointer, 5828 take the reference, drop ref to old tile group */ 5829 if (connector->tile_group) { 5830 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5831 } 5832 connector->tile_group = tg; 5833 } else 5834 /* if same tile group, then release the ref we just took. */ 5835 drm_mode_put_tile_group(connector->dev, tg); 5836 return 0; 5837 } 5838 5839 static int drm_parse_display_id(struct drm_connector *connector, 5840 u8 *displayid, int length, 5841 bool is_edid_extension) 5842 { 5843 /* if this is an EDID extension the first byte will be 0x70 */ 5844 int idx = 0; 5845 struct displayid_block *block; 5846 int ret; 5847 5848 if (is_edid_extension) 5849 idx = 1; 5850 5851 ret = validate_displayid(displayid, length, idx); 5852 if (ret) 5853 return ret; 5854 5855 idx += sizeof(struct displayid_hdr); 5856 for_each_displayid_db(displayid, block, idx, length) { 5857 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5858 block->tag, block->rev, block->num_bytes); 5859 5860 switch (block->tag) { 5861 case DATA_BLOCK_TILED_DISPLAY: 5862 ret = drm_parse_tiled_block(connector, block); 5863 if (ret) 5864 return ret; 5865 break; 5866 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5867 /* handled in mode gathering code. */ 5868 break; 5869 case DATA_BLOCK_CTA: 5870 /* handled in the cea parser code. */ 5871 break; 5872 default: 5873 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5874 break; 5875 } 5876 } 5877 return 0; 5878 } 5879 5880 static void drm_get_displayid(struct drm_connector *connector, 5881 struct edid *edid) 5882 { 5883 void *displayid = NULL; 5884 int ret; 5885 connector->has_tile = false; 5886 displayid = drm_find_displayid_extension(edid); 5887 if (!displayid) { 5888 /* drop reference to any tile group we had */ 5889 goto out_drop_ref; 5890 } 5891 5892 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5893 if (ret < 0) 5894 goto out_drop_ref; 5895 if (!connector->has_tile) 5896 goto out_drop_ref; 5897 return; 5898 out_drop_ref: 5899 if (connector->tile_group) { 5900 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5901 connector->tile_group = NULL; 5902 } 5903 return; 5904 } 5905