1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_scdc_helper.h> 41 42 #include "drm_crtc_internal.h" 43 44 #define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48 #define EDID_EST_TIMINGS 16 49 #define EDID_STD_TIMINGS 8 50 #define EDID_DETAILED_TIMINGS 4 51 52 /* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59 /* First detailed mode wrong, use largest 60Hz mode */ 60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61 /* Reported 135MHz pixel clock is too high, needs adjustment */ 62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63 /* Prefer the largest mode at 75 Hz */ 64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65 /* Detail timing is in cm not mm */ 66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67 /* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71 /* Monitor forgot to set the first detailed is preferred bit. */ 72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 73 /* use +hsync +vsync for detailed mode */ 74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 75 /* Force reduced-blanking timings for detailed modes */ 76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 77 /* Force 8bpc */ 78 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 79 /* Force 12bpc */ 80 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 81 /* Force 6bpc */ 82 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 83 /* Force 10bpc */ 84 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 85 86 struct detailed_mode_closure { 87 struct drm_connector *connector; 88 struct edid *edid; 89 bool preferred; 90 u32 quirks; 91 int modes; 92 }; 93 94 #define LEVEL_DMT 0 95 #define LEVEL_GTF 1 96 #define LEVEL_GTF2 2 97 #define LEVEL_CVT 3 98 99 static const struct edid_quirk { 100 char vendor[4]; 101 int product_id; 102 u32 quirks; 103 } edid_quirk_list[] = { 104 /* Acer AL1706 */ 105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 106 /* Acer F51 */ 107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Unknown Acer */ 109 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 110 111 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 112 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 113 114 /* Belinea 10 15 55 */ 115 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 116 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 117 118 /* Envision Peripherals, Inc. EN-7100e */ 119 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 120 /* Envision EN2028 */ 121 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 122 123 /* Funai Electronics PM36B */ 124 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 125 EDID_QUIRK_DETAILED_IN_CM }, 126 127 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 128 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 129 130 /* LG Philips LCD LP154W01-A5 */ 131 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 132 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 133 134 /* Philips 107p5 CRT */ 135 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 136 137 /* Proview AY765C */ 138 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 139 140 /* Samsung SyncMaster 205BW. Note: irony */ 141 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 142 /* Samsung SyncMaster 22[5-6]BW */ 143 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 144 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 145 146 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 147 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 148 149 /* ViewSonic VA2026w */ 150 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 151 152 /* Medion MD 30217 PG */ 153 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 154 155 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 156 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 157 158 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 159 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 160 }; 161 162 /* 163 * Autogenerated from the DMT spec. 164 * This table is copied from xfree86/modes/xf86EdidModes.c. 165 */ 166 static const struct drm_display_mode drm_dmt_modes[] = { 167 /* 0x01 - 640x350@85Hz */ 168 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 169 736, 832, 0, 350, 382, 385, 445, 0, 170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 171 /* 0x02 - 640x400@85Hz */ 172 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 173 736, 832, 0, 400, 401, 404, 445, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 175 /* 0x03 - 720x400@85Hz */ 176 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 177 828, 936, 0, 400, 401, 404, 446, 0, 178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 179 /* 0x04 - 640x480@60Hz */ 180 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 181 752, 800, 0, 480, 490, 492, 525, 0, 182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 183 /* 0x05 - 640x480@72Hz */ 184 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 185 704, 832, 0, 480, 489, 492, 520, 0, 186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 187 /* 0x06 - 640x480@75Hz */ 188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 189 720, 840, 0, 480, 481, 484, 500, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 191 /* 0x07 - 640x480@85Hz */ 192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 193 752, 832, 0, 480, 481, 484, 509, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 195 /* 0x08 - 800x600@56Hz */ 196 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 197 896, 1024, 0, 600, 601, 603, 625, 0, 198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 199 /* 0x09 - 800x600@60Hz */ 200 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 201 968, 1056, 0, 600, 601, 605, 628, 0, 202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 203 /* 0x0a - 800x600@72Hz */ 204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 205 976, 1040, 0, 600, 637, 643, 666, 0, 206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 207 /* 0x0b - 800x600@75Hz */ 208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 209 896, 1056, 0, 600, 601, 604, 625, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x0c - 800x600@85Hz */ 212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 213 896, 1048, 0, 600, 601, 604, 631, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 0x0d - 800x600@120Hz RB */ 216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 217 880, 960, 0, 600, 603, 607, 636, 0, 218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 0x0e - 848x480@60Hz */ 220 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 221 976, 1088, 0, 480, 486, 494, 517, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 0x0f - 1024x768@43Hz, interlace */ 224 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 225 1208, 1264, 0, 768, 768, 776, 817, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 227 DRM_MODE_FLAG_INTERLACE) }, 228 /* 0x10 - 1024x768@60Hz */ 229 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 230 1184, 1344, 0, 768, 771, 777, 806, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 232 /* 0x11 - 1024x768@70Hz */ 233 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 234 1184, 1328, 0, 768, 771, 777, 806, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 236 /* 0x12 - 1024x768@75Hz */ 237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 238 1136, 1312, 0, 768, 769, 772, 800, 0, 239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 240 /* 0x13 - 1024x768@85Hz */ 241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 242 1168, 1376, 0, 768, 769, 772, 808, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 244 /* 0x14 - 1024x768@120Hz RB */ 245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 246 1104, 1184, 0, 768, 771, 775, 813, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x15 - 1152x864@75Hz */ 249 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 250 1344, 1600, 0, 864, 865, 868, 900, 0, 251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x55 - 1280x720@60Hz */ 253 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 254 1430, 1650, 0, 720, 725, 730, 750, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x16 - 1280x768@60Hz RB */ 257 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 258 1360, 1440, 0, 768, 771, 778, 790, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x17 - 1280x768@60Hz */ 261 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 262 1472, 1664, 0, 768, 771, 778, 798, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x18 - 1280x768@75Hz */ 265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 266 1488, 1696, 0, 768, 771, 778, 805, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x19 - 1280x768@85Hz */ 269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 270 1496, 1712, 0, 768, 771, 778, 809, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x1a - 1280x768@120Hz RB */ 273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 274 1360, 1440, 0, 768, 771, 778, 813, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x1b - 1280x800@60Hz RB */ 277 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 278 1360, 1440, 0, 800, 803, 809, 823, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 280 /* 0x1c - 1280x800@60Hz */ 281 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 282 1480, 1680, 0, 800, 803, 809, 831, 0, 283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x1d - 1280x800@75Hz */ 285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 286 1488, 1696, 0, 800, 803, 809, 838, 0, 287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x1e - 1280x800@85Hz */ 289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 290 1496, 1712, 0, 800, 803, 809, 843, 0, 291 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x1f - 1280x800@120Hz RB */ 293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 294 1360, 1440, 0, 800, 803, 809, 847, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x20 - 1280x960@60Hz */ 297 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 298 1488, 1800, 0, 960, 961, 964, 1000, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x21 - 1280x960@85Hz */ 301 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 302 1504, 1728, 0, 960, 961, 964, 1011, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x22 - 1280x960@120Hz RB */ 305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 306 1360, 1440, 0, 960, 963, 967, 1017, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 308 /* 0x23 - 1280x1024@60Hz */ 309 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 310 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 312 /* 0x24 - 1280x1024@75Hz */ 313 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 314 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x25 - 1280x1024@85Hz */ 317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 318 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x26 - 1280x1024@120Hz RB */ 321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 322 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 324 /* 0x27 - 1360x768@60Hz */ 325 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 326 1536, 1792, 0, 768, 771, 777, 795, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x28 - 1360x768@120Hz RB */ 329 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 330 1440, 1520, 0, 768, 771, 776, 813, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 332 /* 0x51 - 1366x768@60Hz */ 333 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 334 1579, 1792, 0, 768, 771, 774, 798, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x56 - 1366x768@60Hz */ 337 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 338 1436, 1500, 0, 768, 769, 772, 800, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 0x29 - 1400x1050@60Hz RB */ 341 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 342 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 344 /* 0x2a - 1400x1050@60Hz */ 345 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 346 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x2b - 1400x1050@75Hz */ 349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 350 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x2c - 1400x1050@85Hz */ 353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 354 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x2d - 1400x1050@120Hz RB */ 357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 358 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x2e - 1440x900@60Hz RB */ 361 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 362 1520, 1600, 0, 900, 903, 909, 926, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 364 /* 0x2f - 1440x900@60Hz */ 365 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 366 1672, 1904, 0, 900, 903, 909, 934, 0, 367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x30 - 1440x900@75Hz */ 369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 370 1688, 1936, 0, 900, 903, 909, 942, 0, 371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x31 - 1440x900@85Hz */ 373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 374 1696, 1952, 0, 900, 903, 909, 948, 0, 375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x32 - 1440x900@120Hz RB */ 377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 378 1520, 1600, 0, 900, 903, 909, 953, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 380 /* 0x53 - 1600x900@60Hz */ 381 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 382 1704, 1800, 0, 900, 901, 904, 1000, 0, 383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x33 - 1600x1200@60Hz */ 385 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 386 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x34 - 1600x1200@65Hz */ 389 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 390 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x35 - 1600x1200@70Hz */ 393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 396 /* 0x36 - 1600x1200@75Hz */ 397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x37 - 1600x1200@85Hz */ 401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x38 - 1600x1200@120Hz RB */ 405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 406 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 408 /* 0x39 - 1680x1050@60Hz RB */ 409 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 410 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 412 /* 0x3a - 1680x1050@60Hz */ 413 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 414 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x3b - 1680x1050@75Hz */ 417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 418 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x3c - 1680x1050@85Hz */ 421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 422 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 424 /* 0x3d - 1680x1050@120Hz RB */ 425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 426 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 428 /* 0x3e - 1792x1344@60Hz */ 429 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 430 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x3f - 1792x1344@75Hz */ 433 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 434 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x40 - 1792x1344@120Hz RB */ 437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 438 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 0x41 - 1856x1392@60Hz */ 441 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 442 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 444 /* 0x42 - 1856x1392@75Hz */ 445 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 446 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x43 - 1856x1392@120Hz RB */ 449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 450 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 452 /* 0x52 - 1920x1080@60Hz */ 453 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 454 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 456 /* 0x44 - 1920x1200@60Hz RB */ 457 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 458 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 460 /* 0x45 - 1920x1200@60Hz */ 461 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 462 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 464 /* 0x46 - 1920x1200@75Hz */ 465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 466 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x47 - 1920x1200@85Hz */ 469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 470 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x48 - 1920x1200@120Hz RB */ 473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 474 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 476 /* 0x49 - 1920x1440@60Hz */ 477 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 478 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x4a - 1920x1440@75Hz */ 481 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 482 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x4b - 1920x1440@120Hz RB */ 485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 486 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 488 /* 0x54 - 2048x1152@60Hz */ 489 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 490 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 492 /* 0x4c - 2560x1600@60Hz RB */ 493 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 494 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 496 /* 0x4d - 2560x1600@60Hz */ 497 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 498 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x4e - 2560x1600@75Hz */ 501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 502 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x4f - 2560x1600@85Hz */ 505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 506 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 508 /* 0x50 - 2560x1600@120Hz RB */ 509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 510 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 512 /* 0x57 - 4096x2160@60Hz RB */ 513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 514 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 516 /* 0x58 - 4096x2160@59.94Hz RB */ 517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 518 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 }; 521 522 /* 523 * These more or less come from the DMT spec. The 720x400 modes are 524 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 525 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 526 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 527 * mode. 528 * 529 * The DMT modes have been fact-checked; the rest are mild guesses. 530 */ 531 static const struct drm_display_mode edid_est_modes[] = { 532 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 533 968, 1056, 0, 600, 601, 605, 628, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 535 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 536 896, 1024, 0, 600, 601, 603, 625, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 539 720, 840, 0, 480, 481, 484, 500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 541 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 542 704, 832, 0, 480, 489, 492, 520, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 544 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 545 768, 864, 0, 480, 483, 486, 525, 0, 546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 547 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 548 752, 800, 0, 480, 490, 492, 525, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 550 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 551 846, 900, 0, 400, 421, 423, 449, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 553 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 554 846, 900, 0, 400, 412, 414, 449, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 556 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 557 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 559 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 560 1136, 1312, 0, 768, 769, 772, 800, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 562 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 563 1184, 1328, 0, 768, 771, 777, 806, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 565 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 566 1184, 1344, 0, 768, 771, 777, 806, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 568 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 569 1208, 1264, 0, 768, 768, 776, 817, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 571 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 572 928, 1152, 0, 624, 625, 628, 667, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 574 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 575 896, 1056, 0, 600, 601, 604, 625, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 577 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 578 976, 1040, 0, 600, 637, 643, 666, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 580 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 581 1344, 1600, 0, 864, 865, 868, 900, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 583 }; 584 585 struct minimode { 586 short w; 587 short h; 588 short r; 589 short rb; 590 }; 591 592 static const struct minimode est3_modes[] = { 593 /* byte 6 */ 594 { 640, 350, 85, 0 }, 595 { 640, 400, 85, 0 }, 596 { 720, 400, 85, 0 }, 597 { 640, 480, 85, 0 }, 598 { 848, 480, 60, 0 }, 599 { 800, 600, 85, 0 }, 600 { 1024, 768, 85, 0 }, 601 { 1152, 864, 75, 0 }, 602 /* byte 7 */ 603 { 1280, 768, 60, 1 }, 604 { 1280, 768, 60, 0 }, 605 { 1280, 768, 75, 0 }, 606 { 1280, 768, 85, 0 }, 607 { 1280, 960, 60, 0 }, 608 { 1280, 960, 85, 0 }, 609 { 1280, 1024, 60, 0 }, 610 { 1280, 1024, 85, 0 }, 611 /* byte 8 */ 612 { 1360, 768, 60, 0 }, 613 { 1440, 900, 60, 1 }, 614 { 1440, 900, 60, 0 }, 615 { 1440, 900, 75, 0 }, 616 { 1440, 900, 85, 0 }, 617 { 1400, 1050, 60, 1 }, 618 { 1400, 1050, 60, 0 }, 619 { 1400, 1050, 75, 0 }, 620 /* byte 9 */ 621 { 1400, 1050, 85, 0 }, 622 { 1680, 1050, 60, 1 }, 623 { 1680, 1050, 60, 0 }, 624 { 1680, 1050, 75, 0 }, 625 { 1680, 1050, 85, 0 }, 626 { 1600, 1200, 60, 0 }, 627 { 1600, 1200, 65, 0 }, 628 { 1600, 1200, 70, 0 }, 629 /* byte 10 */ 630 { 1600, 1200, 75, 0 }, 631 { 1600, 1200, 85, 0 }, 632 { 1792, 1344, 60, 0 }, 633 { 1792, 1344, 75, 0 }, 634 { 1856, 1392, 60, 0 }, 635 { 1856, 1392, 75, 0 }, 636 { 1920, 1200, 60, 1 }, 637 { 1920, 1200, 60, 0 }, 638 /* byte 11 */ 639 { 1920, 1200, 75, 0 }, 640 { 1920, 1200, 85, 0 }, 641 { 1920, 1440, 60, 0 }, 642 { 1920, 1440, 75, 0 }, 643 }; 644 645 static const struct minimode extra_modes[] = { 646 { 1024, 576, 60, 0 }, 647 { 1366, 768, 60, 0 }, 648 { 1600, 900, 60, 0 }, 649 { 1680, 945, 60, 0 }, 650 { 1920, 1080, 60, 0 }, 651 { 2048, 1152, 60, 0 }, 652 { 2048, 1536, 60, 0 }, 653 }; 654 655 /* 656 * Probably taken from CEA-861 spec. 657 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 658 * 659 * Index using the VIC. 660 */ 661 static const struct drm_display_mode edid_cea_modes[] = { 662 /* 0 - dummy, VICs start at 1 */ 663 { }, 664 /* 1 - 640x480@60Hz */ 665 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 666 752, 800, 0, 480, 490, 492, 525, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 669 /* 2 - 720x480@60Hz */ 670 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 671 798, 858, 0, 480, 489, 495, 525, 0, 672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 674 /* 3 - 720x480@60Hz */ 675 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 676 798, 858, 0, 480, 489, 495, 525, 0, 677 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 679 /* 4 - 1280x720@60Hz */ 680 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 681 1430, 1650, 0, 720, 725, 730, 750, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 684 /* 5 - 1920x1080i@60Hz */ 685 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 686 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 688 DRM_MODE_FLAG_INTERLACE), 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 690 /* 6 - 720(1440)x480i@60Hz */ 691 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 692 801, 858, 0, 480, 488, 494, 525, 0, 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 694 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 696 /* 7 - 720(1440)x480i@60Hz */ 697 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 698 801, 858, 0, 480, 488, 494, 525, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 700 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 702 /* 8 - 720(1440)x240@60Hz */ 703 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 704 801, 858, 0, 240, 244, 247, 262, 0, 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 706 DRM_MODE_FLAG_DBLCLK), 707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 708 /* 9 - 720(1440)x240@60Hz */ 709 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 710 801, 858, 0, 240, 244, 247, 262, 0, 711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 712 DRM_MODE_FLAG_DBLCLK), 713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 714 /* 10 - 2880x480i@60Hz */ 715 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 716 3204, 3432, 0, 480, 488, 494, 525, 0, 717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 718 DRM_MODE_FLAG_INTERLACE), 719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 720 /* 11 - 2880x480i@60Hz */ 721 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 722 3204, 3432, 0, 480, 488, 494, 525, 0, 723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 724 DRM_MODE_FLAG_INTERLACE), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 12 - 2880x240@60Hz */ 727 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 728 3204, 3432, 0, 240, 244, 247, 262, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 13 - 2880x240@60Hz */ 732 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 733 3204, 3432, 0, 240, 244, 247, 262, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 14 - 1440x480@60Hz */ 737 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 738 1596, 1716, 0, 480, 489, 495, 525, 0, 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 741 /* 15 - 1440x480@60Hz */ 742 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 743 1596, 1716, 0, 480, 489, 495, 525, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 16 - 1920x1080@60Hz */ 747 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 748 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 17 - 720x576@50Hz */ 752 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 753 796, 864, 0, 576, 581, 586, 625, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 756 /* 18 - 720x576@50Hz */ 757 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 758 796, 864, 0, 576, 581, 586, 625, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 19 - 1280x720@50Hz */ 762 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 763 1760, 1980, 0, 720, 725, 730, 750, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 766 /* 20 - 1920x1080i@50Hz */ 767 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 768 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 770 DRM_MODE_FLAG_INTERLACE), 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 772 /* 21 - 720(1440)x576i@50Hz */ 773 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 774 795, 864, 0, 576, 580, 586, 625, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 776 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 778 /* 22 - 720(1440)x576i@50Hz */ 779 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 780 795, 864, 0, 576, 580, 586, 625, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 784 /* 23 - 720(1440)x288@50Hz */ 785 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 786 795, 864, 0, 288, 290, 293, 312, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_DBLCLK), 789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 790 /* 24 - 720(1440)x288@50Hz */ 791 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 792 795, 864, 0, 288, 290, 293, 312, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 794 DRM_MODE_FLAG_DBLCLK), 795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 796 /* 25 - 2880x576i@50Hz */ 797 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 798 3180, 3456, 0, 576, 580, 586, 625, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 800 DRM_MODE_FLAG_INTERLACE), 801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 26 - 2880x576i@50Hz */ 803 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 804 3180, 3456, 0, 576, 580, 586, 625, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 806 DRM_MODE_FLAG_INTERLACE), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 27 - 2880x288@50Hz */ 809 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 810 3180, 3456, 0, 288, 290, 293, 312, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 813 /* 28 - 2880x288@50Hz */ 814 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 815 3180, 3456, 0, 288, 290, 293, 312, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 29 - 1440x576@50Hz */ 819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 820 1592, 1728, 0, 576, 581, 586, 625, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 823 /* 30 - 1440x576@50Hz */ 824 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 825 1592, 1728, 0, 576, 581, 586, 625, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 31 - 1920x1080@50Hz */ 829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 32 - 1920x1080@24Hz */ 834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 835 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 837 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 33 - 1920x1080@25Hz */ 839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 840 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 842 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 34 - 1920x1080@30Hz */ 844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 845 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 847 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 35 - 2880x480@60Hz */ 849 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 850 3192, 3432, 0, 480, 489, 495, 525, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 852 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 36 - 2880x480@60Hz */ 854 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 855 3192, 3432, 0, 480, 489, 495, 525, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 37 - 2880x576@50Hz */ 859 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 860 3184, 3456, 0, 576, 581, 586, 625, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 863 /* 38 - 2880x576@50Hz */ 864 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 865 3184, 3456, 0, 576, 581, 586, 625, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 868 /* 39 - 1920x1080i@50Hz */ 869 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 870 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 872 DRM_MODE_FLAG_INTERLACE), 873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 40 - 1920x1080i@100Hz */ 875 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 876 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 878 DRM_MODE_FLAG_INTERLACE), 879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 880 /* 41 - 1280x720@100Hz */ 881 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 882 1760, 1980, 0, 720, 725, 730, 750, 0, 883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 42 - 720x576@100Hz */ 886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 887 796, 864, 0, 576, 581, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 43 - 720x576@100Hz */ 891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 892 796, 864, 0, 576, 581, 586, 625, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 44 - 720(1440)x576i@100Hz */ 896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 897 795, 864, 0, 576, 580, 586, 625, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 900 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 901 /* 45 - 720(1440)x576i@100Hz */ 902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 903 795, 864, 0, 576, 580, 586, 625, 0, 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 906 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 46 - 1920x1080i@120Hz */ 908 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 909 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 911 DRM_MODE_FLAG_INTERLACE), 912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 47 - 1280x720@120Hz */ 914 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 915 1430, 1650, 0, 720, 725, 730, 750, 0, 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 918 /* 48 - 720x480@120Hz */ 919 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 920 798, 858, 0, 480, 489, 495, 525, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 923 /* 49 - 720x480@120Hz */ 924 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 925 798, 858, 0, 480, 489, 495, 525, 0, 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 50 - 720(1440)x480i@120Hz */ 929 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 930 801, 858, 0, 480, 488, 494, 525, 0, 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 933 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 934 /* 51 - 720(1440)x480i@120Hz */ 935 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 936 801, 858, 0, 480, 488, 494, 525, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 938 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 939 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 52 - 720x576@200Hz */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 53 - 720x576@200Hz */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 54 - 720(1440)x576i@200Hz */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 55 - 720(1440)x576i@200Hz */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 56 - 720x480@240Hz */ 963 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 964 798, 858, 0, 480, 489, 495, 525, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 967 /* 57 - 720x480@240Hz */ 968 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 969 798, 858, 0, 480, 489, 495, 525, 0, 970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 58 - 720(1440)x480i@240Hz */ 973 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 974 801, 858, 0, 480, 488, 494, 525, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 59 - 720(1440)x480i@240Hz */ 979 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 980 801, 858, 0, 480, 488, 494, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 983 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 60 - 1280x720@24Hz */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 986 3080, 3300, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 61 - 1280x720@25Hz */ 990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 991 3740, 3960, 0, 720, 725, 730, 750, 0, 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 993 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 62 - 1280x720@30Hz */ 995 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 996 3080, 3300, 0, 720, 725, 730, 750, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 998 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 63 - 1920x1080@120Hz */ 1000 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1001 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1003 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 64 - 1920x1080@100Hz */ 1005 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1006 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1008 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1009 /* 65 - 1280x720@24Hz */ 1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1011 3080, 3300, 0, 720, 725, 730, 750, 0, 1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1013 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1014 /* 66 - 1280x720@25Hz */ 1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1016 3740, 3960, 0, 720, 725, 730, 750, 0, 1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1018 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1019 /* 67 - 1280x720@30Hz */ 1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1021 3080, 3300, 0, 720, 725, 730, 750, 0, 1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1023 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1024 /* 68 - 1280x720@50Hz */ 1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1026 1760, 1980, 0, 720, 725, 730, 750, 0, 1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1028 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1029 /* 69 - 1280x720@60Hz */ 1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1031 1430, 1650, 0, 720, 725, 730, 750, 0, 1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1033 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1034 /* 70 - 1280x720@100Hz */ 1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1036 1760, 1980, 0, 720, 725, 730, 750, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1038 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1039 /* 71 - 1280x720@120Hz */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1041 1430, 1650, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1044 /* 72 - 1920x1080@24Hz */ 1045 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1046 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1049 /* 73 - 1920x1080@25Hz */ 1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1051 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1054 /* 74 - 1920x1080@30Hz */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1059 /* 75 - 1920x1080@50Hz */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1064 /* 76 - 1920x1080@60Hz */ 1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1066 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 77 - 1920x1080@100Hz */ 1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1071 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 78 - 1920x1080@120Hz */ 1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1076 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 79 - 1680x720@24Hz */ 1080 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1081 3080, 3300, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 80 - 1680x720@25Hz */ 1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1086 2948, 3168, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 81 - 1680x720@30Hz */ 1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1091 2420, 2640, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 82 - 1680x720@50Hz */ 1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1096 1980, 2200, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 83 - 1680x720@60Hz */ 1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1101 1980, 2200, 0, 720, 725, 730, 750, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 84 - 1680x720@100Hz */ 1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1106 1780, 2000, 0, 720, 725, 730, 825, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 85 - 1680x720@120Hz */ 1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1111 1780, 2000, 0, 720, 725, 730, 825, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 86 - 2560x1080@24Hz */ 1115 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1116 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 87 - 2560x1080@25Hz */ 1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1121 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 88 - 2560x1080@30Hz */ 1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1126 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 89 - 2560x1080@50Hz */ 1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1131 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 90 - 2560x1080@60Hz */ 1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1136 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 91 - 2560x1080@100Hz */ 1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1141 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 92 - 2560x1080@120Hz */ 1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1146 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 93 - 3840x2160p@24Hz 16:9 */ 1150 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1151 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1154 /* 94 - 3840x2160p@25Hz 16:9 */ 1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1156 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1159 /* 95 - 3840x2160p@30Hz 16:9 */ 1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1161 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1164 /* 96 - 3840x2160p@50Hz 16:9 */ 1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1166 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1169 /* 97 - 3840x2160p@60Hz 16:9 */ 1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1171 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1174 /* 98 - 4096x2160p@24Hz 256:135 */ 1175 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1176 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1179 /* 99 - 4096x2160p@25Hz 256:135 */ 1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1181 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1184 /* 100 - 4096x2160p@30Hz 256:135 */ 1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1186 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1189 /* 101 - 4096x2160p@50Hz 256:135 */ 1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1191 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1194 /* 102 - 4096x2160p@60Hz 256:135 */ 1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1196 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1199 /* 103 - 3840x2160p@24Hz 64:27 */ 1200 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1201 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 104 - 3840x2160p@25Hz 64:27 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1206 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1209 /* 105 - 3840x2160p@30Hz 64:27 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1211 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1214 /* 106 - 3840x2160p@50Hz 64:27 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1216 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1219 /* 107 - 3840x2160p@60Hz 64:27 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1221 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1224 }; 1225 1226 /* 1227 * HDMI 1.4 4k modes. Index using the VIC. 1228 */ 1229 static const struct drm_display_mode edid_4k_modes[] = { 1230 /* 0 - dummy, VICs start at 1 */ 1231 { }, 1232 /* 1 - 3840x2160@30Hz */ 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1234 3840, 4016, 4104, 4400, 0, 1235 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 30, }, 1238 /* 2 - 3840x2160@25Hz */ 1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1240 3840, 4896, 4984, 5280, 0, 1241 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .vrefresh = 25, }, 1244 /* 3 - 3840x2160@24Hz */ 1245 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1246 3840, 5116, 5204, 5500, 0, 1247 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .vrefresh = 24, }, 1250 /* 4 - 4096x2160@24Hz (SMPTE) */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1252 4096, 5116, 5204, 5500, 0, 1253 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .vrefresh = 24, }, 1256 }; 1257 1258 /*** DDC fetch and block validation ***/ 1259 1260 static const u8 edid_header[] = { 1261 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1262 }; 1263 1264 /** 1265 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1266 * @raw_edid: pointer to raw base EDID block 1267 * 1268 * Sanity check the header of the base EDID block. 1269 * 1270 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1271 */ 1272 int drm_edid_header_is_valid(const u8 *raw_edid) 1273 { 1274 int i, score = 0; 1275 1276 for (i = 0; i < sizeof(edid_header); i++) 1277 if (raw_edid[i] == edid_header[i]) 1278 score++; 1279 1280 return score; 1281 } 1282 EXPORT_SYMBOL(drm_edid_header_is_valid); 1283 1284 static int edid_fixup __read_mostly = 6; 1285 module_param_named(edid_fixup, edid_fixup, int, 0400); 1286 MODULE_PARM_DESC(edid_fixup, 1287 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1288 1289 static void drm_get_displayid(struct drm_connector *connector, 1290 struct edid *edid); 1291 1292 static int drm_edid_block_checksum(const u8 *raw_edid) 1293 { 1294 int i; 1295 u8 csum = 0; 1296 for (i = 0; i < EDID_LENGTH; i++) 1297 csum += raw_edid[i]; 1298 1299 return csum; 1300 } 1301 1302 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1303 { 1304 if (memchr_inv(in_edid, 0, length)) 1305 return false; 1306 1307 return true; 1308 } 1309 1310 /** 1311 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1312 * @raw_edid: pointer to raw EDID block 1313 * @block: type of block to validate (0 for base, extension otherwise) 1314 * @print_bad_edid: if true, dump bad EDID blocks to the console 1315 * @edid_corrupt: if true, the header or checksum is invalid 1316 * 1317 * Validate a base or extension EDID block and optionally dump bad blocks to 1318 * the console. 1319 * 1320 * Return: True if the block is valid, false otherwise. 1321 */ 1322 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1323 bool *edid_corrupt) 1324 { 1325 u8 csum; 1326 struct edid *edid = (struct edid *)raw_edid; 1327 1328 if (WARN_ON(!raw_edid)) 1329 return false; 1330 1331 if (edid_fixup > 8 || edid_fixup < 0) 1332 edid_fixup = 6; 1333 1334 if (block == 0) { 1335 int score = drm_edid_header_is_valid(raw_edid); 1336 if (score == 8) { 1337 if (edid_corrupt) 1338 *edid_corrupt = false; 1339 } else if (score >= edid_fixup) { 1340 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1341 * The corrupt flag needs to be set here otherwise, the 1342 * fix-up code here will correct the problem, the 1343 * checksum is correct and the test fails 1344 */ 1345 if (edid_corrupt) 1346 *edid_corrupt = true; 1347 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1348 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1349 } else { 1350 if (edid_corrupt) 1351 *edid_corrupt = true; 1352 goto bad; 1353 } 1354 } 1355 1356 csum = drm_edid_block_checksum(raw_edid); 1357 if (csum) { 1358 if (edid_corrupt) 1359 *edid_corrupt = true; 1360 1361 /* allow CEA to slide through, switches mangle this */ 1362 if (raw_edid[0] == CEA_EXT) { 1363 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1364 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1365 } else { 1366 if (print_bad_edid) 1367 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1368 1369 goto bad; 1370 } 1371 } 1372 1373 /* per-block-type checks */ 1374 switch (raw_edid[0]) { 1375 case 0: /* base */ 1376 if (edid->version != 1) { 1377 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1378 goto bad; 1379 } 1380 1381 if (edid->revision > 4) 1382 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1383 break; 1384 1385 default: 1386 break; 1387 } 1388 1389 return true; 1390 1391 bad: 1392 if (print_bad_edid) { 1393 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1394 pr_notice("EDID block is all zeroes\n"); 1395 } else { 1396 pr_notice("Raw EDID:\n"); 1397 print_hex_dump(KERN_NOTICE, 1398 " \t", DUMP_PREFIX_NONE, 16, 1, 1399 raw_edid, EDID_LENGTH, false); 1400 } 1401 } 1402 return false; 1403 } 1404 EXPORT_SYMBOL(drm_edid_block_valid); 1405 1406 /** 1407 * drm_edid_is_valid - sanity check EDID data 1408 * @edid: EDID data 1409 * 1410 * Sanity-check an entire EDID record (including extensions) 1411 * 1412 * Return: True if the EDID data is valid, false otherwise. 1413 */ 1414 bool drm_edid_is_valid(struct edid *edid) 1415 { 1416 int i; 1417 u8 *raw = (u8 *)edid; 1418 1419 if (!edid) 1420 return false; 1421 1422 for (i = 0; i <= edid->extensions; i++) 1423 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1424 return false; 1425 1426 return true; 1427 } 1428 EXPORT_SYMBOL(drm_edid_is_valid); 1429 1430 #define DDC_SEGMENT_ADDR 0x30 1431 /** 1432 * drm_do_probe_ddc_edid() - get EDID information via I2C 1433 * @data: I2C device adapter 1434 * @buf: EDID data buffer to be filled 1435 * @block: 128 byte EDID block to start fetching from 1436 * @len: EDID data buffer length to fetch 1437 * 1438 * Try to fetch EDID information by calling I2C driver functions. 1439 * 1440 * Return: 0 on success or -1 on failure. 1441 */ 1442 static int 1443 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1444 { 1445 struct i2c_adapter *adapter = data; 1446 unsigned char start = block * EDID_LENGTH; 1447 unsigned char segment = block >> 1; 1448 unsigned char xfers = segment ? 3 : 2; 1449 int ret, retries = 5; 1450 1451 /* 1452 * The core I2C driver will automatically retry the transfer if the 1453 * adapter reports EAGAIN. However, we find that bit-banging transfers 1454 * are susceptible to errors under a heavily loaded machine and 1455 * generate spurious NAKs and timeouts. Retrying the transfer 1456 * of the individual block a few times seems to overcome this. 1457 */ 1458 do { 1459 struct i2c_msg msgs[] = { 1460 { 1461 .addr = DDC_SEGMENT_ADDR, 1462 .flags = 0, 1463 .len = 1, 1464 .buf = &segment, 1465 }, { 1466 .addr = DDC_ADDR, 1467 .flags = 0, 1468 .len = 1, 1469 .buf = &start, 1470 }, { 1471 .addr = DDC_ADDR, 1472 .flags = I2C_M_RD, 1473 .len = len, 1474 .buf = buf, 1475 } 1476 }; 1477 1478 /* 1479 * Avoid sending the segment addr to not upset non-compliant 1480 * DDC monitors. 1481 */ 1482 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1483 1484 if (ret == -ENXIO) { 1485 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1486 adapter->name); 1487 break; 1488 } 1489 } while (ret != xfers && --retries); 1490 1491 return ret == xfers ? 0 : -1; 1492 } 1493 1494 static void connector_bad_edid(struct drm_connector *connector, 1495 u8 *edid, int num_blocks) 1496 { 1497 int i; 1498 1499 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1500 return; 1501 1502 dev_warn(connector->dev->dev, 1503 "%s: EDID is invalid:\n", 1504 connector->name); 1505 for (i = 0; i < num_blocks; i++) { 1506 u8 *block = edid + i * EDID_LENGTH; 1507 char prefix[20]; 1508 1509 if (drm_edid_is_zero(block, EDID_LENGTH)) 1510 sprintf(prefix, "\t[%02x] ZERO ", i); 1511 else if (!drm_edid_block_valid(block, i, false, NULL)) 1512 sprintf(prefix, "\t[%02x] BAD ", i); 1513 else 1514 sprintf(prefix, "\t[%02x] GOOD ", i); 1515 1516 print_hex_dump(KERN_WARNING, 1517 prefix, DUMP_PREFIX_NONE, 16, 1, 1518 block, EDID_LENGTH, false); 1519 } 1520 } 1521 1522 /** 1523 * drm_do_get_edid - get EDID data using a custom EDID block read function 1524 * @connector: connector we're probing 1525 * @get_edid_block: EDID block read function 1526 * @data: private data passed to the block read function 1527 * 1528 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1529 * exposes a different interface to read EDID blocks this function can be used 1530 * to get EDID data using a custom block read function. 1531 * 1532 * As in the general case the DDC bus is accessible by the kernel at the I2C 1533 * level, drivers must make all reasonable efforts to expose it as an I2C 1534 * adapter and use drm_get_edid() instead of abusing this function. 1535 * 1536 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1537 */ 1538 struct edid *drm_do_get_edid(struct drm_connector *connector, 1539 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1540 size_t len), 1541 void *data) 1542 { 1543 int i, j = 0, valid_extensions = 0; 1544 u8 *edid, *new; 1545 1546 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1547 return NULL; 1548 1549 /* base block fetch */ 1550 for (i = 0; i < 4; i++) { 1551 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1552 goto out; 1553 if (drm_edid_block_valid(edid, 0, false, 1554 &connector->edid_corrupt)) 1555 break; 1556 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1557 connector->null_edid_counter++; 1558 goto carp; 1559 } 1560 } 1561 if (i == 4) 1562 goto carp; 1563 1564 /* if there's no extensions, we're done */ 1565 valid_extensions = edid[0x7e]; 1566 if (valid_extensions == 0) 1567 return (struct edid *)edid; 1568 1569 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1570 if (!new) 1571 goto out; 1572 edid = new; 1573 1574 for (j = 1; j <= edid[0x7e]; j++) { 1575 u8 *block = edid + j * EDID_LENGTH; 1576 1577 for (i = 0; i < 4; i++) { 1578 if (get_edid_block(data, block, j, EDID_LENGTH)) 1579 goto out; 1580 if (drm_edid_block_valid(block, j, false, NULL)) 1581 break; 1582 } 1583 1584 if (i == 4) 1585 valid_extensions--; 1586 } 1587 1588 if (valid_extensions != edid[0x7e]) { 1589 u8 *base; 1590 1591 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1592 1593 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1594 edid[0x7e] = valid_extensions; 1595 1596 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1597 if (!new) 1598 goto out; 1599 1600 base = new; 1601 for (i = 0; i <= edid[0x7e]; i++) { 1602 u8 *block = edid + i * EDID_LENGTH; 1603 1604 if (!drm_edid_block_valid(block, i, false, NULL)) 1605 continue; 1606 1607 memcpy(base, block, EDID_LENGTH); 1608 base += EDID_LENGTH; 1609 } 1610 1611 kfree(edid); 1612 edid = new; 1613 } 1614 1615 return (struct edid *)edid; 1616 1617 carp: 1618 connector_bad_edid(connector, edid, 1); 1619 out: 1620 kfree(edid); 1621 return NULL; 1622 } 1623 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1624 1625 /** 1626 * drm_probe_ddc() - probe DDC presence 1627 * @adapter: I2C adapter to probe 1628 * 1629 * Return: True on success, false on failure. 1630 */ 1631 bool 1632 drm_probe_ddc(struct i2c_adapter *adapter) 1633 { 1634 unsigned char out; 1635 1636 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1637 } 1638 EXPORT_SYMBOL(drm_probe_ddc); 1639 1640 /** 1641 * drm_get_edid - get EDID data, if available 1642 * @connector: connector we're probing 1643 * @adapter: I2C adapter to use for DDC 1644 * 1645 * Poke the given I2C channel to grab EDID data if possible. If found, 1646 * attach it to the connector. 1647 * 1648 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1649 */ 1650 struct edid *drm_get_edid(struct drm_connector *connector, 1651 struct i2c_adapter *adapter) 1652 { 1653 struct edid *edid; 1654 1655 if (connector->force == DRM_FORCE_OFF) 1656 return NULL; 1657 1658 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1659 return NULL; 1660 1661 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1662 if (edid) 1663 drm_get_displayid(connector, edid); 1664 return edid; 1665 } 1666 EXPORT_SYMBOL(drm_get_edid); 1667 1668 /** 1669 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1670 * @connector: connector we're probing 1671 * @adapter: I2C adapter to use for DDC 1672 * 1673 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1674 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1675 * switch DDC to the GPU which is retrieving EDID. 1676 * 1677 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1678 */ 1679 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1680 struct i2c_adapter *adapter) 1681 { 1682 struct pci_dev *pdev = connector->dev->pdev; 1683 struct edid *edid; 1684 1685 vga_switcheroo_lock_ddc(pdev); 1686 edid = drm_get_edid(connector, adapter); 1687 vga_switcheroo_unlock_ddc(pdev); 1688 1689 return edid; 1690 } 1691 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1692 1693 /** 1694 * drm_edid_duplicate - duplicate an EDID and the extensions 1695 * @edid: EDID to duplicate 1696 * 1697 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1698 */ 1699 struct edid *drm_edid_duplicate(const struct edid *edid) 1700 { 1701 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1702 } 1703 EXPORT_SYMBOL(drm_edid_duplicate); 1704 1705 /*** EDID parsing ***/ 1706 1707 /** 1708 * edid_vendor - match a string against EDID's obfuscated vendor field 1709 * @edid: EDID to match 1710 * @vendor: vendor string 1711 * 1712 * Returns true if @vendor is in @edid, false otherwise 1713 */ 1714 static bool edid_vendor(struct edid *edid, const char *vendor) 1715 { 1716 char edid_vendor[3]; 1717 1718 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1719 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1720 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1721 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1722 1723 return !strncmp(edid_vendor, vendor, 3); 1724 } 1725 1726 /** 1727 * edid_get_quirks - return quirk flags for a given EDID 1728 * @edid: EDID to process 1729 * 1730 * This tells subsequent routines what fixes they need to apply. 1731 */ 1732 static u32 edid_get_quirks(struct edid *edid) 1733 { 1734 const struct edid_quirk *quirk; 1735 int i; 1736 1737 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1738 quirk = &edid_quirk_list[i]; 1739 1740 if (edid_vendor(edid, quirk->vendor) && 1741 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1742 return quirk->quirks; 1743 } 1744 1745 return 0; 1746 } 1747 1748 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1749 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1750 1751 /** 1752 * edid_fixup_preferred - set preferred modes based on quirk list 1753 * @connector: has mode list to fix up 1754 * @quirks: quirks list 1755 * 1756 * Walk the mode list for @connector, clearing the preferred status 1757 * on existing modes and setting it anew for the right mode ala @quirks. 1758 */ 1759 static void edid_fixup_preferred(struct drm_connector *connector, 1760 u32 quirks) 1761 { 1762 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1763 int target_refresh = 0; 1764 int cur_vrefresh, preferred_vrefresh; 1765 1766 if (list_empty(&connector->probed_modes)) 1767 return; 1768 1769 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1770 target_refresh = 60; 1771 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1772 target_refresh = 75; 1773 1774 preferred_mode = list_first_entry(&connector->probed_modes, 1775 struct drm_display_mode, head); 1776 1777 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1778 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1779 1780 if (cur_mode == preferred_mode) 1781 continue; 1782 1783 /* Largest mode is preferred */ 1784 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1785 preferred_mode = cur_mode; 1786 1787 cur_vrefresh = cur_mode->vrefresh ? 1788 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1789 preferred_vrefresh = preferred_mode->vrefresh ? 1790 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1791 /* At a given size, try to get closest to target refresh */ 1792 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1793 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1794 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1795 preferred_mode = cur_mode; 1796 } 1797 } 1798 1799 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1800 } 1801 1802 static bool 1803 mode_is_rb(const struct drm_display_mode *mode) 1804 { 1805 return (mode->htotal - mode->hdisplay == 160) && 1806 (mode->hsync_end - mode->hdisplay == 80) && 1807 (mode->hsync_end - mode->hsync_start == 32) && 1808 (mode->vsync_start - mode->vdisplay == 3); 1809 } 1810 1811 /* 1812 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1813 * @dev: Device to duplicate against 1814 * @hsize: Mode width 1815 * @vsize: Mode height 1816 * @fresh: Mode refresh rate 1817 * @rb: Mode reduced-blanking-ness 1818 * 1819 * Walk the DMT mode list looking for a match for the given parameters. 1820 * 1821 * Return: A newly allocated copy of the mode, or NULL if not found. 1822 */ 1823 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1824 int hsize, int vsize, int fresh, 1825 bool rb) 1826 { 1827 int i; 1828 1829 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1830 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1831 if (hsize != ptr->hdisplay) 1832 continue; 1833 if (vsize != ptr->vdisplay) 1834 continue; 1835 if (fresh != drm_mode_vrefresh(ptr)) 1836 continue; 1837 if (rb != mode_is_rb(ptr)) 1838 continue; 1839 1840 return drm_mode_duplicate(dev, ptr); 1841 } 1842 1843 return NULL; 1844 } 1845 EXPORT_SYMBOL(drm_mode_find_dmt); 1846 1847 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1848 1849 static void 1850 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1851 { 1852 int i, n = 0; 1853 u8 d = ext[0x02]; 1854 u8 *det_base = ext + d; 1855 1856 n = (127 - d) / 18; 1857 for (i = 0; i < n; i++) 1858 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1859 } 1860 1861 static void 1862 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1863 { 1864 unsigned int i, n = min((int)ext[0x02], 6); 1865 u8 *det_base = ext + 5; 1866 1867 if (ext[0x01] != 1) 1868 return; /* unknown version */ 1869 1870 for (i = 0; i < n; i++) 1871 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1872 } 1873 1874 static void 1875 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1876 { 1877 int i; 1878 struct edid *edid = (struct edid *)raw_edid; 1879 1880 if (edid == NULL) 1881 return; 1882 1883 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1884 cb(&(edid->detailed_timings[i]), closure); 1885 1886 for (i = 1; i <= raw_edid[0x7e]; i++) { 1887 u8 *ext = raw_edid + (i * EDID_LENGTH); 1888 switch (*ext) { 1889 case CEA_EXT: 1890 cea_for_each_detailed_block(ext, cb, closure); 1891 break; 1892 case VTB_EXT: 1893 vtb_for_each_detailed_block(ext, cb, closure); 1894 break; 1895 default: 1896 break; 1897 } 1898 } 1899 } 1900 1901 static void 1902 is_rb(struct detailed_timing *t, void *data) 1903 { 1904 u8 *r = (u8 *)t; 1905 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1906 if (r[15] & 0x10) 1907 *(bool *)data = true; 1908 } 1909 1910 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1911 static bool 1912 drm_monitor_supports_rb(struct edid *edid) 1913 { 1914 if (edid->revision >= 4) { 1915 bool ret = false; 1916 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1917 return ret; 1918 } 1919 1920 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1921 } 1922 1923 static void 1924 find_gtf2(struct detailed_timing *t, void *data) 1925 { 1926 u8 *r = (u8 *)t; 1927 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1928 *(u8 **)data = r; 1929 } 1930 1931 /* Secondary GTF curve kicks in above some break frequency */ 1932 static int 1933 drm_gtf2_hbreak(struct edid *edid) 1934 { 1935 u8 *r = NULL; 1936 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1937 return r ? (r[12] * 2) : 0; 1938 } 1939 1940 static int 1941 drm_gtf2_2c(struct edid *edid) 1942 { 1943 u8 *r = NULL; 1944 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1945 return r ? r[13] : 0; 1946 } 1947 1948 static int 1949 drm_gtf2_m(struct edid *edid) 1950 { 1951 u8 *r = NULL; 1952 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1953 return r ? (r[15] << 8) + r[14] : 0; 1954 } 1955 1956 static int 1957 drm_gtf2_k(struct edid *edid) 1958 { 1959 u8 *r = NULL; 1960 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1961 return r ? r[16] : 0; 1962 } 1963 1964 static int 1965 drm_gtf2_2j(struct edid *edid) 1966 { 1967 u8 *r = NULL; 1968 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1969 return r ? r[17] : 0; 1970 } 1971 1972 /** 1973 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1974 * @edid: EDID block to scan 1975 */ 1976 static int standard_timing_level(struct edid *edid) 1977 { 1978 if (edid->revision >= 2) { 1979 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1980 return LEVEL_CVT; 1981 if (drm_gtf2_hbreak(edid)) 1982 return LEVEL_GTF2; 1983 return LEVEL_GTF; 1984 } 1985 return LEVEL_DMT; 1986 } 1987 1988 /* 1989 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1990 * monitors fill with ascii space (0x20) instead. 1991 */ 1992 static int 1993 bad_std_timing(u8 a, u8 b) 1994 { 1995 return (a == 0x00 && b == 0x00) || 1996 (a == 0x01 && b == 0x01) || 1997 (a == 0x20 && b == 0x20); 1998 } 1999 2000 /** 2001 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2002 * @connector: connector of for the EDID block 2003 * @edid: EDID block to scan 2004 * @t: standard timing params 2005 * 2006 * Take the standard timing params (in this case width, aspect, and refresh) 2007 * and convert them into a real mode using CVT/GTF/DMT. 2008 */ 2009 static struct drm_display_mode * 2010 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2011 struct std_timing *t) 2012 { 2013 struct drm_device *dev = connector->dev; 2014 struct drm_display_mode *m, *mode = NULL; 2015 int hsize, vsize; 2016 int vrefresh_rate; 2017 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2018 >> EDID_TIMING_ASPECT_SHIFT; 2019 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2020 >> EDID_TIMING_VFREQ_SHIFT; 2021 int timing_level = standard_timing_level(edid); 2022 2023 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2024 return NULL; 2025 2026 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2027 hsize = t->hsize * 8 + 248; 2028 /* vrefresh_rate = vfreq + 60 */ 2029 vrefresh_rate = vfreq + 60; 2030 /* the vdisplay is calculated based on the aspect ratio */ 2031 if (aspect_ratio == 0) { 2032 if (edid->revision < 3) 2033 vsize = hsize; 2034 else 2035 vsize = (hsize * 10) / 16; 2036 } else if (aspect_ratio == 1) 2037 vsize = (hsize * 3) / 4; 2038 else if (aspect_ratio == 2) 2039 vsize = (hsize * 4) / 5; 2040 else 2041 vsize = (hsize * 9) / 16; 2042 2043 /* HDTV hack, part 1 */ 2044 if (vrefresh_rate == 60 && 2045 ((hsize == 1360 && vsize == 765) || 2046 (hsize == 1368 && vsize == 769))) { 2047 hsize = 1366; 2048 vsize = 768; 2049 } 2050 2051 /* 2052 * If this connector already has a mode for this size and refresh 2053 * rate (because it came from detailed or CVT info), use that 2054 * instead. This way we don't have to guess at interlace or 2055 * reduced blanking. 2056 */ 2057 list_for_each_entry(m, &connector->probed_modes, head) 2058 if (m->hdisplay == hsize && m->vdisplay == vsize && 2059 drm_mode_vrefresh(m) == vrefresh_rate) 2060 return NULL; 2061 2062 /* HDTV hack, part 2 */ 2063 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2064 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2065 false); 2066 mode->hdisplay = 1366; 2067 mode->hsync_start = mode->hsync_start - 1; 2068 mode->hsync_end = mode->hsync_end - 1; 2069 return mode; 2070 } 2071 2072 /* check whether it can be found in default mode table */ 2073 if (drm_monitor_supports_rb(edid)) { 2074 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2075 true); 2076 if (mode) 2077 return mode; 2078 } 2079 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2080 if (mode) 2081 return mode; 2082 2083 /* okay, generate it */ 2084 switch (timing_level) { 2085 case LEVEL_DMT: 2086 break; 2087 case LEVEL_GTF: 2088 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2089 break; 2090 case LEVEL_GTF2: 2091 /* 2092 * This is potentially wrong if there's ever a monitor with 2093 * more than one ranges section, each claiming a different 2094 * secondary GTF curve. Please don't do that. 2095 */ 2096 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2097 if (!mode) 2098 return NULL; 2099 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2100 drm_mode_destroy(dev, mode); 2101 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2102 vrefresh_rate, 0, 0, 2103 drm_gtf2_m(edid), 2104 drm_gtf2_2c(edid), 2105 drm_gtf2_k(edid), 2106 drm_gtf2_2j(edid)); 2107 } 2108 break; 2109 case LEVEL_CVT: 2110 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2111 false); 2112 break; 2113 } 2114 return mode; 2115 } 2116 2117 /* 2118 * EDID is delightfully ambiguous about how interlaced modes are to be 2119 * encoded. Our internal representation is of frame height, but some 2120 * HDTV detailed timings are encoded as field height. 2121 * 2122 * The format list here is from CEA, in frame size. Technically we 2123 * should be checking refresh rate too. Whatever. 2124 */ 2125 static void 2126 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2127 struct detailed_pixel_timing *pt) 2128 { 2129 int i; 2130 static const struct { 2131 int w, h; 2132 } cea_interlaced[] = { 2133 { 1920, 1080 }, 2134 { 720, 480 }, 2135 { 1440, 480 }, 2136 { 2880, 480 }, 2137 { 720, 576 }, 2138 { 1440, 576 }, 2139 { 2880, 576 }, 2140 }; 2141 2142 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2143 return; 2144 2145 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2146 if ((mode->hdisplay == cea_interlaced[i].w) && 2147 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2148 mode->vdisplay *= 2; 2149 mode->vsync_start *= 2; 2150 mode->vsync_end *= 2; 2151 mode->vtotal *= 2; 2152 mode->vtotal |= 1; 2153 } 2154 } 2155 2156 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2157 } 2158 2159 /** 2160 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2161 * @dev: DRM device (needed to create new mode) 2162 * @edid: EDID block 2163 * @timing: EDID detailed timing info 2164 * @quirks: quirks to apply 2165 * 2166 * An EDID detailed timing block contains enough info for us to create and 2167 * return a new struct drm_display_mode. 2168 */ 2169 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2170 struct edid *edid, 2171 struct detailed_timing *timing, 2172 u32 quirks) 2173 { 2174 struct drm_display_mode *mode; 2175 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2176 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2177 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2178 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2179 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2180 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2181 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2182 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2183 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2184 2185 /* ignore tiny modes */ 2186 if (hactive < 64 || vactive < 64) 2187 return NULL; 2188 2189 if (pt->misc & DRM_EDID_PT_STEREO) { 2190 DRM_DEBUG_KMS("stereo mode not supported\n"); 2191 return NULL; 2192 } 2193 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2194 DRM_DEBUG_KMS("composite sync not supported\n"); 2195 } 2196 2197 /* it is incorrect if hsync/vsync width is zero */ 2198 if (!hsync_pulse_width || !vsync_pulse_width) { 2199 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2200 "Wrong Hsync/Vsync pulse width\n"); 2201 return NULL; 2202 } 2203 2204 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2205 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2206 if (!mode) 2207 return NULL; 2208 2209 goto set_size; 2210 } 2211 2212 mode = drm_mode_create(dev); 2213 if (!mode) 2214 return NULL; 2215 2216 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2217 timing->pixel_clock = cpu_to_le16(1088); 2218 2219 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2220 2221 mode->hdisplay = hactive; 2222 mode->hsync_start = mode->hdisplay + hsync_offset; 2223 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2224 mode->htotal = mode->hdisplay + hblank; 2225 2226 mode->vdisplay = vactive; 2227 mode->vsync_start = mode->vdisplay + vsync_offset; 2228 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2229 mode->vtotal = mode->vdisplay + vblank; 2230 2231 /* Some EDIDs have bogus h/vtotal values */ 2232 if (mode->hsync_end > mode->htotal) 2233 mode->htotal = mode->hsync_end + 1; 2234 if (mode->vsync_end > mode->vtotal) 2235 mode->vtotal = mode->vsync_end + 1; 2236 2237 drm_mode_do_interlace_quirk(mode, pt); 2238 2239 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2240 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2241 } 2242 2243 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2244 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2245 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2246 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2247 2248 set_size: 2249 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2250 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2251 2252 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2253 mode->width_mm *= 10; 2254 mode->height_mm *= 10; 2255 } 2256 2257 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2258 mode->width_mm = edid->width_cm * 10; 2259 mode->height_mm = edid->height_cm * 10; 2260 } 2261 2262 mode->type = DRM_MODE_TYPE_DRIVER; 2263 mode->vrefresh = drm_mode_vrefresh(mode); 2264 drm_mode_set_name(mode); 2265 2266 return mode; 2267 } 2268 2269 static bool 2270 mode_in_hsync_range(const struct drm_display_mode *mode, 2271 struct edid *edid, u8 *t) 2272 { 2273 int hsync, hmin, hmax; 2274 2275 hmin = t[7]; 2276 if (edid->revision >= 4) 2277 hmin += ((t[4] & 0x04) ? 255 : 0); 2278 hmax = t[8]; 2279 if (edid->revision >= 4) 2280 hmax += ((t[4] & 0x08) ? 255 : 0); 2281 hsync = drm_mode_hsync(mode); 2282 2283 return (hsync <= hmax && hsync >= hmin); 2284 } 2285 2286 static bool 2287 mode_in_vsync_range(const struct drm_display_mode *mode, 2288 struct edid *edid, u8 *t) 2289 { 2290 int vsync, vmin, vmax; 2291 2292 vmin = t[5]; 2293 if (edid->revision >= 4) 2294 vmin += ((t[4] & 0x01) ? 255 : 0); 2295 vmax = t[6]; 2296 if (edid->revision >= 4) 2297 vmax += ((t[4] & 0x02) ? 255 : 0); 2298 vsync = drm_mode_vrefresh(mode); 2299 2300 return (vsync <= vmax && vsync >= vmin); 2301 } 2302 2303 static u32 2304 range_pixel_clock(struct edid *edid, u8 *t) 2305 { 2306 /* unspecified */ 2307 if (t[9] == 0 || t[9] == 255) 2308 return 0; 2309 2310 /* 1.4 with CVT support gives us real precision, yay */ 2311 if (edid->revision >= 4 && t[10] == 0x04) 2312 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2313 2314 /* 1.3 is pathetic, so fuzz up a bit */ 2315 return t[9] * 10000 + 5001; 2316 } 2317 2318 static bool 2319 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2320 struct detailed_timing *timing) 2321 { 2322 u32 max_clock; 2323 u8 *t = (u8 *)timing; 2324 2325 if (!mode_in_hsync_range(mode, edid, t)) 2326 return false; 2327 2328 if (!mode_in_vsync_range(mode, edid, t)) 2329 return false; 2330 2331 if ((max_clock = range_pixel_clock(edid, t))) 2332 if (mode->clock > max_clock) 2333 return false; 2334 2335 /* 1.4 max horizontal check */ 2336 if (edid->revision >= 4 && t[10] == 0x04) 2337 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2338 return false; 2339 2340 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2341 return false; 2342 2343 return true; 2344 } 2345 2346 static bool valid_inferred_mode(const struct drm_connector *connector, 2347 const struct drm_display_mode *mode) 2348 { 2349 const struct drm_display_mode *m; 2350 bool ok = false; 2351 2352 list_for_each_entry(m, &connector->probed_modes, head) { 2353 if (mode->hdisplay == m->hdisplay && 2354 mode->vdisplay == m->vdisplay && 2355 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2356 return false; /* duplicated */ 2357 if (mode->hdisplay <= m->hdisplay && 2358 mode->vdisplay <= m->vdisplay) 2359 ok = true; 2360 } 2361 return ok; 2362 } 2363 2364 static int 2365 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2366 struct detailed_timing *timing) 2367 { 2368 int i, modes = 0; 2369 struct drm_display_mode *newmode; 2370 struct drm_device *dev = connector->dev; 2371 2372 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2373 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2374 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2375 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2376 if (newmode) { 2377 drm_mode_probed_add(connector, newmode); 2378 modes++; 2379 } 2380 } 2381 } 2382 2383 return modes; 2384 } 2385 2386 /* fix up 1366x768 mode from 1368x768; 2387 * GFT/CVT can't express 1366 width which isn't dividable by 8 2388 */ 2389 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2390 { 2391 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2392 mode->hdisplay = 1366; 2393 mode->hsync_start--; 2394 mode->hsync_end--; 2395 drm_mode_set_name(mode); 2396 } 2397 } 2398 2399 static int 2400 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2401 struct detailed_timing *timing) 2402 { 2403 int i, modes = 0; 2404 struct drm_display_mode *newmode; 2405 struct drm_device *dev = connector->dev; 2406 2407 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2408 const struct minimode *m = &extra_modes[i]; 2409 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2410 if (!newmode) 2411 return modes; 2412 2413 drm_mode_fixup_1366x768(newmode); 2414 if (!mode_in_range(newmode, edid, timing) || 2415 !valid_inferred_mode(connector, newmode)) { 2416 drm_mode_destroy(dev, newmode); 2417 continue; 2418 } 2419 2420 drm_mode_probed_add(connector, newmode); 2421 modes++; 2422 } 2423 2424 return modes; 2425 } 2426 2427 static int 2428 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2429 struct detailed_timing *timing) 2430 { 2431 int i, modes = 0; 2432 struct drm_display_mode *newmode; 2433 struct drm_device *dev = connector->dev; 2434 bool rb = drm_monitor_supports_rb(edid); 2435 2436 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2437 const struct minimode *m = &extra_modes[i]; 2438 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2439 if (!newmode) 2440 return modes; 2441 2442 drm_mode_fixup_1366x768(newmode); 2443 if (!mode_in_range(newmode, edid, timing) || 2444 !valid_inferred_mode(connector, newmode)) { 2445 drm_mode_destroy(dev, newmode); 2446 continue; 2447 } 2448 2449 drm_mode_probed_add(connector, newmode); 2450 modes++; 2451 } 2452 2453 return modes; 2454 } 2455 2456 static void 2457 do_inferred_modes(struct detailed_timing *timing, void *c) 2458 { 2459 struct detailed_mode_closure *closure = c; 2460 struct detailed_non_pixel *data = &timing->data.other_data; 2461 struct detailed_data_monitor_range *range = &data->data.range; 2462 2463 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2464 return; 2465 2466 closure->modes += drm_dmt_modes_for_range(closure->connector, 2467 closure->edid, 2468 timing); 2469 2470 if (!version_greater(closure->edid, 1, 1)) 2471 return; /* GTF not defined yet */ 2472 2473 switch (range->flags) { 2474 case 0x02: /* secondary gtf, XXX could do more */ 2475 case 0x00: /* default gtf */ 2476 closure->modes += drm_gtf_modes_for_range(closure->connector, 2477 closure->edid, 2478 timing); 2479 break; 2480 case 0x04: /* cvt, only in 1.4+ */ 2481 if (!version_greater(closure->edid, 1, 3)) 2482 break; 2483 2484 closure->modes += drm_cvt_modes_for_range(closure->connector, 2485 closure->edid, 2486 timing); 2487 break; 2488 case 0x01: /* just the ranges, no formula */ 2489 default: 2490 break; 2491 } 2492 } 2493 2494 static int 2495 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2496 { 2497 struct detailed_mode_closure closure = { 2498 .connector = connector, 2499 .edid = edid, 2500 }; 2501 2502 if (version_greater(edid, 1, 0)) 2503 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2504 &closure); 2505 2506 return closure.modes; 2507 } 2508 2509 static int 2510 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2511 { 2512 int i, j, m, modes = 0; 2513 struct drm_display_mode *mode; 2514 u8 *est = ((u8 *)timing) + 6; 2515 2516 for (i = 0; i < 6; i++) { 2517 for (j = 7; j >= 0; j--) { 2518 m = (i * 8) + (7 - j); 2519 if (m >= ARRAY_SIZE(est3_modes)) 2520 break; 2521 if (est[i] & (1 << j)) { 2522 mode = drm_mode_find_dmt(connector->dev, 2523 est3_modes[m].w, 2524 est3_modes[m].h, 2525 est3_modes[m].r, 2526 est3_modes[m].rb); 2527 if (mode) { 2528 drm_mode_probed_add(connector, mode); 2529 modes++; 2530 } 2531 } 2532 } 2533 } 2534 2535 return modes; 2536 } 2537 2538 static void 2539 do_established_modes(struct detailed_timing *timing, void *c) 2540 { 2541 struct detailed_mode_closure *closure = c; 2542 struct detailed_non_pixel *data = &timing->data.other_data; 2543 2544 if (data->type == EDID_DETAIL_EST_TIMINGS) 2545 closure->modes += drm_est3_modes(closure->connector, timing); 2546 } 2547 2548 /** 2549 * add_established_modes - get est. modes from EDID and add them 2550 * @connector: connector to add mode(s) to 2551 * @edid: EDID block to scan 2552 * 2553 * Each EDID block contains a bitmap of the supported "established modes" list 2554 * (defined above). Tease them out and add them to the global modes list. 2555 */ 2556 static int 2557 add_established_modes(struct drm_connector *connector, struct edid *edid) 2558 { 2559 struct drm_device *dev = connector->dev; 2560 unsigned long est_bits = edid->established_timings.t1 | 2561 (edid->established_timings.t2 << 8) | 2562 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2563 int i, modes = 0; 2564 struct detailed_mode_closure closure = { 2565 .connector = connector, 2566 .edid = edid, 2567 }; 2568 2569 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2570 if (est_bits & (1<<i)) { 2571 struct drm_display_mode *newmode; 2572 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2573 if (newmode) { 2574 drm_mode_probed_add(connector, newmode); 2575 modes++; 2576 } 2577 } 2578 } 2579 2580 if (version_greater(edid, 1, 0)) 2581 drm_for_each_detailed_block((u8 *)edid, 2582 do_established_modes, &closure); 2583 2584 return modes + closure.modes; 2585 } 2586 2587 static void 2588 do_standard_modes(struct detailed_timing *timing, void *c) 2589 { 2590 struct detailed_mode_closure *closure = c; 2591 struct detailed_non_pixel *data = &timing->data.other_data; 2592 struct drm_connector *connector = closure->connector; 2593 struct edid *edid = closure->edid; 2594 2595 if (data->type == EDID_DETAIL_STD_MODES) { 2596 int i; 2597 for (i = 0; i < 6; i++) { 2598 struct std_timing *std; 2599 struct drm_display_mode *newmode; 2600 2601 std = &data->data.timings[i]; 2602 newmode = drm_mode_std(connector, edid, std); 2603 if (newmode) { 2604 drm_mode_probed_add(connector, newmode); 2605 closure->modes++; 2606 } 2607 } 2608 } 2609 } 2610 2611 /** 2612 * add_standard_modes - get std. modes from EDID and add them 2613 * @connector: connector to add mode(s) to 2614 * @edid: EDID block to scan 2615 * 2616 * Standard modes can be calculated using the appropriate standard (DMT, 2617 * GTF or CVT. Grab them from @edid and add them to the list. 2618 */ 2619 static int 2620 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2621 { 2622 int i, modes = 0; 2623 struct detailed_mode_closure closure = { 2624 .connector = connector, 2625 .edid = edid, 2626 }; 2627 2628 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2629 struct drm_display_mode *newmode; 2630 2631 newmode = drm_mode_std(connector, edid, 2632 &edid->standard_timings[i]); 2633 if (newmode) { 2634 drm_mode_probed_add(connector, newmode); 2635 modes++; 2636 } 2637 } 2638 2639 if (version_greater(edid, 1, 0)) 2640 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2641 &closure); 2642 2643 /* XXX should also look for standard codes in VTB blocks */ 2644 2645 return modes + closure.modes; 2646 } 2647 2648 static int drm_cvt_modes(struct drm_connector *connector, 2649 struct detailed_timing *timing) 2650 { 2651 int i, j, modes = 0; 2652 struct drm_display_mode *newmode; 2653 struct drm_device *dev = connector->dev; 2654 struct cvt_timing *cvt; 2655 const int rates[] = { 60, 85, 75, 60, 50 }; 2656 const u8 empty[3] = { 0, 0, 0 }; 2657 2658 for (i = 0; i < 4; i++) { 2659 int uninitialized_var(width), height; 2660 cvt = &(timing->data.other_data.data.cvt[i]); 2661 2662 if (!memcmp(cvt->code, empty, 3)) 2663 continue; 2664 2665 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2666 switch (cvt->code[1] & 0x0c) { 2667 case 0x00: 2668 width = height * 4 / 3; 2669 break; 2670 case 0x04: 2671 width = height * 16 / 9; 2672 break; 2673 case 0x08: 2674 width = height * 16 / 10; 2675 break; 2676 case 0x0c: 2677 width = height * 15 / 9; 2678 break; 2679 } 2680 2681 for (j = 1; j < 5; j++) { 2682 if (cvt->code[2] & (1 << j)) { 2683 newmode = drm_cvt_mode(dev, width, height, 2684 rates[j], j == 0, 2685 false, false); 2686 if (newmode) { 2687 drm_mode_probed_add(connector, newmode); 2688 modes++; 2689 } 2690 } 2691 } 2692 } 2693 2694 return modes; 2695 } 2696 2697 static void 2698 do_cvt_mode(struct detailed_timing *timing, void *c) 2699 { 2700 struct detailed_mode_closure *closure = c; 2701 struct detailed_non_pixel *data = &timing->data.other_data; 2702 2703 if (data->type == EDID_DETAIL_CVT_3BYTE) 2704 closure->modes += drm_cvt_modes(closure->connector, timing); 2705 } 2706 2707 static int 2708 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2709 { 2710 struct detailed_mode_closure closure = { 2711 .connector = connector, 2712 .edid = edid, 2713 }; 2714 2715 if (version_greater(edid, 1, 2)) 2716 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2717 2718 /* XXX should also look for CVT codes in VTB blocks */ 2719 2720 return closure.modes; 2721 } 2722 2723 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2724 2725 static void 2726 do_detailed_mode(struct detailed_timing *timing, void *c) 2727 { 2728 struct detailed_mode_closure *closure = c; 2729 struct drm_display_mode *newmode; 2730 2731 if (timing->pixel_clock) { 2732 newmode = drm_mode_detailed(closure->connector->dev, 2733 closure->edid, timing, 2734 closure->quirks); 2735 if (!newmode) 2736 return; 2737 2738 if (closure->preferred) 2739 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2740 2741 /* 2742 * Detailed modes are limited to 10kHz pixel clock resolution, 2743 * so fix up anything that looks like CEA/HDMI mode, but the clock 2744 * is just slightly off. 2745 */ 2746 fixup_detailed_cea_mode_clock(newmode); 2747 2748 drm_mode_probed_add(closure->connector, newmode); 2749 closure->modes++; 2750 closure->preferred = 0; 2751 } 2752 } 2753 2754 /* 2755 * add_detailed_modes - Add modes from detailed timings 2756 * @connector: attached connector 2757 * @edid: EDID block to scan 2758 * @quirks: quirks to apply 2759 */ 2760 static int 2761 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2762 u32 quirks) 2763 { 2764 struct detailed_mode_closure closure = { 2765 .connector = connector, 2766 .edid = edid, 2767 .preferred = 1, 2768 .quirks = quirks, 2769 }; 2770 2771 if (closure.preferred && !version_greater(edid, 1, 3)) 2772 closure.preferred = 2773 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2774 2775 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2776 2777 return closure.modes; 2778 } 2779 2780 #define AUDIO_BLOCK 0x01 2781 #define VIDEO_BLOCK 0x02 2782 #define VENDOR_BLOCK 0x03 2783 #define SPEAKER_BLOCK 0x04 2784 #define USE_EXTENDED_TAG 0x07 2785 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2786 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2787 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2788 #define EDID_BASIC_AUDIO (1 << 6) 2789 #define EDID_CEA_YCRCB444 (1 << 5) 2790 #define EDID_CEA_YCRCB422 (1 << 4) 2791 #define EDID_CEA_VCDB_QS (1 << 6) 2792 2793 /* 2794 * Search EDID for CEA extension block. 2795 */ 2796 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2797 { 2798 u8 *edid_ext = NULL; 2799 int i; 2800 2801 /* No EDID or EDID extensions */ 2802 if (edid == NULL || edid->extensions == 0) 2803 return NULL; 2804 2805 /* Find CEA extension */ 2806 for (i = 0; i < edid->extensions; i++) { 2807 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2808 if (edid_ext[0] == ext_id) 2809 break; 2810 } 2811 2812 if (i == edid->extensions) 2813 return NULL; 2814 2815 return edid_ext; 2816 } 2817 2818 static u8 *drm_find_cea_extension(struct edid *edid) 2819 { 2820 return drm_find_edid_extension(edid, CEA_EXT); 2821 } 2822 2823 static u8 *drm_find_displayid_extension(struct edid *edid) 2824 { 2825 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2826 } 2827 2828 /* 2829 * Calculate the alternate clock for the CEA mode 2830 * (60Hz vs. 59.94Hz etc.) 2831 */ 2832 static unsigned int 2833 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2834 { 2835 unsigned int clock = cea_mode->clock; 2836 2837 if (cea_mode->vrefresh % 6 != 0) 2838 return clock; 2839 2840 /* 2841 * edid_cea_modes contains the 59.94Hz 2842 * variant for 240 and 480 line modes, 2843 * and the 60Hz variant otherwise. 2844 */ 2845 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2846 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2847 else 2848 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2849 2850 return clock; 2851 } 2852 2853 static bool 2854 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2855 { 2856 /* 2857 * For certain VICs the spec allows the vertical 2858 * front porch to vary by one or two lines. 2859 * 2860 * cea_modes[] stores the variant with the shortest 2861 * vertical front porch. We can adjust the mode to 2862 * get the other variants by simply increasing the 2863 * vertical front porch length. 2864 */ 2865 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2866 edid_cea_modes[9].vtotal != 262 || 2867 edid_cea_modes[12].vtotal != 262 || 2868 edid_cea_modes[13].vtotal != 262 || 2869 edid_cea_modes[23].vtotal != 312 || 2870 edid_cea_modes[24].vtotal != 312 || 2871 edid_cea_modes[27].vtotal != 312 || 2872 edid_cea_modes[28].vtotal != 312); 2873 2874 if (((vic == 8 || vic == 9 || 2875 vic == 12 || vic == 13) && mode->vtotal < 263) || 2876 ((vic == 23 || vic == 24 || 2877 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2878 mode->vsync_start++; 2879 mode->vsync_end++; 2880 mode->vtotal++; 2881 2882 return true; 2883 } 2884 2885 return false; 2886 } 2887 2888 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2889 unsigned int clock_tolerance) 2890 { 2891 u8 vic; 2892 2893 if (!to_match->clock) 2894 return 0; 2895 2896 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2897 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2898 unsigned int clock1, clock2; 2899 2900 /* Check both 60Hz and 59.94Hz */ 2901 clock1 = cea_mode.clock; 2902 clock2 = cea_mode_alternate_clock(&cea_mode); 2903 2904 if (abs(to_match->clock - clock1) > clock_tolerance && 2905 abs(to_match->clock - clock2) > clock_tolerance) 2906 continue; 2907 2908 do { 2909 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) 2910 return vic; 2911 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2912 } 2913 2914 return 0; 2915 } 2916 2917 /** 2918 * drm_match_cea_mode - look for a CEA mode matching given mode 2919 * @to_match: display mode 2920 * 2921 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2922 * mode. 2923 */ 2924 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2925 { 2926 u8 vic; 2927 2928 if (!to_match->clock) 2929 return 0; 2930 2931 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2932 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2933 unsigned int clock1, clock2; 2934 2935 /* Check both 60Hz and 59.94Hz */ 2936 clock1 = cea_mode.clock; 2937 clock2 = cea_mode_alternate_clock(&cea_mode); 2938 2939 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 2940 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 2941 continue; 2942 2943 do { 2944 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) 2945 return vic; 2946 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2947 } 2948 2949 return 0; 2950 } 2951 EXPORT_SYMBOL(drm_match_cea_mode); 2952 2953 static bool drm_valid_cea_vic(u8 vic) 2954 { 2955 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2956 } 2957 2958 /** 2959 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2960 * the input VIC from the CEA mode list 2961 * @video_code: ID given to each of the CEA modes 2962 * 2963 * Returns picture aspect ratio 2964 */ 2965 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2966 { 2967 return edid_cea_modes[video_code].picture_aspect_ratio; 2968 } 2969 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2970 2971 /* 2972 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2973 * specific block). 2974 * 2975 * It's almost like cea_mode_alternate_clock(), we just need to add an 2976 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2977 * one. 2978 */ 2979 static unsigned int 2980 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2981 { 2982 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2983 return hdmi_mode->clock; 2984 2985 return cea_mode_alternate_clock(hdmi_mode); 2986 } 2987 2988 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2989 unsigned int clock_tolerance) 2990 { 2991 u8 vic; 2992 2993 if (!to_match->clock) 2994 return 0; 2995 2996 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2997 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2998 unsigned int clock1, clock2; 2999 3000 /* Make sure to also match alternate clocks */ 3001 clock1 = hdmi_mode->clock; 3002 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3003 3004 if (abs(to_match->clock - clock1) > clock_tolerance && 3005 abs(to_match->clock - clock2) > clock_tolerance) 3006 continue; 3007 3008 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3009 return vic; 3010 } 3011 3012 return 0; 3013 } 3014 3015 /* 3016 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3017 * @to_match: display mode 3018 * 3019 * An HDMI mode is one defined in the HDMI vendor specific block. 3020 * 3021 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3022 */ 3023 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3024 { 3025 u8 vic; 3026 3027 if (!to_match->clock) 3028 return 0; 3029 3030 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3031 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3032 unsigned int clock1, clock2; 3033 3034 /* Make sure to also match alternate clocks */ 3035 clock1 = hdmi_mode->clock; 3036 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3037 3038 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3039 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3040 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 3041 return vic; 3042 } 3043 return 0; 3044 } 3045 3046 static bool drm_valid_hdmi_vic(u8 vic) 3047 { 3048 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3049 } 3050 3051 static int 3052 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3053 { 3054 struct drm_device *dev = connector->dev; 3055 struct drm_display_mode *mode, *tmp; 3056 LIST_HEAD(list); 3057 int modes = 0; 3058 3059 /* Don't add CEA modes if the CEA extension block is missing */ 3060 if (!drm_find_cea_extension(edid)) 3061 return 0; 3062 3063 /* 3064 * Go through all probed modes and create a new mode 3065 * with the alternate clock for certain CEA modes. 3066 */ 3067 list_for_each_entry(mode, &connector->probed_modes, head) { 3068 const struct drm_display_mode *cea_mode = NULL; 3069 struct drm_display_mode *newmode; 3070 u8 vic = drm_match_cea_mode(mode); 3071 unsigned int clock1, clock2; 3072 3073 if (drm_valid_cea_vic(vic)) { 3074 cea_mode = &edid_cea_modes[vic]; 3075 clock2 = cea_mode_alternate_clock(cea_mode); 3076 } else { 3077 vic = drm_match_hdmi_mode(mode); 3078 if (drm_valid_hdmi_vic(vic)) { 3079 cea_mode = &edid_4k_modes[vic]; 3080 clock2 = hdmi_mode_alternate_clock(cea_mode); 3081 } 3082 } 3083 3084 if (!cea_mode) 3085 continue; 3086 3087 clock1 = cea_mode->clock; 3088 3089 if (clock1 == clock2) 3090 continue; 3091 3092 if (mode->clock != clock1 && mode->clock != clock2) 3093 continue; 3094 3095 newmode = drm_mode_duplicate(dev, cea_mode); 3096 if (!newmode) 3097 continue; 3098 3099 /* Carry over the stereo flags */ 3100 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3101 3102 /* 3103 * The current mode could be either variant. Make 3104 * sure to pick the "other" clock for the new mode. 3105 */ 3106 if (mode->clock != clock1) 3107 newmode->clock = clock1; 3108 else 3109 newmode->clock = clock2; 3110 3111 list_add_tail(&newmode->head, &list); 3112 } 3113 3114 list_for_each_entry_safe(mode, tmp, &list, head) { 3115 list_del(&mode->head); 3116 drm_mode_probed_add(connector, mode); 3117 modes++; 3118 } 3119 3120 return modes; 3121 } 3122 3123 static u8 svd_to_vic(u8 svd) 3124 { 3125 /* 0-6 bit vic, 7th bit native mode indicator */ 3126 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3127 return svd & 127; 3128 3129 return svd; 3130 } 3131 3132 static struct drm_display_mode * 3133 drm_display_mode_from_vic_index(struct drm_connector *connector, 3134 const u8 *video_db, u8 video_len, 3135 u8 video_index) 3136 { 3137 struct drm_device *dev = connector->dev; 3138 struct drm_display_mode *newmode; 3139 u8 vic; 3140 3141 if (video_db == NULL || video_index >= video_len) 3142 return NULL; 3143 3144 /* CEA modes are numbered 1..127 */ 3145 vic = svd_to_vic(video_db[video_index]); 3146 if (!drm_valid_cea_vic(vic)) 3147 return NULL; 3148 3149 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3150 if (!newmode) 3151 return NULL; 3152 3153 newmode->vrefresh = 0; 3154 3155 return newmode; 3156 } 3157 3158 /* 3159 * do_y420vdb_modes - Parse YCBCR 420 only modes 3160 * @connector: connector corresponding to the HDMI sink 3161 * @svds: start of the data block of CEA YCBCR 420 VDB 3162 * @len: length of the CEA YCBCR 420 VDB 3163 * 3164 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3165 * which contains modes which can be supported in YCBCR 420 3166 * output format only. 3167 */ 3168 static int do_y420vdb_modes(struct drm_connector *connector, 3169 const u8 *svds, u8 svds_len) 3170 { 3171 int modes = 0, i; 3172 struct drm_device *dev = connector->dev; 3173 struct drm_display_info *info = &connector->display_info; 3174 struct drm_hdmi_info *hdmi = &info->hdmi; 3175 3176 for (i = 0; i < svds_len; i++) { 3177 u8 vic = svd_to_vic(svds[i]); 3178 struct drm_display_mode *newmode; 3179 3180 if (!drm_valid_cea_vic(vic)) 3181 continue; 3182 3183 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3184 if (!newmode) 3185 break; 3186 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3187 drm_mode_probed_add(connector, newmode); 3188 modes++; 3189 } 3190 3191 if (modes > 0) 3192 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3193 return modes; 3194 } 3195 3196 /* 3197 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3198 * @connector: connector corresponding to the HDMI sink 3199 * @vic: CEA vic for the video mode to be added in the map 3200 * 3201 * Makes an entry for a videomode in the YCBCR 420 bitmap 3202 */ 3203 static void 3204 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3205 { 3206 u8 vic = svd_to_vic(svd); 3207 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3208 3209 if (!drm_valid_cea_vic(vic)) 3210 return; 3211 3212 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3213 } 3214 3215 static int 3216 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3217 { 3218 int i, modes = 0; 3219 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3220 3221 for (i = 0; i < len; i++) { 3222 struct drm_display_mode *mode; 3223 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3224 if (mode) { 3225 /* 3226 * YCBCR420 capability block contains a bitmap which 3227 * gives the index of CEA modes from CEA VDB, which 3228 * can support YCBCR 420 sampling output also (apart 3229 * from RGB/YCBCR444 etc). 3230 * For example, if the bit 0 in bitmap is set, 3231 * first mode in VDB can support YCBCR420 output too. 3232 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3233 */ 3234 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3235 drm_add_cmdb_modes(connector, db[i]); 3236 3237 drm_mode_probed_add(connector, mode); 3238 modes++; 3239 } 3240 } 3241 3242 return modes; 3243 } 3244 3245 struct stereo_mandatory_mode { 3246 int width, height, vrefresh; 3247 unsigned int flags; 3248 }; 3249 3250 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3251 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3252 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3253 { 1920, 1080, 50, 3254 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3255 { 1920, 1080, 60, 3256 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3257 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3258 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3259 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3260 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3261 }; 3262 3263 static bool 3264 stereo_match_mandatory(const struct drm_display_mode *mode, 3265 const struct stereo_mandatory_mode *stereo_mode) 3266 { 3267 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3268 3269 return mode->hdisplay == stereo_mode->width && 3270 mode->vdisplay == stereo_mode->height && 3271 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3272 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3273 } 3274 3275 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3276 { 3277 struct drm_device *dev = connector->dev; 3278 const struct drm_display_mode *mode; 3279 struct list_head stereo_modes; 3280 int modes = 0, i; 3281 3282 INIT_LIST_HEAD(&stereo_modes); 3283 3284 list_for_each_entry(mode, &connector->probed_modes, head) { 3285 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3286 const struct stereo_mandatory_mode *mandatory; 3287 struct drm_display_mode *new_mode; 3288 3289 if (!stereo_match_mandatory(mode, 3290 &stereo_mandatory_modes[i])) 3291 continue; 3292 3293 mandatory = &stereo_mandatory_modes[i]; 3294 new_mode = drm_mode_duplicate(dev, mode); 3295 if (!new_mode) 3296 continue; 3297 3298 new_mode->flags |= mandatory->flags; 3299 list_add_tail(&new_mode->head, &stereo_modes); 3300 modes++; 3301 } 3302 } 3303 3304 list_splice_tail(&stereo_modes, &connector->probed_modes); 3305 3306 return modes; 3307 } 3308 3309 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3310 { 3311 struct drm_device *dev = connector->dev; 3312 struct drm_display_mode *newmode; 3313 3314 if (!drm_valid_hdmi_vic(vic)) { 3315 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3316 return 0; 3317 } 3318 3319 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3320 if (!newmode) 3321 return 0; 3322 3323 drm_mode_probed_add(connector, newmode); 3324 3325 return 1; 3326 } 3327 3328 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3329 const u8 *video_db, u8 video_len, u8 video_index) 3330 { 3331 struct drm_display_mode *newmode; 3332 int modes = 0; 3333 3334 if (structure & (1 << 0)) { 3335 newmode = drm_display_mode_from_vic_index(connector, video_db, 3336 video_len, 3337 video_index); 3338 if (newmode) { 3339 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3340 drm_mode_probed_add(connector, newmode); 3341 modes++; 3342 } 3343 } 3344 if (structure & (1 << 6)) { 3345 newmode = drm_display_mode_from_vic_index(connector, video_db, 3346 video_len, 3347 video_index); 3348 if (newmode) { 3349 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3350 drm_mode_probed_add(connector, newmode); 3351 modes++; 3352 } 3353 } 3354 if (structure & (1 << 8)) { 3355 newmode = drm_display_mode_from_vic_index(connector, video_db, 3356 video_len, 3357 video_index); 3358 if (newmode) { 3359 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3360 drm_mode_probed_add(connector, newmode); 3361 modes++; 3362 } 3363 } 3364 3365 return modes; 3366 } 3367 3368 /* 3369 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3370 * @connector: connector corresponding to the HDMI sink 3371 * @db: start of the CEA vendor specific block 3372 * @len: length of the CEA block payload, ie. one can access up to db[len] 3373 * 3374 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3375 * also adds the stereo 3d modes when applicable. 3376 */ 3377 static int 3378 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3379 const u8 *video_db, u8 video_len) 3380 { 3381 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3382 u8 vic_len, hdmi_3d_len = 0; 3383 u16 mask; 3384 u16 structure_all; 3385 3386 if (len < 8) 3387 goto out; 3388 3389 /* no HDMI_Video_Present */ 3390 if (!(db[8] & (1 << 5))) 3391 goto out; 3392 3393 /* Latency_Fields_Present */ 3394 if (db[8] & (1 << 7)) 3395 offset += 2; 3396 3397 /* I_Latency_Fields_Present */ 3398 if (db[8] & (1 << 6)) 3399 offset += 2; 3400 3401 /* the declared length is not long enough for the 2 first bytes 3402 * of additional video format capabilities */ 3403 if (len < (8 + offset + 2)) 3404 goto out; 3405 3406 /* 3D_Present */ 3407 offset++; 3408 if (db[8 + offset] & (1 << 7)) { 3409 modes += add_hdmi_mandatory_stereo_modes(connector); 3410 3411 /* 3D_Multi_present */ 3412 multi_present = (db[8 + offset] & 0x60) >> 5; 3413 } 3414 3415 offset++; 3416 vic_len = db[8 + offset] >> 5; 3417 hdmi_3d_len = db[8 + offset] & 0x1f; 3418 3419 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3420 u8 vic; 3421 3422 vic = db[9 + offset + i]; 3423 modes += add_hdmi_mode(connector, vic); 3424 } 3425 offset += 1 + vic_len; 3426 3427 if (multi_present == 1) 3428 multi_len = 2; 3429 else if (multi_present == 2) 3430 multi_len = 4; 3431 else 3432 multi_len = 0; 3433 3434 if (len < (8 + offset + hdmi_3d_len - 1)) 3435 goto out; 3436 3437 if (hdmi_3d_len < multi_len) 3438 goto out; 3439 3440 if (multi_present == 1 || multi_present == 2) { 3441 /* 3D_Structure_ALL */ 3442 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3443 3444 /* check if 3D_MASK is present */ 3445 if (multi_present == 2) 3446 mask = (db[10 + offset] << 8) | db[11 + offset]; 3447 else 3448 mask = 0xffff; 3449 3450 for (i = 0; i < 16; i++) { 3451 if (mask & (1 << i)) 3452 modes += add_3d_struct_modes(connector, 3453 structure_all, 3454 video_db, 3455 video_len, i); 3456 } 3457 } 3458 3459 offset += multi_len; 3460 3461 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3462 int vic_index; 3463 struct drm_display_mode *newmode = NULL; 3464 unsigned int newflag = 0; 3465 bool detail_present; 3466 3467 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3468 3469 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3470 break; 3471 3472 /* 2D_VIC_order_X */ 3473 vic_index = db[8 + offset + i] >> 4; 3474 3475 /* 3D_Structure_X */ 3476 switch (db[8 + offset + i] & 0x0f) { 3477 case 0: 3478 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3479 break; 3480 case 6: 3481 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3482 break; 3483 case 8: 3484 /* 3D_Detail_X */ 3485 if ((db[9 + offset + i] >> 4) == 1) 3486 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3487 break; 3488 } 3489 3490 if (newflag != 0) { 3491 newmode = drm_display_mode_from_vic_index(connector, 3492 video_db, 3493 video_len, 3494 vic_index); 3495 3496 if (newmode) { 3497 newmode->flags |= newflag; 3498 drm_mode_probed_add(connector, newmode); 3499 modes++; 3500 } 3501 } 3502 3503 if (detail_present) 3504 i++; 3505 } 3506 3507 out: 3508 return modes; 3509 } 3510 3511 static int 3512 cea_db_payload_len(const u8 *db) 3513 { 3514 return db[0] & 0x1f; 3515 } 3516 3517 static int 3518 cea_db_extended_tag(const u8 *db) 3519 { 3520 return db[1]; 3521 } 3522 3523 static int 3524 cea_db_tag(const u8 *db) 3525 { 3526 return db[0] >> 5; 3527 } 3528 3529 static int 3530 cea_revision(const u8 *cea) 3531 { 3532 return cea[1]; 3533 } 3534 3535 static int 3536 cea_db_offsets(const u8 *cea, int *start, int *end) 3537 { 3538 /* Data block offset in CEA extension block */ 3539 *start = 4; 3540 *end = cea[2]; 3541 if (*end == 0) 3542 *end = 127; 3543 if (*end < 4 || *end > 127) 3544 return -ERANGE; 3545 return 0; 3546 } 3547 3548 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3549 { 3550 int hdmi_id; 3551 3552 if (cea_db_tag(db) != VENDOR_BLOCK) 3553 return false; 3554 3555 if (cea_db_payload_len(db) < 5) 3556 return false; 3557 3558 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3559 3560 return hdmi_id == HDMI_IEEE_OUI; 3561 } 3562 3563 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3564 { 3565 unsigned int oui; 3566 3567 if (cea_db_tag(db) != VENDOR_BLOCK) 3568 return false; 3569 3570 if (cea_db_payload_len(db) < 7) 3571 return false; 3572 3573 oui = db[3] << 16 | db[2] << 8 | db[1]; 3574 3575 return oui == HDMI_FORUM_IEEE_OUI; 3576 } 3577 3578 static bool cea_db_is_y420cmdb(const u8 *db) 3579 { 3580 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3581 return false; 3582 3583 if (!cea_db_payload_len(db)) 3584 return false; 3585 3586 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3587 return false; 3588 3589 return true; 3590 } 3591 3592 static bool cea_db_is_y420vdb(const u8 *db) 3593 { 3594 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3595 return false; 3596 3597 if (!cea_db_payload_len(db)) 3598 return false; 3599 3600 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3601 return false; 3602 3603 return true; 3604 } 3605 3606 #define for_each_cea_db(cea, i, start, end) \ 3607 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3608 3609 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3610 const u8 *db) 3611 { 3612 struct drm_display_info *info = &connector->display_info; 3613 struct drm_hdmi_info *hdmi = &info->hdmi; 3614 u8 map_len = cea_db_payload_len(db) - 1; 3615 u8 count; 3616 u64 map = 0; 3617 3618 if (map_len == 0) { 3619 /* All CEA modes support ycbcr420 sampling also.*/ 3620 hdmi->y420_cmdb_map = U64_MAX; 3621 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3622 return; 3623 } 3624 3625 /* 3626 * This map indicates which of the existing CEA block modes 3627 * from VDB can support YCBCR420 output too. So if bit=0 is 3628 * set, first mode from VDB can support YCBCR420 output too. 3629 * We will parse and keep this map, before parsing VDB itself 3630 * to avoid going through the same block again and again. 3631 * 3632 * Spec is not clear about max possible size of this block. 3633 * Clamping max bitmap block size at 8 bytes. Every byte can 3634 * address 8 CEA modes, in this way this map can address 3635 * 8*8 = first 64 SVDs. 3636 */ 3637 if (WARN_ON_ONCE(map_len > 8)) 3638 map_len = 8; 3639 3640 for (count = 0; count < map_len; count++) 3641 map |= (u64)db[2 + count] << (8 * count); 3642 3643 if (map) 3644 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3645 3646 hdmi->y420_cmdb_map = map; 3647 } 3648 3649 static int 3650 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3651 { 3652 const u8 *cea = drm_find_cea_extension(edid); 3653 const u8 *db, *hdmi = NULL, *video = NULL; 3654 u8 dbl, hdmi_len, video_len = 0; 3655 int modes = 0; 3656 3657 if (cea && cea_revision(cea) >= 3) { 3658 int i, start, end; 3659 3660 if (cea_db_offsets(cea, &start, &end)) 3661 return 0; 3662 3663 for_each_cea_db(cea, i, start, end) { 3664 db = &cea[i]; 3665 dbl = cea_db_payload_len(db); 3666 3667 if (cea_db_tag(db) == VIDEO_BLOCK) { 3668 video = db + 1; 3669 video_len = dbl; 3670 modes += do_cea_modes(connector, video, dbl); 3671 } else if (cea_db_is_hdmi_vsdb(db)) { 3672 hdmi = db; 3673 hdmi_len = dbl; 3674 } else if (cea_db_is_y420vdb(db)) { 3675 const u8 *vdb420 = &db[2]; 3676 3677 /* Add 4:2:0(only) modes present in EDID */ 3678 modes += do_y420vdb_modes(connector, 3679 vdb420, 3680 dbl - 1); 3681 } 3682 } 3683 } 3684 3685 /* 3686 * We parse the HDMI VSDB after having added the cea modes as we will 3687 * be patching their flags when the sink supports stereo 3D. 3688 */ 3689 if (hdmi) 3690 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3691 video_len); 3692 3693 return modes; 3694 } 3695 3696 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3697 { 3698 const struct drm_display_mode *cea_mode; 3699 int clock1, clock2, clock; 3700 u8 vic; 3701 const char *type; 3702 3703 /* 3704 * allow 5kHz clock difference either way to account for 3705 * the 10kHz clock resolution limit of detailed timings. 3706 */ 3707 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3708 if (drm_valid_cea_vic(vic)) { 3709 type = "CEA"; 3710 cea_mode = &edid_cea_modes[vic]; 3711 clock1 = cea_mode->clock; 3712 clock2 = cea_mode_alternate_clock(cea_mode); 3713 } else { 3714 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3715 if (drm_valid_hdmi_vic(vic)) { 3716 type = "HDMI"; 3717 cea_mode = &edid_4k_modes[vic]; 3718 clock1 = cea_mode->clock; 3719 clock2 = hdmi_mode_alternate_clock(cea_mode); 3720 } else { 3721 return; 3722 } 3723 } 3724 3725 /* pick whichever is closest */ 3726 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3727 clock = clock1; 3728 else 3729 clock = clock2; 3730 3731 if (mode->clock == clock) 3732 return; 3733 3734 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3735 type, vic, mode->clock, clock); 3736 mode->clock = clock; 3737 } 3738 3739 static void 3740 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3741 { 3742 u8 len = cea_db_payload_len(db); 3743 3744 if (len >= 6) 3745 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3746 if (len >= 8) { 3747 connector->latency_present[0] = db[8] >> 7; 3748 connector->latency_present[1] = (db[8] >> 6) & 1; 3749 } 3750 if (len >= 9) 3751 connector->video_latency[0] = db[9]; 3752 if (len >= 10) 3753 connector->audio_latency[0] = db[10]; 3754 if (len >= 11) 3755 connector->video_latency[1] = db[11]; 3756 if (len >= 12) 3757 connector->audio_latency[1] = db[12]; 3758 3759 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3760 "video latency %d %d, " 3761 "audio latency %d %d\n", 3762 connector->latency_present[0], 3763 connector->latency_present[1], 3764 connector->video_latency[0], 3765 connector->video_latency[1], 3766 connector->audio_latency[0], 3767 connector->audio_latency[1]); 3768 } 3769 3770 static void 3771 monitor_name(struct detailed_timing *t, void *data) 3772 { 3773 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3774 *(u8 **)data = t->data.other_data.data.str.str; 3775 } 3776 3777 static int get_monitor_name(struct edid *edid, char name[13]) 3778 { 3779 char *edid_name = NULL; 3780 int mnl; 3781 3782 if (!edid || !name) 3783 return 0; 3784 3785 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3786 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3787 if (edid_name[mnl] == 0x0a) 3788 break; 3789 3790 name[mnl] = edid_name[mnl]; 3791 } 3792 3793 return mnl; 3794 } 3795 3796 /** 3797 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3798 * @edid: monitor EDID information 3799 * @name: pointer to a character array to hold the name of the monitor 3800 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3801 * 3802 */ 3803 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3804 { 3805 int name_length; 3806 char buf[13]; 3807 3808 if (bufsize <= 0) 3809 return; 3810 3811 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3812 memcpy(name, buf, name_length); 3813 name[name_length] = '\0'; 3814 } 3815 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3816 3817 /** 3818 * drm_edid_to_eld - build ELD from EDID 3819 * @connector: connector corresponding to the HDMI/DP sink 3820 * @edid: EDID to parse 3821 * 3822 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3823 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3824 * fill in. 3825 */ 3826 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3827 { 3828 uint8_t *eld = connector->eld; 3829 u8 *cea; 3830 u8 *db; 3831 int total_sad_count = 0; 3832 int mnl; 3833 int dbl; 3834 3835 memset(eld, 0, sizeof(connector->eld)); 3836 3837 connector->latency_present[0] = false; 3838 connector->latency_present[1] = false; 3839 connector->video_latency[0] = 0; 3840 connector->audio_latency[0] = 0; 3841 connector->video_latency[1] = 0; 3842 connector->audio_latency[1] = 0; 3843 3844 if (!edid) 3845 return; 3846 3847 cea = drm_find_cea_extension(edid); 3848 if (!cea) { 3849 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3850 return; 3851 } 3852 3853 mnl = get_monitor_name(edid, eld + 20); 3854 3855 eld[4] = (cea[1] << 5) | mnl; 3856 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3857 3858 eld[0] = 2 << 3; /* ELD version: 2 */ 3859 3860 eld[16] = edid->mfg_id[0]; 3861 eld[17] = edid->mfg_id[1]; 3862 eld[18] = edid->prod_code[0]; 3863 eld[19] = edid->prod_code[1]; 3864 3865 if (cea_revision(cea) >= 3) { 3866 int i, start, end; 3867 3868 if (cea_db_offsets(cea, &start, &end)) { 3869 start = 0; 3870 end = 0; 3871 } 3872 3873 for_each_cea_db(cea, i, start, end) { 3874 db = &cea[i]; 3875 dbl = cea_db_payload_len(db); 3876 3877 switch (cea_db_tag(db)) { 3878 int sad_count; 3879 3880 case AUDIO_BLOCK: 3881 /* Audio Data Block, contains SADs */ 3882 sad_count = min(dbl / 3, 15 - total_sad_count); 3883 if (sad_count >= 1) 3884 memcpy(eld + 20 + mnl + total_sad_count * 3, 3885 &db[1], sad_count * 3); 3886 total_sad_count += sad_count; 3887 break; 3888 case SPEAKER_BLOCK: 3889 /* Speaker Allocation Data Block */ 3890 if (dbl >= 1) 3891 eld[7] = db[1]; 3892 break; 3893 case VENDOR_BLOCK: 3894 /* HDMI Vendor-Specific Data Block */ 3895 if (cea_db_is_hdmi_vsdb(db)) 3896 drm_parse_hdmi_vsdb_audio(connector, db); 3897 break; 3898 default: 3899 break; 3900 } 3901 } 3902 } 3903 eld[5] |= total_sad_count << 4; 3904 3905 eld[DRM_ELD_BASELINE_ELD_LEN] = 3906 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3907 3908 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3909 drm_eld_size(eld), total_sad_count); 3910 } 3911 EXPORT_SYMBOL(drm_edid_to_eld); 3912 3913 /** 3914 * drm_edid_to_sad - extracts SADs from EDID 3915 * @edid: EDID to parse 3916 * @sads: pointer that will be set to the extracted SADs 3917 * 3918 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3919 * 3920 * Note: The returned pointer needs to be freed using kfree(). 3921 * 3922 * Return: The number of found SADs or negative number on error. 3923 */ 3924 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3925 { 3926 int count = 0; 3927 int i, start, end, dbl; 3928 u8 *cea; 3929 3930 cea = drm_find_cea_extension(edid); 3931 if (!cea) { 3932 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3933 return -ENOENT; 3934 } 3935 3936 if (cea_revision(cea) < 3) { 3937 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3938 return -ENOTSUPP; 3939 } 3940 3941 if (cea_db_offsets(cea, &start, &end)) { 3942 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3943 return -EPROTO; 3944 } 3945 3946 for_each_cea_db(cea, i, start, end) { 3947 u8 *db = &cea[i]; 3948 3949 if (cea_db_tag(db) == AUDIO_BLOCK) { 3950 int j; 3951 dbl = cea_db_payload_len(db); 3952 3953 count = dbl / 3; /* SAD is 3B */ 3954 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3955 if (!*sads) 3956 return -ENOMEM; 3957 for (j = 0; j < count; j++) { 3958 u8 *sad = &db[1 + j * 3]; 3959 3960 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3961 (*sads)[j].channels = sad[0] & 0x7; 3962 (*sads)[j].freq = sad[1] & 0x7F; 3963 (*sads)[j].byte2 = sad[2]; 3964 } 3965 break; 3966 } 3967 } 3968 3969 return count; 3970 } 3971 EXPORT_SYMBOL(drm_edid_to_sad); 3972 3973 /** 3974 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3975 * @edid: EDID to parse 3976 * @sadb: pointer to the speaker block 3977 * 3978 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3979 * 3980 * Note: The returned pointer needs to be freed using kfree(). 3981 * 3982 * Return: The number of found Speaker Allocation Blocks or negative number on 3983 * error. 3984 */ 3985 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3986 { 3987 int count = 0; 3988 int i, start, end, dbl; 3989 const u8 *cea; 3990 3991 cea = drm_find_cea_extension(edid); 3992 if (!cea) { 3993 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3994 return -ENOENT; 3995 } 3996 3997 if (cea_revision(cea) < 3) { 3998 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3999 return -ENOTSUPP; 4000 } 4001 4002 if (cea_db_offsets(cea, &start, &end)) { 4003 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4004 return -EPROTO; 4005 } 4006 4007 for_each_cea_db(cea, i, start, end) { 4008 const u8 *db = &cea[i]; 4009 4010 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4011 dbl = cea_db_payload_len(db); 4012 4013 /* Speaker Allocation Data Block */ 4014 if (dbl == 3) { 4015 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4016 if (!*sadb) 4017 return -ENOMEM; 4018 count = dbl; 4019 break; 4020 } 4021 } 4022 } 4023 4024 return count; 4025 } 4026 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4027 4028 /** 4029 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4030 * @connector: connector associated with the HDMI/DP sink 4031 * @mode: the display mode 4032 * 4033 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4034 * the sink doesn't support audio or video. 4035 */ 4036 int drm_av_sync_delay(struct drm_connector *connector, 4037 const struct drm_display_mode *mode) 4038 { 4039 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4040 int a, v; 4041 4042 if (!connector->latency_present[0]) 4043 return 0; 4044 if (!connector->latency_present[1]) 4045 i = 0; 4046 4047 a = connector->audio_latency[i]; 4048 v = connector->video_latency[i]; 4049 4050 /* 4051 * HDMI/DP sink doesn't support audio or video? 4052 */ 4053 if (a == 255 || v == 255) 4054 return 0; 4055 4056 /* 4057 * Convert raw EDID values to millisecond. 4058 * Treat unknown latency as 0ms. 4059 */ 4060 if (a) 4061 a = min(2 * (a - 1), 500); 4062 if (v) 4063 v = min(2 * (v - 1), 500); 4064 4065 return max(v - a, 0); 4066 } 4067 EXPORT_SYMBOL(drm_av_sync_delay); 4068 4069 /** 4070 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4071 * @edid: monitor EDID information 4072 * 4073 * Parse the CEA extension according to CEA-861-B. 4074 * 4075 * Return: True if the monitor is HDMI, false if not or unknown. 4076 */ 4077 bool drm_detect_hdmi_monitor(struct edid *edid) 4078 { 4079 u8 *edid_ext; 4080 int i; 4081 int start_offset, end_offset; 4082 4083 edid_ext = drm_find_cea_extension(edid); 4084 if (!edid_ext) 4085 return false; 4086 4087 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4088 return false; 4089 4090 /* 4091 * Because HDMI identifier is in Vendor Specific Block, 4092 * search it from all data blocks of CEA extension. 4093 */ 4094 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4095 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4096 return true; 4097 } 4098 4099 return false; 4100 } 4101 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4102 4103 /** 4104 * drm_detect_monitor_audio - check monitor audio capability 4105 * @edid: EDID block to scan 4106 * 4107 * Monitor should have CEA extension block. 4108 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4109 * audio' only. If there is any audio extension block and supported 4110 * audio format, assume at least 'basic audio' support, even if 'basic 4111 * audio' is not defined in EDID. 4112 * 4113 * Return: True if the monitor supports audio, false otherwise. 4114 */ 4115 bool drm_detect_monitor_audio(struct edid *edid) 4116 { 4117 u8 *edid_ext; 4118 int i, j; 4119 bool has_audio = false; 4120 int start_offset, end_offset; 4121 4122 edid_ext = drm_find_cea_extension(edid); 4123 if (!edid_ext) 4124 goto end; 4125 4126 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4127 4128 if (has_audio) { 4129 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4130 goto end; 4131 } 4132 4133 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4134 goto end; 4135 4136 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4137 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4138 has_audio = true; 4139 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4140 DRM_DEBUG_KMS("CEA audio format %d\n", 4141 (edid_ext[i + j] >> 3) & 0xf); 4142 goto end; 4143 } 4144 } 4145 end: 4146 return has_audio; 4147 } 4148 EXPORT_SYMBOL(drm_detect_monitor_audio); 4149 4150 /** 4151 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 4152 * @edid: EDID block to scan 4153 * 4154 * Check whether the monitor reports the RGB quantization range selection 4155 * as supported. The AVI infoframe can then be used to inform the monitor 4156 * which quantization range (full or limited) is used. 4157 * 4158 * Return: True if the RGB quantization range is selectable, false otherwise. 4159 */ 4160 bool drm_rgb_quant_range_selectable(struct edid *edid) 4161 { 4162 u8 *edid_ext; 4163 int i, start, end; 4164 4165 edid_ext = drm_find_cea_extension(edid); 4166 if (!edid_ext) 4167 return false; 4168 4169 if (cea_db_offsets(edid_ext, &start, &end)) 4170 return false; 4171 4172 for_each_cea_db(edid_ext, i, start, end) { 4173 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG && 4174 cea_db_payload_len(&edid_ext[i]) == 2 && 4175 cea_db_extended_tag(&edid_ext[i]) == 4176 EXT_VIDEO_CAPABILITY_BLOCK) { 4177 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 4178 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 4179 } 4180 } 4181 4182 return false; 4183 } 4184 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 4185 4186 /** 4187 * drm_default_rgb_quant_range - default RGB quantization range 4188 * @mode: display mode 4189 * 4190 * Determine the default RGB quantization range for the mode, 4191 * as specified in CEA-861. 4192 * 4193 * Return: The default RGB quantization range for the mode 4194 */ 4195 enum hdmi_quantization_range 4196 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4197 { 4198 /* All CEA modes other than VIC 1 use limited quantization range. */ 4199 return drm_match_cea_mode(mode) > 1 ? 4200 HDMI_QUANTIZATION_RANGE_LIMITED : 4201 HDMI_QUANTIZATION_RANGE_FULL; 4202 } 4203 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4204 4205 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4206 const u8 *db) 4207 { 4208 u8 dc_mask; 4209 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4210 4211 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4212 hdmi->y420_dc_modes |= dc_mask; 4213 } 4214 4215 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4216 const u8 *hf_vsdb) 4217 { 4218 struct drm_display_info *display = &connector->display_info; 4219 struct drm_hdmi_info *hdmi = &display->hdmi; 4220 4221 if (hf_vsdb[6] & 0x80) { 4222 hdmi->scdc.supported = true; 4223 if (hf_vsdb[6] & 0x40) 4224 hdmi->scdc.read_request = true; 4225 } 4226 4227 /* 4228 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4229 * And as per the spec, three factors confirm this: 4230 * * Availability of a HF-VSDB block in EDID (check) 4231 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4232 * * SCDC support available (let's check) 4233 * Lets check it out. 4234 */ 4235 4236 if (hf_vsdb[5]) { 4237 /* max clock is 5000 KHz times block value */ 4238 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4239 struct drm_scdc *scdc = &hdmi->scdc; 4240 4241 if (max_tmds_clock > 340000) { 4242 display->max_tmds_clock = max_tmds_clock; 4243 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4244 display->max_tmds_clock); 4245 } 4246 4247 if (scdc->supported) { 4248 scdc->scrambling.supported = true; 4249 4250 /* Few sinks support scrambling for cloks < 340M */ 4251 if ((hf_vsdb[6] & 0x8)) 4252 scdc->scrambling.low_rates = true; 4253 } 4254 } 4255 4256 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4257 } 4258 4259 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4260 const u8 *hdmi) 4261 { 4262 struct drm_display_info *info = &connector->display_info; 4263 unsigned int dc_bpc = 0; 4264 4265 /* HDMI supports at least 8 bpc */ 4266 info->bpc = 8; 4267 4268 if (cea_db_payload_len(hdmi) < 6) 4269 return; 4270 4271 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4272 dc_bpc = 10; 4273 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4274 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4275 connector->name); 4276 } 4277 4278 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4279 dc_bpc = 12; 4280 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4281 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4282 connector->name); 4283 } 4284 4285 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4286 dc_bpc = 16; 4287 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4288 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4289 connector->name); 4290 } 4291 4292 if (dc_bpc == 0) { 4293 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4294 connector->name); 4295 return; 4296 } 4297 4298 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4299 connector->name, dc_bpc); 4300 info->bpc = dc_bpc; 4301 4302 /* 4303 * Deep color support mandates RGB444 support for all video 4304 * modes and forbids YCRCB422 support for all video modes per 4305 * HDMI 1.3 spec. 4306 */ 4307 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4308 4309 /* YCRCB444 is optional according to spec. */ 4310 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4311 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4312 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4313 connector->name); 4314 } 4315 4316 /* 4317 * Spec says that if any deep color mode is supported at all, 4318 * then deep color 36 bit must be supported. 4319 */ 4320 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4321 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4322 connector->name); 4323 } 4324 } 4325 4326 static void 4327 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4328 { 4329 struct drm_display_info *info = &connector->display_info; 4330 u8 len = cea_db_payload_len(db); 4331 4332 if (len >= 6) 4333 info->dvi_dual = db[6] & 1; 4334 if (len >= 7) 4335 info->max_tmds_clock = db[7] * 5000; 4336 4337 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4338 "max TMDS clock %d kHz\n", 4339 info->dvi_dual, 4340 info->max_tmds_clock); 4341 4342 drm_parse_hdmi_deep_color_info(connector, db); 4343 } 4344 4345 static void drm_parse_cea_ext(struct drm_connector *connector, 4346 struct edid *edid) 4347 { 4348 struct drm_display_info *info = &connector->display_info; 4349 const u8 *edid_ext; 4350 int i, start, end; 4351 4352 edid_ext = drm_find_cea_extension(edid); 4353 if (!edid_ext) 4354 return; 4355 4356 info->cea_rev = edid_ext[1]; 4357 4358 /* The existence of a CEA block should imply RGB support */ 4359 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4360 if (edid_ext[3] & EDID_CEA_YCRCB444) 4361 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4362 if (edid_ext[3] & EDID_CEA_YCRCB422) 4363 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4364 4365 if (cea_db_offsets(edid_ext, &start, &end)) 4366 return; 4367 4368 for_each_cea_db(edid_ext, i, start, end) { 4369 const u8 *db = &edid_ext[i]; 4370 4371 if (cea_db_is_hdmi_vsdb(db)) 4372 drm_parse_hdmi_vsdb_video(connector, db); 4373 if (cea_db_is_hdmi_forum_vsdb(db)) 4374 drm_parse_hdmi_forum_vsdb(connector, db); 4375 if (cea_db_is_y420cmdb(db)) 4376 drm_parse_y420cmdb_bitmap(connector, db); 4377 } 4378 } 4379 4380 static void drm_add_display_info(struct drm_connector *connector, 4381 struct edid *edid) 4382 { 4383 struct drm_display_info *info = &connector->display_info; 4384 4385 info->width_mm = edid->width_cm * 10; 4386 info->height_mm = edid->height_cm * 10; 4387 4388 /* driver figures it out in this case */ 4389 info->bpc = 0; 4390 info->color_formats = 0; 4391 info->cea_rev = 0; 4392 info->max_tmds_clock = 0; 4393 info->dvi_dual = false; 4394 4395 if (edid->revision < 3) 4396 return; 4397 4398 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4399 return; 4400 4401 drm_parse_cea_ext(connector, edid); 4402 4403 /* 4404 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4405 * 4406 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4407 * tells us to assume 8 bpc color depth if the EDID doesn't have 4408 * extensions which tell otherwise. 4409 */ 4410 if ((info->bpc == 0) && (edid->revision < 4) && 4411 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4412 info->bpc = 8; 4413 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4414 connector->name, info->bpc); 4415 } 4416 4417 /* Only defined for 1.4 with digital displays */ 4418 if (edid->revision < 4) 4419 return; 4420 4421 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4422 case DRM_EDID_DIGITAL_DEPTH_6: 4423 info->bpc = 6; 4424 break; 4425 case DRM_EDID_DIGITAL_DEPTH_8: 4426 info->bpc = 8; 4427 break; 4428 case DRM_EDID_DIGITAL_DEPTH_10: 4429 info->bpc = 10; 4430 break; 4431 case DRM_EDID_DIGITAL_DEPTH_12: 4432 info->bpc = 12; 4433 break; 4434 case DRM_EDID_DIGITAL_DEPTH_14: 4435 info->bpc = 14; 4436 break; 4437 case DRM_EDID_DIGITAL_DEPTH_16: 4438 info->bpc = 16; 4439 break; 4440 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4441 default: 4442 info->bpc = 0; 4443 break; 4444 } 4445 4446 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4447 connector->name, info->bpc); 4448 4449 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4450 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4451 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4452 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4453 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4454 } 4455 4456 static int validate_displayid(u8 *displayid, int length, int idx) 4457 { 4458 int i; 4459 u8 csum = 0; 4460 struct displayid_hdr *base; 4461 4462 base = (struct displayid_hdr *)&displayid[idx]; 4463 4464 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4465 base->rev, base->bytes, base->prod_id, base->ext_count); 4466 4467 if (base->bytes + 5 > length - idx) 4468 return -EINVAL; 4469 for (i = idx; i <= base->bytes + 5; i++) { 4470 csum += displayid[i]; 4471 } 4472 if (csum) { 4473 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4474 return -EINVAL; 4475 } 4476 return 0; 4477 } 4478 4479 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4480 struct displayid_detailed_timings_1 *timings) 4481 { 4482 struct drm_display_mode *mode; 4483 unsigned pixel_clock = (timings->pixel_clock[0] | 4484 (timings->pixel_clock[1] << 8) | 4485 (timings->pixel_clock[2] << 16)); 4486 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4487 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4488 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4489 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4490 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4491 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4492 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4493 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4494 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4495 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4496 mode = drm_mode_create(dev); 4497 if (!mode) 4498 return NULL; 4499 4500 mode->clock = pixel_clock * 10; 4501 mode->hdisplay = hactive; 4502 mode->hsync_start = mode->hdisplay + hsync; 4503 mode->hsync_end = mode->hsync_start + hsync_width; 4504 mode->htotal = mode->hdisplay + hblank; 4505 4506 mode->vdisplay = vactive; 4507 mode->vsync_start = mode->vdisplay + vsync; 4508 mode->vsync_end = mode->vsync_start + vsync_width; 4509 mode->vtotal = mode->vdisplay + vblank; 4510 4511 mode->flags = 0; 4512 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4513 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4514 mode->type = DRM_MODE_TYPE_DRIVER; 4515 4516 if (timings->flags & 0x80) 4517 mode->type |= DRM_MODE_TYPE_PREFERRED; 4518 mode->vrefresh = drm_mode_vrefresh(mode); 4519 drm_mode_set_name(mode); 4520 4521 return mode; 4522 } 4523 4524 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4525 struct displayid_block *block) 4526 { 4527 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4528 int i; 4529 int num_timings; 4530 struct drm_display_mode *newmode; 4531 int num_modes = 0; 4532 /* blocks must be multiple of 20 bytes length */ 4533 if (block->num_bytes % 20) 4534 return 0; 4535 4536 num_timings = block->num_bytes / 20; 4537 for (i = 0; i < num_timings; i++) { 4538 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4539 4540 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4541 if (!newmode) 4542 continue; 4543 4544 drm_mode_probed_add(connector, newmode); 4545 num_modes++; 4546 } 4547 return num_modes; 4548 } 4549 4550 static int add_displayid_detailed_modes(struct drm_connector *connector, 4551 struct edid *edid) 4552 { 4553 u8 *displayid; 4554 int ret; 4555 int idx = 1; 4556 int length = EDID_LENGTH; 4557 struct displayid_block *block; 4558 int num_modes = 0; 4559 4560 displayid = drm_find_displayid_extension(edid); 4561 if (!displayid) 4562 return 0; 4563 4564 ret = validate_displayid(displayid, length, idx); 4565 if (ret) 4566 return 0; 4567 4568 idx += sizeof(struct displayid_hdr); 4569 while (block = (struct displayid_block *)&displayid[idx], 4570 idx + sizeof(struct displayid_block) <= length && 4571 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4572 block->num_bytes > 0) { 4573 idx += block->num_bytes + sizeof(struct displayid_block); 4574 switch (block->tag) { 4575 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4576 num_modes += add_displayid_detailed_1_modes(connector, block); 4577 break; 4578 } 4579 } 4580 return num_modes; 4581 } 4582 4583 /** 4584 * drm_add_edid_modes - add modes from EDID data, if available 4585 * @connector: connector we're probing 4586 * @edid: EDID data 4587 * 4588 * Add the specified modes to the connector's mode list. Also fills out the 4589 * &drm_display_info structure in @connector with any information which can be 4590 * derived from the edid. 4591 * 4592 * Return: The number of modes added or 0 if we couldn't find any. 4593 */ 4594 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4595 { 4596 int num_modes = 0; 4597 u32 quirks; 4598 4599 if (edid == NULL) { 4600 return 0; 4601 } 4602 if (!drm_edid_is_valid(edid)) { 4603 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4604 connector->name); 4605 return 0; 4606 } 4607 4608 quirks = edid_get_quirks(edid); 4609 4610 /* 4611 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4612 * To avoid multiple parsing of same block, lets parse that map 4613 * from sink info, before parsing CEA modes. 4614 */ 4615 drm_add_display_info(connector, edid); 4616 4617 /* 4618 * EDID spec says modes should be preferred in this order: 4619 * - preferred detailed mode 4620 * - other detailed modes from base block 4621 * - detailed modes from extension blocks 4622 * - CVT 3-byte code modes 4623 * - standard timing codes 4624 * - established timing codes 4625 * - modes inferred from GTF or CVT range information 4626 * 4627 * We get this pretty much right. 4628 * 4629 * XXX order for additional mode types in extension blocks? 4630 */ 4631 num_modes += add_detailed_modes(connector, edid, quirks); 4632 num_modes += add_cvt_modes(connector, edid); 4633 num_modes += add_standard_modes(connector, edid); 4634 num_modes += add_established_modes(connector, edid); 4635 num_modes += add_cea_modes(connector, edid); 4636 num_modes += add_alternate_cea_modes(connector, edid); 4637 num_modes += add_displayid_detailed_modes(connector, edid); 4638 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4639 num_modes += add_inferred_modes(connector, edid); 4640 4641 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4642 edid_fixup_preferred(connector, quirks); 4643 4644 if (quirks & EDID_QUIRK_FORCE_6BPC) 4645 connector->display_info.bpc = 6; 4646 4647 if (quirks & EDID_QUIRK_FORCE_8BPC) 4648 connector->display_info.bpc = 8; 4649 4650 if (quirks & EDID_QUIRK_FORCE_10BPC) 4651 connector->display_info.bpc = 10; 4652 4653 if (quirks & EDID_QUIRK_FORCE_12BPC) 4654 connector->display_info.bpc = 12; 4655 4656 return num_modes; 4657 } 4658 EXPORT_SYMBOL(drm_add_edid_modes); 4659 4660 /** 4661 * drm_add_modes_noedid - add modes for the connectors without EDID 4662 * @connector: connector we're probing 4663 * @hdisplay: the horizontal display limit 4664 * @vdisplay: the vertical display limit 4665 * 4666 * Add the specified modes to the connector's mode list. Only when the 4667 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4668 * 4669 * Return: The number of modes added or 0 if we couldn't find any. 4670 */ 4671 int drm_add_modes_noedid(struct drm_connector *connector, 4672 int hdisplay, int vdisplay) 4673 { 4674 int i, count, num_modes = 0; 4675 struct drm_display_mode *mode; 4676 struct drm_device *dev = connector->dev; 4677 4678 count = ARRAY_SIZE(drm_dmt_modes); 4679 if (hdisplay < 0) 4680 hdisplay = 0; 4681 if (vdisplay < 0) 4682 vdisplay = 0; 4683 4684 for (i = 0; i < count; i++) { 4685 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4686 if (hdisplay && vdisplay) { 4687 /* 4688 * Only when two are valid, they will be used to check 4689 * whether the mode should be added to the mode list of 4690 * the connector. 4691 */ 4692 if (ptr->hdisplay > hdisplay || 4693 ptr->vdisplay > vdisplay) 4694 continue; 4695 } 4696 if (drm_mode_vrefresh(ptr) > 61) 4697 continue; 4698 mode = drm_mode_duplicate(dev, ptr); 4699 if (mode) { 4700 drm_mode_probed_add(connector, mode); 4701 num_modes++; 4702 } 4703 } 4704 return num_modes; 4705 } 4706 EXPORT_SYMBOL(drm_add_modes_noedid); 4707 4708 /** 4709 * drm_set_preferred_mode - Sets the preferred mode of a connector 4710 * @connector: connector whose mode list should be processed 4711 * @hpref: horizontal resolution of preferred mode 4712 * @vpref: vertical resolution of preferred mode 4713 * 4714 * Marks a mode as preferred if it matches the resolution specified by @hpref 4715 * and @vpref. 4716 */ 4717 void drm_set_preferred_mode(struct drm_connector *connector, 4718 int hpref, int vpref) 4719 { 4720 struct drm_display_mode *mode; 4721 4722 list_for_each_entry(mode, &connector->probed_modes, head) { 4723 if (mode->hdisplay == hpref && 4724 mode->vdisplay == vpref) 4725 mode->type |= DRM_MODE_TYPE_PREFERRED; 4726 } 4727 } 4728 EXPORT_SYMBOL(drm_set_preferred_mode); 4729 4730 /** 4731 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4732 * data from a DRM display mode 4733 * @frame: HDMI AVI infoframe 4734 * @mode: DRM display mode 4735 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant 4736 * 4737 * Return: 0 on success or a negative error code on failure. 4738 */ 4739 int 4740 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4741 const struct drm_display_mode *mode, 4742 bool is_hdmi2_sink) 4743 { 4744 int err; 4745 4746 if (!frame || !mode) 4747 return -EINVAL; 4748 4749 err = hdmi_avi_infoframe_init(frame); 4750 if (err < 0) 4751 return err; 4752 4753 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4754 frame->pixel_repeat = 1; 4755 4756 frame->video_code = drm_match_cea_mode(mode); 4757 4758 /* 4759 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4760 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4761 * have to make sure we dont break HDMI 1.4 sinks. 4762 */ 4763 if (!is_hdmi2_sink && frame->video_code > 64) 4764 frame->video_code = 0; 4765 4766 /* 4767 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 4768 * we should send its VIC in vendor infoframes, else send the 4769 * VIC in AVI infoframes. Lets check if this mode is present in 4770 * HDMI 1.4b 4K modes 4771 */ 4772 if (frame->video_code) { 4773 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 4774 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 4775 4776 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 4777 frame->video_code = 0; 4778 } 4779 4780 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4781 4782 /* 4783 * Populate picture aspect ratio from either 4784 * user input (if specified) or from the CEA mode list. 4785 */ 4786 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4787 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4788 frame->picture_aspect = mode->picture_aspect_ratio; 4789 else if (frame->video_code > 0) 4790 frame->picture_aspect = drm_get_cea_aspect_ratio( 4791 frame->video_code); 4792 4793 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4794 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4795 4796 return 0; 4797 } 4798 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4799 4800 /** 4801 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4802 * quantization range information 4803 * @frame: HDMI AVI infoframe 4804 * @mode: DRM display mode 4805 * @rgb_quant_range: RGB quantization range (Q) 4806 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 4807 */ 4808 void 4809 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 4810 const struct drm_display_mode *mode, 4811 enum hdmi_quantization_range rgb_quant_range, 4812 bool rgb_quant_range_selectable) 4813 { 4814 /* 4815 * CEA-861: 4816 * "A Source shall not send a non-zero Q value that does not correspond 4817 * to the default RGB Quantization Range for the transmitted Picture 4818 * unless the Sink indicates support for the Q bit in a Video 4819 * Capabilities Data Block." 4820 * 4821 * HDMI 2.0 recommends sending non-zero Q when it does match the 4822 * default RGB quantization range for the mode, even when QS=0. 4823 */ 4824 if (rgb_quant_range_selectable || 4825 rgb_quant_range == drm_default_rgb_quant_range(mode)) 4826 frame->quantization_range = rgb_quant_range; 4827 else 4828 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 4829 4830 /* 4831 * CEA-861-F: 4832 * "When transmitting any RGB colorimetry, the Source should set the 4833 * YQ-field to match the RGB Quantization Range being transmitted 4834 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 4835 * set YQ=1) and the Sink shall ignore the YQ-field." 4836 */ 4837 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4838 frame->ycc_quantization_range = 4839 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 4840 else 4841 frame->ycc_quantization_range = 4842 HDMI_YCC_QUANTIZATION_RANGE_FULL; 4843 } 4844 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 4845 4846 static enum hdmi_3d_structure 4847 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4848 { 4849 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4850 4851 switch (layout) { 4852 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4853 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4854 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4855 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4856 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4857 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4858 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4859 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4860 case DRM_MODE_FLAG_3D_L_DEPTH: 4861 return HDMI_3D_STRUCTURE_L_DEPTH; 4862 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4863 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4864 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4865 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4866 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4867 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4868 default: 4869 return HDMI_3D_STRUCTURE_INVALID; 4870 } 4871 } 4872 4873 /** 4874 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4875 * data from a DRM display mode 4876 * @frame: HDMI vendor infoframe 4877 * @mode: DRM display mode 4878 * 4879 * Note that there's is a need to send HDMI vendor infoframes only when using a 4880 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4881 * function will return -EINVAL, error that can be safely ignored. 4882 * 4883 * Return: 0 on success or a negative error code on failure. 4884 */ 4885 int 4886 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4887 const struct drm_display_mode *mode) 4888 { 4889 int err; 4890 u32 s3d_flags; 4891 u8 vic; 4892 4893 if (!frame || !mode) 4894 return -EINVAL; 4895 4896 vic = drm_match_hdmi_mode(mode); 4897 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4898 4899 if (!vic && !s3d_flags) 4900 return -EINVAL; 4901 4902 if (vic && s3d_flags) 4903 return -EINVAL; 4904 4905 err = hdmi_vendor_infoframe_init(frame); 4906 if (err < 0) 4907 return err; 4908 4909 if (vic) 4910 frame->vic = vic; 4911 else 4912 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4913 4914 return 0; 4915 } 4916 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4917 4918 static int drm_parse_tiled_block(struct drm_connector *connector, 4919 struct displayid_block *block) 4920 { 4921 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4922 u16 w, h; 4923 u8 tile_v_loc, tile_h_loc; 4924 u8 num_v_tile, num_h_tile; 4925 struct drm_tile_group *tg; 4926 4927 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4928 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4929 4930 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4931 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4932 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4933 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4934 4935 connector->has_tile = true; 4936 if (tile->tile_cap & 0x80) 4937 connector->tile_is_single_monitor = true; 4938 4939 connector->num_h_tile = num_h_tile + 1; 4940 connector->num_v_tile = num_v_tile + 1; 4941 connector->tile_h_loc = tile_h_loc; 4942 connector->tile_v_loc = tile_v_loc; 4943 connector->tile_h_size = w + 1; 4944 connector->tile_v_size = h + 1; 4945 4946 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4947 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4948 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4949 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4950 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4951 4952 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4953 if (!tg) { 4954 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4955 } 4956 if (!tg) 4957 return -ENOMEM; 4958 4959 if (connector->tile_group != tg) { 4960 /* if we haven't got a pointer, 4961 take the reference, drop ref to old tile group */ 4962 if (connector->tile_group) { 4963 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4964 } 4965 connector->tile_group = tg; 4966 } else 4967 /* if same tile group, then release the ref we just took. */ 4968 drm_mode_put_tile_group(connector->dev, tg); 4969 return 0; 4970 } 4971 4972 static int drm_parse_display_id(struct drm_connector *connector, 4973 u8 *displayid, int length, 4974 bool is_edid_extension) 4975 { 4976 /* if this is an EDID extension the first byte will be 0x70 */ 4977 int idx = 0; 4978 struct displayid_block *block; 4979 int ret; 4980 4981 if (is_edid_extension) 4982 idx = 1; 4983 4984 ret = validate_displayid(displayid, length, idx); 4985 if (ret) 4986 return ret; 4987 4988 idx += sizeof(struct displayid_hdr); 4989 while (block = (struct displayid_block *)&displayid[idx], 4990 idx + sizeof(struct displayid_block) <= length && 4991 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4992 block->num_bytes > 0) { 4993 idx += block->num_bytes + sizeof(struct displayid_block); 4994 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4995 block->tag, block->rev, block->num_bytes); 4996 4997 switch (block->tag) { 4998 case DATA_BLOCK_TILED_DISPLAY: 4999 ret = drm_parse_tiled_block(connector, block); 5000 if (ret) 5001 return ret; 5002 break; 5003 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5004 /* handled in mode gathering code. */ 5005 break; 5006 default: 5007 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5008 break; 5009 } 5010 } 5011 return 0; 5012 } 5013 5014 static void drm_get_displayid(struct drm_connector *connector, 5015 struct edid *edid) 5016 { 5017 void *displayid = NULL; 5018 int ret; 5019 connector->has_tile = false; 5020 displayid = drm_find_displayid_extension(edid); 5021 if (!displayid) { 5022 /* drop reference to any tile group we had */ 5023 goto out_drop_ref; 5024 } 5025 5026 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5027 if (ret < 0) 5028 goto out_drop_ref; 5029 if (!connector->has_tile) 5030 goto out_drop_ref; 5031 return; 5032 out_drop_ref: 5033 if (connector->tile_group) { 5034 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5035 connector->tile_group = NULL; 5036 } 5037 return; 5038 } 5039