1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 #include <linux/vga_switcheroo.h> 38 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_encoder.h> 43 #include <drm/drm_print.h> 44 #include <drm/drm_scdc_helper.h> 45 46 #include "drm_crtc_internal.h" 47 48 #define version_greater(edid, maj, min) \ 49 (((edid)->version > (maj)) || \ 50 ((edid)->version == (maj) && (edid)->revision > (min))) 51 52 #define EDID_EST_TIMINGS 16 53 #define EDID_STD_TIMINGS 8 54 #define EDID_DETAILED_TIMINGS 4 55 56 /* 57 * EDID blocks out in the wild have a variety of bugs, try to collect 58 * them here (note that userspace may work around broken monitors first, 59 * but fixes should make their way here so that the kernel "just works" 60 * on as many displays as possible). 61 */ 62 63 /* First detailed mode wrong, use largest 60Hz mode */ 64 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 65 /* Reported 135MHz pixel clock is too high, needs adjustment */ 66 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 67 /* Prefer the largest mode at 75 Hz */ 68 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 69 /* Detail timing is in cm not mm */ 70 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 71 /* Detailed timing descriptors have bogus size values, so just take the 72 * maximum size and use that. 73 */ 74 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 75 /* use +hsync +vsync for detailed mode */ 76 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 77 /* Force reduced-blanking timings for detailed modes */ 78 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 79 /* Force 8bpc */ 80 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 81 /* Force 12bpc */ 82 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 83 /* Force 6bpc */ 84 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 85 /* Force 10bpc */ 86 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 87 /* Non desktop display (i.e. HMD) */ 88 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 89 90 struct detailed_mode_closure { 91 struct drm_connector *connector; 92 struct edid *edid; 93 bool preferred; 94 u32 quirks; 95 int modes; 96 }; 97 98 #define LEVEL_DMT 0 99 #define LEVEL_GTF 1 100 #define LEVEL_GTF2 2 101 #define LEVEL_CVT 3 102 103 #define EDID_QUIRK(vend, product_id, _quirks) \ 104 { \ 105 .panel_id = drm_edid_encode_panel_id(vend, product_id), \ 106 .quirks = _quirks \ 107 } 108 109 static const struct edid_quirk { 110 u32 panel_id; 111 u32 quirks; 112 } edid_quirk_list[] = { 113 /* Acer AL1706 */ 114 EDID_QUIRK("ACR", 44358, EDID_QUIRK_PREFER_LARGE_60), 115 /* Acer F51 */ 116 EDID_QUIRK("API", 0x7602, EDID_QUIRK_PREFER_LARGE_60), 117 118 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 119 EDID_QUIRK("AEO", 0, EDID_QUIRK_FORCE_6BPC), 120 121 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 122 EDID_QUIRK("BOE", 0x78b, EDID_QUIRK_FORCE_6BPC), 123 124 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 125 EDID_QUIRK("CPT", 0x17df, EDID_QUIRK_FORCE_6BPC), 126 127 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 128 EDID_QUIRK("SDC", 0x3652, EDID_QUIRK_FORCE_6BPC), 129 130 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 131 EDID_QUIRK("BOE", 0x0771, EDID_QUIRK_FORCE_6BPC), 132 133 /* Belinea 10 15 55 */ 134 EDID_QUIRK("MAX", 1516, EDID_QUIRK_PREFER_LARGE_60), 135 EDID_QUIRK("MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60), 136 137 /* Envision Peripherals, Inc. EN-7100e */ 138 EDID_QUIRK("EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 139 /* Envision EN2028 */ 140 EDID_QUIRK("EPI", 8232, EDID_QUIRK_PREFER_LARGE_60), 141 142 /* Funai Electronics PM36B */ 143 EDID_QUIRK("FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 144 EDID_QUIRK_DETAILED_IN_CM), 145 146 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 147 EDID_QUIRK("LGD", 764, EDID_QUIRK_FORCE_10BPC), 148 149 /* LG Philips LCD LP154W01-A5 */ 150 EDID_QUIRK("LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 151 EDID_QUIRK("LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 152 153 /* Samsung SyncMaster 205BW. Note: irony */ 154 EDID_QUIRK("SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP), 155 /* Samsung SyncMaster 22[5-6]BW */ 156 EDID_QUIRK("SAM", 596, EDID_QUIRK_PREFER_LARGE_60), 157 EDID_QUIRK("SAM", 638, EDID_QUIRK_PREFER_LARGE_60), 158 159 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 160 EDID_QUIRK("SNY", 0x2541, EDID_QUIRK_FORCE_12BPC), 161 162 /* ViewSonic VA2026w */ 163 EDID_QUIRK("VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 164 165 /* Medion MD 30217 PG */ 166 EDID_QUIRK("MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 167 168 /* Lenovo G50 */ 169 EDID_QUIRK("SDC", 18514, EDID_QUIRK_FORCE_6BPC), 170 171 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 172 EDID_QUIRK("SEC", 0xd033, EDID_QUIRK_FORCE_8BPC), 173 174 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 175 EDID_QUIRK("ETR", 13896, EDID_QUIRK_FORCE_8BPC), 176 177 /* Valve Index Headset */ 178 EDID_QUIRK("VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP), 179 EDID_QUIRK("VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP), 180 EDID_QUIRK("VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP), 181 EDID_QUIRK("VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP), 182 EDID_QUIRK("VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP), 183 EDID_QUIRK("VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP), 184 EDID_QUIRK("VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP), 185 EDID_QUIRK("VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP), 186 EDID_QUIRK("VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP), 187 EDID_QUIRK("VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP), 188 EDID_QUIRK("VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP), 189 EDID_QUIRK("VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK("VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK("VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK("VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK("VLV", 0x91be, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK("VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP), 195 196 /* HTC Vive and Vive Pro VR Headsets */ 197 EDID_QUIRK("HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK("HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP), 199 200 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 201 EDID_QUIRK("OVR", 0x0001, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK("OVR", 0x0003, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK("OVR", 0x0004, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK("OVR", 0x0012, EDID_QUIRK_NON_DESKTOP), 205 206 /* Windows Mixed Reality Headsets */ 207 EDID_QUIRK("ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK("HPN", 0x3515, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK("LEN", 0x0408, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK("LEN", 0xb800, EDID_QUIRK_NON_DESKTOP), 211 EDID_QUIRK("FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK("DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK("SEC", 0x144a, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK("AUS", 0xc102, EDID_QUIRK_NON_DESKTOP), 215 216 /* Sony PlayStation VR Headset */ 217 EDID_QUIRK("SNY", 0x0704, EDID_QUIRK_NON_DESKTOP), 218 219 /* Sensics VR Headsets */ 220 EDID_QUIRK("SEN", 0x1019, EDID_QUIRK_NON_DESKTOP), 221 222 /* OSVR HDK and HDK2 VR Headsets */ 223 EDID_QUIRK("SVR", 0x1019, EDID_QUIRK_NON_DESKTOP), 224 }; 225 226 /* 227 * Autogenerated from the DMT spec. 228 * This table is copied from xfree86/modes/xf86EdidModes.c. 229 */ 230 static const struct drm_display_mode drm_dmt_modes[] = { 231 /* 0x01 - 640x350@85Hz */ 232 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 233 736, 832, 0, 350, 382, 385, 445, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 235 /* 0x02 - 640x400@85Hz */ 236 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 237 736, 832, 0, 400, 401, 404, 445, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 239 /* 0x03 - 720x400@85Hz */ 240 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 241 828, 936, 0, 400, 401, 404, 446, 0, 242 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 243 /* 0x04 - 640x480@60Hz */ 244 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 245 752, 800, 0, 480, 490, 492, 525, 0, 246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 247 /* 0x05 - 640x480@72Hz */ 248 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 249 704, 832, 0, 480, 489, 492, 520, 0, 250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 0x06 - 640x480@75Hz */ 252 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 253 720, 840, 0, 480, 481, 484, 500, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 255 /* 0x07 - 640x480@85Hz */ 256 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 257 752, 832, 0, 480, 481, 484, 509, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 259 /* 0x08 - 800x600@56Hz */ 260 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 261 896, 1024, 0, 600, 601, 603, 625, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 263 /* 0x09 - 800x600@60Hz */ 264 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 265 968, 1056, 0, 600, 601, 605, 628, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 267 /* 0x0a - 800x600@72Hz */ 268 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 269 976, 1040, 0, 600, 637, 643, 666, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 271 /* 0x0b - 800x600@75Hz */ 272 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 273 896, 1056, 0, 600, 601, 604, 625, 0, 274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 275 /* 0x0c - 800x600@85Hz */ 276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 277 896, 1048, 0, 600, 601, 604, 631, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 0x0d - 800x600@120Hz RB */ 280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 281 880, 960, 0, 600, 603, 607, 636, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 283 /* 0x0e - 848x480@60Hz */ 284 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 285 976, 1088, 0, 480, 486, 494, 517, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 287 /* 0x0f - 1024x768@43Hz, interlace */ 288 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 289 1208, 1264, 0, 768, 768, 776, 817, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 291 DRM_MODE_FLAG_INTERLACE) }, 292 /* 0x10 - 1024x768@60Hz */ 293 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 294 1184, 1344, 0, 768, 771, 777, 806, 0, 295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x11 - 1024x768@70Hz */ 297 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 298 1184, 1328, 0, 768, 771, 777, 806, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 300 /* 0x12 - 1024x768@75Hz */ 301 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 302 1136, 1312, 0, 768, 769, 772, 800, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x13 - 1024x768@85Hz */ 305 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 306 1168, 1376, 0, 768, 769, 772, 808, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 308 /* 0x14 - 1024x768@120Hz RB */ 309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 310 1104, 1184, 0, 768, 771, 775, 813, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 312 /* 0x15 - 1152x864@75Hz */ 313 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 314 1344, 1600, 0, 864, 865, 868, 900, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x55 - 1280x720@60Hz */ 317 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 318 1430, 1650, 0, 720, 725, 730, 750, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x16 - 1280x768@60Hz RB */ 321 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 322 1360, 1440, 0, 768, 771, 778, 790, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 324 /* 0x17 - 1280x768@60Hz */ 325 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 326 1472, 1664, 0, 768, 771, 778, 798, 0, 327 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x18 - 1280x768@75Hz */ 329 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 330 1488, 1696, 0, 768, 771, 778, 805, 0, 331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 332 /* 0x19 - 1280x768@85Hz */ 333 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 334 1496, 1712, 0, 768, 771, 778, 809, 0, 335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x1a - 1280x768@120Hz RB */ 337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 338 1360, 1440, 0, 768, 771, 778, 813, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 340 /* 0x1b - 1280x800@60Hz RB */ 341 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 342 1360, 1440, 0, 800, 803, 809, 823, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 344 /* 0x1c - 1280x800@60Hz */ 345 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 346 1480, 1680, 0, 800, 803, 809, 831, 0, 347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x1d - 1280x800@75Hz */ 349 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 350 1488, 1696, 0, 800, 803, 809, 838, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x1e - 1280x800@85Hz */ 353 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 354 1496, 1712, 0, 800, 803, 809, 843, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x1f - 1280x800@120Hz RB */ 357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 358 1360, 1440, 0, 800, 803, 809, 847, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 360 /* 0x20 - 1280x960@60Hz */ 361 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 362 1488, 1800, 0, 960, 961, 964, 1000, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x21 - 1280x960@85Hz */ 365 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 366 1504, 1728, 0, 960, 961, 964, 1011, 0, 367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x22 - 1280x960@120Hz RB */ 369 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 370 1360, 1440, 0, 960, 963, 967, 1017, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 372 /* 0x23 - 1280x1024@60Hz */ 373 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 374 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x24 - 1280x1024@75Hz */ 377 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 378 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x25 - 1280x1024@85Hz */ 381 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 382 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x26 - 1280x1024@120Hz RB */ 385 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 386 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 388 /* 0x27 - 1360x768@60Hz */ 389 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 390 1536, 1792, 0, 768, 771, 777, 795, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x28 - 1360x768@120Hz RB */ 393 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 394 1440, 1520, 0, 768, 771, 776, 813, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 396 /* 0x51 - 1366x768@60Hz */ 397 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 398 1579, 1792, 0, 768, 771, 774, 798, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x56 - 1366x768@60Hz */ 401 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 402 1436, 1500, 0, 768, 769, 772, 800, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x29 - 1400x1050@60Hz RB */ 405 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 406 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 408 /* 0x2a - 1400x1050@60Hz */ 409 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 410 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x2b - 1400x1050@75Hz */ 413 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 414 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x2c - 1400x1050@85Hz */ 417 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 418 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x2d - 1400x1050@120Hz RB */ 421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 422 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 424 /* 0x2e - 1440x900@60Hz RB */ 425 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 426 1520, 1600, 0, 900, 903, 909, 926, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 428 /* 0x2f - 1440x900@60Hz */ 429 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 430 1672, 1904, 0, 900, 903, 909, 934, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x30 - 1440x900@75Hz */ 433 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 434 1688, 1936, 0, 900, 903, 909, 942, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x31 - 1440x900@85Hz */ 437 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 438 1696, 1952, 0, 900, 903, 909, 948, 0, 439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 440 /* 0x32 - 1440x900@120Hz RB */ 441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 442 1520, 1600, 0, 900, 903, 909, 953, 0, 443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x53 - 1600x900@60Hz */ 445 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 446 1704, 1800, 0, 900, 901, 904, 1000, 0, 447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x33 - 1600x1200@60Hz */ 449 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 450 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x34 - 1600x1200@65Hz */ 453 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 454 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x35 - 1600x1200@70Hz */ 457 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 458 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 460 /* 0x36 - 1600x1200@75Hz */ 461 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 462 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 464 /* 0x37 - 1600x1200@85Hz */ 465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x38 - 1600x1200@120Hz RB */ 469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 470 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 472 /* 0x39 - 1680x1050@60Hz RB */ 473 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 474 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 476 /* 0x3a - 1680x1050@60Hz */ 477 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 478 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x3b - 1680x1050@75Hz */ 481 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 482 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x3c - 1680x1050@85Hz */ 485 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 486 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 488 /* 0x3d - 1680x1050@120Hz RB */ 489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 490 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 492 /* 0x3e - 1792x1344@60Hz */ 493 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 494 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x3f - 1792x1344@75Hz */ 497 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 498 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x40 - 1792x1344@120Hz RB */ 501 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 502 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 504 /* 0x41 - 1856x1392@60Hz */ 505 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 506 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 508 /* 0x42 - 1856x1392@75Hz */ 509 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 510 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 512 /* 0x43 - 1856x1392@120Hz RB */ 513 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 514 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 516 /* 0x52 - 1920x1080@60Hz */ 517 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 518 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 /* 0x44 - 1920x1200@60Hz RB */ 521 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 522 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 524 /* 0x45 - 1920x1200@60Hz */ 525 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 526 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 528 /* 0x46 - 1920x1200@75Hz */ 529 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 530 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 532 /* 0x47 - 1920x1200@85Hz */ 533 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 534 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 536 /* 0x48 - 1920x1200@120Hz RB */ 537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 538 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 540 /* 0x49 - 1920x1440@60Hz */ 541 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 542 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 544 /* 0x4a - 1920x1440@75Hz */ 545 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 546 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 548 /* 0x4b - 1920x1440@120Hz RB */ 549 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 550 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 552 /* 0x54 - 2048x1152@60Hz */ 553 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 554 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 556 /* 0x4c - 2560x1600@60Hz RB */ 557 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 558 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 560 /* 0x4d - 2560x1600@60Hz */ 561 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 562 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 564 /* 0x4e - 2560x1600@75Hz */ 565 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 566 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 568 /* 0x4f - 2560x1600@85Hz */ 569 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 570 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 571 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 572 /* 0x50 - 2560x1600@120Hz RB */ 573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 574 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 576 /* 0x57 - 4096x2160@60Hz RB */ 577 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 578 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 580 /* 0x58 - 4096x2160@59.94Hz RB */ 581 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 582 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 584 }; 585 586 /* 587 * These more or less come from the DMT spec. The 720x400 modes are 588 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 589 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 590 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 591 * mode. 592 * 593 * The DMT modes have been fact-checked; the rest are mild guesses. 594 */ 595 static const struct drm_display_mode edid_est_modes[] = { 596 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 597 968, 1056, 0, 600, 601, 605, 628, 0, 598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 599 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 600 896, 1024, 0, 600, 601, 603, 625, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 603 720, 840, 0, 480, 481, 484, 500, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 606 704, 832, 0, 480, 489, 492, 520, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 608 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 609 768, 864, 0, 480, 483, 486, 525, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 612 752, 800, 0, 480, 490, 492, 525, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 614 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 615 846, 900, 0, 400, 421, 423, 449, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 617 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 618 846, 900, 0, 400, 412, 414, 449, 0, 619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 620 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 621 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 624 1136, 1312, 0, 768, 769, 772, 800, 0, 625 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 626 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 627 1184, 1328, 0, 768, 771, 777, 806, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 629 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 630 1184, 1344, 0, 768, 771, 777, 806, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 632 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 633 1208, 1264, 0, 768, 768, 776, 817, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 635 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 636 928, 1152, 0, 624, 625, 628, 667, 0, 637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 638 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 639 896, 1056, 0, 600, 601, 604, 625, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 641 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 642 976, 1040, 0, 600, 637, 643, 666, 0, 643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 644 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 645 1344, 1600, 0, 864, 865, 868, 900, 0, 646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 647 }; 648 649 struct minimode { 650 short w; 651 short h; 652 short r; 653 short rb; 654 }; 655 656 static const struct minimode est3_modes[] = { 657 /* byte 6 */ 658 { 640, 350, 85, 0 }, 659 { 640, 400, 85, 0 }, 660 { 720, 400, 85, 0 }, 661 { 640, 480, 85, 0 }, 662 { 848, 480, 60, 0 }, 663 { 800, 600, 85, 0 }, 664 { 1024, 768, 85, 0 }, 665 { 1152, 864, 75, 0 }, 666 /* byte 7 */ 667 { 1280, 768, 60, 1 }, 668 { 1280, 768, 60, 0 }, 669 { 1280, 768, 75, 0 }, 670 { 1280, 768, 85, 0 }, 671 { 1280, 960, 60, 0 }, 672 { 1280, 960, 85, 0 }, 673 { 1280, 1024, 60, 0 }, 674 { 1280, 1024, 85, 0 }, 675 /* byte 8 */ 676 { 1360, 768, 60, 0 }, 677 { 1440, 900, 60, 1 }, 678 { 1440, 900, 60, 0 }, 679 { 1440, 900, 75, 0 }, 680 { 1440, 900, 85, 0 }, 681 { 1400, 1050, 60, 1 }, 682 { 1400, 1050, 60, 0 }, 683 { 1400, 1050, 75, 0 }, 684 /* byte 9 */ 685 { 1400, 1050, 85, 0 }, 686 { 1680, 1050, 60, 1 }, 687 { 1680, 1050, 60, 0 }, 688 { 1680, 1050, 75, 0 }, 689 { 1680, 1050, 85, 0 }, 690 { 1600, 1200, 60, 0 }, 691 { 1600, 1200, 65, 0 }, 692 { 1600, 1200, 70, 0 }, 693 /* byte 10 */ 694 { 1600, 1200, 75, 0 }, 695 { 1600, 1200, 85, 0 }, 696 { 1792, 1344, 60, 0 }, 697 { 1792, 1344, 75, 0 }, 698 { 1856, 1392, 60, 0 }, 699 { 1856, 1392, 75, 0 }, 700 { 1920, 1200, 60, 1 }, 701 { 1920, 1200, 60, 0 }, 702 /* byte 11 */ 703 { 1920, 1200, 75, 0 }, 704 { 1920, 1200, 85, 0 }, 705 { 1920, 1440, 60, 0 }, 706 { 1920, 1440, 75, 0 }, 707 }; 708 709 static const struct minimode extra_modes[] = { 710 { 1024, 576, 60, 0 }, 711 { 1366, 768, 60, 0 }, 712 { 1600, 900, 60, 0 }, 713 { 1680, 945, 60, 0 }, 714 { 1920, 1080, 60, 0 }, 715 { 2048, 1152, 60, 0 }, 716 { 2048, 1536, 60, 0 }, 717 }; 718 719 /* 720 * From CEA/CTA-861 spec. 721 * 722 * Do not access directly, instead always use cea_mode_for_vic(). 723 */ 724 static const struct drm_display_mode edid_cea_modes_1[] = { 725 /* 1 - 640x480@60Hz 4:3 */ 726 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 727 752, 800, 0, 480, 490, 492, 525, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 729 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 730 /* 2 - 720x480@60Hz 4:3 */ 731 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 732 798, 858, 0, 480, 489, 495, 525, 0, 733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 734 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 735 /* 3 - 720x480@60Hz 16:9 */ 736 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 737 798, 858, 0, 480, 489, 495, 525, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 740 /* 4 - 1280x720@60Hz 16:9 */ 741 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 742 1430, 1650, 0, 720, 725, 730, 750, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 5 - 1920x1080i@60Hz 16:9 */ 746 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 747 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 748 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 749 DRM_MODE_FLAG_INTERLACE), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 6 - 720(1440)x480i@60Hz 4:3 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 757 /* 7 - 720(1440)x480i@60Hz 16:9 */ 758 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 480, 488, 494, 525, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 763 /* 8 - 720(1440)x240@60Hz 4:3 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 769 /* 9 - 720(1440)x240@60Hz 16:9 */ 770 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 771 801, 858, 0, 240, 244, 247, 262, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_DBLCLK), 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 775 /* 10 - 2880x480i@60Hz 4:3 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 781 /* 11 - 2880x480i@60Hz 16:9 */ 782 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 480, 488, 494, 525, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 785 DRM_MODE_FLAG_INTERLACE), 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 787 /* 12 - 2880x240@60Hz 4:3 */ 788 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 789 3204, 3432, 0, 240, 244, 247, 262, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 792 /* 13 - 2880x240@60Hz 16:9 */ 793 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 794 3204, 3432, 0, 240, 244, 247, 262, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 14 - 1440x480@60Hz 4:3 */ 798 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 799 1596, 1716, 0, 480, 489, 495, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 15 - 1440x480@60Hz 16:9 */ 803 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 804 1596, 1716, 0, 480, 489, 495, 525, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 16 - 1920x1080@60Hz 16:9 */ 808 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 809 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 812 /* 17 - 720x576@50Hz 4:3 */ 813 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 814 796, 864, 0, 576, 581, 586, 625, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 817 /* 18 - 720x576@50Hz 16:9 */ 818 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 819 796, 864, 0, 576, 581, 586, 625, 0, 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 19 - 1280x720@50Hz 16:9 */ 823 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 824 1760, 1980, 0, 720, 725, 730, 750, 0, 825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 20 - 1920x1080i@50Hz 16:9 */ 828 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 829 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 831 DRM_MODE_FLAG_INTERLACE), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 21 - 720(1440)x576i@50Hz 4:3 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 839 /* 22 - 720(1440)x576i@50Hz 16:9 */ 840 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 576, 580, 586, 625, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 845 /* 23 - 720(1440)x288@50Hz 4:3 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 851 /* 24 - 720(1440)x288@50Hz 16:9 */ 852 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 853 795, 864, 0, 288, 290, 293, 312, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_DBLCLK), 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 857 /* 25 - 2880x576i@50Hz 4:3 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 863 /* 26 - 2880x576i@50Hz 16:9 */ 864 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 576, 580, 586, 625, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 867 DRM_MODE_FLAG_INTERLACE), 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 27 - 2880x288@50Hz 4:3 */ 870 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 871 3180, 3456, 0, 288, 290, 293, 312, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 874 /* 28 - 2880x288@50Hz 16:9 */ 875 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 876 3180, 3456, 0, 288, 290, 293, 312, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 29 - 1440x576@50Hz 4:3 */ 880 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 881 1592, 1728, 0, 576, 581, 586, 625, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 884 /* 30 - 1440x576@50Hz 16:9 */ 885 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 886 1592, 1728, 0, 576, 581, 586, 625, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 31 - 1920x1080@50Hz 16:9 */ 890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 891 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 32 - 1920x1080@24Hz 16:9 */ 895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 896 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 33 - 1920x1080@25Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 34 - 1920x1080@30Hz 16:9 */ 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 906 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 35 - 2880x480@60Hz 4:3 */ 910 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 911 3192, 3432, 0, 480, 489, 495, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 914 /* 36 - 2880x480@60Hz 16:9 */ 915 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 916 3192, 3432, 0, 480, 489, 495, 525, 0, 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 37 - 2880x576@50Hz 4:3 */ 920 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 921 3184, 3456, 0, 576, 581, 586, 625, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 38 - 2880x576@50Hz 16:9 */ 925 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 926 3184, 3456, 0, 576, 581, 586, 625, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 39 - 1920x1080i@50Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 931 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 40 - 1920x1080i@100Hz 16:9 */ 936 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 937 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 939 DRM_MODE_FLAG_INTERLACE), 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 41 - 1280x720@100Hz 16:9 */ 942 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 943 1760, 1980, 0, 720, 725, 730, 750, 0, 944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 946 /* 42 - 720x576@100Hz 4:3 */ 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 948 796, 864, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 951 /* 43 - 720x576@100Hz 16:9 */ 952 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 953 796, 864, 0, 576, 581, 586, 625, 0, 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 44 - 720(1440)x576i@100Hz 4:3 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 962 /* 45 - 720(1440)x576i@100Hz 16:9 */ 963 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 964 795, 864, 0, 576, 580, 586, 625, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 46 - 1920x1080i@120Hz 16:9 */ 969 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 970 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 972 DRM_MODE_FLAG_INTERLACE), 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 47 - 1280x720@120Hz 16:9 */ 975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 976 1430, 1650, 0, 720, 725, 730, 750, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 48 - 720x480@120Hz 4:3 */ 980 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 981 798, 858, 0, 480, 489, 495, 525, 0, 982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 984 /* 49 - 720x480@120Hz 16:9 */ 985 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 986 798, 858, 0, 480, 489, 495, 525, 0, 987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 50 - 720(1440)x480i@120Hz 4:3 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 995 /* 51 - 720(1440)x480i@120Hz 16:9 */ 996 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 997 801, 858, 0, 480, 488, 494, 525, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 999 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1001 /* 52 - 720x576@200Hz 4:3 */ 1002 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1003 796, 864, 0, 576, 581, 586, 625, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1005 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1006 /* 53 - 720x576@200Hz 16:9 */ 1007 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1008 796, 864, 0, 576, 581, 586, 625, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1017 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1018 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1019 795, 864, 0, 576, 580, 586, 625, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1021 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1023 /* 56 - 720x480@240Hz 4:3 */ 1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1025 798, 858, 0, 480, 489, 495, 525, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1028 /* 57 - 720x480@240Hz 16:9 */ 1029 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1030 798, 858, 0, 480, 489, 495, 525, 0, 1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1033 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1039 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1040 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1041 801, 858, 0, 480, 488, 494, 525, 0, 1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1043 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1045 /* 60 - 1280x720@24Hz 16:9 */ 1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1047 3080, 3300, 0, 720, 725, 730, 750, 0, 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1050 /* 61 - 1280x720@25Hz 16:9 */ 1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1052 3740, 3960, 0, 720, 725, 730, 750, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 62 - 1280x720@30Hz 16:9 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 63 - 1920x1080@120Hz 16:9 */ 1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1062 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 64 - 1920x1080@100Hz 16:9 */ 1066 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1067 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 65 - 1280x720@24Hz 64:27 */ 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1072 3080, 3300, 0, 720, 725, 730, 750, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1075 /* 66 - 1280x720@25Hz 64:27 */ 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1077 3740, 3960, 0, 720, 725, 730, 750, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1080 /* 67 - 1280x720@30Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 68 - 1280x720@50Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1087 1760, 1980, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 69 - 1280x720@60Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1092 1430, 1650, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 70 - 1280x720@100Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1097 1760, 1980, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 71 - 1280x720@120Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1102 1430, 1650, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 72 - 1920x1080@24Hz 64:27 */ 1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1107 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 73 - 1920x1080@25Hz 64:27 */ 1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1112 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 74 - 1920x1080@30Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1117 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 75 - 1920x1080@50Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 76 - 1920x1080@60Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 77 - 1920x1080@100Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 78 - 1920x1080@120Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 79 - 1680x720@24Hz 64:27 */ 1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1142 3080, 3300, 0, 720, 725, 730, 750, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 80 - 1680x720@25Hz 64:27 */ 1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1147 2948, 3168, 0, 720, 725, 730, 750, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 81 - 1680x720@30Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1152 2420, 2640, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 82 - 1680x720@50Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1157 1980, 2200, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 83 - 1680x720@60Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1162 1980, 2200, 0, 720, 725, 730, 750, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 84 - 1680x720@100Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1167 1780, 2000, 0, 720, 725, 730, 825, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 85 - 1680x720@120Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1172 1780, 2000, 0, 720, 725, 730, 825, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 86 - 2560x1080@24Hz 64:27 */ 1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1177 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 87 - 2560x1080@25Hz 64:27 */ 1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1182 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 88 - 2560x1080@30Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1187 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 89 - 2560x1080@50Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1192 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 90 - 2560x1080@60Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1197 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 91 - 2560x1080@100Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1202 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 92 - 2560x1080@120Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1207 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 93 - 3840x2160@24Hz 16:9 */ 1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1212 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1215 /* 94 - 3840x2160@25Hz 16:9 */ 1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1217 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1220 /* 95 - 3840x2160@30Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1222 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 96 - 3840x2160@50Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 97 - 3840x2160@60Hz 16:9 */ 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1235 /* 98 - 4096x2160@24Hz 256:135 */ 1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1240 /* 99 - 4096x2160@25Hz 256:135 */ 1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1242 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1245 /* 100 - 4096x2160@30Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1247 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 101 - 4096x2160@50Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 102 - 4096x2160@60Hz 256:135 */ 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1260 /* 103 - 3840x2160@24Hz 64:27 */ 1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1265 /* 104 - 3840x2160@25Hz 64:27 */ 1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1267 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1270 /* 105 - 3840x2160@30Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1272 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 106 - 3840x2160@50Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 107 - 3840x2160@60Hz 64:27 */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1285 /* 108 - 1280x720@48Hz 16:9 */ 1286 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1287 2280, 2500, 0, 720, 725, 730, 750, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1290 /* 109 - 1280x720@48Hz 64:27 */ 1291 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1292 2280, 2500, 0, 720, 725, 730, 750, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 110 - 1680x720@48Hz 64:27 */ 1296 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1297 2530, 2750, 0, 720, 725, 730, 750, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1300 /* 111 - 1920x1080@48Hz 16:9 */ 1301 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1302 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1305 /* 112 - 1920x1080@48Hz 64:27 */ 1306 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1307 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 113 - 2560x1080@48Hz 64:27 */ 1311 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1312 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1315 /* 114 - 3840x2160@48Hz 16:9 */ 1316 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1317 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1320 /* 115 - 4096x2160@48Hz 256:135 */ 1321 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1322 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1325 /* 116 - 3840x2160@48Hz 64:27 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1330 /* 117 - 3840x2160@100Hz 16:9 */ 1331 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1332 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1335 /* 118 - 3840x2160@120Hz 16:9 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1337 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1340 /* 119 - 3840x2160@100Hz 64:27 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1345 /* 120 - 3840x2160@120Hz 64:27 */ 1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1350 /* 121 - 5120x2160@24Hz 64:27 */ 1351 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1352 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 122 - 5120x2160@25Hz 64:27 */ 1356 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1357 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 123 - 5120x2160@30Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1362 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 124 - 5120x2160@48Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1367 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 125 - 5120x2160@50Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1372 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 126 - 5120x2160@60Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1377 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 /* 127 - 5120x2160@100Hz 64:27 */ 1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1385 }; 1386 1387 /* 1388 * From CEA/CTA-861 spec. 1389 * 1390 * Do not access directly, instead always use cea_mode_for_vic(). 1391 */ 1392 static const struct drm_display_mode edid_cea_modes_193[] = { 1393 /* 193 - 5120x2160@120Hz 64:27 */ 1394 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1395 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1398 /* 194 - 7680x4320@24Hz 16:9 */ 1399 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1400 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1402 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1403 /* 195 - 7680x4320@25Hz 16:9 */ 1404 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1405 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1408 /* 196 - 7680x4320@30Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1410 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 197 - 7680x4320@48Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1415 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 198 - 7680x4320@50Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1420 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 199 - 7680x4320@60Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1425 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 200 - 7680x4320@100Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1430 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 201 - 7680x4320@120Hz 16:9 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1435 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1438 /* 202 - 7680x4320@24Hz 64:27 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1443 /* 203 - 7680x4320@25Hz 64:27 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1448 /* 204 - 7680x4320@30Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 205 - 7680x4320@48Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1455 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 206 - 7680x4320@50Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1460 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 207 - 7680x4320@60Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1465 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 208 - 7680x4320@100Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1470 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 209 - 7680x4320@120Hz 64:27 */ 1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1475 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 210 - 10240x4320@24Hz 64:27 */ 1479 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1480 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 211 - 10240x4320@25Hz 64:27 */ 1484 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1485 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 212 - 10240x4320@30Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1490 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 213 - 10240x4320@48Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1495 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 214 - 10240x4320@50Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1500 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 215 - 10240x4320@60Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1505 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 216 - 10240x4320@100Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1510 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 217 - 10240x4320@120Hz 64:27 */ 1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1518 /* 218 - 4096x2160@100Hz 256:135 */ 1519 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1520 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1523 /* 219 - 4096x2160@120Hz 256:135 */ 1524 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1525 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1528 }; 1529 1530 /* 1531 * HDMI 1.4 4k modes. Index using the VIC. 1532 */ 1533 static const struct drm_display_mode edid_4k_modes[] = { 1534 /* 0 - dummy, VICs start at 1 */ 1535 { }, 1536 /* 1 - 3840x2160@30Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4016, 4104, 4400, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 2 - 3840x2160@25Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 4896, 4984, 5280, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 3 - 3840x2160@24Hz */ 1549 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 3840, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1554 /* 4 - 4096x2160@24Hz (SMPTE) */ 1555 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1556 4096, 5116, 5204, 5500, 0, 1557 2160, 2168, 2178, 2250, 0, 1558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1559 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1560 }; 1561 1562 /*** DDC fetch and block validation ***/ 1563 1564 static const u8 edid_header[] = { 1565 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1566 }; 1567 1568 /** 1569 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1570 * @raw_edid: pointer to raw base EDID block 1571 * 1572 * Sanity check the header of the base EDID block. 1573 * 1574 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1575 */ 1576 int drm_edid_header_is_valid(const u8 *raw_edid) 1577 { 1578 int i, score = 0; 1579 1580 for (i = 0; i < sizeof(edid_header); i++) 1581 if (raw_edid[i] == edid_header[i]) 1582 score++; 1583 1584 return score; 1585 } 1586 EXPORT_SYMBOL(drm_edid_header_is_valid); 1587 1588 static int edid_fixup __read_mostly = 6; 1589 module_param_named(edid_fixup, edid_fixup, int, 0400); 1590 MODULE_PARM_DESC(edid_fixup, 1591 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1592 1593 static int drm_edid_block_checksum(const u8 *raw_edid) 1594 { 1595 int i; 1596 u8 csum = 0, crc = 0; 1597 1598 for (i = 0; i < EDID_LENGTH - 1; i++) 1599 csum += raw_edid[i]; 1600 1601 crc = 0x100 - csum; 1602 1603 return crc; 1604 } 1605 1606 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1607 { 1608 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1609 return true; 1610 else 1611 return false; 1612 } 1613 1614 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1615 { 1616 if (memchr_inv(in_edid, 0, length)) 1617 return false; 1618 1619 return true; 1620 } 1621 1622 /** 1623 * drm_edid_are_equal - compare two edid blobs. 1624 * @edid1: pointer to first blob 1625 * @edid2: pointer to second blob 1626 * This helper can be used during probing to determine if 1627 * edid had changed. 1628 */ 1629 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1630 { 1631 int edid1_len, edid2_len; 1632 bool edid1_present = edid1 != NULL; 1633 bool edid2_present = edid2 != NULL; 1634 1635 if (edid1_present != edid2_present) 1636 return false; 1637 1638 if (edid1) { 1639 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1640 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1641 1642 if (edid1_len != edid2_len) 1643 return false; 1644 1645 if (memcmp(edid1, edid2, edid1_len)) 1646 return false; 1647 } 1648 1649 return true; 1650 } 1651 EXPORT_SYMBOL(drm_edid_are_equal); 1652 1653 /** 1654 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1655 * @raw_edid: pointer to raw EDID block 1656 * @block: type of block to validate (0 for base, extension otherwise) 1657 * @print_bad_edid: if true, dump bad EDID blocks to the console 1658 * @edid_corrupt: if true, the header or checksum is invalid 1659 * 1660 * Validate a base or extension EDID block and optionally dump bad blocks to 1661 * the console. 1662 * 1663 * Return: True if the block is valid, false otherwise. 1664 */ 1665 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1666 bool *edid_corrupt) 1667 { 1668 u8 csum; 1669 struct edid *edid = (struct edid *)raw_edid; 1670 1671 if (WARN_ON(!raw_edid)) 1672 return false; 1673 1674 if (edid_fixup > 8 || edid_fixup < 0) 1675 edid_fixup = 6; 1676 1677 if (block == 0) { 1678 int score = drm_edid_header_is_valid(raw_edid); 1679 1680 if (score == 8) { 1681 if (edid_corrupt) 1682 *edid_corrupt = false; 1683 } else if (score >= edid_fixup) { 1684 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1685 * The corrupt flag needs to be set here otherwise, the 1686 * fix-up code here will correct the problem, the 1687 * checksum is correct and the test fails 1688 */ 1689 if (edid_corrupt) 1690 *edid_corrupt = true; 1691 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1692 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1693 } else { 1694 if (edid_corrupt) 1695 *edid_corrupt = true; 1696 goto bad; 1697 } 1698 } 1699 1700 csum = drm_edid_block_checksum(raw_edid); 1701 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1702 if (edid_corrupt) 1703 *edid_corrupt = true; 1704 1705 /* allow CEA to slide through, switches mangle this */ 1706 if (raw_edid[0] == CEA_EXT) { 1707 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1708 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1709 } else { 1710 if (print_bad_edid) 1711 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1712 1713 goto bad; 1714 } 1715 } 1716 1717 /* per-block-type checks */ 1718 switch (raw_edid[0]) { 1719 case 0: /* base */ 1720 if (edid->version != 1) { 1721 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1722 goto bad; 1723 } 1724 1725 if (edid->revision > 4) 1726 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1727 break; 1728 1729 default: 1730 break; 1731 } 1732 1733 return true; 1734 1735 bad: 1736 if (print_bad_edid) { 1737 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1738 pr_notice("EDID block is all zeroes\n"); 1739 } else { 1740 pr_notice("Raw EDID:\n"); 1741 print_hex_dump(KERN_NOTICE, 1742 " \t", DUMP_PREFIX_NONE, 16, 1, 1743 raw_edid, EDID_LENGTH, false); 1744 } 1745 } 1746 return false; 1747 } 1748 EXPORT_SYMBOL(drm_edid_block_valid); 1749 1750 /** 1751 * drm_edid_is_valid - sanity check EDID data 1752 * @edid: EDID data 1753 * 1754 * Sanity-check an entire EDID record (including extensions) 1755 * 1756 * Return: True if the EDID data is valid, false otherwise. 1757 */ 1758 bool drm_edid_is_valid(struct edid *edid) 1759 { 1760 int i; 1761 u8 *raw = (u8 *)edid; 1762 1763 if (!edid) 1764 return false; 1765 1766 for (i = 0; i <= edid->extensions; i++) 1767 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1768 return false; 1769 1770 return true; 1771 } 1772 EXPORT_SYMBOL(drm_edid_is_valid); 1773 1774 #define DDC_SEGMENT_ADDR 0x30 1775 /** 1776 * drm_do_probe_ddc_edid() - get EDID information via I2C 1777 * @data: I2C device adapter 1778 * @buf: EDID data buffer to be filled 1779 * @block: 128 byte EDID block to start fetching from 1780 * @len: EDID data buffer length to fetch 1781 * 1782 * Try to fetch EDID information by calling I2C driver functions. 1783 * 1784 * Return: 0 on success or -1 on failure. 1785 */ 1786 static int 1787 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1788 { 1789 struct i2c_adapter *adapter = data; 1790 unsigned char start = block * EDID_LENGTH; 1791 unsigned char segment = block >> 1; 1792 unsigned char xfers = segment ? 3 : 2; 1793 int ret, retries = 5; 1794 1795 /* 1796 * The core I2C driver will automatically retry the transfer if the 1797 * adapter reports EAGAIN. However, we find that bit-banging transfers 1798 * are susceptible to errors under a heavily loaded machine and 1799 * generate spurious NAKs and timeouts. Retrying the transfer 1800 * of the individual block a few times seems to overcome this. 1801 */ 1802 do { 1803 struct i2c_msg msgs[] = { 1804 { 1805 .addr = DDC_SEGMENT_ADDR, 1806 .flags = 0, 1807 .len = 1, 1808 .buf = &segment, 1809 }, { 1810 .addr = DDC_ADDR, 1811 .flags = 0, 1812 .len = 1, 1813 .buf = &start, 1814 }, { 1815 .addr = DDC_ADDR, 1816 .flags = I2C_M_RD, 1817 .len = len, 1818 .buf = buf, 1819 } 1820 }; 1821 1822 /* 1823 * Avoid sending the segment addr to not upset non-compliant 1824 * DDC monitors. 1825 */ 1826 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1827 1828 if (ret == -ENXIO) { 1829 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1830 adapter->name); 1831 break; 1832 } 1833 } while (ret != xfers && --retries); 1834 1835 return ret == xfers ? 0 : -1; 1836 } 1837 1838 static void connector_bad_edid(struct drm_connector *connector, 1839 u8 *edid, int num_blocks) 1840 { 1841 int i; 1842 u8 num_of_ext = edid[0x7e]; 1843 1844 /* Calculate real checksum for the last edid extension block data */ 1845 connector->real_edid_checksum = 1846 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1847 1848 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1849 return; 1850 1851 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 1852 for (i = 0; i < num_blocks; i++) { 1853 u8 *block = edid + i * EDID_LENGTH; 1854 char prefix[20]; 1855 1856 if (drm_edid_is_zero(block, EDID_LENGTH)) 1857 sprintf(prefix, "\t[%02x] ZERO ", i); 1858 else if (!drm_edid_block_valid(block, i, false, NULL)) 1859 sprintf(prefix, "\t[%02x] BAD ", i); 1860 else 1861 sprintf(prefix, "\t[%02x] GOOD ", i); 1862 1863 print_hex_dump(KERN_DEBUG, 1864 prefix, DUMP_PREFIX_NONE, 16, 1, 1865 block, EDID_LENGTH, false); 1866 } 1867 } 1868 1869 /* Get override or firmware EDID */ 1870 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1871 { 1872 struct edid *override = NULL; 1873 1874 if (connector->override_edid) 1875 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1876 1877 if (!override) 1878 override = drm_load_edid_firmware(connector); 1879 1880 return IS_ERR(override) ? NULL : override; 1881 } 1882 1883 /** 1884 * drm_add_override_edid_modes - add modes from override/firmware EDID 1885 * @connector: connector we're probing 1886 * 1887 * Add modes from the override/firmware EDID, if available. Only to be used from 1888 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1889 * failed during drm_get_edid() and caused the override/firmware EDID to be 1890 * skipped. 1891 * 1892 * Return: The number of modes added or 0 if we couldn't find any. 1893 */ 1894 int drm_add_override_edid_modes(struct drm_connector *connector) 1895 { 1896 struct edid *override; 1897 int num_modes = 0; 1898 1899 override = drm_get_override_edid(connector); 1900 if (override) { 1901 drm_connector_update_edid_property(connector, override); 1902 num_modes = drm_add_edid_modes(connector, override); 1903 kfree(override); 1904 1905 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1906 connector->base.id, connector->name, num_modes); 1907 } 1908 1909 return num_modes; 1910 } 1911 EXPORT_SYMBOL(drm_add_override_edid_modes); 1912 1913 static struct edid *drm_do_get_edid_base_block( 1914 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1915 size_t len), 1916 void *data, bool *edid_corrupt, int *null_edid_counter) 1917 { 1918 int i; 1919 void *edid; 1920 1921 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 1922 if (edid == NULL) 1923 return NULL; 1924 1925 /* base block fetch */ 1926 for (i = 0; i < 4; i++) { 1927 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1928 goto out; 1929 if (drm_edid_block_valid(edid, 0, false, edid_corrupt)) 1930 break; 1931 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1932 if (null_edid_counter) 1933 (*null_edid_counter)++; 1934 goto carp; 1935 } 1936 } 1937 if (i == 4) 1938 goto carp; 1939 1940 return edid; 1941 1942 carp: 1943 kfree(edid); 1944 return ERR_PTR(-EINVAL); 1945 1946 out: 1947 kfree(edid); 1948 return NULL; 1949 } 1950 1951 /** 1952 * drm_do_get_edid - get EDID data using a custom EDID block read function 1953 * @connector: connector we're probing 1954 * @get_edid_block: EDID block read function 1955 * @data: private data passed to the block read function 1956 * 1957 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1958 * exposes a different interface to read EDID blocks this function can be used 1959 * to get EDID data using a custom block read function. 1960 * 1961 * As in the general case the DDC bus is accessible by the kernel at the I2C 1962 * level, drivers must make all reasonable efforts to expose it as an I2C 1963 * adapter and use drm_get_edid() instead of abusing this function. 1964 * 1965 * The EDID may be overridden using debugfs override_edid or firmware EDID 1966 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1967 * order. Having either of them bypasses actual EDID reads. 1968 * 1969 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1970 */ 1971 struct edid *drm_do_get_edid(struct drm_connector *connector, 1972 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1973 size_t len), 1974 void *data) 1975 { 1976 int i, j = 0, valid_extensions = 0; 1977 u8 *edid, *new; 1978 struct edid *override; 1979 1980 override = drm_get_override_edid(connector); 1981 if (override) 1982 return override; 1983 1984 edid = (u8 *)drm_do_get_edid_base_block(get_edid_block, data, 1985 &connector->edid_corrupt, 1986 &connector->null_edid_counter); 1987 if (IS_ERR_OR_NULL(edid)) { 1988 if (IS_ERR(edid)) 1989 connector_bad_edid(connector, edid, 1); 1990 return NULL; 1991 } 1992 1993 /* if there's no extensions or no connector, we're done */ 1994 valid_extensions = edid[0x7e]; 1995 if (valid_extensions == 0) 1996 return (struct edid *)edid; 1997 1998 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1999 if (!new) 2000 goto out; 2001 edid = new; 2002 2003 for (j = 1; j <= edid[0x7e]; j++) { 2004 u8 *block = edid + j * EDID_LENGTH; 2005 2006 for (i = 0; i < 4; i++) { 2007 if (get_edid_block(data, block, j, EDID_LENGTH)) 2008 goto out; 2009 if (drm_edid_block_valid(block, j, false, NULL)) 2010 break; 2011 } 2012 2013 if (i == 4) 2014 valid_extensions--; 2015 } 2016 2017 if (valid_extensions != edid[0x7e]) { 2018 u8 *base; 2019 2020 connector_bad_edid(connector, edid, edid[0x7e] + 1); 2021 2022 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 2023 edid[0x7e] = valid_extensions; 2024 2025 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 2026 GFP_KERNEL); 2027 if (!new) 2028 goto out; 2029 2030 base = new; 2031 for (i = 0; i <= edid[0x7e]; i++) { 2032 u8 *block = edid + i * EDID_LENGTH; 2033 2034 if (!drm_edid_block_valid(block, i, false, NULL)) 2035 continue; 2036 2037 memcpy(base, block, EDID_LENGTH); 2038 base += EDID_LENGTH; 2039 } 2040 2041 kfree(edid); 2042 edid = new; 2043 } 2044 2045 return (struct edid *)edid; 2046 2047 out: 2048 kfree(edid); 2049 return NULL; 2050 } 2051 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2052 2053 /** 2054 * drm_probe_ddc() - probe DDC presence 2055 * @adapter: I2C adapter to probe 2056 * 2057 * Return: True on success, false on failure. 2058 */ 2059 bool 2060 drm_probe_ddc(struct i2c_adapter *adapter) 2061 { 2062 unsigned char out; 2063 2064 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2065 } 2066 EXPORT_SYMBOL(drm_probe_ddc); 2067 2068 /** 2069 * drm_get_edid - get EDID data, if available 2070 * @connector: connector we're probing 2071 * @adapter: I2C adapter to use for DDC 2072 * 2073 * Poke the given I2C channel to grab EDID data if possible. If found, 2074 * attach it to the connector. 2075 * 2076 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2077 */ 2078 struct edid *drm_get_edid(struct drm_connector *connector, 2079 struct i2c_adapter *adapter) 2080 { 2081 struct edid *edid; 2082 2083 if (connector->force == DRM_FORCE_OFF) 2084 return NULL; 2085 2086 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2087 return NULL; 2088 2089 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2090 drm_connector_update_edid_property(connector, edid); 2091 return edid; 2092 } 2093 EXPORT_SYMBOL(drm_get_edid); 2094 2095 static u32 edid_extract_panel_id(const struct edid *edid) 2096 { 2097 /* 2098 * We represent the ID as a 32-bit number so it can easily be compared 2099 * with "==". 2100 * 2101 * NOTE that we deal with endianness differently for the top half 2102 * of this ID than for the bottom half. The bottom half (the product 2103 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2104 * that's how everyone seems to interpret it. The top half (the mfg_id) 2105 * gets stored as big endian because that makes 2106 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2107 * to write (it's easier to extract the ASCII). It doesn't really 2108 * matter, though, as long as the number here is unique. 2109 */ 2110 return (u32)edid->mfg_id[0] << 24 | 2111 (u32)edid->mfg_id[1] << 16 | 2112 (u32)EDID_PRODUCT_ID(edid); 2113 } 2114 2115 /** 2116 * drm_edid_get_panel_id - Get a panel's ID through DDC 2117 * @adapter: I2C adapter to use for DDC 2118 * 2119 * This function reads the first block of the EDID of a panel and (assuming 2120 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2121 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2122 * supposed to be different for each different modem of panel. 2123 * 2124 * This function is intended to be used during early probing on devices where 2125 * more than one panel might be present. Because of its intended use it must 2126 * assume that the EDID of the panel is correct, at least as far as the ID 2127 * is concerned (in other words, we don't process any overrides here). 2128 * 2129 * NOTE: it's expected that this function and drm_do_get_edid() will both 2130 * be read the EDID, but there is no caching between them. Since we're only 2131 * reading the first block, hopefully this extra overhead won't be too big. 2132 * 2133 * Return: A 32-bit ID that should be different for each make/model of panel. 2134 * See the functions drm_edid_encode_panel_id() and 2135 * drm_edid_decode_panel_id() for some details on the structure of this 2136 * ID. 2137 */ 2138 2139 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2140 { 2141 struct edid *edid; 2142 u32 panel_id; 2143 2144 edid = drm_do_get_edid_base_block(drm_do_probe_ddc_edid, adapter, 2145 NULL, NULL); 2146 2147 /* 2148 * There are no manufacturer IDs of 0, so if there is a problem reading 2149 * the EDID then we'll just return 0. 2150 */ 2151 if (IS_ERR_OR_NULL(edid)) 2152 return 0; 2153 2154 panel_id = edid_extract_panel_id(edid); 2155 kfree(edid); 2156 2157 return panel_id; 2158 } 2159 EXPORT_SYMBOL(drm_edid_get_panel_id); 2160 2161 /** 2162 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2163 * @connector: connector we're probing 2164 * @adapter: I2C adapter to use for DDC 2165 * 2166 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2167 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2168 * switch DDC to the GPU which is retrieving EDID. 2169 * 2170 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2171 */ 2172 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2173 struct i2c_adapter *adapter) 2174 { 2175 struct drm_device *dev = connector->dev; 2176 struct pci_dev *pdev = to_pci_dev(dev->dev); 2177 struct edid *edid; 2178 2179 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2180 return NULL; 2181 2182 vga_switcheroo_lock_ddc(pdev); 2183 edid = drm_get_edid(connector, adapter); 2184 vga_switcheroo_unlock_ddc(pdev); 2185 2186 return edid; 2187 } 2188 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2189 2190 /** 2191 * drm_edid_duplicate - duplicate an EDID and the extensions 2192 * @edid: EDID to duplicate 2193 * 2194 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2195 */ 2196 struct edid *drm_edid_duplicate(const struct edid *edid) 2197 { 2198 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2199 } 2200 EXPORT_SYMBOL(drm_edid_duplicate); 2201 2202 /*** EDID parsing ***/ 2203 2204 /** 2205 * edid_get_quirks - return quirk flags for a given EDID 2206 * @edid: EDID to process 2207 * 2208 * This tells subsequent routines what fixes they need to apply. 2209 */ 2210 static u32 edid_get_quirks(const struct edid *edid) 2211 { 2212 u32 panel_id = edid_extract_panel_id(edid); 2213 const struct edid_quirk *quirk; 2214 int i; 2215 2216 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2217 quirk = &edid_quirk_list[i]; 2218 if (quirk->panel_id == panel_id) 2219 return quirk->quirks; 2220 } 2221 2222 return 0; 2223 } 2224 2225 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2226 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2227 2228 /** 2229 * edid_fixup_preferred - set preferred modes based on quirk list 2230 * @connector: has mode list to fix up 2231 * @quirks: quirks list 2232 * 2233 * Walk the mode list for @connector, clearing the preferred status 2234 * on existing modes and setting it anew for the right mode ala @quirks. 2235 */ 2236 static void edid_fixup_preferred(struct drm_connector *connector, 2237 u32 quirks) 2238 { 2239 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2240 int target_refresh = 0; 2241 int cur_vrefresh, preferred_vrefresh; 2242 2243 if (list_empty(&connector->probed_modes)) 2244 return; 2245 2246 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2247 target_refresh = 60; 2248 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2249 target_refresh = 75; 2250 2251 preferred_mode = list_first_entry(&connector->probed_modes, 2252 struct drm_display_mode, head); 2253 2254 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2255 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2256 2257 if (cur_mode == preferred_mode) 2258 continue; 2259 2260 /* Largest mode is preferred */ 2261 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2262 preferred_mode = cur_mode; 2263 2264 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2265 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2266 /* At a given size, try to get closest to target refresh */ 2267 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2268 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2269 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2270 preferred_mode = cur_mode; 2271 } 2272 } 2273 2274 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2275 } 2276 2277 static bool 2278 mode_is_rb(const struct drm_display_mode *mode) 2279 { 2280 return (mode->htotal - mode->hdisplay == 160) && 2281 (mode->hsync_end - mode->hdisplay == 80) && 2282 (mode->hsync_end - mode->hsync_start == 32) && 2283 (mode->vsync_start - mode->vdisplay == 3); 2284 } 2285 2286 /* 2287 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2288 * @dev: Device to duplicate against 2289 * @hsize: Mode width 2290 * @vsize: Mode height 2291 * @fresh: Mode refresh rate 2292 * @rb: Mode reduced-blanking-ness 2293 * 2294 * Walk the DMT mode list looking for a match for the given parameters. 2295 * 2296 * Return: A newly allocated copy of the mode, or NULL if not found. 2297 */ 2298 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2299 int hsize, int vsize, int fresh, 2300 bool rb) 2301 { 2302 int i; 2303 2304 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2305 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2306 2307 if (hsize != ptr->hdisplay) 2308 continue; 2309 if (vsize != ptr->vdisplay) 2310 continue; 2311 if (fresh != drm_mode_vrefresh(ptr)) 2312 continue; 2313 if (rb != mode_is_rb(ptr)) 2314 continue; 2315 2316 return drm_mode_duplicate(dev, ptr); 2317 } 2318 2319 return NULL; 2320 } 2321 EXPORT_SYMBOL(drm_mode_find_dmt); 2322 2323 static bool is_display_descriptor(const u8 d[18], u8 tag) 2324 { 2325 return d[0] == 0x00 && d[1] == 0x00 && 2326 d[2] == 0x00 && d[3] == tag; 2327 } 2328 2329 static bool is_detailed_timing_descriptor(const u8 d[18]) 2330 { 2331 return d[0] != 0x00 || d[1] != 0x00; 2332 } 2333 2334 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2335 2336 static void 2337 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2338 { 2339 int i, n; 2340 u8 d = ext[0x02]; 2341 u8 *det_base = ext + d; 2342 2343 if (d < 4 || d > 127) 2344 return; 2345 2346 n = (127 - d) / 18; 2347 for (i = 0; i < n; i++) 2348 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2349 } 2350 2351 static void 2352 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2353 { 2354 unsigned int i, n = min((int)ext[0x02], 6); 2355 u8 *det_base = ext + 5; 2356 2357 if (ext[0x01] != 1) 2358 return; /* unknown version */ 2359 2360 for (i = 0; i < n; i++) 2361 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2362 } 2363 2364 static void 2365 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2366 { 2367 int i; 2368 struct edid *edid = (struct edid *)raw_edid; 2369 2370 if (edid == NULL) 2371 return; 2372 2373 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2374 cb(&(edid->detailed_timings[i]), closure); 2375 2376 for (i = 1; i <= raw_edid[0x7e]; i++) { 2377 u8 *ext = raw_edid + (i * EDID_LENGTH); 2378 2379 switch (*ext) { 2380 case CEA_EXT: 2381 cea_for_each_detailed_block(ext, cb, closure); 2382 break; 2383 case VTB_EXT: 2384 vtb_for_each_detailed_block(ext, cb, closure); 2385 break; 2386 default: 2387 break; 2388 } 2389 } 2390 } 2391 2392 static void 2393 is_rb(struct detailed_timing *t, void *data) 2394 { 2395 u8 *r = (u8 *)t; 2396 2397 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2398 return; 2399 2400 if (r[15] & 0x10) 2401 *(bool *)data = true; 2402 } 2403 2404 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2405 static bool 2406 drm_monitor_supports_rb(struct edid *edid) 2407 { 2408 if (edid->revision >= 4) { 2409 bool ret = false; 2410 2411 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2412 return ret; 2413 } 2414 2415 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2416 } 2417 2418 static void 2419 find_gtf2(struct detailed_timing *t, void *data) 2420 { 2421 u8 *r = (u8 *)t; 2422 2423 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2424 return; 2425 2426 if (r[10] == 0x02) 2427 *(u8 **)data = r; 2428 } 2429 2430 /* Secondary GTF curve kicks in above some break frequency */ 2431 static int 2432 drm_gtf2_hbreak(struct edid *edid) 2433 { 2434 u8 *r = NULL; 2435 2436 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2437 return r ? (r[12] * 2) : 0; 2438 } 2439 2440 static int 2441 drm_gtf2_2c(struct edid *edid) 2442 { 2443 u8 *r = NULL; 2444 2445 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2446 return r ? r[13] : 0; 2447 } 2448 2449 static int 2450 drm_gtf2_m(struct edid *edid) 2451 { 2452 u8 *r = NULL; 2453 2454 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2455 return r ? (r[15] << 8) + r[14] : 0; 2456 } 2457 2458 static int 2459 drm_gtf2_k(struct edid *edid) 2460 { 2461 u8 *r = NULL; 2462 2463 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2464 return r ? r[16] : 0; 2465 } 2466 2467 static int 2468 drm_gtf2_2j(struct edid *edid) 2469 { 2470 u8 *r = NULL; 2471 2472 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2473 return r ? r[17] : 0; 2474 } 2475 2476 /** 2477 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2478 * @edid: EDID block to scan 2479 */ 2480 static int standard_timing_level(struct edid *edid) 2481 { 2482 if (edid->revision >= 2) { 2483 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2484 return LEVEL_CVT; 2485 if (drm_gtf2_hbreak(edid)) 2486 return LEVEL_GTF2; 2487 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2488 return LEVEL_GTF; 2489 } 2490 return LEVEL_DMT; 2491 } 2492 2493 /* 2494 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2495 * monitors fill with ascii space (0x20) instead. 2496 */ 2497 static int 2498 bad_std_timing(u8 a, u8 b) 2499 { 2500 return (a == 0x00 && b == 0x00) || 2501 (a == 0x01 && b == 0x01) || 2502 (a == 0x20 && b == 0x20); 2503 } 2504 2505 static int drm_mode_hsync(const struct drm_display_mode *mode) 2506 { 2507 if (mode->htotal <= 0) 2508 return 0; 2509 2510 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2511 } 2512 2513 /** 2514 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2515 * @connector: connector of for the EDID block 2516 * @edid: EDID block to scan 2517 * @t: standard timing params 2518 * 2519 * Take the standard timing params (in this case width, aspect, and refresh) 2520 * and convert them into a real mode using CVT/GTF/DMT. 2521 */ 2522 static struct drm_display_mode * 2523 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2524 struct std_timing *t) 2525 { 2526 struct drm_device *dev = connector->dev; 2527 struct drm_display_mode *m, *mode = NULL; 2528 int hsize, vsize; 2529 int vrefresh_rate; 2530 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2531 >> EDID_TIMING_ASPECT_SHIFT; 2532 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2533 >> EDID_TIMING_VFREQ_SHIFT; 2534 int timing_level = standard_timing_level(edid); 2535 2536 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2537 return NULL; 2538 2539 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2540 hsize = t->hsize * 8 + 248; 2541 /* vrefresh_rate = vfreq + 60 */ 2542 vrefresh_rate = vfreq + 60; 2543 /* the vdisplay is calculated based on the aspect ratio */ 2544 if (aspect_ratio == 0) { 2545 if (edid->revision < 3) 2546 vsize = hsize; 2547 else 2548 vsize = (hsize * 10) / 16; 2549 } else if (aspect_ratio == 1) 2550 vsize = (hsize * 3) / 4; 2551 else if (aspect_ratio == 2) 2552 vsize = (hsize * 4) / 5; 2553 else 2554 vsize = (hsize * 9) / 16; 2555 2556 /* HDTV hack, part 1 */ 2557 if (vrefresh_rate == 60 && 2558 ((hsize == 1360 && vsize == 765) || 2559 (hsize == 1368 && vsize == 769))) { 2560 hsize = 1366; 2561 vsize = 768; 2562 } 2563 2564 /* 2565 * If this connector already has a mode for this size and refresh 2566 * rate (because it came from detailed or CVT info), use that 2567 * instead. This way we don't have to guess at interlace or 2568 * reduced blanking. 2569 */ 2570 list_for_each_entry(m, &connector->probed_modes, head) 2571 if (m->hdisplay == hsize && m->vdisplay == vsize && 2572 drm_mode_vrefresh(m) == vrefresh_rate) 2573 return NULL; 2574 2575 /* HDTV hack, part 2 */ 2576 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2577 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2578 false); 2579 if (!mode) 2580 return NULL; 2581 mode->hdisplay = 1366; 2582 mode->hsync_start = mode->hsync_start - 1; 2583 mode->hsync_end = mode->hsync_end - 1; 2584 return mode; 2585 } 2586 2587 /* check whether it can be found in default mode table */ 2588 if (drm_monitor_supports_rb(edid)) { 2589 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2590 true); 2591 if (mode) 2592 return mode; 2593 } 2594 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2595 if (mode) 2596 return mode; 2597 2598 /* okay, generate it */ 2599 switch (timing_level) { 2600 case LEVEL_DMT: 2601 break; 2602 case LEVEL_GTF: 2603 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2604 break; 2605 case LEVEL_GTF2: 2606 /* 2607 * This is potentially wrong if there's ever a monitor with 2608 * more than one ranges section, each claiming a different 2609 * secondary GTF curve. Please don't do that. 2610 */ 2611 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2612 if (!mode) 2613 return NULL; 2614 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2615 drm_mode_destroy(dev, mode); 2616 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2617 vrefresh_rate, 0, 0, 2618 drm_gtf2_m(edid), 2619 drm_gtf2_2c(edid), 2620 drm_gtf2_k(edid), 2621 drm_gtf2_2j(edid)); 2622 } 2623 break; 2624 case LEVEL_CVT: 2625 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2626 false); 2627 break; 2628 } 2629 return mode; 2630 } 2631 2632 /* 2633 * EDID is delightfully ambiguous about how interlaced modes are to be 2634 * encoded. Our internal representation is of frame height, but some 2635 * HDTV detailed timings are encoded as field height. 2636 * 2637 * The format list here is from CEA, in frame size. Technically we 2638 * should be checking refresh rate too. Whatever. 2639 */ 2640 static void 2641 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2642 struct detailed_pixel_timing *pt) 2643 { 2644 int i; 2645 static const struct { 2646 int w, h; 2647 } cea_interlaced[] = { 2648 { 1920, 1080 }, 2649 { 720, 480 }, 2650 { 1440, 480 }, 2651 { 2880, 480 }, 2652 { 720, 576 }, 2653 { 1440, 576 }, 2654 { 2880, 576 }, 2655 }; 2656 2657 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2658 return; 2659 2660 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2661 if ((mode->hdisplay == cea_interlaced[i].w) && 2662 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2663 mode->vdisplay *= 2; 2664 mode->vsync_start *= 2; 2665 mode->vsync_end *= 2; 2666 mode->vtotal *= 2; 2667 mode->vtotal |= 1; 2668 } 2669 } 2670 2671 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2672 } 2673 2674 /** 2675 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2676 * @dev: DRM device (needed to create new mode) 2677 * @edid: EDID block 2678 * @timing: EDID detailed timing info 2679 * @quirks: quirks to apply 2680 * 2681 * An EDID detailed timing block contains enough info for us to create and 2682 * return a new struct drm_display_mode. 2683 */ 2684 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2685 struct edid *edid, 2686 struct detailed_timing *timing, 2687 u32 quirks) 2688 { 2689 struct drm_display_mode *mode; 2690 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2691 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2692 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2693 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2694 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2695 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2696 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2697 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2698 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2699 2700 /* ignore tiny modes */ 2701 if (hactive < 64 || vactive < 64) 2702 return NULL; 2703 2704 if (pt->misc & DRM_EDID_PT_STEREO) { 2705 DRM_DEBUG_KMS("stereo mode not supported\n"); 2706 return NULL; 2707 } 2708 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2709 DRM_DEBUG_KMS("composite sync not supported\n"); 2710 } 2711 2712 /* it is incorrect if hsync/vsync width is zero */ 2713 if (!hsync_pulse_width || !vsync_pulse_width) { 2714 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2715 "Wrong Hsync/Vsync pulse width\n"); 2716 return NULL; 2717 } 2718 2719 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2720 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2721 if (!mode) 2722 return NULL; 2723 2724 goto set_size; 2725 } 2726 2727 mode = drm_mode_create(dev); 2728 if (!mode) 2729 return NULL; 2730 2731 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2732 timing->pixel_clock = cpu_to_le16(1088); 2733 2734 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2735 2736 mode->hdisplay = hactive; 2737 mode->hsync_start = mode->hdisplay + hsync_offset; 2738 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2739 mode->htotal = mode->hdisplay + hblank; 2740 2741 mode->vdisplay = vactive; 2742 mode->vsync_start = mode->vdisplay + vsync_offset; 2743 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2744 mode->vtotal = mode->vdisplay + vblank; 2745 2746 /* Some EDIDs have bogus h/vtotal values */ 2747 if (mode->hsync_end > mode->htotal) 2748 mode->htotal = mode->hsync_end + 1; 2749 if (mode->vsync_end > mode->vtotal) 2750 mode->vtotal = mode->vsync_end + 1; 2751 2752 drm_mode_do_interlace_quirk(mode, pt); 2753 2754 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2755 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2756 } 2757 2758 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2759 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2760 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2761 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2762 2763 set_size: 2764 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2765 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2766 2767 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2768 mode->width_mm *= 10; 2769 mode->height_mm *= 10; 2770 } 2771 2772 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2773 mode->width_mm = edid->width_cm * 10; 2774 mode->height_mm = edid->height_cm * 10; 2775 } 2776 2777 mode->type = DRM_MODE_TYPE_DRIVER; 2778 drm_mode_set_name(mode); 2779 2780 return mode; 2781 } 2782 2783 static bool 2784 mode_in_hsync_range(const struct drm_display_mode *mode, 2785 struct edid *edid, u8 *t) 2786 { 2787 int hsync, hmin, hmax; 2788 2789 hmin = t[7]; 2790 if (edid->revision >= 4) 2791 hmin += ((t[4] & 0x04) ? 255 : 0); 2792 hmax = t[8]; 2793 if (edid->revision >= 4) 2794 hmax += ((t[4] & 0x08) ? 255 : 0); 2795 hsync = drm_mode_hsync(mode); 2796 2797 return (hsync <= hmax && hsync >= hmin); 2798 } 2799 2800 static bool 2801 mode_in_vsync_range(const struct drm_display_mode *mode, 2802 struct edid *edid, u8 *t) 2803 { 2804 int vsync, vmin, vmax; 2805 2806 vmin = t[5]; 2807 if (edid->revision >= 4) 2808 vmin += ((t[4] & 0x01) ? 255 : 0); 2809 vmax = t[6]; 2810 if (edid->revision >= 4) 2811 vmax += ((t[4] & 0x02) ? 255 : 0); 2812 vsync = drm_mode_vrefresh(mode); 2813 2814 return (vsync <= vmax && vsync >= vmin); 2815 } 2816 2817 static u32 2818 range_pixel_clock(struct edid *edid, u8 *t) 2819 { 2820 /* unspecified */ 2821 if (t[9] == 0 || t[9] == 255) 2822 return 0; 2823 2824 /* 1.4 with CVT support gives us real precision, yay */ 2825 if (edid->revision >= 4 && t[10] == 0x04) 2826 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2827 2828 /* 1.3 is pathetic, so fuzz up a bit */ 2829 return t[9] * 10000 + 5001; 2830 } 2831 2832 static bool 2833 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2834 struct detailed_timing *timing) 2835 { 2836 u32 max_clock; 2837 u8 *t = (u8 *)timing; 2838 2839 if (!mode_in_hsync_range(mode, edid, t)) 2840 return false; 2841 2842 if (!mode_in_vsync_range(mode, edid, t)) 2843 return false; 2844 2845 if ((max_clock = range_pixel_clock(edid, t))) 2846 if (mode->clock > max_clock) 2847 return false; 2848 2849 /* 1.4 max horizontal check */ 2850 if (edid->revision >= 4 && t[10] == 0x04) 2851 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2852 return false; 2853 2854 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2855 return false; 2856 2857 return true; 2858 } 2859 2860 static bool valid_inferred_mode(const struct drm_connector *connector, 2861 const struct drm_display_mode *mode) 2862 { 2863 const struct drm_display_mode *m; 2864 bool ok = false; 2865 2866 list_for_each_entry(m, &connector->probed_modes, head) { 2867 if (mode->hdisplay == m->hdisplay && 2868 mode->vdisplay == m->vdisplay && 2869 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2870 return false; /* duplicated */ 2871 if (mode->hdisplay <= m->hdisplay && 2872 mode->vdisplay <= m->vdisplay) 2873 ok = true; 2874 } 2875 return ok; 2876 } 2877 2878 static int 2879 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2880 struct detailed_timing *timing) 2881 { 2882 int i, modes = 0; 2883 struct drm_display_mode *newmode; 2884 struct drm_device *dev = connector->dev; 2885 2886 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2887 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2888 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2889 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2890 if (newmode) { 2891 drm_mode_probed_add(connector, newmode); 2892 modes++; 2893 } 2894 } 2895 } 2896 2897 return modes; 2898 } 2899 2900 /* fix up 1366x768 mode from 1368x768; 2901 * GFT/CVT can't express 1366 width which isn't dividable by 8 2902 */ 2903 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2904 { 2905 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2906 mode->hdisplay = 1366; 2907 mode->hsync_start--; 2908 mode->hsync_end--; 2909 drm_mode_set_name(mode); 2910 } 2911 } 2912 2913 static int 2914 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2915 struct detailed_timing *timing) 2916 { 2917 int i, modes = 0; 2918 struct drm_display_mode *newmode; 2919 struct drm_device *dev = connector->dev; 2920 2921 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2922 const struct minimode *m = &extra_modes[i]; 2923 2924 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2925 if (!newmode) 2926 return modes; 2927 2928 drm_mode_fixup_1366x768(newmode); 2929 if (!mode_in_range(newmode, edid, timing) || 2930 !valid_inferred_mode(connector, newmode)) { 2931 drm_mode_destroy(dev, newmode); 2932 continue; 2933 } 2934 2935 drm_mode_probed_add(connector, newmode); 2936 modes++; 2937 } 2938 2939 return modes; 2940 } 2941 2942 static int 2943 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2944 struct detailed_timing *timing) 2945 { 2946 int i, modes = 0; 2947 struct drm_display_mode *newmode; 2948 struct drm_device *dev = connector->dev; 2949 bool rb = drm_monitor_supports_rb(edid); 2950 2951 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2952 const struct minimode *m = &extra_modes[i]; 2953 2954 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2955 if (!newmode) 2956 return modes; 2957 2958 drm_mode_fixup_1366x768(newmode); 2959 if (!mode_in_range(newmode, edid, timing) || 2960 !valid_inferred_mode(connector, newmode)) { 2961 drm_mode_destroy(dev, newmode); 2962 continue; 2963 } 2964 2965 drm_mode_probed_add(connector, newmode); 2966 modes++; 2967 } 2968 2969 return modes; 2970 } 2971 2972 static void 2973 do_inferred_modes(struct detailed_timing *timing, void *c) 2974 { 2975 struct detailed_mode_closure *closure = c; 2976 struct detailed_non_pixel *data = &timing->data.other_data; 2977 struct detailed_data_monitor_range *range = &data->data.range; 2978 2979 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2980 return; 2981 2982 closure->modes += drm_dmt_modes_for_range(closure->connector, 2983 closure->edid, 2984 timing); 2985 2986 if (!version_greater(closure->edid, 1, 1)) 2987 return; /* GTF not defined yet */ 2988 2989 switch (range->flags) { 2990 case 0x02: /* secondary gtf, XXX could do more */ 2991 case 0x00: /* default gtf */ 2992 closure->modes += drm_gtf_modes_for_range(closure->connector, 2993 closure->edid, 2994 timing); 2995 break; 2996 case 0x04: /* cvt, only in 1.4+ */ 2997 if (!version_greater(closure->edid, 1, 3)) 2998 break; 2999 3000 closure->modes += drm_cvt_modes_for_range(closure->connector, 3001 closure->edid, 3002 timing); 3003 break; 3004 case 0x01: /* just the ranges, no formula */ 3005 default: 3006 break; 3007 } 3008 } 3009 3010 static int 3011 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 3012 { 3013 struct detailed_mode_closure closure = { 3014 .connector = connector, 3015 .edid = edid, 3016 }; 3017 3018 if (version_greater(edid, 1, 0)) 3019 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 3020 &closure); 3021 3022 return closure.modes; 3023 } 3024 3025 static int 3026 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 3027 { 3028 int i, j, m, modes = 0; 3029 struct drm_display_mode *mode; 3030 u8 *est = ((u8 *)timing) + 6; 3031 3032 for (i = 0; i < 6; i++) { 3033 for (j = 7; j >= 0; j--) { 3034 m = (i * 8) + (7 - j); 3035 if (m >= ARRAY_SIZE(est3_modes)) 3036 break; 3037 if (est[i] & (1 << j)) { 3038 mode = drm_mode_find_dmt(connector->dev, 3039 est3_modes[m].w, 3040 est3_modes[m].h, 3041 est3_modes[m].r, 3042 est3_modes[m].rb); 3043 if (mode) { 3044 drm_mode_probed_add(connector, mode); 3045 modes++; 3046 } 3047 } 3048 } 3049 } 3050 3051 return modes; 3052 } 3053 3054 static void 3055 do_established_modes(struct detailed_timing *timing, void *c) 3056 { 3057 struct detailed_mode_closure *closure = c; 3058 3059 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 3060 return; 3061 3062 closure->modes += drm_est3_modes(closure->connector, timing); 3063 } 3064 3065 /** 3066 * add_established_modes - get est. modes from EDID and add them 3067 * @connector: connector to add mode(s) to 3068 * @edid: EDID block to scan 3069 * 3070 * Each EDID block contains a bitmap of the supported "established modes" list 3071 * (defined above). Tease them out and add them to the global modes list. 3072 */ 3073 static int 3074 add_established_modes(struct drm_connector *connector, struct edid *edid) 3075 { 3076 struct drm_device *dev = connector->dev; 3077 unsigned long est_bits = edid->established_timings.t1 | 3078 (edid->established_timings.t2 << 8) | 3079 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3080 int i, modes = 0; 3081 struct detailed_mode_closure closure = { 3082 .connector = connector, 3083 .edid = edid, 3084 }; 3085 3086 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3087 if (est_bits & (1<<i)) { 3088 struct drm_display_mode *newmode; 3089 3090 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3091 if (newmode) { 3092 drm_mode_probed_add(connector, newmode); 3093 modes++; 3094 } 3095 } 3096 } 3097 3098 if (version_greater(edid, 1, 0)) 3099 drm_for_each_detailed_block((u8 *)edid, 3100 do_established_modes, &closure); 3101 3102 return modes + closure.modes; 3103 } 3104 3105 static void 3106 do_standard_modes(struct detailed_timing *timing, void *c) 3107 { 3108 struct detailed_mode_closure *closure = c; 3109 struct detailed_non_pixel *data = &timing->data.other_data; 3110 struct drm_connector *connector = closure->connector; 3111 struct edid *edid = closure->edid; 3112 int i; 3113 3114 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3115 return; 3116 3117 for (i = 0; i < 6; i++) { 3118 struct std_timing *std = &data->data.timings[i]; 3119 struct drm_display_mode *newmode; 3120 3121 newmode = drm_mode_std(connector, edid, std); 3122 if (newmode) { 3123 drm_mode_probed_add(connector, newmode); 3124 closure->modes++; 3125 } 3126 } 3127 } 3128 3129 /** 3130 * add_standard_modes - get std. modes from EDID and add them 3131 * @connector: connector to add mode(s) to 3132 * @edid: EDID block to scan 3133 * 3134 * Standard modes can be calculated using the appropriate standard (DMT, 3135 * GTF or CVT. Grab them from @edid and add them to the list. 3136 */ 3137 static int 3138 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3139 { 3140 int i, modes = 0; 3141 struct detailed_mode_closure closure = { 3142 .connector = connector, 3143 .edid = edid, 3144 }; 3145 3146 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3147 struct drm_display_mode *newmode; 3148 3149 newmode = drm_mode_std(connector, edid, 3150 &edid->standard_timings[i]); 3151 if (newmode) { 3152 drm_mode_probed_add(connector, newmode); 3153 modes++; 3154 } 3155 } 3156 3157 if (version_greater(edid, 1, 0)) 3158 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3159 &closure); 3160 3161 /* XXX should also look for standard codes in VTB blocks */ 3162 3163 return modes + closure.modes; 3164 } 3165 3166 static int drm_cvt_modes(struct drm_connector *connector, 3167 struct detailed_timing *timing) 3168 { 3169 int i, j, modes = 0; 3170 struct drm_display_mode *newmode; 3171 struct drm_device *dev = connector->dev; 3172 struct cvt_timing *cvt; 3173 const int rates[] = { 60, 85, 75, 60, 50 }; 3174 const u8 empty[3] = { 0, 0, 0 }; 3175 3176 for (i = 0; i < 4; i++) { 3177 int width, height; 3178 3179 cvt = &(timing->data.other_data.data.cvt[i]); 3180 3181 if (!memcmp(cvt->code, empty, 3)) 3182 continue; 3183 3184 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3185 switch (cvt->code[1] & 0x0c) { 3186 /* default - because compiler doesn't see that we've enumerated all cases */ 3187 default: 3188 case 0x00: 3189 width = height * 4 / 3; 3190 break; 3191 case 0x04: 3192 width = height * 16 / 9; 3193 break; 3194 case 0x08: 3195 width = height * 16 / 10; 3196 break; 3197 case 0x0c: 3198 width = height * 15 / 9; 3199 break; 3200 } 3201 3202 for (j = 1; j < 5; j++) { 3203 if (cvt->code[2] & (1 << j)) { 3204 newmode = drm_cvt_mode(dev, width, height, 3205 rates[j], j == 0, 3206 false, false); 3207 if (newmode) { 3208 drm_mode_probed_add(connector, newmode); 3209 modes++; 3210 } 3211 } 3212 } 3213 } 3214 3215 return modes; 3216 } 3217 3218 static void 3219 do_cvt_mode(struct detailed_timing *timing, void *c) 3220 { 3221 struct detailed_mode_closure *closure = c; 3222 3223 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3224 return; 3225 3226 closure->modes += drm_cvt_modes(closure->connector, timing); 3227 } 3228 3229 static int 3230 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3231 { 3232 struct detailed_mode_closure closure = { 3233 .connector = connector, 3234 .edid = edid, 3235 }; 3236 3237 if (version_greater(edid, 1, 2)) 3238 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3239 3240 /* XXX should also look for CVT codes in VTB blocks */ 3241 3242 return closure.modes; 3243 } 3244 3245 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3246 3247 static void 3248 do_detailed_mode(struct detailed_timing *timing, void *c) 3249 { 3250 struct detailed_mode_closure *closure = c; 3251 struct drm_display_mode *newmode; 3252 3253 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3254 return; 3255 3256 newmode = drm_mode_detailed(closure->connector->dev, 3257 closure->edid, timing, 3258 closure->quirks); 3259 if (!newmode) 3260 return; 3261 3262 if (closure->preferred) 3263 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3264 3265 /* 3266 * Detailed modes are limited to 10kHz pixel clock resolution, 3267 * so fix up anything that looks like CEA/HDMI mode, but the clock 3268 * is just slightly off. 3269 */ 3270 fixup_detailed_cea_mode_clock(newmode); 3271 3272 drm_mode_probed_add(closure->connector, newmode); 3273 closure->modes++; 3274 closure->preferred = false; 3275 } 3276 3277 /* 3278 * add_detailed_modes - Add modes from detailed timings 3279 * @connector: attached connector 3280 * @edid: EDID block to scan 3281 * @quirks: quirks to apply 3282 */ 3283 static int 3284 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3285 u32 quirks) 3286 { 3287 struct detailed_mode_closure closure = { 3288 .connector = connector, 3289 .edid = edid, 3290 .preferred = true, 3291 .quirks = quirks, 3292 }; 3293 3294 if (closure.preferred && !version_greater(edid, 1, 3)) 3295 closure.preferred = 3296 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3297 3298 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3299 3300 return closure.modes; 3301 } 3302 3303 #define AUDIO_BLOCK 0x01 3304 #define VIDEO_BLOCK 0x02 3305 #define VENDOR_BLOCK 0x03 3306 #define SPEAKER_BLOCK 0x04 3307 #define HDR_STATIC_METADATA_BLOCK 0x6 3308 #define USE_EXTENDED_TAG 0x07 3309 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3310 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3311 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3312 #define EDID_BASIC_AUDIO (1 << 6) 3313 #define EDID_CEA_YCRCB444 (1 << 5) 3314 #define EDID_CEA_YCRCB422 (1 << 4) 3315 #define EDID_CEA_VCDB_QS (1 << 6) 3316 3317 /* 3318 * Search EDID for CEA extension block. 3319 */ 3320 const u8 *drm_find_edid_extension(const struct edid *edid, 3321 int ext_id, int *ext_index) 3322 { 3323 const u8 *edid_ext = NULL; 3324 int i; 3325 3326 /* No EDID or EDID extensions */ 3327 if (edid == NULL || edid->extensions == 0) 3328 return NULL; 3329 3330 /* Find CEA extension */ 3331 for (i = *ext_index; i < edid->extensions; i++) { 3332 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1); 3333 if (edid_ext[0] == ext_id) 3334 break; 3335 } 3336 3337 if (i >= edid->extensions) 3338 return NULL; 3339 3340 *ext_index = i + 1; 3341 3342 return edid_ext; 3343 } 3344 3345 static const u8 *drm_find_cea_extension(const struct edid *edid) 3346 { 3347 const struct displayid_block *block; 3348 struct displayid_iter iter; 3349 const u8 *cea; 3350 int ext_index = 0; 3351 3352 /* Look for a top level CEA extension block */ 3353 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3354 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3355 if (cea) 3356 return cea; 3357 3358 /* CEA blocks can also be found embedded in a DisplayID block */ 3359 displayid_iter_edid_begin(edid, &iter); 3360 displayid_iter_for_each(block, &iter) { 3361 if (block->tag == DATA_BLOCK_CTA) { 3362 cea = (const u8 *)block; 3363 break; 3364 } 3365 } 3366 displayid_iter_end(&iter); 3367 3368 return cea; 3369 } 3370 3371 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3372 { 3373 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3374 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3375 3376 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3377 return &edid_cea_modes_1[vic - 1]; 3378 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3379 return &edid_cea_modes_193[vic - 193]; 3380 return NULL; 3381 } 3382 3383 static u8 cea_num_vics(void) 3384 { 3385 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3386 } 3387 3388 static u8 cea_next_vic(u8 vic) 3389 { 3390 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3391 vic = 193; 3392 return vic; 3393 } 3394 3395 /* 3396 * Calculate the alternate clock for the CEA mode 3397 * (60Hz vs. 59.94Hz etc.) 3398 */ 3399 static unsigned int 3400 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3401 { 3402 unsigned int clock = cea_mode->clock; 3403 3404 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3405 return clock; 3406 3407 /* 3408 * edid_cea_modes contains the 59.94Hz 3409 * variant for 240 and 480 line modes, 3410 * and the 60Hz variant otherwise. 3411 */ 3412 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3413 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3414 else 3415 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3416 3417 return clock; 3418 } 3419 3420 static bool 3421 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3422 { 3423 /* 3424 * For certain VICs the spec allows the vertical 3425 * front porch to vary by one or two lines. 3426 * 3427 * cea_modes[] stores the variant with the shortest 3428 * vertical front porch. We can adjust the mode to 3429 * get the other variants by simply increasing the 3430 * vertical front porch length. 3431 */ 3432 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3433 cea_mode_for_vic(9)->vtotal != 262 || 3434 cea_mode_for_vic(12)->vtotal != 262 || 3435 cea_mode_for_vic(13)->vtotal != 262 || 3436 cea_mode_for_vic(23)->vtotal != 312 || 3437 cea_mode_for_vic(24)->vtotal != 312 || 3438 cea_mode_for_vic(27)->vtotal != 312 || 3439 cea_mode_for_vic(28)->vtotal != 312); 3440 3441 if (((vic == 8 || vic == 9 || 3442 vic == 12 || vic == 13) && mode->vtotal < 263) || 3443 ((vic == 23 || vic == 24 || 3444 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3445 mode->vsync_start++; 3446 mode->vsync_end++; 3447 mode->vtotal++; 3448 3449 return true; 3450 } 3451 3452 return false; 3453 } 3454 3455 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3456 unsigned int clock_tolerance) 3457 { 3458 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3459 u8 vic; 3460 3461 if (!to_match->clock) 3462 return 0; 3463 3464 if (to_match->picture_aspect_ratio) 3465 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3466 3467 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3468 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3469 unsigned int clock1, clock2; 3470 3471 /* Check both 60Hz and 59.94Hz */ 3472 clock1 = cea_mode.clock; 3473 clock2 = cea_mode_alternate_clock(&cea_mode); 3474 3475 if (abs(to_match->clock - clock1) > clock_tolerance && 3476 abs(to_match->clock - clock2) > clock_tolerance) 3477 continue; 3478 3479 do { 3480 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3481 return vic; 3482 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3483 } 3484 3485 return 0; 3486 } 3487 3488 /** 3489 * drm_match_cea_mode - look for a CEA mode matching given mode 3490 * @to_match: display mode 3491 * 3492 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3493 * mode. 3494 */ 3495 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3496 { 3497 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3498 u8 vic; 3499 3500 if (!to_match->clock) 3501 return 0; 3502 3503 if (to_match->picture_aspect_ratio) 3504 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3505 3506 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3507 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3508 unsigned int clock1, clock2; 3509 3510 /* Check both 60Hz and 59.94Hz */ 3511 clock1 = cea_mode.clock; 3512 clock2 = cea_mode_alternate_clock(&cea_mode); 3513 3514 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3515 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3516 continue; 3517 3518 do { 3519 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3520 return vic; 3521 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3522 } 3523 3524 return 0; 3525 } 3526 EXPORT_SYMBOL(drm_match_cea_mode); 3527 3528 static bool drm_valid_cea_vic(u8 vic) 3529 { 3530 return cea_mode_for_vic(vic) != NULL; 3531 } 3532 3533 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3534 { 3535 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3536 3537 if (mode) 3538 return mode->picture_aspect_ratio; 3539 3540 return HDMI_PICTURE_ASPECT_NONE; 3541 } 3542 3543 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3544 { 3545 return edid_4k_modes[video_code].picture_aspect_ratio; 3546 } 3547 3548 /* 3549 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3550 * specific block). 3551 */ 3552 static unsigned int 3553 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3554 { 3555 return cea_mode_alternate_clock(hdmi_mode); 3556 } 3557 3558 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3559 unsigned int clock_tolerance) 3560 { 3561 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3562 u8 vic; 3563 3564 if (!to_match->clock) 3565 return 0; 3566 3567 if (to_match->picture_aspect_ratio) 3568 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3569 3570 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3571 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3572 unsigned int clock1, clock2; 3573 3574 /* Make sure to also match alternate clocks */ 3575 clock1 = hdmi_mode->clock; 3576 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3577 3578 if (abs(to_match->clock - clock1) > clock_tolerance && 3579 abs(to_match->clock - clock2) > clock_tolerance) 3580 continue; 3581 3582 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3583 return vic; 3584 } 3585 3586 return 0; 3587 } 3588 3589 /* 3590 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3591 * @to_match: display mode 3592 * 3593 * An HDMI mode is one defined in the HDMI vendor specific block. 3594 * 3595 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3596 */ 3597 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3598 { 3599 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3600 u8 vic; 3601 3602 if (!to_match->clock) 3603 return 0; 3604 3605 if (to_match->picture_aspect_ratio) 3606 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3607 3608 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3609 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3610 unsigned int clock1, clock2; 3611 3612 /* Make sure to also match alternate clocks */ 3613 clock1 = hdmi_mode->clock; 3614 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3615 3616 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3617 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3618 drm_mode_match(to_match, hdmi_mode, match_flags)) 3619 return vic; 3620 } 3621 return 0; 3622 } 3623 3624 static bool drm_valid_hdmi_vic(u8 vic) 3625 { 3626 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3627 } 3628 3629 static int 3630 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3631 { 3632 struct drm_device *dev = connector->dev; 3633 struct drm_display_mode *mode, *tmp; 3634 LIST_HEAD(list); 3635 int modes = 0; 3636 3637 /* Don't add CEA modes if the CEA extension block is missing */ 3638 if (!drm_find_cea_extension(edid)) 3639 return 0; 3640 3641 /* 3642 * Go through all probed modes and create a new mode 3643 * with the alternate clock for certain CEA modes. 3644 */ 3645 list_for_each_entry(mode, &connector->probed_modes, head) { 3646 const struct drm_display_mode *cea_mode = NULL; 3647 struct drm_display_mode *newmode; 3648 u8 vic = drm_match_cea_mode(mode); 3649 unsigned int clock1, clock2; 3650 3651 if (drm_valid_cea_vic(vic)) { 3652 cea_mode = cea_mode_for_vic(vic); 3653 clock2 = cea_mode_alternate_clock(cea_mode); 3654 } else { 3655 vic = drm_match_hdmi_mode(mode); 3656 if (drm_valid_hdmi_vic(vic)) { 3657 cea_mode = &edid_4k_modes[vic]; 3658 clock2 = hdmi_mode_alternate_clock(cea_mode); 3659 } 3660 } 3661 3662 if (!cea_mode) 3663 continue; 3664 3665 clock1 = cea_mode->clock; 3666 3667 if (clock1 == clock2) 3668 continue; 3669 3670 if (mode->clock != clock1 && mode->clock != clock2) 3671 continue; 3672 3673 newmode = drm_mode_duplicate(dev, cea_mode); 3674 if (!newmode) 3675 continue; 3676 3677 /* Carry over the stereo flags */ 3678 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3679 3680 /* 3681 * The current mode could be either variant. Make 3682 * sure to pick the "other" clock for the new mode. 3683 */ 3684 if (mode->clock != clock1) 3685 newmode->clock = clock1; 3686 else 3687 newmode->clock = clock2; 3688 3689 list_add_tail(&newmode->head, &list); 3690 } 3691 3692 list_for_each_entry_safe(mode, tmp, &list, head) { 3693 list_del(&mode->head); 3694 drm_mode_probed_add(connector, mode); 3695 modes++; 3696 } 3697 3698 return modes; 3699 } 3700 3701 static u8 svd_to_vic(u8 svd) 3702 { 3703 /* 0-6 bit vic, 7th bit native mode indicator */ 3704 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3705 return svd & 127; 3706 3707 return svd; 3708 } 3709 3710 static struct drm_display_mode * 3711 drm_display_mode_from_vic_index(struct drm_connector *connector, 3712 const u8 *video_db, u8 video_len, 3713 u8 video_index) 3714 { 3715 struct drm_device *dev = connector->dev; 3716 struct drm_display_mode *newmode; 3717 u8 vic; 3718 3719 if (video_db == NULL || video_index >= video_len) 3720 return NULL; 3721 3722 /* CEA modes are numbered 1..127 */ 3723 vic = svd_to_vic(video_db[video_index]); 3724 if (!drm_valid_cea_vic(vic)) 3725 return NULL; 3726 3727 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3728 if (!newmode) 3729 return NULL; 3730 3731 return newmode; 3732 } 3733 3734 /* 3735 * do_y420vdb_modes - Parse YCBCR 420 only modes 3736 * @connector: connector corresponding to the HDMI sink 3737 * @svds: start of the data block of CEA YCBCR 420 VDB 3738 * @len: length of the CEA YCBCR 420 VDB 3739 * 3740 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3741 * which contains modes which can be supported in YCBCR 420 3742 * output format only. 3743 */ 3744 static int do_y420vdb_modes(struct drm_connector *connector, 3745 const u8 *svds, u8 svds_len) 3746 { 3747 int modes = 0, i; 3748 struct drm_device *dev = connector->dev; 3749 struct drm_display_info *info = &connector->display_info; 3750 struct drm_hdmi_info *hdmi = &info->hdmi; 3751 3752 for (i = 0; i < svds_len; i++) { 3753 u8 vic = svd_to_vic(svds[i]); 3754 struct drm_display_mode *newmode; 3755 3756 if (!drm_valid_cea_vic(vic)) 3757 continue; 3758 3759 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3760 if (!newmode) 3761 break; 3762 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3763 drm_mode_probed_add(connector, newmode); 3764 modes++; 3765 } 3766 3767 if (modes > 0) 3768 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3769 return modes; 3770 } 3771 3772 /* 3773 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3774 * @connector: connector corresponding to the HDMI sink 3775 * @vic: CEA vic for the video mode to be added in the map 3776 * 3777 * Makes an entry for a videomode in the YCBCR 420 bitmap 3778 */ 3779 static void 3780 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3781 { 3782 u8 vic = svd_to_vic(svd); 3783 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3784 3785 if (!drm_valid_cea_vic(vic)) 3786 return; 3787 3788 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3789 } 3790 3791 /** 3792 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3793 * @dev: DRM device 3794 * @video_code: CEA VIC of the mode 3795 * 3796 * Creates a new mode matching the specified CEA VIC. 3797 * 3798 * Returns: A new drm_display_mode on success or NULL on failure 3799 */ 3800 struct drm_display_mode * 3801 drm_display_mode_from_cea_vic(struct drm_device *dev, 3802 u8 video_code) 3803 { 3804 const struct drm_display_mode *cea_mode; 3805 struct drm_display_mode *newmode; 3806 3807 cea_mode = cea_mode_for_vic(video_code); 3808 if (!cea_mode) 3809 return NULL; 3810 3811 newmode = drm_mode_duplicate(dev, cea_mode); 3812 if (!newmode) 3813 return NULL; 3814 3815 return newmode; 3816 } 3817 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3818 3819 static int 3820 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3821 { 3822 int i, modes = 0; 3823 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3824 3825 for (i = 0; i < len; i++) { 3826 struct drm_display_mode *mode; 3827 3828 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3829 if (mode) { 3830 /* 3831 * YCBCR420 capability block contains a bitmap which 3832 * gives the index of CEA modes from CEA VDB, which 3833 * can support YCBCR 420 sampling output also (apart 3834 * from RGB/YCBCR444 etc). 3835 * For example, if the bit 0 in bitmap is set, 3836 * first mode in VDB can support YCBCR420 output too. 3837 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3838 */ 3839 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3840 drm_add_cmdb_modes(connector, db[i]); 3841 3842 drm_mode_probed_add(connector, mode); 3843 modes++; 3844 } 3845 } 3846 3847 return modes; 3848 } 3849 3850 struct stereo_mandatory_mode { 3851 int width, height, vrefresh; 3852 unsigned int flags; 3853 }; 3854 3855 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3856 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3857 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3858 { 1920, 1080, 50, 3859 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3860 { 1920, 1080, 60, 3861 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3862 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3863 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3864 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3865 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3866 }; 3867 3868 static bool 3869 stereo_match_mandatory(const struct drm_display_mode *mode, 3870 const struct stereo_mandatory_mode *stereo_mode) 3871 { 3872 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3873 3874 return mode->hdisplay == stereo_mode->width && 3875 mode->vdisplay == stereo_mode->height && 3876 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3877 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3878 } 3879 3880 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3881 { 3882 struct drm_device *dev = connector->dev; 3883 const struct drm_display_mode *mode; 3884 struct list_head stereo_modes; 3885 int modes = 0, i; 3886 3887 INIT_LIST_HEAD(&stereo_modes); 3888 3889 list_for_each_entry(mode, &connector->probed_modes, head) { 3890 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3891 const struct stereo_mandatory_mode *mandatory; 3892 struct drm_display_mode *new_mode; 3893 3894 if (!stereo_match_mandatory(mode, 3895 &stereo_mandatory_modes[i])) 3896 continue; 3897 3898 mandatory = &stereo_mandatory_modes[i]; 3899 new_mode = drm_mode_duplicate(dev, mode); 3900 if (!new_mode) 3901 continue; 3902 3903 new_mode->flags |= mandatory->flags; 3904 list_add_tail(&new_mode->head, &stereo_modes); 3905 modes++; 3906 } 3907 } 3908 3909 list_splice_tail(&stereo_modes, &connector->probed_modes); 3910 3911 return modes; 3912 } 3913 3914 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3915 { 3916 struct drm_device *dev = connector->dev; 3917 struct drm_display_mode *newmode; 3918 3919 if (!drm_valid_hdmi_vic(vic)) { 3920 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3921 return 0; 3922 } 3923 3924 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3925 if (!newmode) 3926 return 0; 3927 3928 drm_mode_probed_add(connector, newmode); 3929 3930 return 1; 3931 } 3932 3933 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3934 const u8 *video_db, u8 video_len, u8 video_index) 3935 { 3936 struct drm_display_mode *newmode; 3937 int modes = 0; 3938 3939 if (structure & (1 << 0)) { 3940 newmode = drm_display_mode_from_vic_index(connector, video_db, 3941 video_len, 3942 video_index); 3943 if (newmode) { 3944 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3945 drm_mode_probed_add(connector, newmode); 3946 modes++; 3947 } 3948 } 3949 if (structure & (1 << 6)) { 3950 newmode = drm_display_mode_from_vic_index(connector, video_db, 3951 video_len, 3952 video_index); 3953 if (newmode) { 3954 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3955 drm_mode_probed_add(connector, newmode); 3956 modes++; 3957 } 3958 } 3959 if (structure & (1 << 8)) { 3960 newmode = drm_display_mode_from_vic_index(connector, video_db, 3961 video_len, 3962 video_index); 3963 if (newmode) { 3964 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3965 drm_mode_probed_add(connector, newmode); 3966 modes++; 3967 } 3968 } 3969 3970 return modes; 3971 } 3972 3973 /* 3974 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3975 * @connector: connector corresponding to the HDMI sink 3976 * @db: start of the CEA vendor specific block 3977 * @len: length of the CEA block payload, ie. one can access up to db[len] 3978 * 3979 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3980 * also adds the stereo 3d modes when applicable. 3981 */ 3982 static int 3983 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3984 const u8 *video_db, u8 video_len) 3985 { 3986 struct drm_display_info *info = &connector->display_info; 3987 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3988 u8 vic_len, hdmi_3d_len = 0; 3989 u16 mask; 3990 u16 structure_all; 3991 3992 if (len < 8) 3993 goto out; 3994 3995 /* no HDMI_Video_Present */ 3996 if (!(db[8] & (1 << 5))) 3997 goto out; 3998 3999 /* Latency_Fields_Present */ 4000 if (db[8] & (1 << 7)) 4001 offset += 2; 4002 4003 /* I_Latency_Fields_Present */ 4004 if (db[8] & (1 << 6)) 4005 offset += 2; 4006 4007 /* the declared length is not long enough for the 2 first bytes 4008 * of additional video format capabilities */ 4009 if (len < (8 + offset + 2)) 4010 goto out; 4011 4012 /* 3D_Present */ 4013 offset++; 4014 if (db[8 + offset] & (1 << 7)) { 4015 modes += add_hdmi_mandatory_stereo_modes(connector); 4016 4017 /* 3D_Multi_present */ 4018 multi_present = (db[8 + offset] & 0x60) >> 5; 4019 } 4020 4021 offset++; 4022 vic_len = db[8 + offset] >> 5; 4023 hdmi_3d_len = db[8 + offset] & 0x1f; 4024 4025 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4026 u8 vic; 4027 4028 vic = db[9 + offset + i]; 4029 modes += add_hdmi_mode(connector, vic); 4030 } 4031 offset += 1 + vic_len; 4032 4033 if (multi_present == 1) 4034 multi_len = 2; 4035 else if (multi_present == 2) 4036 multi_len = 4; 4037 else 4038 multi_len = 0; 4039 4040 if (len < (8 + offset + hdmi_3d_len - 1)) 4041 goto out; 4042 4043 if (hdmi_3d_len < multi_len) 4044 goto out; 4045 4046 if (multi_present == 1 || multi_present == 2) { 4047 /* 3D_Structure_ALL */ 4048 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4049 4050 /* check if 3D_MASK is present */ 4051 if (multi_present == 2) 4052 mask = (db[10 + offset] << 8) | db[11 + offset]; 4053 else 4054 mask = 0xffff; 4055 4056 for (i = 0; i < 16; i++) { 4057 if (mask & (1 << i)) 4058 modes += add_3d_struct_modes(connector, 4059 structure_all, 4060 video_db, 4061 video_len, i); 4062 } 4063 } 4064 4065 offset += multi_len; 4066 4067 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4068 int vic_index; 4069 struct drm_display_mode *newmode = NULL; 4070 unsigned int newflag = 0; 4071 bool detail_present; 4072 4073 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4074 4075 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4076 break; 4077 4078 /* 2D_VIC_order_X */ 4079 vic_index = db[8 + offset + i] >> 4; 4080 4081 /* 3D_Structure_X */ 4082 switch (db[8 + offset + i] & 0x0f) { 4083 case 0: 4084 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4085 break; 4086 case 6: 4087 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4088 break; 4089 case 8: 4090 /* 3D_Detail_X */ 4091 if ((db[9 + offset + i] >> 4) == 1) 4092 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4093 break; 4094 } 4095 4096 if (newflag != 0) { 4097 newmode = drm_display_mode_from_vic_index(connector, 4098 video_db, 4099 video_len, 4100 vic_index); 4101 4102 if (newmode) { 4103 newmode->flags |= newflag; 4104 drm_mode_probed_add(connector, newmode); 4105 modes++; 4106 } 4107 } 4108 4109 if (detail_present) 4110 i++; 4111 } 4112 4113 out: 4114 if (modes > 0) 4115 info->has_hdmi_infoframe = true; 4116 return modes; 4117 } 4118 4119 static int 4120 cea_db_payload_len(const u8 *db) 4121 { 4122 return db[0] & 0x1f; 4123 } 4124 4125 static int 4126 cea_db_extended_tag(const u8 *db) 4127 { 4128 return db[1]; 4129 } 4130 4131 static int 4132 cea_db_tag(const u8 *db) 4133 { 4134 return db[0] >> 5; 4135 } 4136 4137 static int 4138 cea_revision(const u8 *cea) 4139 { 4140 /* 4141 * FIXME is this correct for the DispID variant? 4142 * The DispID spec doesn't really specify whether 4143 * this is the revision of the CEA extension or 4144 * the DispID CEA data block. And the only value 4145 * given as an example is 0. 4146 */ 4147 return cea[1]; 4148 } 4149 4150 static int 4151 cea_db_offsets(const u8 *cea, int *start, int *end) 4152 { 4153 /* DisplayID CTA extension blocks and top-level CEA EDID 4154 * block header definitions differ in the following bytes: 4155 * 1) Byte 2 of the header specifies length differently, 4156 * 2) Byte 3 is only present in the CEA top level block. 4157 * 4158 * The different definitions for byte 2 follow. 4159 * 4160 * DisplayID CTA extension block defines byte 2 as: 4161 * Number of payload bytes 4162 * 4163 * CEA EDID block defines byte 2 as: 4164 * Byte number (decimal) within this block where the 18-byte 4165 * DTDs begin. If no non-DTD data is present in this extension 4166 * block, the value should be set to 04h (the byte after next). 4167 * If set to 00h, there are no DTDs present in this block and 4168 * no non-DTD data. 4169 */ 4170 if (cea[0] == DATA_BLOCK_CTA) { 4171 /* 4172 * for_each_displayid_db() has already verified 4173 * that these stay within expected bounds. 4174 */ 4175 *start = 3; 4176 *end = *start + cea[2]; 4177 } else if (cea[0] == CEA_EXT) { 4178 /* Data block offset in CEA extension block */ 4179 *start = 4; 4180 *end = cea[2]; 4181 if (*end == 0) 4182 *end = 127; 4183 if (*end < 4 || *end > 127) 4184 return -ERANGE; 4185 } else { 4186 return -EOPNOTSUPP; 4187 } 4188 4189 return 0; 4190 } 4191 4192 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4193 { 4194 int hdmi_id; 4195 4196 if (cea_db_tag(db) != VENDOR_BLOCK) 4197 return false; 4198 4199 if (cea_db_payload_len(db) < 5) 4200 return false; 4201 4202 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4203 4204 return hdmi_id == HDMI_IEEE_OUI; 4205 } 4206 4207 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4208 { 4209 unsigned int oui; 4210 4211 if (cea_db_tag(db) != VENDOR_BLOCK) 4212 return false; 4213 4214 if (cea_db_payload_len(db) < 7) 4215 return false; 4216 4217 oui = db[3] << 16 | db[2] << 8 | db[1]; 4218 4219 return oui == HDMI_FORUM_IEEE_OUI; 4220 } 4221 4222 static bool cea_db_is_vcdb(const u8 *db) 4223 { 4224 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4225 return false; 4226 4227 if (cea_db_payload_len(db) != 2) 4228 return false; 4229 4230 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4231 return false; 4232 4233 return true; 4234 } 4235 4236 static bool cea_db_is_y420cmdb(const u8 *db) 4237 { 4238 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4239 return false; 4240 4241 if (!cea_db_payload_len(db)) 4242 return false; 4243 4244 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4245 return false; 4246 4247 return true; 4248 } 4249 4250 static bool cea_db_is_y420vdb(const u8 *db) 4251 { 4252 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4253 return false; 4254 4255 if (!cea_db_payload_len(db)) 4256 return false; 4257 4258 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4259 return false; 4260 4261 return true; 4262 } 4263 4264 #define for_each_cea_db(cea, i, start, end) \ 4265 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4266 4267 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4268 const u8 *db) 4269 { 4270 struct drm_display_info *info = &connector->display_info; 4271 struct drm_hdmi_info *hdmi = &info->hdmi; 4272 u8 map_len = cea_db_payload_len(db) - 1; 4273 u8 count; 4274 u64 map = 0; 4275 4276 if (map_len == 0) { 4277 /* All CEA modes support ycbcr420 sampling also.*/ 4278 hdmi->y420_cmdb_map = U64_MAX; 4279 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4280 return; 4281 } 4282 4283 /* 4284 * This map indicates which of the existing CEA block modes 4285 * from VDB can support YCBCR420 output too. So if bit=0 is 4286 * set, first mode from VDB can support YCBCR420 output too. 4287 * We will parse and keep this map, before parsing VDB itself 4288 * to avoid going through the same block again and again. 4289 * 4290 * Spec is not clear about max possible size of this block. 4291 * Clamping max bitmap block size at 8 bytes. Every byte can 4292 * address 8 CEA modes, in this way this map can address 4293 * 8*8 = first 64 SVDs. 4294 */ 4295 if (WARN_ON_ONCE(map_len > 8)) 4296 map_len = 8; 4297 4298 for (count = 0; count < map_len; count++) 4299 map |= (u64)db[2 + count] << (8 * count); 4300 4301 if (map) 4302 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4303 4304 hdmi->y420_cmdb_map = map; 4305 } 4306 4307 static int 4308 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4309 { 4310 const u8 *cea = drm_find_cea_extension(edid); 4311 const u8 *db, *hdmi = NULL, *video = NULL; 4312 u8 dbl, hdmi_len, video_len = 0; 4313 int modes = 0; 4314 4315 if (cea && cea_revision(cea) >= 3) { 4316 int i, start, end; 4317 4318 if (cea_db_offsets(cea, &start, &end)) 4319 return 0; 4320 4321 for_each_cea_db(cea, i, start, end) { 4322 db = &cea[i]; 4323 dbl = cea_db_payload_len(db); 4324 4325 if (cea_db_tag(db) == VIDEO_BLOCK) { 4326 video = db + 1; 4327 video_len = dbl; 4328 modes += do_cea_modes(connector, video, dbl); 4329 } else if (cea_db_is_hdmi_vsdb(db)) { 4330 hdmi = db; 4331 hdmi_len = dbl; 4332 } else if (cea_db_is_y420vdb(db)) { 4333 const u8 *vdb420 = &db[2]; 4334 4335 /* Add 4:2:0(only) modes present in EDID */ 4336 modes += do_y420vdb_modes(connector, 4337 vdb420, 4338 dbl - 1); 4339 } 4340 } 4341 } 4342 4343 /* 4344 * We parse the HDMI VSDB after having added the cea modes as we will 4345 * be patching their flags when the sink supports stereo 3D. 4346 */ 4347 if (hdmi) 4348 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4349 video_len); 4350 4351 return modes; 4352 } 4353 4354 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4355 { 4356 const struct drm_display_mode *cea_mode; 4357 int clock1, clock2, clock; 4358 u8 vic; 4359 const char *type; 4360 4361 /* 4362 * allow 5kHz clock difference either way to account for 4363 * the 10kHz clock resolution limit of detailed timings. 4364 */ 4365 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4366 if (drm_valid_cea_vic(vic)) { 4367 type = "CEA"; 4368 cea_mode = cea_mode_for_vic(vic); 4369 clock1 = cea_mode->clock; 4370 clock2 = cea_mode_alternate_clock(cea_mode); 4371 } else { 4372 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4373 if (drm_valid_hdmi_vic(vic)) { 4374 type = "HDMI"; 4375 cea_mode = &edid_4k_modes[vic]; 4376 clock1 = cea_mode->clock; 4377 clock2 = hdmi_mode_alternate_clock(cea_mode); 4378 } else { 4379 return; 4380 } 4381 } 4382 4383 /* pick whichever is closest */ 4384 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4385 clock = clock1; 4386 else 4387 clock = clock2; 4388 4389 if (mode->clock == clock) 4390 return; 4391 4392 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4393 type, vic, mode->clock, clock); 4394 mode->clock = clock; 4395 } 4396 4397 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4398 { 4399 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4400 return false; 4401 4402 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4403 return false; 4404 4405 if (cea_db_payload_len(db) < 3) 4406 return false; 4407 4408 return true; 4409 } 4410 4411 static uint8_t eotf_supported(const u8 *edid_ext) 4412 { 4413 return edid_ext[2] & 4414 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4415 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4416 BIT(HDMI_EOTF_SMPTE_ST2084) | 4417 BIT(HDMI_EOTF_BT_2100_HLG)); 4418 } 4419 4420 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4421 { 4422 return edid_ext[3] & 4423 BIT(HDMI_STATIC_METADATA_TYPE1); 4424 } 4425 4426 static void 4427 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4428 { 4429 u16 len; 4430 4431 len = cea_db_payload_len(db); 4432 4433 connector->hdr_sink_metadata.hdmi_type1.eotf = 4434 eotf_supported(db); 4435 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4436 hdr_metadata_type(db); 4437 4438 if (len >= 4) 4439 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4440 if (len >= 5) 4441 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4442 if (len >= 6) 4443 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4444 } 4445 4446 static void 4447 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4448 { 4449 u8 len = cea_db_payload_len(db); 4450 4451 if (len >= 6 && (db[6] & (1 << 7))) 4452 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4453 if (len >= 8) { 4454 connector->latency_present[0] = db[8] >> 7; 4455 connector->latency_present[1] = (db[8] >> 6) & 1; 4456 } 4457 if (len >= 9) 4458 connector->video_latency[0] = db[9]; 4459 if (len >= 10) 4460 connector->audio_latency[0] = db[10]; 4461 if (len >= 11) 4462 connector->video_latency[1] = db[11]; 4463 if (len >= 12) 4464 connector->audio_latency[1] = db[12]; 4465 4466 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4467 "video latency %d %d, " 4468 "audio latency %d %d\n", 4469 connector->latency_present[0], 4470 connector->latency_present[1], 4471 connector->video_latency[0], 4472 connector->video_latency[1], 4473 connector->audio_latency[0], 4474 connector->audio_latency[1]); 4475 } 4476 4477 static void 4478 monitor_name(struct detailed_timing *t, void *data) 4479 { 4480 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4481 return; 4482 4483 *(u8 **)data = t->data.other_data.data.str.str; 4484 } 4485 4486 static int get_monitor_name(struct edid *edid, char name[13]) 4487 { 4488 char *edid_name = NULL; 4489 int mnl; 4490 4491 if (!edid || !name) 4492 return 0; 4493 4494 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4495 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4496 if (edid_name[mnl] == 0x0a) 4497 break; 4498 4499 name[mnl] = edid_name[mnl]; 4500 } 4501 4502 return mnl; 4503 } 4504 4505 /** 4506 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4507 * @edid: monitor EDID information 4508 * @name: pointer to a character array to hold the name of the monitor 4509 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4510 * 4511 */ 4512 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4513 { 4514 int name_length; 4515 char buf[13]; 4516 4517 if (bufsize <= 0) 4518 return; 4519 4520 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4521 memcpy(name, buf, name_length); 4522 name[name_length] = '\0'; 4523 } 4524 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4525 4526 static void clear_eld(struct drm_connector *connector) 4527 { 4528 memset(connector->eld, 0, sizeof(connector->eld)); 4529 4530 connector->latency_present[0] = false; 4531 connector->latency_present[1] = false; 4532 connector->video_latency[0] = 0; 4533 connector->audio_latency[0] = 0; 4534 connector->video_latency[1] = 0; 4535 connector->audio_latency[1] = 0; 4536 } 4537 4538 /* 4539 * drm_edid_to_eld - build ELD from EDID 4540 * @connector: connector corresponding to the HDMI/DP sink 4541 * @edid: EDID to parse 4542 * 4543 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4544 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4545 */ 4546 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4547 { 4548 uint8_t *eld = connector->eld; 4549 const u8 *cea; 4550 const u8 *db; 4551 int total_sad_count = 0; 4552 int mnl; 4553 int dbl; 4554 4555 clear_eld(connector); 4556 4557 if (!edid) 4558 return; 4559 4560 cea = drm_find_cea_extension(edid); 4561 if (!cea) { 4562 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4563 return; 4564 } 4565 4566 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4567 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4568 4569 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4570 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4571 4572 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4573 4574 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4575 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4576 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4577 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4578 4579 if (cea_revision(cea) >= 3) { 4580 int i, start, end; 4581 int sad_count; 4582 4583 if (cea_db_offsets(cea, &start, &end)) { 4584 start = 0; 4585 end = 0; 4586 } 4587 4588 for_each_cea_db(cea, i, start, end) { 4589 db = &cea[i]; 4590 dbl = cea_db_payload_len(db); 4591 4592 switch (cea_db_tag(db)) { 4593 case AUDIO_BLOCK: 4594 /* Audio Data Block, contains SADs */ 4595 sad_count = min(dbl / 3, 15 - total_sad_count); 4596 if (sad_count >= 1) 4597 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4598 &db[1], sad_count * 3); 4599 total_sad_count += sad_count; 4600 break; 4601 case SPEAKER_BLOCK: 4602 /* Speaker Allocation Data Block */ 4603 if (dbl >= 1) 4604 eld[DRM_ELD_SPEAKER] = db[1]; 4605 break; 4606 case VENDOR_BLOCK: 4607 /* HDMI Vendor-Specific Data Block */ 4608 if (cea_db_is_hdmi_vsdb(db)) 4609 drm_parse_hdmi_vsdb_audio(connector, db); 4610 break; 4611 default: 4612 break; 4613 } 4614 } 4615 } 4616 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4617 4618 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4619 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4620 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4621 else 4622 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4623 4624 eld[DRM_ELD_BASELINE_ELD_LEN] = 4625 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4626 4627 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4628 drm_eld_size(eld), total_sad_count); 4629 } 4630 4631 /** 4632 * drm_edid_to_sad - extracts SADs from EDID 4633 * @edid: EDID to parse 4634 * @sads: pointer that will be set to the extracted SADs 4635 * 4636 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4637 * 4638 * Note: The returned pointer needs to be freed using kfree(). 4639 * 4640 * Return: The number of found SADs or negative number on error. 4641 */ 4642 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4643 { 4644 int count = 0; 4645 int i, start, end, dbl; 4646 const u8 *cea; 4647 4648 cea = drm_find_cea_extension(edid); 4649 if (!cea) { 4650 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4651 return 0; 4652 } 4653 4654 if (cea_revision(cea) < 3) { 4655 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4656 return 0; 4657 } 4658 4659 if (cea_db_offsets(cea, &start, &end)) { 4660 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4661 return -EPROTO; 4662 } 4663 4664 for_each_cea_db(cea, i, start, end) { 4665 const u8 *db = &cea[i]; 4666 4667 if (cea_db_tag(db) == AUDIO_BLOCK) { 4668 int j; 4669 4670 dbl = cea_db_payload_len(db); 4671 4672 count = dbl / 3; /* SAD is 3B */ 4673 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4674 if (!*sads) 4675 return -ENOMEM; 4676 for (j = 0; j < count; j++) { 4677 const u8 *sad = &db[1 + j * 3]; 4678 4679 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4680 (*sads)[j].channels = sad[0] & 0x7; 4681 (*sads)[j].freq = sad[1] & 0x7F; 4682 (*sads)[j].byte2 = sad[2]; 4683 } 4684 break; 4685 } 4686 } 4687 4688 return count; 4689 } 4690 EXPORT_SYMBOL(drm_edid_to_sad); 4691 4692 /** 4693 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4694 * @edid: EDID to parse 4695 * @sadb: pointer to the speaker block 4696 * 4697 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4698 * 4699 * Note: The returned pointer needs to be freed using kfree(). 4700 * 4701 * Return: The number of found Speaker Allocation Blocks or negative number on 4702 * error. 4703 */ 4704 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4705 { 4706 int count = 0; 4707 int i, start, end, dbl; 4708 const u8 *cea; 4709 4710 cea = drm_find_cea_extension(edid); 4711 if (!cea) { 4712 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4713 return 0; 4714 } 4715 4716 if (cea_revision(cea) < 3) { 4717 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4718 return 0; 4719 } 4720 4721 if (cea_db_offsets(cea, &start, &end)) { 4722 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4723 return -EPROTO; 4724 } 4725 4726 for_each_cea_db(cea, i, start, end) { 4727 const u8 *db = &cea[i]; 4728 4729 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4730 dbl = cea_db_payload_len(db); 4731 4732 /* Speaker Allocation Data Block */ 4733 if (dbl == 3) { 4734 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4735 if (!*sadb) 4736 return -ENOMEM; 4737 count = dbl; 4738 break; 4739 } 4740 } 4741 } 4742 4743 return count; 4744 } 4745 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4746 4747 /** 4748 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4749 * @connector: connector associated with the HDMI/DP sink 4750 * @mode: the display mode 4751 * 4752 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4753 * the sink doesn't support audio or video. 4754 */ 4755 int drm_av_sync_delay(struct drm_connector *connector, 4756 const struct drm_display_mode *mode) 4757 { 4758 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4759 int a, v; 4760 4761 if (!connector->latency_present[0]) 4762 return 0; 4763 if (!connector->latency_present[1]) 4764 i = 0; 4765 4766 a = connector->audio_latency[i]; 4767 v = connector->video_latency[i]; 4768 4769 /* 4770 * HDMI/DP sink doesn't support audio or video? 4771 */ 4772 if (a == 255 || v == 255) 4773 return 0; 4774 4775 /* 4776 * Convert raw EDID values to millisecond. 4777 * Treat unknown latency as 0ms. 4778 */ 4779 if (a) 4780 a = min(2 * (a - 1), 500); 4781 if (v) 4782 v = min(2 * (v - 1), 500); 4783 4784 return max(v - a, 0); 4785 } 4786 EXPORT_SYMBOL(drm_av_sync_delay); 4787 4788 /** 4789 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4790 * @edid: monitor EDID information 4791 * 4792 * Parse the CEA extension according to CEA-861-B. 4793 * 4794 * Drivers that have added the modes parsed from EDID to drm_display_info 4795 * should use &drm_display_info.is_hdmi instead of calling this function. 4796 * 4797 * Return: True if the monitor is HDMI, false if not or unknown. 4798 */ 4799 bool drm_detect_hdmi_monitor(struct edid *edid) 4800 { 4801 const u8 *edid_ext; 4802 int i; 4803 int start_offset, end_offset; 4804 4805 edid_ext = drm_find_cea_extension(edid); 4806 if (!edid_ext) 4807 return false; 4808 4809 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4810 return false; 4811 4812 /* 4813 * Because HDMI identifier is in Vendor Specific Block, 4814 * search it from all data blocks of CEA extension. 4815 */ 4816 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4817 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4818 return true; 4819 } 4820 4821 return false; 4822 } 4823 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4824 4825 /** 4826 * drm_detect_monitor_audio - check monitor audio capability 4827 * @edid: EDID block to scan 4828 * 4829 * Monitor should have CEA extension block. 4830 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4831 * audio' only. If there is any audio extension block and supported 4832 * audio format, assume at least 'basic audio' support, even if 'basic 4833 * audio' is not defined in EDID. 4834 * 4835 * Return: True if the monitor supports audio, false otherwise. 4836 */ 4837 bool drm_detect_monitor_audio(struct edid *edid) 4838 { 4839 const u8 *edid_ext; 4840 int i, j; 4841 bool has_audio = false; 4842 int start_offset, end_offset; 4843 4844 edid_ext = drm_find_cea_extension(edid); 4845 if (!edid_ext) 4846 goto end; 4847 4848 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4849 4850 if (has_audio) { 4851 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4852 goto end; 4853 } 4854 4855 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4856 goto end; 4857 4858 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4859 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4860 has_audio = true; 4861 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4862 DRM_DEBUG_KMS("CEA audio format %d\n", 4863 (edid_ext[i + j] >> 3) & 0xf); 4864 goto end; 4865 } 4866 } 4867 end: 4868 return has_audio; 4869 } 4870 EXPORT_SYMBOL(drm_detect_monitor_audio); 4871 4872 4873 /** 4874 * drm_default_rgb_quant_range - default RGB quantization range 4875 * @mode: display mode 4876 * 4877 * Determine the default RGB quantization range for the mode, 4878 * as specified in CEA-861. 4879 * 4880 * Return: The default RGB quantization range for the mode 4881 */ 4882 enum hdmi_quantization_range 4883 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4884 { 4885 /* All CEA modes other than VIC 1 use limited quantization range. */ 4886 return drm_match_cea_mode(mode) > 1 ? 4887 HDMI_QUANTIZATION_RANGE_LIMITED : 4888 HDMI_QUANTIZATION_RANGE_FULL; 4889 } 4890 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4891 4892 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4893 { 4894 struct drm_display_info *info = &connector->display_info; 4895 4896 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4897 4898 if (db[2] & EDID_CEA_VCDB_QS) 4899 info->rgb_quant_range_selectable = true; 4900 } 4901 4902 static 4903 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 4904 { 4905 switch (max_frl_rate) { 4906 case 1: 4907 *max_lanes = 3; 4908 *max_rate_per_lane = 3; 4909 break; 4910 case 2: 4911 *max_lanes = 3; 4912 *max_rate_per_lane = 6; 4913 break; 4914 case 3: 4915 *max_lanes = 4; 4916 *max_rate_per_lane = 6; 4917 break; 4918 case 4: 4919 *max_lanes = 4; 4920 *max_rate_per_lane = 8; 4921 break; 4922 case 5: 4923 *max_lanes = 4; 4924 *max_rate_per_lane = 10; 4925 break; 4926 case 6: 4927 *max_lanes = 4; 4928 *max_rate_per_lane = 12; 4929 break; 4930 case 0: 4931 default: 4932 *max_lanes = 0; 4933 *max_rate_per_lane = 0; 4934 } 4935 } 4936 4937 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4938 const u8 *db) 4939 { 4940 u8 dc_mask; 4941 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4942 4943 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4944 hdmi->y420_dc_modes = dc_mask; 4945 } 4946 4947 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4948 const u8 *hf_vsdb) 4949 { 4950 struct drm_display_info *display = &connector->display_info; 4951 struct drm_hdmi_info *hdmi = &display->hdmi; 4952 4953 display->has_hdmi_infoframe = true; 4954 4955 if (hf_vsdb[6] & 0x80) { 4956 hdmi->scdc.supported = true; 4957 if (hf_vsdb[6] & 0x40) 4958 hdmi->scdc.read_request = true; 4959 } 4960 4961 /* 4962 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4963 * And as per the spec, three factors confirm this: 4964 * * Availability of a HF-VSDB block in EDID (check) 4965 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4966 * * SCDC support available (let's check) 4967 * Lets check it out. 4968 */ 4969 4970 if (hf_vsdb[5]) { 4971 /* max clock is 5000 KHz times block value */ 4972 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4973 struct drm_scdc *scdc = &hdmi->scdc; 4974 4975 if (max_tmds_clock > 340000) { 4976 display->max_tmds_clock = max_tmds_clock; 4977 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4978 display->max_tmds_clock); 4979 } 4980 4981 if (scdc->supported) { 4982 scdc->scrambling.supported = true; 4983 4984 /* Few sinks support scrambling for clocks < 340M */ 4985 if ((hf_vsdb[6] & 0x8)) 4986 scdc->scrambling.low_rates = true; 4987 } 4988 } 4989 4990 if (hf_vsdb[7]) { 4991 u8 max_frl_rate; 4992 u8 dsc_max_frl_rate; 4993 u8 dsc_max_slices; 4994 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 4995 4996 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 4997 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 4998 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 4999 &hdmi->max_frl_rate_per_lane); 5000 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 5001 5002 if (hdmi_dsc->v_1p2) { 5003 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 5004 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 5005 5006 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 5007 hdmi_dsc->bpc_supported = 16; 5008 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 5009 hdmi_dsc->bpc_supported = 12; 5010 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 5011 hdmi_dsc->bpc_supported = 10; 5012 else 5013 hdmi_dsc->bpc_supported = 0; 5014 5015 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5016 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5017 &hdmi_dsc->max_frl_rate_per_lane); 5018 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5019 5020 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 5021 switch (dsc_max_slices) { 5022 case 1: 5023 hdmi_dsc->max_slices = 1; 5024 hdmi_dsc->clk_per_slice = 340; 5025 break; 5026 case 2: 5027 hdmi_dsc->max_slices = 2; 5028 hdmi_dsc->clk_per_slice = 340; 5029 break; 5030 case 3: 5031 hdmi_dsc->max_slices = 4; 5032 hdmi_dsc->clk_per_slice = 340; 5033 break; 5034 case 4: 5035 hdmi_dsc->max_slices = 8; 5036 hdmi_dsc->clk_per_slice = 340; 5037 break; 5038 case 5: 5039 hdmi_dsc->max_slices = 8; 5040 hdmi_dsc->clk_per_slice = 400; 5041 break; 5042 case 6: 5043 hdmi_dsc->max_slices = 12; 5044 hdmi_dsc->clk_per_slice = 400; 5045 break; 5046 case 7: 5047 hdmi_dsc->max_slices = 16; 5048 hdmi_dsc->clk_per_slice = 400; 5049 break; 5050 case 0: 5051 default: 5052 hdmi_dsc->max_slices = 0; 5053 hdmi_dsc->clk_per_slice = 0; 5054 } 5055 } 5056 } 5057 5058 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 5059 } 5060 5061 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5062 const u8 *hdmi) 5063 { 5064 struct drm_display_info *info = &connector->display_info; 5065 unsigned int dc_bpc = 0; 5066 5067 /* HDMI supports at least 8 bpc */ 5068 info->bpc = 8; 5069 5070 if (cea_db_payload_len(hdmi) < 6) 5071 return; 5072 5073 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5074 dc_bpc = 10; 5075 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 5076 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5077 connector->name); 5078 } 5079 5080 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5081 dc_bpc = 12; 5082 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 5083 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5084 connector->name); 5085 } 5086 5087 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5088 dc_bpc = 16; 5089 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 5090 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5091 connector->name); 5092 } 5093 5094 if (dc_bpc == 0) { 5095 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5096 connector->name); 5097 return; 5098 } 5099 5100 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5101 connector->name, dc_bpc); 5102 info->bpc = dc_bpc; 5103 5104 /* 5105 * Deep color support mandates RGB444 support for all video 5106 * modes and forbids YCRCB422 support for all video modes per 5107 * HDMI 1.3 spec. 5108 */ 5109 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5110 5111 /* YCRCB444 is optional according to spec. */ 5112 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5113 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5114 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5115 connector->name); 5116 } 5117 5118 /* 5119 * Spec says that if any deep color mode is supported at all, 5120 * then deep color 36 bit must be supported. 5121 */ 5122 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5123 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5124 connector->name); 5125 } 5126 } 5127 5128 static void 5129 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5130 { 5131 struct drm_display_info *info = &connector->display_info; 5132 u8 len = cea_db_payload_len(db); 5133 5134 info->is_hdmi = true; 5135 5136 if (len >= 6) 5137 info->dvi_dual = db[6] & 1; 5138 if (len >= 7) 5139 info->max_tmds_clock = db[7] * 5000; 5140 5141 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5142 "max TMDS clock %d kHz\n", 5143 info->dvi_dual, 5144 info->max_tmds_clock); 5145 5146 drm_parse_hdmi_deep_color_info(connector, db); 5147 } 5148 5149 static void drm_parse_cea_ext(struct drm_connector *connector, 5150 const struct edid *edid) 5151 { 5152 struct drm_display_info *info = &connector->display_info; 5153 const u8 *edid_ext; 5154 int i, start, end; 5155 5156 edid_ext = drm_find_cea_extension(edid); 5157 if (!edid_ext) 5158 return; 5159 5160 info->cea_rev = edid_ext[1]; 5161 5162 /* The existence of a CEA block should imply RGB support */ 5163 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5164 if (edid_ext[3] & EDID_CEA_YCRCB444) 5165 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5166 if (edid_ext[3] & EDID_CEA_YCRCB422) 5167 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5168 5169 if (cea_db_offsets(edid_ext, &start, &end)) 5170 return; 5171 5172 for_each_cea_db(edid_ext, i, start, end) { 5173 const u8 *db = &edid_ext[i]; 5174 5175 if (cea_db_is_hdmi_vsdb(db)) 5176 drm_parse_hdmi_vsdb_video(connector, db); 5177 if (cea_db_is_hdmi_forum_vsdb(db)) 5178 drm_parse_hdmi_forum_vsdb(connector, db); 5179 if (cea_db_is_y420cmdb(db)) 5180 drm_parse_y420cmdb_bitmap(connector, db); 5181 if (cea_db_is_vcdb(db)) 5182 drm_parse_vcdb(connector, db); 5183 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5184 drm_parse_hdr_metadata_block(connector, db); 5185 } 5186 } 5187 5188 static 5189 void get_monitor_range(struct detailed_timing *timing, 5190 void *info_monitor_range) 5191 { 5192 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5193 const struct detailed_non_pixel *data = &timing->data.other_data; 5194 const struct detailed_data_monitor_range *range = &data->data.range; 5195 5196 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 5197 return; 5198 5199 /* 5200 * Check for flag range limits only. If flag == 1 then 5201 * no additional timing information provided. 5202 * Default GTF, GTF Secondary curve and CVT are not 5203 * supported 5204 */ 5205 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5206 return; 5207 5208 monitor_range->min_vfreq = range->min_vfreq; 5209 monitor_range->max_vfreq = range->max_vfreq; 5210 } 5211 5212 static 5213 void drm_get_monitor_range(struct drm_connector *connector, 5214 const struct edid *edid) 5215 { 5216 struct drm_display_info *info = &connector->display_info; 5217 5218 if (!version_greater(edid, 1, 1)) 5219 return; 5220 5221 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 5222 &info->monitor_range); 5223 5224 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5225 info->monitor_range.min_vfreq, 5226 info->monitor_range.max_vfreq); 5227 } 5228 5229 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5230 * all of the values which would have been set from EDID 5231 */ 5232 void 5233 drm_reset_display_info(struct drm_connector *connector) 5234 { 5235 struct drm_display_info *info = &connector->display_info; 5236 5237 info->width_mm = 0; 5238 info->height_mm = 0; 5239 5240 info->bpc = 0; 5241 info->color_formats = 0; 5242 info->cea_rev = 0; 5243 info->max_tmds_clock = 0; 5244 info->dvi_dual = false; 5245 info->is_hdmi = false; 5246 info->has_hdmi_infoframe = false; 5247 info->rgb_quant_range_selectable = false; 5248 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5249 5250 info->non_desktop = 0; 5251 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5252 } 5253 5254 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5255 { 5256 struct drm_display_info *info = &connector->display_info; 5257 5258 u32 quirks = edid_get_quirks(edid); 5259 5260 drm_reset_display_info(connector); 5261 5262 info->width_mm = edid->width_cm * 10; 5263 info->height_mm = edid->height_cm * 10; 5264 5265 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5266 5267 drm_get_monitor_range(connector, edid); 5268 5269 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5270 5271 if (edid->revision < 3) 5272 return quirks; 5273 5274 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5275 return quirks; 5276 5277 drm_parse_cea_ext(connector, edid); 5278 5279 /* 5280 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5281 * 5282 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5283 * tells us to assume 8 bpc color depth if the EDID doesn't have 5284 * extensions which tell otherwise. 5285 */ 5286 if (info->bpc == 0 && edid->revision == 3 && 5287 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5288 info->bpc = 8; 5289 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5290 connector->name, info->bpc); 5291 } 5292 5293 /* Only defined for 1.4 with digital displays */ 5294 if (edid->revision < 4) 5295 return quirks; 5296 5297 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5298 case DRM_EDID_DIGITAL_DEPTH_6: 5299 info->bpc = 6; 5300 break; 5301 case DRM_EDID_DIGITAL_DEPTH_8: 5302 info->bpc = 8; 5303 break; 5304 case DRM_EDID_DIGITAL_DEPTH_10: 5305 info->bpc = 10; 5306 break; 5307 case DRM_EDID_DIGITAL_DEPTH_12: 5308 info->bpc = 12; 5309 break; 5310 case DRM_EDID_DIGITAL_DEPTH_14: 5311 info->bpc = 14; 5312 break; 5313 case DRM_EDID_DIGITAL_DEPTH_16: 5314 info->bpc = 16; 5315 break; 5316 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5317 default: 5318 info->bpc = 0; 5319 break; 5320 } 5321 5322 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5323 connector->name, info->bpc); 5324 5325 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5326 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5327 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5328 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5329 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5330 return quirks; 5331 } 5332 5333 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5334 struct displayid_detailed_timings_1 *timings) 5335 { 5336 struct drm_display_mode *mode; 5337 unsigned pixel_clock = (timings->pixel_clock[0] | 5338 (timings->pixel_clock[1] << 8) | 5339 (timings->pixel_clock[2] << 16)) + 1; 5340 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5341 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5342 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5343 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5344 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5345 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5346 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5347 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5348 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5349 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5350 5351 mode = drm_mode_create(dev); 5352 if (!mode) 5353 return NULL; 5354 5355 mode->clock = pixel_clock * 10; 5356 mode->hdisplay = hactive; 5357 mode->hsync_start = mode->hdisplay + hsync; 5358 mode->hsync_end = mode->hsync_start + hsync_width; 5359 mode->htotal = mode->hdisplay + hblank; 5360 5361 mode->vdisplay = vactive; 5362 mode->vsync_start = mode->vdisplay + vsync; 5363 mode->vsync_end = mode->vsync_start + vsync_width; 5364 mode->vtotal = mode->vdisplay + vblank; 5365 5366 mode->flags = 0; 5367 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5368 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5369 mode->type = DRM_MODE_TYPE_DRIVER; 5370 5371 if (timings->flags & 0x80) 5372 mode->type |= DRM_MODE_TYPE_PREFERRED; 5373 drm_mode_set_name(mode); 5374 5375 return mode; 5376 } 5377 5378 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5379 const struct displayid_block *block) 5380 { 5381 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5382 int i; 5383 int num_timings; 5384 struct drm_display_mode *newmode; 5385 int num_modes = 0; 5386 /* blocks must be multiple of 20 bytes length */ 5387 if (block->num_bytes % 20) 5388 return 0; 5389 5390 num_timings = block->num_bytes / 20; 5391 for (i = 0; i < num_timings; i++) { 5392 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5393 5394 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5395 if (!newmode) 5396 continue; 5397 5398 drm_mode_probed_add(connector, newmode); 5399 num_modes++; 5400 } 5401 return num_modes; 5402 } 5403 5404 static int add_displayid_detailed_modes(struct drm_connector *connector, 5405 struct edid *edid) 5406 { 5407 const struct displayid_block *block; 5408 struct displayid_iter iter; 5409 int num_modes = 0; 5410 5411 displayid_iter_edid_begin(edid, &iter); 5412 displayid_iter_for_each(block, &iter) { 5413 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING) 5414 num_modes += add_displayid_detailed_1_modes(connector, block); 5415 } 5416 displayid_iter_end(&iter); 5417 5418 return num_modes; 5419 } 5420 5421 /** 5422 * drm_add_edid_modes - add modes from EDID data, if available 5423 * @connector: connector we're probing 5424 * @edid: EDID data 5425 * 5426 * Add the specified modes to the connector's mode list. Also fills out the 5427 * &drm_display_info structure and ELD in @connector with any information which 5428 * can be derived from the edid. 5429 * 5430 * Return: The number of modes added or 0 if we couldn't find any. 5431 */ 5432 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5433 { 5434 int num_modes = 0; 5435 u32 quirks; 5436 5437 if (edid == NULL) { 5438 clear_eld(connector); 5439 return 0; 5440 } 5441 if (!drm_edid_is_valid(edid)) { 5442 clear_eld(connector); 5443 drm_warn(connector->dev, "%s: EDID invalid.\n", 5444 connector->name); 5445 return 0; 5446 } 5447 5448 drm_edid_to_eld(connector, edid); 5449 5450 /* 5451 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5452 * To avoid multiple parsing of same block, lets parse that map 5453 * from sink info, before parsing CEA modes. 5454 */ 5455 quirks = drm_add_display_info(connector, edid); 5456 5457 /* 5458 * EDID spec says modes should be preferred in this order: 5459 * - preferred detailed mode 5460 * - other detailed modes from base block 5461 * - detailed modes from extension blocks 5462 * - CVT 3-byte code modes 5463 * - standard timing codes 5464 * - established timing codes 5465 * - modes inferred from GTF or CVT range information 5466 * 5467 * We get this pretty much right. 5468 * 5469 * XXX order for additional mode types in extension blocks? 5470 */ 5471 num_modes += add_detailed_modes(connector, edid, quirks); 5472 num_modes += add_cvt_modes(connector, edid); 5473 num_modes += add_standard_modes(connector, edid); 5474 num_modes += add_established_modes(connector, edid); 5475 num_modes += add_cea_modes(connector, edid); 5476 num_modes += add_alternate_cea_modes(connector, edid); 5477 num_modes += add_displayid_detailed_modes(connector, edid); 5478 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5479 num_modes += add_inferred_modes(connector, edid); 5480 5481 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5482 edid_fixup_preferred(connector, quirks); 5483 5484 if (quirks & EDID_QUIRK_FORCE_6BPC) 5485 connector->display_info.bpc = 6; 5486 5487 if (quirks & EDID_QUIRK_FORCE_8BPC) 5488 connector->display_info.bpc = 8; 5489 5490 if (quirks & EDID_QUIRK_FORCE_10BPC) 5491 connector->display_info.bpc = 10; 5492 5493 if (quirks & EDID_QUIRK_FORCE_12BPC) 5494 connector->display_info.bpc = 12; 5495 5496 return num_modes; 5497 } 5498 EXPORT_SYMBOL(drm_add_edid_modes); 5499 5500 /** 5501 * drm_add_modes_noedid - add modes for the connectors without EDID 5502 * @connector: connector we're probing 5503 * @hdisplay: the horizontal display limit 5504 * @vdisplay: the vertical display limit 5505 * 5506 * Add the specified modes to the connector's mode list. Only when the 5507 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5508 * 5509 * Return: The number of modes added or 0 if we couldn't find any. 5510 */ 5511 int drm_add_modes_noedid(struct drm_connector *connector, 5512 int hdisplay, int vdisplay) 5513 { 5514 int i, count, num_modes = 0; 5515 struct drm_display_mode *mode; 5516 struct drm_device *dev = connector->dev; 5517 5518 count = ARRAY_SIZE(drm_dmt_modes); 5519 if (hdisplay < 0) 5520 hdisplay = 0; 5521 if (vdisplay < 0) 5522 vdisplay = 0; 5523 5524 for (i = 0; i < count; i++) { 5525 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5526 5527 if (hdisplay && vdisplay) { 5528 /* 5529 * Only when two are valid, they will be used to check 5530 * whether the mode should be added to the mode list of 5531 * the connector. 5532 */ 5533 if (ptr->hdisplay > hdisplay || 5534 ptr->vdisplay > vdisplay) 5535 continue; 5536 } 5537 if (drm_mode_vrefresh(ptr) > 61) 5538 continue; 5539 mode = drm_mode_duplicate(dev, ptr); 5540 if (mode) { 5541 drm_mode_probed_add(connector, mode); 5542 num_modes++; 5543 } 5544 } 5545 return num_modes; 5546 } 5547 EXPORT_SYMBOL(drm_add_modes_noedid); 5548 5549 /** 5550 * drm_set_preferred_mode - Sets the preferred mode of a connector 5551 * @connector: connector whose mode list should be processed 5552 * @hpref: horizontal resolution of preferred mode 5553 * @vpref: vertical resolution of preferred mode 5554 * 5555 * Marks a mode as preferred if it matches the resolution specified by @hpref 5556 * and @vpref. 5557 */ 5558 void drm_set_preferred_mode(struct drm_connector *connector, 5559 int hpref, int vpref) 5560 { 5561 struct drm_display_mode *mode; 5562 5563 list_for_each_entry(mode, &connector->probed_modes, head) { 5564 if (mode->hdisplay == hpref && 5565 mode->vdisplay == vpref) 5566 mode->type |= DRM_MODE_TYPE_PREFERRED; 5567 } 5568 } 5569 EXPORT_SYMBOL(drm_set_preferred_mode); 5570 5571 static bool is_hdmi2_sink(const struct drm_connector *connector) 5572 { 5573 /* 5574 * FIXME: sil-sii8620 doesn't have a connector around when 5575 * we need one, so we have to be prepared for a NULL connector. 5576 */ 5577 if (!connector) 5578 return true; 5579 5580 return connector->display_info.hdmi.scdc.supported || 5581 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5582 } 5583 5584 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5585 { 5586 return sink_eotf & BIT(output_eotf); 5587 } 5588 5589 /** 5590 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5591 * HDR metadata from userspace 5592 * @frame: HDMI DRM infoframe 5593 * @conn_state: Connector state containing HDR metadata 5594 * 5595 * Return: 0 on success or a negative error code on failure. 5596 */ 5597 int 5598 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5599 const struct drm_connector_state *conn_state) 5600 { 5601 struct drm_connector *connector; 5602 struct hdr_output_metadata *hdr_metadata; 5603 int err; 5604 5605 if (!frame || !conn_state) 5606 return -EINVAL; 5607 5608 connector = conn_state->connector; 5609 5610 if (!conn_state->hdr_output_metadata) 5611 return -EINVAL; 5612 5613 hdr_metadata = conn_state->hdr_output_metadata->data; 5614 5615 if (!hdr_metadata || !connector) 5616 return -EINVAL; 5617 5618 /* Sink EOTF is Bit map while infoframe is absolute values */ 5619 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5620 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5621 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5622 return -EINVAL; 5623 } 5624 5625 err = hdmi_drm_infoframe_init(frame); 5626 if (err < 0) 5627 return err; 5628 5629 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5630 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5631 5632 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5633 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5634 BUILD_BUG_ON(sizeof(frame->white_point) != 5635 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5636 5637 memcpy(&frame->display_primaries, 5638 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5639 sizeof(frame->display_primaries)); 5640 5641 memcpy(&frame->white_point, 5642 &hdr_metadata->hdmi_metadata_type1.white_point, 5643 sizeof(frame->white_point)); 5644 5645 frame->max_display_mastering_luminance = 5646 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5647 frame->min_display_mastering_luminance = 5648 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5649 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5650 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5651 5652 return 0; 5653 } 5654 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5655 5656 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5657 const struct drm_display_mode *mode) 5658 { 5659 bool has_hdmi_infoframe = connector ? 5660 connector->display_info.has_hdmi_infoframe : false; 5661 5662 if (!has_hdmi_infoframe) 5663 return 0; 5664 5665 /* No HDMI VIC when signalling 3D video format */ 5666 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5667 return 0; 5668 5669 return drm_match_hdmi_mode(mode); 5670 } 5671 5672 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5673 const struct drm_display_mode *mode) 5674 { 5675 u8 vic; 5676 5677 /* 5678 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5679 * we should send its VIC in vendor infoframes, else send the 5680 * VIC in AVI infoframes. Lets check if this mode is present in 5681 * HDMI 1.4b 4K modes 5682 */ 5683 if (drm_mode_hdmi_vic(connector, mode)) 5684 return 0; 5685 5686 vic = drm_match_cea_mode(mode); 5687 5688 /* 5689 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5690 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5691 * have to make sure we dont break HDMI 1.4 sinks. 5692 */ 5693 if (!is_hdmi2_sink(connector) && vic > 64) 5694 return 0; 5695 5696 return vic; 5697 } 5698 5699 /** 5700 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5701 * data from a DRM display mode 5702 * @frame: HDMI AVI infoframe 5703 * @connector: the connector 5704 * @mode: DRM display mode 5705 * 5706 * Return: 0 on success or a negative error code on failure. 5707 */ 5708 int 5709 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5710 const struct drm_connector *connector, 5711 const struct drm_display_mode *mode) 5712 { 5713 enum hdmi_picture_aspect picture_aspect; 5714 u8 vic, hdmi_vic; 5715 5716 if (!frame || !mode) 5717 return -EINVAL; 5718 5719 hdmi_avi_infoframe_init(frame); 5720 5721 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5722 frame->pixel_repeat = 1; 5723 5724 vic = drm_mode_cea_vic(connector, mode); 5725 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5726 5727 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5728 5729 /* 5730 * As some drivers don't support atomic, we can't use connector state. 5731 * So just initialize the frame with default values, just the same way 5732 * as it's done with other properties here. 5733 */ 5734 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5735 frame->itc = 0; 5736 5737 /* 5738 * Populate picture aspect ratio from either 5739 * user input (if specified) or from the CEA/HDMI mode lists. 5740 */ 5741 picture_aspect = mode->picture_aspect_ratio; 5742 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5743 if (vic) 5744 picture_aspect = drm_get_cea_aspect_ratio(vic); 5745 else if (hdmi_vic) 5746 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5747 } 5748 5749 /* 5750 * The infoframe can't convey anything but none, 4:3 5751 * and 16:9, so if the user has asked for anything else 5752 * we can only satisfy it by specifying the right VIC. 5753 */ 5754 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5755 if (vic) { 5756 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5757 return -EINVAL; 5758 } else if (hdmi_vic) { 5759 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5760 return -EINVAL; 5761 } else { 5762 return -EINVAL; 5763 } 5764 5765 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5766 } 5767 5768 frame->video_code = vic; 5769 frame->picture_aspect = picture_aspect; 5770 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5771 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5772 5773 return 0; 5774 } 5775 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5776 5777 /* HDMI Colorspace Spec Definitions */ 5778 #define FULL_COLORIMETRY_MASK 0x1FF 5779 #define NORMAL_COLORIMETRY_MASK 0x3 5780 #define EXTENDED_COLORIMETRY_MASK 0x7 5781 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5782 5783 #define C(x) ((x) << 0) 5784 #define EC(x) ((x) << 2) 5785 #define ACE(x) ((x) << 5) 5786 5787 #define HDMI_COLORIMETRY_NO_DATA 0x0 5788 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5789 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5790 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5791 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5792 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5793 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5794 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5795 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5796 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5797 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5798 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5799 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5800 5801 static const u32 hdmi_colorimetry_val[] = { 5802 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5803 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5804 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5805 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5806 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5807 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5808 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5809 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5810 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5811 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5812 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5813 }; 5814 5815 #undef C 5816 #undef EC 5817 #undef ACE 5818 5819 /** 5820 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5821 * colorspace information 5822 * @frame: HDMI AVI infoframe 5823 * @conn_state: connector state 5824 */ 5825 void 5826 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5827 const struct drm_connector_state *conn_state) 5828 { 5829 u32 colorimetry_val; 5830 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5831 5832 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5833 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5834 else 5835 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5836 5837 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5838 /* 5839 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5840 * structure and extend it in drivers/video/hdmi 5841 */ 5842 frame->extended_colorimetry = (colorimetry_val >> 2) & 5843 EXTENDED_COLORIMETRY_MASK; 5844 } 5845 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5846 5847 /** 5848 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5849 * quantization range information 5850 * @frame: HDMI AVI infoframe 5851 * @connector: the connector 5852 * @mode: DRM display mode 5853 * @rgb_quant_range: RGB quantization range (Q) 5854 */ 5855 void 5856 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5857 const struct drm_connector *connector, 5858 const struct drm_display_mode *mode, 5859 enum hdmi_quantization_range rgb_quant_range) 5860 { 5861 const struct drm_display_info *info = &connector->display_info; 5862 5863 /* 5864 * CEA-861: 5865 * "A Source shall not send a non-zero Q value that does not correspond 5866 * to the default RGB Quantization Range for the transmitted Picture 5867 * unless the Sink indicates support for the Q bit in a Video 5868 * Capabilities Data Block." 5869 * 5870 * HDMI 2.0 recommends sending non-zero Q when it does match the 5871 * default RGB quantization range for the mode, even when QS=0. 5872 */ 5873 if (info->rgb_quant_range_selectable || 5874 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5875 frame->quantization_range = rgb_quant_range; 5876 else 5877 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5878 5879 /* 5880 * CEA-861-F: 5881 * "When transmitting any RGB colorimetry, the Source should set the 5882 * YQ-field to match the RGB Quantization Range being transmitted 5883 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5884 * set YQ=1) and the Sink shall ignore the YQ-field." 5885 * 5886 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5887 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5888 * good way to tell which version of CEA-861 the sink supports, so 5889 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5890 * on on CEA-861-F. 5891 */ 5892 if (!is_hdmi2_sink(connector) || 5893 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5894 frame->ycc_quantization_range = 5895 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5896 else 5897 frame->ycc_quantization_range = 5898 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5899 } 5900 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5901 5902 /** 5903 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5904 * bar information 5905 * @frame: HDMI AVI infoframe 5906 * @conn_state: connector state 5907 */ 5908 void 5909 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5910 const struct drm_connector_state *conn_state) 5911 { 5912 frame->right_bar = conn_state->tv.margins.right; 5913 frame->left_bar = conn_state->tv.margins.left; 5914 frame->top_bar = conn_state->tv.margins.top; 5915 frame->bottom_bar = conn_state->tv.margins.bottom; 5916 } 5917 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5918 5919 static enum hdmi_3d_structure 5920 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5921 { 5922 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5923 5924 switch (layout) { 5925 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5926 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5927 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5928 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5929 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5930 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5931 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5932 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5933 case DRM_MODE_FLAG_3D_L_DEPTH: 5934 return HDMI_3D_STRUCTURE_L_DEPTH; 5935 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5936 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5937 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5938 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5939 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5940 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5941 default: 5942 return HDMI_3D_STRUCTURE_INVALID; 5943 } 5944 } 5945 5946 /** 5947 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5948 * data from a DRM display mode 5949 * @frame: HDMI vendor infoframe 5950 * @connector: the connector 5951 * @mode: DRM display mode 5952 * 5953 * Note that there's is a need to send HDMI vendor infoframes only when using a 5954 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5955 * function will return -EINVAL, error that can be safely ignored. 5956 * 5957 * Return: 0 on success or a negative error code on failure. 5958 */ 5959 int 5960 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5961 const struct drm_connector *connector, 5962 const struct drm_display_mode *mode) 5963 { 5964 /* 5965 * FIXME: sil-sii8620 doesn't have a connector around when 5966 * we need one, so we have to be prepared for a NULL connector. 5967 */ 5968 bool has_hdmi_infoframe = connector ? 5969 connector->display_info.has_hdmi_infoframe : false; 5970 int err; 5971 5972 if (!frame || !mode) 5973 return -EINVAL; 5974 5975 if (!has_hdmi_infoframe) 5976 return -EINVAL; 5977 5978 err = hdmi_vendor_infoframe_init(frame); 5979 if (err < 0) 5980 return err; 5981 5982 /* 5983 * Even if it's not absolutely necessary to send the infoframe 5984 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5985 * know that the sink can handle it. This is based on a 5986 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5987 * have trouble realizing that they should switch from 3D to 2D 5988 * mode if the source simply stops sending the infoframe when 5989 * it wants to switch from 3D to 2D. 5990 */ 5991 frame->vic = drm_mode_hdmi_vic(connector, mode); 5992 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5993 5994 return 0; 5995 } 5996 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5997 5998 static void drm_parse_tiled_block(struct drm_connector *connector, 5999 const struct displayid_block *block) 6000 { 6001 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6002 u16 w, h; 6003 u8 tile_v_loc, tile_h_loc; 6004 u8 num_v_tile, num_h_tile; 6005 struct drm_tile_group *tg; 6006 6007 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6008 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6009 6010 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6011 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6012 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6013 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6014 6015 connector->has_tile = true; 6016 if (tile->tile_cap & 0x80) 6017 connector->tile_is_single_monitor = true; 6018 6019 connector->num_h_tile = num_h_tile + 1; 6020 connector->num_v_tile = num_v_tile + 1; 6021 connector->tile_h_loc = tile_h_loc; 6022 connector->tile_v_loc = tile_v_loc; 6023 connector->tile_h_size = w + 1; 6024 connector->tile_v_size = h + 1; 6025 6026 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6027 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6028 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6029 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6030 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6031 6032 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6033 if (!tg) 6034 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6035 if (!tg) 6036 return; 6037 6038 if (connector->tile_group != tg) { 6039 /* if we haven't got a pointer, 6040 take the reference, drop ref to old tile group */ 6041 if (connector->tile_group) 6042 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6043 connector->tile_group = tg; 6044 } else { 6045 /* if same tile group, then release the ref we just took. */ 6046 drm_mode_put_tile_group(connector->dev, tg); 6047 } 6048 } 6049 6050 void drm_update_tile_info(struct drm_connector *connector, 6051 const struct edid *edid) 6052 { 6053 const struct displayid_block *block; 6054 struct displayid_iter iter; 6055 6056 connector->has_tile = false; 6057 6058 displayid_iter_edid_begin(edid, &iter); 6059 displayid_iter_for_each(block, &iter) { 6060 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6061 drm_parse_tiled_block(connector, block); 6062 } 6063 displayid_iter_end(&iter); 6064 6065 if (!connector->has_tile && connector->tile_group) { 6066 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6067 connector->tile_group = NULL; 6068 } 6069 } 6070