1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 91 #define MICROSOFT_IEEE_OUI 0xca125c 92 93 struct detailed_mode_closure { 94 struct drm_connector *connector; 95 const struct drm_edid *drm_edid; 96 bool preferred; 97 u32 quirks; 98 int modes; 99 }; 100 101 #define LEVEL_DMT 0 102 #define LEVEL_GTF 1 103 #define LEVEL_GTF2 2 104 #define LEVEL_CVT 3 105 106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 107 { \ 108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 109 product_id), \ 110 .quirks = _quirks \ 111 } 112 113 static const struct edid_quirk { 114 u32 panel_id; 115 u32 quirks; 116 } edid_quirk_list[] = { 117 /* Acer AL1706 */ 118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 119 /* Acer F51 */ 120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 121 122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 124 125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 127 128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 130 131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 133 134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 136 137 /* Belinea 10 15 55 */ 138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 140 141 /* Envision Peripherals, Inc. EN-7100e */ 142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 143 /* Envision EN2028 */ 144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 145 146 /* Funai Electronics PM36B */ 147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 148 EDID_QUIRK_DETAILED_IN_CM), 149 150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 152 153 /* LG Philips LCD LP154W01-A5 */ 154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 156 157 /* Samsung SyncMaster 205BW. Note: irony */ 158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 159 /* Samsung SyncMaster 22[5-6]BW */ 160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 162 163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 165 166 /* ViewSonic VA2026w */ 167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 168 169 /* Medion MD 30217 PG */ 170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 171 172 /* Lenovo G50 */ 173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 174 175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 177 178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 180 181 /* Valve Index Headset */ 182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 199 200 /* HTC Vive and Vive Pro VR Headsets */ 201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 203 204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 209 210 /* Windows Mixed Reality Headsets */ 211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 217 218 /* Sony PlayStation VR Headset */ 219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 220 221 /* Sensics VR Headsets */ 222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 223 224 /* OSVR HDK and HDK2 VR Headsets */ 225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 226 }; 227 228 /* 229 * Autogenerated from the DMT spec. 230 * This table is copied from xfree86/modes/xf86EdidModes.c. 231 */ 232 static const struct drm_display_mode drm_dmt_modes[] = { 233 /* 0x01 - 640x350@85Hz */ 234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 235 736, 832, 0, 350, 382, 385, 445, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 0x02 - 640x400@85Hz */ 238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 239 736, 832, 0, 400, 401, 404, 445, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 0x03 - 720x400@85Hz */ 242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 243 828, 936, 0, 400, 401, 404, 446, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 0x04 - 640x480@60Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 247 752, 800, 0, 480, 490, 492, 525, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x05 - 640x480@72Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 251 704, 832, 0, 480, 489, 492, 520, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x06 - 640x480@75Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 255 720, 840, 0, 480, 481, 484, 500, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x07 - 640x480@85Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 259 752, 832, 0, 480, 481, 484, 509, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x08 - 800x600@56Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 263 896, 1024, 0, 600, 601, 603, 625, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x09 - 800x600@60Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 267 968, 1056, 0, 600, 601, 605, 628, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0a - 800x600@72Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 271 976, 1040, 0, 600, 637, 643, 666, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0b - 800x600@75Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 275 896, 1056, 0, 600, 601, 604, 625, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0c - 800x600@85Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 279 896, 1048, 0, 600, 601, 604, 631, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0d - 800x600@120Hz RB */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 283 880, 960, 0, 600, 603, 607, 636, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 285 /* 0x0e - 848x480@60Hz */ 286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 287 976, 1088, 0, 480, 486, 494, 517, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0f - 1024x768@43Hz, interlace */ 290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 291 1208, 1264, 0, 768, 768, 776, 817, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 293 DRM_MODE_FLAG_INTERLACE) }, 294 /* 0x10 - 1024x768@60Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 296 1184, 1344, 0, 768, 771, 777, 806, 0, 297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 298 /* 0x11 - 1024x768@70Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 300 1184, 1328, 0, 768, 771, 777, 806, 0, 301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 302 /* 0x12 - 1024x768@75Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 304 1136, 1312, 0, 768, 769, 772, 800, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x13 - 1024x768@85Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 308 1168, 1376, 0, 768, 769, 772, 808, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x14 - 1024x768@120Hz RB */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 312 1104, 1184, 0, 768, 771, 775, 813, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x15 - 1152x864@75Hz */ 315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 316 1344, 1600, 0, 864, 865, 868, 900, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x55 - 1280x720@60Hz */ 319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 320 1430, 1650, 0, 720, 725, 730, 750, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x16 - 1280x768@60Hz RB */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 324 1360, 1440, 0, 768, 771, 778, 790, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 326 /* 0x17 - 1280x768@60Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 328 1472, 1664, 0, 768, 771, 778, 798, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x18 - 1280x768@75Hz */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 332 1488, 1696, 0, 768, 771, 778, 805, 0, 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 334 /* 0x19 - 1280x768@85Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 336 1496, 1712, 0, 768, 771, 778, 809, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x1a - 1280x768@120Hz RB */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 340 1360, 1440, 0, 768, 771, 778, 813, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 342 /* 0x1b - 1280x800@60Hz RB */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 344 1360, 1440, 0, 800, 803, 809, 823, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 346 /* 0x1c - 1280x800@60Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 348 1480, 1680, 0, 800, 803, 809, 831, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1d - 1280x800@75Hz */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 352 1488, 1696, 0, 800, 803, 809, 838, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x1e - 1280x800@85Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 356 1496, 1712, 0, 800, 803, 809, 843, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1f - 1280x800@120Hz RB */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 360 1360, 1440, 0, 800, 803, 809, 847, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x20 - 1280x960@60Hz */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 364 1488, 1800, 0, 960, 961, 964, 1000, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x21 - 1280x960@85Hz */ 367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 368 1504, 1728, 0, 960, 961, 964, 1011, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x22 - 1280x960@120Hz RB */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 372 1360, 1440, 0, 960, 963, 967, 1017, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 374 /* 0x23 - 1280x1024@60Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x24 - 1280x1024@75Hz */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x25 - 1280x1024@85Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x26 - 1280x1024@120Hz RB */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x27 - 1360x768@60Hz */ 391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 392 1536, 1792, 0, 768, 771, 777, 795, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x28 - 1360x768@120Hz RB */ 395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 396 1440, 1520, 0, 768, 771, 776, 813, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x51 - 1366x768@60Hz */ 399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 400 1579, 1792, 0, 768, 771, 774, 798, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x56 - 1366x768@60Hz */ 403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 404 1436, 1500, 0, 768, 769, 772, 800, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x29 - 1400x1050@60Hz RB */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 410 /* 0x2a - 1400x1050@60Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2b - 1400x1050@75Hz */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x2c - 1400x1050@85Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2d - 1400x1050@120Hz RB */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 426 /* 0x2e - 1440x900@60Hz RB */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 428 1520, 1600, 0, 900, 903, 909, 926, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 430 /* 0x2f - 1440x900@60Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 432 1672, 1904, 0, 900, 903, 909, 934, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x30 - 1440x900@75Hz */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 436 1688, 1936, 0, 900, 903, 909, 942, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x31 - 1440x900@85Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 440 1696, 1952, 0, 900, 903, 909, 948, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x32 - 1440x900@120Hz RB */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 444 1520, 1600, 0, 900, 903, 909, 953, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 446 /* 0x53 - 1600x900@60Hz */ 447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 448 1704, 1800, 0, 900, 901, 904, 1000, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x33 - 1600x1200@60Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x34 - 1600x1200@65Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x35 - 1600x1200@70Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x36 - 1600x1200@75Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x37 - 1600x1200@85Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x38 - 1600x1200@120Hz RB */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 474 /* 0x39 - 1680x1050@60Hz RB */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x3a - 1680x1050@60Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3b - 1680x1050@75Hz */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x3c - 1680x1050@85Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3d - 1680x1050@120Hz RB */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 494 /* 0x3e - 1792x1344@60Hz */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3f - 1792x1344@75Hz */ 499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x40 - 1792x1344@120Hz RB */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x41 - 1856x1392@60Hz */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x42 - 1856x1392@75Hz */ 511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x43 - 1856x1392@120Hz RB */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x52 - 1920x1080@60Hz */ 519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 522 /* 0x44 - 1920x1200@60Hz RB */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x45 - 1920x1200@60Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x46 - 1920x1200@75Hz */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x47 - 1920x1200@85Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x48 - 1920x1200@120Hz RB */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 542 /* 0x49 - 1920x1440@60Hz */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x4a - 1920x1440@75Hz */ 547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4b - 1920x1440@120Hz RB */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x54 - 2048x1152@60Hz */ 555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4c - 2560x1600@60Hz RB */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x4d - 2560x1600@60Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4e - 2560x1600@75Hz */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 570 /* 0x4f - 2560x1600@85Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x50 - 2560x1600@120Hz RB */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 /* 0x57 - 4096x2160@60Hz RB */ 579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 582 /* 0x58 - 4096x2160@59.94Hz RB */ 583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 }; 587 588 /* 589 * These more or less come from the DMT spec. The 720x400 modes are 590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 593 * mode. 594 * 595 * The DMT modes have been fact-checked; the rest are mild guesses. 596 */ 597 static const struct drm_display_mode edid_est_modes[] = { 598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 599 968, 1056, 0, 600, 601, 605, 628, 0, 600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 602 896, 1024, 0, 600, 601, 603, 625, 0, 603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 605 720, 840, 0, 480, 481, 484, 500, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 608 704, 832, 0, 480, 489, 492, 520, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 611 768, 864, 0, 480, 483, 486, 525, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 614 752, 800, 0, 480, 490, 492, 525, 0, 615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 617 846, 900, 0, 400, 421, 423, 449, 0, 618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 620 846, 900, 0, 400, 412, 414, 449, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 626 1136, 1312, 0, 768, 769, 772, 800, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 629 1184, 1328, 0, 768, 771, 777, 806, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 632 1184, 1344, 0, 768, 771, 777, 806, 0, 633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 635 1208, 1264, 0, 768, 768, 776, 817, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 638 928, 1152, 0, 624, 625, 628, 667, 0, 639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 641 896, 1056, 0, 600, 601, 604, 625, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 644 976, 1040, 0, 600, 637, 643, 666, 0, 645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 647 1344, 1600, 0, 864, 865, 868, 900, 0, 648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 649 }; 650 651 struct minimode { 652 short w; 653 short h; 654 short r; 655 short rb; 656 }; 657 658 static const struct minimode est3_modes[] = { 659 /* byte 6 */ 660 { 640, 350, 85, 0 }, 661 { 640, 400, 85, 0 }, 662 { 720, 400, 85, 0 }, 663 { 640, 480, 85, 0 }, 664 { 848, 480, 60, 0 }, 665 { 800, 600, 85, 0 }, 666 { 1024, 768, 85, 0 }, 667 { 1152, 864, 75, 0 }, 668 /* byte 7 */ 669 { 1280, 768, 60, 1 }, 670 { 1280, 768, 60, 0 }, 671 { 1280, 768, 75, 0 }, 672 { 1280, 768, 85, 0 }, 673 { 1280, 960, 60, 0 }, 674 { 1280, 960, 85, 0 }, 675 { 1280, 1024, 60, 0 }, 676 { 1280, 1024, 85, 0 }, 677 /* byte 8 */ 678 { 1360, 768, 60, 0 }, 679 { 1440, 900, 60, 1 }, 680 { 1440, 900, 60, 0 }, 681 { 1440, 900, 75, 0 }, 682 { 1440, 900, 85, 0 }, 683 { 1400, 1050, 60, 1 }, 684 { 1400, 1050, 60, 0 }, 685 { 1400, 1050, 75, 0 }, 686 /* byte 9 */ 687 { 1400, 1050, 85, 0 }, 688 { 1680, 1050, 60, 1 }, 689 { 1680, 1050, 60, 0 }, 690 { 1680, 1050, 75, 0 }, 691 { 1680, 1050, 85, 0 }, 692 { 1600, 1200, 60, 0 }, 693 { 1600, 1200, 65, 0 }, 694 { 1600, 1200, 70, 0 }, 695 /* byte 10 */ 696 { 1600, 1200, 75, 0 }, 697 { 1600, 1200, 85, 0 }, 698 { 1792, 1344, 60, 0 }, 699 { 1792, 1344, 75, 0 }, 700 { 1856, 1392, 60, 0 }, 701 { 1856, 1392, 75, 0 }, 702 { 1920, 1200, 60, 1 }, 703 { 1920, 1200, 60, 0 }, 704 /* byte 11 */ 705 { 1920, 1200, 75, 0 }, 706 { 1920, 1200, 85, 0 }, 707 { 1920, 1440, 60, 0 }, 708 { 1920, 1440, 75, 0 }, 709 }; 710 711 static const struct minimode extra_modes[] = { 712 { 1024, 576, 60, 0 }, 713 { 1366, 768, 60, 0 }, 714 { 1600, 900, 60, 0 }, 715 { 1680, 945, 60, 0 }, 716 { 1920, 1080, 60, 0 }, 717 { 2048, 1152, 60, 0 }, 718 { 2048, 1536, 60, 0 }, 719 }; 720 721 /* 722 * From CEA/CTA-861 spec. 723 * 724 * Do not access directly, instead always use cea_mode_for_vic(). 725 */ 726 static const struct drm_display_mode edid_cea_modes_1[] = { 727 /* 1 - 640x480@60Hz 4:3 */ 728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 729 752, 800, 0, 480, 490, 492, 525, 0, 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 732 /* 2 - 720x480@60Hz 4:3 */ 733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 734 798, 858, 0, 480, 489, 495, 525, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 3 - 720x480@60Hz 16:9 */ 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 739 798, 858, 0, 480, 489, 495, 525, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 4 - 1280x720@60Hz 16:9 */ 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 744 1430, 1650, 0, 720, 725, 730, 750, 0, 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 5 - 1920x1080i@60Hz 16:9 */ 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 6 - 720(1440)x480i@60Hz 4:3 */ 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 755 801, 858, 0, 480, 488, 494, 525, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 759 /* 7 - 720(1440)x480i@60Hz 16:9 */ 760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 761 801, 858, 0, 480, 488, 494, 525, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 8 - 720(1440)x240@60Hz 4:3 */ 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 767 801, 858, 0, 240, 244, 247, 262, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 9 - 720(1440)x240@60Hz 16:9 */ 772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 773 801, 858, 0, 240, 244, 247, 262, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_DBLCLK), 776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 10 - 2880x480i@60Hz 4:3 */ 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 779 3204, 3432, 0, 480, 488, 494, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 11 - 2880x480i@60Hz 16:9 */ 784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 785 3204, 3432, 0, 480, 488, 494, 525, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_INTERLACE), 788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 12 - 2880x240@60Hz 4:3 */ 790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 791 3204, 3432, 0, 240, 244, 247, 262, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 13 - 2880x240@60Hz 16:9 */ 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 240, 244, 247, 262, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 14 - 1440x480@60Hz 4:3 */ 800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 801 1596, 1716, 0, 480, 489, 495, 525, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 804 /* 15 - 1440x480@60Hz 16:9 */ 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 806 1596, 1716, 0, 480, 489, 495, 525, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 16 - 1920x1080@60Hz 16:9 */ 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 17 - 720x576@50Hz 4:3 */ 815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 816 796, 864, 0, 576, 581, 586, 625, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 819 /* 18 - 720x576@50Hz 16:9 */ 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 821 796, 864, 0, 576, 581, 586, 625, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 19 - 1280x720@50Hz 16:9 */ 825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 826 1760, 1980, 0, 720, 725, 730, 750, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 20 - 1920x1080i@50Hz 16:9 */ 830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 833 DRM_MODE_FLAG_INTERLACE), 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 21 - 720(1440)x576i@50Hz 4:3 */ 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 837 795, 864, 0, 576, 580, 586, 625, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 841 /* 22 - 720(1440)x576i@50Hz 16:9 */ 842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 843 795, 864, 0, 576, 580, 586, 625, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 847 /* 23 - 720(1440)x288@50Hz 4:3 */ 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 849 795, 864, 0, 288, 290, 293, 312, 0, 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 851 DRM_MODE_FLAG_DBLCLK), 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 24 - 720(1440)x288@50Hz 16:9 */ 854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 855 795, 864, 0, 288, 290, 293, 312, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 857 DRM_MODE_FLAG_DBLCLK), 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 25 - 2880x576i@50Hz 4:3 */ 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 861 3180, 3456, 0, 576, 580, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 865 /* 26 - 2880x576i@50Hz 16:9 */ 866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 867 3180, 3456, 0, 576, 580, 586, 625, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 869 DRM_MODE_FLAG_INTERLACE), 870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 871 /* 27 - 2880x288@50Hz 4:3 */ 872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 873 3180, 3456, 0, 288, 290, 293, 312, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 28 - 2880x288@50Hz 16:9 */ 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 288, 290, 293, 312, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 881 /* 29 - 1440x576@50Hz 4:3 */ 882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 883 1592, 1728, 0, 576, 581, 586, 625, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 886 /* 30 - 1440x576@50Hz 16:9 */ 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 888 1592, 1728, 0, 576, 581, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 891 /* 31 - 1920x1080@50Hz 16:9 */ 892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 896 /* 32 - 1920x1080@24Hz 16:9 */ 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 33 - 1920x1080@25Hz 16:9 */ 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 34 - 1920x1080@30Hz 16:9 */ 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 911 /* 35 - 2880x480@60Hz 4:3 */ 912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 913 3192, 3432, 0, 480, 489, 495, 525, 0, 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 916 /* 36 - 2880x480@60Hz 16:9 */ 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 918 3192, 3432, 0, 480, 489, 495, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 37 - 2880x576@50Hz 4:3 */ 922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 923 3184, 3456, 0, 576, 581, 586, 625, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 926 /* 38 - 2880x576@50Hz 16:9 */ 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 928 3184, 3456, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 39 - 1920x1080i@50Hz 16:9 */ 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 935 DRM_MODE_FLAG_INTERLACE), 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 937 /* 40 - 1920x1080i@100Hz 16:9 */ 938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 941 DRM_MODE_FLAG_INTERLACE), 942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 41 - 1280x720@100Hz 16:9 */ 944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 945 1760, 1980, 0, 720, 725, 730, 750, 0, 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 42 - 720x576@100Hz 4:3 */ 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 950 796, 864, 0, 576, 581, 586, 625, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 953 /* 43 - 720x576@100Hz 16:9 */ 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 955 796, 864, 0, 576, 581, 586, 625, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 /* 44 - 720(1440)x576i@100Hz 4:3 */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 45 - 720(1440)x576i@100Hz 16:9 */ 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 966 795, 864, 0, 576, 580, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 46 - 1920x1080i@120Hz 16:9 */ 971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 974 DRM_MODE_FLAG_INTERLACE), 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 976 /* 47 - 1280x720@120Hz 16:9 */ 977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 978 1430, 1650, 0, 720, 725, 730, 750, 0, 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 48 - 720x480@120Hz 4:3 */ 982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 983 798, 858, 0, 480, 489, 495, 525, 0, 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 986 /* 49 - 720x480@120Hz 16:9 */ 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 988 798, 858, 0, 480, 489, 495, 525, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 991 /* 50 - 720(1440)x480i@120Hz 4:3 */ 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 993 801, 858, 0, 480, 488, 494, 525, 0, 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 997 /* 51 - 720(1440)x480i@120Hz 16:9 */ 998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 999 801, 858, 0, 480, 488, 494, 525, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1003 /* 52 - 720x576@200Hz 4:3 */ 1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1005 796, 864, 0, 576, 581, 586, 625, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1008 /* 53 - 720x576@200Hz 16:9 */ 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1010 796, 864, 0, 576, 581, 586, 625, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1013 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1015 795, 864, 0, 576, 580, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1019 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1021 795, 864, 0, 576, 580, 586, 625, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1025 /* 56 - 720x480@240Hz 4:3 */ 1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1027 798, 858, 0, 480, 489, 495, 525, 0, 1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1030 /* 57 - 720x480@240Hz 16:9 */ 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1032 798, 858, 0, 480, 489, 495, 525, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1035 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1037 801, 858, 0, 480, 488, 494, 525, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1041 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1043 801, 858, 0, 480, 488, 494, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1047 /* 60 - 1280x720@24Hz 16:9 */ 1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1049 3080, 3300, 0, 720, 725, 730, 750, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1052 /* 61 - 1280x720@25Hz 16:9 */ 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1054 3740, 3960, 0, 720, 725, 730, 750, 0, 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1057 /* 62 - 1280x720@30Hz 16:9 */ 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1059 3080, 3300, 0, 720, 725, 730, 750, 0, 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1062 /* 63 - 1920x1080@120Hz 16:9 */ 1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1067 /* 64 - 1920x1080@100Hz 16:9 */ 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1072 /* 65 - 1280x720@24Hz 64:27 */ 1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1074 3080, 3300, 0, 720, 725, 730, 750, 0, 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1077 /* 66 - 1280x720@25Hz 64:27 */ 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1079 3740, 3960, 0, 720, 725, 730, 750, 0, 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1082 /* 67 - 1280x720@30Hz 64:27 */ 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1084 3080, 3300, 0, 720, 725, 730, 750, 0, 1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1087 /* 68 - 1280x720@50Hz 64:27 */ 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1089 1760, 1980, 0, 720, 725, 730, 750, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1092 /* 69 - 1280x720@60Hz 64:27 */ 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1094 1430, 1650, 0, 720, 725, 730, 750, 0, 1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1097 /* 70 - 1280x720@100Hz 64:27 */ 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1099 1760, 1980, 0, 720, 725, 730, 750, 0, 1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1102 /* 71 - 1280x720@120Hz 64:27 */ 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1104 1430, 1650, 0, 720, 725, 730, 750, 0, 1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1107 /* 72 - 1920x1080@24Hz 64:27 */ 1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1112 /* 73 - 1920x1080@25Hz 64:27 */ 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1117 /* 74 - 1920x1080@30Hz 64:27 */ 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1122 /* 75 - 1920x1080@50Hz 64:27 */ 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1127 /* 76 - 1920x1080@60Hz 64:27 */ 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1132 /* 77 - 1920x1080@100Hz 64:27 */ 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1137 /* 78 - 1920x1080@120Hz 64:27 */ 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1142 /* 79 - 1680x720@24Hz 64:27 */ 1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1144 3080, 3300, 0, 720, 725, 730, 750, 0, 1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1147 /* 80 - 1680x720@25Hz 64:27 */ 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1149 2948, 3168, 0, 720, 725, 730, 750, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1152 /* 81 - 1680x720@30Hz 64:27 */ 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1154 2420, 2640, 0, 720, 725, 730, 750, 0, 1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1157 /* 82 - 1680x720@50Hz 64:27 */ 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1159 1980, 2200, 0, 720, 725, 730, 750, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1162 /* 83 - 1680x720@60Hz 64:27 */ 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1164 1980, 2200, 0, 720, 725, 730, 750, 0, 1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1167 /* 84 - 1680x720@100Hz 64:27 */ 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1169 1780, 2000, 0, 720, 725, 730, 825, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1172 /* 85 - 1680x720@120Hz 64:27 */ 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1174 1780, 2000, 0, 720, 725, 730, 825, 0, 1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1177 /* 86 - 2560x1080@24Hz 64:27 */ 1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1182 /* 87 - 2560x1080@25Hz 64:27 */ 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1187 /* 88 - 2560x1080@30Hz 64:27 */ 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1192 /* 89 - 2560x1080@50Hz 64:27 */ 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1197 /* 90 - 2560x1080@60Hz 64:27 */ 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1202 /* 91 - 2560x1080@100Hz 64:27 */ 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1207 /* 92 - 2560x1080@120Hz 64:27 */ 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1212 /* 93 - 3840x2160@24Hz 16:9 */ 1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1217 /* 94 - 3840x2160@25Hz 16:9 */ 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1222 /* 95 - 3840x2160@30Hz 16:9 */ 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1227 /* 96 - 3840x2160@50Hz 16:9 */ 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1232 /* 97 - 3840x2160@60Hz 16:9 */ 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1237 /* 98 - 4096x2160@24Hz 256:135 */ 1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1242 /* 99 - 4096x2160@25Hz 256:135 */ 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1247 /* 100 - 4096x2160@30Hz 256:135 */ 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1252 /* 101 - 4096x2160@50Hz 256:135 */ 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1257 /* 102 - 4096x2160@60Hz 256:135 */ 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1262 /* 103 - 3840x2160@24Hz 64:27 */ 1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1267 /* 104 - 3840x2160@25Hz 64:27 */ 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1272 /* 105 - 3840x2160@30Hz 64:27 */ 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1277 /* 106 - 3840x2160@50Hz 64:27 */ 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1282 /* 107 - 3840x2160@60Hz 64:27 */ 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1287 /* 108 - 1280x720@48Hz 16:9 */ 1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1289 2280, 2500, 0, 720, 725, 730, 750, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1292 /* 109 - 1280x720@48Hz 64:27 */ 1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1294 2280, 2500, 0, 720, 725, 730, 750, 0, 1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1297 /* 110 - 1680x720@48Hz 64:27 */ 1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1299 2530, 2750, 0, 720, 725, 730, 750, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1302 /* 111 - 1920x1080@48Hz 16:9 */ 1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1307 /* 112 - 1920x1080@48Hz 64:27 */ 1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1312 /* 113 - 2560x1080@48Hz 64:27 */ 1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1317 /* 114 - 3840x2160@48Hz 16:9 */ 1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1322 /* 115 - 4096x2160@48Hz 256:135 */ 1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1327 /* 116 - 3840x2160@48Hz 64:27 */ 1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1332 /* 117 - 3840x2160@100Hz 16:9 */ 1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1337 /* 118 - 3840x2160@120Hz 16:9 */ 1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1342 /* 119 - 3840x2160@100Hz 64:27 */ 1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1347 /* 120 - 3840x2160@120Hz 64:27 */ 1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1352 /* 121 - 5120x2160@24Hz 64:27 */ 1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1357 /* 122 - 5120x2160@25Hz 64:27 */ 1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1362 /* 123 - 5120x2160@30Hz 64:27 */ 1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1367 /* 124 - 5120x2160@48Hz 64:27 */ 1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1372 /* 125 - 5120x2160@50Hz 64:27 */ 1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1377 /* 126 - 5120x2160@60Hz 64:27 */ 1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1382 /* 127 - 5120x2160@100Hz 64:27 */ 1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1387 }; 1388 1389 /* 1390 * From CEA/CTA-861 spec. 1391 * 1392 * Do not access directly, instead always use cea_mode_for_vic(). 1393 */ 1394 static const struct drm_display_mode edid_cea_modes_193[] = { 1395 /* 193 - 5120x2160@120Hz 64:27 */ 1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1400 /* 194 - 7680x4320@24Hz 16:9 */ 1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1405 /* 195 - 7680x4320@25Hz 16:9 */ 1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1410 /* 196 - 7680x4320@30Hz 16:9 */ 1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1415 /* 197 - 7680x4320@48Hz 16:9 */ 1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1420 /* 198 - 7680x4320@50Hz 16:9 */ 1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1425 /* 199 - 7680x4320@60Hz 16:9 */ 1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1430 /* 200 - 7680x4320@100Hz 16:9 */ 1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1435 /* 201 - 7680x4320@120Hz 16:9 */ 1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1440 /* 202 - 7680x4320@24Hz 64:27 */ 1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1445 /* 203 - 7680x4320@25Hz 64:27 */ 1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1450 /* 204 - 7680x4320@30Hz 64:27 */ 1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1455 /* 205 - 7680x4320@48Hz 64:27 */ 1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1460 /* 206 - 7680x4320@50Hz 64:27 */ 1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1465 /* 207 - 7680x4320@60Hz 64:27 */ 1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1470 /* 208 - 7680x4320@100Hz 64:27 */ 1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1475 /* 209 - 7680x4320@120Hz 64:27 */ 1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1480 /* 210 - 10240x4320@24Hz 64:27 */ 1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1485 /* 211 - 10240x4320@25Hz 64:27 */ 1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1490 /* 212 - 10240x4320@30Hz 64:27 */ 1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1495 /* 213 - 10240x4320@48Hz 64:27 */ 1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1500 /* 214 - 10240x4320@50Hz 64:27 */ 1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1505 /* 215 - 10240x4320@60Hz 64:27 */ 1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1510 /* 216 - 10240x4320@100Hz 64:27 */ 1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1515 /* 217 - 10240x4320@120Hz 64:27 */ 1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1520 /* 218 - 4096x2160@100Hz 256:135 */ 1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1525 /* 219 - 4096x2160@120Hz 256:135 */ 1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1530 }; 1531 1532 /* 1533 * HDMI 1.4 4k modes. Index using the VIC. 1534 */ 1535 static const struct drm_display_mode edid_4k_modes[] = { 1536 /* 0 - dummy, VICs start at 1 */ 1537 { }, 1538 /* 1 - 3840x2160@30Hz */ 1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1540 3840, 4016, 4104, 4400, 0, 1541 2160, 2168, 2178, 2250, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1544 /* 2 - 3840x2160@25Hz */ 1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1546 3840, 4896, 4984, 5280, 0, 1547 2160, 2168, 2178, 2250, 0, 1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1550 /* 3 - 3840x2160@24Hz */ 1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1552 3840, 5116, 5204, 5500, 0, 1553 2160, 2168, 2178, 2250, 0, 1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1556 /* 4 - 4096x2160@24Hz (SMPTE) */ 1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1558 4096, 5116, 5204, 5500, 0, 1559 2160, 2168, 2178, 2250, 0, 1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1562 }; 1563 1564 /*** DDC fetch and block validation ***/ 1565 1566 /* 1567 * The opaque EDID type, internal to drm_edid.c. 1568 */ 1569 struct drm_edid { 1570 /* Size allocated for edid */ 1571 size_t size; 1572 const struct edid *edid; 1573 }; 1574 1575 static bool version_greater(const struct drm_edid *drm_edid, 1576 u8 version, u8 revision) 1577 { 1578 const struct edid *edid = drm_edid->edid; 1579 1580 return edid->version > version || 1581 (edid->version == version && edid->revision > revision); 1582 } 1583 1584 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1585 1586 static int edid_hfeeodb_block_count(const struct edid *edid) 1587 { 1588 int eeodb = edid_hfeeodb_extension_block_count(edid); 1589 1590 return eeodb ? eeodb + 1 : 0; 1591 } 1592 1593 static int edid_extension_block_count(const struct edid *edid) 1594 { 1595 return edid->extensions; 1596 } 1597 1598 static int edid_block_count(const struct edid *edid) 1599 { 1600 return edid_extension_block_count(edid) + 1; 1601 } 1602 1603 static int edid_size_by_blocks(int num_blocks) 1604 { 1605 return num_blocks * EDID_LENGTH; 1606 } 1607 1608 static int edid_size(const struct edid *edid) 1609 { 1610 return edid_size_by_blocks(edid_block_count(edid)); 1611 } 1612 1613 static const void *edid_block_data(const struct edid *edid, int index) 1614 { 1615 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1616 1617 return edid + index; 1618 } 1619 1620 static const void *edid_extension_block_data(const struct edid *edid, int index) 1621 { 1622 return edid_block_data(edid, index + 1); 1623 } 1624 1625 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1626 { 1627 int num_blocks; 1628 1629 /* Starting point */ 1630 num_blocks = edid_block_count(drm_edid->edid); 1631 1632 /* HF-EEODB override */ 1633 if (drm_edid->size >= edid_size_by_blocks(2)) { 1634 int eeodb; 1635 1636 /* 1637 * Note: HF-EEODB may specify a smaller extension count than the 1638 * regular one. Unlike in buffer allocation, here we can use it. 1639 */ 1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1641 if (eeodb) 1642 num_blocks = eeodb; 1643 } 1644 1645 /* Limit by allocated size */ 1646 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH); 1647 1648 return num_blocks; 1649 } 1650 1651 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1652 { 1653 return drm_edid_block_count(drm_edid) - 1; 1654 } 1655 1656 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1657 { 1658 return edid_block_data(drm_edid->edid, index); 1659 } 1660 1661 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1662 int index) 1663 { 1664 return edid_extension_block_data(drm_edid->edid, index); 1665 } 1666 1667 /* 1668 * Initializer helper for legacy interfaces, where we have no choice but to 1669 * trust edid size. Not for general purpose use. 1670 */ 1671 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1672 const struct edid *edid) 1673 { 1674 if (!edid) 1675 return NULL; 1676 1677 memset(drm_edid, 0, sizeof(*drm_edid)); 1678 1679 drm_edid->edid = edid; 1680 drm_edid->size = edid_size(edid); 1681 1682 return drm_edid; 1683 } 1684 1685 /* 1686 * EDID base and extension block iterator. 1687 * 1688 * struct drm_edid_iter iter; 1689 * const u8 *block; 1690 * 1691 * drm_edid_iter_begin(drm_edid, &iter); 1692 * drm_edid_iter_for_each(block, &iter) { 1693 * // do stuff with block 1694 * } 1695 * drm_edid_iter_end(&iter); 1696 */ 1697 struct drm_edid_iter { 1698 const struct drm_edid *drm_edid; 1699 1700 /* Current block index. */ 1701 int index; 1702 }; 1703 1704 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1705 struct drm_edid_iter *iter) 1706 { 1707 memset(iter, 0, sizeof(*iter)); 1708 1709 iter->drm_edid = drm_edid; 1710 } 1711 1712 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1713 { 1714 const void *block = NULL; 1715 1716 if (!iter->drm_edid) 1717 return NULL; 1718 1719 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1720 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1721 1722 return block; 1723 } 1724 1725 #define drm_edid_iter_for_each(__block, __iter) \ 1726 while (((__block) = __drm_edid_iter_next(__iter))) 1727 1728 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1729 { 1730 memset(iter, 0, sizeof(*iter)); 1731 } 1732 1733 static const u8 edid_header[] = { 1734 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1735 }; 1736 1737 static void edid_header_fix(void *edid) 1738 { 1739 memcpy(edid, edid_header, sizeof(edid_header)); 1740 } 1741 1742 /** 1743 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1744 * @_edid: pointer to raw base EDID block 1745 * 1746 * Sanity check the header of the base EDID block. 1747 * 1748 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1749 */ 1750 int drm_edid_header_is_valid(const void *_edid) 1751 { 1752 const struct edid *edid = _edid; 1753 int i, score = 0; 1754 1755 for (i = 0; i < sizeof(edid_header); i++) { 1756 if (edid->header[i] == edid_header[i]) 1757 score++; 1758 } 1759 1760 return score; 1761 } 1762 EXPORT_SYMBOL(drm_edid_header_is_valid); 1763 1764 static int edid_fixup __read_mostly = 6; 1765 module_param_named(edid_fixup, edid_fixup, int, 0400); 1766 MODULE_PARM_DESC(edid_fixup, 1767 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1768 1769 static int edid_block_compute_checksum(const void *_block) 1770 { 1771 const u8 *block = _block; 1772 int i; 1773 u8 csum = 0, crc = 0; 1774 1775 for (i = 0; i < EDID_LENGTH - 1; i++) 1776 csum += block[i]; 1777 1778 crc = 0x100 - csum; 1779 1780 return crc; 1781 } 1782 1783 static int edid_block_get_checksum(const void *_block) 1784 { 1785 const struct edid *block = _block; 1786 1787 return block->checksum; 1788 } 1789 1790 static int edid_block_tag(const void *_block) 1791 { 1792 const u8 *block = _block; 1793 1794 return block[0]; 1795 } 1796 1797 static bool edid_block_is_zero(const void *edid) 1798 { 1799 return !memchr_inv(edid, 0, EDID_LENGTH); 1800 } 1801 1802 /** 1803 * drm_edid_are_equal - compare two edid blobs. 1804 * @edid1: pointer to first blob 1805 * @edid2: pointer to second blob 1806 * This helper can be used during probing to determine if 1807 * edid had changed. 1808 */ 1809 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1810 { 1811 int edid1_len, edid2_len; 1812 bool edid1_present = edid1 != NULL; 1813 bool edid2_present = edid2 != NULL; 1814 1815 if (edid1_present != edid2_present) 1816 return false; 1817 1818 if (edid1) { 1819 edid1_len = edid_size(edid1); 1820 edid2_len = edid_size(edid2); 1821 1822 if (edid1_len != edid2_len) 1823 return false; 1824 1825 if (memcmp(edid1, edid2, edid1_len)) 1826 return false; 1827 } 1828 1829 return true; 1830 } 1831 EXPORT_SYMBOL(drm_edid_are_equal); 1832 1833 enum edid_block_status { 1834 EDID_BLOCK_OK = 0, 1835 EDID_BLOCK_READ_FAIL, 1836 EDID_BLOCK_NULL, 1837 EDID_BLOCK_ZERO, 1838 EDID_BLOCK_HEADER_CORRUPT, 1839 EDID_BLOCK_HEADER_REPAIR, 1840 EDID_BLOCK_HEADER_FIXED, 1841 EDID_BLOCK_CHECKSUM, 1842 EDID_BLOCK_VERSION, 1843 }; 1844 1845 static enum edid_block_status edid_block_check(const void *_block, 1846 bool is_base_block) 1847 { 1848 const struct edid *block = _block; 1849 1850 if (!block) 1851 return EDID_BLOCK_NULL; 1852 1853 if (is_base_block) { 1854 int score = drm_edid_header_is_valid(block); 1855 1856 if (score < clamp(edid_fixup, 0, 8)) { 1857 if (edid_block_is_zero(block)) 1858 return EDID_BLOCK_ZERO; 1859 else 1860 return EDID_BLOCK_HEADER_CORRUPT; 1861 } 1862 1863 if (score < 8) 1864 return EDID_BLOCK_HEADER_REPAIR; 1865 } 1866 1867 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1868 if (edid_block_is_zero(block)) 1869 return EDID_BLOCK_ZERO; 1870 else 1871 return EDID_BLOCK_CHECKSUM; 1872 } 1873 1874 if (is_base_block) { 1875 if (block->version != 1) 1876 return EDID_BLOCK_VERSION; 1877 } 1878 1879 return EDID_BLOCK_OK; 1880 } 1881 1882 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1883 { 1884 return status == EDID_BLOCK_OK || 1885 status == EDID_BLOCK_HEADER_FIXED || 1886 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1887 } 1888 1889 static bool edid_block_valid(const void *block, bool base) 1890 { 1891 return edid_block_status_valid(edid_block_check(block, base), 1892 edid_block_tag(block)); 1893 } 1894 1895 static void edid_block_status_print(enum edid_block_status status, 1896 const struct edid *block, 1897 int block_num) 1898 { 1899 switch (status) { 1900 case EDID_BLOCK_OK: 1901 break; 1902 case EDID_BLOCK_READ_FAIL: 1903 pr_debug("EDID block %d read failed\n", block_num); 1904 break; 1905 case EDID_BLOCK_NULL: 1906 pr_debug("EDID block %d pointer is NULL\n", block_num); 1907 break; 1908 case EDID_BLOCK_ZERO: 1909 pr_notice("EDID block %d is all zeroes\n", block_num); 1910 break; 1911 case EDID_BLOCK_HEADER_CORRUPT: 1912 pr_notice("EDID has corrupt header\n"); 1913 break; 1914 case EDID_BLOCK_HEADER_REPAIR: 1915 pr_debug("EDID corrupt header needs repair\n"); 1916 break; 1917 case EDID_BLOCK_HEADER_FIXED: 1918 pr_debug("EDID corrupt header fixed\n"); 1919 break; 1920 case EDID_BLOCK_CHECKSUM: 1921 if (edid_block_status_valid(status, edid_block_tag(block))) { 1922 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1923 block_num, edid_block_tag(block), 1924 edid_block_compute_checksum(block)); 1925 } else { 1926 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1927 block_num, edid_block_tag(block), 1928 edid_block_compute_checksum(block)); 1929 } 1930 break; 1931 case EDID_BLOCK_VERSION: 1932 pr_notice("EDID has major version %d, instead of 1\n", 1933 block->version); 1934 break; 1935 default: 1936 WARN(1, "EDID block %d unknown edid block status code %d\n", 1937 block_num, status); 1938 break; 1939 } 1940 } 1941 1942 static void edid_block_dump(const char *level, const void *block, int block_num) 1943 { 1944 enum edid_block_status status; 1945 char prefix[20]; 1946 1947 status = edid_block_check(block, block_num == 0); 1948 if (status == EDID_BLOCK_ZERO) 1949 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1950 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1951 sprintf(prefix, "\t[%02x] BAD ", block_num); 1952 else 1953 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1954 1955 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1956 block, EDID_LENGTH, false); 1957 } 1958 1959 /** 1960 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1961 * @_block: pointer to raw EDID block 1962 * @block_num: type of block to validate (0 for base, extension otherwise) 1963 * @print_bad_edid: if true, dump bad EDID blocks to the console 1964 * @edid_corrupt: if true, the header or checksum is invalid 1965 * 1966 * Validate a base or extension EDID block and optionally dump bad blocks to 1967 * the console. 1968 * 1969 * Return: True if the block is valid, false otherwise. 1970 */ 1971 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1972 bool *edid_corrupt) 1973 { 1974 struct edid *block = (struct edid *)_block; 1975 enum edid_block_status status; 1976 bool is_base_block = block_num == 0; 1977 bool valid; 1978 1979 if (WARN_ON(!block)) 1980 return false; 1981 1982 status = edid_block_check(block, is_base_block); 1983 if (status == EDID_BLOCK_HEADER_REPAIR) { 1984 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1985 edid_header_fix(block); 1986 1987 /* Retry with fixed header, update status if that worked. */ 1988 status = edid_block_check(block, is_base_block); 1989 if (status == EDID_BLOCK_OK) 1990 status = EDID_BLOCK_HEADER_FIXED; 1991 } 1992 1993 if (edid_corrupt) { 1994 /* 1995 * Unknown major version isn't corrupt but we can't use it. Only 1996 * the base block can reset edid_corrupt to false. 1997 */ 1998 if (is_base_block && 1999 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2000 *edid_corrupt = false; 2001 else if (status != EDID_BLOCK_OK) 2002 *edid_corrupt = true; 2003 } 2004 2005 edid_block_status_print(status, block, block_num); 2006 2007 /* Determine whether we can use this block with this status. */ 2008 valid = edid_block_status_valid(status, edid_block_tag(block)); 2009 2010 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2011 pr_notice("Raw EDID:\n"); 2012 edid_block_dump(KERN_NOTICE, block, block_num); 2013 } 2014 2015 return valid; 2016 } 2017 EXPORT_SYMBOL(drm_edid_block_valid); 2018 2019 /** 2020 * drm_edid_is_valid - sanity check EDID data 2021 * @edid: EDID data 2022 * 2023 * Sanity-check an entire EDID record (including extensions) 2024 * 2025 * Return: True if the EDID data is valid, false otherwise. 2026 */ 2027 bool drm_edid_is_valid(struct edid *edid) 2028 { 2029 int i; 2030 2031 if (!edid) 2032 return false; 2033 2034 for (i = 0; i < edid_block_count(edid); i++) { 2035 void *block = (void *)edid_block_data(edid, i); 2036 2037 if (!drm_edid_block_valid(block, i, true, NULL)) 2038 return false; 2039 } 2040 2041 return true; 2042 } 2043 EXPORT_SYMBOL(drm_edid_is_valid); 2044 2045 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2046 size_t *alloc_size) 2047 { 2048 struct edid *new; 2049 int i, valid_blocks = 0; 2050 2051 /* 2052 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2053 * back to regular extension count here. We don't want to start 2054 * modifying the HF-EEODB extension too. 2055 */ 2056 for (i = 0; i < edid_block_count(edid); i++) { 2057 const void *src_block = edid_block_data(edid, i); 2058 2059 if (edid_block_valid(src_block, i == 0)) { 2060 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2061 2062 memmove(dst_block, src_block, EDID_LENGTH); 2063 valid_blocks++; 2064 } 2065 } 2066 2067 /* We already trusted the base block to be valid here... */ 2068 if (WARN_ON(!valid_blocks)) { 2069 kfree(edid); 2070 return NULL; 2071 } 2072 2073 edid->extensions = valid_blocks - 1; 2074 edid->checksum = edid_block_compute_checksum(edid); 2075 2076 *alloc_size = edid_size_by_blocks(valid_blocks); 2077 2078 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2079 if (!new) 2080 kfree(edid); 2081 2082 return new; 2083 } 2084 2085 #define DDC_SEGMENT_ADDR 0x30 2086 /** 2087 * drm_do_probe_ddc_edid() - get EDID information via I2C 2088 * @data: I2C device adapter 2089 * @buf: EDID data buffer to be filled 2090 * @block: 128 byte EDID block to start fetching from 2091 * @len: EDID data buffer length to fetch 2092 * 2093 * Try to fetch EDID information by calling I2C driver functions. 2094 * 2095 * Return: 0 on success or -1 on failure. 2096 */ 2097 static int 2098 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2099 { 2100 struct i2c_adapter *adapter = data; 2101 unsigned char start = block * EDID_LENGTH; 2102 unsigned char segment = block >> 1; 2103 unsigned char xfers = segment ? 3 : 2; 2104 int ret, retries = 5; 2105 2106 /* 2107 * The core I2C driver will automatically retry the transfer if the 2108 * adapter reports EAGAIN. However, we find that bit-banging transfers 2109 * are susceptible to errors under a heavily loaded machine and 2110 * generate spurious NAKs and timeouts. Retrying the transfer 2111 * of the individual block a few times seems to overcome this. 2112 */ 2113 do { 2114 struct i2c_msg msgs[] = { 2115 { 2116 .addr = DDC_SEGMENT_ADDR, 2117 .flags = 0, 2118 .len = 1, 2119 .buf = &segment, 2120 }, { 2121 .addr = DDC_ADDR, 2122 .flags = 0, 2123 .len = 1, 2124 .buf = &start, 2125 }, { 2126 .addr = DDC_ADDR, 2127 .flags = I2C_M_RD, 2128 .len = len, 2129 .buf = buf, 2130 } 2131 }; 2132 2133 /* 2134 * Avoid sending the segment addr to not upset non-compliant 2135 * DDC monitors. 2136 */ 2137 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2138 2139 if (ret == -ENXIO) { 2140 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2141 adapter->name); 2142 break; 2143 } 2144 } while (ret != xfers && --retries); 2145 2146 return ret == xfers ? 0 : -1; 2147 } 2148 2149 static void connector_bad_edid(struct drm_connector *connector, 2150 const struct edid *edid, int num_blocks) 2151 { 2152 int i; 2153 u8 last_block; 2154 2155 /* 2156 * 0x7e in the EDID is the number of extension blocks. The EDID 2157 * is 1 (base block) + num_ext_blocks big. That means we can think 2158 * of 0x7e in the EDID of the _index_ of the last block in the 2159 * combined chunk of memory. 2160 */ 2161 last_block = edid->extensions; 2162 2163 /* Calculate real checksum for the last edid extension block data */ 2164 if (last_block < num_blocks) 2165 connector->real_edid_checksum = 2166 edid_block_compute_checksum(edid + last_block); 2167 2168 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2169 return; 2170 2171 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 2172 for (i = 0; i < num_blocks; i++) 2173 edid_block_dump(KERN_DEBUG, edid + i, i); 2174 } 2175 2176 /* Get override or firmware EDID */ 2177 static struct edid *drm_get_override_edid(struct drm_connector *connector, 2178 size_t *alloc_size) 2179 { 2180 struct edid *override = NULL; 2181 2182 if (connector->override_edid) 2183 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 2184 2185 if (!override) 2186 override = drm_load_edid_firmware(connector); 2187 2188 /* FIXME: Get alloc size from deeper down the stack */ 2189 if (!IS_ERR_OR_NULL(override) && alloc_size) 2190 *alloc_size = edid_size(override); 2191 2192 return IS_ERR(override) ? NULL : override; 2193 } 2194 2195 /* For debugfs edid_override implementation */ 2196 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2197 size_t size) 2198 { 2199 int ret; 2200 2201 if (size < EDID_LENGTH || edid_size(edid) > size) 2202 return -EINVAL; 2203 2204 connector->override_edid = false; 2205 2206 ret = drm_connector_update_edid_property(connector, edid); 2207 if (!ret) 2208 connector->override_edid = true; 2209 2210 return ret; 2211 } 2212 2213 /* For debugfs edid_override implementation */ 2214 int drm_edid_override_reset(struct drm_connector *connector) 2215 { 2216 connector->override_edid = false; 2217 2218 return drm_connector_update_edid_property(connector, NULL); 2219 } 2220 2221 /** 2222 * drm_add_override_edid_modes - add modes from override/firmware EDID 2223 * @connector: connector we're probing 2224 * 2225 * Add modes from the override/firmware EDID, if available. Only to be used from 2226 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2227 * failed during drm_get_edid() and caused the override/firmware EDID to be 2228 * skipped. 2229 * 2230 * Return: The number of modes added or 0 if we couldn't find any. 2231 */ 2232 int drm_add_override_edid_modes(struct drm_connector *connector) 2233 { 2234 struct edid *override; 2235 int num_modes = 0; 2236 2237 override = drm_get_override_edid(connector, NULL); 2238 if (override) { 2239 drm_connector_update_edid_property(connector, override); 2240 num_modes = drm_add_edid_modes(connector, override); 2241 kfree(override); 2242 2243 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2244 connector->base.id, connector->name, num_modes); 2245 } 2246 2247 return num_modes; 2248 } 2249 EXPORT_SYMBOL(drm_add_override_edid_modes); 2250 2251 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2252 2253 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2254 read_block_fn read_block, 2255 void *context) 2256 { 2257 enum edid_block_status status; 2258 bool is_base_block = block_num == 0; 2259 int try; 2260 2261 for (try = 0; try < 4; try++) { 2262 if (read_block(context, block, block_num, EDID_LENGTH)) 2263 return EDID_BLOCK_READ_FAIL; 2264 2265 status = edid_block_check(block, is_base_block); 2266 if (status == EDID_BLOCK_HEADER_REPAIR) { 2267 edid_header_fix(block); 2268 2269 /* Retry with fixed header, update status if that worked. */ 2270 status = edid_block_check(block, is_base_block); 2271 if (status == EDID_BLOCK_OK) 2272 status = EDID_BLOCK_HEADER_FIXED; 2273 } 2274 2275 if (edid_block_status_valid(status, edid_block_tag(block))) 2276 break; 2277 2278 /* Fail early for unrepairable base block all zeros. */ 2279 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2280 break; 2281 } 2282 2283 return status; 2284 } 2285 2286 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2287 read_block_fn read_block, void *context, 2288 size_t *size) 2289 { 2290 enum edid_block_status status; 2291 int i, num_blocks, invalid_blocks = 0; 2292 struct edid *edid, *new; 2293 size_t alloc_size = EDID_LENGTH; 2294 2295 edid = drm_get_override_edid(connector, &alloc_size); 2296 if (edid) 2297 goto ok; 2298 2299 edid = kmalloc(alloc_size, GFP_KERNEL); 2300 if (!edid) 2301 return NULL; 2302 2303 status = edid_block_read(edid, 0, read_block, context); 2304 2305 edid_block_status_print(status, edid, 0); 2306 2307 if (status == EDID_BLOCK_READ_FAIL) 2308 goto fail; 2309 2310 /* FIXME: Clarify what a corrupt EDID actually means. */ 2311 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2312 connector->edid_corrupt = false; 2313 else 2314 connector->edid_corrupt = true; 2315 2316 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2317 if (status == EDID_BLOCK_ZERO) 2318 connector->null_edid_counter++; 2319 2320 connector_bad_edid(connector, edid, 1); 2321 goto fail; 2322 } 2323 2324 if (!edid_extension_block_count(edid)) 2325 goto ok; 2326 2327 alloc_size = edid_size(edid); 2328 new = krealloc(edid, alloc_size, GFP_KERNEL); 2329 if (!new) 2330 goto fail; 2331 edid = new; 2332 2333 num_blocks = edid_block_count(edid); 2334 for (i = 1; i < num_blocks; i++) { 2335 void *block = (void *)edid_block_data(edid, i); 2336 2337 status = edid_block_read(block, i, read_block, context); 2338 2339 edid_block_status_print(status, block, i); 2340 2341 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2342 if (status == EDID_BLOCK_READ_FAIL) 2343 goto fail; 2344 invalid_blocks++; 2345 } else if (i == 1) { 2346 /* 2347 * If the first EDID extension is a CTA extension, and 2348 * the first Data Block is HF-EEODB, override the 2349 * extension block count. 2350 * 2351 * Note: HF-EEODB could specify a smaller extension 2352 * count too, but we can't risk allocating a smaller 2353 * amount. 2354 */ 2355 int eeodb = edid_hfeeodb_block_count(edid); 2356 2357 if (eeodb > num_blocks) { 2358 num_blocks = eeodb; 2359 alloc_size = edid_size_by_blocks(num_blocks); 2360 new = krealloc(edid, alloc_size, GFP_KERNEL); 2361 if (!new) 2362 goto fail; 2363 edid = new; 2364 } 2365 } 2366 } 2367 2368 if (invalid_blocks) { 2369 connector_bad_edid(connector, edid, num_blocks); 2370 2371 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2372 } 2373 2374 ok: 2375 if (size) 2376 *size = alloc_size; 2377 2378 return edid; 2379 2380 fail: 2381 kfree(edid); 2382 return NULL; 2383 } 2384 2385 /** 2386 * drm_do_get_edid - get EDID data using a custom EDID block read function 2387 * @connector: connector we're probing 2388 * @read_block: EDID block read function 2389 * @context: private data passed to the block read function 2390 * 2391 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2392 * exposes a different interface to read EDID blocks this function can be used 2393 * to get EDID data using a custom block read function. 2394 * 2395 * As in the general case the DDC bus is accessible by the kernel at the I2C 2396 * level, drivers must make all reasonable efforts to expose it as an I2C 2397 * adapter and use drm_get_edid() instead of abusing this function. 2398 * 2399 * The EDID may be overridden using debugfs override_edid or firmware EDID 2400 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2401 * order. Having either of them bypasses actual EDID reads. 2402 * 2403 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2404 */ 2405 struct edid *drm_do_get_edid(struct drm_connector *connector, 2406 read_block_fn read_block, 2407 void *context) 2408 { 2409 return _drm_do_get_edid(connector, read_block, context, NULL); 2410 } 2411 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2412 2413 /** 2414 * drm_edid_raw - Get a pointer to the raw EDID data. 2415 * @drm_edid: drm_edid container 2416 * 2417 * Get a pointer to the raw EDID data. 2418 * 2419 * This is for transition only. Avoid using this like the plague. 2420 * 2421 * Return: Pointer to raw EDID data. 2422 */ 2423 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2424 { 2425 if (!drm_edid || !drm_edid->size) 2426 return NULL; 2427 2428 /* 2429 * Do not return pointers where relying on EDID extension count would 2430 * lead to buffer overflow. 2431 */ 2432 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2433 return NULL; 2434 2435 return drm_edid->edid; 2436 } 2437 EXPORT_SYMBOL(drm_edid_raw); 2438 2439 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2440 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2441 { 2442 struct drm_edid *drm_edid; 2443 2444 if (!edid || !size || size < EDID_LENGTH) 2445 return NULL; 2446 2447 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2448 if (drm_edid) { 2449 drm_edid->edid = edid; 2450 drm_edid->size = size; 2451 } 2452 2453 return drm_edid; 2454 } 2455 2456 /** 2457 * drm_edid_alloc - Allocate a new drm_edid container 2458 * @edid: Pointer to raw EDID data 2459 * @size: Size of memory allocated for EDID 2460 * 2461 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2462 * the actual size that has been allocated for the data. There is no validation 2463 * of the raw EDID data against the size, but at least the EDID base block must 2464 * fit in the buffer. 2465 * 2466 * The returned pointer must be freed using drm_edid_free(). 2467 * 2468 * Return: drm_edid container, or NULL on errors 2469 */ 2470 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2471 { 2472 const struct drm_edid *drm_edid; 2473 2474 if (!edid || !size || size < EDID_LENGTH) 2475 return NULL; 2476 2477 edid = kmemdup(edid, size, GFP_KERNEL); 2478 if (!edid) 2479 return NULL; 2480 2481 drm_edid = _drm_edid_alloc(edid, size); 2482 if (!drm_edid) 2483 kfree(edid); 2484 2485 return drm_edid; 2486 } 2487 EXPORT_SYMBOL(drm_edid_alloc); 2488 2489 /** 2490 * drm_edid_dup - Duplicate a drm_edid container 2491 * @drm_edid: EDID to duplicate 2492 * 2493 * The returned pointer must be freed using drm_edid_free(). 2494 * 2495 * Returns: drm_edid container copy, or NULL on errors 2496 */ 2497 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2498 { 2499 if (!drm_edid) 2500 return NULL; 2501 2502 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2503 } 2504 EXPORT_SYMBOL(drm_edid_dup); 2505 2506 /** 2507 * drm_edid_free - Free the drm_edid container 2508 * @drm_edid: EDID to free 2509 */ 2510 void drm_edid_free(const struct drm_edid *drm_edid) 2511 { 2512 if (!drm_edid) 2513 return; 2514 2515 kfree(drm_edid->edid); 2516 kfree(drm_edid); 2517 } 2518 EXPORT_SYMBOL(drm_edid_free); 2519 2520 /** 2521 * drm_probe_ddc() - probe DDC presence 2522 * @adapter: I2C adapter to probe 2523 * 2524 * Return: True on success, false on failure. 2525 */ 2526 bool 2527 drm_probe_ddc(struct i2c_adapter *adapter) 2528 { 2529 unsigned char out; 2530 2531 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2532 } 2533 EXPORT_SYMBOL(drm_probe_ddc); 2534 2535 /** 2536 * drm_get_edid - get EDID data, if available 2537 * @connector: connector we're probing 2538 * @adapter: I2C adapter to use for DDC 2539 * 2540 * Poke the given I2C channel to grab EDID data if possible. If found, 2541 * attach it to the connector. 2542 * 2543 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2544 */ 2545 struct edid *drm_get_edid(struct drm_connector *connector, 2546 struct i2c_adapter *adapter) 2547 { 2548 struct edid *edid; 2549 2550 if (connector->force == DRM_FORCE_OFF) 2551 return NULL; 2552 2553 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2554 return NULL; 2555 2556 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2557 drm_connector_update_edid_property(connector, edid); 2558 return edid; 2559 } 2560 EXPORT_SYMBOL(drm_get_edid); 2561 2562 /** 2563 * drm_edid_read_custom - Read EDID data using given EDID block read function 2564 * @connector: Connector to use 2565 * @read_block: EDID block read function 2566 * @context: Private data passed to the block read function 2567 * 2568 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2569 * exposes a different interface to read EDID blocks this function can be used 2570 * to get EDID data using a custom block read function. 2571 * 2572 * As in the general case the DDC bus is accessible by the kernel at the I2C 2573 * level, drivers must make all reasonable efforts to expose it as an I2C 2574 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2575 * this function. 2576 * 2577 * The EDID may be overridden using debugfs override_edid or firmware EDID 2578 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2579 * order. Having either of them bypasses actual EDID reads. 2580 * 2581 * The returned pointer must be freed using drm_edid_free(). 2582 * 2583 * Return: Pointer to EDID, or NULL if probe/read failed. 2584 */ 2585 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2586 read_block_fn read_block, 2587 void *context) 2588 { 2589 const struct drm_edid *drm_edid; 2590 struct edid *edid; 2591 size_t size = 0; 2592 2593 edid = _drm_do_get_edid(connector, read_block, context, &size); 2594 if (!edid) 2595 return NULL; 2596 2597 /* Sanity check for now */ 2598 drm_WARN_ON(connector->dev, !size); 2599 2600 drm_edid = _drm_edid_alloc(edid, size); 2601 if (!drm_edid) 2602 kfree(edid); 2603 2604 return drm_edid; 2605 } 2606 EXPORT_SYMBOL(drm_edid_read_custom); 2607 2608 /** 2609 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2610 * @connector: Connector to use 2611 * @adapter: I2C adapter to use for DDC 2612 * 2613 * Read EDID using the given I2C adapter. 2614 * 2615 * The EDID may be overridden using debugfs override_edid or firmware EDID 2616 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2617 * order. Having either of them bypasses actual EDID reads. 2618 * 2619 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2620 * using drm_edid_read() instead of this function. 2621 * 2622 * The returned pointer must be freed using drm_edid_free(). 2623 * 2624 * Return: Pointer to EDID, or NULL if probe/read failed. 2625 */ 2626 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2627 struct i2c_adapter *adapter) 2628 { 2629 const struct drm_edid *drm_edid; 2630 2631 if (connector->force == DRM_FORCE_OFF) 2632 return NULL; 2633 2634 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2635 return NULL; 2636 2637 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2638 2639 /* Note: Do *not* call connector updates here. */ 2640 2641 return drm_edid; 2642 } 2643 EXPORT_SYMBOL(drm_edid_read_ddc); 2644 2645 /** 2646 * drm_edid_read - Read EDID data using connector's I2C adapter 2647 * @connector: Connector to use 2648 * 2649 * Read EDID using the connector's I2C adapter. 2650 * 2651 * The EDID may be overridden using debugfs override_edid or firmware EDID 2652 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2653 * order. Having either of them bypasses actual EDID reads. 2654 * 2655 * The returned pointer must be freed using drm_edid_free(). 2656 * 2657 * Return: Pointer to EDID, or NULL if probe/read failed. 2658 */ 2659 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2660 { 2661 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2662 return NULL; 2663 2664 return drm_edid_read_ddc(connector, connector->ddc); 2665 } 2666 EXPORT_SYMBOL(drm_edid_read); 2667 2668 static u32 edid_extract_panel_id(const struct edid *edid) 2669 { 2670 /* 2671 * We represent the ID as a 32-bit number so it can easily be compared 2672 * with "==". 2673 * 2674 * NOTE that we deal with endianness differently for the top half 2675 * of this ID than for the bottom half. The bottom half (the product 2676 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2677 * that's how everyone seems to interpret it. The top half (the mfg_id) 2678 * gets stored as big endian because that makes 2679 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2680 * to write (it's easier to extract the ASCII). It doesn't really 2681 * matter, though, as long as the number here is unique. 2682 */ 2683 return (u32)edid->mfg_id[0] << 24 | 2684 (u32)edid->mfg_id[1] << 16 | 2685 (u32)EDID_PRODUCT_ID(edid); 2686 } 2687 2688 /** 2689 * drm_edid_get_panel_id - Get a panel's ID through DDC 2690 * @adapter: I2C adapter to use for DDC 2691 * 2692 * This function reads the first block of the EDID of a panel and (assuming 2693 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2694 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2695 * supposed to be different for each different modem of panel. 2696 * 2697 * This function is intended to be used during early probing on devices where 2698 * more than one panel might be present. Because of its intended use it must 2699 * assume that the EDID of the panel is correct, at least as far as the ID 2700 * is concerned (in other words, we don't process any overrides here). 2701 * 2702 * NOTE: it's expected that this function and drm_do_get_edid() will both 2703 * be read the EDID, but there is no caching between them. Since we're only 2704 * reading the first block, hopefully this extra overhead won't be too big. 2705 * 2706 * Return: A 32-bit ID that should be different for each make/model of panel. 2707 * See the functions drm_edid_encode_panel_id() and 2708 * drm_edid_decode_panel_id() for some details on the structure of this 2709 * ID. 2710 */ 2711 2712 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2713 { 2714 enum edid_block_status status; 2715 void *base_block; 2716 u32 panel_id = 0; 2717 2718 /* 2719 * There are no manufacturer IDs of 0, so if there is a problem reading 2720 * the EDID then we'll just return 0. 2721 */ 2722 2723 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); 2724 if (!base_block) 2725 return 0; 2726 2727 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2728 2729 edid_block_status_print(status, base_block, 0); 2730 2731 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2732 panel_id = edid_extract_panel_id(base_block); 2733 2734 kfree(base_block); 2735 2736 return panel_id; 2737 } 2738 EXPORT_SYMBOL(drm_edid_get_panel_id); 2739 2740 /** 2741 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2742 * @connector: connector we're probing 2743 * @adapter: I2C adapter to use for DDC 2744 * 2745 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2746 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2747 * switch DDC to the GPU which is retrieving EDID. 2748 * 2749 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2750 */ 2751 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2752 struct i2c_adapter *adapter) 2753 { 2754 struct drm_device *dev = connector->dev; 2755 struct pci_dev *pdev = to_pci_dev(dev->dev); 2756 struct edid *edid; 2757 2758 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2759 return NULL; 2760 2761 vga_switcheroo_lock_ddc(pdev); 2762 edid = drm_get_edid(connector, adapter); 2763 vga_switcheroo_unlock_ddc(pdev); 2764 2765 return edid; 2766 } 2767 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2768 2769 /** 2770 * drm_edid_duplicate - duplicate an EDID and the extensions 2771 * @edid: EDID to duplicate 2772 * 2773 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2774 */ 2775 struct edid *drm_edid_duplicate(const struct edid *edid) 2776 { 2777 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2778 } 2779 EXPORT_SYMBOL(drm_edid_duplicate); 2780 2781 /*** EDID parsing ***/ 2782 2783 /** 2784 * edid_get_quirks - return quirk flags for a given EDID 2785 * @drm_edid: EDID to process 2786 * 2787 * This tells subsequent routines what fixes they need to apply. 2788 */ 2789 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2790 { 2791 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2792 const struct edid_quirk *quirk; 2793 int i; 2794 2795 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2796 quirk = &edid_quirk_list[i]; 2797 if (quirk->panel_id == panel_id) 2798 return quirk->quirks; 2799 } 2800 2801 return 0; 2802 } 2803 2804 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2805 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2806 2807 /* 2808 * Walk the mode list for connector, clearing the preferred status on existing 2809 * modes and setting it anew for the right mode ala quirks. 2810 */ 2811 static void edid_fixup_preferred(struct drm_connector *connector, 2812 u32 quirks) 2813 { 2814 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2815 int target_refresh = 0; 2816 int cur_vrefresh, preferred_vrefresh; 2817 2818 if (list_empty(&connector->probed_modes)) 2819 return; 2820 2821 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2822 target_refresh = 60; 2823 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2824 target_refresh = 75; 2825 2826 preferred_mode = list_first_entry(&connector->probed_modes, 2827 struct drm_display_mode, head); 2828 2829 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2830 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2831 2832 if (cur_mode == preferred_mode) 2833 continue; 2834 2835 /* Largest mode is preferred */ 2836 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2837 preferred_mode = cur_mode; 2838 2839 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2840 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2841 /* At a given size, try to get closest to target refresh */ 2842 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2843 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2844 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2845 preferred_mode = cur_mode; 2846 } 2847 } 2848 2849 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2850 } 2851 2852 static bool 2853 mode_is_rb(const struct drm_display_mode *mode) 2854 { 2855 return (mode->htotal - mode->hdisplay == 160) && 2856 (mode->hsync_end - mode->hdisplay == 80) && 2857 (mode->hsync_end - mode->hsync_start == 32) && 2858 (mode->vsync_start - mode->vdisplay == 3); 2859 } 2860 2861 /* 2862 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2863 * @dev: Device to duplicate against 2864 * @hsize: Mode width 2865 * @vsize: Mode height 2866 * @fresh: Mode refresh rate 2867 * @rb: Mode reduced-blanking-ness 2868 * 2869 * Walk the DMT mode list looking for a match for the given parameters. 2870 * 2871 * Return: A newly allocated copy of the mode, or NULL if not found. 2872 */ 2873 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2874 int hsize, int vsize, int fresh, 2875 bool rb) 2876 { 2877 int i; 2878 2879 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2880 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2881 2882 if (hsize != ptr->hdisplay) 2883 continue; 2884 if (vsize != ptr->vdisplay) 2885 continue; 2886 if (fresh != drm_mode_vrefresh(ptr)) 2887 continue; 2888 if (rb != mode_is_rb(ptr)) 2889 continue; 2890 2891 return drm_mode_duplicate(dev, ptr); 2892 } 2893 2894 return NULL; 2895 } 2896 EXPORT_SYMBOL(drm_mode_find_dmt); 2897 2898 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2899 { 2900 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2901 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2902 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2903 2904 return descriptor->pixel_clock == 0 && 2905 descriptor->data.other_data.pad1 == 0 && 2906 descriptor->data.other_data.type == type; 2907 } 2908 2909 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2910 { 2911 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2912 2913 return descriptor->pixel_clock != 0; 2914 } 2915 2916 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2917 2918 static void 2919 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2920 { 2921 int i, n; 2922 u8 d = ext[0x02]; 2923 const u8 *det_base = ext + d; 2924 2925 if (d < 4 || d > 127) 2926 return; 2927 2928 n = (127 - d) / 18; 2929 for (i = 0; i < n; i++) 2930 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2931 } 2932 2933 static void 2934 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2935 { 2936 unsigned int i, n = min((int)ext[0x02], 6); 2937 const u8 *det_base = ext + 5; 2938 2939 if (ext[0x01] != 1) 2940 return; /* unknown version */ 2941 2942 for (i = 0; i < n; i++) 2943 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2944 } 2945 2946 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 2947 detailed_cb *cb, void *closure) 2948 { 2949 struct drm_edid_iter edid_iter; 2950 const u8 *ext; 2951 int i; 2952 2953 if (!drm_edid) 2954 return; 2955 2956 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2957 cb(&drm_edid->edid->detailed_timings[i], closure); 2958 2959 drm_edid_iter_begin(drm_edid, &edid_iter); 2960 drm_edid_iter_for_each(ext, &edid_iter) { 2961 switch (*ext) { 2962 case CEA_EXT: 2963 cea_for_each_detailed_block(ext, cb, closure); 2964 break; 2965 case VTB_EXT: 2966 vtb_for_each_detailed_block(ext, cb, closure); 2967 break; 2968 default: 2969 break; 2970 } 2971 } 2972 drm_edid_iter_end(&edid_iter); 2973 } 2974 2975 static void 2976 is_rb(const struct detailed_timing *descriptor, void *data) 2977 { 2978 bool *res = data; 2979 2980 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2981 return; 2982 2983 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2984 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 2985 2986 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 2987 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) 2988 *res = true; 2989 } 2990 2991 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2992 static bool 2993 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 2994 { 2995 if (drm_edid->edid->revision >= 4) { 2996 bool ret = false; 2997 2998 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 2999 return ret; 3000 } 3001 3002 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3003 } 3004 3005 static void 3006 find_gtf2(const struct detailed_timing *descriptor, void *data) 3007 { 3008 const struct detailed_timing **res = data; 3009 3010 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3011 return; 3012 3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3014 3015 if (descriptor->data.other_data.data.range.flags == 0x02) 3016 *res = descriptor; 3017 } 3018 3019 /* Secondary GTF curve kicks in above some break frequency */ 3020 static int 3021 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3022 { 3023 const struct detailed_timing *descriptor = NULL; 3024 3025 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3026 3027 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3028 3029 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3030 } 3031 3032 static int 3033 drm_gtf2_2c(const struct drm_edid *drm_edid) 3034 { 3035 const struct detailed_timing *descriptor = NULL; 3036 3037 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3038 3039 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3040 3041 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3042 } 3043 3044 static int 3045 drm_gtf2_m(const struct drm_edid *drm_edid) 3046 { 3047 const struct detailed_timing *descriptor = NULL; 3048 3049 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3050 3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3052 3053 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3054 } 3055 3056 static int 3057 drm_gtf2_k(const struct drm_edid *drm_edid) 3058 { 3059 const struct detailed_timing *descriptor = NULL; 3060 3061 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3062 3063 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3064 3065 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3066 } 3067 3068 static int 3069 drm_gtf2_2j(const struct drm_edid *drm_edid) 3070 { 3071 const struct detailed_timing *descriptor = NULL; 3072 3073 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3074 3075 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3076 3077 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3078 } 3079 3080 /* Get standard timing level (CVT/GTF/DMT). */ 3081 static int standard_timing_level(const struct drm_edid *drm_edid) 3082 { 3083 const struct edid *edid = drm_edid->edid; 3084 3085 if (edid->revision >= 2) { 3086 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3087 return LEVEL_CVT; 3088 if (drm_gtf2_hbreak(drm_edid)) 3089 return LEVEL_GTF2; 3090 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3091 return LEVEL_GTF; 3092 } 3093 return LEVEL_DMT; 3094 } 3095 3096 /* 3097 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3098 * monitors fill with ascii space (0x20) instead. 3099 */ 3100 static int 3101 bad_std_timing(u8 a, u8 b) 3102 { 3103 return (a == 0x00 && b == 0x00) || 3104 (a == 0x01 && b == 0x01) || 3105 (a == 0x20 && b == 0x20); 3106 } 3107 3108 static int drm_mode_hsync(const struct drm_display_mode *mode) 3109 { 3110 if (mode->htotal <= 0) 3111 return 0; 3112 3113 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3114 } 3115 3116 /* 3117 * Take the standard timing params (in this case width, aspect, and refresh) 3118 * and convert them into a real mode using CVT/GTF/DMT. 3119 */ 3120 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3121 const struct drm_edid *drm_edid, 3122 const struct std_timing *t) 3123 { 3124 struct drm_device *dev = connector->dev; 3125 struct drm_display_mode *m, *mode = NULL; 3126 int hsize, vsize; 3127 int vrefresh_rate; 3128 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3129 >> EDID_TIMING_ASPECT_SHIFT; 3130 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3131 >> EDID_TIMING_VFREQ_SHIFT; 3132 int timing_level = standard_timing_level(drm_edid); 3133 3134 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3135 return NULL; 3136 3137 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3138 hsize = t->hsize * 8 + 248; 3139 /* vrefresh_rate = vfreq + 60 */ 3140 vrefresh_rate = vfreq + 60; 3141 /* the vdisplay is calculated based on the aspect ratio */ 3142 if (aspect_ratio == 0) { 3143 if (drm_edid->edid->revision < 3) 3144 vsize = hsize; 3145 else 3146 vsize = (hsize * 10) / 16; 3147 } else if (aspect_ratio == 1) 3148 vsize = (hsize * 3) / 4; 3149 else if (aspect_ratio == 2) 3150 vsize = (hsize * 4) / 5; 3151 else 3152 vsize = (hsize * 9) / 16; 3153 3154 /* HDTV hack, part 1 */ 3155 if (vrefresh_rate == 60 && 3156 ((hsize == 1360 && vsize == 765) || 3157 (hsize == 1368 && vsize == 769))) { 3158 hsize = 1366; 3159 vsize = 768; 3160 } 3161 3162 /* 3163 * If this connector already has a mode for this size and refresh 3164 * rate (because it came from detailed or CVT info), use that 3165 * instead. This way we don't have to guess at interlace or 3166 * reduced blanking. 3167 */ 3168 list_for_each_entry(m, &connector->probed_modes, head) 3169 if (m->hdisplay == hsize && m->vdisplay == vsize && 3170 drm_mode_vrefresh(m) == vrefresh_rate) 3171 return NULL; 3172 3173 /* HDTV hack, part 2 */ 3174 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3175 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3176 false); 3177 if (!mode) 3178 return NULL; 3179 mode->hdisplay = 1366; 3180 mode->hsync_start = mode->hsync_start - 1; 3181 mode->hsync_end = mode->hsync_end - 1; 3182 return mode; 3183 } 3184 3185 /* check whether it can be found in default mode table */ 3186 if (drm_monitor_supports_rb(drm_edid)) { 3187 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3188 true); 3189 if (mode) 3190 return mode; 3191 } 3192 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3193 if (mode) 3194 return mode; 3195 3196 /* okay, generate it */ 3197 switch (timing_level) { 3198 case LEVEL_DMT: 3199 break; 3200 case LEVEL_GTF: 3201 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3202 break; 3203 case LEVEL_GTF2: 3204 /* 3205 * This is potentially wrong if there's ever a monitor with 3206 * more than one ranges section, each claiming a different 3207 * secondary GTF curve. Please don't do that. 3208 */ 3209 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3210 if (!mode) 3211 return NULL; 3212 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3213 drm_mode_destroy(dev, mode); 3214 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3215 vrefresh_rate, 0, 0, 3216 drm_gtf2_m(drm_edid), 3217 drm_gtf2_2c(drm_edid), 3218 drm_gtf2_k(drm_edid), 3219 drm_gtf2_2j(drm_edid)); 3220 } 3221 break; 3222 case LEVEL_CVT: 3223 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3224 false); 3225 break; 3226 } 3227 return mode; 3228 } 3229 3230 /* 3231 * EDID is delightfully ambiguous about how interlaced modes are to be 3232 * encoded. Our internal representation is of frame height, but some 3233 * HDTV detailed timings are encoded as field height. 3234 * 3235 * The format list here is from CEA, in frame size. Technically we 3236 * should be checking refresh rate too. Whatever. 3237 */ 3238 static void 3239 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3240 const struct detailed_pixel_timing *pt) 3241 { 3242 int i; 3243 static const struct { 3244 int w, h; 3245 } cea_interlaced[] = { 3246 { 1920, 1080 }, 3247 { 720, 480 }, 3248 { 1440, 480 }, 3249 { 2880, 480 }, 3250 { 720, 576 }, 3251 { 1440, 576 }, 3252 { 2880, 576 }, 3253 }; 3254 3255 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3256 return; 3257 3258 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3259 if ((mode->hdisplay == cea_interlaced[i].w) && 3260 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3261 mode->vdisplay *= 2; 3262 mode->vsync_start *= 2; 3263 mode->vsync_end *= 2; 3264 mode->vtotal *= 2; 3265 mode->vtotal |= 1; 3266 } 3267 } 3268 3269 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3270 } 3271 3272 /* 3273 * Create a new mode from an EDID detailed timing section. An EDID detailed 3274 * timing block contains enough info for us to create and return a new struct 3275 * drm_display_mode. 3276 */ 3277 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 3278 const struct drm_edid *drm_edid, 3279 const struct detailed_timing *timing, 3280 u32 quirks) 3281 { 3282 struct drm_display_mode *mode; 3283 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3284 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3285 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3286 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3287 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3288 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3289 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3290 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3291 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3292 3293 /* ignore tiny modes */ 3294 if (hactive < 64 || vactive < 64) 3295 return NULL; 3296 3297 if (pt->misc & DRM_EDID_PT_STEREO) { 3298 DRM_DEBUG_KMS("stereo mode not supported\n"); 3299 return NULL; 3300 } 3301 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3302 DRM_DEBUG_KMS("composite sync not supported\n"); 3303 } 3304 3305 /* it is incorrect if hsync/vsync width is zero */ 3306 if (!hsync_pulse_width || !vsync_pulse_width) { 3307 DRM_DEBUG_KMS("Incorrect Detailed timing. " 3308 "Wrong Hsync/Vsync pulse width\n"); 3309 return NULL; 3310 } 3311 3312 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3313 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3314 if (!mode) 3315 return NULL; 3316 3317 goto set_size; 3318 } 3319 3320 mode = drm_mode_create(dev); 3321 if (!mode) 3322 return NULL; 3323 3324 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3325 mode->clock = 1088 * 10; 3326 else 3327 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3328 3329 mode->hdisplay = hactive; 3330 mode->hsync_start = mode->hdisplay + hsync_offset; 3331 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3332 mode->htotal = mode->hdisplay + hblank; 3333 3334 mode->vdisplay = vactive; 3335 mode->vsync_start = mode->vdisplay + vsync_offset; 3336 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3337 mode->vtotal = mode->vdisplay + vblank; 3338 3339 /* Some EDIDs have bogus h/vtotal values */ 3340 if (mode->hsync_end > mode->htotal) 3341 mode->htotal = mode->hsync_end + 1; 3342 if (mode->vsync_end > mode->vtotal) 3343 mode->vtotal = mode->vsync_end + 1; 3344 3345 drm_mode_do_interlace_quirk(mode, pt); 3346 3347 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3348 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3349 } else { 3350 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3351 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3352 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3353 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3354 } 3355 3356 set_size: 3357 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3358 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3359 3360 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 3361 mode->width_mm *= 10; 3362 mode->height_mm *= 10; 3363 } 3364 3365 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3366 mode->width_mm = drm_edid->edid->width_cm * 10; 3367 mode->height_mm = drm_edid->edid->height_cm * 10; 3368 } 3369 3370 mode->type = DRM_MODE_TYPE_DRIVER; 3371 drm_mode_set_name(mode); 3372 3373 return mode; 3374 } 3375 3376 static bool 3377 mode_in_hsync_range(const struct drm_display_mode *mode, 3378 const struct edid *edid, const u8 *t) 3379 { 3380 int hsync, hmin, hmax; 3381 3382 hmin = t[7]; 3383 if (edid->revision >= 4) 3384 hmin += ((t[4] & 0x04) ? 255 : 0); 3385 hmax = t[8]; 3386 if (edid->revision >= 4) 3387 hmax += ((t[4] & 0x08) ? 255 : 0); 3388 hsync = drm_mode_hsync(mode); 3389 3390 return (hsync <= hmax && hsync >= hmin); 3391 } 3392 3393 static bool 3394 mode_in_vsync_range(const struct drm_display_mode *mode, 3395 const struct edid *edid, const u8 *t) 3396 { 3397 int vsync, vmin, vmax; 3398 3399 vmin = t[5]; 3400 if (edid->revision >= 4) 3401 vmin += ((t[4] & 0x01) ? 255 : 0); 3402 vmax = t[6]; 3403 if (edid->revision >= 4) 3404 vmax += ((t[4] & 0x02) ? 255 : 0); 3405 vsync = drm_mode_vrefresh(mode); 3406 3407 return (vsync <= vmax && vsync >= vmin); 3408 } 3409 3410 static u32 3411 range_pixel_clock(const struct edid *edid, const u8 *t) 3412 { 3413 /* unspecified */ 3414 if (t[9] == 0 || t[9] == 255) 3415 return 0; 3416 3417 /* 1.4 with CVT support gives us real precision, yay */ 3418 if (edid->revision >= 4 && t[10] == 0x04) 3419 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3420 3421 /* 1.3 is pathetic, so fuzz up a bit */ 3422 return t[9] * 10000 + 5001; 3423 } 3424 3425 static bool mode_in_range(const struct drm_display_mode *mode, 3426 const struct drm_edid *drm_edid, 3427 const struct detailed_timing *timing) 3428 { 3429 const struct edid *edid = drm_edid->edid; 3430 u32 max_clock; 3431 const u8 *t = (const u8 *)timing; 3432 3433 if (!mode_in_hsync_range(mode, edid, t)) 3434 return false; 3435 3436 if (!mode_in_vsync_range(mode, edid, t)) 3437 return false; 3438 3439 if ((max_clock = range_pixel_clock(edid, t))) 3440 if (mode->clock > max_clock) 3441 return false; 3442 3443 /* 1.4 max horizontal check */ 3444 if (edid->revision >= 4 && t[10] == 0x04) 3445 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3446 return false; 3447 3448 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3449 return false; 3450 3451 return true; 3452 } 3453 3454 static bool valid_inferred_mode(const struct drm_connector *connector, 3455 const struct drm_display_mode *mode) 3456 { 3457 const struct drm_display_mode *m; 3458 bool ok = false; 3459 3460 list_for_each_entry(m, &connector->probed_modes, head) { 3461 if (mode->hdisplay == m->hdisplay && 3462 mode->vdisplay == m->vdisplay && 3463 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3464 return false; /* duplicated */ 3465 if (mode->hdisplay <= m->hdisplay && 3466 mode->vdisplay <= m->vdisplay) 3467 ok = true; 3468 } 3469 return ok; 3470 } 3471 3472 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3473 const struct drm_edid *drm_edid, 3474 const struct detailed_timing *timing) 3475 { 3476 int i, modes = 0; 3477 struct drm_display_mode *newmode; 3478 struct drm_device *dev = connector->dev; 3479 3480 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3481 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3482 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3483 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3484 if (newmode) { 3485 drm_mode_probed_add(connector, newmode); 3486 modes++; 3487 } 3488 } 3489 } 3490 3491 return modes; 3492 } 3493 3494 /* fix up 1366x768 mode from 1368x768; 3495 * GFT/CVT can't express 1366 width which isn't dividable by 8 3496 */ 3497 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3498 { 3499 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3500 mode->hdisplay = 1366; 3501 mode->hsync_start--; 3502 mode->hsync_end--; 3503 drm_mode_set_name(mode); 3504 } 3505 } 3506 3507 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3508 const struct drm_edid *drm_edid, 3509 const struct detailed_timing *timing) 3510 { 3511 int i, modes = 0; 3512 struct drm_display_mode *newmode; 3513 struct drm_device *dev = connector->dev; 3514 3515 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3516 const struct minimode *m = &extra_modes[i]; 3517 3518 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3519 if (!newmode) 3520 return modes; 3521 3522 drm_mode_fixup_1366x768(newmode); 3523 if (!mode_in_range(newmode, drm_edid, timing) || 3524 !valid_inferred_mode(connector, newmode)) { 3525 drm_mode_destroy(dev, newmode); 3526 continue; 3527 } 3528 3529 drm_mode_probed_add(connector, newmode); 3530 modes++; 3531 } 3532 3533 return modes; 3534 } 3535 3536 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3537 const struct drm_edid *drm_edid, 3538 const struct detailed_timing *timing) 3539 { 3540 int i, modes = 0; 3541 struct drm_display_mode *newmode; 3542 struct drm_device *dev = connector->dev; 3543 bool rb = drm_monitor_supports_rb(drm_edid); 3544 3545 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3546 const struct minimode *m = &extra_modes[i]; 3547 3548 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3549 if (!newmode) 3550 return modes; 3551 3552 drm_mode_fixup_1366x768(newmode); 3553 if (!mode_in_range(newmode, drm_edid, timing) || 3554 !valid_inferred_mode(connector, newmode)) { 3555 drm_mode_destroy(dev, newmode); 3556 continue; 3557 } 3558 3559 drm_mode_probed_add(connector, newmode); 3560 modes++; 3561 } 3562 3563 return modes; 3564 } 3565 3566 static void 3567 do_inferred_modes(const struct detailed_timing *timing, void *c) 3568 { 3569 struct detailed_mode_closure *closure = c; 3570 const struct detailed_non_pixel *data = &timing->data.other_data; 3571 const struct detailed_data_monitor_range *range = &data->data.range; 3572 3573 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3574 return; 3575 3576 closure->modes += drm_dmt_modes_for_range(closure->connector, 3577 closure->drm_edid, 3578 timing); 3579 3580 if (!version_greater(closure->drm_edid, 1, 1)) 3581 return; /* GTF not defined yet */ 3582 3583 switch (range->flags) { 3584 case 0x02: /* secondary gtf, XXX could do more */ 3585 case 0x00: /* default gtf */ 3586 closure->modes += drm_gtf_modes_for_range(closure->connector, 3587 closure->drm_edid, 3588 timing); 3589 break; 3590 case 0x04: /* cvt, only in 1.4+ */ 3591 if (!version_greater(closure->drm_edid, 1, 3)) 3592 break; 3593 3594 closure->modes += drm_cvt_modes_for_range(closure->connector, 3595 closure->drm_edid, 3596 timing); 3597 break; 3598 case 0x01: /* just the ranges, no formula */ 3599 default: 3600 break; 3601 } 3602 } 3603 3604 static int add_inferred_modes(struct drm_connector *connector, 3605 const struct drm_edid *drm_edid) 3606 { 3607 struct detailed_mode_closure closure = { 3608 .connector = connector, 3609 .drm_edid = drm_edid, 3610 }; 3611 3612 if (version_greater(drm_edid, 1, 0)) 3613 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3614 3615 return closure.modes; 3616 } 3617 3618 static int 3619 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3620 { 3621 int i, j, m, modes = 0; 3622 struct drm_display_mode *mode; 3623 const u8 *est = ((const u8 *)timing) + 6; 3624 3625 for (i = 0; i < 6; i++) { 3626 for (j = 7; j >= 0; j--) { 3627 m = (i * 8) + (7 - j); 3628 if (m >= ARRAY_SIZE(est3_modes)) 3629 break; 3630 if (est[i] & (1 << j)) { 3631 mode = drm_mode_find_dmt(connector->dev, 3632 est3_modes[m].w, 3633 est3_modes[m].h, 3634 est3_modes[m].r, 3635 est3_modes[m].rb); 3636 if (mode) { 3637 drm_mode_probed_add(connector, mode); 3638 modes++; 3639 } 3640 } 3641 } 3642 } 3643 3644 return modes; 3645 } 3646 3647 static void 3648 do_established_modes(const struct detailed_timing *timing, void *c) 3649 { 3650 struct detailed_mode_closure *closure = c; 3651 3652 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3653 return; 3654 3655 closure->modes += drm_est3_modes(closure->connector, timing); 3656 } 3657 3658 /* 3659 * Get established modes from EDID and add them. Each EDID block contains a 3660 * bitmap of the supported "established modes" list (defined above). Tease them 3661 * out and add them to the global modes list. 3662 */ 3663 static int add_established_modes(struct drm_connector *connector, 3664 const struct drm_edid *drm_edid) 3665 { 3666 struct drm_device *dev = connector->dev; 3667 const struct edid *edid = drm_edid->edid; 3668 unsigned long est_bits = edid->established_timings.t1 | 3669 (edid->established_timings.t2 << 8) | 3670 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3671 int i, modes = 0; 3672 struct detailed_mode_closure closure = { 3673 .connector = connector, 3674 .drm_edid = drm_edid, 3675 }; 3676 3677 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3678 if (est_bits & (1<<i)) { 3679 struct drm_display_mode *newmode; 3680 3681 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3682 if (newmode) { 3683 drm_mode_probed_add(connector, newmode); 3684 modes++; 3685 } 3686 } 3687 } 3688 3689 if (version_greater(drm_edid, 1, 0)) 3690 drm_for_each_detailed_block(drm_edid, do_established_modes, 3691 &closure); 3692 3693 return modes + closure.modes; 3694 } 3695 3696 static void 3697 do_standard_modes(const struct detailed_timing *timing, void *c) 3698 { 3699 struct detailed_mode_closure *closure = c; 3700 const struct detailed_non_pixel *data = &timing->data.other_data; 3701 struct drm_connector *connector = closure->connector; 3702 int i; 3703 3704 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3705 return; 3706 3707 for (i = 0; i < 6; i++) { 3708 const struct std_timing *std = &data->data.timings[i]; 3709 struct drm_display_mode *newmode; 3710 3711 newmode = drm_mode_std(connector, closure->drm_edid, std); 3712 if (newmode) { 3713 drm_mode_probed_add(connector, newmode); 3714 closure->modes++; 3715 } 3716 } 3717 } 3718 3719 /* 3720 * Get standard modes from EDID and add them. Standard modes can be calculated 3721 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3722 * add them to the list. 3723 */ 3724 static int add_standard_modes(struct drm_connector *connector, 3725 const struct drm_edid *drm_edid) 3726 { 3727 int i, modes = 0; 3728 struct detailed_mode_closure closure = { 3729 .connector = connector, 3730 .drm_edid = drm_edid, 3731 }; 3732 3733 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3734 struct drm_display_mode *newmode; 3735 3736 newmode = drm_mode_std(connector, drm_edid, 3737 &drm_edid->edid->standard_timings[i]); 3738 if (newmode) { 3739 drm_mode_probed_add(connector, newmode); 3740 modes++; 3741 } 3742 } 3743 3744 if (version_greater(drm_edid, 1, 0)) 3745 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3746 &closure); 3747 3748 /* XXX should also look for standard codes in VTB blocks */ 3749 3750 return modes + closure.modes; 3751 } 3752 3753 static int drm_cvt_modes(struct drm_connector *connector, 3754 const struct detailed_timing *timing) 3755 { 3756 int i, j, modes = 0; 3757 struct drm_display_mode *newmode; 3758 struct drm_device *dev = connector->dev; 3759 const struct cvt_timing *cvt; 3760 const int rates[] = { 60, 85, 75, 60, 50 }; 3761 const u8 empty[3] = { 0, 0, 0 }; 3762 3763 for (i = 0; i < 4; i++) { 3764 int width, height; 3765 3766 cvt = &(timing->data.other_data.data.cvt[i]); 3767 3768 if (!memcmp(cvt->code, empty, 3)) 3769 continue; 3770 3771 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3772 switch (cvt->code[1] & 0x0c) { 3773 /* default - because compiler doesn't see that we've enumerated all cases */ 3774 default: 3775 case 0x00: 3776 width = height * 4 / 3; 3777 break; 3778 case 0x04: 3779 width = height * 16 / 9; 3780 break; 3781 case 0x08: 3782 width = height * 16 / 10; 3783 break; 3784 case 0x0c: 3785 width = height * 15 / 9; 3786 break; 3787 } 3788 3789 for (j = 1; j < 5; j++) { 3790 if (cvt->code[2] & (1 << j)) { 3791 newmode = drm_cvt_mode(dev, width, height, 3792 rates[j], j == 0, 3793 false, false); 3794 if (newmode) { 3795 drm_mode_probed_add(connector, newmode); 3796 modes++; 3797 } 3798 } 3799 } 3800 } 3801 3802 return modes; 3803 } 3804 3805 static void 3806 do_cvt_mode(const struct detailed_timing *timing, void *c) 3807 { 3808 struct detailed_mode_closure *closure = c; 3809 3810 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3811 return; 3812 3813 closure->modes += drm_cvt_modes(closure->connector, timing); 3814 } 3815 3816 static int 3817 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 3818 { 3819 struct detailed_mode_closure closure = { 3820 .connector = connector, 3821 .drm_edid = drm_edid, 3822 }; 3823 3824 if (version_greater(drm_edid, 1, 2)) 3825 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 3826 3827 /* XXX should also look for CVT codes in VTB blocks */ 3828 3829 return closure.modes; 3830 } 3831 3832 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3833 3834 static void 3835 do_detailed_mode(const struct detailed_timing *timing, void *c) 3836 { 3837 struct detailed_mode_closure *closure = c; 3838 struct drm_display_mode *newmode; 3839 3840 if (!is_detailed_timing_descriptor(timing)) 3841 return; 3842 3843 newmode = drm_mode_detailed(closure->connector->dev, 3844 closure->drm_edid, timing, 3845 closure->quirks); 3846 if (!newmode) 3847 return; 3848 3849 if (closure->preferred) 3850 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3851 3852 /* 3853 * Detailed modes are limited to 10kHz pixel clock resolution, 3854 * so fix up anything that looks like CEA/HDMI mode, but the clock 3855 * is just slightly off. 3856 */ 3857 fixup_detailed_cea_mode_clock(newmode); 3858 3859 drm_mode_probed_add(closure->connector, newmode); 3860 closure->modes++; 3861 closure->preferred = false; 3862 } 3863 3864 /* 3865 * add_detailed_modes - Add modes from detailed timings 3866 * @connector: attached connector 3867 * @drm_edid: EDID block to scan 3868 * @quirks: quirks to apply 3869 */ 3870 static int add_detailed_modes(struct drm_connector *connector, 3871 const struct drm_edid *drm_edid, u32 quirks) 3872 { 3873 struct detailed_mode_closure closure = { 3874 .connector = connector, 3875 .drm_edid = drm_edid, 3876 .preferred = true, 3877 .quirks = quirks, 3878 }; 3879 3880 if (closure.preferred && !version_greater(drm_edid, 1, 3)) 3881 closure.preferred = 3882 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3883 3884 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 3885 3886 return closure.modes; 3887 } 3888 3889 /* CTA-861-H Table 60 - CTA Tag Codes */ 3890 #define CTA_DB_AUDIO 1 3891 #define CTA_DB_VIDEO 2 3892 #define CTA_DB_VENDOR 3 3893 #define CTA_DB_SPEAKER 4 3894 #define CTA_DB_EXTENDED_TAG 7 3895 3896 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 3897 #define CTA_EXT_DB_VIDEO_CAP 0 3898 #define CTA_EXT_DB_VENDOR 1 3899 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 3900 #define CTA_EXT_DB_420_VIDEO_DATA 14 3901 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 3902 #define CTA_EXT_DB_HF_EEODB 0x78 3903 #define CTA_EXT_DB_HF_SCDB 0x79 3904 3905 #define EDID_BASIC_AUDIO (1 << 6) 3906 #define EDID_CEA_YCRCB444 (1 << 5) 3907 #define EDID_CEA_YCRCB422 (1 << 4) 3908 #define EDID_CEA_VCDB_QS (1 << 6) 3909 3910 /* 3911 * Search EDID for CEA extension block. 3912 * 3913 * FIXME: Prefer not returning pointers to raw EDID data. 3914 */ 3915 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 3916 int ext_id, int *ext_index) 3917 { 3918 const u8 *edid_ext = NULL; 3919 int i; 3920 3921 /* No EDID or EDID extensions */ 3922 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 3923 return NULL; 3924 3925 /* Find CEA extension */ 3926 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 3927 edid_ext = drm_edid_extension_block_data(drm_edid, i); 3928 if (edid_block_tag(edid_ext) == ext_id) 3929 break; 3930 } 3931 3932 if (i >= drm_edid_extension_block_count(drm_edid)) 3933 return NULL; 3934 3935 *ext_index = i + 1; 3936 3937 return edid_ext; 3938 } 3939 3940 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 3941 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 3942 { 3943 const struct displayid_block *block; 3944 struct displayid_iter iter; 3945 int ext_index = 0; 3946 bool found = false; 3947 3948 /* Look for a top level CEA extension block */ 3949 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 3950 return true; 3951 3952 /* CEA blocks can also be found embedded in a DisplayID block */ 3953 displayid_iter_edid_begin(drm_edid, &iter); 3954 displayid_iter_for_each(block, &iter) { 3955 if (block->tag == DATA_BLOCK_CTA) { 3956 found = true; 3957 break; 3958 } 3959 } 3960 displayid_iter_end(&iter); 3961 3962 return found; 3963 } 3964 3965 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3966 { 3967 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3968 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3969 3970 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3971 return &edid_cea_modes_1[vic - 1]; 3972 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3973 return &edid_cea_modes_193[vic - 193]; 3974 return NULL; 3975 } 3976 3977 static u8 cea_num_vics(void) 3978 { 3979 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3980 } 3981 3982 static u8 cea_next_vic(u8 vic) 3983 { 3984 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3985 vic = 193; 3986 return vic; 3987 } 3988 3989 /* 3990 * Calculate the alternate clock for the CEA mode 3991 * (60Hz vs. 59.94Hz etc.) 3992 */ 3993 static unsigned int 3994 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3995 { 3996 unsigned int clock = cea_mode->clock; 3997 3998 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3999 return clock; 4000 4001 /* 4002 * edid_cea_modes contains the 59.94Hz 4003 * variant for 240 and 480 line modes, 4004 * and the 60Hz variant otherwise. 4005 */ 4006 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4007 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4008 else 4009 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4010 4011 return clock; 4012 } 4013 4014 static bool 4015 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4016 { 4017 /* 4018 * For certain VICs the spec allows the vertical 4019 * front porch to vary by one or two lines. 4020 * 4021 * cea_modes[] stores the variant with the shortest 4022 * vertical front porch. We can adjust the mode to 4023 * get the other variants by simply increasing the 4024 * vertical front porch length. 4025 */ 4026 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4027 cea_mode_for_vic(9)->vtotal != 262 || 4028 cea_mode_for_vic(12)->vtotal != 262 || 4029 cea_mode_for_vic(13)->vtotal != 262 || 4030 cea_mode_for_vic(23)->vtotal != 312 || 4031 cea_mode_for_vic(24)->vtotal != 312 || 4032 cea_mode_for_vic(27)->vtotal != 312 || 4033 cea_mode_for_vic(28)->vtotal != 312); 4034 4035 if (((vic == 8 || vic == 9 || 4036 vic == 12 || vic == 13) && mode->vtotal < 263) || 4037 ((vic == 23 || vic == 24 || 4038 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4039 mode->vsync_start++; 4040 mode->vsync_end++; 4041 mode->vtotal++; 4042 4043 return true; 4044 } 4045 4046 return false; 4047 } 4048 4049 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4050 unsigned int clock_tolerance) 4051 { 4052 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4053 u8 vic; 4054 4055 if (!to_match->clock) 4056 return 0; 4057 4058 if (to_match->picture_aspect_ratio) 4059 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4060 4061 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4062 struct drm_display_mode cea_mode; 4063 unsigned int clock1, clock2; 4064 4065 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4066 4067 /* Check both 60Hz and 59.94Hz */ 4068 clock1 = cea_mode.clock; 4069 clock2 = cea_mode_alternate_clock(&cea_mode); 4070 4071 if (abs(to_match->clock - clock1) > clock_tolerance && 4072 abs(to_match->clock - clock2) > clock_tolerance) 4073 continue; 4074 4075 do { 4076 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4077 return vic; 4078 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4079 } 4080 4081 return 0; 4082 } 4083 4084 /** 4085 * drm_match_cea_mode - look for a CEA mode matching given mode 4086 * @to_match: display mode 4087 * 4088 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4089 * mode. 4090 */ 4091 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4092 { 4093 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4094 u8 vic; 4095 4096 if (!to_match->clock) 4097 return 0; 4098 4099 if (to_match->picture_aspect_ratio) 4100 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4101 4102 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4103 struct drm_display_mode cea_mode; 4104 unsigned int clock1, clock2; 4105 4106 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4107 4108 /* Check both 60Hz and 59.94Hz */ 4109 clock1 = cea_mode.clock; 4110 clock2 = cea_mode_alternate_clock(&cea_mode); 4111 4112 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4113 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4114 continue; 4115 4116 do { 4117 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4118 return vic; 4119 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4120 } 4121 4122 return 0; 4123 } 4124 EXPORT_SYMBOL(drm_match_cea_mode); 4125 4126 static bool drm_valid_cea_vic(u8 vic) 4127 { 4128 return cea_mode_for_vic(vic) != NULL; 4129 } 4130 4131 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4132 { 4133 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4134 4135 if (mode) 4136 return mode->picture_aspect_ratio; 4137 4138 return HDMI_PICTURE_ASPECT_NONE; 4139 } 4140 4141 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4142 { 4143 return edid_4k_modes[video_code].picture_aspect_ratio; 4144 } 4145 4146 /* 4147 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4148 * specific block). 4149 */ 4150 static unsigned int 4151 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4152 { 4153 return cea_mode_alternate_clock(hdmi_mode); 4154 } 4155 4156 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4157 unsigned int clock_tolerance) 4158 { 4159 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4160 u8 vic; 4161 4162 if (!to_match->clock) 4163 return 0; 4164 4165 if (to_match->picture_aspect_ratio) 4166 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4167 4168 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4169 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4170 unsigned int clock1, clock2; 4171 4172 /* Make sure to also match alternate clocks */ 4173 clock1 = hdmi_mode->clock; 4174 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4175 4176 if (abs(to_match->clock - clock1) > clock_tolerance && 4177 abs(to_match->clock - clock2) > clock_tolerance) 4178 continue; 4179 4180 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4181 return vic; 4182 } 4183 4184 return 0; 4185 } 4186 4187 /* 4188 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4189 * @to_match: display mode 4190 * 4191 * An HDMI mode is one defined in the HDMI vendor specific block. 4192 * 4193 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4194 */ 4195 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4196 { 4197 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4198 u8 vic; 4199 4200 if (!to_match->clock) 4201 return 0; 4202 4203 if (to_match->picture_aspect_ratio) 4204 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4205 4206 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4207 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4208 unsigned int clock1, clock2; 4209 4210 /* Make sure to also match alternate clocks */ 4211 clock1 = hdmi_mode->clock; 4212 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4213 4214 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4215 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4216 drm_mode_match(to_match, hdmi_mode, match_flags)) 4217 return vic; 4218 } 4219 return 0; 4220 } 4221 4222 static bool drm_valid_hdmi_vic(u8 vic) 4223 { 4224 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4225 } 4226 4227 static int add_alternate_cea_modes(struct drm_connector *connector, 4228 const struct drm_edid *drm_edid) 4229 { 4230 struct drm_device *dev = connector->dev; 4231 struct drm_display_mode *mode, *tmp; 4232 LIST_HEAD(list); 4233 int modes = 0; 4234 4235 /* Don't add CTA modes if the CTA extension block is missing */ 4236 if (!drm_edid_has_cta_extension(drm_edid)) 4237 return 0; 4238 4239 /* 4240 * Go through all probed modes and create a new mode 4241 * with the alternate clock for certain CEA modes. 4242 */ 4243 list_for_each_entry(mode, &connector->probed_modes, head) { 4244 const struct drm_display_mode *cea_mode = NULL; 4245 struct drm_display_mode *newmode; 4246 u8 vic = drm_match_cea_mode(mode); 4247 unsigned int clock1, clock2; 4248 4249 if (drm_valid_cea_vic(vic)) { 4250 cea_mode = cea_mode_for_vic(vic); 4251 clock2 = cea_mode_alternate_clock(cea_mode); 4252 } else { 4253 vic = drm_match_hdmi_mode(mode); 4254 if (drm_valid_hdmi_vic(vic)) { 4255 cea_mode = &edid_4k_modes[vic]; 4256 clock2 = hdmi_mode_alternate_clock(cea_mode); 4257 } 4258 } 4259 4260 if (!cea_mode) 4261 continue; 4262 4263 clock1 = cea_mode->clock; 4264 4265 if (clock1 == clock2) 4266 continue; 4267 4268 if (mode->clock != clock1 && mode->clock != clock2) 4269 continue; 4270 4271 newmode = drm_mode_duplicate(dev, cea_mode); 4272 if (!newmode) 4273 continue; 4274 4275 /* Carry over the stereo flags */ 4276 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4277 4278 /* 4279 * The current mode could be either variant. Make 4280 * sure to pick the "other" clock for the new mode. 4281 */ 4282 if (mode->clock != clock1) 4283 newmode->clock = clock1; 4284 else 4285 newmode->clock = clock2; 4286 4287 list_add_tail(&newmode->head, &list); 4288 } 4289 4290 list_for_each_entry_safe(mode, tmp, &list, head) { 4291 list_del(&mode->head); 4292 drm_mode_probed_add(connector, mode); 4293 modes++; 4294 } 4295 4296 return modes; 4297 } 4298 4299 static u8 svd_to_vic(u8 svd) 4300 { 4301 /* 0-6 bit vic, 7th bit native mode indicator */ 4302 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4303 return svd & 127; 4304 4305 return svd; 4306 } 4307 4308 static struct drm_display_mode * 4309 drm_display_mode_from_vic_index(struct drm_connector *connector, 4310 const u8 *video_db, u8 video_len, 4311 u8 video_index) 4312 { 4313 struct drm_device *dev = connector->dev; 4314 struct drm_display_mode *newmode; 4315 u8 vic; 4316 4317 if (video_db == NULL || video_index >= video_len) 4318 return NULL; 4319 4320 /* CEA modes are numbered 1..127 */ 4321 vic = svd_to_vic(video_db[video_index]); 4322 if (!drm_valid_cea_vic(vic)) 4323 return NULL; 4324 4325 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4326 if (!newmode) 4327 return NULL; 4328 4329 return newmode; 4330 } 4331 4332 /* 4333 * do_y420vdb_modes - Parse YCBCR 420 only modes 4334 * @connector: connector corresponding to the HDMI sink 4335 * @svds: start of the data block of CEA YCBCR 420 VDB 4336 * @len: length of the CEA YCBCR 420 VDB 4337 * 4338 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4339 * which contains modes which can be supported in YCBCR 420 4340 * output format only. 4341 */ 4342 static int do_y420vdb_modes(struct drm_connector *connector, 4343 const u8 *svds, u8 svds_len) 4344 { 4345 int modes = 0, i; 4346 struct drm_device *dev = connector->dev; 4347 struct drm_display_info *info = &connector->display_info; 4348 struct drm_hdmi_info *hdmi = &info->hdmi; 4349 4350 for (i = 0; i < svds_len; i++) { 4351 u8 vic = svd_to_vic(svds[i]); 4352 struct drm_display_mode *newmode; 4353 4354 if (!drm_valid_cea_vic(vic)) 4355 continue; 4356 4357 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4358 if (!newmode) 4359 break; 4360 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 4361 drm_mode_probed_add(connector, newmode); 4362 modes++; 4363 } 4364 4365 if (modes > 0) 4366 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4367 return modes; 4368 } 4369 4370 /* 4371 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 4372 * @connector: connector corresponding to the HDMI sink 4373 * @vic: CEA vic for the video mode to be added in the map 4374 * 4375 * Makes an entry for a videomode in the YCBCR 420 bitmap 4376 */ 4377 static void 4378 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 4379 { 4380 u8 vic = svd_to_vic(svd); 4381 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4382 4383 if (!drm_valid_cea_vic(vic)) 4384 return; 4385 4386 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 4387 } 4388 4389 /** 4390 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4391 * @dev: DRM device 4392 * @video_code: CEA VIC of the mode 4393 * 4394 * Creates a new mode matching the specified CEA VIC. 4395 * 4396 * Returns: A new drm_display_mode on success or NULL on failure 4397 */ 4398 struct drm_display_mode * 4399 drm_display_mode_from_cea_vic(struct drm_device *dev, 4400 u8 video_code) 4401 { 4402 const struct drm_display_mode *cea_mode; 4403 struct drm_display_mode *newmode; 4404 4405 cea_mode = cea_mode_for_vic(video_code); 4406 if (!cea_mode) 4407 return NULL; 4408 4409 newmode = drm_mode_duplicate(dev, cea_mode); 4410 if (!newmode) 4411 return NULL; 4412 4413 return newmode; 4414 } 4415 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4416 4417 static int 4418 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 4419 { 4420 int i, modes = 0; 4421 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4422 4423 for (i = 0; i < len; i++) { 4424 struct drm_display_mode *mode; 4425 4426 mode = drm_display_mode_from_vic_index(connector, db, len, i); 4427 if (mode) { 4428 /* 4429 * YCBCR420 capability block contains a bitmap which 4430 * gives the index of CEA modes from CEA VDB, which 4431 * can support YCBCR 420 sampling output also (apart 4432 * from RGB/YCBCR444 etc). 4433 * For example, if the bit 0 in bitmap is set, 4434 * first mode in VDB can support YCBCR420 output too. 4435 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 4436 */ 4437 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 4438 drm_add_cmdb_modes(connector, db[i]); 4439 4440 drm_mode_probed_add(connector, mode); 4441 modes++; 4442 } 4443 } 4444 4445 return modes; 4446 } 4447 4448 struct stereo_mandatory_mode { 4449 int width, height, vrefresh; 4450 unsigned int flags; 4451 }; 4452 4453 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4454 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4455 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4456 { 1920, 1080, 50, 4457 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4458 { 1920, 1080, 60, 4459 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4460 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4461 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4462 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4463 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4464 }; 4465 4466 static bool 4467 stereo_match_mandatory(const struct drm_display_mode *mode, 4468 const struct stereo_mandatory_mode *stereo_mode) 4469 { 4470 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4471 4472 return mode->hdisplay == stereo_mode->width && 4473 mode->vdisplay == stereo_mode->height && 4474 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4475 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4476 } 4477 4478 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4479 { 4480 struct drm_device *dev = connector->dev; 4481 const struct drm_display_mode *mode; 4482 struct list_head stereo_modes; 4483 int modes = 0, i; 4484 4485 INIT_LIST_HEAD(&stereo_modes); 4486 4487 list_for_each_entry(mode, &connector->probed_modes, head) { 4488 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4489 const struct stereo_mandatory_mode *mandatory; 4490 struct drm_display_mode *new_mode; 4491 4492 if (!stereo_match_mandatory(mode, 4493 &stereo_mandatory_modes[i])) 4494 continue; 4495 4496 mandatory = &stereo_mandatory_modes[i]; 4497 new_mode = drm_mode_duplicate(dev, mode); 4498 if (!new_mode) 4499 continue; 4500 4501 new_mode->flags |= mandatory->flags; 4502 list_add_tail(&new_mode->head, &stereo_modes); 4503 modes++; 4504 } 4505 } 4506 4507 list_splice_tail(&stereo_modes, &connector->probed_modes); 4508 4509 return modes; 4510 } 4511 4512 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4513 { 4514 struct drm_device *dev = connector->dev; 4515 struct drm_display_mode *newmode; 4516 4517 if (!drm_valid_hdmi_vic(vic)) { 4518 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 4519 return 0; 4520 } 4521 4522 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4523 if (!newmode) 4524 return 0; 4525 4526 drm_mode_probed_add(connector, newmode); 4527 4528 return 1; 4529 } 4530 4531 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4532 const u8 *video_db, u8 video_len, u8 video_index) 4533 { 4534 struct drm_display_mode *newmode; 4535 int modes = 0; 4536 4537 if (structure & (1 << 0)) { 4538 newmode = drm_display_mode_from_vic_index(connector, video_db, 4539 video_len, 4540 video_index); 4541 if (newmode) { 4542 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4543 drm_mode_probed_add(connector, newmode); 4544 modes++; 4545 } 4546 } 4547 if (structure & (1 << 6)) { 4548 newmode = drm_display_mode_from_vic_index(connector, video_db, 4549 video_len, 4550 video_index); 4551 if (newmode) { 4552 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4553 drm_mode_probed_add(connector, newmode); 4554 modes++; 4555 } 4556 } 4557 if (structure & (1 << 8)) { 4558 newmode = drm_display_mode_from_vic_index(connector, video_db, 4559 video_len, 4560 video_index); 4561 if (newmode) { 4562 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4563 drm_mode_probed_add(connector, newmode); 4564 modes++; 4565 } 4566 } 4567 4568 return modes; 4569 } 4570 4571 /* 4572 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4573 * @connector: connector corresponding to the HDMI sink 4574 * @db: start of the CEA vendor specific block 4575 * @len: length of the CEA block payload, ie. one can access up to db[len] 4576 * 4577 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4578 * also adds the stereo 3d modes when applicable. 4579 */ 4580 static int 4581 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4582 const u8 *video_db, u8 video_len) 4583 { 4584 struct drm_display_info *info = &connector->display_info; 4585 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4586 u8 vic_len, hdmi_3d_len = 0; 4587 u16 mask; 4588 u16 structure_all; 4589 4590 if (len < 8) 4591 goto out; 4592 4593 /* no HDMI_Video_Present */ 4594 if (!(db[8] & (1 << 5))) 4595 goto out; 4596 4597 /* Latency_Fields_Present */ 4598 if (db[8] & (1 << 7)) 4599 offset += 2; 4600 4601 /* I_Latency_Fields_Present */ 4602 if (db[8] & (1 << 6)) 4603 offset += 2; 4604 4605 /* the declared length is not long enough for the 2 first bytes 4606 * of additional video format capabilities */ 4607 if (len < (8 + offset + 2)) 4608 goto out; 4609 4610 /* 3D_Present */ 4611 offset++; 4612 if (db[8 + offset] & (1 << 7)) { 4613 modes += add_hdmi_mandatory_stereo_modes(connector); 4614 4615 /* 3D_Multi_present */ 4616 multi_present = (db[8 + offset] & 0x60) >> 5; 4617 } 4618 4619 offset++; 4620 vic_len = db[8 + offset] >> 5; 4621 hdmi_3d_len = db[8 + offset] & 0x1f; 4622 4623 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4624 u8 vic; 4625 4626 vic = db[9 + offset + i]; 4627 modes += add_hdmi_mode(connector, vic); 4628 } 4629 offset += 1 + vic_len; 4630 4631 if (multi_present == 1) 4632 multi_len = 2; 4633 else if (multi_present == 2) 4634 multi_len = 4; 4635 else 4636 multi_len = 0; 4637 4638 if (len < (8 + offset + hdmi_3d_len - 1)) 4639 goto out; 4640 4641 if (hdmi_3d_len < multi_len) 4642 goto out; 4643 4644 if (multi_present == 1 || multi_present == 2) { 4645 /* 3D_Structure_ALL */ 4646 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4647 4648 /* check if 3D_MASK is present */ 4649 if (multi_present == 2) 4650 mask = (db[10 + offset] << 8) | db[11 + offset]; 4651 else 4652 mask = 0xffff; 4653 4654 for (i = 0; i < 16; i++) { 4655 if (mask & (1 << i)) 4656 modes += add_3d_struct_modes(connector, 4657 structure_all, 4658 video_db, 4659 video_len, i); 4660 } 4661 } 4662 4663 offset += multi_len; 4664 4665 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4666 int vic_index; 4667 struct drm_display_mode *newmode = NULL; 4668 unsigned int newflag = 0; 4669 bool detail_present; 4670 4671 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4672 4673 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4674 break; 4675 4676 /* 2D_VIC_order_X */ 4677 vic_index = db[8 + offset + i] >> 4; 4678 4679 /* 3D_Structure_X */ 4680 switch (db[8 + offset + i] & 0x0f) { 4681 case 0: 4682 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4683 break; 4684 case 6: 4685 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4686 break; 4687 case 8: 4688 /* 3D_Detail_X */ 4689 if ((db[9 + offset + i] >> 4) == 1) 4690 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4691 break; 4692 } 4693 4694 if (newflag != 0) { 4695 newmode = drm_display_mode_from_vic_index(connector, 4696 video_db, 4697 video_len, 4698 vic_index); 4699 4700 if (newmode) { 4701 newmode->flags |= newflag; 4702 drm_mode_probed_add(connector, newmode); 4703 modes++; 4704 } 4705 } 4706 4707 if (detail_present) 4708 i++; 4709 } 4710 4711 out: 4712 if (modes > 0) 4713 info->has_hdmi_infoframe = true; 4714 return modes; 4715 } 4716 4717 static int 4718 cea_revision(const u8 *cea) 4719 { 4720 /* 4721 * FIXME is this correct for the DispID variant? 4722 * The DispID spec doesn't really specify whether 4723 * this is the revision of the CEA extension or 4724 * the DispID CEA data block. And the only value 4725 * given as an example is 0. 4726 */ 4727 return cea[1]; 4728 } 4729 4730 /* 4731 * CTA Data Block iterator. 4732 * 4733 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4734 * CTA Data Blocks. 4735 * 4736 * struct cea_db *db: 4737 * struct cea_db_iter iter; 4738 * 4739 * cea_db_iter_edid_begin(edid, &iter); 4740 * cea_db_iter_for_each(db, &iter) { 4741 * // do stuff with db 4742 * } 4743 * cea_db_iter_end(&iter); 4744 */ 4745 struct cea_db_iter { 4746 struct drm_edid_iter edid_iter; 4747 struct displayid_iter displayid_iter; 4748 4749 /* Current Data Block Collection. */ 4750 const u8 *collection; 4751 4752 /* Current Data Block index in current collection. */ 4753 int index; 4754 4755 /* End index in current collection. */ 4756 int end; 4757 }; 4758 4759 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4760 struct cea_db { 4761 u8 tag_length; 4762 u8 data[]; 4763 } __packed; 4764 4765 static int cea_db_tag(const struct cea_db *db) 4766 { 4767 return db->tag_length >> 5; 4768 } 4769 4770 static int cea_db_payload_len(const void *_db) 4771 { 4772 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4773 const struct cea_db *db = _db; 4774 4775 return db->tag_length & 0x1f; 4776 } 4777 4778 static const void *cea_db_data(const struct cea_db *db) 4779 { 4780 return db->data; 4781 } 4782 4783 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4784 { 4785 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4786 cea_db_payload_len(db) >= 1 && 4787 db->data[0] == tag; 4788 } 4789 4790 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4791 { 4792 const u8 *data = cea_db_data(db); 4793 4794 return cea_db_tag(db) == CTA_DB_VENDOR && 4795 cea_db_payload_len(db) >= 3 && 4796 oui(data[2], data[1], data[0]) == vendor_oui; 4797 } 4798 4799 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4800 struct cea_db_iter *iter) 4801 { 4802 memset(iter, 0, sizeof(*iter)); 4803 4804 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4805 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4806 } 4807 4808 static const struct cea_db * 4809 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4810 { 4811 const struct cea_db *db; 4812 4813 if (!iter->collection) 4814 return NULL; 4815 4816 db = (const struct cea_db *)&iter->collection[iter->index]; 4817 4818 if (iter->index + sizeof(*db) <= iter->end && 4819 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4820 return db; 4821 4822 return NULL; 4823 } 4824 4825 /* 4826 * References: 4827 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4828 */ 4829 static int cea_db_collection_size(const u8 *cta) 4830 { 4831 u8 d = cta[2]; 4832 4833 if (d < 4 || d > 127) 4834 return 0; 4835 4836 return d - 4; 4837 } 4838 4839 /* 4840 * References: 4841 * - VESA E-EDID v1.4 4842 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4843 */ 4844 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4845 { 4846 const u8 *ext; 4847 4848 drm_edid_iter_for_each(ext, &iter->edid_iter) { 4849 int size; 4850 4851 /* Only support CTA Extension revision 3+ */ 4852 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 4853 continue; 4854 4855 size = cea_db_collection_size(ext); 4856 if (!size) 4857 continue; 4858 4859 iter->index = 4; 4860 iter->end = iter->index + size; 4861 4862 return ext; 4863 } 4864 4865 return NULL; 4866 } 4867 4868 /* 4869 * References: 4870 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 4871 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 4872 * 4873 * Note that the above do not specify any connection between DisplayID Data 4874 * Block revision and CTA Extension versions. 4875 */ 4876 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 4877 { 4878 const struct displayid_block *block; 4879 4880 displayid_iter_for_each(block, &iter->displayid_iter) { 4881 if (block->tag != DATA_BLOCK_CTA) 4882 continue; 4883 4884 /* 4885 * The displayid iterator has already verified the block bounds 4886 * in displayid_iter_block(). 4887 */ 4888 iter->index = sizeof(*block); 4889 iter->end = iter->index + block->num_bytes; 4890 4891 return block; 4892 } 4893 4894 return NULL; 4895 } 4896 4897 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 4898 { 4899 const struct cea_db *db; 4900 4901 if (iter->collection) { 4902 /* Current collection should always be valid. */ 4903 db = __cea_db_iter_current_block(iter); 4904 if (WARN_ON(!db)) { 4905 iter->collection = NULL; 4906 return NULL; 4907 } 4908 4909 /* Next block in CTA Data Block Collection */ 4910 iter->index += sizeof(*db) + cea_db_payload_len(db); 4911 4912 db = __cea_db_iter_current_block(iter); 4913 if (db) 4914 return db; 4915 } 4916 4917 for (;;) { 4918 /* 4919 * Find the next CTA Data Block Collection. First iterate all 4920 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 4921 * 4922 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 4923 * Extension, it's recommended that DisplayID extensions are 4924 * exposed after all of the CTA Extensions. 4925 */ 4926 iter->collection = __cea_db_iter_edid_next(iter); 4927 if (!iter->collection) 4928 iter->collection = __cea_db_iter_displayid_next(iter); 4929 4930 if (!iter->collection) 4931 return NULL; 4932 4933 db = __cea_db_iter_current_block(iter); 4934 if (db) 4935 return db; 4936 } 4937 } 4938 4939 #define cea_db_iter_for_each(__db, __iter) \ 4940 while (((__db) = __cea_db_iter_next(__iter))) 4941 4942 static void cea_db_iter_end(struct cea_db_iter *iter) 4943 { 4944 displayid_iter_end(&iter->displayid_iter); 4945 drm_edid_iter_end(&iter->edid_iter); 4946 4947 memset(iter, 0, sizeof(*iter)); 4948 } 4949 4950 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 4951 { 4952 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 4953 cea_db_payload_len(db) >= 5; 4954 } 4955 4956 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 4957 { 4958 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 4959 cea_db_payload_len(db) >= 7; 4960 } 4961 4962 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 4963 { 4964 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 4965 cea_db_payload_len(db) >= 2; 4966 } 4967 4968 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 4969 { 4970 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 4971 cea_db_payload_len(db) == 21; 4972 } 4973 4974 static bool cea_db_is_vcdb(const struct cea_db *db) 4975 { 4976 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 4977 cea_db_payload_len(db) == 2; 4978 } 4979 4980 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 4981 { 4982 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 4983 cea_db_payload_len(db) >= 7; 4984 } 4985 4986 static bool cea_db_is_y420cmdb(const struct cea_db *db) 4987 { 4988 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 4989 } 4990 4991 static bool cea_db_is_y420vdb(const struct cea_db *db) 4992 { 4993 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 4994 } 4995 4996 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 4997 { 4998 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 4999 cea_db_payload_len(db) >= 3; 5000 } 5001 5002 /* 5003 * Get the HF-EEODB override extension block count from EDID. 5004 * 5005 * The passed in EDID may be partially read, as long as it has at least two 5006 * blocks (base block and one extension block) if EDID extension count is > 0. 5007 * 5008 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5009 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5010 * iterators instead. 5011 * 5012 * References: 5013 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5014 */ 5015 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5016 { 5017 const u8 *cta; 5018 5019 /* No extensions according to base block, no HF-EEODB. */ 5020 if (!edid_extension_block_count(edid)) 5021 return 0; 5022 5023 /* HF-EEODB is always in the first EDID extension block only */ 5024 cta = edid_extension_block_data(edid, 0); 5025 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5026 return 0; 5027 5028 /* Need to have the data block collection, and at least 3 bytes. */ 5029 if (cea_db_collection_size(cta) < 3) 5030 return 0; 5031 5032 /* 5033 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5034 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5035 * through 6 of Block 1 of the E-EDID. 5036 */ 5037 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5038 return 0; 5039 5040 return cta[4 + 2]; 5041 } 5042 5043 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 5044 const u8 *db) 5045 { 5046 struct drm_display_info *info = &connector->display_info; 5047 struct drm_hdmi_info *hdmi = &info->hdmi; 5048 u8 map_len = cea_db_payload_len(db) - 1; 5049 u8 count; 5050 u64 map = 0; 5051 5052 if (map_len == 0) { 5053 /* All CEA modes support ycbcr420 sampling also.*/ 5054 hdmi->y420_cmdb_map = U64_MAX; 5055 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5056 return; 5057 } 5058 5059 /* 5060 * This map indicates which of the existing CEA block modes 5061 * from VDB can support YCBCR420 output too. So if bit=0 is 5062 * set, first mode from VDB can support YCBCR420 output too. 5063 * We will parse and keep this map, before parsing VDB itself 5064 * to avoid going through the same block again and again. 5065 * 5066 * Spec is not clear about max possible size of this block. 5067 * Clamping max bitmap block size at 8 bytes. Every byte can 5068 * address 8 CEA modes, in this way this map can address 5069 * 8*8 = first 64 SVDs. 5070 */ 5071 if (WARN_ON_ONCE(map_len > 8)) 5072 map_len = 8; 5073 5074 for (count = 0; count < map_len; count++) 5075 map |= (u64)db[2 + count] << (8 * count); 5076 5077 if (map) 5078 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5079 5080 hdmi->y420_cmdb_map = map; 5081 } 5082 5083 static int add_cea_modes(struct drm_connector *connector, 5084 const struct drm_edid *drm_edid) 5085 { 5086 const struct cea_db *db; 5087 struct cea_db_iter iter; 5088 int modes = 0; 5089 5090 cea_db_iter_edid_begin(drm_edid, &iter); 5091 cea_db_iter_for_each(db, &iter) { 5092 const u8 *hdmi = NULL, *video = NULL; 5093 u8 hdmi_len = 0, video_len = 0; 5094 5095 if (cea_db_tag(db) == CTA_DB_VIDEO) { 5096 video = cea_db_data(db); 5097 video_len = cea_db_payload_len(db); 5098 modes += do_cea_modes(connector, video, video_len); 5099 } else if (cea_db_is_hdmi_vsdb(db)) { 5100 /* FIXME: Switch to use cea_db_data() */ 5101 hdmi = (const u8 *)db; 5102 hdmi_len = cea_db_payload_len(db); 5103 } else if (cea_db_is_y420vdb(db)) { 5104 const u8 *vdb420 = cea_db_data(db) + 1; 5105 5106 /* Add 4:2:0(only) modes present in EDID */ 5107 modes += do_y420vdb_modes(connector, vdb420, 5108 cea_db_payload_len(db) - 1); 5109 } 5110 5111 /* 5112 * We parse the HDMI VSDB after having added the cea modes as we 5113 * will be patching their flags when the sink supports stereo 5114 * 3D. 5115 */ 5116 if (hdmi) 5117 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, 5118 video, video_len); 5119 } 5120 cea_db_iter_end(&iter); 5121 5122 return modes; 5123 } 5124 5125 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 5126 { 5127 const struct drm_display_mode *cea_mode; 5128 int clock1, clock2, clock; 5129 u8 vic; 5130 const char *type; 5131 5132 /* 5133 * allow 5kHz clock difference either way to account for 5134 * the 10kHz clock resolution limit of detailed timings. 5135 */ 5136 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5137 if (drm_valid_cea_vic(vic)) { 5138 type = "CEA"; 5139 cea_mode = cea_mode_for_vic(vic); 5140 clock1 = cea_mode->clock; 5141 clock2 = cea_mode_alternate_clock(cea_mode); 5142 } else { 5143 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5144 if (drm_valid_hdmi_vic(vic)) { 5145 type = "HDMI"; 5146 cea_mode = &edid_4k_modes[vic]; 5147 clock1 = cea_mode->clock; 5148 clock2 = hdmi_mode_alternate_clock(cea_mode); 5149 } else { 5150 return; 5151 } 5152 } 5153 5154 /* pick whichever is closest */ 5155 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5156 clock = clock1; 5157 else 5158 clock = clock2; 5159 5160 if (mode->clock == clock) 5161 return; 5162 5163 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5164 type, vic, mode->clock, clock); 5165 mode->clock = clock; 5166 } 5167 5168 static void drm_calculate_luminance_range(struct drm_connector *connector) 5169 { 5170 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5171 struct drm_luminance_range_info *luminance_range = 5172 &connector->display_info.luminance_range; 5173 static const u8 pre_computed_values[] = { 5174 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5175 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5176 }; 5177 u32 max_avg, min_cll, max, min, q, r; 5178 5179 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5180 return; 5181 5182 max_avg = hdr_metadata->max_fall; 5183 min_cll = hdr_metadata->min_cll; 5184 5185 /* 5186 * From the specification (CTA-861-G), for calculating the maximum 5187 * luminance we need to use: 5188 * Luminance = 50*2**(CV/32) 5189 * Where CV is a one-byte value. 5190 * For calculating this expression we may need float point precision; 5191 * to avoid this complexity level, we take advantage that CV is divided 5192 * by a constant. From the Euclids division algorithm, we know that CV 5193 * can be written as: CV = 32*q + r. Next, we replace CV in the 5194 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5195 * need to pre-compute the value of r/32. For pre-computing the values 5196 * We just used the following Ruby line: 5197 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5198 * The results of the above expressions can be verified at 5199 * pre_computed_values. 5200 */ 5201 q = max_avg >> 5; 5202 r = max_avg % 32; 5203 max = (1 << q) * pre_computed_values[r]; 5204 5205 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5206 q = DIV_ROUND_CLOSEST(min_cll, 255); 5207 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5208 5209 luminance_range->min_luminance = min; 5210 luminance_range->max_luminance = max; 5211 } 5212 5213 static uint8_t eotf_supported(const u8 *edid_ext) 5214 { 5215 return edid_ext[2] & 5216 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5217 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5218 BIT(HDMI_EOTF_SMPTE_ST2084) | 5219 BIT(HDMI_EOTF_BT_2100_HLG)); 5220 } 5221 5222 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5223 { 5224 return edid_ext[3] & 5225 BIT(HDMI_STATIC_METADATA_TYPE1); 5226 } 5227 5228 static void 5229 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5230 { 5231 u16 len; 5232 5233 len = cea_db_payload_len(db); 5234 5235 connector->hdr_sink_metadata.hdmi_type1.eotf = 5236 eotf_supported(db); 5237 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5238 hdr_metadata_type(db); 5239 5240 if (len >= 4) 5241 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5242 if (len >= 5) 5243 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5244 if (len >= 6) { 5245 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5246 5247 /* Calculate only when all values are available */ 5248 drm_calculate_luminance_range(connector); 5249 } 5250 } 5251 5252 static void 5253 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5254 { 5255 u8 len = cea_db_payload_len(db); 5256 5257 if (len >= 6 && (db[6] & (1 << 7))) 5258 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5259 if (len >= 8) { 5260 connector->latency_present[0] = db[8] >> 7; 5261 connector->latency_present[1] = (db[8] >> 6) & 1; 5262 } 5263 if (len >= 9) 5264 connector->video_latency[0] = db[9]; 5265 if (len >= 10) 5266 connector->audio_latency[0] = db[10]; 5267 if (len >= 11) 5268 connector->video_latency[1] = db[11]; 5269 if (len >= 12) 5270 connector->audio_latency[1] = db[12]; 5271 5272 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 5273 "video latency %d %d, " 5274 "audio latency %d %d\n", 5275 connector->latency_present[0], 5276 connector->latency_present[1], 5277 connector->video_latency[0], 5278 connector->video_latency[1], 5279 connector->audio_latency[0], 5280 connector->audio_latency[1]); 5281 } 5282 5283 static void 5284 monitor_name(const struct detailed_timing *timing, void *data) 5285 { 5286 const char **res = data; 5287 5288 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5289 return; 5290 5291 *res = timing->data.other_data.data.str.str; 5292 } 5293 5294 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5295 { 5296 const char *edid_name = NULL; 5297 int mnl; 5298 5299 if (!drm_edid || !name) 5300 return 0; 5301 5302 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5303 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5304 if (edid_name[mnl] == 0x0a) 5305 break; 5306 5307 name[mnl] = edid_name[mnl]; 5308 } 5309 5310 return mnl; 5311 } 5312 5313 /** 5314 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5315 * @edid: monitor EDID information 5316 * @name: pointer to a character array to hold the name of the monitor 5317 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5318 * 5319 */ 5320 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5321 { 5322 int name_length = 0; 5323 5324 if (bufsize <= 0) 5325 return; 5326 5327 if (edid) { 5328 char buf[13]; 5329 struct drm_edid drm_edid = { 5330 .edid = edid, 5331 .size = edid_size(edid), 5332 }; 5333 5334 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5335 memcpy(name, buf, name_length); 5336 } 5337 5338 name[name_length] = '\0'; 5339 } 5340 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5341 5342 static void clear_eld(struct drm_connector *connector) 5343 { 5344 memset(connector->eld, 0, sizeof(connector->eld)); 5345 5346 connector->latency_present[0] = false; 5347 connector->latency_present[1] = false; 5348 connector->video_latency[0] = 0; 5349 connector->audio_latency[0] = 0; 5350 connector->video_latency[1] = 0; 5351 connector->audio_latency[1] = 0; 5352 } 5353 5354 /* 5355 * drm_edid_to_eld - build ELD from EDID 5356 * @connector: connector corresponding to the HDMI/DP sink 5357 * @drm_edid: EDID to parse 5358 * 5359 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5360 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5361 */ 5362 static void drm_edid_to_eld(struct drm_connector *connector, 5363 const struct drm_edid *drm_edid) 5364 { 5365 const struct drm_display_info *info = &connector->display_info; 5366 const struct cea_db *db; 5367 struct cea_db_iter iter; 5368 uint8_t *eld = connector->eld; 5369 int total_sad_count = 0; 5370 int mnl; 5371 5372 clear_eld(connector); 5373 5374 if (!drm_edid) 5375 return; 5376 5377 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5378 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 5379 5380 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5381 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5382 5383 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5384 5385 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5386 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5387 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5388 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5389 5390 cea_db_iter_edid_begin(drm_edid, &iter); 5391 cea_db_iter_for_each(db, &iter) { 5392 const u8 *data = cea_db_data(db); 5393 int len = cea_db_payload_len(db); 5394 int sad_count; 5395 5396 switch (cea_db_tag(db)) { 5397 case CTA_DB_AUDIO: 5398 /* Audio Data Block, contains SADs */ 5399 sad_count = min(len / 3, 15 - total_sad_count); 5400 if (sad_count >= 1) 5401 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5402 data, sad_count * 3); 5403 total_sad_count += sad_count; 5404 break; 5405 case CTA_DB_SPEAKER: 5406 /* Speaker Allocation Data Block */ 5407 if (len >= 1) 5408 eld[DRM_ELD_SPEAKER] = data[0]; 5409 break; 5410 case CTA_DB_VENDOR: 5411 /* HDMI Vendor-Specific Data Block */ 5412 if (cea_db_is_hdmi_vsdb(db)) 5413 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5414 break; 5415 default: 5416 break; 5417 } 5418 } 5419 cea_db_iter_end(&iter); 5420 5421 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5422 5423 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5424 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5425 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5426 else 5427 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5428 5429 eld[DRM_ELD_BASELINE_ELD_LEN] = 5430 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5431 5432 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 5433 drm_eld_size(eld), total_sad_count); 5434 } 5435 5436 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5437 struct cea_sad **sads) 5438 { 5439 const struct cea_db *db; 5440 struct cea_db_iter iter; 5441 int count = 0; 5442 5443 cea_db_iter_edid_begin(drm_edid, &iter); 5444 cea_db_iter_for_each(db, &iter) { 5445 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5446 int j; 5447 5448 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5449 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5450 if (!*sads) 5451 return -ENOMEM; 5452 for (j = 0; j < count; j++) { 5453 const u8 *sad = &db->data[j * 3]; 5454 5455 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5456 (*sads)[j].channels = sad[0] & 0x7; 5457 (*sads)[j].freq = sad[1] & 0x7F; 5458 (*sads)[j].byte2 = sad[2]; 5459 } 5460 break; 5461 } 5462 } 5463 cea_db_iter_end(&iter); 5464 5465 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5466 5467 return count; 5468 } 5469 5470 /** 5471 * drm_edid_to_sad - extracts SADs from EDID 5472 * @edid: EDID to parse 5473 * @sads: pointer that will be set to the extracted SADs 5474 * 5475 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5476 * 5477 * Note: The returned pointer needs to be freed using kfree(). 5478 * 5479 * Return: The number of found SADs or negative number on error. 5480 */ 5481 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5482 { 5483 struct drm_edid drm_edid; 5484 5485 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5486 } 5487 EXPORT_SYMBOL(drm_edid_to_sad); 5488 5489 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5490 u8 **sadb) 5491 { 5492 const struct cea_db *db; 5493 struct cea_db_iter iter; 5494 int count = 0; 5495 5496 cea_db_iter_edid_begin(drm_edid, &iter); 5497 cea_db_iter_for_each(db, &iter) { 5498 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5499 cea_db_payload_len(db) == 3) { 5500 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5501 GFP_KERNEL); 5502 if (!*sadb) 5503 return -ENOMEM; 5504 count = cea_db_payload_len(db); 5505 break; 5506 } 5507 } 5508 cea_db_iter_end(&iter); 5509 5510 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5511 5512 return count; 5513 } 5514 5515 /** 5516 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5517 * @edid: EDID to parse 5518 * @sadb: pointer to the speaker block 5519 * 5520 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5521 * 5522 * Note: The returned pointer needs to be freed using kfree(). 5523 * 5524 * Return: The number of found Speaker Allocation Blocks or negative number on 5525 * error. 5526 */ 5527 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5528 { 5529 struct drm_edid drm_edid; 5530 5531 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5532 sadb); 5533 } 5534 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5535 5536 /** 5537 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5538 * @connector: connector associated with the HDMI/DP sink 5539 * @mode: the display mode 5540 * 5541 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5542 * the sink doesn't support audio or video. 5543 */ 5544 int drm_av_sync_delay(struct drm_connector *connector, 5545 const struct drm_display_mode *mode) 5546 { 5547 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5548 int a, v; 5549 5550 if (!connector->latency_present[0]) 5551 return 0; 5552 if (!connector->latency_present[1]) 5553 i = 0; 5554 5555 a = connector->audio_latency[i]; 5556 v = connector->video_latency[i]; 5557 5558 /* 5559 * HDMI/DP sink doesn't support audio or video? 5560 */ 5561 if (a == 255 || v == 255) 5562 return 0; 5563 5564 /* 5565 * Convert raw EDID values to millisecond. 5566 * Treat unknown latency as 0ms. 5567 */ 5568 if (a) 5569 a = min(2 * (a - 1), 500); 5570 if (v) 5571 v = min(2 * (v - 1), 500); 5572 5573 return max(v - a, 0); 5574 } 5575 EXPORT_SYMBOL(drm_av_sync_delay); 5576 5577 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5578 { 5579 const struct cea_db *db; 5580 struct cea_db_iter iter; 5581 bool hdmi = false; 5582 5583 /* 5584 * Because HDMI identifier is in Vendor Specific Block, 5585 * search it from all data blocks of CEA extension. 5586 */ 5587 cea_db_iter_edid_begin(drm_edid, &iter); 5588 cea_db_iter_for_each(db, &iter) { 5589 if (cea_db_is_hdmi_vsdb(db)) { 5590 hdmi = true; 5591 break; 5592 } 5593 } 5594 cea_db_iter_end(&iter); 5595 5596 return hdmi; 5597 } 5598 5599 /** 5600 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5601 * @edid: monitor EDID information 5602 * 5603 * Parse the CEA extension according to CEA-861-B. 5604 * 5605 * Drivers that have added the modes parsed from EDID to drm_display_info 5606 * should use &drm_display_info.is_hdmi instead of calling this function. 5607 * 5608 * Return: True if the monitor is HDMI, false if not or unknown. 5609 */ 5610 bool drm_detect_hdmi_monitor(const struct edid *edid) 5611 { 5612 struct drm_edid drm_edid; 5613 5614 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5615 } 5616 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5617 5618 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5619 { 5620 struct drm_edid_iter edid_iter; 5621 const struct cea_db *db; 5622 struct cea_db_iter iter; 5623 const u8 *edid_ext; 5624 bool has_audio = false; 5625 5626 drm_edid_iter_begin(drm_edid, &edid_iter); 5627 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5628 if (edid_ext[0] == CEA_EXT) { 5629 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5630 if (has_audio) 5631 break; 5632 } 5633 } 5634 drm_edid_iter_end(&edid_iter); 5635 5636 if (has_audio) { 5637 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5638 goto end; 5639 } 5640 5641 cea_db_iter_edid_begin(drm_edid, &iter); 5642 cea_db_iter_for_each(db, &iter) { 5643 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5644 const u8 *data = cea_db_data(db); 5645 int i; 5646 5647 for (i = 0; i < cea_db_payload_len(db); i += 3) 5648 DRM_DEBUG_KMS("CEA audio format %d\n", 5649 (data[i] >> 3) & 0xf); 5650 has_audio = true; 5651 break; 5652 } 5653 } 5654 cea_db_iter_end(&iter); 5655 5656 end: 5657 return has_audio; 5658 } 5659 5660 /** 5661 * drm_detect_monitor_audio - check monitor audio capability 5662 * @edid: EDID block to scan 5663 * 5664 * Monitor should have CEA extension block. 5665 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5666 * audio' only. If there is any audio extension block and supported 5667 * audio format, assume at least 'basic audio' support, even if 'basic 5668 * audio' is not defined in EDID. 5669 * 5670 * Return: True if the monitor supports audio, false otherwise. 5671 */ 5672 bool drm_detect_monitor_audio(const struct edid *edid) 5673 { 5674 struct drm_edid drm_edid; 5675 5676 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5677 } 5678 EXPORT_SYMBOL(drm_detect_monitor_audio); 5679 5680 5681 /** 5682 * drm_default_rgb_quant_range - default RGB quantization range 5683 * @mode: display mode 5684 * 5685 * Determine the default RGB quantization range for the mode, 5686 * as specified in CEA-861. 5687 * 5688 * Return: The default RGB quantization range for the mode 5689 */ 5690 enum hdmi_quantization_range 5691 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5692 { 5693 /* All CEA modes other than VIC 1 use limited quantization range. */ 5694 return drm_match_cea_mode(mode) > 1 ? 5695 HDMI_QUANTIZATION_RANGE_LIMITED : 5696 HDMI_QUANTIZATION_RANGE_FULL; 5697 } 5698 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5699 5700 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5701 { 5702 struct drm_display_info *info = &connector->display_info; 5703 5704 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 5705 5706 if (db[2] & EDID_CEA_VCDB_QS) 5707 info->rgb_quant_range_selectable = true; 5708 } 5709 5710 static 5711 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5712 { 5713 switch (max_frl_rate) { 5714 case 1: 5715 *max_lanes = 3; 5716 *max_rate_per_lane = 3; 5717 break; 5718 case 2: 5719 *max_lanes = 3; 5720 *max_rate_per_lane = 6; 5721 break; 5722 case 3: 5723 *max_lanes = 4; 5724 *max_rate_per_lane = 6; 5725 break; 5726 case 4: 5727 *max_lanes = 4; 5728 *max_rate_per_lane = 8; 5729 break; 5730 case 5: 5731 *max_lanes = 4; 5732 *max_rate_per_lane = 10; 5733 break; 5734 case 6: 5735 *max_lanes = 4; 5736 *max_rate_per_lane = 12; 5737 break; 5738 case 0: 5739 default: 5740 *max_lanes = 0; 5741 *max_rate_per_lane = 0; 5742 } 5743 } 5744 5745 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5746 const u8 *db) 5747 { 5748 u8 dc_mask; 5749 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5750 5751 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5752 hdmi->y420_dc_modes = dc_mask; 5753 } 5754 5755 /* Sink Capability Data Structure */ 5756 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 5757 const u8 *hf_scds) 5758 { 5759 struct drm_display_info *display = &connector->display_info; 5760 struct drm_hdmi_info *hdmi = &display->hdmi; 5761 5762 display->has_hdmi_infoframe = true; 5763 5764 if (hf_scds[6] & 0x80) { 5765 hdmi->scdc.supported = true; 5766 if (hf_scds[6] & 0x40) 5767 hdmi->scdc.read_request = true; 5768 } 5769 5770 /* 5771 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 5772 * And as per the spec, three factors confirm this: 5773 * * Availability of a HF-VSDB block in EDID (check) 5774 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 5775 * * SCDC support available (let's check) 5776 * Lets check it out. 5777 */ 5778 5779 if (hf_scds[5]) { 5780 /* max clock is 5000 KHz times block value */ 5781 u32 max_tmds_clock = hf_scds[5] * 5000; 5782 struct drm_scdc *scdc = &hdmi->scdc; 5783 5784 if (max_tmds_clock > 340000) { 5785 display->max_tmds_clock = max_tmds_clock; 5786 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 5787 display->max_tmds_clock); 5788 } 5789 5790 if (scdc->supported) { 5791 scdc->scrambling.supported = true; 5792 5793 /* Few sinks support scrambling for clocks < 340M */ 5794 if ((hf_scds[6] & 0x8)) 5795 scdc->scrambling.low_rates = true; 5796 } 5797 } 5798 5799 if (hf_scds[7]) { 5800 u8 max_frl_rate; 5801 u8 dsc_max_frl_rate; 5802 u8 dsc_max_slices; 5803 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5804 5805 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 5806 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 5807 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 5808 &hdmi->max_frl_rate_per_lane); 5809 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5810 5811 if (hdmi_dsc->v_1p2) { 5812 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5813 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5814 5815 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 5816 hdmi_dsc->bpc_supported = 16; 5817 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 5818 hdmi_dsc->bpc_supported = 12; 5819 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 5820 hdmi_dsc->bpc_supported = 10; 5821 else 5822 hdmi_dsc->bpc_supported = 0; 5823 5824 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5825 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5826 &hdmi_dsc->max_frl_rate_per_lane); 5827 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5828 5829 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 5830 switch (dsc_max_slices) { 5831 case 1: 5832 hdmi_dsc->max_slices = 1; 5833 hdmi_dsc->clk_per_slice = 340; 5834 break; 5835 case 2: 5836 hdmi_dsc->max_slices = 2; 5837 hdmi_dsc->clk_per_slice = 340; 5838 break; 5839 case 3: 5840 hdmi_dsc->max_slices = 4; 5841 hdmi_dsc->clk_per_slice = 340; 5842 break; 5843 case 4: 5844 hdmi_dsc->max_slices = 8; 5845 hdmi_dsc->clk_per_slice = 340; 5846 break; 5847 case 5: 5848 hdmi_dsc->max_slices = 8; 5849 hdmi_dsc->clk_per_slice = 400; 5850 break; 5851 case 6: 5852 hdmi_dsc->max_slices = 12; 5853 hdmi_dsc->clk_per_slice = 400; 5854 break; 5855 case 7: 5856 hdmi_dsc->max_slices = 16; 5857 hdmi_dsc->clk_per_slice = 400; 5858 break; 5859 case 0: 5860 default: 5861 hdmi_dsc->max_slices = 0; 5862 hdmi_dsc->clk_per_slice = 0; 5863 } 5864 } 5865 } 5866 5867 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 5868 } 5869 5870 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5871 const u8 *hdmi) 5872 { 5873 struct drm_display_info *info = &connector->display_info; 5874 unsigned int dc_bpc = 0; 5875 5876 /* HDMI supports at least 8 bpc */ 5877 info->bpc = 8; 5878 5879 if (cea_db_payload_len(hdmi) < 6) 5880 return; 5881 5882 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5883 dc_bpc = 10; 5884 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5885 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5886 connector->name); 5887 } 5888 5889 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5890 dc_bpc = 12; 5891 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5892 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5893 connector->name); 5894 } 5895 5896 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5897 dc_bpc = 16; 5898 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5899 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5900 connector->name); 5901 } 5902 5903 if (dc_bpc == 0) { 5904 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5905 connector->name); 5906 return; 5907 } 5908 5909 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5910 connector->name, dc_bpc); 5911 info->bpc = dc_bpc; 5912 5913 /* YCRCB444 is optional according to spec. */ 5914 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5915 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5916 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5917 connector->name); 5918 } 5919 5920 /* 5921 * Spec says that if any deep color mode is supported at all, 5922 * then deep color 36 bit must be supported. 5923 */ 5924 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5925 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5926 connector->name); 5927 } 5928 } 5929 5930 static void 5931 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5932 { 5933 struct drm_display_info *info = &connector->display_info; 5934 u8 len = cea_db_payload_len(db); 5935 5936 info->is_hdmi = true; 5937 5938 if (len >= 6) 5939 info->dvi_dual = db[6] & 1; 5940 if (len >= 7) 5941 info->max_tmds_clock = db[7] * 5000; 5942 5943 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5944 "max TMDS clock %d kHz\n", 5945 info->dvi_dual, 5946 info->max_tmds_clock); 5947 5948 drm_parse_hdmi_deep_color_info(connector, db); 5949 } 5950 5951 /* 5952 * See EDID extension for head-mounted and specialized monitors, specified at: 5953 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 5954 */ 5955 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 5956 const u8 *db) 5957 { 5958 struct drm_display_info *info = &connector->display_info; 5959 u8 version = db[4]; 5960 bool desktop_usage = db[5] & BIT(6); 5961 5962 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 5963 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 5964 info->non_desktop = true; 5965 5966 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", 5967 version, db[5]); 5968 } 5969 5970 static void drm_parse_cea_ext(struct drm_connector *connector, 5971 const struct drm_edid *drm_edid) 5972 { 5973 struct drm_display_info *info = &connector->display_info; 5974 struct drm_edid_iter edid_iter; 5975 const struct cea_db *db; 5976 struct cea_db_iter iter; 5977 const u8 *edid_ext; 5978 5979 drm_edid_iter_begin(drm_edid, &edid_iter); 5980 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5981 if (edid_ext[0] != CEA_EXT) 5982 continue; 5983 5984 if (!info->cea_rev) 5985 info->cea_rev = edid_ext[1]; 5986 5987 if (info->cea_rev != edid_ext[1]) 5988 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n", 5989 info->cea_rev, edid_ext[1]); 5990 5991 /* The existence of a CTA extension should imply RGB support */ 5992 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5993 if (edid_ext[3] & EDID_CEA_YCRCB444) 5994 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5995 if (edid_ext[3] & EDID_CEA_YCRCB422) 5996 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5997 } 5998 drm_edid_iter_end(&edid_iter); 5999 6000 cea_db_iter_edid_begin(drm_edid, &iter); 6001 cea_db_iter_for_each(db, &iter) { 6002 /* FIXME: convert parsers to use struct cea_db */ 6003 const u8 *data = (const u8 *)db; 6004 6005 if (cea_db_is_hdmi_vsdb(db)) 6006 drm_parse_hdmi_vsdb_video(connector, data); 6007 else if (cea_db_is_hdmi_forum_vsdb(db) || 6008 cea_db_is_hdmi_forum_scdb(db)) 6009 drm_parse_hdmi_forum_scds(connector, data); 6010 else if (cea_db_is_microsoft_vsdb(db)) 6011 drm_parse_microsoft_vsdb(connector, data); 6012 else if (cea_db_is_y420cmdb(db)) 6013 drm_parse_y420cmdb_bitmap(connector, data); 6014 else if (cea_db_is_vcdb(db)) 6015 drm_parse_vcdb(connector, data); 6016 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6017 drm_parse_hdr_metadata_block(connector, data); 6018 } 6019 cea_db_iter_end(&iter); 6020 } 6021 6022 static 6023 void get_monitor_range(const struct detailed_timing *timing, void *c) 6024 { 6025 struct detailed_mode_closure *closure = c; 6026 struct drm_display_info *info = &closure->connector->display_info; 6027 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6028 const struct detailed_non_pixel *data = &timing->data.other_data; 6029 const struct detailed_data_monitor_range *range = &data->data.range; 6030 const struct edid *edid = closure->drm_edid->edid; 6031 6032 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6033 return; 6034 6035 /* 6036 * Check for flag range limits only. If flag == 1 then 6037 * no additional timing information provided. 6038 * Default GTF, GTF Secondary curve and CVT are not 6039 * supported 6040 */ 6041 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6042 return; 6043 6044 monitor_range->min_vfreq = range->min_vfreq; 6045 monitor_range->max_vfreq = range->max_vfreq; 6046 6047 if (edid->revision >= 4) { 6048 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6049 monitor_range->min_vfreq += 255; 6050 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6051 monitor_range->max_vfreq += 255; 6052 } 6053 } 6054 6055 static void drm_get_monitor_range(struct drm_connector *connector, 6056 const struct drm_edid *drm_edid) 6057 { 6058 const struct drm_display_info *info = &connector->display_info; 6059 struct detailed_mode_closure closure = { 6060 .connector = connector, 6061 .drm_edid = drm_edid, 6062 }; 6063 6064 if (!version_greater(drm_edid, 1, 1)) 6065 return; 6066 6067 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6068 6069 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6070 info->monitor_range.min_vfreq, 6071 info->monitor_range.max_vfreq); 6072 } 6073 6074 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6075 const struct displayid_block *block) 6076 { 6077 struct displayid_vesa_vendor_specific_block *vesa = 6078 (struct displayid_vesa_vendor_specific_block *)block; 6079 struct drm_display_info *info = &connector->display_info; 6080 6081 if (block->num_bytes < 3) { 6082 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", 6083 block->num_bytes); 6084 return; 6085 } 6086 6087 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6088 return; 6089 6090 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6091 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); 6092 return; 6093 } 6094 6095 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6096 default: 6097 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); 6098 fallthrough; 6099 case 0: 6100 info->mso_stream_count = 0; 6101 break; 6102 case 1: 6103 info->mso_stream_count = 2; /* 2 or 4 links */ 6104 break; 6105 case 2: 6106 info->mso_stream_count = 4; /* 4 links */ 6107 break; 6108 } 6109 6110 if (!info->mso_stream_count) { 6111 info->mso_pixel_overlap = 0; 6112 return; 6113 } 6114 6115 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6116 if (info->mso_pixel_overlap > 8) { 6117 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", 6118 info->mso_pixel_overlap); 6119 info->mso_pixel_overlap = 8; 6120 } 6121 6122 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", 6123 info->mso_stream_count, info->mso_pixel_overlap); 6124 } 6125 6126 static void drm_update_mso(struct drm_connector *connector, 6127 const struct drm_edid *drm_edid) 6128 { 6129 const struct displayid_block *block; 6130 struct displayid_iter iter; 6131 6132 displayid_iter_edid_begin(drm_edid, &iter); 6133 displayid_iter_for_each(block, &iter) { 6134 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6135 drm_parse_vesa_mso_data(connector, block); 6136 } 6137 displayid_iter_end(&iter); 6138 } 6139 6140 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6141 * all of the values which would have been set from EDID 6142 */ 6143 static void drm_reset_display_info(struct drm_connector *connector) 6144 { 6145 struct drm_display_info *info = &connector->display_info; 6146 6147 info->width_mm = 0; 6148 info->height_mm = 0; 6149 6150 info->bpc = 0; 6151 info->color_formats = 0; 6152 info->cea_rev = 0; 6153 info->max_tmds_clock = 0; 6154 info->dvi_dual = false; 6155 info->is_hdmi = false; 6156 info->has_hdmi_infoframe = false; 6157 info->rgb_quant_range_selectable = false; 6158 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6159 6160 info->edid_hdmi_rgb444_dc_modes = 0; 6161 info->edid_hdmi_ycbcr444_dc_modes = 0; 6162 6163 info->non_desktop = 0; 6164 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6165 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6166 6167 info->mso_stream_count = 0; 6168 info->mso_pixel_overlap = 0; 6169 } 6170 6171 static u32 update_display_info(struct drm_connector *connector, 6172 const struct drm_edid *drm_edid) 6173 { 6174 struct drm_display_info *info = &connector->display_info; 6175 const struct edid *edid = drm_edid->edid; 6176 6177 u32 quirks = edid_get_quirks(drm_edid); 6178 6179 drm_reset_display_info(connector); 6180 6181 info->width_mm = edid->width_cm * 10; 6182 info->height_mm = edid->height_cm * 10; 6183 6184 drm_get_monitor_range(connector, drm_edid); 6185 6186 if (edid->revision < 3) 6187 goto out; 6188 6189 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6190 goto out; 6191 6192 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6193 drm_parse_cea_ext(connector, drm_edid); 6194 6195 /* 6196 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6197 * 6198 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6199 * tells us to assume 8 bpc color depth if the EDID doesn't have 6200 * extensions which tell otherwise. 6201 */ 6202 if (info->bpc == 0 && edid->revision == 3 && 6203 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6204 info->bpc = 8; 6205 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 6206 connector->name, info->bpc); 6207 } 6208 6209 /* Only defined for 1.4 with digital displays */ 6210 if (edid->revision < 4) 6211 goto out; 6212 6213 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6214 case DRM_EDID_DIGITAL_DEPTH_6: 6215 info->bpc = 6; 6216 break; 6217 case DRM_EDID_DIGITAL_DEPTH_8: 6218 info->bpc = 8; 6219 break; 6220 case DRM_EDID_DIGITAL_DEPTH_10: 6221 info->bpc = 10; 6222 break; 6223 case DRM_EDID_DIGITAL_DEPTH_12: 6224 info->bpc = 12; 6225 break; 6226 case DRM_EDID_DIGITAL_DEPTH_14: 6227 info->bpc = 14; 6228 break; 6229 case DRM_EDID_DIGITAL_DEPTH_16: 6230 info->bpc = 16; 6231 break; 6232 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6233 default: 6234 info->bpc = 0; 6235 break; 6236 } 6237 6238 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6239 connector->name, info->bpc); 6240 6241 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6242 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6243 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6244 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6245 6246 drm_update_mso(connector, drm_edid); 6247 6248 out: 6249 if (quirks & EDID_QUIRK_NON_DESKTOP) { 6250 drm_dbg_kms(connector->dev, "Non-desktop display%s\n", 6251 info->non_desktop ? " (redundant quirk)" : ""); 6252 info->non_desktop = true; 6253 } 6254 6255 return quirks; 6256 } 6257 6258 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6259 struct displayid_detailed_timings_1 *timings, 6260 bool type_7) 6261 { 6262 struct drm_display_mode *mode; 6263 unsigned pixel_clock = (timings->pixel_clock[0] | 6264 (timings->pixel_clock[1] << 8) | 6265 (timings->pixel_clock[2] << 16)) + 1; 6266 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6267 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6268 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6269 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6270 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6271 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6272 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6273 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6274 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6275 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6276 6277 mode = drm_mode_create(dev); 6278 if (!mode) 6279 return NULL; 6280 6281 /* resolution is kHz for type VII, and 10 kHz for type I */ 6282 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6283 mode->hdisplay = hactive; 6284 mode->hsync_start = mode->hdisplay + hsync; 6285 mode->hsync_end = mode->hsync_start + hsync_width; 6286 mode->htotal = mode->hdisplay + hblank; 6287 6288 mode->vdisplay = vactive; 6289 mode->vsync_start = mode->vdisplay + vsync; 6290 mode->vsync_end = mode->vsync_start + vsync_width; 6291 mode->vtotal = mode->vdisplay + vblank; 6292 6293 mode->flags = 0; 6294 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6295 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6296 mode->type = DRM_MODE_TYPE_DRIVER; 6297 6298 if (timings->flags & 0x80) 6299 mode->type |= DRM_MODE_TYPE_PREFERRED; 6300 drm_mode_set_name(mode); 6301 6302 return mode; 6303 } 6304 6305 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6306 const struct displayid_block *block) 6307 { 6308 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6309 int i; 6310 int num_timings; 6311 struct drm_display_mode *newmode; 6312 int num_modes = 0; 6313 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6314 /* blocks must be multiple of 20 bytes length */ 6315 if (block->num_bytes % 20) 6316 return 0; 6317 6318 num_timings = block->num_bytes / 20; 6319 for (i = 0; i < num_timings; i++) { 6320 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6321 6322 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6323 if (!newmode) 6324 continue; 6325 6326 drm_mode_probed_add(connector, newmode); 6327 num_modes++; 6328 } 6329 return num_modes; 6330 } 6331 6332 static int add_displayid_detailed_modes(struct drm_connector *connector, 6333 const struct drm_edid *drm_edid) 6334 { 6335 const struct displayid_block *block; 6336 struct displayid_iter iter; 6337 int num_modes = 0; 6338 6339 displayid_iter_edid_begin(drm_edid, &iter); 6340 displayid_iter_for_each(block, &iter) { 6341 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6342 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6343 num_modes += add_displayid_detailed_1_modes(connector, block); 6344 } 6345 displayid_iter_end(&iter); 6346 6347 return num_modes; 6348 } 6349 6350 static int _drm_edid_connector_update(struct drm_connector *connector, 6351 const struct drm_edid *drm_edid) 6352 { 6353 int num_modes = 0; 6354 u32 quirks; 6355 6356 if (!drm_edid) { 6357 drm_reset_display_info(connector); 6358 clear_eld(connector); 6359 return 0; 6360 } 6361 6362 /* 6363 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 6364 * To avoid multiple parsing of same block, lets parse that map 6365 * from sink info, before parsing CEA modes. 6366 */ 6367 quirks = update_display_info(connector, drm_edid); 6368 6369 /* Depends on info->cea_rev set by update_display_info() above */ 6370 drm_edid_to_eld(connector, drm_edid); 6371 6372 /* 6373 * EDID spec says modes should be preferred in this order: 6374 * - preferred detailed mode 6375 * - other detailed modes from base block 6376 * - detailed modes from extension blocks 6377 * - CVT 3-byte code modes 6378 * - standard timing codes 6379 * - established timing codes 6380 * - modes inferred from GTF or CVT range information 6381 * 6382 * We get this pretty much right. 6383 * 6384 * XXX order for additional mode types in extension blocks? 6385 */ 6386 num_modes += add_detailed_modes(connector, drm_edid, quirks); 6387 num_modes += add_cvt_modes(connector, drm_edid); 6388 num_modes += add_standard_modes(connector, drm_edid); 6389 num_modes += add_established_modes(connector, drm_edid); 6390 num_modes += add_cea_modes(connector, drm_edid); 6391 num_modes += add_alternate_cea_modes(connector, drm_edid); 6392 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6393 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 6394 num_modes += add_inferred_modes(connector, drm_edid); 6395 6396 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6397 edid_fixup_preferred(connector, quirks); 6398 6399 if (quirks & EDID_QUIRK_FORCE_6BPC) 6400 connector->display_info.bpc = 6; 6401 6402 if (quirks & EDID_QUIRK_FORCE_8BPC) 6403 connector->display_info.bpc = 8; 6404 6405 if (quirks & EDID_QUIRK_FORCE_10BPC) 6406 connector->display_info.bpc = 10; 6407 6408 if (quirks & EDID_QUIRK_FORCE_12BPC) 6409 connector->display_info.bpc = 12; 6410 6411 return num_modes; 6412 } 6413 6414 static void _drm_update_tile_info(struct drm_connector *connector, 6415 const struct drm_edid *drm_edid); 6416 6417 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6418 const struct drm_edid *drm_edid) 6419 { 6420 struct drm_device *dev = connector->dev; 6421 int ret; 6422 6423 if (connector->edid_blob_ptr) { 6424 const struct edid *old_edid = connector->edid_blob_ptr->data; 6425 6426 if (old_edid) { 6427 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6428 connector->epoch_counter++; 6429 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6430 connector->base.id, connector->name, 6431 connector->epoch_counter); 6432 } 6433 } 6434 } 6435 6436 ret = drm_property_replace_global_blob(dev, 6437 &connector->edid_blob_ptr, 6438 drm_edid ? drm_edid->size : 0, 6439 drm_edid ? drm_edid->edid : NULL, 6440 &connector->base, 6441 dev->mode_config.edid_property); 6442 if (ret) { 6443 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6444 connector->base.id, connector->name, ret); 6445 goto out; 6446 } 6447 6448 ret = drm_object_property_set_value(&connector->base, 6449 dev->mode_config.non_desktop_property, 6450 connector->display_info.non_desktop); 6451 if (ret) { 6452 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6453 connector->base.id, connector->name, ret); 6454 goto out; 6455 } 6456 6457 ret = drm_connector_set_tile_property(connector); 6458 if (ret) { 6459 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6460 connector->base.id, connector->name, ret); 6461 goto out; 6462 } 6463 6464 out: 6465 return ret; 6466 } 6467 6468 /** 6469 * drm_edid_connector_update - Update connector information from EDID 6470 * @connector: Connector 6471 * @drm_edid: EDID 6472 * 6473 * Update the connector mode list, display info, ELD, HDR metadata, relevant 6474 * properties, etc. from the passed in EDID. 6475 * 6476 * If EDID is NULL, reset the information. 6477 * 6478 * Return: The number of modes added or 0 if we couldn't find any. 6479 */ 6480 int drm_edid_connector_update(struct drm_connector *connector, 6481 const struct drm_edid *drm_edid) 6482 { 6483 int count; 6484 6485 /* 6486 * FIXME: Reconcile the differences in override_edid handling between 6487 * this and drm_connector_update_edid_property(). 6488 * 6489 * If override_edid is set, and the EDID passed in here originates from 6490 * drm_edid_read() and friends, it will be the override EDID, and there 6491 * are no issues. drm_connector_update_edid_property() ignoring requests 6492 * to set the EDID dates back to a time when override EDID was not 6493 * handled at the low level EDID read. 6494 * 6495 * The only way the EDID passed in here can be different from the 6496 * override EDID is when a driver passes in an EDID that does *not* 6497 * originate from drm_edid_read() and friends, or passes in a stale 6498 * cached version. This, in turn, is a question of when an override EDID 6499 * set via debugfs should take effect. 6500 */ 6501 6502 count = _drm_edid_connector_update(connector, drm_edid); 6503 6504 _drm_update_tile_info(connector, drm_edid); 6505 6506 /* Note: Ignore errors for now. */ 6507 _drm_edid_connector_property_update(connector, drm_edid); 6508 6509 return count; 6510 } 6511 EXPORT_SYMBOL(drm_edid_connector_update); 6512 6513 static int _drm_connector_update_edid_property(struct drm_connector *connector, 6514 const struct drm_edid *drm_edid) 6515 { 6516 /* ignore requests to set edid when overridden */ 6517 if (connector->override_edid) 6518 return 0; 6519 6520 /* 6521 * Set the display info, using edid if available, otherwise resetting 6522 * the values to defaults. This duplicates the work done in 6523 * drm_add_edid_modes, but that function is not consistently called 6524 * before this one in all drivers and the computation is cheap enough 6525 * that it seems better to duplicate it rather than attempt to ensure 6526 * some arbitrary ordering of calls. 6527 */ 6528 if (drm_edid) 6529 update_display_info(connector, drm_edid); 6530 else 6531 drm_reset_display_info(connector); 6532 6533 _drm_update_tile_info(connector, drm_edid); 6534 6535 return _drm_edid_connector_property_update(connector, drm_edid); 6536 } 6537 6538 /** 6539 * drm_connector_update_edid_property - update the edid property of a connector 6540 * @connector: drm connector 6541 * @edid: new value of the edid property 6542 * 6543 * This function creates a new blob modeset object and assigns its id to the 6544 * connector's edid property. 6545 * Since we also parse tile information from EDID's displayID block, we also 6546 * set the connector's tile property here. See drm_connector_set_tile_property() 6547 * for more details. 6548 * 6549 * This function is deprecated. Use drm_edid_connector_update() instead. 6550 * 6551 * Returns: 6552 * Zero on success, negative errno on failure. 6553 */ 6554 int drm_connector_update_edid_property(struct drm_connector *connector, 6555 const struct edid *edid) 6556 { 6557 struct drm_edid drm_edid; 6558 6559 return _drm_connector_update_edid_property(connector, 6560 drm_edid_legacy_init(&drm_edid, edid)); 6561 } 6562 EXPORT_SYMBOL(drm_connector_update_edid_property); 6563 6564 /** 6565 * drm_add_edid_modes - add modes from EDID data, if available 6566 * @connector: connector we're probing 6567 * @edid: EDID data 6568 * 6569 * Add the specified modes to the connector's mode list. Also fills out the 6570 * &drm_display_info structure and ELD in @connector with any information which 6571 * can be derived from the edid. 6572 * 6573 * This function is deprecated. Use drm_edid_connector_update() instead. 6574 * 6575 * Return: The number of modes added or 0 if we couldn't find any. 6576 */ 6577 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6578 { 6579 struct drm_edid drm_edid; 6580 6581 if (edid && !drm_edid_is_valid(edid)) { 6582 drm_warn(connector->dev, "%s: EDID invalid.\n", 6583 connector->name); 6584 edid = NULL; 6585 } 6586 6587 return _drm_edid_connector_update(connector, 6588 drm_edid_legacy_init(&drm_edid, edid)); 6589 } 6590 EXPORT_SYMBOL(drm_add_edid_modes); 6591 6592 /** 6593 * drm_add_modes_noedid - add modes for the connectors without EDID 6594 * @connector: connector we're probing 6595 * @hdisplay: the horizontal display limit 6596 * @vdisplay: the vertical display limit 6597 * 6598 * Add the specified modes to the connector's mode list. Only when the 6599 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6600 * 6601 * Return: The number of modes added or 0 if we couldn't find any. 6602 */ 6603 int drm_add_modes_noedid(struct drm_connector *connector, 6604 int hdisplay, int vdisplay) 6605 { 6606 int i, count, num_modes = 0; 6607 struct drm_display_mode *mode; 6608 struct drm_device *dev = connector->dev; 6609 6610 count = ARRAY_SIZE(drm_dmt_modes); 6611 if (hdisplay < 0) 6612 hdisplay = 0; 6613 if (vdisplay < 0) 6614 vdisplay = 0; 6615 6616 for (i = 0; i < count; i++) { 6617 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6618 6619 if (hdisplay && vdisplay) { 6620 /* 6621 * Only when two are valid, they will be used to check 6622 * whether the mode should be added to the mode list of 6623 * the connector. 6624 */ 6625 if (ptr->hdisplay > hdisplay || 6626 ptr->vdisplay > vdisplay) 6627 continue; 6628 } 6629 if (drm_mode_vrefresh(ptr) > 61) 6630 continue; 6631 mode = drm_mode_duplicate(dev, ptr); 6632 if (mode) { 6633 drm_mode_probed_add(connector, mode); 6634 num_modes++; 6635 } 6636 } 6637 return num_modes; 6638 } 6639 EXPORT_SYMBOL(drm_add_modes_noedid); 6640 6641 /** 6642 * drm_set_preferred_mode - Sets the preferred mode of a connector 6643 * @connector: connector whose mode list should be processed 6644 * @hpref: horizontal resolution of preferred mode 6645 * @vpref: vertical resolution of preferred mode 6646 * 6647 * Marks a mode as preferred if it matches the resolution specified by @hpref 6648 * and @vpref. 6649 */ 6650 void drm_set_preferred_mode(struct drm_connector *connector, 6651 int hpref, int vpref) 6652 { 6653 struct drm_display_mode *mode; 6654 6655 list_for_each_entry(mode, &connector->probed_modes, head) { 6656 if (mode->hdisplay == hpref && 6657 mode->vdisplay == vpref) 6658 mode->type |= DRM_MODE_TYPE_PREFERRED; 6659 } 6660 } 6661 EXPORT_SYMBOL(drm_set_preferred_mode); 6662 6663 static bool is_hdmi2_sink(const struct drm_connector *connector) 6664 { 6665 /* 6666 * FIXME: sil-sii8620 doesn't have a connector around when 6667 * we need one, so we have to be prepared for a NULL connector. 6668 */ 6669 if (!connector) 6670 return true; 6671 6672 return connector->display_info.hdmi.scdc.supported || 6673 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6674 } 6675 6676 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6677 const struct drm_display_mode *mode) 6678 { 6679 bool has_hdmi_infoframe = connector ? 6680 connector->display_info.has_hdmi_infoframe : false; 6681 6682 if (!has_hdmi_infoframe) 6683 return 0; 6684 6685 /* No HDMI VIC when signalling 3D video format */ 6686 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 6687 return 0; 6688 6689 return drm_match_hdmi_mode(mode); 6690 } 6691 6692 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 6693 const struct drm_display_mode *mode) 6694 { 6695 u8 vic; 6696 6697 /* 6698 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 6699 * we should send its VIC in vendor infoframes, else send the 6700 * VIC in AVI infoframes. Lets check if this mode is present in 6701 * HDMI 1.4b 4K modes 6702 */ 6703 if (drm_mode_hdmi_vic(connector, mode)) 6704 return 0; 6705 6706 vic = drm_match_cea_mode(mode); 6707 6708 /* 6709 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 6710 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 6711 * have to make sure we dont break HDMI 1.4 sinks. 6712 */ 6713 if (!is_hdmi2_sink(connector) && vic > 64) 6714 return 0; 6715 6716 return vic; 6717 } 6718 6719 /** 6720 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 6721 * data from a DRM display mode 6722 * @frame: HDMI AVI infoframe 6723 * @connector: the connector 6724 * @mode: DRM display mode 6725 * 6726 * Return: 0 on success or a negative error code on failure. 6727 */ 6728 int 6729 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 6730 const struct drm_connector *connector, 6731 const struct drm_display_mode *mode) 6732 { 6733 enum hdmi_picture_aspect picture_aspect; 6734 u8 vic, hdmi_vic; 6735 6736 if (!frame || !mode) 6737 return -EINVAL; 6738 6739 hdmi_avi_infoframe_init(frame); 6740 6741 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 6742 frame->pixel_repeat = 1; 6743 6744 vic = drm_mode_cea_vic(connector, mode); 6745 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 6746 6747 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6748 6749 /* 6750 * As some drivers don't support atomic, we can't use connector state. 6751 * So just initialize the frame with default values, just the same way 6752 * as it's done with other properties here. 6753 */ 6754 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 6755 frame->itc = 0; 6756 6757 /* 6758 * Populate picture aspect ratio from either 6759 * user input (if specified) or from the CEA/HDMI mode lists. 6760 */ 6761 picture_aspect = mode->picture_aspect_ratio; 6762 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 6763 if (vic) 6764 picture_aspect = drm_get_cea_aspect_ratio(vic); 6765 else if (hdmi_vic) 6766 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 6767 } 6768 6769 /* 6770 * The infoframe can't convey anything but none, 4:3 6771 * and 16:9, so if the user has asked for anything else 6772 * we can only satisfy it by specifying the right VIC. 6773 */ 6774 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 6775 if (vic) { 6776 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 6777 return -EINVAL; 6778 } else if (hdmi_vic) { 6779 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 6780 return -EINVAL; 6781 } else { 6782 return -EINVAL; 6783 } 6784 6785 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6786 } 6787 6788 frame->video_code = vic; 6789 frame->picture_aspect = picture_aspect; 6790 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 6791 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 6792 6793 return 0; 6794 } 6795 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 6796 6797 /** 6798 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 6799 * quantization range information 6800 * @frame: HDMI AVI infoframe 6801 * @connector: the connector 6802 * @mode: DRM display mode 6803 * @rgb_quant_range: RGB quantization range (Q) 6804 */ 6805 void 6806 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6807 const struct drm_connector *connector, 6808 const struct drm_display_mode *mode, 6809 enum hdmi_quantization_range rgb_quant_range) 6810 { 6811 const struct drm_display_info *info = &connector->display_info; 6812 6813 /* 6814 * CEA-861: 6815 * "A Source shall not send a non-zero Q value that does not correspond 6816 * to the default RGB Quantization Range for the transmitted Picture 6817 * unless the Sink indicates support for the Q bit in a Video 6818 * Capabilities Data Block." 6819 * 6820 * HDMI 2.0 recommends sending non-zero Q when it does match the 6821 * default RGB quantization range for the mode, even when QS=0. 6822 */ 6823 if (info->rgb_quant_range_selectable || 6824 rgb_quant_range == drm_default_rgb_quant_range(mode)) 6825 frame->quantization_range = rgb_quant_range; 6826 else 6827 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 6828 6829 /* 6830 * CEA-861-F: 6831 * "When transmitting any RGB colorimetry, the Source should set the 6832 * YQ-field to match the RGB Quantization Range being transmitted 6833 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 6834 * set YQ=1) and the Sink shall ignore the YQ-field." 6835 * 6836 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 6837 * by non-zero YQ when receiving RGB. There doesn't seem to be any 6838 * good way to tell which version of CEA-861 the sink supports, so 6839 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 6840 * on on CEA-861-F. 6841 */ 6842 if (!is_hdmi2_sink(connector) || 6843 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 6844 frame->ycc_quantization_range = 6845 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 6846 else 6847 frame->ycc_quantization_range = 6848 HDMI_YCC_QUANTIZATION_RANGE_FULL; 6849 } 6850 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 6851 6852 static enum hdmi_3d_structure 6853 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 6854 { 6855 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 6856 6857 switch (layout) { 6858 case DRM_MODE_FLAG_3D_FRAME_PACKING: 6859 return HDMI_3D_STRUCTURE_FRAME_PACKING; 6860 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 6861 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 6862 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 6863 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 6864 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 6865 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 6866 case DRM_MODE_FLAG_3D_L_DEPTH: 6867 return HDMI_3D_STRUCTURE_L_DEPTH; 6868 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 6869 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 6870 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 6871 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 6872 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 6873 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 6874 default: 6875 return HDMI_3D_STRUCTURE_INVALID; 6876 } 6877 } 6878 6879 /** 6880 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 6881 * data from a DRM display mode 6882 * @frame: HDMI vendor infoframe 6883 * @connector: the connector 6884 * @mode: DRM display mode 6885 * 6886 * Note that there's is a need to send HDMI vendor infoframes only when using a 6887 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 6888 * function will return -EINVAL, error that can be safely ignored. 6889 * 6890 * Return: 0 on success or a negative error code on failure. 6891 */ 6892 int 6893 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 6894 const struct drm_connector *connector, 6895 const struct drm_display_mode *mode) 6896 { 6897 /* 6898 * FIXME: sil-sii8620 doesn't have a connector around when 6899 * we need one, so we have to be prepared for a NULL connector. 6900 */ 6901 bool has_hdmi_infoframe = connector ? 6902 connector->display_info.has_hdmi_infoframe : false; 6903 int err; 6904 6905 if (!frame || !mode) 6906 return -EINVAL; 6907 6908 if (!has_hdmi_infoframe) 6909 return -EINVAL; 6910 6911 err = hdmi_vendor_infoframe_init(frame); 6912 if (err < 0) 6913 return err; 6914 6915 /* 6916 * Even if it's not absolutely necessary to send the infoframe 6917 * (ie.vic==0 and s3d_struct==0) we will still send it if we 6918 * know that the sink can handle it. This is based on a 6919 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 6920 * have trouble realizing that they should switch from 3D to 2D 6921 * mode if the source simply stops sending the infoframe when 6922 * it wants to switch from 3D to 2D. 6923 */ 6924 frame->vic = drm_mode_hdmi_vic(connector, mode); 6925 frame->s3d_struct = s3d_structure_from_display_mode(mode); 6926 6927 return 0; 6928 } 6929 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 6930 6931 static void drm_parse_tiled_block(struct drm_connector *connector, 6932 const struct displayid_block *block) 6933 { 6934 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6935 u16 w, h; 6936 u8 tile_v_loc, tile_h_loc; 6937 u8 num_v_tile, num_h_tile; 6938 struct drm_tile_group *tg; 6939 6940 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6941 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6942 6943 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6944 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6945 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6946 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6947 6948 connector->has_tile = true; 6949 if (tile->tile_cap & 0x80) 6950 connector->tile_is_single_monitor = true; 6951 6952 connector->num_h_tile = num_h_tile + 1; 6953 connector->num_v_tile = num_v_tile + 1; 6954 connector->tile_h_loc = tile_h_loc; 6955 connector->tile_v_loc = tile_v_loc; 6956 connector->tile_h_size = w + 1; 6957 connector->tile_v_size = h + 1; 6958 6959 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6960 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6961 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6962 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6963 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6964 6965 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6966 if (!tg) 6967 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6968 if (!tg) 6969 return; 6970 6971 if (connector->tile_group != tg) { 6972 /* if we haven't got a pointer, 6973 take the reference, drop ref to old tile group */ 6974 if (connector->tile_group) 6975 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6976 connector->tile_group = tg; 6977 } else { 6978 /* if same tile group, then release the ref we just took. */ 6979 drm_mode_put_tile_group(connector->dev, tg); 6980 } 6981 } 6982 6983 static void _drm_update_tile_info(struct drm_connector *connector, 6984 const struct drm_edid *drm_edid) 6985 { 6986 const struct displayid_block *block; 6987 struct displayid_iter iter; 6988 6989 connector->has_tile = false; 6990 6991 displayid_iter_edid_begin(drm_edid, &iter); 6992 displayid_iter_for_each(block, &iter) { 6993 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6994 drm_parse_tiled_block(connector, block); 6995 } 6996 displayid_iter_end(&iter); 6997 6998 if (!connector->has_tile && connector->tile_group) { 6999 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7000 connector->tile_group = NULL; 7001 } 7002 } 7003