1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <drm/drmP.h> 36 #include <drm/drm_edid.h> 37 38 #define version_greater(edid, maj, min) \ 39 (((edid)->version > (maj)) || \ 40 ((edid)->version == (maj) && (edid)->revision > (min))) 41 42 #define EDID_EST_TIMINGS 16 43 #define EDID_STD_TIMINGS 8 44 #define EDID_DETAILED_TIMINGS 4 45 46 /* 47 * EDID blocks out in the wild have a variety of bugs, try to collect 48 * them here (note that userspace may work around broken monitors first, 49 * but fixes should make their way here so that the kernel "just works" 50 * on as many displays as possible). 51 */ 52 53 /* First detailed mode wrong, use largest 60Hz mode */ 54 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 55 /* Reported 135MHz pixel clock is too high, needs adjustment */ 56 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 57 /* Prefer the largest mode at 75 Hz */ 58 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 59 /* Detail timing is in cm not mm */ 60 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 61 /* Detailed timing descriptors have bogus size values, so just take the 62 * maximum size and use that. 63 */ 64 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 65 /* Monitor forgot to set the first detailed is preferred bit. */ 66 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 67 /* use +hsync +vsync for detailed mode */ 68 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 69 /* Force reduced-blanking timings for detailed modes */ 70 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 71 72 struct detailed_mode_closure { 73 struct drm_connector *connector; 74 struct edid *edid; 75 bool preferred; 76 u32 quirks; 77 int modes; 78 }; 79 80 #define LEVEL_DMT 0 81 #define LEVEL_GTF 1 82 #define LEVEL_GTF2 2 83 #define LEVEL_CVT 3 84 85 static struct edid_quirk { 86 char vendor[4]; 87 int product_id; 88 u32 quirks; 89 } edid_quirk_list[] = { 90 /* Acer AL1706 */ 91 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 92 /* Acer F51 */ 93 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Unknown Acer */ 95 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 96 97 /* Belinea 10 15 55 */ 98 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 99 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 100 101 /* Envision Peripherals, Inc. EN-7100e */ 102 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 103 /* Envision EN2028 */ 104 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Funai Electronics PM36B */ 107 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 108 EDID_QUIRK_DETAILED_IN_CM }, 109 110 /* LG Philips LCD LP154W01-A5 */ 111 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 112 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 113 114 /* Philips 107p5 CRT */ 115 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 116 117 /* Proview AY765C */ 118 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 119 120 /* Samsung SyncMaster 205BW. Note: irony */ 121 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 122 /* Samsung SyncMaster 22[5-6]BW */ 123 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 124 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 125 126 /* ViewSonic VA2026w */ 127 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 128 129 /* Medion MD 30217 PG */ 130 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 131 }; 132 133 /* 134 * Autogenerated from the DMT spec. 135 * This table is copied from xfree86/modes/xf86EdidModes.c. 136 */ 137 static const struct drm_display_mode drm_dmt_modes[] = { 138 /* 640x350@85Hz */ 139 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 140 736, 832, 0, 350, 382, 385, 445, 0, 141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 142 /* 640x400@85Hz */ 143 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 144 736, 832, 0, 400, 401, 404, 445, 0, 145 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 146 /* 720x400@85Hz */ 147 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 148 828, 936, 0, 400, 401, 404, 446, 0, 149 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 150 /* 640x480@60Hz */ 151 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 152 752, 800, 0, 480, 489, 492, 525, 0, 153 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 154 /* 640x480@72Hz */ 155 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 156 704, 832, 0, 480, 489, 492, 520, 0, 157 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 158 /* 640x480@75Hz */ 159 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 160 720, 840, 0, 480, 481, 484, 500, 0, 161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 162 /* 640x480@85Hz */ 163 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 164 752, 832, 0, 480, 481, 484, 509, 0, 165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 166 /* 800x600@56Hz */ 167 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 168 896, 1024, 0, 600, 601, 603, 625, 0, 169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 170 /* 800x600@60Hz */ 171 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 172 968, 1056, 0, 600, 601, 605, 628, 0, 173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 174 /* 800x600@72Hz */ 175 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 176 976, 1040, 0, 600, 637, 643, 666, 0, 177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 178 /* 800x600@75Hz */ 179 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 180 896, 1056, 0, 600, 601, 604, 625, 0, 181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 182 /* 800x600@85Hz */ 183 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 184 896, 1048, 0, 600, 601, 604, 631, 0, 185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 186 /* 800x600@120Hz RB */ 187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 188 880, 960, 0, 600, 603, 607, 636, 0, 189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 190 /* 848x480@60Hz */ 191 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 192 976, 1088, 0, 480, 486, 494, 517, 0, 193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 194 /* 1024x768@43Hz, interlace */ 195 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 196 1208, 1264, 0, 768, 768, 772, 817, 0, 197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 198 DRM_MODE_FLAG_INTERLACE) }, 199 /* 1024x768@60Hz */ 200 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 201 1184, 1344, 0, 768, 771, 777, 806, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 203 /* 1024x768@70Hz */ 204 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 205 1184, 1328, 0, 768, 771, 777, 806, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 207 /* 1024x768@75Hz */ 208 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 209 1136, 1312, 0, 768, 769, 772, 800, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 1024x768@85Hz */ 212 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 213 1168, 1376, 0, 768, 769, 772, 808, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 1024x768@120Hz RB */ 216 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 217 1104, 1184, 0, 768, 771, 775, 813, 0, 218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 1152x864@75Hz */ 220 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 221 1344, 1600, 0, 864, 865, 868, 900, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 1280x768@60Hz RB */ 224 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 225 1360, 1440, 0, 768, 771, 778, 790, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 227 /* 1280x768@60Hz */ 228 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 229 1472, 1664, 0, 768, 771, 778, 798, 0, 230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 231 /* 1280x768@75Hz */ 232 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 233 1488, 1696, 0, 768, 771, 778, 805, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 235 /* 1280x768@85Hz */ 236 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 237 1496, 1712, 0, 768, 771, 778, 809, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 239 /* 1280x768@120Hz RB */ 240 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 241 1360, 1440, 0, 768, 771, 778, 813, 0, 242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 243 /* 1280x800@60Hz RB */ 244 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 245 1360, 1440, 0, 800, 803, 809, 823, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 247 /* 1280x800@60Hz */ 248 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 249 1480, 1680, 0, 800, 803, 809, 831, 0, 250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 1280x800@75Hz */ 252 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 253 1488, 1696, 0, 800, 803, 809, 838, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 255 /* 1280x800@85Hz */ 256 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 257 1496, 1712, 0, 800, 803, 809, 843, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 259 /* 1280x800@120Hz RB */ 260 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 261 1360, 1440, 0, 800, 803, 809, 847, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 263 /* 1280x960@60Hz */ 264 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 265 1488, 1800, 0, 960, 961, 964, 1000, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 267 /* 1280x960@85Hz */ 268 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 269 1504, 1728, 0, 960, 961, 964, 1011, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 271 /* 1280x960@120Hz RB */ 272 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 273 1360, 1440, 0, 960, 963, 967, 1017, 0, 274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 275 /* 1280x1024@60Hz */ 276 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 277 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 1280x1024@75Hz */ 280 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 281 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 283 /* 1280x1024@85Hz */ 284 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 285 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 287 /* 1280x1024@120Hz RB */ 288 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 289 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 291 /* 1360x768@60Hz */ 292 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 293 1536, 1792, 0, 768, 771, 777, 795, 0, 294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 295 /* 1360x768@120Hz RB */ 296 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 297 1440, 1520, 0, 768, 771, 776, 813, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 299 /* 1400x1050@60Hz RB */ 300 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 301 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 303 /* 1400x1050@60Hz */ 304 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 305 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 307 /* 1400x1050@75Hz */ 308 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 309 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 1400x1050@85Hz */ 312 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 313 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 1400x1050@120Hz RB */ 316 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 317 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 319 /* 1440x900@60Hz RB */ 320 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 321 1520, 1600, 0, 900, 903, 909, 926, 0, 322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 323 /* 1440x900@60Hz */ 324 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 325 1672, 1904, 0, 900, 903, 909, 934, 0, 326 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 1440x900@75Hz */ 328 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 329 1688, 1936, 0, 900, 903, 909, 942, 0, 330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 331 /* 1440x900@85Hz */ 332 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 333 1696, 1952, 0, 900, 903, 909, 948, 0, 334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 335 /* 1440x900@120Hz RB */ 336 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 337 1520, 1600, 0, 900, 903, 909, 953, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 339 /* 1600x1200@60Hz */ 340 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 341 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 1600x1200@65Hz */ 344 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 345 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 1600x1200@70Hz */ 348 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 349 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 351 /* 1600x1200@75Hz */ 352 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 353 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 355 /* 1600x1200@85Hz */ 356 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 357 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 1600x1200@120Hz RB */ 360 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 361 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 363 /* 1680x1050@60Hz RB */ 364 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 365 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 367 /* 1680x1050@60Hz */ 368 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 369 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 1680x1050@75Hz */ 372 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 373 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 1680x1050@85Hz */ 376 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 377 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 379 /* 1680x1050@120Hz RB */ 380 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 381 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 383 /* 1792x1344@60Hz */ 384 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 385 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 1792x1344@75Hz */ 388 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 389 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 391 /* 1792x1344@120Hz RB */ 392 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 393 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 395 /* 1856x1392@60Hz */ 396 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 397 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 1856x1392@75Hz */ 400 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 401 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, 402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 403 /* 1856x1392@120Hz RB */ 404 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 405 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 407 /* 1920x1200@60Hz RB */ 408 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 409 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 411 /* 1920x1200@60Hz */ 412 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 413 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 1920x1200@75Hz */ 416 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 417 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 419 /* 1920x1200@85Hz */ 420 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 421 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 423 /* 1920x1200@120Hz RB */ 424 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 425 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 427 /* 1920x1440@60Hz */ 428 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 429 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 1920x1440@75Hz */ 432 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 433 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 435 /* 1920x1440@120Hz RB */ 436 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 437 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 439 /* 2560x1600@60Hz RB */ 440 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 441 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 443 /* 2560x1600@60Hz */ 444 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 445 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 2560x1600@75HZ */ 448 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 449 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 451 /* 2560x1600@85HZ */ 452 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 453 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 2560x1600@120Hz RB */ 456 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 457 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 459 }; 460 461 /* 462 * These more or less come from the DMT spec. The 720x400 modes are 463 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 464 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 465 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 466 * mode. 467 * 468 * The DMT modes have been fact-checked; the rest are mild guesses. 469 */ 470 static const struct drm_display_mode edid_est_modes[] = { 471 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 472 968, 1056, 0, 600, 601, 605, 628, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 474 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 475 896, 1024, 0, 600, 601, 603, 625, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 477 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 478 720, 840, 0, 480, 481, 484, 500, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 480 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 481 704, 832, 0, 480, 489, 491, 520, 0, 482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 483 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 484 768, 864, 0, 480, 483, 486, 525, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 486 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 487 752, 800, 0, 480, 490, 492, 525, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 489 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 490 846, 900, 0, 400, 421, 423, 449, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 492 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 493 846, 900, 0, 400, 412, 414, 449, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 495 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 496 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 498 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 499 1136, 1312, 0, 768, 769, 772, 800, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 501 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 502 1184, 1328, 0, 768, 771, 777, 806, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 504 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 505 1184, 1344, 0, 768, 771, 777, 806, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 507 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 508 1208, 1264, 0, 768, 768, 776, 817, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 510 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 511 928, 1152, 0, 624, 625, 628, 667, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 513 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 514 896, 1056, 0, 600, 601, 604, 625, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 516 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 517 976, 1040, 0, 600, 637, 643, 666, 0, 518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 519 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 520 1344, 1600, 0, 864, 865, 868, 900, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 522 }; 523 524 struct minimode { 525 short w; 526 short h; 527 short r; 528 short rb; 529 }; 530 531 static const struct minimode est3_modes[] = { 532 /* byte 6 */ 533 { 640, 350, 85, 0 }, 534 { 640, 400, 85, 0 }, 535 { 720, 400, 85, 0 }, 536 { 640, 480, 85, 0 }, 537 { 848, 480, 60, 0 }, 538 { 800, 600, 85, 0 }, 539 { 1024, 768, 85, 0 }, 540 { 1152, 864, 75, 0 }, 541 /* byte 7 */ 542 { 1280, 768, 60, 1 }, 543 { 1280, 768, 60, 0 }, 544 { 1280, 768, 75, 0 }, 545 { 1280, 768, 85, 0 }, 546 { 1280, 960, 60, 0 }, 547 { 1280, 960, 85, 0 }, 548 { 1280, 1024, 60, 0 }, 549 { 1280, 1024, 85, 0 }, 550 /* byte 8 */ 551 { 1360, 768, 60, 0 }, 552 { 1440, 900, 60, 1 }, 553 { 1440, 900, 60, 0 }, 554 { 1440, 900, 75, 0 }, 555 { 1440, 900, 85, 0 }, 556 { 1400, 1050, 60, 1 }, 557 { 1400, 1050, 60, 0 }, 558 { 1400, 1050, 75, 0 }, 559 /* byte 9 */ 560 { 1400, 1050, 85, 0 }, 561 { 1680, 1050, 60, 1 }, 562 { 1680, 1050, 60, 0 }, 563 { 1680, 1050, 75, 0 }, 564 { 1680, 1050, 85, 0 }, 565 { 1600, 1200, 60, 0 }, 566 { 1600, 1200, 65, 0 }, 567 { 1600, 1200, 70, 0 }, 568 /* byte 10 */ 569 { 1600, 1200, 75, 0 }, 570 { 1600, 1200, 85, 0 }, 571 { 1792, 1344, 60, 0 }, 572 { 1792, 1344, 75, 0 }, 573 { 1856, 1392, 60, 0 }, 574 { 1856, 1392, 75, 0 }, 575 { 1920, 1200, 60, 1 }, 576 { 1920, 1200, 60, 0 }, 577 /* byte 11 */ 578 { 1920, 1200, 75, 0 }, 579 { 1920, 1200, 85, 0 }, 580 { 1920, 1440, 60, 0 }, 581 { 1920, 1440, 75, 0 }, 582 }; 583 584 static const struct minimode extra_modes[] = { 585 { 1024, 576, 60, 0 }, 586 { 1366, 768, 60, 0 }, 587 { 1600, 900, 60, 0 }, 588 { 1680, 945, 60, 0 }, 589 { 1920, 1080, 60, 0 }, 590 { 2048, 1152, 60, 0 }, 591 { 2048, 1536, 60, 0 }, 592 }; 593 594 /* 595 * Probably taken from CEA-861 spec. 596 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 597 */ 598 static const struct drm_display_mode edid_cea_modes[] = { 599 /* 1 - 640x480@60Hz */ 600 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 601 752, 800, 0, 480, 490, 492, 525, 0, 602 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 603 .vrefresh = 60, }, 604 /* 2 - 720x480@60Hz */ 605 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 606 798, 858, 0, 480, 489, 495, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 608 .vrefresh = 60, }, 609 /* 3 - 720x480@60Hz */ 610 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 611 798, 858, 0, 480, 489, 495, 525, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 613 .vrefresh = 60, }, 614 /* 4 - 1280x720@60Hz */ 615 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 616 1430, 1650, 0, 720, 725, 730, 750, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 618 .vrefresh = 60, }, 619 /* 5 - 1920x1080i@60Hz */ 620 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 621 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 623 DRM_MODE_FLAG_INTERLACE), 624 .vrefresh = 60, }, 625 /* 6 - 1440x480i@60Hz */ 626 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 627 1602, 1716, 0, 480, 488, 494, 525, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 629 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 630 .vrefresh = 60, }, 631 /* 7 - 1440x480i@60Hz */ 632 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 633 1602, 1716, 0, 480, 488, 494, 525, 0, 634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 635 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 636 .vrefresh = 60, }, 637 /* 8 - 1440x240@60Hz */ 638 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 639 1602, 1716, 0, 240, 244, 247, 262, 0, 640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 641 DRM_MODE_FLAG_DBLCLK), 642 .vrefresh = 60, }, 643 /* 9 - 1440x240@60Hz */ 644 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 645 1602, 1716, 0, 240, 244, 247, 262, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 647 DRM_MODE_FLAG_DBLCLK), 648 .vrefresh = 60, }, 649 /* 10 - 2880x480i@60Hz */ 650 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 651 3204, 3432, 0, 480, 488, 494, 525, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 653 DRM_MODE_FLAG_INTERLACE), 654 .vrefresh = 60, }, 655 /* 11 - 2880x480i@60Hz */ 656 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 657 3204, 3432, 0, 480, 488, 494, 525, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 659 DRM_MODE_FLAG_INTERLACE), 660 .vrefresh = 60, }, 661 /* 12 - 2880x240@60Hz */ 662 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 663 3204, 3432, 0, 240, 244, 247, 262, 0, 664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 665 .vrefresh = 60, }, 666 /* 13 - 2880x240@60Hz */ 667 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 668 3204, 3432, 0, 240, 244, 247, 262, 0, 669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 670 .vrefresh = 60, }, 671 /* 14 - 1440x480@60Hz */ 672 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 673 1596, 1716, 0, 480, 489, 495, 525, 0, 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 675 .vrefresh = 60, }, 676 /* 15 - 1440x480@60Hz */ 677 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 678 1596, 1716, 0, 480, 489, 495, 525, 0, 679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 680 .vrefresh = 60, }, 681 /* 16 - 1920x1080@60Hz */ 682 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 683 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 685 .vrefresh = 60, }, 686 /* 17 - 720x576@50Hz */ 687 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 688 796, 864, 0, 576, 581, 586, 625, 0, 689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 690 .vrefresh = 50, }, 691 /* 18 - 720x576@50Hz */ 692 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 693 796, 864, 0, 576, 581, 586, 625, 0, 694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 695 .vrefresh = 50, }, 696 /* 19 - 1280x720@50Hz */ 697 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 698 1760, 1980, 0, 720, 725, 730, 750, 0, 699 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 700 .vrefresh = 50, }, 701 /* 20 - 1920x1080i@50Hz */ 702 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 703 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 705 DRM_MODE_FLAG_INTERLACE), 706 .vrefresh = 50, }, 707 /* 21 - 1440x576i@50Hz */ 708 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 709 1590, 1728, 0, 576, 580, 586, 625, 0, 710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 711 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 712 .vrefresh = 50, }, 713 /* 22 - 1440x576i@50Hz */ 714 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 715 1590, 1728, 0, 576, 580, 586, 625, 0, 716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 717 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 718 .vrefresh = 50, }, 719 /* 23 - 1440x288@50Hz */ 720 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 721 1590, 1728, 0, 288, 290, 293, 312, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 723 DRM_MODE_FLAG_DBLCLK), 724 .vrefresh = 50, }, 725 /* 24 - 1440x288@50Hz */ 726 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 727 1590, 1728, 0, 288, 290, 293, 312, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 729 DRM_MODE_FLAG_DBLCLK), 730 .vrefresh = 50, }, 731 /* 25 - 2880x576i@50Hz */ 732 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 733 3180, 3456, 0, 576, 580, 586, 625, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 735 DRM_MODE_FLAG_INTERLACE), 736 .vrefresh = 50, }, 737 /* 26 - 2880x576i@50Hz */ 738 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 739 3180, 3456, 0, 576, 580, 586, 625, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 741 DRM_MODE_FLAG_INTERLACE), 742 .vrefresh = 50, }, 743 /* 27 - 2880x288@50Hz */ 744 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 745 3180, 3456, 0, 288, 290, 293, 312, 0, 746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 747 .vrefresh = 50, }, 748 /* 28 - 2880x288@50Hz */ 749 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 750 3180, 3456, 0, 288, 290, 293, 312, 0, 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 752 .vrefresh = 50, }, 753 /* 29 - 1440x576@50Hz */ 754 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 755 1592, 1728, 0, 576, 581, 586, 625, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 757 .vrefresh = 50, }, 758 /* 30 - 1440x576@50Hz */ 759 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 760 1592, 1728, 0, 576, 581, 586, 625, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 762 .vrefresh = 50, }, 763 /* 31 - 1920x1080@50Hz */ 764 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 765 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 767 .vrefresh = 50, }, 768 /* 32 - 1920x1080@24Hz */ 769 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 770 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 772 .vrefresh = 24, }, 773 /* 33 - 1920x1080@25Hz */ 774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 775 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 777 .vrefresh = 25, }, 778 /* 34 - 1920x1080@30Hz */ 779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 780 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 782 .vrefresh = 30, }, 783 /* 35 - 2880x480@60Hz */ 784 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 785 3192, 3432, 0, 480, 489, 495, 525, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 787 .vrefresh = 60, }, 788 /* 36 - 2880x480@60Hz */ 789 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 790 3192, 3432, 0, 480, 489, 495, 525, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 792 .vrefresh = 60, }, 793 /* 37 - 2880x576@50Hz */ 794 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 795 3184, 3456, 0, 576, 581, 586, 625, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 50, }, 798 /* 38 - 2880x576@50Hz */ 799 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 800 3184, 3456, 0, 576, 581, 586, 625, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 50, }, 803 /* 39 - 1920x1080i@50Hz */ 804 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 805 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 807 DRM_MODE_FLAG_INTERLACE), 808 .vrefresh = 50, }, 809 /* 40 - 1920x1080i@100Hz */ 810 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 811 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 813 DRM_MODE_FLAG_INTERLACE), 814 .vrefresh = 100, }, 815 /* 41 - 1280x720@100Hz */ 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 817 1760, 1980, 0, 720, 725, 730, 750, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .vrefresh = 100, }, 820 /* 42 - 720x576@100Hz */ 821 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 822 796, 864, 0, 576, 581, 586, 625, 0, 823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 824 .vrefresh = 100, }, 825 /* 43 - 720x576@100Hz */ 826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 827 796, 864, 0, 576, 581, 586, 625, 0, 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 829 .vrefresh = 100, }, 830 /* 44 - 1440x576i@100Hz */ 831 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 832 1590, 1728, 0, 576, 580, 586, 625, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 834 DRM_MODE_FLAG_DBLCLK), 835 .vrefresh = 100, }, 836 /* 45 - 1440x576i@100Hz */ 837 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 838 1590, 1728, 0, 576, 580, 586, 625, 0, 839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 840 DRM_MODE_FLAG_DBLCLK), 841 .vrefresh = 100, }, 842 /* 46 - 1920x1080i@120Hz */ 843 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 844 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 846 DRM_MODE_FLAG_INTERLACE), 847 .vrefresh = 120, }, 848 /* 47 - 1280x720@120Hz */ 849 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 850 1430, 1650, 0, 720, 725, 730, 750, 0, 851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 852 .vrefresh = 120, }, 853 /* 48 - 720x480@120Hz */ 854 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 855 798, 858, 0, 480, 489, 495, 525, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .vrefresh = 120, }, 858 /* 49 - 720x480@120Hz */ 859 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 860 798, 858, 0, 480, 489, 495, 525, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 862 .vrefresh = 120, }, 863 /* 50 - 1440x480i@120Hz */ 864 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 865 1602, 1716, 0, 480, 488, 494, 525, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 867 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 868 .vrefresh = 120, }, 869 /* 51 - 1440x480i@120Hz */ 870 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 871 1602, 1716, 0, 480, 488, 494, 525, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 873 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 874 .vrefresh = 120, }, 875 /* 52 - 720x576@200Hz */ 876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 877 796, 864, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 200, }, 880 /* 53 - 720x576@200Hz */ 881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 882 796, 864, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 200, }, 885 /* 54 - 1440x576i@200Hz */ 886 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 887 1590, 1728, 0, 576, 580, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 889 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 890 .vrefresh = 200, }, 891 /* 55 - 1440x576i@200Hz */ 892 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 893 1590, 1728, 0, 576, 580, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 895 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 896 .vrefresh = 200, }, 897 /* 56 - 720x480@240Hz */ 898 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 899 798, 858, 0, 480, 489, 495, 525, 0, 900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 901 .vrefresh = 240, }, 902 /* 57 - 720x480@240Hz */ 903 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 904 798, 858, 0, 480, 489, 495, 525, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 906 .vrefresh = 240, }, 907 /* 58 - 1440x480i@240 */ 908 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 909 1602, 1716, 0, 480, 488, 494, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 911 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 912 .vrefresh = 240, }, 913 /* 59 - 1440x480i@240 */ 914 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 915 1602, 1716, 0, 480, 488, 494, 525, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 917 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 918 .vrefresh = 240, }, 919 /* 60 - 1280x720@24Hz */ 920 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 921 3080, 3300, 0, 720, 725, 730, 750, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 24, }, 924 /* 61 - 1280x720@25Hz */ 925 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 926 3740, 3960, 0, 720, 725, 730, 750, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .vrefresh = 25, }, 929 /* 62 - 1280x720@30Hz */ 930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 931 3080, 3300, 0, 720, 725, 730, 750, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 30, }, 934 /* 63 - 1920x1080@120Hz */ 935 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 936 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 120, }, 939 /* 64 - 1920x1080@100Hz */ 940 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 941 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 100, }, 944 }; 945 946 /* 947 * HDMI 1.4 4k modes. 948 */ 949 static const struct drm_display_mode edid_4k_modes[] = { 950 /* 1 - 3840x2160@30Hz */ 951 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 952 3840, 4016, 4104, 4400, 0, 953 2160, 2168, 2178, 2250, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .vrefresh = 30, }, 956 /* 2 - 3840x2160@25Hz */ 957 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 958 3840, 4896, 4984, 5280, 0, 959 2160, 2168, 2178, 2250, 0, 960 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 961 .vrefresh = 25, }, 962 /* 3 - 3840x2160@24Hz */ 963 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 964 3840, 5116, 5204, 5500, 0, 965 2160, 2168, 2178, 2250, 0, 966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 967 .vrefresh = 24, }, 968 /* 4 - 4096x2160@24Hz (SMPTE) */ 969 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 970 4096, 5116, 5204, 5500, 0, 971 2160, 2168, 2178, 2250, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 973 .vrefresh = 24, }, 974 }; 975 976 /*** DDC fetch and block validation ***/ 977 978 static const u8 edid_header[] = { 979 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 980 }; 981 982 /* 983 * Sanity check the header of the base EDID block. Return 8 if the header 984 * is perfect, down to 0 if it's totally wrong. 985 */ 986 int drm_edid_header_is_valid(const u8 *raw_edid) 987 { 988 int i, score = 0; 989 990 for (i = 0; i < sizeof(edid_header); i++) 991 if (raw_edid[i] == edid_header[i]) 992 score++; 993 994 return score; 995 } 996 EXPORT_SYMBOL(drm_edid_header_is_valid); 997 998 static int edid_fixup __read_mostly = 6; 999 module_param_named(edid_fixup, edid_fixup, int, 0400); 1000 MODULE_PARM_DESC(edid_fixup, 1001 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1002 1003 /* 1004 * Sanity check the EDID block (base or extension). Return 0 if the block 1005 * doesn't check out, or 1 if it's valid. 1006 */ 1007 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) 1008 { 1009 int i; 1010 u8 csum = 0; 1011 struct edid *edid = (struct edid *)raw_edid; 1012 1013 if (WARN_ON(!raw_edid)) 1014 return false; 1015 1016 if (edid_fixup > 8 || edid_fixup < 0) 1017 edid_fixup = 6; 1018 1019 if (block == 0) { 1020 int score = drm_edid_header_is_valid(raw_edid); 1021 if (score == 8) ; 1022 else if (score >= edid_fixup) { 1023 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1024 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1025 } else { 1026 goto bad; 1027 } 1028 } 1029 1030 for (i = 0; i < EDID_LENGTH; i++) 1031 csum += raw_edid[i]; 1032 if (csum) { 1033 if (print_bad_edid) { 1034 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1035 } 1036 1037 /* allow CEA to slide through, switches mangle this */ 1038 if (raw_edid[0] != 0x02) 1039 goto bad; 1040 } 1041 1042 /* per-block-type checks */ 1043 switch (raw_edid[0]) { 1044 case 0: /* base */ 1045 if (edid->version != 1) { 1046 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1047 goto bad; 1048 } 1049 1050 if (edid->revision > 4) 1051 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1052 break; 1053 1054 default: 1055 break; 1056 } 1057 1058 return true; 1059 1060 bad: 1061 if (print_bad_edid) { 1062 printk(KERN_ERR "Raw EDID:\n"); 1063 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1064 raw_edid, EDID_LENGTH, false); 1065 } 1066 return false; 1067 } 1068 EXPORT_SYMBOL(drm_edid_block_valid); 1069 1070 /** 1071 * drm_edid_is_valid - sanity check EDID data 1072 * @edid: EDID data 1073 * 1074 * Sanity-check an entire EDID record (including extensions) 1075 */ 1076 bool drm_edid_is_valid(struct edid *edid) 1077 { 1078 int i; 1079 u8 *raw = (u8 *)edid; 1080 1081 if (!edid) 1082 return false; 1083 1084 for (i = 0; i <= edid->extensions; i++) 1085 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) 1086 return false; 1087 1088 return true; 1089 } 1090 EXPORT_SYMBOL(drm_edid_is_valid); 1091 1092 #define DDC_SEGMENT_ADDR 0x30 1093 /** 1094 * Get EDID information via I2C. 1095 * 1096 * \param adapter : i2c device adaptor 1097 * \param buf : EDID data buffer to be filled 1098 * \param len : EDID data buffer length 1099 * \return 0 on success or -1 on failure. 1100 * 1101 * Try to fetch EDID information by calling i2c driver function. 1102 */ 1103 static int 1104 drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, 1105 int block, int len) 1106 { 1107 unsigned char start = block * EDID_LENGTH; 1108 unsigned char segment = block >> 1; 1109 unsigned char xfers = segment ? 3 : 2; 1110 int ret, retries = 5; 1111 1112 /* The core i2c driver will automatically retry the transfer if the 1113 * adapter reports EAGAIN. However, we find that bit-banging transfers 1114 * are susceptible to errors under a heavily loaded machine and 1115 * generate spurious NAKs and timeouts. Retrying the transfer 1116 * of the individual block a few times seems to overcome this. 1117 */ 1118 do { 1119 struct i2c_msg msgs[] = { 1120 { 1121 .addr = DDC_SEGMENT_ADDR, 1122 .flags = 0, 1123 .len = 1, 1124 .buf = &segment, 1125 }, { 1126 .addr = DDC_ADDR, 1127 .flags = 0, 1128 .len = 1, 1129 .buf = &start, 1130 }, { 1131 .addr = DDC_ADDR, 1132 .flags = I2C_M_RD, 1133 .len = len, 1134 .buf = buf, 1135 } 1136 }; 1137 1138 /* 1139 * Avoid sending the segment addr to not upset non-compliant ddc 1140 * monitors. 1141 */ 1142 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1143 1144 if (ret == -ENXIO) { 1145 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1146 adapter->name); 1147 break; 1148 } 1149 } while (ret != xfers && --retries); 1150 1151 return ret == xfers ? 0 : -1; 1152 } 1153 1154 static bool drm_edid_is_zero(u8 *in_edid, int length) 1155 { 1156 if (memchr_inv(in_edid, 0, length)) 1157 return false; 1158 1159 return true; 1160 } 1161 1162 static u8 * 1163 drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 1164 { 1165 int i, j = 0, valid_extensions = 0; 1166 u8 *block, *new; 1167 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1168 1169 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1170 return NULL; 1171 1172 /* base block fetch */ 1173 for (i = 0; i < 4; i++) { 1174 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) 1175 goto out; 1176 if (drm_edid_block_valid(block, 0, print_bad_edid)) 1177 break; 1178 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1179 connector->null_edid_counter++; 1180 goto carp; 1181 } 1182 } 1183 if (i == 4) 1184 goto carp; 1185 1186 /* if there's no extensions, we're done */ 1187 if (block[0x7e] == 0) 1188 return block; 1189 1190 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1191 if (!new) 1192 goto out; 1193 block = new; 1194 1195 for (j = 1; j <= block[0x7e]; j++) { 1196 for (i = 0; i < 4; i++) { 1197 if (drm_do_probe_ddc_edid(adapter, 1198 block + (valid_extensions + 1) * EDID_LENGTH, 1199 j, EDID_LENGTH)) 1200 goto out; 1201 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { 1202 valid_extensions++; 1203 break; 1204 } 1205 } 1206 1207 if (i == 4 && print_bad_edid) { 1208 dev_warn(connector->dev->dev, 1209 "%s: Ignoring invalid EDID block %d.\n", 1210 drm_get_connector_name(connector), j); 1211 1212 connector->bad_edid_counter++; 1213 } 1214 } 1215 1216 if (valid_extensions != block[0x7e]) { 1217 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1218 block[0x7e] = valid_extensions; 1219 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1220 if (!new) 1221 goto out; 1222 block = new; 1223 } 1224 1225 return block; 1226 1227 carp: 1228 if (print_bad_edid) { 1229 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1230 drm_get_connector_name(connector), j); 1231 } 1232 connector->bad_edid_counter++; 1233 1234 out: 1235 kfree(block); 1236 return NULL; 1237 } 1238 1239 /** 1240 * Probe DDC presence. 1241 * 1242 * \param adapter : i2c device adaptor 1243 * \return 1 on success 1244 */ 1245 bool 1246 drm_probe_ddc(struct i2c_adapter *adapter) 1247 { 1248 unsigned char out; 1249 1250 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1251 } 1252 EXPORT_SYMBOL(drm_probe_ddc); 1253 1254 /** 1255 * drm_get_edid - get EDID data, if available 1256 * @connector: connector we're probing 1257 * @adapter: i2c adapter to use for DDC 1258 * 1259 * Poke the given i2c channel to grab EDID data if possible. If found, 1260 * attach it to the connector. 1261 * 1262 * Return edid data or NULL if we couldn't find any. 1263 */ 1264 struct edid *drm_get_edid(struct drm_connector *connector, 1265 struct i2c_adapter *adapter) 1266 { 1267 struct edid *edid = NULL; 1268 1269 if (drm_probe_ddc(adapter)) 1270 edid = (struct edid *)drm_do_get_edid(connector, adapter); 1271 1272 return edid; 1273 } 1274 EXPORT_SYMBOL(drm_get_edid); 1275 1276 /** 1277 * drm_edid_duplicate - duplicate an EDID and the extensions 1278 * @edid: EDID to duplicate 1279 * 1280 * Return duplicate edid or NULL on allocation failure. 1281 */ 1282 struct edid *drm_edid_duplicate(const struct edid *edid) 1283 { 1284 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1285 } 1286 EXPORT_SYMBOL(drm_edid_duplicate); 1287 1288 /*** EDID parsing ***/ 1289 1290 /** 1291 * edid_vendor - match a string against EDID's obfuscated vendor field 1292 * @edid: EDID to match 1293 * @vendor: vendor string 1294 * 1295 * Returns true if @vendor is in @edid, false otherwise 1296 */ 1297 static bool edid_vendor(struct edid *edid, char *vendor) 1298 { 1299 char edid_vendor[3]; 1300 1301 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1302 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1303 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1304 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1305 1306 return !strncmp(edid_vendor, vendor, 3); 1307 } 1308 1309 /** 1310 * edid_get_quirks - return quirk flags for a given EDID 1311 * @edid: EDID to process 1312 * 1313 * This tells subsequent routines what fixes they need to apply. 1314 */ 1315 static u32 edid_get_quirks(struct edid *edid) 1316 { 1317 struct edid_quirk *quirk; 1318 int i; 1319 1320 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1321 quirk = &edid_quirk_list[i]; 1322 1323 if (edid_vendor(edid, quirk->vendor) && 1324 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1325 return quirk->quirks; 1326 } 1327 1328 return 0; 1329 } 1330 1331 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1332 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1333 1334 /** 1335 * edid_fixup_preferred - set preferred modes based on quirk list 1336 * @connector: has mode list to fix up 1337 * @quirks: quirks list 1338 * 1339 * Walk the mode list for @connector, clearing the preferred status 1340 * on existing modes and setting it anew for the right mode ala @quirks. 1341 */ 1342 static void edid_fixup_preferred(struct drm_connector *connector, 1343 u32 quirks) 1344 { 1345 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1346 int target_refresh = 0; 1347 int cur_vrefresh, preferred_vrefresh; 1348 1349 if (list_empty(&connector->probed_modes)) 1350 return; 1351 1352 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1353 target_refresh = 60; 1354 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1355 target_refresh = 75; 1356 1357 preferred_mode = list_first_entry(&connector->probed_modes, 1358 struct drm_display_mode, head); 1359 1360 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1361 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1362 1363 if (cur_mode == preferred_mode) 1364 continue; 1365 1366 /* Largest mode is preferred */ 1367 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1368 preferred_mode = cur_mode; 1369 1370 cur_vrefresh = cur_mode->vrefresh ? 1371 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1372 preferred_vrefresh = preferred_mode->vrefresh ? 1373 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1374 /* At a given size, try to get closest to target refresh */ 1375 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1376 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1377 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1378 preferred_mode = cur_mode; 1379 } 1380 } 1381 1382 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1383 } 1384 1385 static bool 1386 mode_is_rb(const struct drm_display_mode *mode) 1387 { 1388 return (mode->htotal - mode->hdisplay == 160) && 1389 (mode->hsync_end - mode->hdisplay == 80) && 1390 (mode->hsync_end - mode->hsync_start == 32) && 1391 (mode->vsync_start - mode->vdisplay == 3); 1392 } 1393 1394 /* 1395 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1396 * @dev: Device to duplicate against 1397 * @hsize: Mode width 1398 * @vsize: Mode height 1399 * @fresh: Mode refresh rate 1400 * @rb: Mode reduced-blanking-ness 1401 * 1402 * Walk the DMT mode list looking for a match for the given parameters. 1403 * Return a newly allocated copy of the mode, or NULL if not found. 1404 */ 1405 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1406 int hsize, int vsize, int fresh, 1407 bool rb) 1408 { 1409 int i; 1410 1411 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1412 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1413 if (hsize != ptr->hdisplay) 1414 continue; 1415 if (vsize != ptr->vdisplay) 1416 continue; 1417 if (fresh != drm_mode_vrefresh(ptr)) 1418 continue; 1419 if (rb != mode_is_rb(ptr)) 1420 continue; 1421 1422 return drm_mode_duplicate(dev, ptr); 1423 } 1424 1425 return NULL; 1426 } 1427 EXPORT_SYMBOL(drm_mode_find_dmt); 1428 1429 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1430 1431 static void 1432 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1433 { 1434 int i, n = 0; 1435 u8 d = ext[0x02]; 1436 u8 *det_base = ext + d; 1437 1438 n = (127 - d) / 18; 1439 for (i = 0; i < n; i++) 1440 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1441 } 1442 1443 static void 1444 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1445 { 1446 unsigned int i, n = min((int)ext[0x02], 6); 1447 u8 *det_base = ext + 5; 1448 1449 if (ext[0x01] != 1) 1450 return; /* unknown version */ 1451 1452 for (i = 0; i < n; i++) 1453 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1454 } 1455 1456 static void 1457 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1458 { 1459 int i; 1460 struct edid *edid = (struct edid *)raw_edid; 1461 1462 if (edid == NULL) 1463 return; 1464 1465 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1466 cb(&(edid->detailed_timings[i]), closure); 1467 1468 for (i = 1; i <= raw_edid[0x7e]; i++) { 1469 u8 *ext = raw_edid + (i * EDID_LENGTH); 1470 switch (*ext) { 1471 case CEA_EXT: 1472 cea_for_each_detailed_block(ext, cb, closure); 1473 break; 1474 case VTB_EXT: 1475 vtb_for_each_detailed_block(ext, cb, closure); 1476 break; 1477 default: 1478 break; 1479 } 1480 } 1481 } 1482 1483 static void 1484 is_rb(struct detailed_timing *t, void *data) 1485 { 1486 u8 *r = (u8 *)t; 1487 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1488 if (r[15] & 0x10) 1489 *(bool *)data = true; 1490 } 1491 1492 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1493 static bool 1494 drm_monitor_supports_rb(struct edid *edid) 1495 { 1496 if (edid->revision >= 4) { 1497 bool ret = false; 1498 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1499 return ret; 1500 } 1501 1502 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1503 } 1504 1505 static void 1506 find_gtf2(struct detailed_timing *t, void *data) 1507 { 1508 u8 *r = (u8 *)t; 1509 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1510 *(u8 **)data = r; 1511 } 1512 1513 /* Secondary GTF curve kicks in above some break frequency */ 1514 static int 1515 drm_gtf2_hbreak(struct edid *edid) 1516 { 1517 u8 *r = NULL; 1518 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1519 return r ? (r[12] * 2) : 0; 1520 } 1521 1522 static int 1523 drm_gtf2_2c(struct edid *edid) 1524 { 1525 u8 *r = NULL; 1526 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1527 return r ? r[13] : 0; 1528 } 1529 1530 static int 1531 drm_gtf2_m(struct edid *edid) 1532 { 1533 u8 *r = NULL; 1534 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1535 return r ? (r[15] << 8) + r[14] : 0; 1536 } 1537 1538 static int 1539 drm_gtf2_k(struct edid *edid) 1540 { 1541 u8 *r = NULL; 1542 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1543 return r ? r[16] : 0; 1544 } 1545 1546 static int 1547 drm_gtf2_2j(struct edid *edid) 1548 { 1549 u8 *r = NULL; 1550 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1551 return r ? r[17] : 0; 1552 } 1553 1554 /** 1555 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1556 * @edid: EDID block to scan 1557 */ 1558 static int standard_timing_level(struct edid *edid) 1559 { 1560 if (edid->revision >= 2) { 1561 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1562 return LEVEL_CVT; 1563 if (drm_gtf2_hbreak(edid)) 1564 return LEVEL_GTF2; 1565 return LEVEL_GTF; 1566 } 1567 return LEVEL_DMT; 1568 } 1569 1570 /* 1571 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1572 * monitors fill with ascii space (0x20) instead. 1573 */ 1574 static int 1575 bad_std_timing(u8 a, u8 b) 1576 { 1577 return (a == 0x00 && b == 0x00) || 1578 (a == 0x01 && b == 0x01) || 1579 (a == 0x20 && b == 0x20); 1580 } 1581 1582 /** 1583 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1584 * @t: standard timing params 1585 * @timing_level: standard timing level 1586 * 1587 * Take the standard timing params (in this case width, aspect, and refresh) 1588 * and convert them into a real mode using CVT/GTF/DMT. 1589 */ 1590 static struct drm_display_mode * 1591 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1592 struct std_timing *t, int revision) 1593 { 1594 struct drm_device *dev = connector->dev; 1595 struct drm_display_mode *m, *mode = NULL; 1596 int hsize, vsize; 1597 int vrefresh_rate; 1598 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1599 >> EDID_TIMING_ASPECT_SHIFT; 1600 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1601 >> EDID_TIMING_VFREQ_SHIFT; 1602 int timing_level = standard_timing_level(edid); 1603 1604 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1605 return NULL; 1606 1607 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1608 hsize = t->hsize * 8 + 248; 1609 /* vrefresh_rate = vfreq + 60 */ 1610 vrefresh_rate = vfreq + 60; 1611 /* the vdisplay is calculated based on the aspect ratio */ 1612 if (aspect_ratio == 0) { 1613 if (revision < 3) 1614 vsize = hsize; 1615 else 1616 vsize = (hsize * 10) / 16; 1617 } else if (aspect_ratio == 1) 1618 vsize = (hsize * 3) / 4; 1619 else if (aspect_ratio == 2) 1620 vsize = (hsize * 4) / 5; 1621 else 1622 vsize = (hsize * 9) / 16; 1623 1624 /* HDTV hack, part 1 */ 1625 if (vrefresh_rate == 60 && 1626 ((hsize == 1360 && vsize == 765) || 1627 (hsize == 1368 && vsize == 769))) { 1628 hsize = 1366; 1629 vsize = 768; 1630 } 1631 1632 /* 1633 * If this connector already has a mode for this size and refresh 1634 * rate (because it came from detailed or CVT info), use that 1635 * instead. This way we don't have to guess at interlace or 1636 * reduced blanking. 1637 */ 1638 list_for_each_entry(m, &connector->probed_modes, head) 1639 if (m->hdisplay == hsize && m->vdisplay == vsize && 1640 drm_mode_vrefresh(m) == vrefresh_rate) 1641 return NULL; 1642 1643 /* HDTV hack, part 2 */ 1644 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1645 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1646 false); 1647 mode->hdisplay = 1366; 1648 mode->hsync_start = mode->hsync_start - 1; 1649 mode->hsync_end = mode->hsync_end - 1; 1650 return mode; 1651 } 1652 1653 /* check whether it can be found in default mode table */ 1654 if (drm_monitor_supports_rb(edid)) { 1655 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1656 true); 1657 if (mode) 1658 return mode; 1659 } 1660 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1661 if (mode) 1662 return mode; 1663 1664 /* okay, generate it */ 1665 switch (timing_level) { 1666 case LEVEL_DMT: 1667 break; 1668 case LEVEL_GTF: 1669 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1670 break; 1671 case LEVEL_GTF2: 1672 /* 1673 * This is potentially wrong if there's ever a monitor with 1674 * more than one ranges section, each claiming a different 1675 * secondary GTF curve. Please don't do that. 1676 */ 1677 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1678 if (!mode) 1679 return NULL; 1680 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1681 drm_mode_destroy(dev, mode); 1682 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1683 vrefresh_rate, 0, 0, 1684 drm_gtf2_m(edid), 1685 drm_gtf2_2c(edid), 1686 drm_gtf2_k(edid), 1687 drm_gtf2_2j(edid)); 1688 } 1689 break; 1690 case LEVEL_CVT: 1691 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1692 false); 1693 break; 1694 } 1695 return mode; 1696 } 1697 1698 /* 1699 * EDID is delightfully ambiguous about how interlaced modes are to be 1700 * encoded. Our internal representation is of frame height, but some 1701 * HDTV detailed timings are encoded as field height. 1702 * 1703 * The format list here is from CEA, in frame size. Technically we 1704 * should be checking refresh rate too. Whatever. 1705 */ 1706 static void 1707 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1708 struct detailed_pixel_timing *pt) 1709 { 1710 int i; 1711 static const struct { 1712 int w, h; 1713 } cea_interlaced[] = { 1714 { 1920, 1080 }, 1715 { 720, 480 }, 1716 { 1440, 480 }, 1717 { 2880, 480 }, 1718 { 720, 576 }, 1719 { 1440, 576 }, 1720 { 2880, 576 }, 1721 }; 1722 1723 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1724 return; 1725 1726 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1727 if ((mode->hdisplay == cea_interlaced[i].w) && 1728 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1729 mode->vdisplay *= 2; 1730 mode->vsync_start *= 2; 1731 mode->vsync_end *= 2; 1732 mode->vtotal *= 2; 1733 mode->vtotal |= 1; 1734 } 1735 } 1736 1737 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1738 } 1739 1740 /** 1741 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1742 * @dev: DRM device (needed to create new mode) 1743 * @edid: EDID block 1744 * @timing: EDID detailed timing info 1745 * @quirks: quirks to apply 1746 * 1747 * An EDID detailed timing block contains enough info for us to create and 1748 * return a new struct drm_display_mode. 1749 */ 1750 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1751 struct edid *edid, 1752 struct detailed_timing *timing, 1753 u32 quirks) 1754 { 1755 struct drm_display_mode *mode; 1756 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1757 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1758 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1759 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1760 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1761 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1762 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1763 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1764 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1765 1766 /* ignore tiny modes */ 1767 if (hactive < 64 || vactive < 64) 1768 return NULL; 1769 1770 if (pt->misc & DRM_EDID_PT_STEREO) { 1771 DRM_DEBUG_KMS("stereo mode not supported\n"); 1772 return NULL; 1773 } 1774 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1775 DRM_DEBUG_KMS("composite sync not supported\n"); 1776 } 1777 1778 /* it is incorrect if hsync/vsync width is zero */ 1779 if (!hsync_pulse_width || !vsync_pulse_width) { 1780 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1781 "Wrong Hsync/Vsync pulse width\n"); 1782 return NULL; 1783 } 1784 1785 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1786 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1787 if (!mode) 1788 return NULL; 1789 1790 goto set_size; 1791 } 1792 1793 mode = drm_mode_create(dev); 1794 if (!mode) 1795 return NULL; 1796 1797 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1798 timing->pixel_clock = cpu_to_le16(1088); 1799 1800 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1801 1802 mode->hdisplay = hactive; 1803 mode->hsync_start = mode->hdisplay + hsync_offset; 1804 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1805 mode->htotal = mode->hdisplay + hblank; 1806 1807 mode->vdisplay = vactive; 1808 mode->vsync_start = mode->vdisplay + vsync_offset; 1809 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1810 mode->vtotal = mode->vdisplay + vblank; 1811 1812 /* Some EDIDs have bogus h/vtotal values */ 1813 if (mode->hsync_end > mode->htotal) 1814 mode->htotal = mode->hsync_end + 1; 1815 if (mode->vsync_end > mode->vtotal) 1816 mode->vtotal = mode->vsync_end + 1; 1817 1818 drm_mode_do_interlace_quirk(mode, pt); 1819 1820 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1821 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1822 } 1823 1824 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1825 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1826 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1827 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1828 1829 set_size: 1830 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1831 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1832 1833 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1834 mode->width_mm *= 10; 1835 mode->height_mm *= 10; 1836 } 1837 1838 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1839 mode->width_mm = edid->width_cm * 10; 1840 mode->height_mm = edid->height_cm * 10; 1841 } 1842 1843 mode->type = DRM_MODE_TYPE_DRIVER; 1844 mode->vrefresh = drm_mode_vrefresh(mode); 1845 drm_mode_set_name(mode); 1846 1847 return mode; 1848 } 1849 1850 static bool 1851 mode_in_hsync_range(const struct drm_display_mode *mode, 1852 struct edid *edid, u8 *t) 1853 { 1854 int hsync, hmin, hmax; 1855 1856 hmin = t[7]; 1857 if (edid->revision >= 4) 1858 hmin += ((t[4] & 0x04) ? 255 : 0); 1859 hmax = t[8]; 1860 if (edid->revision >= 4) 1861 hmax += ((t[4] & 0x08) ? 255 : 0); 1862 hsync = drm_mode_hsync(mode); 1863 1864 return (hsync <= hmax && hsync >= hmin); 1865 } 1866 1867 static bool 1868 mode_in_vsync_range(const struct drm_display_mode *mode, 1869 struct edid *edid, u8 *t) 1870 { 1871 int vsync, vmin, vmax; 1872 1873 vmin = t[5]; 1874 if (edid->revision >= 4) 1875 vmin += ((t[4] & 0x01) ? 255 : 0); 1876 vmax = t[6]; 1877 if (edid->revision >= 4) 1878 vmax += ((t[4] & 0x02) ? 255 : 0); 1879 vsync = drm_mode_vrefresh(mode); 1880 1881 return (vsync <= vmax && vsync >= vmin); 1882 } 1883 1884 static u32 1885 range_pixel_clock(struct edid *edid, u8 *t) 1886 { 1887 /* unspecified */ 1888 if (t[9] == 0 || t[9] == 255) 1889 return 0; 1890 1891 /* 1.4 with CVT support gives us real precision, yay */ 1892 if (edid->revision >= 4 && t[10] == 0x04) 1893 return (t[9] * 10000) - ((t[12] >> 2) * 250); 1894 1895 /* 1.3 is pathetic, so fuzz up a bit */ 1896 return t[9] * 10000 + 5001; 1897 } 1898 1899 static bool 1900 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 1901 struct detailed_timing *timing) 1902 { 1903 u32 max_clock; 1904 u8 *t = (u8 *)timing; 1905 1906 if (!mode_in_hsync_range(mode, edid, t)) 1907 return false; 1908 1909 if (!mode_in_vsync_range(mode, edid, t)) 1910 return false; 1911 1912 if ((max_clock = range_pixel_clock(edid, t))) 1913 if (mode->clock > max_clock) 1914 return false; 1915 1916 /* 1.4 max horizontal check */ 1917 if (edid->revision >= 4 && t[10] == 0x04) 1918 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 1919 return false; 1920 1921 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 1922 return false; 1923 1924 return true; 1925 } 1926 1927 static bool valid_inferred_mode(const struct drm_connector *connector, 1928 const struct drm_display_mode *mode) 1929 { 1930 struct drm_display_mode *m; 1931 bool ok = false; 1932 1933 list_for_each_entry(m, &connector->probed_modes, head) { 1934 if (mode->hdisplay == m->hdisplay && 1935 mode->vdisplay == m->vdisplay && 1936 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 1937 return false; /* duplicated */ 1938 if (mode->hdisplay <= m->hdisplay && 1939 mode->vdisplay <= m->vdisplay) 1940 ok = true; 1941 } 1942 return ok; 1943 } 1944 1945 static int 1946 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1947 struct detailed_timing *timing) 1948 { 1949 int i, modes = 0; 1950 struct drm_display_mode *newmode; 1951 struct drm_device *dev = connector->dev; 1952 1953 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1954 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 1955 valid_inferred_mode(connector, drm_dmt_modes + i)) { 1956 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 1957 if (newmode) { 1958 drm_mode_probed_add(connector, newmode); 1959 modes++; 1960 } 1961 } 1962 } 1963 1964 return modes; 1965 } 1966 1967 /* fix up 1366x768 mode from 1368x768; 1968 * GFT/CVT can't express 1366 width which isn't dividable by 8 1969 */ 1970 static void fixup_mode_1366x768(struct drm_display_mode *mode) 1971 { 1972 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 1973 mode->hdisplay = 1366; 1974 mode->hsync_start--; 1975 mode->hsync_end--; 1976 drm_mode_set_name(mode); 1977 } 1978 } 1979 1980 static int 1981 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 1982 struct detailed_timing *timing) 1983 { 1984 int i, modes = 0; 1985 struct drm_display_mode *newmode; 1986 struct drm_device *dev = connector->dev; 1987 1988 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 1989 const struct minimode *m = &extra_modes[i]; 1990 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 1991 if (!newmode) 1992 return modes; 1993 1994 fixup_mode_1366x768(newmode); 1995 if (!mode_in_range(newmode, edid, timing) || 1996 !valid_inferred_mode(connector, newmode)) { 1997 drm_mode_destroy(dev, newmode); 1998 continue; 1999 } 2000 2001 drm_mode_probed_add(connector, newmode); 2002 modes++; 2003 } 2004 2005 return modes; 2006 } 2007 2008 static int 2009 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2010 struct detailed_timing *timing) 2011 { 2012 int i, modes = 0; 2013 struct drm_display_mode *newmode; 2014 struct drm_device *dev = connector->dev; 2015 bool rb = drm_monitor_supports_rb(edid); 2016 2017 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2018 const struct minimode *m = &extra_modes[i]; 2019 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2020 if (!newmode) 2021 return modes; 2022 2023 fixup_mode_1366x768(newmode); 2024 if (!mode_in_range(newmode, edid, timing) || 2025 !valid_inferred_mode(connector, newmode)) { 2026 drm_mode_destroy(dev, newmode); 2027 continue; 2028 } 2029 2030 drm_mode_probed_add(connector, newmode); 2031 modes++; 2032 } 2033 2034 return modes; 2035 } 2036 2037 static void 2038 do_inferred_modes(struct detailed_timing *timing, void *c) 2039 { 2040 struct detailed_mode_closure *closure = c; 2041 struct detailed_non_pixel *data = &timing->data.other_data; 2042 struct detailed_data_monitor_range *range = &data->data.range; 2043 2044 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2045 return; 2046 2047 closure->modes += drm_dmt_modes_for_range(closure->connector, 2048 closure->edid, 2049 timing); 2050 2051 if (!version_greater(closure->edid, 1, 1)) 2052 return; /* GTF not defined yet */ 2053 2054 switch (range->flags) { 2055 case 0x02: /* secondary gtf, XXX could do more */ 2056 case 0x00: /* default gtf */ 2057 closure->modes += drm_gtf_modes_for_range(closure->connector, 2058 closure->edid, 2059 timing); 2060 break; 2061 case 0x04: /* cvt, only in 1.4+ */ 2062 if (!version_greater(closure->edid, 1, 3)) 2063 break; 2064 2065 closure->modes += drm_cvt_modes_for_range(closure->connector, 2066 closure->edid, 2067 timing); 2068 break; 2069 case 0x01: /* just the ranges, no formula */ 2070 default: 2071 break; 2072 } 2073 } 2074 2075 static int 2076 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2077 { 2078 struct detailed_mode_closure closure = { 2079 connector, edid, 0, 0, 0 2080 }; 2081 2082 if (version_greater(edid, 1, 0)) 2083 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2084 &closure); 2085 2086 return closure.modes; 2087 } 2088 2089 static int 2090 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2091 { 2092 int i, j, m, modes = 0; 2093 struct drm_display_mode *mode; 2094 u8 *est = ((u8 *)timing) + 5; 2095 2096 for (i = 0; i < 6; i++) { 2097 for (j = 7; j >= 0; j--) { 2098 m = (i * 8) + (7 - j); 2099 if (m >= ARRAY_SIZE(est3_modes)) 2100 break; 2101 if (est[i] & (1 << j)) { 2102 mode = drm_mode_find_dmt(connector->dev, 2103 est3_modes[m].w, 2104 est3_modes[m].h, 2105 est3_modes[m].r, 2106 est3_modes[m].rb); 2107 if (mode) { 2108 drm_mode_probed_add(connector, mode); 2109 modes++; 2110 } 2111 } 2112 } 2113 } 2114 2115 return modes; 2116 } 2117 2118 static void 2119 do_established_modes(struct detailed_timing *timing, void *c) 2120 { 2121 struct detailed_mode_closure *closure = c; 2122 struct detailed_non_pixel *data = &timing->data.other_data; 2123 2124 if (data->type == EDID_DETAIL_EST_TIMINGS) 2125 closure->modes += drm_est3_modes(closure->connector, timing); 2126 } 2127 2128 /** 2129 * add_established_modes - get est. modes from EDID and add them 2130 * @edid: EDID block to scan 2131 * 2132 * Each EDID block contains a bitmap of the supported "established modes" list 2133 * (defined above). Tease them out and add them to the global modes list. 2134 */ 2135 static int 2136 add_established_modes(struct drm_connector *connector, struct edid *edid) 2137 { 2138 struct drm_device *dev = connector->dev; 2139 unsigned long est_bits = edid->established_timings.t1 | 2140 (edid->established_timings.t2 << 8) | 2141 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2142 int i, modes = 0; 2143 struct detailed_mode_closure closure = { 2144 connector, edid, 0, 0, 0 2145 }; 2146 2147 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2148 if (est_bits & (1<<i)) { 2149 struct drm_display_mode *newmode; 2150 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2151 if (newmode) { 2152 drm_mode_probed_add(connector, newmode); 2153 modes++; 2154 } 2155 } 2156 } 2157 2158 if (version_greater(edid, 1, 0)) 2159 drm_for_each_detailed_block((u8 *)edid, 2160 do_established_modes, &closure); 2161 2162 return modes + closure.modes; 2163 } 2164 2165 static void 2166 do_standard_modes(struct detailed_timing *timing, void *c) 2167 { 2168 struct detailed_mode_closure *closure = c; 2169 struct detailed_non_pixel *data = &timing->data.other_data; 2170 struct drm_connector *connector = closure->connector; 2171 struct edid *edid = closure->edid; 2172 2173 if (data->type == EDID_DETAIL_STD_MODES) { 2174 int i; 2175 for (i = 0; i < 6; i++) { 2176 struct std_timing *std; 2177 struct drm_display_mode *newmode; 2178 2179 std = &data->data.timings[i]; 2180 newmode = drm_mode_std(connector, edid, std, 2181 edid->revision); 2182 if (newmode) { 2183 drm_mode_probed_add(connector, newmode); 2184 closure->modes++; 2185 } 2186 } 2187 } 2188 } 2189 2190 /** 2191 * add_standard_modes - get std. modes from EDID and add them 2192 * @edid: EDID block to scan 2193 * 2194 * Standard modes can be calculated using the appropriate standard (DMT, 2195 * GTF or CVT. Grab them from @edid and add them to the list. 2196 */ 2197 static int 2198 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2199 { 2200 int i, modes = 0; 2201 struct detailed_mode_closure closure = { 2202 connector, edid, 0, 0, 0 2203 }; 2204 2205 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2206 struct drm_display_mode *newmode; 2207 2208 newmode = drm_mode_std(connector, edid, 2209 &edid->standard_timings[i], 2210 edid->revision); 2211 if (newmode) { 2212 drm_mode_probed_add(connector, newmode); 2213 modes++; 2214 } 2215 } 2216 2217 if (version_greater(edid, 1, 0)) 2218 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2219 &closure); 2220 2221 /* XXX should also look for standard codes in VTB blocks */ 2222 2223 return modes + closure.modes; 2224 } 2225 2226 static int drm_cvt_modes(struct drm_connector *connector, 2227 struct detailed_timing *timing) 2228 { 2229 int i, j, modes = 0; 2230 struct drm_display_mode *newmode; 2231 struct drm_device *dev = connector->dev; 2232 struct cvt_timing *cvt; 2233 const int rates[] = { 60, 85, 75, 60, 50 }; 2234 const u8 empty[3] = { 0, 0, 0 }; 2235 2236 for (i = 0; i < 4; i++) { 2237 int uninitialized_var(width), height; 2238 cvt = &(timing->data.other_data.data.cvt[i]); 2239 2240 if (!memcmp(cvt->code, empty, 3)) 2241 continue; 2242 2243 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2244 switch (cvt->code[1] & 0x0c) { 2245 case 0x00: 2246 width = height * 4 / 3; 2247 break; 2248 case 0x04: 2249 width = height * 16 / 9; 2250 break; 2251 case 0x08: 2252 width = height * 16 / 10; 2253 break; 2254 case 0x0c: 2255 width = height * 15 / 9; 2256 break; 2257 } 2258 2259 for (j = 1; j < 5; j++) { 2260 if (cvt->code[2] & (1 << j)) { 2261 newmode = drm_cvt_mode(dev, width, height, 2262 rates[j], j == 0, 2263 false, false); 2264 if (newmode) { 2265 drm_mode_probed_add(connector, newmode); 2266 modes++; 2267 } 2268 } 2269 } 2270 } 2271 2272 return modes; 2273 } 2274 2275 static void 2276 do_cvt_mode(struct detailed_timing *timing, void *c) 2277 { 2278 struct detailed_mode_closure *closure = c; 2279 struct detailed_non_pixel *data = &timing->data.other_data; 2280 2281 if (data->type == EDID_DETAIL_CVT_3BYTE) 2282 closure->modes += drm_cvt_modes(closure->connector, timing); 2283 } 2284 2285 static int 2286 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2287 { 2288 struct detailed_mode_closure closure = { 2289 connector, edid, 0, 0, 0 2290 }; 2291 2292 if (version_greater(edid, 1, 2)) 2293 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2294 2295 /* XXX should also look for CVT codes in VTB blocks */ 2296 2297 return closure.modes; 2298 } 2299 2300 static void 2301 do_detailed_mode(struct detailed_timing *timing, void *c) 2302 { 2303 struct detailed_mode_closure *closure = c; 2304 struct drm_display_mode *newmode; 2305 2306 if (timing->pixel_clock) { 2307 newmode = drm_mode_detailed(closure->connector->dev, 2308 closure->edid, timing, 2309 closure->quirks); 2310 if (!newmode) 2311 return; 2312 2313 if (closure->preferred) 2314 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2315 2316 drm_mode_probed_add(closure->connector, newmode); 2317 closure->modes++; 2318 closure->preferred = 0; 2319 } 2320 } 2321 2322 /* 2323 * add_detailed_modes - Add modes from detailed timings 2324 * @connector: attached connector 2325 * @edid: EDID block to scan 2326 * @quirks: quirks to apply 2327 */ 2328 static int 2329 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2330 u32 quirks) 2331 { 2332 struct detailed_mode_closure closure = { 2333 connector, 2334 edid, 2335 1, 2336 quirks, 2337 0 2338 }; 2339 2340 if (closure.preferred && !version_greater(edid, 1, 3)) 2341 closure.preferred = 2342 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2343 2344 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2345 2346 return closure.modes; 2347 } 2348 2349 #define AUDIO_BLOCK 0x01 2350 #define VIDEO_BLOCK 0x02 2351 #define VENDOR_BLOCK 0x03 2352 #define SPEAKER_BLOCK 0x04 2353 #define VIDEO_CAPABILITY_BLOCK 0x07 2354 #define EDID_BASIC_AUDIO (1 << 6) 2355 #define EDID_CEA_YCRCB444 (1 << 5) 2356 #define EDID_CEA_YCRCB422 (1 << 4) 2357 #define EDID_CEA_VCDB_QS (1 << 6) 2358 2359 /* 2360 * Search EDID for CEA extension block. 2361 */ 2362 static u8 *drm_find_cea_extension(struct edid *edid) 2363 { 2364 u8 *edid_ext = NULL; 2365 int i; 2366 2367 /* No EDID or EDID extensions */ 2368 if (edid == NULL || edid->extensions == 0) 2369 return NULL; 2370 2371 /* Find CEA extension */ 2372 for (i = 0; i < edid->extensions; i++) { 2373 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2374 if (edid_ext[0] == CEA_EXT) 2375 break; 2376 } 2377 2378 if (i == edid->extensions) 2379 return NULL; 2380 2381 return edid_ext; 2382 } 2383 2384 /* 2385 * Calculate the alternate clock for the CEA mode 2386 * (60Hz vs. 59.94Hz etc.) 2387 */ 2388 static unsigned int 2389 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2390 { 2391 unsigned int clock = cea_mode->clock; 2392 2393 if (cea_mode->vrefresh % 6 != 0) 2394 return clock; 2395 2396 /* 2397 * edid_cea_modes contains the 59.94Hz 2398 * variant for 240 and 480 line modes, 2399 * and the 60Hz variant otherwise. 2400 */ 2401 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2402 clock = clock * 1001 / 1000; 2403 else 2404 clock = DIV_ROUND_UP(clock * 1000, 1001); 2405 2406 return clock; 2407 } 2408 2409 /** 2410 * drm_match_cea_mode - look for a CEA mode matching given mode 2411 * @to_match: display mode 2412 * 2413 * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2414 * mode. 2415 */ 2416 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2417 { 2418 u8 mode; 2419 2420 if (!to_match->clock) 2421 return 0; 2422 2423 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2424 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2425 unsigned int clock1, clock2; 2426 2427 /* Check both 60Hz and 59.94Hz */ 2428 clock1 = cea_mode->clock; 2429 clock2 = cea_mode_alternate_clock(cea_mode); 2430 2431 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2432 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2433 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2434 return mode + 1; 2435 } 2436 return 0; 2437 } 2438 EXPORT_SYMBOL(drm_match_cea_mode); 2439 2440 /* 2441 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2442 * specific block). 2443 * 2444 * It's almost like cea_mode_alternate_clock(), we just need to add an 2445 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2446 * one. 2447 */ 2448 static unsigned int 2449 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2450 { 2451 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2452 return hdmi_mode->clock; 2453 2454 return cea_mode_alternate_clock(hdmi_mode); 2455 } 2456 2457 /* 2458 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2459 * @to_match: display mode 2460 * 2461 * An HDMI mode is one defined in the HDMI vendor specific block. 2462 * 2463 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2464 */ 2465 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2466 { 2467 u8 mode; 2468 2469 if (!to_match->clock) 2470 return 0; 2471 2472 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2473 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2474 unsigned int clock1, clock2; 2475 2476 /* Make sure to also match alternate clocks */ 2477 clock1 = hdmi_mode->clock; 2478 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2479 2480 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2481 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2482 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2483 return mode + 1; 2484 } 2485 return 0; 2486 } 2487 2488 static int 2489 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2490 { 2491 struct drm_device *dev = connector->dev; 2492 struct drm_display_mode *mode, *tmp; 2493 LIST_HEAD(list); 2494 int modes = 0; 2495 2496 /* Don't add CEA modes if the CEA extension block is missing */ 2497 if (!drm_find_cea_extension(edid)) 2498 return 0; 2499 2500 /* 2501 * Go through all probed modes and create a new mode 2502 * with the alternate clock for certain CEA modes. 2503 */ 2504 list_for_each_entry(mode, &connector->probed_modes, head) { 2505 const struct drm_display_mode *cea_mode = NULL; 2506 struct drm_display_mode *newmode; 2507 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2508 unsigned int clock1, clock2; 2509 2510 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2511 cea_mode = &edid_cea_modes[mode_idx]; 2512 clock2 = cea_mode_alternate_clock(cea_mode); 2513 } else { 2514 mode_idx = drm_match_hdmi_mode(mode) - 1; 2515 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2516 cea_mode = &edid_4k_modes[mode_idx]; 2517 clock2 = hdmi_mode_alternate_clock(cea_mode); 2518 } 2519 } 2520 2521 if (!cea_mode) 2522 continue; 2523 2524 clock1 = cea_mode->clock; 2525 2526 if (clock1 == clock2) 2527 continue; 2528 2529 if (mode->clock != clock1 && mode->clock != clock2) 2530 continue; 2531 2532 newmode = drm_mode_duplicate(dev, cea_mode); 2533 if (!newmode) 2534 continue; 2535 2536 /* Carry over the stereo flags */ 2537 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2538 2539 /* 2540 * The current mode could be either variant. Make 2541 * sure to pick the "other" clock for the new mode. 2542 */ 2543 if (mode->clock != clock1) 2544 newmode->clock = clock1; 2545 else 2546 newmode->clock = clock2; 2547 2548 list_add_tail(&newmode->head, &list); 2549 } 2550 2551 list_for_each_entry_safe(mode, tmp, &list, head) { 2552 list_del(&mode->head); 2553 drm_mode_probed_add(connector, mode); 2554 modes++; 2555 } 2556 2557 return modes; 2558 } 2559 2560 static int 2561 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2562 { 2563 struct drm_device *dev = connector->dev; 2564 const u8 *mode; 2565 u8 cea_mode; 2566 int modes = 0; 2567 2568 for (mode = db; mode < db + len; mode++) { 2569 cea_mode = (*mode & 127) - 1; /* CEA modes are numbered 1..127 */ 2570 if (cea_mode < ARRAY_SIZE(edid_cea_modes)) { 2571 struct drm_display_mode *newmode; 2572 newmode = drm_mode_duplicate(dev, 2573 &edid_cea_modes[cea_mode]); 2574 if (newmode) { 2575 newmode->vrefresh = 0; 2576 drm_mode_probed_add(connector, newmode); 2577 modes++; 2578 } 2579 } 2580 } 2581 2582 return modes; 2583 } 2584 2585 struct stereo_mandatory_mode { 2586 int width, height, vrefresh; 2587 unsigned int flags; 2588 }; 2589 2590 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2591 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2592 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2593 { 1920, 1080, 50, 2594 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2595 { 1920, 1080, 60, 2596 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2597 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2598 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2599 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2600 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2601 }; 2602 2603 static bool 2604 stereo_match_mandatory(const struct drm_display_mode *mode, 2605 const struct stereo_mandatory_mode *stereo_mode) 2606 { 2607 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2608 2609 return mode->hdisplay == stereo_mode->width && 2610 mode->vdisplay == stereo_mode->height && 2611 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2612 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2613 } 2614 2615 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2616 { 2617 struct drm_device *dev = connector->dev; 2618 const struct drm_display_mode *mode; 2619 struct list_head stereo_modes; 2620 int modes = 0, i; 2621 2622 INIT_LIST_HEAD(&stereo_modes); 2623 2624 list_for_each_entry(mode, &connector->probed_modes, head) { 2625 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2626 const struct stereo_mandatory_mode *mandatory; 2627 struct drm_display_mode *new_mode; 2628 2629 if (!stereo_match_mandatory(mode, 2630 &stereo_mandatory_modes[i])) 2631 continue; 2632 2633 mandatory = &stereo_mandatory_modes[i]; 2634 new_mode = drm_mode_duplicate(dev, mode); 2635 if (!new_mode) 2636 continue; 2637 2638 new_mode->flags |= mandatory->flags; 2639 list_add_tail(&new_mode->head, &stereo_modes); 2640 modes++; 2641 } 2642 } 2643 2644 list_splice_tail(&stereo_modes, &connector->probed_modes); 2645 2646 return modes; 2647 } 2648 2649 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2650 { 2651 struct drm_device *dev = connector->dev; 2652 struct drm_display_mode *newmode; 2653 2654 vic--; /* VICs start at 1 */ 2655 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2656 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2657 return 0; 2658 } 2659 2660 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2661 if (!newmode) 2662 return 0; 2663 2664 drm_mode_probed_add(connector, newmode); 2665 2666 return 1; 2667 } 2668 2669 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2670 const u8 *video_db, u8 video_len, u8 video_index) 2671 { 2672 struct drm_device *dev = connector->dev; 2673 struct drm_display_mode *newmode; 2674 int modes = 0; 2675 u8 cea_mode; 2676 2677 if (video_db == NULL || video_index >= video_len) 2678 return 0; 2679 2680 /* CEA modes are numbered 1..127 */ 2681 cea_mode = (video_db[video_index] & 127) - 1; 2682 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2683 return 0; 2684 2685 if (structure & (1 << 0)) { 2686 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2687 if (newmode) { 2688 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2689 drm_mode_probed_add(connector, newmode); 2690 modes++; 2691 } 2692 } 2693 if (structure & (1 << 6)) { 2694 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2695 if (newmode) { 2696 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2697 drm_mode_probed_add(connector, newmode); 2698 modes++; 2699 } 2700 } 2701 if (structure & (1 << 8)) { 2702 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2703 if (newmode) { 2704 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2705 drm_mode_probed_add(connector, newmode); 2706 modes++; 2707 } 2708 } 2709 2710 return modes; 2711 } 2712 2713 /* 2714 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2715 * @connector: connector corresponding to the HDMI sink 2716 * @db: start of the CEA vendor specific block 2717 * @len: length of the CEA block payload, ie. one can access up to db[len] 2718 * 2719 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2720 * also adds the stereo 3d modes when applicable. 2721 */ 2722 static int 2723 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2724 const u8 *video_db, u8 video_len) 2725 { 2726 int modes = 0, offset = 0, i, multi_present = 0; 2727 u8 vic_len, hdmi_3d_len = 0; 2728 u16 mask; 2729 u16 structure_all; 2730 2731 if (len < 8) 2732 goto out; 2733 2734 /* no HDMI_Video_Present */ 2735 if (!(db[8] & (1 << 5))) 2736 goto out; 2737 2738 /* Latency_Fields_Present */ 2739 if (db[8] & (1 << 7)) 2740 offset += 2; 2741 2742 /* I_Latency_Fields_Present */ 2743 if (db[8] & (1 << 6)) 2744 offset += 2; 2745 2746 /* the declared length is not long enough for the 2 first bytes 2747 * of additional video format capabilities */ 2748 if (len < (8 + offset + 2)) 2749 goto out; 2750 2751 /* 3D_Present */ 2752 offset++; 2753 if (db[8 + offset] & (1 << 7)) { 2754 modes += add_hdmi_mandatory_stereo_modes(connector); 2755 2756 /* 3D_Multi_present */ 2757 multi_present = (db[8 + offset] & 0x60) >> 5; 2758 } 2759 2760 offset++; 2761 vic_len = db[8 + offset] >> 5; 2762 hdmi_3d_len = db[8 + offset] & 0x1f; 2763 2764 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2765 u8 vic; 2766 2767 vic = db[9 + offset + i]; 2768 modes += add_hdmi_mode(connector, vic); 2769 } 2770 offset += 1 + vic_len; 2771 2772 if (!(multi_present == 1 || multi_present == 2)) 2773 goto out; 2774 2775 if ((multi_present == 1 && len < (9 + offset)) || 2776 (multi_present == 2 && len < (11 + offset))) 2777 goto out; 2778 2779 if ((multi_present == 1 && hdmi_3d_len < 2) || 2780 (multi_present == 2 && hdmi_3d_len < 4)) 2781 goto out; 2782 2783 /* 3D_Structure_ALL */ 2784 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2785 2786 /* check if 3D_MASK is present */ 2787 if (multi_present == 2) 2788 mask = (db[10 + offset] << 8) | db[11 + offset]; 2789 else 2790 mask = 0xffff; 2791 2792 for (i = 0; i < 16; i++) { 2793 if (mask & (1 << i)) 2794 modes += add_3d_struct_modes(connector, 2795 structure_all, 2796 video_db, 2797 video_len, i); 2798 } 2799 2800 out: 2801 return modes; 2802 } 2803 2804 static int 2805 cea_db_payload_len(const u8 *db) 2806 { 2807 return db[0] & 0x1f; 2808 } 2809 2810 static int 2811 cea_db_tag(const u8 *db) 2812 { 2813 return db[0] >> 5; 2814 } 2815 2816 static int 2817 cea_revision(const u8 *cea) 2818 { 2819 return cea[1]; 2820 } 2821 2822 static int 2823 cea_db_offsets(const u8 *cea, int *start, int *end) 2824 { 2825 /* Data block offset in CEA extension block */ 2826 *start = 4; 2827 *end = cea[2]; 2828 if (*end == 0) 2829 *end = 127; 2830 if (*end < 4 || *end > 127) 2831 return -ERANGE; 2832 return 0; 2833 } 2834 2835 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2836 { 2837 int hdmi_id; 2838 2839 if (cea_db_tag(db) != VENDOR_BLOCK) 2840 return false; 2841 2842 if (cea_db_payload_len(db) < 5) 2843 return false; 2844 2845 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2846 2847 return hdmi_id == HDMI_IEEE_OUI; 2848 } 2849 2850 #define for_each_cea_db(cea, i, start, end) \ 2851 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2852 2853 static int 2854 add_cea_modes(struct drm_connector *connector, struct edid *edid) 2855 { 2856 const u8 *cea = drm_find_cea_extension(edid); 2857 const u8 *db, *hdmi = NULL, *video = NULL; 2858 u8 dbl, hdmi_len, video_len = 0; 2859 int modes = 0; 2860 2861 if (cea && cea_revision(cea) >= 3) { 2862 int i, start, end; 2863 2864 if (cea_db_offsets(cea, &start, &end)) 2865 return 0; 2866 2867 for_each_cea_db(cea, i, start, end) { 2868 db = &cea[i]; 2869 dbl = cea_db_payload_len(db); 2870 2871 if (cea_db_tag(db) == VIDEO_BLOCK) { 2872 video = db + 1; 2873 video_len = dbl; 2874 modes += do_cea_modes(connector, video, dbl); 2875 } 2876 else if (cea_db_is_hdmi_vsdb(db)) { 2877 hdmi = db; 2878 hdmi_len = dbl; 2879 } 2880 } 2881 } 2882 2883 /* 2884 * We parse the HDMI VSDB after having added the cea modes as we will 2885 * be patching their flags when the sink supports stereo 3D. 2886 */ 2887 if (hdmi) 2888 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 2889 video_len); 2890 2891 return modes; 2892 } 2893 2894 static void 2895 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 2896 { 2897 u8 len = cea_db_payload_len(db); 2898 2899 if (len >= 6) { 2900 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 2901 connector->dvi_dual = db[6] & 1; 2902 } 2903 if (len >= 7) 2904 connector->max_tmds_clock = db[7] * 5; 2905 if (len >= 8) { 2906 connector->latency_present[0] = db[8] >> 7; 2907 connector->latency_present[1] = (db[8] >> 6) & 1; 2908 } 2909 if (len >= 9) 2910 connector->video_latency[0] = db[9]; 2911 if (len >= 10) 2912 connector->audio_latency[0] = db[10]; 2913 if (len >= 11) 2914 connector->video_latency[1] = db[11]; 2915 if (len >= 12) 2916 connector->audio_latency[1] = db[12]; 2917 2918 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 2919 "max TMDS clock %d, " 2920 "latency present %d %d, " 2921 "video latency %d %d, " 2922 "audio latency %d %d\n", 2923 connector->dvi_dual, 2924 connector->max_tmds_clock, 2925 (int) connector->latency_present[0], 2926 (int) connector->latency_present[1], 2927 connector->video_latency[0], 2928 connector->video_latency[1], 2929 connector->audio_latency[0], 2930 connector->audio_latency[1]); 2931 } 2932 2933 static void 2934 monitor_name(struct detailed_timing *t, void *data) 2935 { 2936 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 2937 *(u8 **)data = t->data.other_data.data.str.str; 2938 } 2939 2940 /** 2941 * drm_edid_to_eld - build ELD from EDID 2942 * @connector: connector corresponding to the HDMI/DP sink 2943 * @edid: EDID to parse 2944 * 2945 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. 2946 * Some ELD fields are left to the graphics driver caller: 2947 * - Conn_Type 2948 * - HDCP 2949 * - Port_ID 2950 */ 2951 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 2952 { 2953 uint8_t *eld = connector->eld; 2954 u8 *cea; 2955 u8 *name; 2956 u8 *db; 2957 int sad_count = 0; 2958 int mnl; 2959 int dbl; 2960 2961 memset(eld, 0, sizeof(connector->eld)); 2962 2963 cea = drm_find_cea_extension(edid); 2964 if (!cea) { 2965 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 2966 return; 2967 } 2968 2969 name = NULL; 2970 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 2971 for (mnl = 0; name && mnl < 13; mnl++) { 2972 if (name[mnl] == 0x0a) 2973 break; 2974 eld[20 + mnl] = name[mnl]; 2975 } 2976 eld[4] = (cea[1] << 5) | mnl; 2977 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 2978 2979 eld[0] = 2 << 3; /* ELD version: 2 */ 2980 2981 eld[16] = edid->mfg_id[0]; 2982 eld[17] = edid->mfg_id[1]; 2983 eld[18] = edid->prod_code[0]; 2984 eld[19] = edid->prod_code[1]; 2985 2986 if (cea_revision(cea) >= 3) { 2987 int i, start, end; 2988 2989 if (cea_db_offsets(cea, &start, &end)) { 2990 start = 0; 2991 end = 0; 2992 } 2993 2994 for_each_cea_db(cea, i, start, end) { 2995 db = &cea[i]; 2996 dbl = cea_db_payload_len(db); 2997 2998 switch (cea_db_tag(db)) { 2999 case AUDIO_BLOCK: 3000 /* Audio Data Block, contains SADs */ 3001 sad_count = dbl / 3; 3002 if (dbl >= 1) 3003 memcpy(eld + 20 + mnl, &db[1], dbl); 3004 break; 3005 case SPEAKER_BLOCK: 3006 /* Speaker Allocation Data Block */ 3007 if (dbl >= 1) 3008 eld[7] = db[1]; 3009 break; 3010 case VENDOR_BLOCK: 3011 /* HDMI Vendor-Specific Data Block */ 3012 if (cea_db_is_hdmi_vsdb(db)) 3013 parse_hdmi_vsdb(connector, db); 3014 break; 3015 default: 3016 break; 3017 } 3018 } 3019 } 3020 eld[5] |= sad_count << 4; 3021 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3022 3023 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3024 } 3025 EXPORT_SYMBOL(drm_edid_to_eld); 3026 3027 /** 3028 * drm_edid_to_sad - extracts SADs from EDID 3029 * @edid: EDID to parse 3030 * @sads: pointer that will be set to the extracted SADs 3031 * 3032 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3033 * Note: returned pointer needs to be kfreed 3034 * 3035 * Return number of found SADs or negative number on error. 3036 */ 3037 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3038 { 3039 int count = 0; 3040 int i, start, end, dbl; 3041 u8 *cea; 3042 3043 cea = drm_find_cea_extension(edid); 3044 if (!cea) { 3045 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3046 return -ENOENT; 3047 } 3048 3049 if (cea_revision(cea) < 3) { 3050 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3051 return -ENOTSUPP; 3052 } 3053 3054 if (cea_db_offsets(cea, &start, &end)) { 3055 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3056 return -EPROTO; 3057 } 3058 3059 for_each_cea_db(cea, i, start, end) { 3060 u8 *db = &cea[i]; 3061 3062 if (cea_db_tag(db) == AUDIO_BLOCK) { 3063 int j; 3064 dbl = cea_db_payload_len(db); 3065 3066 count = dbl / 3; /* SAD is 3B */ 3067 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3068 if (!*sads) 3069 return -ENOMEM; 3070 for (j = 0; j < count; j++) { 3071 u8 *sad = &db[1 + j * 3]; 3072 3073 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3074 (*sads)[j].channels = sad[0] & 0x7; 3075 (*sads)[j].freq = sad[1] & 0x7F; 3076 (*sads)[j].byte2 = sad[2]; 3077 } 3078 break; 3079 } 3080 } 3081 3082 return count; 3083 } 3084 EXPORT_SYMBOL(drm_edid_to_sad); 3085 3086 /** 3087 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3088 * @edid: EDID to parse 3089 * @sadb: pointer to the speaker block 3090 * 3091 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3092 * Note: returned pointer needs to be kfreed 3093 * 3094 * Return number of found Speaker Allocation Blocks or negative number on error. 3095 */ 3096 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3097 { 3098 int count = 0; 3099 int i, start, end, dbl; 3100 const u8 *cea; 3101 3102 cea = drm_find_cea_extension(edid); 3103 if (!cea) { 3104 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3105 return -ENOENT; 3106 } 3107 3108 if (cea_revision(cea) < 3) { 3109 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3110 return -ENOTSUPP; 3111 } 3112 3113 if (cea_db_offsets(cea, &start, &end)) { 3114 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3115 return -EPROTO; 3116 } 3117 3118 for_each_cea_db(cea, i, start, end) { 3119 const u8 *db = &cea[i]; 3120 3121 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3122 dbl = cea_db_payload_len(db); 3123 3124 /* Speaker Allocation Data Block */ 3125 if (dbl == 3) { 3126 *sadb = kmalloc(dbl, GFP_KERNEL); 3127 if (!*sadb) 3128 return -ENOMEM; 3129 memcpy(*sadb, &db[1], dbl); 3130 count = dbl; 3131 break; 3132 } 3133 } 3134 } 3135 3136 return count; 3137 } 3138 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3139 3140 /** 3141 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond 3142 * @connector: connector associated with the HDMI/DP sink 3143 * @mode: the display mode 3144 */ 3145 int drm_av_sync_delay(struct drm_connector *connector, 3146 struct drm_display_mode *mode) 3147 { 3148 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3149 int a, v; 3150 3151 if (!connector->latency_present[0]) 3152 return 0; 3153 if (!connector->latency_present[1]) 3154 i = 0; 3155 3156 a = connector->audio_latency[i]; 3157 v = connector->video_latency[i]; 3158 3159 /* 3160 * HDMI/DP sink doesn't support audio or video? 3161 */ 3162 if (a == 255 || v == 255) 3163 return 0; 3164 3165 /* 3166 * Convert raw EDID values to millisecond. 3167 * Treat unknown latency as 0ms. 3168 */ 3169 if (a) 3170 a = min(2 * (a - 1), 500); 3171 if (v) 3172 v = min(2 * (v - 1), 500); 3173 3174 return max(v - a, 0); 3175 } 3176 EXPORT_SYMBOL(drm_av_sync_delay); 3177 3178 /** 3179 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3180 * @encoder: the encoder just changed display mode 3181 * @mode: the adjusted display mode 3182 * 3183 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3184 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3185 */ 3186 struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 3187 struct drm_display_mode *mode) 3188 { 3189 struct drm_connector *connector; 3190 struct drm_device *dev = encoder->dev; 3191 3192 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 3193 if (connector->encoder == encoder && connector->eld[0]) 3194 return connector; 3195 3196 return NULL; 3197 } 3198 EXPORT_SYMBOL(drm_select_eld); 3199 3200 /** 3201 * drm_detect_hdmi_monitor - detect whether monitor is hdmi. 3202 * @edid: monitor EDID information 3203 * 3204 * Parse the CEA extension according to CEA-861-B. 3205 * Return true if HDMI, false if not or unknown. 3206 */ 3207 bool drm_detect_hdmi_monitor(struct edid *edid) 3208 { 3209 u8 *edid_ext; 3210 int i; 3211 int start_offset, end_offset; 3212 3213 edid_ext = drm_find_cea_extension(edid); 3214 if (!edid_ext) 3215 return false; 3216 3217 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3218 return false; 3219 3220 /* 3221 * Because HDMI identifier is in Vendor Specific Block, 3222 * search it from all data blocks of CEA extension. 3223 */ 3224 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3225 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3226 return true; 3227 } 3228 3229 return false; 3230 } 3231 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3232 3233 /** 3234 * drm_detect_monitor_audio - check monitor audio capability 3235 * 3236 * Monitor should have CEA extension block. 3237 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3238 * audio' only. If there is any audio extension block and supported 3239 * audio format, assume at least 'basic audio' support, even if 'basic 3240 * audio' is not defined in EDID. 3241 * 3242 */ 3243 bool drm_detect_monitor_audio(struct edid *edid) 3244 { 3245 u8 *edid_ext; 3246 int i, j; 3247 bool has_audio = false; 3248 int start_offset, end_offset; 3249 3250 edid_ext = drm_find_cea_extension(edid); 3251 if (!edid_ext) 3252 goto end; 3253 3254 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3255 3256 if (has_audio) { 3257 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3258 goto end; 3259 } 3260 3261 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3262 goto end; 3263 3264 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3265 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3266 has_audio = true; 3267 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3268 DRM_DEBUG_KMS("CEA audio format %d\n", 3269 (edid_ext[i + j] >> 3) & 0xf); 3270 goto end; 3271 } 3272 } 3273 end: 3274 return has_audio; 3275 } 3276 EXPORT_SYMBOL(drm_detect_monitor_audio); 3277 3278 /** 3279 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3280 * 3281 * Check whether the monitor reports the RGB quantization range selection 3282 * as supported. The AVI infoframe can then be used to inform the monitor 3283 * which quantization range (full or limited) is used. 3284 */ 3285 bool drm_rgb_quant_range_selectable(struct edid *edid) 3286 { 3287 u8 *edid_ext; 3288 int i, start, end; 3289 3290 edid_ext = drm_find_cea_extension(edid); 3291 if (!edid_ext) 3292 return false; 3293 3294 if (cea_db_offsets(edid_ext, &start, &end)) 3295 return false; 3296 3297 for_each_cea_db(edid_ext, i, start, end) { 3298 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3299 cea_db_payload_len(&edid_ext[i]) == 2) { 3300 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3301 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3302 } 3303 } 3304 3305 return false; 3306 } 3307 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3308 3309 /** 3310 * drm_add_display_info - pull display info out if present 3311 * @edid: EDID data 3312 * @info: display info (attached to connector) 3313 * 3314 * Grab any available display info and stuff it into the drm_display_info 3315 * structure that's part of the connector. Useful for tracking bpp and 3316 * color spaces. 3317 */ 3318 static void drm_add_display_info(struct edid *edid, 3319 struct drm_display_info *info) 3320 { 3321 u8 *edid_ext; 3322 3323 info->width_mm = edid->width_cm * 10; 3324 info->height_mm = edid->height_cm * 10; 3325 3326 /* driver figures it out in this case */ 3327 info->bpc = 0; 3328 info->color_formats = 0; 3329 3330 if (edid->revision < 3) 3331 return; 3332 3333 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3334 return; 3335 3336 /* Get data from CEA blocks if present */ 3337 edid_ext = drm_find_cea_extension(edid); 3338 if (edid_ext) { 3339 info->cea_rev = edid_ext[1]; 3340 3341 /* The existence of a CEA block should imply RGB support */ 3342 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3343 if (edid_ext[3] & EDID_CEA_YCRCB444) 3344 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3345 if (edid_ext[3] & EDID_CEA_YCRCB422) 3346 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3347 } 3348 3349 /* Only defined for 1.4 with digital displays */ 3350 if (edid->revision < 4) 3351 return; 3352 3353 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3354 case DRM_EDID_DIGITAL_DEPTH_6: 3355 info->bpc = 6; 3356 break; 3357 case DRM_EDID_DIGITAL_DEPTH_8: 3358 info->bpc = 8; 3359 break; 3360 case DRM_EDID_DIGITAL_DEPTH_10: 3361 info->bpc = 10; 3362 break; 3363 case DRM_EDID_DIGITAL_DEPTH_12: 3364 info->bpc = 12; 3365 break; 3366 case DRM_EDID_DIGITAL_DEPTH_14: 3367 info->bpc = 14; 3368 break; 3369 case DRM_EDID_DIGITAL_DEPTH_16: 3370 info->bpc = 16; 3371 break; 3372 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3373 default: 3374 info->bpc = 0; 3375 break; 3376 } 3377 3378 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3379 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3380 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3381 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3382 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3383 } 3384 3385 /** 3386 * drm_add_edid_modes - add modes from EDID data, if available 3387 * @connector: connector we're probing 3388 * @edid: edid data 3389 * 3390 * Add the specified modes to the connector's mode list. 3391 * 3392 * Return number of modes added or 0 if we couldn't find any. 3393 */ 3394 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3395 { 3396 int num_modes = 0; 3397 u32 quirks; 3398 3399 if (edid == NULL) { 3400 return 0; 3401 } 3402 if (!drm_edid_is_valid(edid)) { 3403 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3404 drm_get_connector_name(connector)); 3405 return 0; 3406 } 3407 3408 quirks = edid_get_quirks(edid); 3409 3410 /* 3411 * EDID spec says modes should be preferred in this order: 3412 * - preferred detailed mode 3413 * - other detailed modes from base block 3414 * - detailed modes from extension blocks 3415 * - CVT 3-byte code modes 3416 * - standard timing codes 3417 * - established timing codes 3418 * - modes inferred from GTF or CVT range information 3419 * 3420 * We get this pretty much right. 3421 * 3422 * XXX order for additional mode types in extension blocks? 3423 */ 3424 num_modes += add_detailed_modes(connector, edid, quirks); 3425 num_modes += add_cvt_modes(connector, edid); 3426 num_modes += add_standard_modes(connector, edid); 3427 num_modes += add_established_modes(connector, edid); 3428 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3429 num_modes += add_inferred_modes(connector, edid); 3430 num_modes += add_cea_modes(connector, edid); 3431 num_modes += add_alternate_cea_modes(connector, edid); 3432 3433 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3434 edid_fixup_preferred(connector, quirks); 3435 3436 drm_add_display_info(edid, &connector->display_info); 3437 3438 return num_modes; 3439 } 3440 EXPORT_SYMBOL(drm_add_edid_modes); 3441 3442 /** 3443 * drm_add_modes_noedid - add modes for the connectors without EDID 3444 * @connector: connector we're probing 3445 * @hdisplay: the horizontal display limit 3446 * @vdisplay: the vertical display limit 3447 * 3448 * Add the specified modes to the connector's mode list. Only when the 3449 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3450 * 3451 * Return number of modes added or 0 if we couldn't find any. 3452 */ 3453 int drm_add_modes_noedid(struct drm_connector *connector, 3454 int hdisplay, int vdisplay) 3455 { 3456 int i, count, num_modes = 0; 3457 struct drm_display_mode *mode; 3458 struct drm_device *dev = connector->dev; 3459 3460 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); 3461 if (hdisplay < 0) 3462 hdisplay = 0; 3463 if (vdisplay < 0) 3464 vdisplay = 0; 3465 3466 for (i = 0; i < count; i++) { 3467 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3468 if (hdisplay && vdisplay) { 3469 /* 3470 * Only when two are valid, they will be used to check 3471 * whether the mode should be added to the mode list of 3472 * the connector. 3473 */ 3474 if (ptr->hdisplay > hdisplay || 3475 ptr->vdisplay > vdisplay) 3476 continue; 3477 } 3478 if (drm_mode_vrefresh(ptr) > 61) 3479 continue; 3480 mode = drm_mode_duplicate(dev, ptr); 3481 if (mode) { 3482 drm_mode_probed_add(connector, mode); 3483 num_modes++; 3484 } 3485 } 3486 return num_modes; 3487 } 3488 EXPORT_SYMBOL(drm_add_modes_noedid); 3489 3490 void drm_set_preferred_mode(struct drm_connector *connector, 3491 int hpref, int vpref) 3492 { 3493 struct drm_display_mode *mode; 3494 3495 list_for_each_entry(mode, &connector->probed_modes, head) { 3496 if (drm_mode_width(mode) == hpref && 3497 drm_mode_height(mode) == vpref) 3498 mode->type |= DRM_MODE_TYPE_PREFERRED; 3499 } 3500 } 3501 EXPORT_SYMBOL(drm_set_preferred_mode); 3502 3503 /** 3504 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3505 * data from a DRM display mode 3506 * @frame: HDMI AVI infoframe 3507 * @mode: DRM display mode 3508 * 3509 * Returns 0 on success or a negative error code on failure. 3510 */ 3511 int 3512 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3513 const struct drm_display_mode *mode) 3514 { 3515 int err; 3516 3517 if (!frame || !mode) 3518 return -EINVAL; 3519 3520 err = hdmi_avi_infoframe_init(frame); 3521 if (err < 0) 3522 return err; 3523 3524 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3525 frame->pixel_repeat = 1; 3526 3527 frame->video_code = drm_match_cea_mode(mode); 3528 3529 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3530 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3531 3532 return 0; 3533 } 3534 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3535 3536 static enum hdmi_3d_structure 3537 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3538 { 3539 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3540 3541 switch (layout) { 3542 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3543 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3544 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3545 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3546 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3547 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3548 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3549 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 3550 case DRM_MODE_FLAG_3D_L_DEPTH: 3551 return HDMI_3D_STRUCTURE_L_DEPTH; 3552 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 3553 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 3554 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 3555 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 3556 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 3557 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 3558 default: 3559 return HDMI_3D_STRUCTURE_INVALID; 3560 } 3561 } 3562 3563 /** 3564 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 3565 * data from a DRM display mode 3566 * @frame: HDMI vendor infoframe 3567 * @mode: DRM display mode 3568 * 3569 * Note that there's is a need to send HDMI vendor infoframes only when using a 3570 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 3571 * function will return -EINVAL, error that can be safely ignored. 3572 * 3573 * Returns 0 on success or a negative error code on failure. 3574 */ 3575 int 3576 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 3577 const struct drm_display_mode *mode) 3578 { 3579 int err; 3580 u32 s3d_flags; 3581 u8 vic; 3582 3583 if (!frame || !mode) 3584 return -EINVAL; 3585 3586 vic = drm_match_hdmi_mode(mode); 3587 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 3588 3589 if (!vic && !s3d_flags) 3590 return -EINVAL; 3591 3592 if (vic && s3d_flags) 3593 return -EINVAL; 3594 3595 err = hdmi_vendor_infoframe_init(frame); 3596 if (err < 0) 3597 return err; 3598 3599 if (vic) 3600 frame->vic = vic; 3601 else 3602 frame->s3d_struct = s3d_structure_from_display_mode(mode); 3603 3604 return 0; 3605 } 3606 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 3607