1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 91 #define MICROSOFT_IEEE_OUI 0xca125c 92 93 struct detailed_mode_closure { 94 struct drm_connector *connector; 95 const struct drm_edid *drm_edid; 96 bool preferred; 97 u32 quirks; 98 int modes; 99 }; 100 101 #define LEVEL_DMT 0 102 #define LEVEL_GTF 1 103 #define LEVEL_GTF2 2 104 #define LEVEL_CVT 3 105 106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 107 { \ 108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 109 product_id), \ 110 .quirks = _quirks \ 111 } 112 113 static const struct edid_quirk { 114 u32 panel_id; 115 u32 quirks; 116 } edid_quirk_list[] = { 117 /* Acer AL1706 */ 118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 119 /* Acer F51 */ 120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 121 122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 124 125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 127 128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 130 131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 133 134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 136 137 /* Belinea 10 15 55 */ 138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 140 141 /* Envision Peripherals, Inc. EN-7100e */ 142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 143 /* Envision EN2028 */ 144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 145 146 /* Funai Electronics PM36B */ 147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 148 EDID_QUIRK_DETAILED_IN_CM), 149 150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 152 153 /* LG Philips LCD LP154W01-A5 */ 154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 156 157 /* Samsung SyncMaster 205BW. Note: irony */ 158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 159 /* Samsung SyncMaster 22[5-6]BW */ 160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 162 163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 165 166 /* ViewSonic VA2026w */ 167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 168 169 /* Medion MD 30217 PG */ 170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 171 172 /* Lenovo G50 */ 173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 174 175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 177 178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 180 181 /* Valve Index Headset */ 182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 199 200 /* HTC Vive and Vive Pro VR Headsets */ 201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 203 204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 209 210 /* Windows Mixed Reality Headsets */ 211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 217 218 /* Sony PlayStation VR Headset */ 219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 220 221 /* Sensics VR Headsets */ 222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 223 224 /* OSVR HDK and HDK2 VR Headsets */ 225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 226 }; 227 228 /* 229 * Autogenerated from the DMT spec. 230 * This table is copied from xfree86/modes/xf86EdidModes.c. 231 */ 232 static const struct drm_display_mode drm_dmt_modes[] = { 233 /* 0x01 - 640x350@85Hz */ 234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 235 736, 832, 0, 350, 382, 385, 445, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 0x02 - 640x400@85Hz */ 238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 239 736, 832, 0, 400, 401, 404, 445, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 0x03 - 720x400@85Hz */ 242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 243 828, 936, 0, 400, 401, 404, 446, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 0x04 - 640x480@60Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 247 752, 800, 0, 480, 490, 492, 525, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x05 - 640x480@72Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 251 704, 832, 0, 480, 489, 492, 520, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x06 - 640x480@75Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 255 720, 840, 0, 480, 481, 484, 500, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x07 - 640x480@85Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 259 752, 832, 0, 480, 481, 484, 509, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x08 - 800x600@56Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 263 896, 1024, 0, 600, 601, 603, 625, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x09 - 800x600@60Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 267 968, 1056, 0, 600, 601, 605, 628, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0a - 800x600@72Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 271 976, 1040, 0, 600, 637, 643, 666, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0b - 800x600@75Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 275 896, 1056, 0, 600, 601, 604, 625, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0c - 800x600@85Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 279 896, 1048, 0, 600, 601, 604, 631, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0d - 800x600@120Hz RB */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 283 880, 960, 0, 600, 603, 607, 636, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 285 /* 0x0e - 848x480@60Hz */ 286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 287 976, 1088, 0, 480, 486, 494, 517, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0f - 1024x768@43Hz, interlace */ 290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 291 1208, 1264, 0, 768, 768, 776, 817, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 293 DRM_MODE_FLAG_INTERLACE) }, 294 /* 0x10 - 1024x768@60Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 296 1184, 1344, 0, 768, 771, 777, 806, 0, 297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 298 /* 0x11 - 1024x768@70Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 300 1184, 1328, 0, 768, 771, 777, 806, 0, 301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 302 /* 0x12 - 1024x768@75Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 304 1136, 1312, 0, 768, 769, 772, 800, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x13 - 1024x768@85Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 308 1168, 1376, 0, 768, 769, 772, 808, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x14 - 1024x768@120Hz RB */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 312 1104, 1184, 0, 768, 771, 775, 813, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x15 - 1152x864@75Hz */ 315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 316 1344, 1600, 0, 864, 865, 868, 900, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x55 - 1280x720@60Hz */ 319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 320 1430, 1650, 0, 720, 725, 730, 750, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x16 - 1280x768@60Hz RB */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 324 1360, 1440, 0, 768, 771, 778, 790, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 326 /* 0x17 - 1280x768@60Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 328 1472, 1664, 0, 768, 771, 778, 798, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x18 - 1280x768@75Hz */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 332 1488, 1696, 0, 768, 771, 778, 805, 0, 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 334 /* 0x19 - 1280x768@85Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 336 1496, 1712, 0, 768, 771, 778, 809, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x1a - 1280x768@120Hz RB */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 340 1360, 1440, 0, 768, 771, 778, 813, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 342 /* 0x1b - 1280x800@60Hz RB */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 344 1360, 1440, 0, 800, 803, 809, 823, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 346 /* 0x1c - 1280x800@60Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 348 1480, 1680, 0, 800, 803, 809, 831, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1d - 1280x800@75Hz */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 352 1488, 1696, 0, 800, 803, 809, 838, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x1e - 1280x800@85Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 356 1496, 1712, 0, 800, 803, 809, 843, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1f - 1280x800@120Hz RB */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 360 1360, 1440, 0, 800, 803, 809, 847, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 362 /* 0x20 - 1280x960@60Hz */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 364 1488, 1800, 0, 960, 961, 964, 1000, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x21 - 1280x960@85Hz */ 367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 368 1504, 1728, 0, 960, 961, 964, 1011, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x22 - 1280x960@120Hz RB */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 372 1360, 1440, 0, 960, 963, 967, 1017, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 374 /* 0x23 - 1280x1024@60Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x24 - 1280x1024@75Hz */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x25 - 1280x1024@85Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x26 - 1280x1024@120Hz RB */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x27 - 1360x768@60Hz */ 391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 392 1536, 1792, 0, 768, 771, 777, 795, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x28 - 1360x768@120Hz RB */ 395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 396 1440, 1520, 0, 768, 771, 776, 813, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x51 - 1366x768@60Hz */ 399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 400 1579, 1792, 0, 768, 771, 774, 798, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x56 - 1366x768@60Hz */ 403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 404 1436, 1500, 0, 768, 769, 772, 800, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x29 - 1400x1050@60Hz RB */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 410 /* 0x2a - 1400x1050@60Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2b - 1400x1050@75Hz */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x2c - 1400x1050@85Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2d - 1400x1050@120Hz RB */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 426 /* 0x2e - 1440x900@60Hz RB */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 428 1520, 1600, 0, 900, 903, 909, 926, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 430 /* 0x2f - 1440x900@60Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 432 1672, 1904, 0, 900, 903, 909, 934, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x30 - 1440x900@75Hz */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 436 1688, 1936, 0, 900, 903, 909, 942, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x31 - 1440x900@85Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 440 1696, 1952, 0, 900, 903, 909, 948, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x32 - 1440x900@120Hz RB */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 444 1520, 1600, 0, 900, 903, 909, 953, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 446 /* 0x53 - 1600x900@60Hz */ 447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 448 1704, 1800, 0, 900, 901, 904, 1000, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x33 - 1600x1200@60Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x34 - 1600x1200@65Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x35 - 1600x1200@70Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x36 - 1600x1200@75Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x37 - 1600x1200@85Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x38 - 1600x1200@120Hz RB */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 474 /* 0x39 - 1680x1050@60Hz RB */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x3a - 1680x1050@60Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3b - 1680x1050@75Hz */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x3c - 1680x1050@85Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3d - 1680x1050@120Hz RB */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 494 /* 0x3e - 1792x1344@60Hz */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3f - 1792x1344@75Hz */ 499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x40 - 1792x1344@120Hz RB */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x41 - 1856x1392@60Hz */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x42 - 1856x1392@75Hz */ 511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x43 - 1856x1392@120Hz RB */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x52 - 1920x1080@60Hz */ 519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 522 /* 0x44 - 1920x1200@60Hz RB */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x45 - 1920x1200@60Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x46 - 1920x1200@75Hz */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x47 - 1920x1200@85Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x48 - 1920x1200@120Hz RB */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 542 /* 0x49 - 1920x1440@60Hz */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x4a - 1920x1440@75Hz */ 547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4b - 1920x1440@120Hz RB */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x54 - 2048x1152@60Hz */ 555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4c - 2560x1600@60Hz RB */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x4d - 2560x1600@60Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4e - 2560x1600@75Hz */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 570 /* 0x4f - 2560x1600@85Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x50 - 2560x1600@120Hz RB */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 /* 0x57 - 4096x2160@60Hz RB */ 579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 582 /* 0x58 - 4096x2160@59.94Hz RB */ 583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 }; 587 588 /* 589 * These more or less come from the DMT spec. The 720x400 modes are 590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 593 * mode. 594 * 595 * The DMT modes have been fact-checked; the rest are mild guesses. 596 */ 597 static const struct drm_display_mode edid_est_modes[] = { 598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 599 968, 1056, 0, 600, 601, 605, 628, 0, 600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 602 896, 1024, 0, 600, 601, 603, 625, 0, 603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 605 720, 840, 0, 480, 481, 484, 500, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 608 704, 832, 0, 480, 489, 492, 520, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 611 768, 864, 0, 480, 483, 486, 525, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 614 752, 800, 0, 480, 490, 492, 525, 0, 615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 617 846, 900, 0, 400, 421, 423, 449, 0, 618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 620 846, 900, 0, 400, 412, 414, 449, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 626 1136, 1312, 0, 768, 769, 772, 800, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 629 1184, 1328, 0, 768, 771, 777, 806, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 632 1184, 1344, 0, 768, 771, 777, 806, 0, 633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 635 1208, 1264, 0, 768, 768, 776, 817, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 638 928, 1152, 0, 624, 625, 628, 667, 0, 639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 641 896, 1056, 0, 600, 601, 604, 625, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 644 976, 1040, 0, 600, 637, 643, 666, 0, 645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 647 1344, 1600, 0, 864, 865, 868, 900, 0, 648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 649 }; 650 651 struct minimode { 652 short w; 653 short h; 654 short r; 655 short rb; 656 }; 657 658 static const struct minimode est3_modes[] = { 659 /* byte 6 */ 660 { 640, 350, 85, 0 }, 661 { 640, 400, 85, 0 }, 662 { 720, 400, 85, 0 }, 663 { 640, 480, 85, 0 }, 664 { 848, 480, 60, 0 }, 665 { 800, 600, 85, 0 }, 666 { 1024, 768, 85, 0 }, 667 { 1152, 864, 75, 0 }, 668 /* byte 7 */ 669 { 1280, 768, 60, 1 }, 670 { 1280, 768, 60, 0 }, 671 { 1280, 768, 75, 0 }, 672 { 1280, 768, 85, 0 }, 673 { 1280, 960, 60, 0 }, 674 { 1280, 960, 85, 0 }, 675 { 1280, 1024, 60, 0 }, 676 { 1280, 1024, 85, 0 }, 677 /* byte 8 */ 678 { 1360, 768, 60, 0 }, 679 { 1440, 900, 60, 1 }, 680 { 1440, 900, 60, 0 }, 681 { 1440, 900, 75, 0 }, 682 { 1440, 900, 85, 0 }, 683 { 1400, 1050, 60, 1 }, 684 { 1400, 1050, 60, 0 }, 685 { 1400, 1050, 75, 0 }, 686 /* byte 9 */ 687 { 1400, 1050, 85, 0 }, 688 { 1680, 1050, 60, 1 }, 689 { 1680, 1050, 60, 0 }, 690 { 1680, 1050, 75, 0 }, 691 { 1680, 1050, 85, 0 }, 692 { 1600, 1200, 60, 0 }, 693 { 1600, 1200, 65, 0 }, 694 { 1600, 1200, 70, 0 }, 695 /* byte 10 */ 696 { 1600, 1200, 75, 0 }, 697 { 1600, 1200, 85, 0 }, 698 { 1792, 1344, 60, 0 }, 699 { 1792, 1344, 75, 0 }, 700 { 1856, 1392, 60, 0 }, 701 { 1856, 1392, 75, 0 }, 702 { 1920, 1200, 60, 1 }, 703 { 1920, 1200, 60, 0 }, 704 /* byte 11 */ 705 { 1920, 1200, 75, 0 }, 706 { 1920, 1200, 85, 0 }, 707 { 1920, 1440, 60, 0 }, 708 { 1920, 1440, 75, 0 }, 709 }; 710 711 static const struct minimode extra_modes[] = { 712 { 1024, 576, 60, 0 }, 713 { 1366, 768, 60, 0 }, 714 { 1600, 900, 60, 0 }, 715 { 1680, 945, 60, 0 }, 716 { 1920, 1080, 60, 0 }, 717 { 2048, 1152, 60, 0 }, 718 { 2048, 1536, 60, 0 }, 719 }; 720 721 /* 722 * From CEA/CTA-861 spec. 723 * 724 * Do not access directly, instead always use cea_mode_for_vic(). 725 */ 726 static const struct drm_display_mode edid_cea_modes_1[] = { 727 /* 1 - 640x480@60Hz 4:3 */ 728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 729 752, 800, 0, 480, 490, 492, 525, 0, 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 732 /* 2 - 720x480@60Hz 4:3 */ 733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 734 798, 858, 0, 480, 489, 495, 525, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 3 - 720x480@60Hz 16:9 */ 738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 739 798, 858, 0, 480, 489, 495, 525, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 4 - 1280x720@60Hz 16:9 */ 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 744 1430, 1650, 0, 720, 725, 730, 750, 0, 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 5 - 1920x1080i@60Hz 16:9 */ 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 6 - 720(1440)x480i@60Hz 4:3 */ 754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 755 801, 858, 0, 480, 488, 494, 525, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 759 /* 7 - 720(1440)x480i@60Hz 16:9 */ 760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 761 801, 858, 0, 480, 488, 494, 525, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 8 - 720(1440)x240@60Hz 4:3 */ 766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 767 801, 858, 0, 240, 244, 247, 262, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 9 - 720(1440)x240@60Hz 16:9 */ 772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 773 801, 858, 0, 240, 244, 247, 262, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_DBLCLK), 776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 10 - 2880x480i@60Hz 4:3 */ 778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 779 3204, 3432, 0, 480, 488, 494, 525, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 11 - 2880x480i@60Hz 16:9 */ 784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 785 3204, 3432, 0, 480, 488, 494, 525, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_INTERLACE), 788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 12 - 2880x240@60Hz 4:3 */ 790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 791 3204, 3432, 0, 240, 244, 247, 262, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 13 - 2880x240@60Hz 16:9 */ 795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 240, 244, 247, 262, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 14 - 1440x480@60Hz 4:3 */ 800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 801 1596, 1716, 0, 480, 489, 495, 525, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 804 /* 15 - 1440x480@60Hz 16:9 */ 805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 806 1596, 1716, 0, 480, 489, 495, 525, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 16 - 1920x1080@60Hz 16:9 */ 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 17 - 720x576@50Hz 4:3 */ 815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 816 796, 864, 0, 576, 581, 586, 625, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 819 /* 18 - 720x576@50Hz 16:9 */ 820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 821 796, 864, 0, 576, 581, 586, 625, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 19 - 1280x720@50Hz 16:9 */ 825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 826 1760, 1980, 0, 720, 725, 730, 750, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 20 - 1920x1080i@50Hz 16:9 */ 830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 833 DRM_MODE_FLAG_INTERLACE), 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 21 - 720(1440)x576i@50Hz 4:3 */ 836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 837 795, 864, 0, 576, 580, 586, 625, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 841 /* 22 - 720(1440)x576i@50Hz 16:9 */ 842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 843 795, 864, 0, 576, 580, 586, 625, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 847 /* 23 - 720(1440)x288@50Hz 4:3 */ 848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 849 795, 864, 0, 288, 290, 293, 312, 0, 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 851 DRM_MODE_FLAG_DBLCLK), 852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 24 - 720(1440)x288@50Hz 16:9 */ 854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 855 795, 864, 0, 288, 290, 293, 312, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 857 DRM_MODE_FLAG_DBLCLK), 858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 25 - 2880x576i@50Hz 4:3 */ 860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 861 3180, 3456, 0, 576, 580, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 865 /* 26 - 2880x576i@50Hz 16:9 */ 866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 867 3180, 3456, 0, 576, 580, 586, 625, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 869 DRM_MODE_FLAG_INTERLACE), 870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 871 /* 27 - 2880x288@50Hz 4:3 */ 872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 873 3180, 3456, 0, 288, 290, 293, 312, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 28 - 2880x288@50Hz 16:9 */ 877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 288, 290, 293, 312, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 881 /* 29 - 1440x576@50Hz 4:3 */ 882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 883 1592, 1728, 0, 576, 581, 586, 625, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 886 /* 30 - 1440x576@50Hz 16:9 */ 887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 888 1592, 1728, 0, 576, 581, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 891 /* 31 - 1920x1080@50Hz 16:9 */ 892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 896 /* 32 - 1920x1080@24Hz 16:9 */ 897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 33 - 1920x1080@25Hz 16:9 */ 902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 34 - 1920x1080@30Hz 16:9 */ 907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 911 /* 35 - 2880x480@60Hz 4:3 */ 912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 913 3192, 3432, 0, 480, 489, 495, 525, 0, 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 916 /* 36 - 2880x480@60Hz 16:9 */ 917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 918 3192, 3432, 0, 480, 489, 495, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 37 - 2880x576@50Hz 4:3 */ 922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 923 3184, 3456, 0, 576, 581, 586, 625, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 926 /* 38 - 2880x576@50Hz 16:9 */ 927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 928 3184, 3456, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 39 - 1920x1080i@50Hz 16:9 */ 932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 935 DRM_MODE_FLAG_INTERLACE), 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 937 /* 40 - 1920x1080i@100Hz 16:9 */ 938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 941 DRM_MODE_FLAG_INTERLACE), 942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 41 - 1280x720@100Hz 16:9 */ 944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 945 1760, 1980, 0, 720, 725, 730, 750, 0, 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 42 - 720x576@100Hz 4:3 */ 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 950 796, 864, 0, 576, 581, 586, 625, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 953 /* 43 - 720x576@100Hz 16:9 */ 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 955 796, 864, 0, 576, 581, 586, 625, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 /* 44 - 720(1440)x576i@100Hz 4:3 */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 45 - 720(1440)x576i@100Hz 16:9 */ 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 966 795, 864, 0, 576, 580, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 46 - 1920x1080i@120Hz 16:9 */ 971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 974 DRM_MODE_FLAG_INTERLACE), 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 976 /* 47 - 1280x720@120Hz 16:9 */ 977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 978 1430, 1650, 0, 720, 725, 730, 750, 0, 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 48 - 720x480@120Hz 4:3 */ 982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 983 798, 858, 0, 480, 489, 495, 525, 0, 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 986 /* 49 - 720x480@120Hz 16:9 */ 987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 988 798, 858, 0, 480, 489, 495, 525, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 991 /* 50 - 720(1440)x480i@120Hz 4:3 */ 992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 993 801, 858, 0, 480, 488, 494, 525, 0, 994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 997 /* 51 - 720(1440)x480i@120Hz 16:9 */ 998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 999 801, 858, 0, 480, 488, 494, 525, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1003 /* 52 - 720x576@200Hz 4:3 */ 1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1005 796, 864, 0, 576, 581, 586, 625, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1008 /* 53 - 720x576@200Hz 16:9 */ 1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1010 796, 864, 0, 576, 581, 586, 625, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1013 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1015 795, 864, 0, 576, 580, 586, 625, 0, 1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1019 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1021 795, 864, 0, 576, 580, 586, 625, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1025 /* 56 - 720x480@240Hz 4:3 */ 1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1027 798, 858, 0, 480, 489, 495, 525, 0, 1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1030 /* 57 - 720x480@240Hz 16:9 */ 1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1032 798, 858, 0, 480, 489, 495, 525, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1035 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1037 801, 858, 0, 480, 488, 494, 525, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1041 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1043 801, 858, 0, 480, 488, 494, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1047 /* 60 - 1280x720@24Hz 16:9 */ 1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1049 3080, 3300, 0, 720, 725, 730, 750, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1052 /* 61 - 1280x720@25Hz 16:9 */ 1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1054 3740, 3960, 0, 720, 725, 730, 750, 0, 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1057 /* 62 - 1280x720@30Hz 16:9 */ 1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1059 3080, 3300, 0, 720, 725, 730, 750, 0, 1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1062 /* 63 - 1920x1080@120Hz 16:9 */ 1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1067 /* 64 - 1920x1080@100Hz 16:9 */ 1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1072 /* 65 - 1280x720@24Hz 64:27 */ 1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1074 3080, 3300, 0, 720, 725, 730, 750, 0, 1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1077 /* 66 - 1280x720@25Hz 64:27 */ 1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1079 3740, 3960, 0, 720, 725, 730, 750, 0, 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1082 /* 67 - 1280x720@30Hz 64:27 */ 1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1084 3080, 3300, 0, 720, 725, 730, 750, 0, 1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1087 /* 68 - 1280x720@50Hz 64:27 */ 1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1089 1760, 1980, 0, 720, 725, 730, 750, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1092 /* 69 - 1280x720@60Hz 64:27 */ 1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1094 1430, 1650, 0, 720, 725, 730, 750, 0, 1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1097 /* 70 - 1280x720@100Hz 64:27 */ 1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1099 1760, 1980, 0, 720, 725, 730, 750, 0, 1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1102 /* 71 - 1280x720@120Hz 64:27 */ 1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1104 1430, 1650, 0, 720, 725, 730, 750, 0, 1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1107 /* 72 - 1920x1080@24Hz 64:27 */ 1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1112 /* 73 - 1920x1080@25Hz 64:27 */ 1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1117 /* 74 - 1920x1080@30Hz 64:27 */ 1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1122 /* 75 - 1920x1080@50Hz 64:27 */ 1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1127 /* 76 - 1920x1080@60Hz 64:27 */ 1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1132 /* 77 - 1920x1080@100Hz 64:27 */ 1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1137 /* 78 - 1920x1080@120Hz 64:27 */ 1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1142 /* 79 - 1680x720@24Hz 64:27 */ 1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1144 3080, 3300, 0, 720, 725, 730, 750, 0, 1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1147 /* 80 - 1680x720@25Hz 64:27 */ 1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1149 2948, 3168, 0, 720, 725, 730, 750, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1152 /* 81 - 1680x720@30Hz 64:27 */ 1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1154 2420, 2640, 0, 720, 725, 730, 750, 0, 1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1157 /* 82 - 1680x720@50Hz 64:27 */ 1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1159 1980, 2200, 0, 720, 725, 730, 750, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1162 /* 83 - 1680x720@60Hz 64:27 */ 1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1164 1980, 2200, 0, 720, 725, 730, 750, 0, 1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1167 /* 84 - 1680x720@100Hz 64:27 */ 1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1169 1780, 2000, 0, 720, 725, 730, 825, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1172 /* 85 - 1680x720@120Hz 64:27 */ 1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1174 1780, 2000, 0, 720, 725, 730, 825, 0, 1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1177 /* 86 - 2560x1080@24Hz 64:27 */ 1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1182 /* 87 - 2560x1080@25Hz 64:27 */ 1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1187 /* 88 - 2560x1080@30Hz 64:27 */ 1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1192 /* 89 - 2560x1080@50Hz 64:27 */ 1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1197 /* 90 - 2560x1080@60Hz 64:27 */ 1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1202 /* 91 - 2560x1080@100Hz 64:27 */ 1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1207 /* 92 - 2560x1080@120Hz 64:27 */ 1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1212 /* 93 - 3840x2160@24Hz 16:9 */ 1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1217 /* 94 - 3840x2160@25Hz 16:9 */ 1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1222 /* 95 - 3840x2160@30Hz 16:9 */ 1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1227 /* 96 - 3840x2160@50Hz 16:9 */ 1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1232 /* 97 - 3840x2160@60Hz 16:9 */ 1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1237 /* 98 - 4096x2160@24Hz 256:135 */ 1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1242 /* 99 - 4096x2160@25Hz 256:135 */ 1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1247 /* 100 - 4096x2160@30Hz 256:135 */ 1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1252 /* 101 - 4096x2160@50Hz 256:135 */ 1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1257 /* 102 - 4096x2160@60Hz 256:135 */ 1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1262 /* 103 - 3840x2160@24Hz 64:27 */ 1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1267 /* 104 - 3840x2160@25Hz 64:27 */ 1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1272 /* 105 - 3840x2160@30Hz 64:27 */ 1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1277 /* 106 - 3840x2160@50Hz 64:27 */ 1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1282 /* 107 - 3840x2160@60Hz 64:27 */ 1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1287 /* 108 - 1280x720@48Hz 16:9 */ 1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1289 2280, 2500, 0, 720, 725, 730, 750, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1292 /* 109 - 1280x720@48Hz 64:27 */ 1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1294 2280, 2500, 0, 720, 725, 730, 750, 0, 1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1297 /* 110 - 1680x720@48Hz 64:27 */ 1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1299 2530, 2750, 0, 720, 725, 730, 750, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1302 /* 111 - 1920x1080@48Hz 16:9 */ 1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1307 /* 112 - 1920x1080@48Hz 64:27 */ 1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1312 /* 113 - 2560x1080@48Hz 64:27 */ 1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1317 /* 114 - 3840x2160@48Hz 16:9 */ 1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1322 /* 115 - 4096x2160@48Hz 256:135 */ 1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1327 /* 116 - 3840x2160@48Hz 64:27 */ 1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1332 /* 117 - 3840x2160@100Hz 16:9 */ 1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1337 /* 118 - 3840x2160@120Hz 16:9 */ 1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1342 /* 119 - 3840x2160@100Hz 64:27 */ 1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1347 /* 120 - 3840x2160@120Hz 64:27 */ 1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1352 /* 121 - 5120x2160@24Hz 64:27 */ 1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1357 /* 122 - 5120x2160@25Hz 64:27 */ 1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1362 /* 123 - 5120x2160@30Hz 64:27 */ 1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1367 /* 124 - 5120x2160@48Hz 64:27 */ 1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1372 /* 125 - 5120x2160@50Hz 64:27 */ 1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1377 /* 126 - 5120x2160@60Hz 64:27 */ 1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1382 /* 127 - 5120x2160@100Hz 64:27 */ 1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1387 }; 1388 1389 /* 1390 * From CEA/CTA-861 spec. 1391 * 1392 * Do not access directly, instead always use cea_mode_for_vic(). 1393 */ 1394 static const struct drm_display_mode edid_cea_modes_193[] = { 1395 /* 193 - 5120x2160@120Hz 64:27 */ 1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1400 /* 194 - 7680x4320@24Hz 16:9 */ 1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1405 /* 195 - 7680x4320@25Hz 16:9 */ 1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1410 /* 196 - 7680x4320@30Hz 16:9 */ 1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1415 /* 197 - 7680x4320@48Hz 16:9 */ 1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1420 /* 198 - 7680x4320@50Hz 16:9 */ 1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1425 /* 199 - 7680x4320@60Hz 16:9 */ 1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1430 /* 200 - 7680x4320@100Hz 16:9 */ 1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1435 /* 201 - 7680x4320@120Hz 16:9 */ 1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1440 /* 202 - 7680x4320@24Hz 64:27 */ 1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1445 /* 203 - 7680x4320@25Hz 64:27 */ 1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1450 /* 204 - 7680x4320@30Hz 64:27 */ 1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1455 /* 205 - 7680x4320@48Hz 64:27 */ 1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1460 /* 206 - 7680x4320@50Hz 64:27 */ 1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1465 /* 207 - 7680x4320@60Hz 64:27 */ 1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1470 /* 208 - 7680x4320@100Hz 64:27 */ 1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1475 /* 209 - 7680x4320@120Hz 64:27 */ 1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1480 /* 210 - 10240x4320@24Hz 64:27 */ 1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1485 /* 211 - 10240x4320@25Hz 64:27 */ 1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1490 /* 212 - 10240x4320@30Hz 64:27 */ 1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1495 /* 213 - 10240x4320@48Hz 64:27 */ 1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1500 /* 214 - 10240x4320@50Hz 64:27 */ 1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1505 /* 215 - 10240x4320@60Hz 64:27 */ 1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1510 /* 216 - 10240x4320@100Hz 64:27 */ 1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1515 /* 217 - 10240x4320@120Hz 64:27 */ 1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1520 /* 218 - 4096x2160@100Hz 256:135 */ 1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1525 /* 219 - 4096x2160@120Hz 256:135 */ 1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1530 }; 1531 1532 /* 1533 * HDMI 1.4 4k modes. Index using the VIC. 1534 */ 1535 static const struct drm_display_mode edid_4k_modes[] = { 1536 /* 0 - dummy, VICs start at 1 */ 1537 { }, 1538 /* 1 - 3840x2160@30Hz */ 1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1540 3840, 4016, 4104, 4400, 0, 1541 2160, 2168, 2178, 2250, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1544 /* 2 - 3840x2160@25Hz */ 1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1546 3840, 4896, 4984, 5280, 0, 1547 2160, 2168, 2178, 2250, 0, 1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1550 /* 3 - 3840x2160@24Hz */ 1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1552 3840, 5116, 5204, 5500, 0, 1553 2160, 2168, 2178, 2250, 0, 1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1556 /* 4 - 4096x2160@24Hz (SMPTE) */ 1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1558 4096, 5116, 5204, 5500, 0, 1559 2160, 2168, 2178, 2250, 0, 1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1562 }; 1563 1564 /*** DDC fetch and block validation ***/ 1565 1566 /* 1567 * The opaque EDID type, internal to drm_edid.c. 1568 */ 1569 struct drm_edid { 1570 /* Size allocated for edid */ 1571 size_t size; 1572 const struct edid *edid; 1573 }; 1574 1575 static bool version_greater(const struct drm_edid *drm_edid, 1576 u8 version, u8 revision) 1577 { 1578 const struct edid *edid = drm_edid->edid; 1579 1580 return edid->version > version || 1581 (edid->version == version && edid->revision > revision); 1582 } 1583 1584 static int edid_extension_block_count(const struct edid *edid) 1585 { 1586 return edid->extensions; 1587 } 1588 1589 static int edid_block_count(const struct edid *edid) 1590 { 1591 return edid_extension_block_count(edid) + 1; 1592 } 1593 1594 static int edid_size_by_blocks(int num_blocks) 1595 { 1596 return num_blocks * EDID_LENGTH; 1597 } 1598 1599 static int edid_size(const struct edid *edid) 1600 { 1601 return edid_size_by_blocks(edid_block_count(edid)); 1602 } 1603 1604 static const void *edid_block_data(const struct edid *edid, int index) 1605 { 1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1607 1608 return edid + index; 1609 } 1610 1611 static const void *edid_extension_block_data(const struct edid *edid, int index) 1612 { 1613 return edid_block_data(edid, index + 1); 1614 } 1615 1616 /* 1617 * Initializer helper for legacy interfaces, where we have no choice but to 1618 * trust edid size. Not for general purpose use. 1619 */ 1620 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1621 const struct edid *edid) 1622 { 1623 if (!edid) 1624 return NULL; 1625 1626 memset(drm_edid, 0, sizeof(*drm_edid)); 1627 1628 drm_edid->edid = edid; 1629 drm_edid->size = edid_size(edid); 1630 1631 return drm_edid; 1632 } 1633 1634 /* 1635 * EDID base and extension block iterator. 1636 * 1637 * struct drm_edid_iter iter; 1638 * const u8 *block; 1639 * 1640 * drm_edid_iter_begin(drm_edid, &iter); 1641 * drm_edid_iter_for_each(block, &iter) { 1642 * // do stuff with block 1643 * } 1644 * drm_edid_iter_end(&iter); 1645 */ 1646 struct drm_edid_iter { 1647 const struct drm_edid *drm_edid; 1648 1649 /* Current block index. */ 1650 int index; 1651 }; 1652 1653 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1654 struct drm_edid_iter *iter) 1655 { 1656 memset(iter, 0, sizeof(*iter)); 1657 1658 iter->drm_edid = drm_edid; 1659 } 1660 1661 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1662 { 1663 const void *block = NULL; 1664 1665 if (!iter->drm_edid) 1666 return NULL; 1667 1668 if (iter->index < edid_block_count(iter->drm_edid->edid)) 1669 block = edid_block_data(iter->drm_edid->edid, iter->index++); 1670 1671 return block; 1672 } 1673 1674 #define drm_edid_iter_for_each(__block, __iter) \ 1675 while (((__block) = __drm_edid_iter_next(__iter))) 1676 1677 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1678 { 1679 memset(iter, 0, sizeof(*iter)); 1680 } 1681 1682 static const u8 edid_header[] = { 1683 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1684 }; 1685 1686 static void edid_header_fix(void *edid) 1687 { 1688 memcpy(edid, edid_header, sizeof(edid_header)); 1689 } 1690 1691 /** 1692 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1693 * @_edid: pointer to raw base EDID block 1694 * 1695 * Sanity check the header of the base EDID block. 1696 * 1697 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1698 */ 1699 int drm_edid_header_is_valid(const void *_edid) 1700 { 1701 const struct edid *edid = _edid; 1702 int i, score = 0; 1703 1704 for (i = 0; i < sizeof(edid_header); i++) { 1705 if (edid->header[i] == edid_header[i]) 1706 score++; 1707 } 1708 1709 return score; 1710 } 1711 EXPORT_SYMBOL(drm_edid_header_is_valid); 1712 1713 static int edid_fixup __read_mostly = 6; 1714 module_param_named(edid_fixup, edid_fixup, int, 0400); 1715 MODULE_PARM_DESC(edid_fixup, 1716 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1717 1718 static int edid_block_compute_checksum(const void *_block) 1719 { 1720 const u8 *block = _block; 1721 int i; 1722 u8 csum = 0, crc = 0; 1723 1724 for (i = 0; i < EDID_LENGTH - 1; i++) 1725 csum += block[i]; 1726 1727 crc = 0x100 - csum; 1728 1729 return crc; 1730 } 1731 1732 static int edid_block_get_checksum(const void *_block) 1733 { 1734 const struct edid *block = _block; 1735 1736 return block->checksum; 1737 } 1738 1739 static int edid_block_tag(const void *_block) 1740 { 1741 const u8 *block = _block; 1742 1743 return block[0]; 1744 } 1745 1746 static bool edid_block_is_zero(const void *edid) 1747 { 1748 return !memchr_inv(edid, 0, EDID_LENGTH); 1749 } 1750 1751 /** 1752 * drm_edid_are_equal - compare two edid blobs. 1753 * @edid1: pointer to first blob 1754 * @edid2: pointer to second blob 1755 * This helper can be used during probing to determine if 1756 * edid had changed. 1757 */ 1758 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1759 { 1760 int edid1_len, edid2_len; 1761 bool edid1_present = edid1 != NULL; 1762 bool edid2_present = edid2 != NULL; 1763 1764 if (edid1_present != edid2_present) 1765 return false; 1766 1767 if (edid1) { 1768 edid1_len = edid_size(edid1); 1769 edid2_len = edid_size(edid2); 1770 1771 if (edid1_len != edid2_len) 1772 return false; 1773 1774 if (memcmp(edid1, edid2, edid1_len)) 1775 return false; 1776 } 1777 1778 return true; 1779 } 1780 EXPORT_SYMBOL(drm_edid_are_equal); 1781 1782 enum edid_block_status { 1783 EDID_BLOCK_OK = 0, 1784 EDID_BLOCK_READ_FAIL, 1785 EDID_BLOCK_NULL, 1786 EDID_BLOCK_ZERO, 1787 EDID_BLOCK_HEADER_CORRUPT, 1788 EDID_BLOCK_HEADER_REPAIR, 1789 EDID_BLOCK_HEADER_FIXED, 1790 EDID_BLOCK_CHECKSUM, 1791 EDID_BLOCK_VERSION, 1792 }; 1793 1794 static enum edid_block_status edid_block_check(const void *_block, 1795 bool is_base_block) 1796 { 1797 const struct edid *block = _block; 1798 1799 if (!block) 1800 return EDID_BLOCK_NULL; 1801 1802 if (is_base_block) { 1803 int score = drm_edid_header_is_valid(block); 1804 1805 if (score < clamp(edid_fixup, 0, 8)) { 1806 if (edid_block_is_zero(block)) 1807 return EDID_BLOCK_ZERO; 1808 else 1809 return EDID_BLOCK_HEADER_CORRUPT; 1810 } 1811 1812 if (score < 8) 1813 return EDID_BLOCK_HEADER_REPAIR; 1814 } 1815 1816 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1817 if (edid_block_is_zero(block)) 1818 return EDID_BLOCK_ZERO; 1819 else 1820 return EDID_BLOCK_CHECKSUM; 1821 } 1822 1823 if (is_base_block) { 1824 if (block->version != 1) 1825 return EDID_BLOCK_VERSION; 1826 } 1827 1828 return EDID_BLOCK_OK; 1829 } 1830 1831 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1832 { 1833 return status == EDID_BLOCK_OK || 1834 status == EDID_BLOCK_HEADER_FIXED || 1835 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1836 } 1837 1838 static bool edid_block_valid(const void *block, bool base) 1839 { 1840 return edid_block_status_valid(edid_block_check(block, base), 1841 edid_block_tag(block)); 1842 } 1843 1844 static void edid_block_status_print(enum edid_block_status status, 1845 const struct edid *block, 1846 int block_num) 1847 { 1848 switch (status) { 1849 case EDID_BLOCK_OK: 1850 break; 1851 case EDID_BLOCK_READ_FAIL: 1852 pr_debug("EDID block %d read failed\n", block_num); 1853 break; 1854 case EDID_BLOCK_NULL: 1855 pr_debug("EDID block %d pointer is NULL\n", block_num); 1856 break; 1857 case EDID_BLOCK_ZERO: 1858 pr_notice("EDID block %d is all zeroes\n", block_num); 1859 break; 1860 case EDID_BLOCK_HEADER_CORRUPT: 1861 pr_notice("EDID has corrupt header\n"); 1862 break; 1863 case EDID_BLOCK_HEADER_REPAIR: 1864 pr_debug("EDID corrupt header needs repair\n"); 1865 break; 1866 case EDID_BLOCK_HEADER_FIXED: 1867 pr_debug("EDID corrupt header fixed\n"); 1868 break; 1869 case EDID_BLOCK_CHECKSUM: 1870 if (edid_block_status_valid(status, edid_block_tag(block))) { 1871 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1872 block_num, edid_block_tag(block), 1873 edid_block_compute_checksum(block)); 1874 } else { 1875 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1876 block_num, edid_block_tag(block), 1877 edid_block_compute_checksum(block)); 1878 } 1879 break; 1880 case EDID_BLOCK_VERSION: 1881 pr_notice("EDID has major version %d, instead of 1\n", 1882 block->version); 1883 break; 1884 default: 1885 WARN(1, "EDID block %d unknown edid block status code %d\n", 1886 block_num, status); 1887 break; 1888 } 1889 } 1890 1891 static void edid_block_dump(const char *level, const void *block, int block_num) 1892 { 1893 enum edid_block_status status; 1894 char prefix[20]; 1895 1896 status = edid_block_check(block, block_num == 0); 1897 if (status == EDID_BLOCK_ZERO) 1898 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1899 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1900 sprintf(prefix, "\t[%02x] BAD ", block_num); 1901 else 1902 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1903 1904 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1905 block, EDID_LENGTH, false); 1906 } 1907 1908 /** 1909 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1910 * @_block: pointer to raw EDID block 1911 * @block_num: type of block to validate (0 for base, extension otherwise) 1912 * @print_bad_edid: if true, dump bad EDID blocks to the console 1913 * @edid_corrupt: if true, the header or checksum is invalid 1914 * 1915 * Validate a base or extension EDID block and optionally dump bad blocks to 1916 * the console. 1917 * 1918 * Return: True if the block is valid, false otherwise. 1919 */ 1920 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1921 bool *edid_corrupt) 1922 { 1923 struct edid *block = (struct edid *)_block; 1924 enum edid_block_status status; 1925 bool is_base_block = block_num == 0; 1926 bool valid; 1927 1928 if (WARN_ON(!block)) 1929 return false; 1930 1931 status = edid_block_check(block, is_base_block); 1932 if (status == EDID_BLOCK_HEADER_REPAIR) { 1933 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1934 edid_header_fix(block); 1935 1936 /* Retry with fixed header, update status if that worked. */ 1937 status = edid_block_check(block, is_base_block); 1938 if (status == EDID_BLOCK_OK) 1939 status = EDID_BLOCK_HEADER_FIXED; 1940 } 1941 1942 if (edid_corrupt) { 1943 /* 1944 * Unknown major version isn't corrupt but we can't use it. Only 1945 * the base block can reset edid_corrupt to false. 1946 */ 1947 if (is_base_block && 1948 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 1949 *edid_corrupt = false; 1950 else if (status != EDID_BLOCK_OK) 1951 *edid_corrupt = true; 1952 } 1953 1954 edid_block_status_print(status, block, block_num); 1955 1956 /* Determine whether we can use this block with this status. */ 1957 valid = edid_block_status_valid(status, edid_block_tag(block)); 1958 1959 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 1960 pr_notice("Raw EDID:\n"); 1961 edid_block_dump(KERN_NOTICE, block, block_num); 1962 } 1963 1964 return valid; 1965 } 1966 EXPORT_SYMBOL(drm_edid_block_valid); 1967 1968 /** 1969 * drm_edid_is_valid - sanity check EDID data 1970 * @edid: EDID data 1971 * 1972 * Sanity-check an entire EDID record (including extensions) 1973 * 1974 * Return: True if the EDID data is valid, false otherwise. 1975 */ 1976 bool drm_edid_is_valid(struct edid *edid) 1977 { 1978 int i; 1979 1980 if (!edid) 1981 return false; 1982 1983 for (i = 0; i < edid_block_count(edid); i++) { 1984 void *block = (void *)edid_block_data(edid, i); 1985 1986 if (!drm_edid_block_valid(block, i, true, NULL)) 1987 return false; 1988 } 1989 1990 return true; 1991 } 1992 EXPORT_SYMBOL(drm_edid_is_valid); 1993 1994 static struct edid *edid_filter_invalid_blocks(const struct edid *edid, 1995 int invalid_blocks) 1996 { 1997 struct edid *new, *dest_block; 1998 int valid_extensions = edid->extensions - invalid_blocks; 1999 int i; 2000 2001 new = kmalloc(edid_size_by_blocks(valid_extensions + 1), GFP_KERNEL); 2002 if (!new) 2003 goto out; 2004 2005 dest_block = new; 2006 for (i = 0; i < edid_block_count(edid); i++) { 2007 const void *block = edid_block_data(edid, i); 2008 2009 if (edid_block_valid(block, i == 0)) 2010 memcpy(dest_block++, block, EDID_LENGTH); 2011 } 2012 2013 new->extensions = valid_extensions; 2014 new->checksum = edid_block_compute_checksum(new); 2015 2016 out: 2017 kfree(edid); 2018 2019 return new; 2020 } 2021 2022 #define DDC_SEGMENT_ADDR 0x30 2023 /** 2024 * drm_do_probe_ddc_edid() - get EDID information via I2C 2025 * @data: I2C device adapter 2026 * @buf: EDID data buffer to be filled 2027 * @block: 128 byte EDID block to start fetching from 2028 * @len: EDID data buffer length to fetch 2029 * 2030 * Try to fetch EDID information by calling I2C driver functions. 2031 * 2032 * Return: 0 on success or -1 on failure. 2033 */ 2034 static int 2035 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2036 { 2037 struct i2c_adapter *adapter = data; 2038 unsigned char start = block * EDID_LENGTH; 2039 unsigned char segment = block >> 1; 2040 unsigned char xfers = segment ? 3 : 2; 2041 int ret, retries = 5; 2042 2043 /* 2044 * The core I2C driver will automatically retry the transfer if the 2045 * adapter reports EAGAIN. However, we find that bit-banging transfers 2046 * are susceptible to errors under a heavily loaded machine and 2047 * generate spurious NAKs and timeouts. Retrying the transfer 2048 * of the individual block a few times seems to overcome this. 2049 */ 2050 do { 2051 struct i2c_msg msgs[] = { 2052 { 2053 .addr = DDC_SEGMENT_ADDR, 2054 .flags = 0, 2055 .len = 1, 2056 .buf = &segment, 2057 }, { 2058 .addr = DDC_ADDR, 2059 .flags = 0, 2060 .len = 1, 2061 .buf = &start, 2062 }, { 2063 .addr = DDC_ADDR, 2064 .flags = I2C_M_RD, 2065 .len = len, 2066 .buf = buf, 2067 } 2068 }; 2069 2070 /* 2071 * Avoid sending the segment addr to not upset non-compliant 2072 * DDC monitors. 2073 */ 2074 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2075 2076 if (ret == -ENXIO) { 2077 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2078 adapter->name); 2079 break; 2080 } 2081 } while (ret != xfers && --retries); 2082 2083 return ret == xfers ? 0 : -1; 2084 } 2085 2086 static void connector_bad_edid(struct drm_connector *connector, 2087 const struct edid *edid, int num_blocks) 2088 { 2089 int i; 2090 u8 last_block; 2091 2092 /* 2093 * 0x7e in the EDID is the number of extension blocks. The EDID 2094 * is 1 (base block) + num_ext_blocks big. That means we can think 2095 * of 0x7e in the EDID of the _index_ of the last block in the 2096 * combined chunk of memory. 2097 */ 2098 last_block = edid->extensions; 2099 2100 /* Calculate real checksum for the last edid extension block data */ 2101 if (last_block < num_blocks) 2102 connector->real_edid_checksum = 2103 edid_block_compute_checksum(edid + last_block); 2104 2105 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2106 return; 2107 2108 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 2109 for (i = 0; i < num_blocks; i++) 2110 edid_block_dump(KERN_DEBUG, edid + i, i); 2111 } 2112 2113 /* Get override or firmware EDID */ 2114 static struct edid *drm_get_override_edid(struct drm_connector *connector) 2115 { 2116 struct edid *override = NULL; 2117 2118 if (connector->override_edid) 2119 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 2120 2121 if (!override) 2122 override = drm_load_edid_firmware(connector); 2123 2124 return IS_ERR(override) ? NULL : override; 2125 } 2126 2127 /** 2128 * drm_add_override_edid_modes - add modes from override/firmware EDID 2129 * @connector: connector we're probing 2130 * 2131 * Add modes from the override/firmware EDID, if available. Only to be used from 2132 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2133 * failed during drm_get_edid() and caused the override/firmware EDID to be 2134 * skipped. 2135 * 2136 * Return: The number of modes added or 0 if we couldn't find any. 2137 */ 2138 int drm_add_override_edid_modes(struct drm_connector *connector) 2139 { 2140 struct edid *override; 2141 int num_modes = 0; 2142 2143 override = drm_get_override_edid(connector); 2144 if (override) { 2145 drm_connector_update_edid_property(connector, override); 2146 num_modes = drm_add_edid_modes(connector, override); 2147 kfree(override); 2148 2149 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2150 connector->base.id, connector->name, num_modes); 2151 } 2152 2153 return num_modes; 2154 } 2155 EXPORT_SYMBOL(drm_add_override_edid_modes); 2156 2157 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2158 2159 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2160 read_block_fn read_block, 2161 void *context) 2162 { 2163 enum edid_block_status status; 2164 bool is_base_block = block_num == 0; 2165 int try; 2166 2167 for (try = 0; try < 4; try++) { 2168 if (read_block(context, block, block_num, EDID_LENGTH)) 2169 return EDID_BLOCK_READ_FAIL; 2170 2171 status = edid_block_check(block, is_base_block); 2172 if (status == EDID_BLOCK_HEADER_REPAIR) { 2173 edid_header_fix(block); 2174 2175 /* Retry with fixed header, update status if that worked. */ 2176 status = edid_block_check(block, is_base_block); 2177 if (status == EDID_BLOCK_OK) 2178 status = EDID_BLOCK_HEADER_FIXED; 2179 } 2180 2181 if (edid_block_status_valid(status, edid_block_tag(block))) 2182 break; 2183 2184 /* Fail early for unrepairable base block all zeros. */ 2185 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2186 break; 2187 } 2188 2189 return status; 2190 } 2191 2192 /** 2193 * drm_do_get_edid - get EDID data using a custom EDID block read function 2194 * @connector: connector we're probing 2195 * @read_block: EDID block read function 2196 * @context: private data passed to the block read function 2197 * 2198 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2199 * exposes a different interface to read EDID blocks this function can be used 2200 * to get EDID data using a custom block read function. 2201 * 2202 * As in the general case the DDC bus is accessible by the kernel at the I2C 2203 * level, drivers must make all reasonable efforts to expose it as an I2C 2204 * adapter and use drm_get_edid() instead of abusing this function. 2205 * 2206 * The EDID may be overridden using debugfs override_edid or firmware EDID 2207 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2208 * order. Having either of them bypasses actual EDID reads. 2209 * 2210 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2211 */ 2212 struct edid *drm_do_get_edid(struct drm_connector *connector, 2213 read_block_fn read_block, 2214 void *context) 2215 { 2216 enum edid_block_status status; 2217 int i, invalid_blocks = 0; 2218 struct edid *edid, *new; 2219 2220 edid = drm_get_override_edid(connector); 2221 if (edid) 2222 goto ok; 2223 2224 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 2225 if (!edid) 2226 return NULL; 2227 2228 status = edid_block_read(edid, 0, read_block, context); 2229 2230 edid_block_status_print(status, edid, 0); 2231 2232 if (status == EDID_BLOCK_READ_FAIL) 2233 goto fail; 2234 2235 /* FIXME: Clarify what a corrupt EDID actually means. */ 2236 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2237 connector->edid_corrupt = false; 2238 else 2239 connector->edid_corrupt = true; 2240 2241 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2242 if (status == EDID_BLOCK_ZERO) 2243 connector->null_edid_counter++; 2244 2245 connector_bad_edid(connector, edid, 1); 2246 goto fail; 2247 } 2248 2249 if (!edid_extension_block_count(edid)) 2250 goto ok; 2251 2252 new = krealloc(edid, edid_size(edid), GFP_KERNEL); 2253 if (!new) 2254 goto fail; 2255 edid = new; 2256 2257 for (i = 1; i < edid_block_count(edid); i++) { 2258 void *block = (void *)edid_block_data(edid, i); 2259 2260 status = edid_block_read(block, i, read_block, context); 2261 2262 edid_block_status_print(status, block, i); 2263 2264 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2265 if (status == EDID_BLOCK_READ_FAIL) 2266 goto fail; 2267 invalid_blocks++; 2268 } 2269 } 2270 2271 if (invalid_blocks) { 2272 connector_bad_edid(connector, edid, edid_block_count(edid)); 2273 2274 edid = edid_filter_invalid_blocks(edid, invalid_blocks); 2275 } 2276 2277 ok: 2278 return edid; 2279 2280 fail: 2281 kfree(edid); 2282 return NULL; 2283 } 2284 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2285 2286 /** 2287 * drm_probe_ddc() - probe DDC presence 2288 * @adapter: I2C adapter to probe 2289 * 2290 * Return: True on success, false on failure. 2291 */ 2292 bool 2293 drm_probe_ddc(struct i2c_adapter *adapter) 2294 { 2295 unsigned char out; 2296 2297 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2298 } 2299 EXPORT_SYMBOL(drm_probe_ddc); 2300 2301 /** 2302 * drm_get_edid - get EDID data, if available 2303 * @connector: connector we're probing 2304 * @adapter: I2C adapter to use for DDC 2305 * 2306 * Poke the given I2C channel to grab EDID data if possible. If found, 2307 * attach it to the connector. 2308 * 2309 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2310 */ 2311 struct edid *drm_get_edid(struct drm_connector *connector, 2312 struct i2c_adapter *adapter) 2313 { 2314 struct edid *edid; 2315 2316 if (connector->force == DRM_FORCE_OFF) 2317 return NULL; 2318 2319 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2320 return NULL; 2321 2322 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2323 drm_connector_update_edid_property(connector, edid); 2324 return edid; 2325 } 2326 EXPORT_SYMBOL(drm_get_edid); 2327 2328 static u32 edid_extract_panel_id(const struct edid *edid) 2329 { 2330 /* 2331 * We represent the ID as a 32-bit number so it can easily be compared 2332 * with "==". 2333 * 2334 * NOTE that we deal with endianness differently for the top half 2335 * of this ID than for the bottom half. The bottom half (the product 2336 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2337 * that's how everyone seems to interpret it. The top half (the mfg_id) 2338 * gets stored as big endian because that makes 2339 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2340 * to write (it's easier to extract the ASCII). It doesn't really 2341 * matter, though, as long as the number here is unique. 2342 */ 2343 return (u32)edid->mfg_id[0] << 24 | 2344 (u32)edid->mfg_id[1] << 16 | 2345 (u32)EDID_PRODUCT_ID(edid); 2346 } 2347 2348 /** 2349 * drm_edid_get_panel_id - Get a panel's ID through DDC 2350 * @adapter: I2C adapter to use for DDC 2351 * 2352 * This function reads the first block of the EDID of a panel and (assuming 2353 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2354 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2355 * supposed to be different for each different modem of panel. 2356 * 2357 * This function is intended to be used during early probing on devices where 2358 * more than one panel might be present. Because of its intended use it must 2359 * assume that the EDID of the panel is correct, at least as far as the ID 2360 * is concerned (in other words, we don't process any overrides here). 2361 * 2362 * NOTE: it's expected that this function and drm_do_get_edid() will both 2363 * be read the EDID, but there is no caching between them. Since we're only 2364 * reading the first block, hopefully this extra overhead won't be too big. 2365 * 2366 * Return: A 32-bit ID that should be different for each make/model of panel. 2367 * See the functions drm_edid_encode_panel_id() and 2368 * drm_edid_decode_panel_id() for some details on the structure of this 2369 * ID. 2370 */ 2371 2372 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2373 { 2374 enum edid_block_status status; 2375 void *base_block; 2376 u32 panel_id = 0; 2377 2378 /* 2379 * There are no manufacturer IDs of 0, so if there is a problem reading 2380 * the EDID then we'll just return 0. 2381 */ 2382 2383 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); 2384 if (!base_block) 2385 return 0; 2386 2387 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2388 2389 edid_block_status_print(status, base_block, 0); 2390 2391 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2392 panel_id = edid_extract_panel_id(base_block); 2393 2394 kfree(base_block); 2395 2396 return panel_id; 2397 } 2398 EXPORT_SYMBOL(drm_edid_get_panel_id); 2399 2400 /** 2401 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2402 * @connector: connector we're probing 2403 * @adapter: I2C adapter to use for DDC 2404 * 2405 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2406 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2407 * switch DDC to the GPU which is retrieving EDID. 2408 * 2409 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2410 */ 2411 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2412 struct i2c_adapter *adapter) 2413 { 2414 struct drm_device *dev = connector->dev; 2415 struct pci_dev *pdev = to_pci_dev(dev->dev); 2416 struct edid *edid; 2417 2418 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2419 return NULL; 2420 2421 vga_switcheroo_lock_ddc(pdev); 2422 edid = drm_get_edid(connector, adapter); 2423 vga_switcheroo_unlock_ddc(pdev); 2424 2425 return edid; 2426 } 2427 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2428 2429 /** 2430 * drm_edid_duplicate - duplicate an EDID and the extensions 2431 * @edid: EDID to duplicate 2432 * 2433 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2434 */ 2435 struct edid *drm_edid_duplicate(const struct edid *edid) 2436 { 2437 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2438 } 2439 EXPORT_SYMBOL(drm_edid_duplicate); 2440 2441 /*** EDID parsing ***/ 2442 2443 /** 2444 * edid_get_quirks - return quirk flags for a given EDID 2445 * @drm_edid: EDID to process 2446 * 2447 * This tells subsequent routines what fixes they need to apply. 2448 */ 2449 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2450 { 2451 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2452 const struct edid_quirk *quirk; 2453 int i; 2454 2455 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2456 quirk = &edid_quirk_list[i]; 2457 if (quirk->panel_id == panel_id) 2458 return quirk->quirks; 2459 } 2460 2461 return 0; 2462 } 2463 2464 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2465 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2466 2467 /* 2468 * Walk the mode list for connector, clearing the preferred status on existing 2469 * modes and setting it anew for the right mode ala quirks. 2470 */ 2471 static void edid_fixup_preferred(struct drm_connector *connector, 2472 u32 quirks) 2473 { 2474 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2475 int target_refresh = 0; 2476 int cur_vrefresh, preferred_vrefresh; 2477 2478 if (list_empty(&connector->probed_modes)) 2479 return; 2480 2481 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2482 target_refresh = 60; 2483 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2484 target_refresh = 75; 2485 2486 preferred_mode = list_first_entry(&connector->probed_modes, 2487 struct drm_display_mode, head); 2488 2489 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2490 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2491 2492 if (cur_mode == preferred_mode) 2493 continue; 2494 2495 /* Largest mode is preferred */ 2496 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2497 preferred_mode = cur_mode; 2498 2499 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2500 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2501 /* At a given size, try to get closest to target refresh */ 2502 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2503 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2504 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2505 preferred_mode = cur_mode; 2506 } 2507 } 2508 2509 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2510 } 2511 2512 static bool 2513 mode_is_rb(const struct drm_display_mode *mode) 2514 { 2515 return (mode->htotal - mode->hdisplay == 160) && 2516 (mode->hsync_end - mode->hdisplay == 80) && 2517 (mode->hsync_end - mode->hsync_start == 32) && 2518 (mode->vsync_start - mode->vdisplay == 3); 2519 } 2520 2521 /* 2522 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2523 * @dev: Device to duplicate against 2524 * @hsize: Mode width 2525 * @vsize: Mode height 2526 * @fresh: Mode refresh rate 2527 * @rb: Mode reduced-blanking-ness 2528 * 2529 * Walk the DMT mode list looking for a match for the given parameters. 2530 * 2531 * Return: A newly allocated copy of the mode, or NULL if not found. 2532 */ 2533 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2534 int hsize, int vsize, int fresh, 2535 bool rb) 2536 { 2537 int i; 2538 2539 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2540 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2541 2542 if (hsize != ptr->hdisplay) 2543 continue; 2544 if (vsize != ptr->vdisplay) 2545 continue; 2546 if (fresh != drm_mode_vrefresh(ptr)) 2547 continue; 2548 if (rb != mode_is_rb(ptr)) 2549 continue; 2550 2551 return drm_mode_duplicate(dev, ptr); 2552 } 2553 2554 return NULL; 2555 } 2556 EXPORT_SYMBOL(drm_mode_find_dmt); 2557 2558 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2559 { 2560 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2561 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2562 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2563 2564 return descriptor->pixel_clock == 0 && 2565 descriptor->data.other_data.pad1 == 0 && 2566 descriptor->data.other_data.type == type; 2567 } 2568 2569 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2570 { 2571 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2572 2573 return descriptor->pixel_clock != 0; 2574 } 2575 2576 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2577 2578 static void 2579 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2580 { 2581 int i, n; 2582 u8 d = ext[0x02]; 2583 const u8 *det_base = ext + d; 2584 2585 if (d < 4 || d > 127) 2586 return; 2587 2588 n = (127 - d) / 18; 2589 for (i = 0; i < n; i++) 2590 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2591 } 2592 2593 static void 2594 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2595 { 2596 unsigned int i, n = min((int)ext[0x02], 6); 2597 const u8 *det_base = ext + 5; 2598 2599 if (ext[0x01] != 1) 2600 return; /* unknown version */ 2601 2602 for (i = 0; i < n; i++) 2603 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2604 } 2605 2606 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 2607 detailed_cb *cb, void *closure) 2608 { 2609 struct drm_edid_iter edid_iter; 2610 const u8 *ext; 2611 int i; 2612 2613 if (!drm_edid) 2614 return; 2615 2616 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2617 cb(&drm_edid->edid->detailed_timings[i], closure); 2618 2619 drm_edid_iter_begin(drm_edid, &edid_iter); 2620 drm_edid_iter_for_each(ext, &edid_iter) { 2621 switch (*ext) { 2622 case CEA_EXT: 2623 cea_for_each_detailed_block(ext, cb, closure); 2624 break; 2625 case VTB_EXT: 2626 vtb_for_each_detailed_block(ext, cb, closure); 2627 break; 2628 default: 2629 break; 2630 } 2631 } 2632 drm_edid_iter_end(&edid_iter); 2633 } 2634 2635 static void 2636 is_rb(const struct detailed_timing *descriptor, void *data) 2637 { 2638 bool *res = data; 2639 2640 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2641 return; 2642 2643 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2644 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 2645 2646 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 2647 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) 2648 *res = true; 2649 } 2650 2651 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2652 static bool 2653 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 2654 { 2655 if (drm_edid->edid->revision >= 4) { 2656 bool ret = false; 2657 2658 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 2659 return ret; 2660 } 2661 2662 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2663 } 2664 2665 static void 2666 find_gtf2(const struct detailed_timing *descriptor, void *data) 2667 { 2668 const struct detailed_timing **res = data; 2669 2670 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2671 return; 2672 2673 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2674 2675 if (descriptor->data.other_data.data.range.flags == 0x02) 2676 *res = descriptor; 2677 } 2678 2679 /* Secondary GTF curve kicks in above some break frequency */ 2680 static int 2681 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 2682 { 2683 const struct detailed_timing *descriptor = NULL; 2684 2685 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2686 2687 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 2688 2689 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 2690 } 2691 2692 static int 2693 drm_gtf2_2c(const struct drm_edid *drm_edid) 2694 { 2695 const struct detailed_timing *descriptor = NULL; 2696 2697 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2698 2699 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 2700 2701 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 2702 } 2703 2704 static int 2705 drm_gtf2_m(const struct drm_edid *drm_edid) 2706 { 2707 const struct detailed_timing *descriptor = NULL; 2708 2709 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2710 2711 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 2712 2713 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 2714 } 2715 2716 static int 2717 drm_gtf2_k(const struct drm_edid *drm_edid) 2718 { 2719 const struct detailed_timing *descriptor = NULL; 2720 2721 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2722 2723 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 2724 2725 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 2726 } 2727 2728 static int 2729 drm_gtf2_2j(const struct drm_edid *drm_edid) 2730 { 2731 const struct detailed_timing *descriptor = NULL; 2732 2733 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 2734 2735 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 2736 2737 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 2738 } 2739 2740 /* Get standard timing level (CVT/GTF/DMT). */ 2741 static int standard_timing_level(const struct drm_edid *drm_edid) 2742 { 2743 const struct edid *edid = drm_edid->edid; 2744 2745 if (edid->revision >= 2) { 2746 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2747 return LEVEL_CVT; 2748 if (drm_gtf2_hbreak(drm_edid)) 2749 return LEVEL_GTF2; 2750 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2751 return LEVEL_GTF; 2752 } 2753 return LEVEL_DMT; 2754 } 2755 2756 /* 2757 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2758 * monitors fill with ascii space (0x20) instead. 2759 */ 2760 static int 2761 bad_std_timing(u8 a, u8 b) 2762 { 2763 return (a == 0x00 && b == 0x00) || 2764 (a == 0x01 && b == 0x01) || 2765 (a == 0x20 && b == 0x20); 2766 } 2767 2768 static int drm_mode_hsync(const struct drm_display_mode *mode) 2769 { 2770 if (mode->htotal <= 0) 2771 return 0; 2772 2773 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2774 } 2775 2776 /* 2777 * Take the standard timing params (in this case width, aspect, and refresh) 2778 * and convert them into a real mode using CVT/GTF/DMT. 2779 */ 2780 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 2781 const struct drm_edid *drm_edid, 2782 const struct std_timing *t) 2783 { 2784 struct drm_device *dev = connector->dev; 2785 struct drm_display_mode *m, *mode = NULL; 2786 int hsize, vsize; 2787 int vrefresh_rate; 2788 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2789 >> EDID_TIMING_ASPECT_SHIFT; 2790 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2791 >> EDID_TIMING_VFREQ_SHIFT; 2792 int timing_level = standard_timing_level(drm_edid); 2793 2794 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2795 return NULL; 2796 2797 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2798 hsize = t->hsize * 8 + 248; 2799 /* vrefresh_rate = vfreq + 60 */ 2800 vrefresh_rate = vfreq + 60; 2801 /* the vdisplay is calculated based on the aspect ratio */ 2802 if (aspect_ratio == 0) { 2803 if (drm_edid->edid->revision < 3) 2804 vsize = hsize; 2805 else 2806 vsize = (hsize * 10) / 16; 2807 } else if (aspect_ratio == 1) 2808 vsize = (hsize * 3) / 4; 2809 else if (aspect_ratio == 2) 2810 vsize = (hsize * 4) / 5; 2811 else 2812 vsize = (hsize * 9) / 16; 2813 2814 /* HDTV hack, part 1 */ 2815 if (vrefresh_rate == 60 && 2816 ((hsize == 1360 && vsize == 765) || 2817 (hsize == 1368 && vsize == 769))) { 2818 hsize = 1366; 2819 vsize = 768; 2820 } 2821 2822 /* 2823 * If this connector already has a mode for this size and refresh 2824 * rate (because it came from detailed or CVT info), use that 2825 * instead. This way we don't have to guess at interlace or 2826 * reduced blanking. 2827 */ 2828 list_for_each_entry(m, &connector->probed_modes, head) 2829 if (m->hdisplay == hsize && m->vdisplay == vsize && 2830 drm_mode_vrefresh(m) == vrefresh_rate) 2831 return NULL; 2832 2833 /* HDTV hack, part 2 */ 2834 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2835 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2836 false); 2837 if (!mode) 2838 return NULL; 2839 mode->hdisplay = 1366; 2840 mode->hsync_start = mode->hsync_start - 1; 2841 mode->hsync_end = mode->hsync_end - 1; 2842 return mode; 2843 } 2844 2845 /* check whether it can be found in default mode table */ 2846 if (drm_monitor_supports_rb(drm_edid)) { 2847 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2848 true); 2849 if (mode) 2850 return mode; 2851 } 2852 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2853 if (mode) 2854 return mode; 2855 2856 /* okay, generate it */ 2857 switch (timing_level) { 2858 case LEVEL_DMT: 2859 break; 2860 case LEVEL_GTF: 2861 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2862 break; 2863 case LEVEL_GTF2: 2864 /* 2865 * This is potentially wrong if there's ever a monitor with 2866 * more than one ranges section, each claiming a different 2867 * secondary GTF curve. Please don't do that. 2868 */ 2869 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2870 if (!mode) 2871 return NULL; 2872 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 2873 drm_mode_destroy(dev, mode); 2874 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2875 vrefresh_rate, 0, 0, 2876 drm_gtf2_m(drm_edid), 2877 drm_gtf2_2c(drm_edid), 2878 drm_gtf2_k(drm_edid), 2879 drm_gtf2_2j(drm_edid)); 2880 } 2881 break; 2882 case LEVEL_CVT: 2883 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2884 false); 2885 break; 2886 } 2887 return mode; 2888 } 2889 2890 /* 2891 * EDID is delightfully ambiguous about how interlaced modes are to be 2892 * encoded. Our internal representation is of frame height, but some 2893 * HDTV detailed timings are encoded as field height. 2894 * 2895 * The format list here is from CEA, in frame size. Technically we 2896 * should be checking refresh rate too. Whatever. 2897 */ 2898 static void 2899 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2900 const struct detailed_pixel_timing *pt) 2901 { 2902 int i; 2903 static const struct { 2904 int w, h; 2905 } cea_interlaced[] = { 2906 { 1920, 1080 }, 2907 { 720, 480 }, 2908 { 1440, 480 }, 2909 { 2880, 480 }, 2910 { 720, 576 }, 2911 { 1440, 576 }, 2912 { 2880, 576 }, 2913 }; 2914 2915 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2916 return; 2917 2918 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2919 if ((mode->hdisplay == cea_interlaced[i].w) && 2920 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2921 mode->vdisplay *= 2; 2922 mode->vsync_start *= 2; 2923 mode->vsync_end *= 2; 2924 mode->vtotal *= 2; 2925 mode->vtotal |= 1; 2926 } 2927 } 2928 2929 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2930 } 2931 2932 /* 2933 * Create a new mode from an EDID detailed timing section. An EDID detailed 2934 * timing block contains enough info for us to create and return a new struct 2935 * drm_display_mode. 2936 */ 2937 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2938 const struct drm_edid *drm_edid, 2939 const struct detailed_timing *timing, 2940 u32 quirks) 2941 { 2942 struct drm_display_mode *mode; 2943 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2944 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2945 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2946 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2947 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2948 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2949 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2950 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2951 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2952 2953 /* ignore tiny modes */ 2954 if (hactive < 64 || vactive < 64) 2955 return NULL; 2956 2957 if (pt->misc & DRM_EDID_PT_STEREO) { 2958 DRM_DEBUG_KMS("stereo mode not supported\n"); 2959 return NULL; 2960 } 2961 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2962 DRM_DEBUG_KMS("composite sync not supported\n"); 2963 } 2964 2965 /* it is incorrect if hsync/vsync width is zero */ 2966 if (!hsync_pulse_width || !vsync_pulse_width) { 2967 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2968 "Wrong Hsync/Vsync pulse width\n"); 2969 return NULL; 2970 } 2971 2972 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2973 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2974 if (!mode) 2975 return NULL; 2976 2977 goto set_size; 2978 } 2979 2980 mode = drm_mode_create(dev); 2981 if (!mode) 2982 return NULL; 2983 2984 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2985 mode->clock = 1088 * 10; 2986 else 2987 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2988 2989 mode->hdisplay = hactive; 2990 mode->hsync_start = mode->hdisplay + hsync_offset; 2991 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2992 mode->htotal = mode->hdisplay + hblank; 2993 2994 mode->vdisplay = vactive; 2995 mode->vsync_start = mode->vdisplay + vsync_offset; 2996 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2997 mode->vtotal = mode->vdisplay + vblank; 2998 2999 /* Some EDIDs have bogus h/vtotal values */ 3000 if (mode->hsync_end > mode->htotal) 3001 mode->htotal = mode->hsync_end + 1; 3002 if (mode->vsync_end > mode->vtotal) 3003 mode->vtotal = mode->vsync_end + 1; 3004 3005 drm_mode_do_interlace_quirk(mode, pt); 3006 3007 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3008 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3009 } else { 3010 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3011 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3012 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3013 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3014 } 3015 3016 set_size: 3017 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3018 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3019 3020 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 3021 mode->width_mm *= 10; 3022 mode->height_mm *= 10; 3023 } 3024 3025 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3026 mode->width_mm = drm_edid->edid->width_cm * 10; 3027 mode->height_mm = drm_edid->edid->height_cm * 10; 3028 } 3029 3030 mode->type = DRM_MODE_TYPE_DRIVER; 3031 drm_mode_set_name(mode); 3032 3033 return mode; 3034 } 3035 3036 static bool 3037 mode_in_hsync_range(const struct drm_display_mode *mode, 3038 const struct edid *edid, const u8 *t) 3039 { 3040 int hsync, hmin, hmax; 3041 3042 hmin = t[7]; 3043 if (edid->revision >= 4) 3044 hmin += ((t[4] & 0x04) ? 255 : 0); 3045 hmax = t[8]; 3046 if (edid->revision >= 4) 3047 hmax += ((t[4] & 0x08) ? 255 : 0); 3048 hsync = drm_mode_hsync(mode); 3049 3050 return (hsync <= hmax && hsync >= hmin); 3051 } 3052 3053 static bool 3054 mode_in_vsync_range(const struct drm_display_mode *mode, 3055 const struct edid *edid, const u8 *t) 3056 { 3057 int vsync, vmin, vmax; 3058 3059 vmin = t[5]; 3060 if (edid->revision >= 4) 3061 vmin += ((t[4] & 0x01) ? 255 : 0); 3062 vmax = t[6]; 3063 if (edid->revision >= 4) 3064 vmax += ((t[4] & 0x02) ? 255 : 0); 3065 vsync = drm_mode_vrefresh(mode); 3066 3067 return (vsync <= vmax && vsync >= vmin); 3068 } 3069 3070 static u32 3071 range_pixel_clock(const struct edid *edid, const u8 *t) 3072 { 3073 /* unspecified */ 3074 if (t[9] == 0 || t[9] == 255) 3075 return 0; 3076 3077 /* 1.4 with CVT support gives us real precision, yay */ 3078 if (edid->revision >= 4 && t[10] == 0x04) 3079 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3080 3081 /* 1.3 is pathetic, so fuzz up a bit */ 3082 return t[9] * 10000 + 5001; 3083 } 3084 3085 static bool mode_in_range(const struct drm_display_mode *mode, 3086 const struct drm_edid *drm_edid, 3087 const struct detailed_timing *timing) 3088 { 3089 const struct edid *edid = drm_edid->edid; 3090 u32 max_clock; 3091 const u8 *t = (const u8 *)timing; 3092 3093 if (!mode_in_hsync_range(mode, edid, t)) 3094 return false; 3095 3096 if (!mode_in_vsync_range(mode, edid, t)) 3097 return false; 3098 3099 if ((max_clock = range_pixel_clock(edid, t))) 3100 if (mode->clock > max_clock) 3101 return false; 3102 3103 /* 1.4 max horizontal check */ 3104 if (edid->revision >= 4 && t[10] == 0x04) 3105 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3106 return false; 3107 3108 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3109 return false; 3110 3111 return true; 3112 } 3113 3114 static bool valid_inferred_mode(const struct drm_connector *connector, 3115 const struct drm_display_mode *mode) 3116 { 3117 const struct drm_display_mode *m; 3118 bool ok = false; 3119 3120 list_for_each_entry(m, &connector->probed_modes, head) { 3121 if (mode->hdisplay == m->hdisplay && 3122 mode->vdisplay == m->vdisplay && 3123 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3124 return false; /* duplicated */ 3125 if (mode->hdisplay <= m->hdisplay && 3126 mode->vdisplay <= m->vdisplay) 3127 ok = true; 3128 } 3129 return ok; 3130 } 3131 3132 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3133 const struct drm_edid *drm_edid, 3134 const struct detailed_timing *timing) 3135 { 3136 int i, modes = 0; 3137 struct drm_display_mode *newmode; 3138 struct drm_device *dev = connector->dev; 3139 3140 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3141 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3142 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3143 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3144 if (newmode) { 3145 drm_mode_probed_add(connector, newmode); 3146 modes++; 3147 } 3148 } 3149 } 3150 3151 return modes; 3152 } 3153 3154 /* fix up 1366x768 mode from 1368x768; 3155 * GFT/CVT can't express 1366 width which isn't dividable by 8 3156 */ 3157 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3158 { 3159 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3160 mode->hdisplay = 1366; 3161 mode->hsync_start--; 3162 mode->hsync_end--; 3163 drm_mode_set_name(mode); 3164 } 3165 } 3166 3167 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3168 const struct drm_edid *drm_edid, 3169 const struct detailed_timing *timing) 3170 { 3171 int i, modes = 0; 3172 struct drm_display_mode *newmode; 3173 struct drm_device *dev = connector->dev; 3174 3175 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3176 const struct minimode *m = &extra_modes[i]; 3177 3178 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3179 if (!newmode) 3180 return modes; 3181 3182 drm_mode_fixup_1366x768(newmode); 3183 if (!mode_in_range(newmode, drm_edid, timing) || 3184 !valid_inferred_mode(connector, newmode)) { 3185 drm_mode_destroy(dev, newmode); 3186 continue; 3187 } 3188 3189 drm_mode_probed_add(connector, newmode); 3190 modes++; 3191 } 3192 3193 return modes; 3194 } 3195 3196 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3197 const struct drm_edid *drm_edid, 3198 const struct detailed_timing *timing) 3199 { 3200 int i, modes = 0; 3201 struct drm_display_mode *newmode; 3202 struct drm_device *dev = connector->dev; 3203 bool rb = drm_monitor_supports_rb(drm_edid); 3204 3205 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3206 const struct minimode *m = &extra_modes[i]; 3207 3208 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3209 if (!newmode) 3210 return modes; 3211 3212 drm_mode_fixup_1366x768(newmode); 3213 if (!mode_in_range(newmode, drm_edid, timing) || 3214 !valid_inferred_mode(connector, newmode)) { 3215 drm_mode_destroy(dev, newmode); 3216 continue; 3217 } 3218 3219 drm_mode_probed_add(connector, newmode); 3220 modes++; 3221 } 3222 3223 return modes; 3224 } 3225 3226 static void 3227 do_inferred_modes(const struct detailed_timing *timing, void *c) 3228 { 3229 struct detailed_mode_closure *closure = c; 3230 const struct detailed_non_pixel *data = &timing->data.other_data; 3231 const struct detailed_data_monitor_range *range = &data->data.range; 3232 3233 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3234 return; 3235 3236 closure->modes += drm_dmt_modes_for_range(closure->connector, 3237 closure->drm_edid, 3238 timing); 3239 3240 if (!version_greater(closure->drm_edid, 1, 1)) 3241 return; /* GTF not defined yet */ 3242 3243 switch (range->flags) { 3244 case 0x02: /* secondary gtf, XXX could do more */ 3245 case 0x00: /* default gtf */ 3246 closure->modes += drm_gtf_modes_for_range(closure->connector, 3247 closure->drm_edid, 3248 timing); 3249 break; 3250 case 0x04: /* cvt, only in 1.4+ */ 3251 if (!version_greater(closure->drm_edid, 1, 3)) 3252 break; 3253 3254 closure->modes += drm_cvt_modes_for_range(closure->connector, 3255 closure->drm_edid, 3256 timing); 3257 break; 3258 case 0x01: /* just the ranges, no formula */ 3259 default: 3260 break; 3261 } 3262 } 3263 3264 static int add_inferred_modes(struct drm_connector *connector, 3265 const struct drm_edid *drm_edid) 3266 { 3267 struct detailed_mode_closure closure = { 3268 .connector = connector, 3269 .drm_edid = drm_edid, 3270 }; 3271 3272 if (version_greater(drm_edid, 1, 0)) 3273 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3274 3275 return closure.modes; 3276 } 3277 3278 static int 3279 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3280 { 3281 int i, j, m, modes = 0; 3282 struct drm_display_mode *mode; 3283 const u8 *est = ((const u8 *)timing) + 6; 3284 3285 for (i = 0; i < 6; i++) { 3286 for (j = 7; j >= 0; j--) { 3287 m = (i * 8) + (7 - j); 3288 if (m >= ARRAY_SIZE(est3_modes)) 3289 break; 3290 if (est[i] & (1 << j)) { 3291 mode = drm_mode_find_dmt(connector->dev, 3292 est3_modes[m].w, 3293 est3_modes[m].h, 3294 est3_modes[m].r, 3295 est3_modes[m].rb); 3296 if (mode) { 3297 drm_mode_probed_add(connector, mode); 3298 modes++; 3299 } 3300 } 3301 } 3302 } 3303 3304 return modes; 3305 } 3306 3307 static void 3308 do_established_modes(const struct detailed_timing *timing, void *c) 3309 { 3310 struct detailed_mode_closure *closure = c; 3311 3312 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3313 return; 3314 3315 closure->modes += drm_est3_modes(closure->connector, timing); 3316 } 3317 3318 /* 3319 * Get established modes from EDID and add them. Each EDID block contains a 3320 * bitmap of the supported "established modes" list (defined above). Tease them 3321 * out and add them to the global modes list. 3322 */ 3323 static int add_established_modes(struct drm_connector *connector, 3324 const struct drm_edid *drm_edid) 3325 { 3326 struct drm_device *dev = connector->dev; 3327 const struct edid *edid = drm_edid->edid; 3328 unsigned long est_bits = edid->established_timings.t1 | 3329 (edid->established_timings.t2 << 8) | 3330 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3331 int i, modes = 0; 3332 struct detailed_mode_closure closure = { 3333 .connector = connector, 3334 .drm_edid = drm_edid, 3335 }; 3336 3337 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3338 if (est_bits & (1<<i)) { 3339 struct drm_display_mode *newmode; 3340 3341 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3342 if (newmode) { 3343 drm_mode_probed_add(connector, newmode); 3344 modes++; 3345 } 3346 } 3347 } 3348 3349 if (version_greater(drm_edid, 1, 0)) 3350 drm_for_each_detailed_block(drm_edid, do_established_modes, 3351 &closure); 3352 3353 return modes + closure.modes; 3354 } 3355 3356 static void 3357 do_standard_modes(const struct detailed_timing *timing, void *c) 3358 { 3359 struct detailed_mode_closure *closure = c; 3360 const struct detailed_non_pixel *data = &timing->data.other_data; 3361 struct drm_connector *connector = closure->connector; 3362 int i; 3363 3364 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3365 return; 3366 3367 for (i = 0; i < 6; i++) { 3368 const struct std_timing *std = &data->data.timings[i]; 3369 struct drm_display_mode *newmode; 3370 3371 newmode = drm_mode_std(connector, closure->drm_edid, std); 3372 if (newmode) { 3373 drm_mode_probed_add(connector, newmode); 3374 closure->modes++; 3375 } 3376 } 3377 } 3378 3379 /* 3380 * Get standard modes from EDID and add them. Standard modes can be calculated 3381 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3382 * add them to the list. 3383 */ 3384 static int add_standard_modes(struct drm_connector *connector, 3385 const struct drm_edid *drm_edid) 3386 { 3387 int i, modes = 0; 3388 struct detailed_mode_closure closure = { 3389 .connector = connector, 3390 .drm_edid = drm_edid, 3391 }; 3392 3393 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3394 struct drm_display_mode *newmode; 3395 3396 newmode = drm_mode_std(connector, drm_edid, 3397 &drm_edid->edid->standard_timings[i]); 3398 if (newmode) { 3399 drm_mode_probed_add(connector, newmode); 3400 modes++; 3401 } 3402 } 3403 3404 if (version_greater(drm_edid, 1, 0)) 3405 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3406 &closure); 3407 3408 /* XXX should also look for standard codes in VTB blocks */ 3409 3410 return modes + closure.modes; 3411 } 3412 3413 static int drm_cvt_modes(struct drm_connector *connector, 3414 const struct detailed_timing *timing) 3415 { 3416 int i, j, modes = 0; 3417 struct drm_display_mode *newmode; 3418 struct drm_device *dev = connector->dev; 3419 const struct cvt_timing *cvt; 3420 const int rates[] = { 60, 85, 75, 60, 50 }; 3421 const u8 empty[3] = { 0, 0, 0 }; 3422 3423 for (i = 0; i < 4; i++) { 3424 int width, height; 3425 3426 cvt = &(timing->data.other_data.data.cvt[i]); 3427 3428 if (!memcmp(cvt->code, empty, 3)) 3429 continue; 3430 3431 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3432 switch (cvt->code[1] & 0x0c) { 3433 /* default - because compiler doesn't see that we've enumerated all cases */ 3434 default: 3435 case 0x00: 3436 width = height * 4 / 3; 3437 break; 3438 case 0x04: 3439 width = height * 16 / 9; 3440 break; 3441 case 0x08: 3442 width = height * 16 / 10; 3443 break; 3444 case 0x0c: 3445 width = height * 15 / 9; 3446 break; 3447 } 3448 3449 for (j = 1; j < 5; j++) { 3450 if (cvt->code[2] & (1 << j)) { 3451 newmode = drm_cvt_mode(dev, width, height, 3452 rates[j], j == 0, 3453 false, false); 3454 if (newmode) { 3455 drm_mode_probed_add(connector, newmode); 3456 modes++; 3457 } 3458 } 3459 } 3460 } 3461 3462 return modes; 3463 } 3464 3465 static void 3466 do_cvt_mode(const struct detailed_timing *timing, void *c) 3467 { 3468 struct detailed_mode_closure *closure = c; 3469 3470 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3471 return; 3472 3473 closure->modes += drm_cvt_modes(closure->connector, timing); 3474 } 3475 3476 static int 3477 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 3478 { 3479 struct detailed_mode_closure closure = { 3480 .connector = connector, 3481 .drm_edid = drm_edid, 3482 }; 3483 3484 if (version_greater(drm_edid, 1, 2)) 3485 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 3486 3487 /* XXX should also look for CVT codes in VTB blocks */ 3488 3489 return closure.modes; 3490 } 3491 3492 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3493 3494 static void 3495 do_detailed_mode(const struct detailed_timing *timing, void *c) 3496 { 3497 struct detailed_mode_closure *closure = c; 3498 struct drm_display_mode *newmode; 3499 3500 if (!is_detailed_timing_descriptor(timing)) 3501 return; 3502 3503 newmode = drm_mode_detailed(closure->connector->dev, 3504 closure->drm_edid, timing, 3505 closure->quirks); 3506 if (!newmode) 3507 return; 3508 3509 if (closure->preferred) 3510 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3511 3512 /* 3513 * Detailed modes are limited to 10kHz pixel clock resolution, 3514 * so fix up anything that looks like CEA/HDMI mode, but the clock 3515 * is just slightly off. 3516 */ 3517 fixup_detailed_cea_mode_clock(newmode); 3518 3519 drm_mode_probed_add(closure->connector, newmode); 3520 closure->modes++; 3521 closure->preferred = false; 3522 } 3523 3524 /* 3525 * add_detailed_modes - Add modes from detailed timings 3526 * @connector: attached connector 3527 * @drm_edid: EDID block to scan 3528 * @quirks: quirks to apply 3529 */ 3530 static int add_detailed_modes(struct drm_connector *connector, 3531 const struct drm_edid *drm_edid, u32 quirks) 3532 { 3533 struct detailed_mode_closure closure = { 3534 .connector = connector, 3535 .drm_edid = drm_edid, 3536 .preferred = true, 3537 .quirks = quirks, 3538 }; 3539 3540 if (closure.preferred && !version_greater(drm_edid, 1, 3)) 3541 closure.preferred = 3542 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3543 3544 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 3545 3546 return closure.modes; 3547 } 3548 3549 /* CTA-861-H Table 60 - CTA Tag Codes */ 3550 #define CTA_DB_AUDIO 1 3551 #define CTA_DB_VIDEO 2 3552 #define CTA_DB_VENDOR 3 3553 #define CTA_DB_SPEAKER 4 3554 #define CTA_DB_EXTENDED_TAG 7 3555 3556 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 3557 #define CTA_EXT_DB_VIDEO_CAP 0 3558 #define CTA_EXT_DB_VENDOR 1 3559 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 3560 #define CTA_EXT_DB_420_VIDEO_DATA 14 3561 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 3562 #define CTA_EXT_DB_HF_SCDB 0x79 3563 3564 #define EDID_BASIC_AUDIO (1 << 6) 3565 #define EDID_CEA_YCRCB444 (1 << 5) 3566 #define EDID_CEA_YCRCB422 (1 << 4) 3567 #define EDID_CEA_VCDB_QS (1 << 6) 3568 3569 /* 3570 * Search EDID for CEA extension block. 3571 * 3572 * FIXME: Prefer not returning pointers to raw EDID data. 3573 */ 3574 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 3575 int ext_id, int *ext_index) 3576 { 3577 const struct edid *edid = drm_edid ? drm_edid->edid : NULL; 3578 const u8 *edid_ext = NULL; 3579 int i; 3580 3581 /* No EDID or EDID extensions */ 3582 if (!edid || !edid_extension_block_count(edid)) 3583 return NULL; 3584 3585 /* Find CEA extension */ 3586 for (i = *ext_index; i < edid_extension_block_count(edid); i++) { 3587 edid_ext = edid_extension_block_data(edid, i); 3588 if (edid_block_tag(edid_ext) == ext_id) 3589 break; 3590 } 3591 3592 if (i >= edid_extension_block_count(edid)) 3593 return NULL; 3594 3595 *ext_index = i + 1; 3596 3597 return edid_ext; 3598 } 3599 3600 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 3601 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 3602 { 3603 const struct displayid_block *block; 3604 struct displayid_iter iter; 3605 int ext_index = 0; 3606 bool found = false; 3607 3608 /* Look for a top level CEA extension block */ 3609 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 3610 return true; 3611 3612 /* CEA blocks can also be found embedded in a DisplayID block */ 3613 displayid_iter_edid_begin(drm_edid, &iter); 3614 displayid_iter_for_each(block, &iter) { 3615 if (block->tag == DATA_BLOCK_CTA) { 3616 found = true; 3617 break; 3618 } 3619 } 3620 displayid_iter_end(&iter); 3621 3622 return found; 3623 } 3624 3625 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3626 { 3627 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3628 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3629 3630 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3631 return &edid_cea_modes_1[vic - 1]; 3632 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3633 return &edid_cea_modes_193[vic - 193]; 3634 return NULL; 3635 } 3636 3637 static u8 cea_num_vics(void) 3638 { 3639 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3640 } 3641 3642 static u8 cea_next_vic(u8 vic) 3643 { 3644 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3645 vic = 193; 3646 return vic; 3647 } 3648 3649 /* 3650 * Calculate the alternate clock for the CEA mode 3651 * (60Hz vs. 59.94Hz etc.) 3652 */ 3653 static unsigned int 3654 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3655 { 3656 unsigned int clock = cea_mode->clock; 3657 3658 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3659 return clock; 3660 3661 /* 3662 * edid_cea_modes contains the 59.94Hz 3663 * variant for 240 and 480 line modes, 3664 * and the 60Hz variant otherwise. 3665 */ 3666 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3667 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3668 else 3669 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3670 3671 return clock; 3672 } 3673 3674 static bool 3675 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3676 { 3677 /* 3678 * For certain VICs the spec allows the vertical 3679 * front porch to vary by one or two lines. 3680 * 3681 * cea_modes[] stores the variant with the shortest 3682 * vertical front porch. We can adjust the mode to 3683 * get the other variants by simply increasing the 3684 * vertical front porch length. 3685 */ 3686 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3687 cea_mode_for_vic(9)->vtotal != 262 || 3688 cea_mode_for_vic(12)->vtotal != 262 || 3689 cea_mode_for_vic(13)->vtotal != 262 || 3690 cea_mode_for_vic(23)->vtotal != 312 || 3691 cea_mode_for_vic(24)->vtotal != 312 || 3692 cea_mode_for_vic(27)->vtotal != 312 || 3693 cea_mode_for_vic(28)->vtotal != 312); 3694 3695 if (((vic == 8 || vic == 9 || 3696 vic == 12 || vic == 13) && mode->vtotal < 263) || 3697 ((vic == 23 || vic == 24 || 3698 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3699 mode->vsync_start++; 3700 mode->vsync_end++; 3701 mode->vtotal++; 3702 3703 return true; 3704 } 3705 3706 return false; 3707 } 3708 3709 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3710 unsigned int clock_tolerance) 3711 { 3712 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3713 u8 vic; 3714 3715 if (!to_match->clock) 3716 return 0; 3717 3718 if (to_match->picture_aspect_ratio) 3719 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3720 3721 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3722 struct drm_display_mode cea_mode; 3723 unsigned int clock1, clock2; 3724 3725 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 3726 3727 /* Check both 60Hz and 59.94Hz */ 3728 clock1 = cea_mode.clock; 3729 clock2 = cea_mode_alternate_clock(&cea_mode); 3730 3731 if (abs(to_match->clock - clock1) > clock_tolerance && 3732 abs(to_match->clock - clock2) > clock_tolerance) 3733 continue; 3734 3735 do { 3736 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3737 return vic; 3738 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3739 } 3740 3741 return 0; 3742 } 3743 3744 /** 3745 * drm_match_cea_mode - look for a CEA mode matching given mode 3746 * @to_match: display mode 3747 * 3748 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3749 * mode. 3750 */ 3751 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3752 { 3753 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3754 u8 vic; 3755 3756 if (!to_match->clock) 3757 return 0; 3758 3759 if (to_match->picture_aspect_ratio) 3760 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3761 3762 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3763 struct drm_display_mode cea_mode; 3764 unsigned int clock1, clock2; 3765 3766 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 3767 3768 /* Check both 60Hz and 59.94Hz */ 3769 clock1 = cea_mode.clock; 3770 clock2 = cea_mode_alternate_clock(&cea_mode); 3771 3772 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3773 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3774 continue; 3775 3776 do { 3777 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3778 return vic; 3779 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3780 } 3781 3782 return 0; 3783 } 3784 EXPORT_SYMBOL(drm_match_cea_mode); 3785 3786 static bool drm_valid_cea_vic(u8 vic) 3787 { 3788 return cea_mode_for_vic(vic) != NULL; 3789 } 3790 3791 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3792 { 3793 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3794 3795 if (mode) 3796 return mode->picture_aspect_ratio; 3797 3798 return HDMI_PICTURE_ASPECT_NONE; 3799 } 3800 3801 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3802 { 3803 return edid_4k_modes[video_code].picture_aspect_ratio; 3804 } 3805 3806 /* 3807 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3808 * specific block). 3809 */ 3810 static unsigned int 3811 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3812 { 3813 return cea_mode_alternate_clock(hdmi_mode); 3814 } 3815 3816 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3817 unsigned int clock_tolerance) 3818 { 3819 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3820 u8 vic; 3821 3822 if (!to_match->clock) 3823 return 0; 3824 3825 if (to_match->picture_aspect_ratio) 3826 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3827 3828 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3829 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3830 unsigned int clock1, clock2; 3831 3832 /* Make sure to also match alternate clocks */ 3833 clock1 = hdmi_mode->clock; 3834 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3835 3836 if (abs(to_match->clock - clock1) > clock_tolerance && 3837 abs(to_match->clock - clock2) > clock_tolerance) 3838 continue; 3839 3840 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3841 return vic; 3842 } 3843 3844 return 0; 3845 } 3846 3847 /* 3848 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3849 * @to_match: display mode 3850 * 3851 * An HDMI mode is one defined in the HDMI vendor specific block. 3852 * 3853 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3854 */ 3855 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3856 { 3857 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3858 u8 vic; 3859 3860 if (!to_match->clock) 3861 return 0; 3862 3863 if (to_match->picture_aspect_ratio) 3864 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3865 3866 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3867 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3868 unsigned int clock1, clock2; 3869 3870 /* Make sure to also match alternate clocks */ 3871 clock1 = hdmi_mode->clock; 3872 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3873 3874 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3875 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3876 drm_mode_match(to_match, hdmi_mode, match_flags)) 3877 return vic; 3878 } 3879 return 0; 3880 } 3881 3882 static bool drm_valid_hdmi_vic(u8 vic) 3883 { 3884 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3885 } 3886 3887 static int add_alternate_cea_modes(struct drm_connector *connector, 3888 const struct drm_edid *drm_edid) 3889 { 3890 struct drm_device *dev = connector->dev; 3891 struct drm_display_mode *mode, *tmp; 3892 LIST_HEAD(list); 3893 int modes = 0; 3894 3895 /* Don't add CTA modes if the CTA extension block is missing */ 3896 if (!drm_edid_has_cta_extension(drm_edid)) 3897 return 0; 3898 3899 /* 3900 * Go through all probed modes and create a new mode 3901 * with the alternate clock for certain CEA modes. 3902 */ 3903 list_for_each_entry(mode, &connector->probed_modes, head) { 3904 const struct drm_display_mode *cea_mode = NULL; 3905 struct drm_display_mode *newmode; 3906 u8 vic = drm_match_cea_mode(mode); 3907 unsigned int clock1, clock2; 3908 3909 if (drm_valid_cea_vic(vic)) { 3910 cea_mode = cea_mode_for_vic(vic); 3911 clock2 = cea_mode_alternate_clock(cea_mode); 3912 } else { 3913 vic = drm_match_hdmi_mode(mode); 3914 if (drm_valid_hdmi_vic(vic)) { 3915 cea_mode = &edid_4k_modes[vic]; 3916 clock2 = hdmi_mode_alternate_clock(cea_mode); 3917 } 3918 } 3919 3920 if (!cea_mode) 3921 continue; 3922 3923 clock1 = cea_mode->clock; 3924 3925 if (clock1 == clock2) 3926 continue; 3927 3928 if (mode->clock != clock1 && mode->clock != clock2) 3929 continue; 3930 3931 newmode = drm_mode_duplicate(dev, cea_mode); 3932 if (!newmode) 3933 continue; 3934 3935 /* Carry over the stereo flags */ 3936 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3937 3938 /* 3939 * The current mode could be either variant. Make 3940 * sure to pick the "other" clock for the new mode. 3941 */ 3942 if (mode->clock != clock1) 3943 newmode->clock = clock1; 3944 else 3945 newmode->clock = clock2; 3946 3947 list_add_tail(&newmode->head, &list); 3948 } 3949 3950 list_for_each_entry_safe(mode, tmp, &list, head) { 3951 list_del(&mode->head); 3952 drm_mode_probed_add(connector, mode); 3953 modes++; 3954 } 3955 3956 return modes; 3957 } 3958 3959 static u8 svd_to_vic(u8 svd) 3960 { 3961 /* 0-6 bit vic, 7th bit native mode indicator */ 3962 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3963 return svd & 127; 3964 3965 return svd; 3966 } 3967 3968 static struct drm_display_mode * 3969 drm_display_mode_from_vic_index(struct drm_connector *connector, 3970 const u8 *video_db, u8 video_len, 3971 u8 video_index) 3972 { 3973 struct drm_device *dev = connector->dev; 3974 struct drm_display_mode *newmode; 3975 u8 vic; 3976 3977 if (video_db == NULL || video_index >= video_len) 3978 return NULL; 3979 3980 /* CEA modes are numbered 1..127 */ 3981 vic = svd_to_vic(video_db[video_index]); 3982 if (!drm_valid_cea_vic(vic)) 3983 return NULL; 3984 3985 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3986 if (!newmode) 3987 return NULL; 3988 3989 return newmode; 3990 } 3991 3992 /* 3993 * do_y420vdb_modes - Parse YCBCR 420 only modes 3994 * @connector: connector corresponding to the HDMI sink 3995 * @svds: start of the data block of CEA YCBCR 420 VDB 3996 * @len: length of the CEA YCBCR 420 VDB 3997 * 3998 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3999 * which contains modes which can be supported in YCBCR 420 4000 * output format only. 4001 */ 4002 static int do_y420vdb_modes(struct drm_connector *connector, 4003 const u8 *svds, u8 svds_len) 4004 { 4005 int modes = 0, i; 4006 struct drm_device *dev = connector->dev; 4007 struct drm_display_info *info = &connector->display_info; 4008 struct drm_hdmi_info *hdmi = &info->hdmi; 4009 4010 for (i = 0; i < svds_len; i++) { 4011 u8 vic = svd_to_vic(svds[i]); 4012 struct drm_display_mode *newmode; 4013 4014 if (!drm_valid_cea_vic(vic)) 4015 continue; 4016 4017 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4018 if (!newmode) 4019 break; 4020 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 4021 drm_mode_probed_add(connector, newmode); 4022 modes++; 4023 } 4024 4025 if (modes > 0) 4026 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4027 return modes; 4028 } 4029 4030 /* 4031 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 4032 * @connector: connector corresponding to the HDMI sink 4033 * @vic: CEA vic for the video mode to be added in the map 4034 * 4035 * Makes an entry for a videomode in the YCBCR 420 bitmap 4036 */ 4037 static void 4038 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 4039 { 4040 u8 vic = svd_to_vic(svd); 4041 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4042 4043 if (!drm_valid_cea_vic(vic)) 4044 return; 4045 4046 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 4047 } 4048 4049 /** 4050 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4051 * @dev: DRM device 4052 * @video_code: CEA VIC of the mode 4053 * 4054 * Creates a new mode matching the specified CEA VIC. 4055 * 4056 * Returns: A new drm_display_mode on success or NULL on failure 4057 */ 4058 struct drm_display_mode * 4059 drm_display_mode_from_cea_vic(struct drm_device *dev, 4060 u8 video_code) 4061 { 4062 const struct drm_display_mode *cea_mode; 4063 struct drm_display_mode *newmode; 4064 4065 cea_mode = cea_mode_for_vic(video_code); 4066 if (!cea_mode) 4067 return NULL; 4068 4069 newmode = drm_mode_duplicate(dev, cea_mode); 4070 if (!newmode) 4071 return NULL; 4072 4073 return newmode; 4074 } 4075 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4076 4077 static int 4078 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 4079 { 4080 int i, modes = 0; 4081 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4082 4083 for (i = 0; i < len; i++) { 4084 struct drm_display_mode *mode; 4085 4086 mode = drm_display_mode_from_vic_index(connector, db, len, i); 4087 if (mode) { 4088 /* 4089 * YCBCR420 capability block contains a bitmap which 4090 * gives the index of CEA modes from CEA VDB, which 4091 * can support YCBCR 420 sampling output also (apart 4092 * from RGB/YCBCR444 etc). 4093 * For example, if the bit 0 in bitmap is set, 4094 * first mode in VDB can support YCBCR420 output too. 4095 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 4096 */ 4097 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 4098 drm_add_cmdb_modes(connector, db[i]); 4099 4100 drm_mode_probed_add(connector, mode); 4101 modes++; 4102 } 4103 } 4104 4105 return modes; 4106 } 4107 4108 struct stereo_mandatory_mode { 4109 int width, height, vrefresh; 4110 unsigned int flags; 4111 }; 4112 4113 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4114 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4115 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4116 { 1920, 1080, 50, 4117 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4118 { 1920, 1080, 60, 4119 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4120 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4121 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4122 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4123 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4124 }; 4125 4126 static bool 4127 stereo_match_mandatory(const struct drm_display_mode *mode, 4128 const struct stereo_mandatory_mode *stereo_mode) 4129 { 4130 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4131 4132 return mode->hdisplay == stereo_mode->width && 4133 mode->vdisplay == stereo_mode->height && 4134 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4135 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4136 } 4137 4138 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4139 { 4140 struct drm_device *dev = connector->dev; 4141 const struct drm_display_mode *mode; 4142 struct list_head stereo_modes; 4143 int modes = 0, i; 4144 4145 INIT_LIST_HEAD(&stereo_modes); 4146 4147 list_for_each_entry(mode, &connector->probed_modes, head) { 4148 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4149 const struct stereo_mandatory_mode *mandatory; 4150 struct drm_display_mode *new_mode; 4151 4152 if (!stereo_match_mandatory(mode, 4153 &stereo_mandatory_modes[i])) 4154 continue; 4155 4156 mandatory = &stereo_mandatory_modes[i]; 4157 new_mode = drm_mode_duplicate(dev, mode); 4158 if (!new_mode) 4159 continue; 4160 4161 new_mode->flags |= mandatory->flags; 4162 list_add_tail(&new_mode->head, &stereo_modes); 4163 modes++; 4164 } 4165 } 4166 4167 list_splice_tail(&stereo_modes, &connector->probed_modes); 4168 4169 return modes; 4170 } 4171 4172 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4173 { 4174 struct drm_device *dev = connector->dev; 4175 struct drm_display_mode *newmode; 4176 4177 if (!drm_valid_hdmi_vic(vic)) { 4178 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 4179 return 0; 4180 } 4181 4182 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4183 if (!newmode) 4184 return 0; 4185 4186 drm_mode_probed_add(connector, newmode); 4187 4188 return 1; 4189 } 4190 4191 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4192 const u8 *video_db, u8 video_len, u8 video_index) 4193 { 4194 struct drm_display_mode *newmode; 4195 int modes = 0; 4196 4197 if (structure & (1 << 0)) { 4198 newmode = drm_display_mode_from_vic_index(connector, video_db, 4199 video_len, 4200 video_index); 4201 if (newmode) { 4202 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4203 drm_mode_probed_add(connector, newmode); 4204 modes++; 4205 } 4206 } 4207 if (structure & (1 << 6)) { 4208 newmode = drm_display_mode_from_vic_index(connector, video_db, 4209 video_len, 4210 video_index); 4211 if (newmode) { 4212 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4213 drm_mode_probed_add(connector, newmode); 4214 modes++; 4215 } 4216 } 4217 if (structure & (1 << 8)) { 4218 newmode = drm_display_mode_from_vic_index(connector, video_db, 4219 video_len, 4220 video_index); 4221 if (newmode) { 4222 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4223 drm_mode_probed_add(connector, newmode); 4224 modes++; 4225 } 4226 } 4227 4228 return modes; 4229 } 4230 4231 /* 4232 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4233 * @connector: connector corresponding to the HDMI sink 4234 * @db: start of the CEA vendor specific block 4235 * @len: length of the CEA block payload, ie. one can access up to db[len] 4236 * 4237 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4238 * also adds the stereo 3d modes when applicable. 4239 */ 4240 static int 4241 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4242 const u8 *video_db, u8 video_len) 4243 { 4244 struct drm_display_info *info = &connector->display_info; 4245 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4246 u8 vic_len, hdmi_3d_len = 0; 4247 u16 mask; 4248 u16 structure_all; 4249 4250 if (len < 8) 4251 goto out; 4252 4253 /* no HDMI_Video_Present */ 4254 if (!(db[8] & (1 << 5))) 4255 goto out; 4256 4257 /* Latency_Fields_Present */ 4258 if (db[8] & (1 << 7)) 4259 offset += 2; 4260 4261 /* I_Latency_Fields_Present */ 4262 if (db[8] & (1 << 6)) 4263 offset += 2; 4264 4265 /* the declared length is not long enough for the 2 first bytes 4266 * of additional video format capabilities */ 4267 if (len < (8 + offset + 2)) 4268 goto out; 4269 4270 /* 3D_Present */ 4271 offset++; 4272 if (db[8 + offset] & (1 << 7)) { 4273 modes += add_hdmi_mandatory_stereo_modes(connector); 4274 4275 /* 3D_Multi_present */ 4276 multi_present = (db[8 + offset] & 0x60) >> 5; 4277 } 4278 4279 offset++; 4280 vic_len = db[8 + offset] >> 5; 4281 hdmi_3d_len = db[8 + offset] & 0x1f; 4282 4283 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4284 u8 vic; 4285 4286 vic = db[9 + offset + i]; 4287 modes += add_hdmi_mode(connector, vic); 4288 } 4289 offset += 1 + vic_len; 4290 4291 if (multi_present == 1) 4292 multi_len = 2; 4293 else if (multi_present == 2) 4294 multi_len = 4; 4295 else 4296 multi_len = 0; 4297 4298 if (len < (8 + offset + hdmi_3d_len - 1)) 4299 goto out; 4300 4301 if (hdmi_3d_len < multi_len) 4302 goto out; 4303 4304 if (multi_present == 1 || multi_present == 2) { 4305 /* 3D_Structure_ALL */ 4306 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4307 4308 /* check if 3D_MASK is present */ 4309 if (multi_present == 2) 4310 mask = (db[10 + offset] << 8) | db[11 + offset]; 4311 else 4312 mask = 0xffff; 4313 4314 for (i = 0; i < 16; i++) { 4315 if (mask & (1 << i)) 4316 modes += add_3d_struct_modes(connector, 4317 structure_all, 4318 video_db, 4319 video_len, i); 4320 } 4321 } 4322 4323 offset += multi_len; 4324 4325 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4326 int vic_index; 4327 struct drm_display_mode *newmode = NULL; 4328 unsigned int newflag = 0; 4329 bool detail_present; 4330 4331 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4332 4333 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4334 break; 4335 4336 /* 2D_VIC_order_X */ 4337 vic_index = db[8 + offset + i] >> 4; 4338 4339 /* 3D_Structure_X */ 4340 switch (db[8 + offset + i] & 0x0f) { 4341 case 0: 4342 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4343 break; 4344 case 6: 4345 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4346 break; 4347 case 8: 4348 /* 3D_Detail_X */ 4349 if ((db[9 + offset + i] >> 4) == 1) 4350 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4351 break; 4352 } 4353 4354 if (newflag != 0) { 4355 newmode = drm_display_mode_from_vic_index(connector, 4356 video_db, 4357 video_len, 4358 vic_index); 4359 4360 if (newmode) { 4361 newmode->flags |= newflag; 4362 drm_mode_probed_add(connector, newmode); 4363 modes++; 4364 } 4365 } 4366 4367 if (detail_present) 4368 i++; 4369 } 4370 4371 out: 4372 if (modes > 0) 4373 info->has_hdmi_infoframe = true; 4374 return modes; 4375 } 4376 4377 static int 4378 cea_revision(const u8 *cea) 4379 { 4380 /* 4381 * FIXME is this correct for the DispID variant? 4382 * The DispID spec doesn't really specify whether 4383 * this is the revision of the CEA extension or 4384 * the DispID CEA data block. And the only value 4385 * given as an example is 0. 4386 */ 4387 return cea[1]; 4388 } 4389 4390 /* 4391 * CTA Data Block iterator. 4392 * 4393 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4394 * CTA Data Blocks. 4395 * 4396 * struct cea_db *db: 4397 * struct cea_db_iter iter; 4398 * 4399 * cea_db_iter_edid_begin(edid, &iter); 4400 * cea_db_iter_for_each(db, &iter) { 4401 * // do stuff with db 4402 * } 4403 * cea_db_iter_end(&iter); 4404 */ 4405 struct cea_db_iter { 4406 struct drm_edid_iter edid_iter; 4407 struct displayid_iter displayid_iter; 4408 4409 /* Current Data Block Collection. */ 4410 const u8 *collection; 4411 4412 /* Current Data Block index in current collection. */ 4413 int index; 4414 4415 /* End index in current collection. */ 4416 int end; 4417 }; 4418 4419 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4420 struct cea_db { 4421 u8 tag_length; 4422 u8 data[]; 4423 } __packed; 4424 4425 static int cea_db_tag(const struct cea_db *db) 4426 { 4427 return db->tag_length >> 5; 4428 } 4429 4430 static int cea_db_payload_len(const void *_db) 4431 { 4432 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4433 const struct cea_db *db = _db; 4434 4435 return db->tag_length & 0x1f; 4436 } 4437 4438 static const void *cea_db_data(const struct cea_db *db) 4439 { 4440 return db->data; 4441 } 4442 4443 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4444 { 4445 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4446 cea_db_payload_len(db) >= 1 && 4447 db->data[0] == tag; 4448 } 4449 4450 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4451 { 4452 const u8 *data = cea_db_data(db); 4453 4454 return cea_db_tag(db) == CTA_DB_VENDOR && 4455 cea_db_payload_len(db) >= 3 && 4456 oui(data[2], data[1], data[0]) == vendor_oui; 4457 } 4458 4459 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4460 struct cea_db_iter *iter) 4461 { 4462 memset(iter, 0, sizeof(*iter)); 4463 4464 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4465 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4466 } 4467 4468 static const struct cea_db * 4469 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4470 { 4471 const struct cea_db *db; 4472 4473 if (!iter->collection) 4474 return NULL; 4475 4476 db = (const struct cea_db *)&iter->collection[iter->index]; 4477 4478 if (iter->index + sizeof(*db) <= iter->end && 4479 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4480 return db; 4481 4482 return NULL; 4483 } 4484 4485 /* 4486 * References: 4487 * - VESA E-EDID v1.4 4488 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4489 */ 4490 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4491 { 4492 const u8 *ext; 4493 4494 drm_edid_iter_for_each(ext, &iter->edid_iter) { 4495 /* Only support CTA Extension revision 3+ */ 4496 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 4497 continue; 4498 4499 iter->index = 4; 4500 iter->end = ext[2]; 4501 if (iter->end == 0) 4502 iter->end = 127; 4503 if (iter->end < 4 || iter->end > 127) 4504 continue; 4505 4506 return ext; 4507 } 4508 4509 return NULL; 4510 } 4511 4512 /* 4513 * References: 4514 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 4515 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 4516 * 4517 * Note that the above do not specify any connection between DisplayID Data 4518 * Block revision and CTA Extension versions. 4519 */ 4520 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 4521 { 4522 const struct displayid_block *block; 4523 4524 displayid_iter_for_each(block, &iter->displayid_iter) { 4525 if (block->tag != DATA_BLOCK_CTA) 4526 continue; 4527 4528 /* 4529 * The displayid iterator has already verified the block bounds 4530 * in displayid_iter_block(). 4531 */ 4532 iter->index = sizeof(*block); 4533 iter->end = iter->index + block->num_bytes; 4534 4535 return block; 4536 } 4537 4538 return NULL; 4539 } 4540 4541 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 4542 { 4543 const struct cea_db *db; 4544 4545 if (iter->collection) { 4546 /* Current collection should always be valid. */ 4547 db = __cea_db_iter_current_block(iter); 4548 if (WARN_ON(!db)) { 4549 iter->collection = NULL; 4550 return NULL; 4551 } 4552 4553 /* Next block in CTA Data Block Collection */ 4554 iter->index += sizeof(*db) + cea_db_payload_len(db); 4555 4556 db = __cea_db_iter_current_block(iter); 4557 if (db) 4558 return db; 4559 } 4560 4561 for (;;) { 4562 /* 4563 * Find the next CTA Data Block Collection. First iterate all 4564 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 4565 * 4566 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 4567 * Extension, it's recommended that DisplayID extensions are 4568 * exposed after all of the CTA Extensions. 4569 */ 4570 iter->collection = __cea_db_iter_edid_next(iter); 4571 if (!iter->collection) 4572 iter->collection = __cea_db_iter_displayid_next(iter); 4573 4574 if (!iter->collection) 4575 return NULL; 4576 4577 db = __cea_db_iter_current_block(iter); 4578 if (db) 4579 return db; 4580 } 4581 } 4582 4583 #define cea_db_iter_for_each(__db, __iter) \ 4584 while (((__db) = __cea_db_iter_next(__iter))) 4585 4586 static void cea_db_iter_end(struct cea_db_iter *iter) 4587 { 4588 displayid_iter_end(&iter->displayid_iter); 4589 drm_edid_iter_end(&iter->edid_iter); 4590 4591 memset(iter, 0, sizeof(*iter)); 4592 } 4593 4594 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 4595 { 4596 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 4597 cea_db_payload_len(db) >= 5; 4598 } 4599 4600 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 4601 { 4602 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 4603 cea_db_payload_len(db) >= 7; 4604 } 4605 4606 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 4607 { 4608 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 4609 cea_db_payload_len(db) == 21; 4610 } 4611 4612 static bool cea_db_is_vcdb(const struct cea_db *db) 4613 { 4614 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 4615 cea_db_payload_len(db) == 2; 4616 } 4617 4618 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 4619 { 4620 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 4621 cea_db_payload_len(db) >= 7; 4622 } 4623 4624 static bool cea_db_is_y420cmdb(const struct cea_db *db) 4625 { 4626 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 4627 } 4628 4629 static bool cea_db_is_y420vdb(const struct cea_db *db) 4630 { 4631 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 4632 } 4633 4634 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 4635 { 4636 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 4637 cea_db_payload_len(db) >= 3; 4638 } 4639 4640 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4641 const u8 *db) 4642 { 4643 struct drm_display_info *info = &connector->display_info; 4644 struct drm_hdmi_info *hdmi = &info->hdmi; 4645 u8 map_len = cea_db_payload_len(db) - 1; 4646 u8 count; 4647 u64 map = 0; 4648 4649 if (map_len == 0) { 4650 /* All CEA modes support ycbcr420 sampling also.*/ 4651 hdmi->y420_cmdb_map = U64_MAX; 4652 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4653 return; 4654 } 4655 4656 /* 4657 * This map indicates which of the existing CEA block modes 4658 * from VDB can support YCBCR420 output too. So if bit=0 is 4659 * set, first mode from VDB can support YCBCR420 output too. 4660 * We will parse and keep this map, before parsing VDB itself 4661 * to avoid going through the same block again and again. 4662 * 4663 * Spec is not clear about max possible size of this block. 4664 * Clamping max bitmap block size at 8 bytes. Every byte can 4665 * address 8 CEA modes, in this way this map can address 4666 * 8*8 = first 64 SVDs. 4667 */ 4668 if (WARN_ON_ONCE(map_len > 8)) 4669 map_len = 8; 4670 4671 for (count = 0; count < map_len; count++) 4672 map |= (u64)db[2 + count] << (8 * count); 4673 4674 if (map) 4675 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4676 4677 hdmi->y420_cmdb_map = map; 4678 } 4679 4680 static int add_cea_modes(struct drm_connector *connector, 4681 const struct drm_edid *drm_edid) 4682 { 4683 const struct cea_db *db; 4684 struct cea_db_iter iter; 4685 int modes = 0; 4686 4687 cea_db_iter_edid_begin(drm_edid, &iter); 4688 cea_db_iter_for_each(db, &iter) { 4689 const u8 *hdmi = NULL, *video = NULL; 4690 u8 hdmi_len = 0, video_len = 0; 4691 4692 if (cea_db_tag(db) == CTA_DB_VIDEO) { 4693 video = cea_db_data(db); 4694 video_len = cea_db_payload_len(db); 4695 modes += do_cea_modes(connector, video, video_len); 4696 } else if (cea_db_is_hdmi_vsdb(db)) { 4697 /* FIXME: Switch to use cea_db_data() */ 4698 hdmi = (const u8 *)db; 4699 hdmi_len = cea_db_payload_len(db); 4700 } else if (cea_db_is_y420vdb(db)) { 4701 const u8 *vdb420 = cea_db_data(db) + 1; 4702 4703 /* Add 4:2:0(only) modes present in EDID */ 4704 modes += do_y420vdb_modes(connector, vdb420, 4705 cea_db_payload_len(db) - 1); 4706 } 4707 4708 /* 4709 * We parse the HDMI VSDB after having added the cea modes as we 4710 * will be patching their flags when the sink supports stereo 4711 * 3D. 4712 */ 4713 if (hdmi) 4714 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, 4715 video, video_len); 4716 } 4717 cea_db_iter_end(&iter); 4718 4719 return modes; 4720 } 4721 4722 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4723 { 4724 const struct drm_display_mode *cea_mode; 4725 int clock1, clock2, clock; 4726 u8 vic; 4727 const char *type; 4728 4729 /* 4730 * allow 5kHz clock difference either way to account for 4731 * the 10kHz clock resolution limit of detailed timings. 4732 */ 4733 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4734 if (drm_valid_cea_vic(vic)) { 4735 type = "CEA"; 4736 cea_mode = cea_mode_for_vic(vic); 4737 clock1 = cea_mode->clock; 4738 clock2 = cea_mode_alternate_clock(cea_mode); 4739 } else { 4740 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4741 if (drm_valid_hdmi_vic(vic)) { 4742 type = "HDMI"; 4743 cea_mode = &edid_4k_modes[vic]; 4744 clock1 = cea_mode->clock; 4745 clock2 = hdmi_mode_alternate_clock(cea_mode); 4746 } else { 4747 return; 4748 } 4749 } 4750 4751 /* pick whichever is closest */ 4752 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4753 clock = clock1; 4754 else 4755 clock = clock2; 4756 4757 if (mode->clock == clock) 4758 return; 4759 4760 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4761 type, vic, mode->clock, clock); 4762 mode->clock = clock; 4763 } 4764 4765 static uint8_t eotf_supported(const u8 *edid_ext) 4766 { 4767 return edid_ext[2] & 4768 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4769 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4770 BIT(HDMI_EOTF_SMPTE_ST2084) | 4771 BIT(HDMI_EOTF_BT_2100_HLG)); 4772 } 4773 4774 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4775 { 4776 return edid_ext[3] & 4777 BIT(HDMI_STATIC_METADATA_TYPE1); 4778 } 4779 4780 static void 4781 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4782 { 4783 u16 len; 4784 4785 len = cea_db_payload_len(db); 4786 4787 connector->hdr_sink_metadata.hdmi_type1.eotf = 4788 eotf_supported(db); 4789 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4790 hdr_metadata_type(db); 4791 4792 if (len >= 4) 4793 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4794 if (len >= 5) 4795 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4796 if (len >= 6) 4797 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4798 } 4799 4800 static void 4801 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4802 { 4803 u8 len = cea_db_payload_len(db); 4804 4805 if (len >= 6 && (db[6] & (1 << 7))) 4806 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4807 if (len >= 8) { 4808 connector->latency_present[0] = db[8] >> 7; 4809 connector->latency_present[1] = (db[8] >> 6) & 1; 4810 } 4811 if (len >= 9) 4812 connector->video_latency[0] = db[9]; 4813 if (len >= 10) 4814 connector->audio_latency[0] = db[10]; 4815 if (len >= 11) 4816 connector->video_latency[1] = db[11]; 4817 if (len >= 12) 4818 connector->audio_latency[1] = db[12]; 4819 4820 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4821 "video latency %d %d, " 4822 "audio latency %d %d\n", 4823 connector->latency_present[0], 4824 connector->latency_present[1], 4825 connector->video_latency[0], 4826 connector->video_latency[1], 4827 connector->audio_latency[0], 4828 connector->audio_latency[1]); 4829 } 4830 4831 static void 4832 monitor_name(const struct detailed_timing *timing, void *data) 4833 { 4834 const char **res = data; 4835 4836 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 4837 return; 4838 4839 *res = timing->data.other_data.data.str.str; 4840 } 4841 4842 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 4843 { 4844 const char *edid_name = NULL; 4845 int mnl; 4846 4847 if (!drm_edid || !name) 4848 return 0; 4849 4850 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 4851 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4852 if (edid_name[mnl] == 0x0a) 4853 break; 4854 4855 name[mnl] = edid_name[mnl]; 4856 } 4857 4858 return mnl; 4859 } 4860 4861 /** 4862 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4863 * @edid: monitor EDID information 4864 * @name: pointer to a character array to hold the name of the monitor 4865 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4866 * 4867 */ 4868 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 4869 { 4870 int name_length = 0; 4871 4872 if (bufsize <= 0) 4873 return; 4874 4875 if (edid) { 4876 char buf[13]; 4877 struct drm_edid drm_edid = { 4878 .edid = edid, 4879 .size = edid_size(edid), 4880 }; 4881 4882 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 4883 memcpy(name, buf, name_length); 4884 } 4885 4886 name[name_length] = '\0'; 4887 } 4888 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4889 4890 static void clear_eld(struct drm_connector *connector) 4891 { 4892 memset(connector->eld, 0, sizeof(connector->eld)); 4893 4894 connector->latency_present[0] = false; 4895 connector->latency_present[1] = false; 4896 connector->video_latency[0] = 0; 4897 connector->audio_latency[0] = 0; 4898 connector->video_latency[1] = 0; 4899 connector->audio_latency[1] = 0; 4900 } 4901 4902 /* 4903 * drm_edid_to_eld - build ELD from EDID 4904 * @connector: connector corresponding to the HDMI/DP sink 4905 * @drm_edid: EDID to parse 4906 * 4907 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4908 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4909 */ 4910 static void drm_edid_to_eld(struct drm_connector *connector, 4911 const struct drm_edid *drm_edid) 4912 { 4913 const struct drm_display_info *info = &connector->display_info; 4914 const struct cea_db *db; 4915 struct cea_db_iter iter; 4916 uint8_t *eld = connector->eld; 4917 int total_sad_count = 0; 4918 int mnl; 4919 4920 clear_eld(connector); 4921 4922 if (!drm_edid) 4923 return; 4924 4925 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4926 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4927 4928 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 4929 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4930 4931 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4932 4933 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 4934 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 4935 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 4936 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 4937 4938 cea_db_iter_edid_begin(drm_edid, &iter); 4939 cea_db_iter_for_each(db, &iter) { 4940 const u8 *data = cea_db_data(db); 4941 int len = cea_db_payload_len(db); 4942 int sad_count; 4943 4944 switch (cea_db_tag(db)) { 4945 case CTA_DB_AUDIO: 4946 /* Audio Data Block, contains SADs */ 4947 sad_count = min(len / 3, 15 - total_sad_count); 4948 if (sad_count >= 1) 4949 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4950 data, sad_count * 3); 4951 total_sad_count += sad_count; 4952 break; 4953 case CTA_DB_SPEAKER: 4954 /* Speaker Allocation Data Block */ 4955 if (len >= 1) 4956 eld[DRM_ELD_SPEAKER] = data[0]; 4957 break; 4958 case CTA_DB_VENDOR: 4959 /* HDMI Vendor-Specific Data Block */ 4960 if (cea_db_is_hdmi_vsdb(db)) 4961 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 4962 break; 4963 default: 4964 break; 4965 } 4966 } 4967 cea_db_iter_end(&iter); 4968 4969 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4970 4971 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4972 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4973 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4974 else 4975 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4976 4977 eld[DRM_ELD_BASELINE_ELD_LEN] = 4978 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4979 4980 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4981 drm_eld_size(eld), total_sad_count); 4982 } 4983 4984 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 4985 struct cea_sad **sads) 4986 { 4987 const struct cea_db *db; 4988 struct cea_db_iter iter; 4989 int count = 0; 4990 4991 cea_db_iter_edid_begin(drm_edid, &iter); 4992 cea_db_iter_for_each(db, &iter) { 4993 if (cea_db_tag(db) == CTA_DB_AUDIO) { 4994 int j; 4995 4996 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 4997 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4998 if (!*sads) 4999 return -ENOMEM; 5000 for (j = 0; j < count; j++) { 5001 const u8 *sad = &db->data[j * 3]; 5002 5003 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5004 (*sads)[j].channels = sad[0] & 0x7; 5005 (*sads)[j].freq = sad[1] & 0x7F; 5006 (*sads)[j].byte2 = sad[2]; 5007 } 5008 break; 5009 } 5010 } 5011 cea_db_iter_end(&iter); 5012 5013 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5014 5015 return count; 5016 } 5017 5018 /** 5019 * drm_edid_to_sad - extracts SADs from EDID 5020 * @edid: EDID to parse 5021 * @sads: pointer that will be set to the extracted SADs 5022 * 5023 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5024 * 5025 * Note: The returned pointer needs to be freed using kfree(). 5026 * 5027 * Return: The number of found SADs or negative number on error. 5028 */ 5029 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5030 { 5031 struct drm_edid drm_edid; 5032 5033 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5034 } 5035 EXPORT_SYMBOL(drm_edid_to_sad); 5036 5037 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5038 u8 **sadb) 5039 { 5040 const struct cea_db *db; 5041 struct cea_db_iter iter; 5042 int count = 0; 5043 5044 cea_db_iter_edid_begin(drm_edid, &iter); 5045 cea_db_iter_for_each(db, &iter) { 5046 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5047 cea_db_payload_len(db) == 3) { 5048 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5049 GFP_KERNEL); 5050 if (!*sadb) 5051 return -ENOMEM; 5052 count = cea_db_payload_len(db); 5053 break; 5054 } 5055 } 5056 cea_db_iter_end(&iter); 5057 5058 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5059 5060 return count; 5061 } 5062 5063 /** 5064 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5065 * @edid: EDID to parse 5066 * @sadb: pointer to the speaker block 5067 * 5068 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5069 * 5070 * Note: The returned pointer needs to be freed using kfree(). 5071 * 5072 * Return: The number of found Speaker Allocation Blocks or negative number on 5073 * error. 5074 */ 5075 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5076 { 5077 struct drm_edid drm_edid; 5078 5079 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5080 sadb); 5081 } 5082 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5083 5084 /** 5085 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5086 * @connector: connector associated with the HDMI/DP sink 5087 * @mode: the display mode 5088 * 5089 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5090 * the sink doesn't support audio or video. 5091 */ 5092 int drm_av_sync_delay(struct drm_connector *connector, 5093 const struct drm_display_mode *mode) 5094 { 5095 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5096 int a, v; 5097 5098 if (!connector->latency_present[0]) 5099 return 0; 5100 if (!connector->latency_present[1]) 5101 i = 0; 5102 5103 a = connector->audio_latency[i]; 5104 v = connector->video_latency[i]; 5105 5106 /* 5107 * HDMI/DP sink doesn't support audio or video? 5108 */ 5109 if (a == 255 || v == 255) 5110 return 0; 5111 5112 /* 5113 * Convert raw EDID values to millisecond. 5114 * Treat unknown latency as 0ms. 5115 */ 5116 if (a) 5117 a = min(2 * (a - 1), 500); 5118 if (v) 5119 v = min(2 * (v - 1), 500); 5120 5121 return max(v - a, 0); 5122 } 5123 EXPORT_SYMBOL(drm_av_sync_delay); 5124 5125 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5126 { 5127 const struct cea_db *db; 5128 struct cea_db_iter iter; 5129 bool hdmi = false; 5130 5131 /* 5132 * Because HDMI identifier is in Vendor Specific Block, 5133 * search it from all data blocks of CEA extension. 5134 */ 5135 cea_db_iter_edid_begin(drm_edid, &iter); 5136 cea_db_iter_for_each(db, &iter) { 5137 if (cea_db_is_hdmi_vsdb(db)) { 5138 hdmi = true; 5139 break; 5140 } 5141 } 5142 cea_db_iter_end(&iter); 5143 5144 return hdmi; 5145 } 5146 5147 /** 5148 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5149 * @edid: monitor EDID information 5150 * 5151 * Parse the CEA extension according to CEA-861-B. 5152 * 5153 * Drivers that have added the modes parsed from EDID to drm_display_info 5154 * should use &drm_display_info.is_hdmi instead of calling this function. 5155 * 5156 * Return: True if the monitor is HDMI, false if not or unknown. 5157 */ 5158 bool drm_detect_hdmi_monitor(const struct edid *edid) 5159 { 5160 struct drm_edid drm_edid; 5161 5162 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5163 } 5164 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5165 5166 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5167 { 5168 struct drm_edid_iter edid_iter; 5169 const struct cea_db *db; 5170 struct cea_db_iter iter; 5171 const u8 *edid_ext; 5172 bool has_audio = false; 5173 5174 drm_edid_iter_begin(drm_edid, &edid_iter); 5175 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5176 if (edid_ext[0] == CEA_EXT) { 5177 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5178 if (has_audio) 5179 break; 5180 } 5181 } 5182 drm_edid_iter_end(&edid_iter); 5183 5184 if (has_audio) { 5185 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5186 goto end; 5187 } 5188 5189 cea_db_iter_edid_begin(drm_edid, &iter); 5190 cea_db_iter_for_each(db, &iter) { 5191 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5192 const u8 *data = cea_db_data(db); 5193 int i; 5194 5195 for (i = 0; i < cea_db_payload_len(db); i += 3) 5196 DRM_DEBUG_KMS("CEA audio format %d\n", 5197 (data[i] >> 3) & 0xf); 5198 has_audio = true; 5199 break; 5200 } 5201 } 5202 cea_db_iter_end(&iter); 5203 5204 end: 5205 return has_audio; 5206 } 5207 5208 /** 5209 * drm_detect_monitor_audio - check monitor audio capability 5210 * @edid: EDID block to scan 5211 * 5212 * Monitor should have CEA extension block. 5213 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5214 * audio' only. If there is any audio extension block and supported 5215 * audio format, assume at least 'basic audio' support, even if 'basic 5216 * audio' is not defined in EDID. 5217 * 5218 * Return: True if the monitor supports audio, false otherwise. 5219 */ 5220 bool drm_detect_monitor_audio(const struct edid *edid) 5221 { 5222 struct drm_edid drm_edid; 5223 5224 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5225 } 5226 EXPORT_SYMBOL(drm_detect_monitor_audio); 5227 5228 5229 /** 5230 * drm_default_rgb_quant_range - default RGB quantization range 5231 * @mode: display mode 5232 * 5233 * Determine the default RGB quantization range for the mode, 5234 * as specified in CEA-861. 5235 * 5236 * Return: The default RGB quantization range for the mode 5237 */ 5238 enum hdmi_quantization_range 5239 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5240 { 5241 /* All CEA modes other than VIC 1 use limited quantization range. */ 5242 return drm_match_cea_mode(mode) > 1 ? 5243 HDMI_QUANTIZATION_RANGE_LIMITED : 5244 HDMI_QUANTIZATION_RANGE_FULL; 5245 } 5246 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5247 5248 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5249 { 5250 struct drm_display_info *info = &connector->display_info; 5251 5252 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 5253 5254 if (db[2] & EDID_CEA_VCDB_QS) 5255 info->rgb_quant_range_selectable = true; 5256 } 5257 5258 static 5259 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5260 { 5261 switch (max_frl_rate) { 5262 case 1: 5263 *max_lanes = 3; 5264 *max_rate_per_lane = 3; 5265 break; 5266 case 2: 5267 *max_lanes = 3; 5268 *max_rate_per_lane = 6; 5269 break; 5270 case 3: 5271 *max_lanes = 4; 5272 *max_rate_per_lane = 6; 5273 break; 5274 case 4: 5275 *max_lanes = 4; 5276 *max_rate_per_lane = 8; 5277 break; 5278 case 5: 5279 *max_lanes = 4; 5280 *max_rate_per_lane = 10; 5281 break; 5282 case 6: 5283 *max_lanes = 4; 5284 *max_rate_per_lane = 12; 5285 break; 5286 case 0: 5287 default: 5288 *max_lanes = 0; 5289 *max_rate_per_lane = 0; 5290 } 5291 } 5292 5293 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5294 const u8 *db) 5295 { 5296 u8 dc_mask; 5297 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5298 5299 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5300 hdmi->y420_dc_modes = dc_mask; 5301 } 5302 5303 /* Sink Capability Data Structure */ 5304 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 5305 const u8 *hf_scds) 5306 { 5307 struct drm_display_info *display = &connector->display_info; 5308 struct drm_hdmi_info *hdmi = &display->hdmi; 5309 5310 display->has_hdmi_infoframe = true; 5311 5312 if (hf_scds[6] & 0x80) { 5313 hdmi->scdc.supported = true; 5314 if (hf_scds[6] & 0x40) 5315 hdmi->scdc.read_request = true; 5316 } 5317 5318 /* 5319 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 5320 * And as per the spec, three factors confirm this: 5321 * * Availability of a HF-VSDB block in EDID (check) 5322 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 5323 * * SCDC support available (let's check) 5324 * Lets check it out. 5325 */ 5326 5327 if (hf_scds[5]) { 5328 /* max clock is 5000 KHz times block value */ 5329 u32 max_tmds_clock = hf_scds[5] * 5000; 5330 struct drm_scdc *scdc = &hdmi->scdc; 5331 5332 if (max_tmds_clock > 340000) { 5333 display->max_tmds_clock = max_tmds_clock; 5334 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 5335 display->max_tmds_clock); 5336 } 5337 5338 if (scdc->supported) { 5339 scdc->scrambling.supported = true; 5340 5341 /* Few sinks support scrambling for clocks < 340M */ 5342 if ((hf_scds[6] & 0x8)) 5343 scdc->scrambling.low_rates = true; 5344 } 5345 } 5346 5347 if (hf_scds[7]) { 5348 u8 max_frl_rate; 5349 u8 dsc_max_frl_rate; 5350 u8 dsc_max_slices; 5351 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5352 5353 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 5354 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 5355 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 5356 &hdmi->max_frl_rate_per_lane); 5357 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5358 5359 if (hdmi_dsc->v_1p2) { 5360 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5361 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5362 5363 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 5364 hdmi_dsc->bpc_supported = 16; 5365 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 5366 hdmi_dsc->bpc_supported = 12; 5367 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 5368 hdmi_dsc->bpc_supported = 10; 5369 else 5370 hdmi_dsc->bpc_supported = 0; 5371 5372 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5373 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5374 &hdmi_dsc->max_frl_rate_per_lane); 5375 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5376 5377 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 5378 switch (dsc_max_slices) { 5379 case 1: 5380 hdmi_dsc->max_slices = 1; 5381 hdmi_dsc->clk_per_slice = 340; 5382 break; 5383 case 2: 5384 hdmi_dsc->max_slices = 2; 5385 hdmi_dsc->clk_per_slice = 340; 5386 break; 5387 case 3: 5388 hdmi_dsc->max_slices = 4; 5389 hdmi_dsc->clk_per_slice = 340; 5390 break; 5391 case 4: 5392 hdmi_dsc->max_slices = 8; 5393 hdmi_dsc->clk_per_slice = 340; 5394 break; 5395 case 5: 5396 hdmi_dsc->max_slices = 8; 5397 hdmi_dsc->clk_per_slice = 400; 5398 break; 5399 case 6: 5400 hdmi_dsc->max_slices = 12; 5401 hdmi_dsc->clk_per_slice = 400; 5402 break; 5403 case 7: 5404 hdmi_dsc->max_slices = 16; 5405 hdmi_dsc->clk_per_slice = 400; 5406 break; 5407 case 0: 5408 default: 5409 hdmi_dsc->max_slices = 0; 5410 hdmi_dsc->clk_per_slice = 0; 5411 } 5412 } 5413 } 5414 5415 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 5416 } 5417 5418 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5419 const u8 *hdmi) 5420 { 5421 struct drm_display_info *info = &connector->display_info; 5422 unsigned int dc_bpc = 0; 5423 5424 /* HDMI supports at least 8 bpc */ 5425 info->bpc = 8; 5426 5427 if (cea_db_payload_len(hdmi) < 6) 5428 return; 5429 5430 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5431 dc_bpc = 10; 5432 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5433 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5434 connector->name); 5435 } 5436 5437 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5438 dc_bpc = 12; 5439 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5440 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5441 connector->name); 5442 } 5443 5444 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5445 dc_bpc = 16; 5446 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5447 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5448 connector->name); 5449 } 5450 5451 if (dc_bpc == 0) { 5452 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5453 connector->name); 5454 return; 5455 } 5456 5457 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5458 connector->name, dc_bpc); 5459 info->bpc = dc_bpc; 5460 5461 /* YCRCB444 is optional according to spec. */ 5462 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5463 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5464 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5465 connector->name); 5466 } 5467 5468 /* 5469 * Spec says that if any deep color mode is supported at all, 5470 * then deep color 36 bit must be supported. 5471 */ 5472 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5473 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5474 connector->name); 5475 } 5476 } 5477 5478 static void 5479 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5480 { 5481 struct drm_display_info *info = &connector->display_info; 5482 u8 len = cea_db_payload_len(db); 5483 5484 info->is_hdmi = true; 5485 5486 if (len >= 6) 5487 info->dvi_dual = db[6] & 1; 5488 if (len >= 7) 5489 info->max_tmds_clock = db[7] * 5000; 5490 5491 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5492 "max TMDS clock %d kHz\n", 5493 info->dvi_dual, 5494 info->max_tmds_clock); 5495 5496 drm_parse_hdmi_deep_color_info(connector, db); 5497 } 5498 5499 /* 5500 * See EDID extension for head-mounted and specialized monitors, specified at: 5501 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 5502 */ 5503 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 5504 const u8 *db) 5505 { 5506 struct drm_display_info *info = &connector->display_info; 5507 u8 version = db[4]; 5508 bool desktop_usage = db[5] & BIT(6); 5509 5510 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 5511 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 5512 info->non_desktop = true; 5513 5514 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", 5515 version, db[5]); 5516 } 5517 5518 static void drm_parse_cea_ext(struct drm_connector *connector, 5519 const struct drm_edid *drm_edid) 5520 { 5521 struct drm_display_info *info = &connector->display_info; 5522 struct drm_edid_iter edid_iter; 5523 const struct cea_db *db; 5524 struct cea_db_iter iter; 5525 const u8 *edid_ext; 5526 5527 drm_edid_iter_begin(drm_edid, &edid_iter); 5528 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5529 if (edid_ext[0] != CEA_EXT) 5530 continue; 5531 5532 if (!info->cea_rev) 5533 info->cea_rev = edid_ext[1]; 5534 5535 if (info->cea_rev != edid_ext[1]) 5536 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n", 5537 info->cea_rev, edid_ext[1]); 5538 5539 /* The existence of a CTA extension should imply RGB support */ 5540 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5541 if (edid_ext[3] & EDID_CEA_YCRCB444) 5542 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5543 if (edid_ext[3] & EDID_CEA_YCRCB422) 5544 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5545 } 5546 drm_edid_iter_end(&edid_iter); 5547 5548 cea_db_iter_edid_begin(drm_edid, &iter); 5549 cea_db_iter_for_each(db, &iter) { 5550 /* FIXME: convert parsers to use struct cea_db */ 5551 const u8 *data = (const u8 *)db; 5552 5553 if (cea_db_is_hdmi_vsdb(db)) 5554 drm_parse_hdmi_vsdb_video(connector, data); 5555 else if (cea_db_is_hdmi_forum_vsdb(db) || 5556 cea_db_is_hdmi_forum_scdb(db)) 5557 drm_parse_hdmi_forum_scds(connector, data); 5558 else if (cea_db_is_microsoft_vsdb(db)) 5559 drm_parse_microsoft_vsdb(connector, data); 5560 else if (cea_db_is_y420cmdb(db)) 5561 drm_parse_y420cmdb_bitmap(connector, data); 5562 else if (cea_db_is_vcdb(db)) 5563 drm_parse_vcdb(connector, data); 5564 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 5565 drm_parse_hdr_metadata_block(connector, data); 5566 } 5567 cea_db_iter_end(&iter); 5568 } 5569 5570 static 5571 void get_monitor_range(const struct detailed_timing *timing, 5572 void *info_monitor_range) 5573 { 5574 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5575 const struct detailed_non_pixel *data = &timing->data.other_data; 5576 const struct detailed_data_monitor_range *range = &data->data.range; 5577 5578 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 5579 return; 5580 5581 /* 5582 * Check for flag range limits only. If flag == 1 then 5583 * no additional timing information provided. 5584 * Default GTF, GTF Secondary curve and CVT are not 5585 * supported 5586 */ 5587 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5588 return; 5589 5590 monitor_range->min_vfreq = range->min_vfreq; 5591 monitor_range->max_vfreq = range->max_vfreq; 5592 } 5593 5594 static void drm_get_monitor_range(struct drm_connector *connector, 5595 const struct drm_edid *drm_edid) 5596 { 5597 struct drm_display_info *info = &connector->display_info; 5598 5599 if (!version_greater(drm_edid, 1, 1)) 5600 return; 5601 5602 drm_for_each_detailed_block(drm_edid, get_monitor_range, 5603 &info->monitor_range); 5604 5605 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5606 info->monitor_range.min_vfreq, 5607 info->monitor_range.max_vfreq); 5608 } 5609 5610 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 5611 const struct displayid_block *block) 5612 { 5613 struct displayid_vesa_vendor_specific_block *vesa = 5614 (struct displayid_vesa_vendor_specific_block *)block; 5615 struct drm_display_info *info = &connector->display_info; 5616 5617 if (block->num_bytes < 3) { 5618 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", 5619 block->num_bytes); 5620 return; 5621 } 5622 5623 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 5624 return; 5625 5626 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 5627 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); 5628 return; 5629 } 5630 5631 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 5632 default: 5633 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); 5634 fallthrough; 5635 case 0: 5636 info->mso_stream_count = 0; 5637 break; 5638 case 1: 5639 info->mso_stream_count = 2; /* 2 or 4 links */ 5640 break; 5641 case 2: 5642 info->mso_stream_count = 4; /* 4 links */ 5643 break; 5644 } 5645 5646 if (!info->mso_stream_count) { 5647 info->mso_pixel_overlap = 0; 5648 return; 5649 } 5650 5651 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 5652 if (info->mso_pixel_overlap > 8) { 5653 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", 5654 info->mso_pixel_overlap); 5655 info->mso_pixel_overlap = 8; 5656 } 5657 5658 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", 5659 info->mso_stream_count, info->mso_pixel_overlap); 5660 } 5661 5662 static void drm_update_mso(struct drm_connector *connector, 5663 const struct drm_edid *drm_edid) 5664 { 5665 const struct displayid_block *block; 5666 struct displayid_iter iter; 5667 5668 displayid_iter_edid_begin(drm_edid, &iter); 5669 displayid_iter_for_each(block, &iter) { 5670 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 5671 drm_parse_vesa_mso_data(connector, block); 5672 } 5673 displayid_iter_end(&iter); 5674 } 5675 5676 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5677 * all of the values which would have been set from EDID 5678 */ 5679 void 5680 drm_reset_display_info(struct drm_connector *connector) 5681 { 5682 struct drm_display_info *info = &connector->display_info; 5683 5684 info->width_mm = 0; 5685 info->height_mm = 0; 5686 5687 info->bpc = 0; 5688 info->color_formats = 0; 5689 info->cea_rev = 0; 5690 info->max_tmds_clock = 0; 5691 info->dvi_dual = false; 5692 info->is_hdmi = false; 5693 info->has_hdmi_infoframe = false; 5694 info->rgb_quant_range_selectable = false; 5695 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5696 5697 info->edid_hdmi_rgb444_dc_modes = 0; 5698 info->edid_hdmi_ycbcr444_dc_modes = 0; 5699 5700 info->non_desktop = 0; 5701 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5702 5703 info->mso_stream_count = 0; 5704 info->mso_pixel_overlap = 0; 5705 } 5706 5707 static u32 update_display_info(struct drm_connector *connector, 5708 const struct drm_edid *drm_edid) 5709 { 5710 struct drm_display_info *info = &connector->display_info; 5711 const struct edid *edid = drm_edid->edid; 5712 5713 u32 quirks = edid_get_quirks(drm_edid); 5714 5715 drm_reset_display_info(connector); 5716 5717 info->width_mm = edid->width_cm * 10; 5718 info->height_mm = edid->height_cm * 10; 5719 5720 drm_get_monitor_range(connector, drm_edid); 5721 5722 if (edid->revision < 3) 5723 goto out; 5724 5725 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5726 goto out; 5727 5728 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5729 drm_parse_cea_ext(connector, drm_edid); 5730 5731 /* 5732 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5733 * 5734 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5735 * tells us to assume 8 bpc color depth if the EDID doesn't have 5736 * extensions which tell otherwise. 5737 */ 5738 if (info->bpc == 0 && edid->revision == 3 && 5739 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5740 info->bpc = 8; 5741 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5742 connector->name, info->bpc); 5743 } 5744 5745 /* Only defined for 1.4 with digital displays */ 5746 if (edid->revision < 4) 5747 goto out; 5748 5749 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5750 case DRM_EDID_DIGITAL_DEPTH_6: 5751 info->bpc = 6; 5752 break; 5753 case DRM_EDID_DIGITAL_DEPTH_8: 5754 info->bpc = 8; 5755 break; 5756 case DRM_EDID_DIGITAL_DEPTH_10: 5757 info->bpc = 10; 5758 break; 5759 case DRM_EDID_DIGITAL_DEPTH_12: 5760 info->bpc = 12; 5761 break; 5762 case DRM_EDID_DIGITAL_DEPTH_14: 5763 info->bpc = 14; 5764 break; 5765 case DRM_EDID_DIGITAL_DEPTH_16: 5766 info->bpc = 16; 5767 break; 5768 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5769 default: 5770 info->bpc = 0; 5771 break; 5772 } 5773 5774 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5775 connector->name, info->bpc); 5776 5777 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5778 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5779 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5780 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5781 5782 drm_update_mso(connector, drm_edid); 5783 5784 out: 5785 if (quirks & EDID_QUIRK_NON_DESKTOP) { 5786 drm_dbg_kms(connector->dev, "Non-desktop display%s\n", 5787 info->non_desktop ? " (redundant quirk)" : ""); 5788 info->non_desktop = true; 5789 } 5790 5791 return quirks; 5792 } 5793 5794 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5795 { 5796 struct drm_edid drm_edid; 5797 5798 return update_display_info(connector, 5799 drm_edid_legacy_init(&drm_edid, edid)); 5800 } 5801 5802 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5803 struct displayid_detailed_timings_1 *timings, 5804 bool type_7) 5805 { 5806 struct drm_display_mode *mode; 5807 unsigned pixel_clock = (timings->pixel_clock[0] | 5808 (timings->pixel_clock[1] << 8) | 5809 (timings->pixel_clock[2] << 16)) + 1; 5810 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5811 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5812 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5813 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5814 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5815 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5816 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5817 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5818 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5819 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5820 5821 mode = drm_mode_create(dev); 5822 if (!mode) 5823 return NULL; 5824 5825 /* resolution is kHz for type VII, and 10 kHz for type I */ 5826 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 5827 mode->hdisplay = hactive; 5828 mode->hsync_start = mode->hdisplay + hsync; 5829 mode->hsync_end = mode->hsync_start + hsync_width; 5830 mode->htotal = mode->hdisplay + hblank; 5831 5832 mode->vdisplay = vactive; 5833 mode->vsync_start = mode->vdisplay + vsync; 5834 mode->vsync_end = mode->vsync_start + vsync_width; 5835 mode->vtotal = mode->vdisplay + vblank; 5836 5837 mode->flags = 0; 5838 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5839 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5840 mode->type = DRM_MODE_TYPE_DRIVER; 5841 5842 if (timings->flags & 0x80) 5843 mode->type |= DRM_MODE_TYPE_PREFERRED; 5844 drm_mode_set_name(mode); 5845 5846 return mode; 5847 } 5848 5849 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5850 const struct displayid_block *block) 5851 { 5852 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5853 int i; 5854 int num_timings; 5855 struct drm_display_mode *newmode; 5856 int num_modes = 0; 5857 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 5858 /* blocks must be multiple of 20 bytes length */ 5859 if (block->num_bytes % 20) 5860 return 0; 5861 5862 num_timings = block->num_bytes / 20; 5863 for (i = 0; i < num_timings; i++) { 5864 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5865 5866 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 5867 if (!newmode) 5868 continue; 5869 5870 drm_mode_probed_add(connector, newmode); 5871 num_modes++; 5872 } 5873 return num_modes; 5874 } 5875 5876 static int add_displayid_detailed_modes(struct drm_connector *connector, 5877 const struct drm_edid *drm_edid) 5878 { 5879 const struct displayid_block *block; 5880 struct displayid_iter iter; 5881 int num_modes = 0; 5882 5883 displayid_iter_edid_begin(drm_edid, &iter); 5884 displayid_iter_for_each(block, &iter) { 5885 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 5886 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 5887 num_modes += add_displayid_detailed_1_modes(connector, block); 5888 } 5889 displayid_iter_end(&iter); 5890 5891 return num_modes; 5892 } 5893 5894 static int drm_edid_connector_update(struct drm_connector *connector, 5895 const struct drm_edid *drm_edid) 5896 { 5897 int num_modes = 0; 5898 u32 quirks; 5899 5900 if (!drm_edid) { 5901 drm_reset_display_info(connector); 5902 clear_eld(connector); 5903 return 0; 5904 } 5905 5906 /* 5907 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5908 * To avoid multiple parsing of same block, lets parse that map 5909 * from sink info, before parsing CEA modes. 5910 */ 5911 quirks = update_display_info(connector, drm_edid); 5912 5913 /* Depends on info->cea_rev set by update_display_info() above */ 5914 drm_edid_to_eld(connector, drm_edid); 5915 5916 /* 5917 * EDID spec says modes should be preferred in this order: 5918 * - preferred detailed mode 5919 * - other detailed modes from base block 5920 * - detailed modes from extension blocks 5921 * - CVT 3-byte code modes 5922 * - standard timing codes 5923 * - established timing codes 5924 * - modes inferred from GTF or CVT range information 5925 * 5926 * We get this pretty much right. 5927 * 5928 * XXX order for additional mode types in extension blocks? 5929 */ 5930 num_modes += add_detailed_modes(connector, drm_edid, quirks); 5931 num_modes += add_cvt_modes(connector, drm_edid); 5932 num_modes += add_standard_modes(connector, drm_edid); 5933 num_modes += add_established_modes(connector, drm_edid); 5934 num_modes += add_cea_modes(connector, drm_edid); 5935 num_modes += add_alternate_cea_modes(connector, drm_edid); 5936 num_modes += add_displayid_detailed_modes(connector, drm_edid); 5937 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5938 num_modes += add_inferred_modes(connector, drm_edid); 5939 5940 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5941 edid_fixup_preferred(connector, quirks); 5942 5943 if (quirks & EDID_QUIRK_FORCE_6BPC) 5944 connector->display_info.bpc = 6; 5945 5946 if (quirks & EDID_QUIRK_FORCE_8BPC) 5947 connector->display_info.bpc = 8; 5948 5949 if (quirks & EDID_QUIRK_FORCE_10BPC) 5950 connector->display_info.bpc = 10; 5951 5952 if (quirks & EDID_QUIRK_FORCE_12BPC) 5953 connector->display_info.bpc = 12; 5954 5955 return num_modes; 5956 } 5957 5958 /** 5959 * drm_add_edid_modes - add modes from EDID data, if available 5960 * @connector: connector we're probing 5961 * @edid: EDID data 5962 * 5963 * Add the specified modes to the connector's mode list. Also fills out the 5964 * &drm_display_info structure and ELD in @connector with any information which 5965 * can be derived from the edid. 5966 * 5967 * Return: The number of modes added or 0 if we couldn't find any. 5968 */ 5969 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5970 { 5971 struct drm_edid drm_edid; 5972 5973 if (edid && !drm_edid_is_valid(edid)) { 5974 drm_warn(connector->dev, "%s: EDID invalid.\n", 5975 connector->name); 5976 edid = NULL; 5977 } 5978 5979 return drm_edid_connector_update(connector, 5980 drm_edid_legacy_init(&drm_edid, edid)); 5981 } 5982 EXPORT_SYMBOL(drm_add_edid_modes); 5983 5984 /** 5985 * drm_add_modes_noedid - add modes for the connectors without EDID 5986 * @connector: connector we're probing 5987 * @hdisplay: the horizontal display limit 5988 * @vdisplay: the vertical display limit 5989 * 5990 * Add the specified modes to the connector's mode list. Only when the 5991 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5992 * 5993 * Return: The number of modes added or 0 if we couldn't find any. 5994 */ 5995 int drm_add_modes_noedid(struct drm_connector *connector, 5996 int hdisplay, int vdisplay) 5997 { 5998 int i, count, num_modes = 0; 5999 struct drm_display_mode *mode; 6000 struct drm_device *dev = connector->dev; 6001 6002 count = ARRAY_SIZE(drm_dmt_modes); 6003 if (hdisplay < 0) 6004 hdisplay = 0; 6005 if (vdisplay < 0) 6006 vdisplay = 0; 6007 6008 for (i = 0; i < count; i++) { 6009 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6010 6011 if (hdisplay && vdisplay) { 6012 /* 6013 * Only when two are valid, they will be used to check 6014 * whether the mode should be added to the mode list of 6015 * the connector. 6016 */ 6017 if (ptr->hdisplay > hdisplay || 6018 ptr->vdisplay > vdisplay) 6019 continue; 6020 } 6021 if (drm_mode_vrefresh(ptr) > 61) 6022 continue; 6023 mode = drm_mode_duplicate(dev, ptr); 6024 if (mode) { 6025 drm_mode_probed_add(connector, mode); 6026 num_modes++; 6027 } 6028 } 6029 return num_modes; 6030 } 6031 EXPORT_SYMBOL(drm_add_modes_noedid); 6032 6033 /** 6034 * drm_set_preferred_mode - Sets the preferred mode of a connector 6035 * @connector: connector whose mode list should be processed 6036 * @hpref: horizontal resolution of preferred mode 6037 * @vpref: vertical resolution of preferred mode 6038 * 6039 * Marks a mode as preferred if it matches the resolution specified by @hpref 6040 * and @vpref. 6041 */ 6042 void drm_set_preferred_mode(struct drm_connector *connector, 6043 int hpref, int vpref) 6044 { 6045 struct drm_display_mode *mode; 6046 6047 list_for_each_entry(mode, &connector->probed_modes, head) { 6048 if (mode->hdisplay == hpref && 6049 mode->vdisplay == vpref) 6050 mode->type |= DRM_MODE_TYPE_PREFERRED; 6051 } 6052 } 6053 EXPORT_SYMBOL(drm_set_preferred_mode); 6054 6055 static bool is_hdmi2_sink(const struct drm_connector *connector) 6056 { 6057 /* 6058 * FIXME: sil-sii8620 doesn't have a connector around when 6059 * we need one, so we have to be prepared for a NULL connector. 6060 */ 6061 if (!connector) 6062 return true; 6063 6064 return connector->display_info.hdmi.scdc.supported || 6065 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6066 } 6067 6068 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6069 const struct drm_display_mode *mode) 6070 { 6071 bool has_hdmi_infoframe = connector ? 6072 connector->display_info.has_hdmi_infoframe : false; 6073 6074 if (!has_hdmi_infoframe) 6075 return 0; 6076 6077 /* No HDMI VIC when signalling 3D video format */ 6078 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 6079 return 0; 6080 6081 return drm_match_hdmi_mode(mode); 6082 } 6083 6084 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 6085 const struct drm_display_mode *mode) 6086 { 6087 u8 vic; 6088 6089 /* 6090 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 6091 * we should send its VIC in vendor infoframes, else send the 6092 * VIC in AVI infoframes. Lets check if this mode is present in 6093 * HDMI 1.4b 4K modes 6094 */ 6095 if (drm_mode_hdmi_vic(connector, mode)) 6096 return 0; 6097 6098 vic = drm_match_cea_mode(mode); 6099 6100 /* 6101 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 6102 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 6103 * have to make sure we dont break HDMI 1.4 sinks. 6104 */ 6105 if (!is_hdmi2_sink(connector) && vic > 64) 6106 return 0; 6107 6108 return vic; 6109 } 6110 6111 /** 6112 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 6113 * data from a DRM display mode 6114 * @frame: HDMI AVI infoframe 6115 * @connector: the connector 6116 * @mode: DRM display mode 6117 * 6118 * Return: 0 on success or a negative error code on failure. 6119 */ 6120 int 6121 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 6122 const struct drm_connector *connector, 6123 const struct drm_display_mode *mode) 6124 { 6125 enum hdmi_picture_aspect picture_aspect; 6126 u8 vic, hdmi_vic; 6127 6128 if (!frame || !mode) 6129 return -EINVAL; 6130 6131 hdmi_avi_infoframe_init(frame); 6132 6133 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 6134 frame->pixel_repeat = 1; 6135 6136 vic = drm_mode_cea_vic(connector, mode); 6137 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 6138 6139 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6140 6141 /* 6142 * As some drivers don't support atomic, we can't use connector state. 6143 * So just initialize the frame with default values, just the same way 6144 * as it's done with other properties here. 6145 */ 6146 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 6147 frame->itc = 0; 6148 6149 /* 6150 * Populate picture aspect ratio from either 6151 * user input (if specified) or from the CEA/HDMI mode lists. 6152 */ 6153 picture_aspect = mode->picture_aspect_ratio; 6154 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 6155 if (vic) 6156 picture_aspect = drm_get_cea_aspect_ratio(vic); 6157 else if (hdmi_vic) 6158 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 6159 } 6160 6161 /* 6162 * The infoframe can't convey anything but none, 4:3 6163 * and 16:9, so if the user has asked for anything else 6164 * we can only satisfy it by specifying the right VIC. 6165 */ 6166 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 6167 if (vic) { 6168 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 6169 return -EINVAL; 6170 } else if (hdmi_vic) { 6171 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 6172 return -EINVAL; 6173 } else { 6174 return -EINVAL; 6175 } 6176 6177 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6178 } 6179 6180 frame->video_code = vic; 6181 frame->picture_aspect = picture_aspect; 6182 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 6183 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 6184 6185 return 0; 6186 } 6187 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 6188 6189 /** 6190 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 6191 * quantization range information 6192 * @frame: HDMI AVI infoframe 6193 * @connector: the connector 6194 * @mode: DRM display mode 6195 * @rgb_quant_range: RGB quantization range (Q) 6196 */ 6197 void 6198 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6199 const struct drm_connector *connector, 6200 const struct drm_display_mode *mode, 6201 enum hdmi_quantization_range rgb_quant_range) 6202 { 6203 const struct drm_display_info *info = &connector->display_info; 6204 6205 /* 6206 * CEA-861: 6207 * "A Source shall not send a non-zero Q value that does not correspond 6208 * to the default RGB Quantization Range for the transmitted Picture 6209 * unless the Sink indicates support for the Q bit in a Video 6210 * Capabilities Data Block." 6211 * 6212 * HDMI 2.0 recommends sending non-zero Q when it does match the 6213 * default RGB quantization range for the mode, even when QS=0. 6214 */ 6215 if (info->rgb_quant_range_selectable || 6216 rgb_quant_range == drm_default_rgb_quant_range(mode)) 6217 frame->quantization_range = rgb_quant_range; 6218 else 6219 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 6220 6221 /* 6222 * CEA-861-F: 6223 * "When transmitting any RGB colorimetry, the Source should set the 6224 * YQ-field to match the RGB Quantization Range being transmitted 6225 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 6226 * set YQ=1) and the Sink shall ignore the YQ-field." 6227 * 6228 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 6229 * by non-zero YQ when receiving RGB. There doesn't seem to be any 6230 * good way to tell which version of CEA-861 the sink supports, so 6231 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 6232 * on on CEA-861-F. 6233 */ 6234 if (!is_hdmi2_sink(connector) || 6235 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 6236 frame->ycc_quantization_range = 6237 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 6238 else 6239 frame->ycc_quantization_range = 6240 HDMI_YCC_QUANTIZATION_RANGE_FULL; 6241 } 6242 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 6243 6244 static enum hdmi_3d_structure 6245 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 6246 { 6247 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 6248 6249 switch (layout) { 6250 case DRM_MODE_FLAG_3D_FRAME_PACKING: 6251 return HDMI_3D_STRUCTURE_FRAME_PACKING; 6252 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 6253 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 6254 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 6255 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 6256 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 6257 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 6258 case DRM_MODE_FLAG_3D_L_DEPTH: 6259 return HDMI_3D_STRUCTURE_L_DEPTH; 6260 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 6261 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 6262 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 6263 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 6264 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 6265 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 6266 default: 6267 return HDMI_3D_STRUCTURE_INVALID; 6268 } 6269 } 6270 6271 /** 6272 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 6273 * data from a DRM display mode 6274 * @frame: HDMI vendor infoframe 6275 * @connector: the connector 6276 * @mode: DRM display mode 6277 * 6278 * Note that there's is a need to send HDMI vendor infoframes only when using a 6279 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 6280 * function will return -EINVAL, error that can be safely ignored. 6281 * 6282 * Return: 0 on success or a negative error code on failure. 6283 */ 6284 int 6285 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 6286 const struct drm_connector *connector, 6287 const struct drm_display_mode *mode) 6288 { 6289 /* 6290 * FIXME: sil-sii8620 doesn't have a connector around when 6291 * we need one, so we have to be prepared for a NULL connector. 6292 */ 6293 bool has_hdmi_infoframe = connector ? 6294 connector->display_info.has_hdmi_infoframe : false; 6295 int err; 6296 6297 if (!frame || !mode) 6298 return -EINVAL; 6299 6300 if (!has_hdmi_infoframe) 6301 return -EINVAL; 6302 6303 err = hdmi_vendor_infoframe_init(frame); 6304 if (err < 0) 6305 return err; 6306 6307 /* 6308 * Even if it's not absolutely necessary to send the infoframe 6309 * (ie.vic==0 and s3d_struct==0) we will still send it if we 6310 * know that the sink can handle it. This is based on a 6311 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 6312 * have trouble realizing that they should switch from 3D to 2D 6313 * mode if the source simply stops sending the infoframe when 6314 * it wants to switch from 3D to 2D. 6315 */ 6316 frame->vic = drm_mode_hdmi_vic(connector, mode); 6317 frame->s3d_struct = s3d_structure_from_display_mode(mode); 6318 6319 return 0; 6320 } 6321 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 6322 6323 static void drm_parse_tiled_block(struct drm_connector *connector, 6324 const struct displayid_block *block) 6325 { 6326 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6327 u16 w, h; 6328 u8 tile_v_loc, tile_h_loc; 6329 u8 num_v_tile, num_h_tile; 6330 struct drm_tile_group *tg; 6331 6332 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6333 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6334 6335 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6336 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6337 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6338 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6339 6340 connector->has_tile = true; 6341 if (tile->tile_cap & 0x80) 6342 connector->tile_is_single_monitor = true; 6343 6344 connector->num_h_tile = num_h_tile + 1; 6345 connector->num_v_tile = num_v_tile + 1; 6346 connector->tile_h_loc = tile_h_loc; 6347 connector->tile_v_loc = tile_v_loc; 6348 connector->tile_h_size = w + 1; 6349 connector->tile_v_size = h + 1; 6350 6351 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6352 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6353 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6354 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6355 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6356 6357 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6358 if (!tg) 6359 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6360 if (!tg) 6361 return; 6362 6363 if (connector->tile_group != tg) { 6364 /* if we haven't got a pointer, 6365 take the reference, drop ref to old tile group */ 6366 if (connector->tile_group) 6367 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6368 connector->tile_group = tg; 6369 } else { 6370 /* if same tile group, then release the ref we just took. */ 6371 drm_mode_put_tile_group(connector->dev, tg); 6372 } 6373 } 6374 6375 static void _drm_update_tile_info(struct drm_connector *connector, 6376 const struct drm_edid *drm_edid) 6377 { 6378 const struct displayid_block *block; 6379 struct displayid_iter iter; 6380 6381 connector->has_tile = false; 6382 6383 displayid_iter_edid_begin(drm_edid, &iter); 6384 displayid_iter_for_each(block, &iter) { 6385 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6386 drm_parse_tiled_block(connector, block); 6387 } 6388 displayid_iter_end(&iter); 6389 6390 if (!connector->has_tile && connector->tile_group) { 6391 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6392 connector->tile_group = NULL; 6393 } 6394 } 6395 6396 void drm_update_tile_info(struct drm_connector *connector, 6397 const struct edid *edid) 6398 { 6399 struct drm_edid drm_edid; 6400 6401 _drm_update_tile_info(connector, drm_edid_legacy_init(&drm_edid, edid)); 6402 } 6403