1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 int modes; 100 }; 101 102 #define LEVEL_DMT 0 103 #define LEVEL_GTF 1 104 #define LEVEL_GTF2 2 105 #define LEVEL_CVT 3 106 107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 108 { \ 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 110 product_id), \ 111 .quirks = _quirks \ 112 } 113 114 static const struct edid_quirk { 115 u32 panel_id; 116 u32 quirks; 117 } edid_quirk_list[] = { 118 /* Acer AL1706 */ 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 120 /* Acer F51 */ 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 122 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 125 126 /* BenQ GW2765 */ 127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC), 128 129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 131 132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 134 135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 137 138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 140 141 /* Belinea 10 15 55 */ 142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 144 145 /* Envision Peripherals, Inc. EN-7100e */ 146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 147 /* Envision EN2028 */ 148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 149 150 /* Funai Electronics PM36B */ 151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 152 EDID_QUIRK_DETAILED_IN_CM), 153 154 /* LG 27GP950 */ 155 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 156 157 /* LG 27GN950 */ 158 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 159 160 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 161 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 162 163 /* LG Philips LCD LP154W01-A5 */ 164 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 165 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 166 167 /* Samsung SyncMaster 205BW. Note: irony */ 168 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 169 /* Samsung SyncMaster 22[5-6]BW */ 170 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 171 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 172 173 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 174 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 175 176 /* ViewSonic VA2026w */ 177 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 178 179 /* Medion MD 30217 PG */ 180 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 181 182 /* Lenovo G50 */ 183 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 184 185 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 186 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 187 188 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 189 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 190 191 /* Valve Index Headset */ 192 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 209 210 /* HTC Vive and Vive Pro VR Headsets */ 211 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 213 214 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 215 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 219 220 /* Windows Mixed Reality Headsets */ 221 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 224 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 225 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 226 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 227 228 /* Sony PlayStation VR Headset */ 229 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 230 231 /* Sensics VR Headsets */ 232 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 233 234 /* OSVR HDK and HDK2 VR Headsets */ 235 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 236 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 237 }; 238 239 /* 240 * Autogenerated from the DMT spec. 241 * This table is copied from xfree86/modes/xf86EdidModes.c. 242 */ 243 static const struct drm_display_mode drm_dmt_modes[] = { 244 /* 0x01 - 640x350@85Hz */ 245 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 246 736, 832, 0, 350, 382, 385, 445, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x02 - 640x400@85Hz */ 249 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 250 736, 832, 0, 400, 401, 404, 445, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x03 - 720x400@85Hz */ 253 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 254 828, 936, 0, 400, 401, 404, 446, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x04 - 640x480@60Hz */ 257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 258 752, 800, 0, 480, 490, 492, 525, 0, 259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x05 - 640x480@72Hz */ 261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 262 704, 832, 0, 480, 489, 492, 520, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 264 /* 0x06 - 640x480@75Hz */ 265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 266 720, 840, 0, 480, 481, 484, 500, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x07 - 640x480@85Hz */ 269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 270 752, 832, 0, 480, 481, 484, 509, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 0x08 - 800x600@56Hz */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 274 896, 1024, 0, 600, 601, 603, 625, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x09 - 800x600@60Hz */ 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 278 968, 1056, 0, 600, 601, 605, 628, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0a - 800x600@72Hz */ 281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 282 976, 1040, 0, 600, 637, 643, 666, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x0b - 800x600@75Hz */ 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 286 896, 1056, 0, 600, 601, 604, 625, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x0c - 800x600@85Hz */ 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 290 896, 1048, 0, 600, 601, 604, 631, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x0d - 800x600@120Hz RB */ 293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 294 880, 960, 0, 600, 603, 607, 636, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x0e - 848x480@60Hz */ 297 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 298 976, 1088, 0, 480, 486, 494, 517, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x0f - 1024x768@43Hz, interlace */ 301 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 302 1208, 1264, 0, 768, 768, 776, 817, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 304 DRM_MODE_FLAG_INTERLACE) }, 305 /* 0x10 - 1024x768@60Hz */ 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 307 1184, 1344, 0, 768, 771, 777, 806, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x11 - 1024x768@70Hz */ 310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 311 1184, 1328, 0, 768, 771, 777, 806, 0, 312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 0x12 - 1024x768@75Hz */ 314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 315 1136, 1312, 0, 768, 769, 772, 800, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x13 - 1024x768@85Hz */ 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 319 1168, 1376, 0, 768, 769, 772, 808, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x14 - 1024x768@120Hz RB */ 322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 323 1104, 1184, 0, 768, 771, 775, 813, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 325 /* 0x15 - 1152x864@75Hz */ 326 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 327 1344, 1600, 0, 864, 865, 868, 900, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x55 - 1280x720@60Hz */ 330 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 331 1430, 1650, 0, 720, 725, 730, 750, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x16 - 1280x768@60Hz RB */ 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 335 1360, 1440, 0, 768, 771, 778, 790, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x17 - 1280x768@60Hz */ 338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 339 1472, 1664, 0, 768, 771, 778, 798, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x18 - 1280x768@75Hz */ 342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 343 1488, 1696, 0, 768, 771, 778, 805, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x19 - 1280x768@85Hz */ 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 347 1496, 1712, 0, 768, 771, 778, 809, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1a - 1280x768@120Hz RB */ 350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 351 1360, 1440, 0, 768, 771, 778, 813, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x1b - 1280x800@60Hz RB */ 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 355 1360, 1440, 0, 800, 803, 809, 823, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 357 /* 0x1c - 1280x800@60Hz */ 358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 359 1480, 1680, 0, 800, 803, 809, 831, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x1d - 1280x800@75Hz */ 362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 363 1488, 1696, 0, 800, 803, 809, 838, 0, 364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x1e - 1280x800@85Hz */ 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 367 1496, 1712, 0, 800, 803, 809, 843, 0, 368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x1f - 1280x800@120Hz RB */ 370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 371 1360, 1440, 0, 800, 803, 809, 847, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 373 /* 0x20 - 1280x960@60Hz */ 374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 375 1488, 1800, 0, 960, 961, 964, 1000, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x21 - 1280x960@85Hz */ 378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 379 1504, 1728, 0, 960, 961, 964, 1011, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x22 - 1280x960@120Hz RB */ 382 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 383 1360, 1440, 0, 960, 963, 967, 1017, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 385 /* 0x23 - 1280x1024@60Hz */ 386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x24 - 1280x1024@75Hz */ 390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 391 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x25 - 1280x1024@85Hz */ 394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 395 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x26 - 1280x1024@120Hz RB */ 398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 399 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x27 - 1360x768@60Hz */ 402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 403 1536, 1792, 0, 768, 771, 777, 795, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x28 - 1360x768@120Hz RB */ 406 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 407 1440, 1520, 0, 768, 771, 776, 813, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 409 /* 0x51 - 1366x768@60Hz */ 410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 411 1579, 1792, 0, 768, 771, 774, 798, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x56 - 1366x768@60Hz */ 414 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 415 1436, 1500, 0, 768, 769, 772, 800, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x29 - 1400x1050@60Hz RB */ 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 419 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2a - 1400x1050@60Hz */ 422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 423 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x2b - 1400x1050@75Hz */ 426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 427 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x2c - 1400x1050@85Hz */ 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 431 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x2d - 1400x1050@120Hz RB */ 434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 435 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x2e - 1440x900@60Hz RB */ 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 439 1520, 1600, 0, 900, 903, 909, 926, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x2f - 1440x900@60Hz */ 442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 443 1672, 1904, 0, 900, 903, 909, 934, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x30 - 1440x900@75Hz */ 446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 447 1688, 1936, 0, 900, 903, 909, 942, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x31 - 1440x900@85Hz */ 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 451 1696, 1952, 0, 900, 903, 909, 948, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x32 - 1440x900@120Hz RB */ 454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 455 1520, 1600, 0, 900, 903, 909, 953, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 457 /* 0x53 - 1600x900@60Hz */ 458 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 459 1704, 1800, 0, 900, 901, 904, 1000, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x33 - 1600x1200@60Hz */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x34 - 1600x1200@65Hz */ 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x35 - 1600x1200@70Hz */ 470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x36 - 1600x1200@75Hz */ 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x37 - 1600x1200@85Hz */ 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x38 - 1600x1200@120Hz RB */ 482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 483 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x39 - 1680x1050@60Hz RB */ 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 487 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 489 /* 0x3a - 1680x1050@60Hz */ 490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 491 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x3b - 1680x1050@75Hz */ 494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 495 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x3c - 1680x1050@85Hz */ 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 499 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x3d - 1680x1050@120Hz RB */ 502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 503 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 /* 0x3e - 1792x1344@60Hz */ 506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 507 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x3f - 1792x1344@75Hz */ 510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 511 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 513 /* 0x40 - 1792x1344@120Hz RB */ 514 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 515 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x41 - 1856x1392@60Hz */ 518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 519 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x42 - 1856x1392@75Hz */ 522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 523 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x43 - 1856x1392@120Hz RB */ 526 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 527 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 529 /* 0x52 - 1920x1080@60Hz */ 530 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 531 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x44 - 1920x1200@60Hz RB */ 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 535 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 537 /* 0x45 - 1920x1200@60Hz */ 538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 539 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x46 - 1920x1200@75Hz */ 542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 543 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 545 /* 0x47 - 1920x1200@85Hz */ 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 547 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x48 - 1920x1200@120Hz RB */ 550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 551 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x49 - 1920x1440@60Hz */ 554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 555 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4a - 1920x1440@75Hz */ 558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 559 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4b - 1920x1440@120Hz RB */ 562 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 563 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 565 /* 0x54 - 2048x1152@60Hz */ 566 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 567 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 569 /* 0x4c - 2560x1600@60Hz RB */ 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 571 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x4d - 2560x1600@60Hz */ 574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 575 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 577 /* 0x4e - 2560x1600@75Hz */ 578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 579 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 581 /* 0x4f - 2560x1600@85Hz */ 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 583 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 584 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 585 /* 0x50 - 2560x1600@120Hz RB */ 586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 587 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 589 /* 0x57 - 4096x2160@60Hz RB */ 590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 593 /* 0x58 - 4096x2160@59.94Hz RB */ 594 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 595 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 597 }; 598 599 /* 600 * These more or less come from the DMT spec. The 720x400 modes are 601 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 602 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 603 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 604 * mode. 605 * 606 * The DMT modes have been fact-checked; the rest are mild guesses. 607 */ 608 static const struct drm_display_mode edid_est_modes[] = { 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 610 968, 1056, 0, 600, 601, 605, 628, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 613 896, 1024, 0, 600, 601, 603, 625, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 616 720, 840, 0, 480, 481, 484, 500, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 619 704, 832, 0, 480, 489, 492, 520, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 622 768, 864, 0, 480, 483, 486, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 625 752, 800, 0, 480, 490, 492, 525, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 628 846, 900, 0, 400, 421, 423, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 631 846, 900, 0, 400, 412, 414, 449, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 633 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 634 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 637 1136, 1312, 0, 768, 769, 772, 800, 0, 638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 640 1184, 1328, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 643 1184, 1344, 0, 768, 771, 777, 806, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 645 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 646 1208, 1264, 0, 768, 768, 776, 817, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 648 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 649 928, 1152, 0, 624, 625, 628, 667, 0, 650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 652 896, 1056, 0, 600, 601, 604, 625, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 655 976, 1040, 0, 600, 637, 643, 666, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 657 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 658 1344, 1600, 0, 864, 865, 868, 900, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 660 }; 661 662 struct minimode { 663 short w; 664 short h; 665 short r; 666 short rb; 667 }; 668 669 static const struct minimode est3_modes[] = { 670 /* byte 6 */ 671 { 640, 350, 85, 0 }, 672 { 640, 400, 85, 0 }, 673 { 720, 400, 85, 0 }, 674 { 640, 480, 85, 0 }, 675 { 848, 480, 60, 0 }, 676 { 800, 600, 85, 0 }, 677 { 1024, 768, 85, 0 }, 678 { 1152, 864, 75, 0 }, 679 /* byte 7 */ 680 { 1280, 768, 60, 1 }, 681 { 1280, 768, 60, 0 }, 682 { 1280, 768, 75, 0 }, 683 { 1280, 768, 85, 0 }, 684 { 1280, 960, 60, 0 }, 685 { 1280, 960, 85, 0 }, 686 { 1280, 1024, 60, 0 }, 687 { 1280, 1024, 85, 0 }, 688 /* byte 8 */ 689 { 1360, 768, 60, 0 }, 690 { 1440, 900, 60, 1 }, 691 { 1440, 900, 60, 0 }, 692 { 1440, 900, 75, 0 }, 693 { 1440, 900, 85, 0 }, 694 { 1400, 1050, 60, 1 }, 695 { 1400, 1050, 60, 0 }, 696 { 1400, 1050, 75, 0 }, 697 /* byte 9 */ 698 { 1400, 1050, 85, 0 }, 699 { 1680, 1050, 60, 1 }, 700 { 1680, 1050, 60, 0 }, 701 { 1680, 1050, 75, 0 }, 702 { 1680, 1050, 85, 0 }, 703 { 1600, 1200, 60, 0 }, 704 { 1600, 1200, 65, 0 }, 705 { 1600, 1200, 70, 0 }, 706 /* byte 10 */ 707 { 1600, 1200, 75, 0 }, 708 { 1600, 1200, 85, 0 }, 709 { 1792, 1344, 60, 0 }, 710 { 1792, 1344, 75, 0 }, 711 { 1856, 1392, 60, 0 }, 712 { 1856, 1392, 75, 0 }, 713 { 1920, 1200, 60, 1 }, 714 { 1920, 1200, 60, 0 }, 715 /* byte 11 */ 716 { 1920, 1200, 75, 0 }, 717 { 1920, 1200, 85, 0 }, 718 { 1920, 1440, 60, 0 }, 719 { 1920, 1440, 75, 0 }, 720 }; 721 722 static const struct minimode extra_modes[] = { 723 { 1024, 576, 60, 0 }, 724 { 1366, 768, 60, 0 }, 725 { 1600, 900, 60, 0 }, 726 { 1680, 945, 60, 0 }, 727 { 1920, 1080, 60, 0 }, 728 { 2048, 1152, 60, 0 }, 729 { 2048, 1536, 60, 0 }, 730 }; 731 732 /* 733 * From CEA/CTA-861 spec. 734 * 735 * Do not access directly, instead always use cea_mode_for_vic(). 736 */ 737 static const struct drm_display_mode edid_cea_modes_1[] = { 738 /* 1 - 640x480@60Hz 4:3 */ 739 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 740 752, 800, 0, 480, 490, 492, 525, 0, 741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 742 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 743 /* 2 - 720x480@60Hz 4:3 */ 744 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 745 798, 858, 0, 480, 489, 495, 525, 0, 746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 747 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 748 /* 3 - 720x480@60Hz 16:9 */ 749 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 750 798, 858, 0, 480, 489, 495, 525, 0, 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 4 - 1280x720@60Hz 16:9 */ 754 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 755 1430, 1650, 0, 720, 725, 730, 750, 0, 756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 5 - 1920x1080i@60Hz 16:9 */ 759 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 760 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 762 DRM_MODE_FLAG_INTERLACE), 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 764 /* 6 - 720(1440)x480i@60Hz 4:3 */ 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 480, 488, 494, 525, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 770 /* 7 - 720(1440)x480i@60Hz 16:9 */ 771 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 772 801, 858, 0, 480, 488, 494, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 8 - 720(1440)x240@60Hz 4:3 */ 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 778 801, 858, 0, 240, 244, 247, 262, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_DBLCLK), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 782 /* 9 - 720(1440)x240@60Hz 16:9 */ 783 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 784 801, 858, 0, 240, 244, 247, 262, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 786 DRM_MODE_FLAG_DBLCLK), 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 10 - 2880x480i@60Hz 4:3 */ 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 480, 488, 494, 525, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 792 DRM_MODE_FLAG_INTERLACE), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 11 - 2880x480i@60Hz 16:9 */ 795 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 480, 488, 494, 525, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 798 DRM_MODE_FLAG_INTERLACE), 799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 12 - 2880x240@60Hz 4:3 */ 801 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 802 3204, 3432, 0, 240, 244, 247, 262, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 13 - 2880x240@60Hz 16:9 */ 806 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 807 3204, 3432, 0, 240, 244, 247, 262, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 810 /* 14 - 1440x480@60Hz 4:3 */ 811 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 812 1596, 1716, 0, 480, 489, 495, 525, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 815 /* 15 - 1440x480@60Hz 16:9 */ 816 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 817 1596, 1716, 0, 480, 489, 495, 525, 0, 818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 16 - 1920x1080@60Hz 16:9 */ 821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 822 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 824 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 17 - 720x576@50Hz 4:3 */ 826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 827 796, 864, 0, 576, 581, 586, 625, 0, 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 829 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 830 /* 18 - 720x576@50Hz 16:9 */ 831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 832 796, 864, 0, 576, 581, 586, 625, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 19 - 1280x720@50Hz 16:9 */ 836 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 837 1760, 1980, 0, 720, 725, 730, 750, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 20 - 1920x1080i@50Hz 16:9 */ 841 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 842 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 844 DRM_MODE_FLAG_INTERLACE), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 21 - 720(1440)x576i@50Hz 4:3 */ 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 576, 580, 586, 625, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 852 /* 22 - 720(1440)x576i@50Hz 16:9 */ 853 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 854 795, 864, 0, 576, 580, 586, 625, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 23 - 720(1440)x288@50Hz 4:3 */ 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 860 795, 864, 0, 288, 290, 293, 312, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_DBLCLK), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 24 - 720(1440)x288@50Hz 16:9 */ 865 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 866 795, 864, 0, 288, 290, 293, 312, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 868 DRM_MODE_FLAG_DBLCLK), 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 25 - 2880x576i@50Hz 4:3 */ 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 576, 580, 586, 625, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 874 DRM_MODE_FLAG_INTERLACE), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 26 - 2880x576i@50Hz 16:9 */ 877 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 576, 580, 586, 625, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE), 881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 27 - 2880x288@50Hz 4:3 */ 883 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 884 3180, 3456, 0, 288, 290, 293, 312, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 887 /* 28 - 2880x288@50Hz 16:9 */ 888 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 889 3180, 3456, 0, 288, 290, 293, 312, 0, 890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 29 - 1440x576@50Hz 4:3 */ 893 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 894 1592, 1728, 0, 576, 581, 586, 625, 0, 895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 897 /* 30 - 1440x576@50Hz 16:9 */ 898 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 899 1592, 1728, 0, 576, 581, 586, 625, 0, 900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 31 - 1920x1080@50Hz 16:9 */ 903 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 904 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 32 - 1920x1080@24Hz 16:9 */ 908 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 909 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 33 - 1920x1080@25Hz 16:9 */ 913 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 914 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 917 /* 34 - 1920x1080@30Hz 16:9 */ 918 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 919 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 35 - 2880x480@60Hz 4:3 */ 923 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 924 3192, 3432, 0, 480, 489, 495, 525, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 926 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 36 - 2880x480@60Hz 16:9 */ 928 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 929 3192, 3432, 0, 480, 489, 495, 525, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 931 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 932 /* 37 - 2880x576@50Hz 4:3 */ 933 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 934 3184, 3456, 0, 576, 581, 586, 625, 0, 935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 937 /* 38 - 2880x576@50Hz 16:9 */ 938 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 939 3184, 3456, 0, 576, 581, 586, 625, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 39 - 1920x1080i@50Hz 16:9 */ 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 944 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 946 DRM_MODE_FLAG_INTERLACE), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 40 - 1920x1080i@100Hz 16:9 */ 949 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 950 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 952 DRM_MODE_FLAG_INTERLACE), 953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 /* 41 - 1280x720@100Hz 16:9 */ 955 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 956 1760, 1980, 0, 720, 725, 730, 750, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 959 /* 42 - 720x576@100Hz 4:3 */ 960 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 961 796, 864, 0, 576, 581, 586, 625, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 43 - 720x576@100Hz 16:9 */ 965 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 966 796, 864, 0, 576, 581, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 44 - 720(1440)x576i@100Hz 4:3 */ 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 971 795, 864, 0, 576, 580, 586, 625, 0, 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 975 /* 45 - 720(1440)x576i@100Hz 16:9 */ 976 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 977 795, 864, 0, 576, 580, 586, 625, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 979 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 46 - 1920x1080i@120Hz 16:9 */ 982 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 983 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 985 DRM_MODE_FLAG_INTERLACE), 986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 987 /* 47 - 1280x720@120Hz 16:9 */ 988 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 989 1430, 1650, 0, 720, 725, 730, 750, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 991 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 48 - 720x480@120Hz 4:3 */ 993 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 994 798, 858, 0, 480, 489, 495, 525, 0, 995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 997 /* 49 - 720x480@120Hz 16:9 */ 998 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 999 798, 858, 0, 480, 489, 495, 525, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1004 801, 858, 0, 480, 488, 494, 525, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1008 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1010 801, 858, 0, 480, 488, 494, 525, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1014 /* 52 - 720x576@200Hz 4:3 */ 1015 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1016 796, 864, 0, 576, 581, 586, 625, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1019 /* 53 - 720x576@200Hz 16:9 */ 1020 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1021 796, 864, 0, 576, 581, 586, 625, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1024 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1026 795, 864, 0, 576, 580, 586, 625, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1030 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1031 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1032 795, 864, 0, 576, 580, 586, 625, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1034 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 56 - 720x480@240Hz 4:3 */ 1037 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1038 798, 858, 0, 480, 489, 495, 525, 0, 1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1041 /* 57 - 720x480@240Hz 16:9 */ 1042 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1043 798, 858, 0, 480, 489, 495, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1046 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1048 801, 858, 0, 480, 488, 494, 525, 0, 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1052 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1053 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1054 801, 858, 0, 480, 488, 494, 525, 0, 1055 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1056 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 60 - 1280x720@24Hz 16:9 */ 1059 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1060 3080, 3300, 0, 720, 725, 730, 750, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 61 - 1280x720@25Hz 16:9 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1065 3740, 3960, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1068 /* 62 - 1280x720@30Hz 16:9 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1070 3080, 3300, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1073 /* 63 - 1920x1080@120Hz 16:9 */ 1074 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1075 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1078 /* 64 - 1920x1080@100Hz 16:9 */ 1079 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1080 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1083 /* 65 - 1280x720@24Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1085 3080, 3300, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 66 - 1280x720@25Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1090 3740, 3960, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 67 - 1280x720@30Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1095 3080, 3300, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 68 - 1280x720@50Hz 64:27 */ 1099 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1100 1760, 1980, 0, 720, 725, 730, 750, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 69 - 1280x720@60Hz 64:27 */ 1104 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1105 1430, 1650, 0, 720, 725, 730, 750, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 70 - 1280x720@100Hz 64:27 */ 1109 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1110 1760, 1980, 0, 720, 725, 730, 750, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 71 - 1280x720@120Hz 64:27 */ 1114 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1115 1430, 1650, 0, 720, 725, 730, 750, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 72 - 1920x1080@24Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1120 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 73 - 1920x1080@25Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 74 - 1920x1080@30Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 75 - 1920x1080@50Hz 64:27 */ 1134 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1135 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 76 - 1920x1080@60Hz 64:27 */ 1139 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1140 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 77 - 1920x1080@100Hz 64:27 */ 1144 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1145 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 78 - 1920x1080@120Hz 64:27 */ 1149 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1150 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 79 - 1680x720@24Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1155 3080, 3300, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 80 - 1680x720@25Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1160 2948, 3168, 0, 720, 725, 730, 750, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 81 - 1680x720@30Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1165 2420, 2640, 0, 720, 725, 730, 750, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 82 - 1680x720@50Hz 64:27 */ 1169 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1170 1980, 2200, 0, 720, 725, 730, 750, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 83 - 1680x720@60Hz 64:27 */ 1174 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1175 1980, 2200, 0, 720, 725, 730, 750, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 84 - 1680x720@100Hz 64:27 */ 1179 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1180 1780, 2000, 0, 720, 725, 730, 825, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 85 - 1680x720@120Hz 64:27 */ 1184 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1185 1780, 2000, 0, 720, 725, 730, 825, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 86 - 2560x1080@24Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1190 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 87 - 2560x1080@25Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1195 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 88 - 2560x1080@30Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1200 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 89 - 2560x1080@50Hz 64:27 */ 1204 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1205 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1208 /* 90 - 2560x1080@60Hz 64:27 */ 1209 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1210 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1213 /* 91 - 2560x1080@100Hz 64:27 */ 1214 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1215 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1218 /* 92 - 2560x1080@120Hz 64:27 */ 1219 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1220 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1223 /* 93 - 3840x2160@24Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1225 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 94 - 3840x2160@25Hz 16:9 */ 1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1230 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1233 /* 95 - 3840x2160@30Hz 16:9 */ 1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1235 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1238 /* 96 - 3840x2160@50Hz 16:9 */ 1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1240 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1243 /* 97 - 3840x2160@60Hz 16:9 */ 1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1245 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1248 /* 98 - 4096x2160@24Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1250 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 99 - 4096x2160@25Hz 256:135 */ 1254 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1255 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1258 /* 100 - 4096x2160@30Hz 256:135 */ 1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1260 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1263 /* 101 - 4096x2160@50Hz 256:135 */ 1264 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1265 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1268 /* 102 - 4096x2160@60Hz 256:135 */ 1269 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1270 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1273 /* 103 - 3840x2160@24Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1275 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 /* 104 - 3840x2160@25Hz 64:27 */ 1279 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1280 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1283 /* 105 - 3840x2160@30Hz 64:27 */ 1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1285 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1288 /* 106 - 3840x2160@50Hz 64:27 */ 1289 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1290 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1293 /* 107 - 3840x2160@60Hz 64:27 */ 1294 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1295 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1298 /* 108 - 1280x720@48Hz 16:9 */ 1299 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1300 2280, 2500, 0, 720, 725, 730, 750, 0, 1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1303 /* 109 - 1280x720@48Hz 64:27 */ 1304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1305 2280, 2500, 0, 720, 725, 730, 750, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1308 /* 110 - 1680x720@48Hz 64:27 */ 1309 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1310 2530, 2750, 0, 720, 725, 730, 750, 0, 1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1313 /* 111 - 1920x1080@48Hz 16:9 */ 1314 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1315 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1318 /* 112 - 1920x1080@48Hz 64:27 */ 1319 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1320 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1323 /* 113 - 2560x1080@48Hz 64:27 */ 1324 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1325 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1328 /* 114 - 3840x2160@48Hz 16:9 */ 1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1330 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1333 /* 115 - 4096x2160@48Hz 256:135 */ 1334 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1335 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1338 /* 116 - 3840x2160@48Hz 64:27 */ 1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1340 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1343 /* 117 - 3840x2160@100Hz 16:9 */ 1344 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1345 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1348 /* 118 - 3840x2160@120Hz 16:9 */ 1349 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1350 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1353 /* 119 - 3840x2160@100Hz 64:27 */ 1354 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1355 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1358 /* 120 - 3840x2160@120Hz 64:27 */ 1359 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1360 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1363 /* 121 - 5120x2160@24Hz 64:27 */ 1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1365 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1368 /* 122 - 5120x2160@25Hz 64:27 */ 1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1370 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1373 /* 123 - 5120x2160@30Hz 64:27 */ 1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1375 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1378 /* 124 - 5120x2160@48Hz 64:27 */ 1379 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1380 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1382 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1383 /* 125 - 5120x2160@50Hz 64:27 */ 1384 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1385 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1387 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1388 /* 126 - 5120x2160@60Hz 64:27 */ 1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1393 /* 127 - 5120x2160@100Hz 64:27 */ 1394 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1395 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1398 }; 1399 1400 /* 1401 * From CEA/CTA-861 spec. 1402 * 1403 * Do not access directly, instead always use cea_mode_for_vic(). 1404 */ 1405 static const struct drm_display_mode edid_cea_modes_193[] = { 1406 /* 193 - 5120x2160@120Hz 64:27 */ 1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1408 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1411 /* 194 - 7680x4320@24Hz 16:9 */ 1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1413 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1416 /* 195 - 7680x4320@25Hz 16:9 */ 1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1418 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1421 /* 196 - 7680x4320@30Hz 16:9 */ 1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1423 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1426 /* 197 - 7680x4320@48Hz 16:9 */ 1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1428 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1431 /* 198 - 7680x4320@50Hz 16:9 */ 1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1433 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1436 /* 199 - 7680x4320@60Hz 16:9 */ 1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1438 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1441 /* 200 - 7680x4320@100Hz 16:9 */ 1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1443 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1446 /* 201 - 7680x4320@120Hz 16:9 */ 1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1448 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1451 /* 202 - 7680x4320@24Hz 64:27 */ 1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1453 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1456 /* 203 - 7680x4320@25Hz 64:27 */ 1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1458 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1461 /* 204 - 7680x4320@30Hz 64:27 */ 1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1463 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1466 /* 205 - 7680x4320@48Hz 64:27 */ 1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1468 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1471 /* 206 - 7680x4320@50Hz 64:27 */ 1472 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1473 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1476 /* 207 - 7680x4320@60Hz 64:27 */ 1477 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1478 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1481 /* 208 - 7680x4320@100Hz 64:27 */ 1482 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1483 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1486 /* 209 - 7680x4320@120Hz 64:27 */ 1487 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1488 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1491 /* 210 - 10240x4320@24Hz 64:27 */ 1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1493 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1496 /* 211 - 10240x4320@25Hz 64:27 */ 1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1498 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1501 /* 212 - 10240x4320@30Hz 64:27 */ 1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1503 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1506 /* 213 - 10240x4320@48Hz 64:27 */ 1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1508 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1511 /* 214 - 10240x4320@50Hz 64:27 */ 1512 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1513 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1516 /* 215 - 10240x4320@60Hz 64:27 */ 1517 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1518 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1521 /* 216 - 10240x4320@100Hz 64:27 */ 1522 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1523 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1525 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1526 /* 217 - 10240x4320@120Hz 64:27 */ 1527 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1528 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1530 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1531 /* 218 - 4096x2160@100Hz 256:135 */ 1532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1533 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1536 /* 219 - 4096x2160@120Hz 256:135 */ 1537 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1538 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1541 }; 1542 1543 /* 1544 * HDMI 1.4 4k modes. Index using the VIC. 1545 */ 1546 static const struct drm_display_mode edid_4k_modes[] = { 1547 /* 0 - dummy, VICs start at 1 */ 1548 { }, 1549 /* 1 - 3840x2160@30Hz */ 1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 3840, 4016, 4104, 4400, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1555 /* 2 - 3840x2160@25Hz */ 1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1557 3840, 4896, 4984, 5280, 0, 1558 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1561 /* 3 - 3840x2160@24Hz */ 1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1563 3840, 5116, 5204, 5500, 0, 1564 2160, 2168, 2178, 2250, 0, 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1567 /* 4 - 4096x2160@24Hz (SMPTE) */ 1568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1569 4096, 5116, 5204, 5500, 0, 1570 2160, 2168, 2178, 2250, 0, 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1573 }; 1574 1575 /*** DDC fetch and block validation ***/ 1576 1577 /* 1578 * The opaque EDID type, internal to drm_edid.c. 1579 */ 1580 struct drm_edid { 1581 /* Size allocated for edid */ 1582 size_t size; 1583 const struct edid *edid; 1584 }; 1585 1586 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1587 1588 static int edid_hfeeodb_block_count(const struct edid *edid) 1589 { 1590 int eeodb = edid_hfeeodb_extension_block_count(edid); 1591 1592 return eeodb ? eeodb + 1 : 0; 1593 } 1594 1595 static int edid_extension_block_count(const struct edid *edid) 1596 { 1597 return edid->extensions; 1598 } 1599 1600 static int edid_block_count(const struct edid *edid) 1601 { 1602 return edid_extension_block_count(edid) + 1; 1603 } 1604 1605 static int edid_size_by_blocks(int num_blocks) 1606 { 1607 return num_blocks * EDID_LENGTH; 1608 } 1609 1610 static int edid_size(const struct edid *edid) 1611 { 1612 return edid_size_by_blocks(edid_block_count(edid)); 1613 } 1614 1615 static const void *edid_block_data(const struct edid *edid, int index) 1616 { 1617 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1618 1619 return edid + index; 1620 } 1621 1622 static const void *edid_extension_block_data(const struct edid *edid, int index) 1623 { 1624 return edid_block_data(edid, index + 1); 1625 } 1626 1627 /* EDID block count indicated in EDID, may exceed allocated size */ 1628 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1629 { 1630 int num_blocks; 1631 1632 /* Starting point */ 1633 num_blocks = edid_block_count(drm_edid->edid); 1634 1635 /* HF-EEODB override */ 1636 if (drm_edid->size >= edid_size_by_blocks(2)) { 1637 int eeodb; 1638 1639 /* 1640 * Note: HF-EEODB may specify a smaller extension count than the 1641 * regular one. Unlike in buffer allocation, here we can use it. 1642 */ 1643 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1644 if (eeodb) 1645 num_blocks = eeodb; 1646 } 1647 1648 return num_blocks; 1649 } 1650 1651 /* EDID block count, limited by allocated size */ 1652 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1653 { 1654 /* Limit by allocated size */ 1655 return min(__drm_edid_block_count(drm_edid), 1656 (int)drm_edid->size / EDID_LENGTH); 1657 } 1658 1659 /* EDID extension block count, limited by allocated size */ 1660 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1661 { 1662 return drm_edid_block_count(drm_edid) - 1; 1663 } 1664 1665 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1666 { 1667 return edid_block_data(drm_edid->edid, index); 1668 } 1669 1670 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1671 int index) 1672 { 1673 return edid_extension_block_data(drm_edid->edid, index); 1674 } 1675 1676 /* 1677 * Initializer helper for legacy interfaces, where we have no choice but to 1678 * trust edid size. Not for general purpose use. 1679 */ 1680 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1681 const struct edid *edid) 1682 { 1683 if (!edid) 1684 return NULL; 1685 1686 memset(drm_edid, 0, sizeof(*drm_edid)); 1687 1688 drm_edid->edid = edid; 1689 drm_edid->size = edid_size(edid); 1690 1691 return drm_edid; 1692 } 1693 1694 /* 1695 * EDID base and extension block iterator. 1696 * 1697 * struct drm_edid_iter iter; 1698 * const u8 *block; 1699 * 1700 * drm_edid_iter_begin(drm_edid, &iter); 1701 * drm_edid_iter_for_each(block, &iter) { 1702 * // do stuff with block 1703 * } 1704 * drm_edid_iter_end(&iter); 1705 */ 1706 struct drm_edid_iter { 1707 const struct drm_edid *drm_edid; 1708 1709 /* Current block index. */ 1710 int index; 1711 }; 1712 1713 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1714 struct drm_edid_iter *iter) 1715 { 1716 memset(iter, 0, sizeof(*iter)); 1717 1718 iter->drm_edid = drm_edid; 1719 } 1720 1721 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1722 { 1723 const void *block = NULL; 1724 1725 if (!iter->drm_edid) 1726 return NULL; 1727 1728 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1729 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1730 1731 return block; 1732 } 1733 1734 #define drm_edid_iter_for_each(__block, __iter) \ 1735 while (((__block) = __drm_edid_iter_next(__iter))) 1736 1737 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1738 { 1739 memset(iter, 0, sizeof(*iter)); 1740 } 1741 1742 static const u8 edid_header[] = { 1743 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1744 }; 1745 1746 static void edid_header_fix(void *edid) 1747 { 1748 memcpy(edid, edid_header, sizeof(edid_header)); 1749 } 1750 1751 /** 1752 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1753 * @_edid: pointer to raw base EDID block 1754 * 1755 * Sanity check the header of the base EDID block. 1756 * 1757 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1758 */ 1759 int drm_edid_header_is_valid(const void *_edid) 1760 { 1761 const struct edid *edid = _edid; 1762 int i, score = 0; 1763 1764 for (i = 0; i < sizeof(edid_header); i++) { 1765 if (edid->header[i] == edid_header[i]) 1766 score++; 1767 } 1768 1769 return score; 1770 } 1771 EXPORT_SYMBOL(drm_edid_header_is_valid); 1772 1773 static int edid_fixup __read_mostly = 6; 1774 module_param_named(edid_fixup, edid_fixup, int, 0400); 1775 MODULE_PARM_DESC(edid_fixup, 1776 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1777 1778 static int edid_block_compute_checksum(const void *_block) 1779 { 1780 const u8 *block = _block; 1781 int i; 1782 u8 csum = 0, crc = 0; 1783 1784 for (i = 0; i < EDID_LENGTH - 1; i++) 1785 csum += block[i]; 1786 1787 crc = 0x100 - csum; 1788 1789 return crc; 1790 } 1791 1792 static int edid_block_get_checksum(const void *_block) 1793 { 1794 const struct edid *block = _block; 1795 1796 return block->checksum; 1797 } 1798 1799 static int edid_block_tag(const void *_block) 1800 { 1801 const u8 *block = _block; 1802 1803 return block[0]; 1804 } 1805 1806 static bool edid_block_is_zero(const void *edid) 1807 { 1808 return !memchr_inv(edid, 0, EDID_LENGTH); 1809 } 1810 1811 /** 1812 * drm_edid_are_equal - compare two edid blobs. 1813 * @edid1: pointer to first blob 1814 * @edid2: pointer to second blob 1815 * This helper can be used during probing to determine if 1816 * edid had changed. 1817 */ 1818 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1819 { 1820 int edid1_len, edid2_len; 1821 bool edid1_present = edid1 != NULL; 1822 bool edid2_present = edid2 != NULL; 1823 1824 if (edid1_present != edid2_present) 1825 return false; 1826 1827 if (edid1) { 1828 edid1_len = edid_size(edid1); 1829 edid2_len = edid_size(edid2); 1830 1831 if (edid1_len != edid2_len) 1832 return false; 1833 1834 if (memcmp(edid1, edid2, edid1_len)) 1835 return false; 1836 } 1837 1838 return true; 1839 } 1840 EXPORT_SYMBOL(drm_edid_are_equal); 1841 1842 enum edid_block_status { 1843 EDID_BLOCK_OK = 0, 1844 EDID_BLOCK_READ_FAIL, 1845 EDID_BLOCK_NULL, 1846 EDID_BLOCK_ZERO, 1847 EDID_BLOCK_HEADER_CORRUPT, 1848 EDID_BLOCK_HEADER_REPAIR, 1849 EDID_BLOCK_HEADER_FIXED, 1850 EDID_BLOCK_CHECKSUM, 1851 EDID_BLOCK_VERSION, 1852 }; 1853 1854 static enum edid_block_status edid_block_check(const void *_block, 1855 bool is_base_block) 1856 { 1857 const struct edid *block = _block; 1858 1859 if (!block) 1860 return EDID_BLOCK_NULL; 1861 1862 if (is_base_block) { 1863 int score = drm_edid_header_is_valid(block); 1864 1865 if (score < clamp(edid_fixup, 0, 8)) { 1866 if (edid_block_is_zero(block)) 1867 return EDID_BLOCK_ZERO; 1868 else 1869 return EDID_BLOCK_HEADER_CORRUPT; 1870 } 1871 1872 if (score < 8) 1873 return EDID_BLOCK_HEADER_REPAIR; 1874 } 1875 1876 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1877 if (edid_block_is_zero(block)) 1878 return EDID_BLOCK_ZERO; 1879 else 1880 return EDID_BLOCK_CHECKSUM; 1881 } 1882 1883 if (is_base_block) { 1884 if (block->version != 1) 1885 return EDID_BLOCK_VERSION; 1886 } 1887 1888 return EDID_BLOCK_OK; 1889 } 1890 1891 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1892 { 1893 return status == EDID_BLOCK_OK || 1894 status == EDID_BLOCK_HEADER_FIXED || 1895 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1896 } 1897 1898 static bool edid_block_valid(const void *block, bool base) 1899 { 1900 return edid_block_status_valid(edid_block_check(block, base), 1901 edid_block_tag(block)); 1902 } 1903 1904 static void edid_block_status_print(enum edid_block_status status, 1905 const struct edid *block, 1906 int block_num) 1907 { 1908 switch (status) { 1909 case EDID_BLOCK_OK: 1910 break; 1911 case EDID_BLOCK_READ_FAIL: 1912 pr_debug("EDID block %d read failed\n", block_num); 1913 break; 1914 case EDID_BLOCK_NULL: 1915 pr_debug("EDID block %d pointer is NULL\n", block_num); 1916 break; 1917 case EDID_BLOCK_ZERO: 1918 pr_notice("EDID block %d is all zeroes\n", block_num); 1919 break; 1920 case EDID_BLOCK_HEADER_CORRUPT: 1921 pr_notice("EDID has corrupt header\n"); 1922 break; 1923 case EDID_BLOCK_HEADER_REPAIR: 1924 pr_debug("EDID corrupt header needs repair\n"); 1925 break; 1926 case EDID_BLOCK_HEADER_FIXED: 1927 pr_debug("EDID corrupt header fixed\n"); 1928 break; 1929 case EDID_BLOCK_CHECKSUM: 1930 if (edid_block_status_valid(status, edid_block_tag(block))) { 1931 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1932 block_num, edid_block_tag(block), 1933 edid_block_compute_checksum(block)); 1934 } else { 1935 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1936 block_num, edid_block_tag(block), 1937 edid_block_compute_checksum(block)); 1938 } 1939 break; 1940 case EDID_BLOCK_VERSION: 1941 pr_notice("EDID has major version %d, instead of 1\n", 1942 block->version); 1943 break; 1944 default: 1945 WARN(1, "EDID block %d unknown edid block status code %d\n", 1946 block_num, status); 1947 break; 1948 } 1949 } 1950 1951 static void edid_block_dump(const char *level, const void *block, int block_num) 1952 { 1953 enum edid_block_status status; 1954 char prefix[20]; 1955 1956 status = edid_block_check(block, block_num == 0); 1957 if (status == EDID_BLOCK_ZERO) 1958 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1959 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1960 sprintf(prefix, "\t[%02x] BAD ", block_num); 1961 else 1962 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1963 1964 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1965 block, EDID_LENGTH, false); 1966 } 1967 1968 /** 1969 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1970 * @_block: pointer to raw EDID block 1971 * @block_num: type of block to validate (0 for base, extension otherwise) 1972 * @print_bad_edid: if true, dump bad EDID blocks to the console 1973 * @edid_corrupt: if true, the header or checksum is invalid 1974 * 1975 * Validate a base or extension EDID block and optionally dump bad blocks to 1976 * the console. 1977 * 1978 * Return: True if the block is valid, false otherwise. 1979 */ 1980 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1981 bool *edid_corrupt) 1982 { 1983 struct edid *block = (struct edid *)_block; 1984 enum edid_block_status status; 1985 bool is_base_block = block_num == 0; 1986 bool valid; 1987 1988 if (WARN_ON(!block)) 1989 return false; 1990 1991 status = edid_block_check(block, is_base_block); 1992 if (status == EDID_BLOCK_HEADER_REPAIR) { 1993 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1994 edid_header_fix(block); 1995 1996 /* Retry with fixed header, update status if that worked. */ 1997 status = edid_block_check(block, is_base_block); 1998 if (status == EDID_BLOCK_OK) 1999 status = EDID_BLOCK_HEADER_FIXED; 2000 } 2001 2002 if (edid_corrupt) { 2003 /* 2004 * Unknown major version isn't corrupt but we can't use it. Only 2005 * the base block can reset edid_corrupt to false. 2006 */ 2007 if (is_base_block && 2008 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2009 *edid_corrupt = false; 2010 else if (status != EDID_BLOCK_OK) 2011 *edid_corrupt = true; 2012 } 2013 2014 edid_block_status_print(status, block, block_num); 2015 2016 /* Determine whether we can use this block with this status. */ 2017 valid = edid_block_status_valid(status, edid_block_tag(block)); 2018 2019 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2020 pr_notice("Raw EDID:\n"); 2021 edid_block_dump(KERN_NOTICE, block, block_num); 2022 } 2023 2024 return valid; 2025 } 2026 EXPORT_SYMBOL(drm_edid_block_valid); 2027 2028 /** 2029 * drm_edid_is_valid - sanity check EDID data 2030 * @edid: EDID data 2031 * 2032 * Sanity-check an entire EDID record (including extensions) 2033 * 2034 * Return: True if the EDID data is valid, false otherwise. 2035 */ 2036 bool drm_edid_is_valid(struct edid *edid) 2037 { 2038 int i; 2039 2040 if (!edid) 2041 return false; 2042 2043 for (i = 0; i < edid_block_count(edid); i++) { 2044 void *block = (void *)edid_block_data(edid, i); 2045 2046 if (!drm_edid_block_valid(block, i, true, NULL)) 2047 return false; 2048 } 2049 2050 return true; 2051 } 2052 EXPORT_SYMBOL(drm_edid_is_valid); 2053 2054 /** 2055 * drm_edid_valid - sanity check EDID data 2056 * @drm_edid: EDID data 2057 * 2058 * Sanity check an EDID. Cross check block count against allocated size and 2059 * checksum the blocks. 2060 * 2061 * Return: True if the EDID data is valid, false otherwise. 2062 */ 2063 bool drm_edid_valid(const struct drm_edid *drm_edid) 2064 { 2065 int i; 2066 2067 if (!drm_edid) 2068 return false; 2069 2070 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2071 return false; 2072 2073 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2074 const void *block = drm_edid_block_data(drm_edid, i); 2075 2076 if (!edid_block_valid(block, i == 0)) 2077 return false; 2078 } 2079 2080 return true; 2081 } 2082 EXPORT_SYMBOL(drm_edid_valid); 2083 2084 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2085 size_t *alloc_size) 2086 { 2087 struct edid *new; 2088 int i, valid_blocks = 0; 2089 2090 /* 2091 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2092 * back to regular extension count here. We don't want to start 2093 * modifying the HF-EEODB extension too. 2094 */ 2095 for (i = 0; i < edid_block_count(edid); i++) { 2096 const void *src_block = edid_block_data(edid, i); 2097 2098 if (edid_block_valid(src_block, i == 0)) { 2099 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2100 2101 memmove(dst_block, src_block, EDID_LENGTH); 2102 valid_blocks++; 2103 } 2104 } 2105 2106 /* We already trusted the base block to be valid here... */ 2107 if (WARN_ON(!valid_blocks)) { 2108 kfree(edid); 2109 return NULL; 2110 } 2111 2112 edid->extensions = valid_blocks - 1; 2113 edid->checksum = edid_block_compute_checksum(edid); 2114 2115 *alloc_size = edid_size_by_blocks(valid_blocks); 2116 2117 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2118 if (!new) 2119 kfree(edid); 2120 2121 return new; 2122 } 2123 2124 #define DDC_SEGMENT_ADDR 0x30 2125 /** 2126 * drm_do_probe_ddc_edid() - get EDID information via I2C 2127 * @data: I2C device adapter 2128 * @buf: EDID data buffer to be filled 2129 * @block: 128 byte EDID block to start fetching from 2130 * @len: EDID data buffer length to fetch 2131 * 2132 * Try to fetch EDID information by calling I2C driver functions. 2133 * 2134 * Return: 0 on success or -1 on failure. 2135 */ 2136 static int 2137 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2138 { 2139 struct i2c_adapter *adapter = data; 2140 unsigned char start = block * EDID_LENGTH; 2141 unsigned char segment = block >> 1; 2142 unsigned char xfers = segment ? 3 : 2; 2143 int ret, retries = 5; 2144 2145 /* 2146 * The core I2C driver will automatically retry the transfer if the 2147 * adapter reports EAGAIN. However, we find that bit-banging transfers 2148 * are susceptible to errors under a heavily loaded machine and 2149 * generate spurious NAKs and timeouts. Retrying the transfer 2150 * of the individual block a few times seems to overcome this. 2151 */ 2152 do { 2153 struct i2c_msg msgs[] = { 2154 { 2155 .addr = DDC_SEGMENT_ADDR, 2156 .flags = 0, 2157 .len = 1, 2158 .buf = &segment, 2159 }, { 2160 .addr = DDC_ADDR, 2161 .flags = 0, 2162 .len = 1, 2163 .buf = &start, 2164 }, { 2165 .addr = DDC_ADDR, 2166 .flags = I2C_M_RD, 2167 .len = len, 2168 .buf = buf, 2169 } 2170 }; 2171 2172 /* 2173 * Avoid sending the segment addr to not upset non-compliant 2174 * DDC monitors. 2175 */ 2176 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2177 2178 if (ret == -ENXIO) { 2179 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2180 adapter->name); 2181 break; 2182 } 2183 } while (ret != xfers && --retries); 2184 2185 return ret == xfers ? 0 : -1; 2186 } 2187 2188 static void connector_bad_edid(struct drm_connector *connector, 2189 const struct edid *edid, int num_blocks) 2190 { 2191 int i; 2192 u8 last_block; 2193 2194 /* 2195 * 0x7e in the EDID is the number of extension blocks. The EDID 2196 * is 1 (base block) + num_ext_blocks big. That means we can think 2197 * of 0x7e in the EDID of the _index_ of the last block in the 2198 * combined chunk of memory. 2199 */ 2200 last_block = edid->extensions; 2201 2202 /* Calculate real checksum for the last edid extension block data */ 2203 if (last_block < num_blocks) 2204 connector->real_edid_checksum = 2205 edid_block_compute_checksum(edid + last_block); 2206 2207 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2208 return; 2209 2210 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2211 connector->base.id, connector->name); 2212 for (i = 0; i < num_blocks; i++) 2213 edid_block_dump(KERN_DEBUG, edid + i, i); 2214 } 2215 2216 /* Get override or firmware EDID */ 2217 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2218 { 2219 const struct drm_edid *override = NULL; 2220 2221 mutex_lock(&connector->edid_override_mutex); 2222 2223 if (connector->edid_override) 2224 override = drm_edid_dup(connector->edid_override); 2225 2226 mutex_unlock(&connector->edid_override_mutex); 2227 2228 if (!override) 2229 override = drm_edid_load_firmware(connector); 2230 2231 return IS_ERR(override) ? NULL : override; 2232 } 2233 2234 /* For debugfs edid_override implementation */ 2235 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2236 { 2237 const struct drm_edid *drm_edid; 2238 2239 mutex_lock(&connector->edid_override_mutex); 2240 2241 drm_edid = connector->edid_override; 2242 if (drm_edid) 2243 seq_write(m, drm_edid->edid, drm_edid->size); 2244 2245 mutex_unlock(&connector->edid_override_mutex); 2246 2247 return 0; 2248 } 2249 2250 /* For debugfs edid_override implementation */ 2251 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2252 size_t size) 2253 { 2254 const struct drm_edid *drm_edid; 2255 2256 drm_edid = drm_edid_alloc(edid, size); 2257 if (!drm_edid_valid(drm_edid)) { 2258 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2259 connector->base.id, connector->name); 2260 drm_edid_free(drm_edid); 2261 return -EINVAL; 2262 } 2263 2264 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2265 connector->base.id, connector->name); 2266 2267 mutex_lock(&connector->edid_override_mutex); 2268 2269 drm_edid_free(connector->edid_override); 2270 connector->edid_override = drm_edid; 2271 2272 mutex_unlock(&connector->edid_override_mutex); 2273 2274 return 0; 2275 } 2276 2277 /* For debugfs edid_override implementation */ 2278 int drm_edid_override_reset(struct drm_connector *connector) 2279 { 2280 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2281 connector->base.id, connector->name); 2282 2283 mutex_lock(&connector->edid_override_mutex); 2284 2285 drm_edid_free(connector->edid_override); 2286 connector->edid_override = NULL; 2287 2288 mutex_unlock(&connector->edid_override_mutex); 2289 2290 return 0; 2291 } 2292 2293 /** 2294 * drm_edid_override_connector_update - add modes from override/firmware EDID 2295 * @connector: connector we're probing 2296 * 2297 * Add modes from the override/firmware EDID, if available. Only to be used from 2298 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2299 * failed during drm_get_edid() and caused the override/firmware EDID to be 2300 * skipped. 2301 * 2302 * Return: The number of modes added or 0 if we couldn't find any. 2303 */ 2304 int drm_edid_override_connector_update(struct drm_connector *connector) 2305 { 2306 const struct drm_edid *override; 2307 int num_modes = 0; 2308 2309 override = drm_edid_override_get(connector); 2310 if (override) { 2311 num_modes = drm_edid_connector_update(connector, override); 2312 2313 drm_edid_free(override); 2314 2315 drm_dbg_kms(connector->dev, 2316 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2317 connector->base.id, connector->name, num_modes); 2318 } 2319 2320 return num_modes; 2321 } 2322 EXPORT_SYMBOL(drm_edid_override_connector_update); 2323 2324 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2325 2326 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2327 read_block_fn read_block, 2328 void *context) 2329 { 2330 enum edid_block_status status; 2331 bool is_base_block = block_num == 0; 2332 int try; 2333 2334 for (try = 0; try < 4; try++) { 2335 if (read_block(context, block, block_num, EDID_LENGTH)) 2336 return EDID_BLOCK_READ_FAIL; 2337 2338 status = edid_block_check(block, is_base_block); 2339 if (status == EDID_BLOCK_HEADER_REPAIR) { 2340 edid_header_fix(block); 2341 2342 /* Retry with fixed header, update status if that worked. */ 2343 status = edid_block_check(block, is_base_block); 2344 if (status == EDID_BLOCK_OK) 2345 status = EDID_BLOCK_HEADER_FIXED; 2346 } 2347 2348 if (edid_block_status_valid(status, edid_block_tag(block))) 2349 break; 2350 2351 /* Fail early for unrepairable base block all zeros. */ 2352 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2353 break; 2354 } 2355 2356 return status; 2357 } 2358 2359 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2360 read_block_fn read_block, void *context, 2361 size_t *size) 2362 { 2363 enum edid_block_status status; 2364 int i, num_blocks, invalid_blocks = 0; 2365 const struct drm_edid *override; 2366 struct edid *edid, *new; 2367 size_t alloc_size = EDID_LENGTH; 2368 2369 override = drm_edid_override_get(connector); 2370 if (override) { 2371 alloc_size = override->size; 2372 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2373 drm_edid_free(override); 2374 if (!edid) 2375 return NULL; 2376 goto ok; 2377 } 2378 2379 edid = kmalloc(alloc_size, GFP_KERNEL); 2380 if (!edid) 2381 return NULL; 2382 2383 status = edid_block_read(edid, 0, read_block, context); 2384 2385 edid_block_status_print(status, edid, 0); 2386 2387 if (status == EDID_BLOCK_READ_FAIL) 2388 goto fail; 2389 2390 /* FIXME: Clarify what a corrupt EDID actually means. */ 2391 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2392 connector->edid_corrupt = false; 2393 else 2394 connector->edid_corrupt = true; 2395 2396 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2397 if (status == EDID_BLOCK_ZERO) 2398 connector->null_edid_counter++; 2399 2400 connector_bad_edid(connector, edid, 1); 2401 goto fail; 2402 } 2403 2404 if (!edid_extension_block_count(edid)) 2405 goto ok; 2406 2407 alloc_size = edid_size(edid); 2408 new = krealloc(edid, alloc_size, GFP_KERNEL); 2409 if (!new) 2410 goto fail; 2411 edid = new; 2412 2413 num_blocks = edid_block_count(edid); 2414 for (i = 1; i < num_blocks; i++) { 2415 void *block = (void *)edid_block_data(edid, i); 2416 2417 status = edid_block_read(block, i, read_block, context); 2418 2419 edid_block_status_print(status, block, i); 2420 2421 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2422 if (status == EDID_BLOCK_READ_FAIL) 2423 goto fail; 2424 invalid_blocks++; 2425 } else if (i == 1) { 2426 /* 2427 * If the first EDID extension is a CTA extension, and 2428 * the first Data Block is HF-EEODB, override the 2429 * extension block count. 2430 * 2431 * Note: HF-EEODB could specify a smaller extension 2432 * count too, but we can't risk allocating a smaller 2433 * amount. 2434 */ 2435 int eeodb = edid_hfeeodb_block_count(edid); 2436 2437 if (eeodb > num_blocks) { 2438 num_blocks = eeodb; 2439 alloc_size = edid_size_by_blocks(num_blocks); 2440 new = krealloc(edid, alloc_size, GFP_KERNEL); 2441 if (!new) 2442 goto fail; 2443 edid = new; 2444 } 2445 } 2446 } 2447 2448 if (invalid_blocks) { 2449 connector_bad_edid(connector, edid, num_blocks); 2450 2451 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2452 } 2453 2454 ok: 2455 if (size) 2456 *size = alloc_size; 2457 2458 return edid; 2459 2460 fail: 2461 kfree(edid); 2462 return NULL; 2463 } 2464 2465 /** 2466 * drm_do_get_edid - get EDID data using a custom EDID block read function 2467 * @connector: connector we're probing 2468 * @read_block: EDID block read function 2469 * @context: private data passed to the block read function 2470 * 2471 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2472 * exposes a different interface to read EDID blocks this function can be used 2473 * to get EDID data using a custom block read function. 2474 * 2475 * As in the general case the DDC bus is accessible by the kernel at the I2C 2476 * level, drivers must make all reasonable efforts to expose it as an I2C 2477 * adapter and use drm_get_edid() instead of abusing this function. 2478 * 2479 * The EDID may be overridden using debugfs override_edid or firmware EDID 2480 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2481 * order. Having either of them bypasses actual EDID reads. 2482 * 2483 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2484 */ 2485 struct edid *drm_do_get_edid(struct drm_connector *connector, 2486 read_block_fn read_block, 2487 void *context) 2488 { 2489 return _drm_do_get_edid(connector, read_block, context, NULL); 2490 } 2491 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2492 2493 /** 2494 * drm_edid_raw - Get a pointer to the raw EDID data. 2495 * @drm_edid: drm_edid container 2496 * 2497 * Get a pointer to the raw EDID data. 2498 * 2499 * This is for transition only. Avoid using this like the plague. 2500 * 2501 * Return: Pointer to raw EDID data. 2502 */ 2503 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2504 { 2505 if (!drm_edid || !drm_edid->size) 2506 return NULL; 2507 2508 /* 2509 * Do not return pointers where relying on EDID extension count would 2510 * lead to buffer overflow. 2511 */ 2512 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2513 return NULL; 2514 2515 return drm_edid->edid; 2516 } 2517 EXPORT_SYMBOL(drm_edid_raw); 2518 2519 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2520 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2521 { 2522 struct drm_edid *drm_edid; 2523 2524 if (!edid || !size || size < EDID_LENGTH) 2525 return NULL; 2526 2527 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2528 if (drm_edid) { 2529 drm_edid->edid = edid; 2530 drm_edid->size = size; 2531 } 2532 2533 return drm_edid; 2534 } 2535 2536 /** 2537 * drm_edid_alloc - Allocate a new drm_edid container 2538 * @edid: Pointer to raw EDID data 2539 * @size: Size of memory allocated for EDID 2540 * 2541 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2542 * the actual size that has been allocated for the data. There is no validation 2543 * of the raw EDID data against the size, but at least the EDID base block must 2544 * fit in the buffer. 2545 * 2546 * The returned pointer must be freed using drm_edid_free(). 2547 * 2548 * Return: drm_edid container, or NULL on errors 2549 */ 2550 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2551 { 2552 const struct drm_edid *drm_edid; 2553 2554 if (!edid || !size || size < EDID_LENGTH) 2555 return NULL; 2556 2557 edid = kmemdup(edid, size, GFP_KERNEL); 2558 if (!edid) 2559 return NULL; 2560 2561 drm_edid = _drm_edid_alloc(edid, size); 2562 if (!drm_edid) 2563 kfree(edid); 2564 2565 return drm_edid; 2566 } 2567 EXPORT_SYMBOL(drm_edid_alloc); 2568 2569 /** 2570 * drm_edid_dup - Duplicate a drm_edid container 2571 * @drm_edid: EDID to duplicate 2572 * 2573 * The returned pointer must be freed using drm_edid_free(). 2574 * 2575 * Returns: drm_edid container copy, or NULL on errors 2576 */ 2577 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2578 { 2579 if (!drm_edid) 2580 return NULL; 2581 2582 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2583 } 2584 EXPORT_SYMBOL(drm_edid_dup); 2585 2586 /** 2587 * drm_edid_free - Free the drm_edid container 2588 * @drm_edid: EDID to free 2589 */ 2590 void drm_edid_free(const struct drm_edid *drm_edid) 2591 { 2592 if (!drm_edid) 2593 return; 2594 2595 kfree(drm_edid->edid); 2596 kfree(drm_edid); 2597 } 2598 EXPORT_SYMBOL(drm_edid_free); 2599 2600 /** 2601 * drm_probe_ddc() - probe DDC presence 2602 * @adapter: I2C adapter to probe 2603 * 2604 * Return: True on success, false on failure. 2605 */ 2606 bool 2607 drm_probe_ddc(struct i2c_adapter *adapter) 2608 { 2609 unsigned char out; 2610 2611 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2612 } 2613 EXPORT_SYMBOL(drm_probe_ddc); 2614 2615 /** 2616 * drm_get_edid - get EDID data, if available 2617 * @connector: connector we're probing 2618 * @adapter: I2C adapter to use for DDC 2619 * 2620 * Poke the given I2C channel to grab EDID data if possible. If found, 2621 * attach it to the connector. 2622 * 2623 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2624 */ 2625 struct edid *drm_get_edid(struct drm_connector *connector, 2626 struct i2c_adapter *adapter) 2627 { 2628 struct edid *edid; 2629 2630 if (connector->force == DRM_FORCE_OFF) 2631 return NULL; 2632 2633 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2634 return NULL; 2635 2636 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2637 drm_connector_update_edid_property(connector, edid); 2638 return edid; 2639 } 2640 EXPORT_SYMBOL(drm_get_edid); 2641 2642 /** 2643 * drm_edid_read_custom - Read EDID data using given EDID block read function 2644 * @connector: Connector to use 2645 * @read_block: EDID block read function 2646 * @context: Private data passed to the block read function 2647 * 2648 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2649 * exposes a different interface to read EDID blocks this function can be used 2650 * to get EDID data using a custom block read function. 2651 * 2652 * As in the general case the DDC bus is accessible by the kernel at the I2C 2653 * level, drivers must make all reasonable efforts to expose it as an I2C 2654 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2655 * this function. 2656 * 2657 * The EDID may be overridden using debugfs override_edid or firmware EDID 2658 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2659 * order. Having either of them bypasses actual EDID reads. 2660 * 2661 * The returned pointer must be freed using drm_edid_free(). 2662 * 2663 * Return: Pointer to EDID, or NULL if probe/read failed. 2664 */ 2665 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2666 read_block_fn read_block, 2667 void *context) 2668 { 2669 const struct drm_edid *drm_edid; 2670 struct edid *edid; 2671 size_t size = 0; 2672 2673 edid = _drm_do_get_edid(connector, read_block, context, &size); 2674 if (!edid) 2675 return NULL; 2676 2677 /* Sanity check for now */ 2678 drm_WARN_ON(connector->dev, !size); 2679 2680 drm_edid = _drm_edid_alloc(edid, size); 2681 if (!drm_edid) 2682 kfree(edid); 2683 2684 return drm_edid; 2685 } 2686 EXPORT_SYMBOL(drm_edid_read_custom); 2687 2688 /** 2689 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2690 * @connector: Connector to use 2691 * @adapter: I2C adapter to use for DDC 2692 * 2693 * Read EDID using the given I2C adapter. 2694 * 2695 * The EDID may be overridden using debugfs override_edid or firmware EDID 2696 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2697 * order. Having either of them bypasses actual EDID reads. 2698 * 2699 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2700 * using drm_edid_read() instead of this function. 2701 * 2702 * The returned pointer must be freed using drm_edid_free(). 2703 * 2704 * Return: Pointer to EDID, or NULL if probe/read failed. 2705 */ 2706 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2707 struct i2c_adapter *adapter) 2708 { 2709 const struct drm_edid *drm_edid; 2710 2711 if (connector->force == DRM_FORCE_OFF) 2712 return NULL; 2713 2714 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2715 return NULL; 2716 2717 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2718 2719 /* Note: Do *not* call connector updates here. */ 2720 2721 return drm_edid; 2722 } 2723 EXPORT_SYMBOL(drm_edid_read_ddc); 2724 2725 /** 2726 * drm_edid_read - Read EDID data using connector's I2C adapter 2727 * @connector: Connector to use 2728 * 2729 * Read EDID using the connector's I2C adapter. 2730 * 2731 * The EDID may be overridden using debugfs override_edid or firmware EDID 2732 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2733 * order. Having either of them bypasses actual EDID reads. 2734 * 2735 * The returned pointer must be freed using drm_edid_free(). 2736 * 2737 * Return: Pointer to EDID, or NULL if probe/read failed. 2738 */ 2739 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2740 { 2741 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2742 return NULL; 2743 2744 return drm_edid_read_ddc(connector, connector->ddc); 2745 } 2746 EXPORT_SYMBOL(drm_edid_read); 2747 2748 static u32 edid_extract_panel_id(const struct edid *edid) 2749 { 2750 /* 2751 * We represent the ID as a 32-bit number so it can easily be compared 2752 * with "==". 2753 * 2754 * NOTE that we deal with endianness differently for the top half 2755 * of this ID than for the bottom half. The bottom half (the product 2756 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2757 * that's how everyone seems to interpret it. The top half (the mfg_id) 2758 * gets stored as big endian because that makes 2759 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2760 * to write (it's easier to extract the ASCII). It doesn't really 2761 * matter, though, as long as the number here is unique. 2762 */ 2763 return (u32)edid->mfg_id[0] << 24 | 2764 (u32)edid->mfg_id[1] << 16 | 2765 (u32)EDID_PRODUCT_ID(edid); 2766 } 2767 2768 /** 2769 * drm_edid_get_panel_id - Get a panel's ID through DDC 2770 * @adapter: I2C adapter to use for DDC 2771 * 2772 * This function reads the first block of the EDID of a panel and (assuming 2773 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2774 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2775 * supposed to be different for each different modem of panel. 2776 * 2777 * This function is intended to be used during early probing on devices where 2778 * more than one panel might be present. Because of its intended use it must 2779 * assume that the EDID of the panel is correct, at least as far as the ID 2780 * is concerned (in other words, we don't process any overrides here). 2781 * 2782 * NOTE: it's expected that this function and drm_do_get_edid() will both 2783 * be read the EDID, but there is no caching between them. Since we're only 2784 * reading the first block, hopefully this extra overhead won't be too big. 2785 * 2786 * Return: A 32-bit ID that should be different for each make/model of panel. 2787 * See the functions drm_edid_encode_panel_id() and 2788 * drm_edid_decode_panel_id() for some details on the structure of this 2789 * ID. 2790 */ 2791 2792 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2793 { 2794 enum edid_block_status status; 2795 void *base_block; 2796 u32 panel_id = 0; 2797 2798 /* 2799 * There are no manufacturer IDs of 0, so if there is a problem reading 2800 * the EDID then we'll just return 0. 2801 */ 2802 2803 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2804 if (!base_block) 2805 return 0; 2806 2807 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2808 2809 edid_block_status_print(status, base_block, 0); 2810 2811 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2812 panel_id = edid_extract_panel_id(base_block); 2813 else 2814 edid_block_dump(KERN_NOTICE, base_block, 0); 2815 2816 kfree(base_block); 2817 2818 return panel_id; 2819 } 2820 EXPORT_SYMBOL(drm_edid_get_panel_id); 2821 2822 /** 2823 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2824 * @connector: connector we're probing 2825 * @adapter: I2C adapter to use for DDC 2826 * 2827 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2828 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2829 * switch DDC to the GPU which is retrieving EDID. 2830 * 2831 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2832 */ 2833 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2834 struct i2c_adapter *adapter) 2835 { 2836 struct drm_device *dev = connector->dev; 2837 struct pci_dev *pdev = to_pci_dev(dev->dev); 2838 struct edid *edid; 2839 2840 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2841 return NULL; 2842 2843 vga_switcheroo_lock_ddc(pdev); 2844 edid = drm_get_edid(connector, adapter); 2845 vga_switcheroo_unlock_ddc(pdev); 2846 2847 return edid; 2848 } 2849 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2850 2851 /** 2852 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2853 * @connector: connector we're probing 2854 * @adapter: I2C adapter to use for DDC 2855 * 2856 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2857 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2858 * temporarily switch DDC to the GPU which is retrieving EDID. 2859 * 2860 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2861 */ 2862 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2863 struct i2c_adapter *adapter) 2864 { 2865 struct drm_device *dev = connector->dev; 2866 struct pci_dev *pdev = to_pci_dev(dev->dev); 2867 const struct drm_edid *drm_edid; 2868 2869 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2870 return NULL; 2871 2872 vga_switcheroo_lock_ddc(pdev); 2873 drm_edid = drm_edid_read_ddc(connector, adapter); 2874 vga_switcheroo_unlock_ddc(pdev); 2875 2876 return drm_edid; 2877 } 2878 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2879 2880 /** 2881 * drm_edid_duplicate - duplicate an EDID and the extensions 2882 * @edid: EDID to duplicate 2883 * 2884 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2885 */ 2886 struct edid *drm_edid_duplicate(const struct edid *edid) 2887 { 2888 if (!edid) 2889 return NULL; 2890 2891 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2892 } 2893 EXPORT_SYMBOL(drm_edid_duplicate); 2894 2895 /*** EDID parsing ***/ 2896 2897 /** 2898 * edid_get_quirks - return quirk flags for a given EDID 2899 * @drm_edid: EDID to process 2900 * 2901 * This tells subsequent routines what fixes they need to apply. 2902 */ 2903 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2904 { 2905 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2906 const struct edid_quirk *quirk; 2907 int i; 2908 2909 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2910 quirk = &edid_quirk_list[i]; 2911 if (quirk->panel_id == panel_id) 2912 return quirk->quirks; 2913 } 2914 2915 return 0; 2916 } 2917 2918 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2919 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2920 2921 /* 2922 * Walk the mode list for connector, clearing the preferred status on existing 2923 * modes and setting it anew for the right mode ala quirks. 2924 */ 2925 static void edid_fixup_preferred(struct drm_connector *connector) 2926 { 2927 const struct drm_display_info *info = &connector->display_info; 2928 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2929 int target_refresh = 0; 2930 int cur_vrefresh, preferred_vrefresh; 2931 2932 if (list_empty(&connector->probed_modes)) 2933 return; 2934 2935 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2936 target_refresh = 60; 2937 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2938 target_refresh = 75; 2939 2940 preferred_mode = list_first_entry(&connector->probed_modes, 2941 struct drm_display_mode, head); 2942 2943 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2944 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2945 2946 if (cur_mode == preferred_mode) 2947 continue; 2948 2949 /* Largest mode is preferred */ 2950 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2951 preferred_mode = cur_mode; 2952 2953 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2954 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2955 /* At a given size, try to get closest to target refresh */ 2956 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2957 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2958 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2959 preferred_mode = cur_mode; 2960 } 2961 } 2962 2963 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2964 } 2965 2966 static bool 2967 mode_is_rb(const struct drm_display_mode *mode) 2968 { 2969 return (mode->htotal - mode->hdisplay == 160) && 2970 (mode->hsync_end - mode->hdisplay == 80) && 2971 (mode->hsync_end - mode->hsync_start == 32) && 2972 (mode->vsync_start - mode->vdisplay == 3); 2973 } 2974 2975 /* 2976 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2977 * @dev: Device to duplicate against 2978 * @hsize: Mode width 2979 * @vsize: Mode height 2980 * @fresh: Mode refresh rate 2981 * @rb: Mode reduced-blanking-ness 2982 * 2983 * Walk the DMT mode list looking for a match for the given parameters. 2984 * 2985 * Return: A newly allocated copy of the mode, or NULL if not found. 2986 */ 2987 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2988 int hsize, int vsize, int fresh, 2989 bool rb) 2990 { 2991 int i; 2992 2993 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2994 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2995 2996 if (hsize != ptr->hdisplay) 2997 continue; 2998 if (vsize != ptr->vdisplay) 2999 continue; 3000 if (fresh != drm_mode_vrefresh(ptr)) 3001 continue; 3002 if (rb != mode_is_rb(ptr)) 3003 continue; 3004 3005 return drm_mode_duplicate(dev, ptr); 3006 } 3007 3008 return NULL; 3009 } 3010 EXPORT_SYMBOL(drm_mode_find_dmt); 3011 3012 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3013 { 3014 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3015 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3016 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3017 3018 return descriptor->pixel_clock == 0 && 3019 descriptor->data.other_data.pad1 == 0 && 3020 descriptor->data.other_data.type == type; 3021 } 3022 3023 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3024 { 3025 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3026 3027 return descriptor->pixel_clock != 0; 3028 } 3029 3030 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3031 3032 static void 3033 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3034 { 3035 int i, n; 3036 u8 d = ext[0x02]; 3037 const u8 *det_base = ext + d; 3038 3039 if (d < 4 || d > 127) 3040 return; 3041 3042 n = (127 - d) / 18; 3043 for (i = 0; i < n; i++) 3044 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3045 } 3046 3047 static void 3048 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3049 { 3050 unsigned int i, n = min((int)ext[0x02], 6); 3051 const u8 *det_base = ext + 5; 3052 3053 if (ext[0x01] != 1) 3054 return; /* unknown version */ 3055 3056 for (i = 0; i < n; i++) 3057 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3058 } 3059 3060 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3061 detailed_cb *cb, void *closure) 3062 { 3063 struct drm_edid_iter edid_iter; 3064 const u8 *ext; 3065 int i; 3066 3067 if (!drm_edid) 3068 return; 3069 3070 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3071 cb(&drm_edid->edid->detailed_timings[i], closure); 3072 3073 drm_edid_iter_begin(drm_edid, &edid_iter); 3074 drm_edid_iter_for_each(ext, &edid_iter) { 3075 switch (*ext) { 3076 case CEA_EXT: 3077 cea_for_each_detailed_block(ext, cb, closure); 3078 break; 3079 case VTB_EXT: 3080 vtb_for_each_detailed_block(ext, cb, closure); 3081 break; 3082 default: 3083 break; 3084 } 3085 } 3086 drm_edid_iter_end(&edid_iter); 3087 } 3088 3089 static void 3090 is_rb(const struct detailed_timing *descriptor, void *data) 3091 { 3092 bool *res = data; 3093 3094 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3095 return; 3096 3097 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3099 3100 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3101 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3102 *res = true; 3103 } 3104 3105 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3106 static bool 3107 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3108 { 3109 if (drm_edid->edid->revision >= 4) { 3110 bool ret = false; 3111 3112 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3113 return ret; 3114 } 3115 3116 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3117 } 3118 3119 static void 3120 find_gtf2(const struct detailed_timing *descriptor, void *data) 3121 { 3122 const struct detailed_timing **res = data; 3123 3124 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3125 return; 3126 3127 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3128 3129 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3130 *res = descriptor; 3131 } 3132 3133 /* Secondary GTF curve kicks in above some break frequency */ 3134 static int 3135 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3136 { 3137 const struct detailed_timing *descriptor = NULL; 3138 3139 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3140 3141 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3142 3143 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3144 } 3145 3146 static int 3147 drm_gtf2_2c(const struct drm_edid *drm_edid) 3148 { 3149 const struct detailed_timing *descriptor = NULL; 3150 3151 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3152 3153 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3154 3155 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3156 } 3157 3158 static int 3159 drm_gtf2_m(const struct drm_edid *drm_edid) 3160 { 3161 const struct detailed_timing *descriptor = NULL; 3162 3163 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3164 3165 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3166 3167 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3168 } 3169 3170 static int 3171 drm_gtf2_k(const struct drm_edid *drm_edid) 3172 { 3173 const struct detailed_timing *descriptor = NULL; 3174 3175 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3176 3177 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3178 3179 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3180 } 3181 3182 static int 3183 drm_gtf2_2j(const struct drm_edid *drm_edid) 3184 { 3185 const struct detailed_timing *descriptor = NULL; 3186 3187 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3188 3189 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3190 3191 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3192 } 3193 3194 static void 3195 get_timing_level(const struct detailed_timing *descriptor, void *data) 3196 { 3197 int *res = data; 3198 3199 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3200 return; 3201 3202 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3203 3204 switch (descriptor->data.other_data.data.range.flags) { 3205 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3206 *res = LEVEL_GTF; 3207 break; 3208 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3209 *res = LEVEL_GTF2; 3210 break; 3211 case DRM_EDID_CVT_SUPPORT_FLAG: 3212 *res = LEVEL_CVT; 3213 break; 3214 default: 3215 break; 3216 } 3217 } 3218 3219 /* Get standard timing level (CVT/GTF/DMT). */ 3220 static int standard_timing_level(const struct drm_edid *drm_edid) 3221 { 3222 const struct edid *edid = drm_edid->edid; 3223 3224 if (edid->revision >= 4) { 3225 /* 3226 * If the range descriptor doesn't 3227 * indicate otherwise default to CVT 3228 */ 3229 int ret = LEVEL_CVT; 3230 3231 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3232 3233 return ret; 3234 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3235 return LEVEL_GTF2; 3236 } else if (edid->revision >= 2) { 3237 return LEVEL_GTF; 3238 } else { 3239 return LEVEL_DMT; 3240 } 3241 } 3242 3243 /* 3244 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3245 * monitors fill with ascii space (0x20) instead. 3246 */ 3247 static int 3248 bad_std_timing(u8 a, u8 b) 3249 { 3250 return (a == 0x00 && b == 0x00) || 3251 (a == 0x01 && b == 0x01) || 3252 (a == 0x20 && b == 0x20); 3253 } 3254 3255 static int drm_mode_hsync(const struct drm_display_mode *mode) 3256 { 3257 if (mode->htotal <= 0) 3258 return 0; 3259 3260 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3261 } 3262 3263 static struct drm_display_mode * 3264 drm_gtf2_mode(struct drm_device *dev, 3265 const struct drm_edid *drm_edid, 3266 int hsize, int vsize, int vrefresh_rate) 3267 { 3268 struct drm_display_mode *mode; 3269 3270 /* 3271 * This is potentially wrong if there's ever a monitor with 3272 * more than one ranges section, each claiming a different 3273 * secondary GTF curve. Please don't do that. 3274 */ 3275 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3276 if (!mode) 3277 return NULL; 3278 3279 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3280 drm_mode_destroy(dev, mode); 3281 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3282 vrefresh_rate, 0, 0, 3283 drm_gtf2_m(drm_edid), 3284 drm_gtf2_2c(drm_edid), 3285 drm_gtf2_k(drm_edid), 3286 drm_gtf2_2j(drm_edid)); 3287 } 3288 3289 return mode; 3290 } 3291 3292 /* 3293 * Take the standard timing params (in this case width, aspect, and refresh) 3294 * and convert them into a real mode using CVT/GTF/DMT. 3295 */ 3296 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3297 const struct drm_edid *drm_edid, 3298 const struct std_timing *t) 3299 { 3300 struct drm_device *dev = connector->dev; 3301 struct drm_display_mode *m, *mode = NULL; 3302 int hsize, vsize; 3303 int vrefresh_rate; 3304 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3305 >> EDID_TIMING_ASPECT_SHIFT; 3306 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3307 >> EDID_TIMING_VFREQ_SHIFT; 3308 int timing_level = standard_timing_level(drm_edid); 3309 3310 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3311 return NULL; 3312 3313 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3314 hsize = t->hsize * 8 + 248; 3315 /* vrefresh_rate = vfreq + 60 */ 3316 vrefresh_rate = vfreq + 60; 3317 /* the vdisplay is calculated based on the aspect ratio */ 3318 if (aspect_ratio == 0) { 3319 if (drm_edid->edid->revision < 3) 3320 vsize = hsize; 3321 else 3322 vsize = (hsize * 10) / 16; 3323 } else if (aspect_ratio == 1) 3324 vsize = (hsize * 3) / 4; 3325 else if (aspect_ratio == 2) 3326 vsize = (hsize * 4) / 5; 3327 else 3328 vsize = (hsize * 9) / 16; 3329 3330 /* HDTV hack, part 1 */ 3331 if (vrefresh_rate == 60 && 3332 ((hsize == 1360 && vsize == 765) || 3333 (hsize == 1368 && vsize == 769))) { 3334 hsize = 1366; 3335 vsize = 768; 3336 } 3337 3338 /* 3339 * If this connector already has a mode for this size and refresh 3340 * rate (because it came from detailed or CVT info), use that 3341 * instead. This way we don't have to guess at interlace or 3342 * reduced blanking. 3343 */ 3344 list_for_each_entry(m, &connector->probed_modes, head) 3345 if (m->hdisplay == hsize && m->vdisplay == vsize && 3346 drm_mode_vrefresh(m) == vrefresh_rate) 3347 return NULL; 3348 3349 /* HDTV hack, part 2 */ 3350 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3351 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3352 false); 3353 if (!mode) 3354 return NULL; 3355 mode->hdisplay = 1366; 3356 mode->hsync_start = mode->hsync_start - 1; 3357 mode->hsync_end = mode->hsync_end - 1; 3358 return mode; 3359 } 3360 3361 /* check whether it can be found in default mode table */ 3362 if (drm_monitor_supports_rb(drm_edid)) { 3363 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3364 true); 3365 if (mode) 3366 return mode; 3367 } 3368 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3369 if (mode) 3370 return mode; 3371 3372 /* okay, generate it */ 3373 switch (timing_level) { 3374 case LEVEL_DMT: 3375 break; 3376 case LEVEL_GTF: 3377 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3378 break; 3379 case LEVEL_GTF2: 3380 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3381 break; 3382 case LEVEL_CVT: 3383 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3384 false); 3385 break; 3386 } 3387 return mode; 3388 } 3389 3390 /* 3391 * EDID is delightfully ambiguous about how interlaced modes are to be 3392 * encoded. Our internal representation is of frame height, but some 3393 * HDTV detailed timings are encoded as field height. 3394 * 3395 * The format list here is from CEA, in frame size. Technically we 3396 * should be checking refresh rate too. Whatever. 3397 */ 3398 static void 3399 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3400 const struct detailed_pixel_timing *pt) 3401 { 3402 int i; 3403 static const struct { 3404 int w, h; 3405 } cea_interlaced[] = { 3406 { 1920, 1080 }, 3407 { 720, 480 }, 3408 { 1440, 480 }, 3409 { 2880, 480 }, 3410 { 720, 576 }, 3411 { 1440, 576 }, 3412 { 2880, 576 }, 3413 }; 3414 3415 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3416 return; 3417 3418 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3419 if ((mode->hdisplay == cea_interlaced[i].w) && 3420 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3421 mode->vdisplay *= 2; 3422 mode->vsync_start *= 2; 3423 mode->vsync_end *= 2; 3424 mode->vtotal *= 2; 3425 mode->vtotal |= 1; 3426 } 3427 } 3428 3429 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3430 } 3431 3432 /* 3433 * Create a new mode from an EDID detailed timing section. An EDID detailed 3434 * timing block contains enough info for us to create and return a new struct 3435 * drm_display_mode. 3436 */ 3437 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3438 const struct drm_edid *drm_edid, 3439 const struct detailed_timing *timing) 3440 { 3441 const struct drm_display_info *info = &connector->display_info; 3442 struct drm_device *dev = connector->dev; 3443 struct drm_display_mode *mode; 3444 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3445 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3446 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3447 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3448 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3449 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3450 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3451 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3452 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3453 3454 /* ignore tiny modes */ 3455 if (hactive < 64 || vactive < 64) 3456 return NULL; 3457 3458 if (pt->misc & DRM_EDID_PT_STEREO) { 3459 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3460 connector->base.id, connector->name); 3461 return NULL; 3462 } 3463 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3464 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3465 connector->base.id, connector->name); 3466 } 3467 3468 /* it is incorrect if hsync/vsync width is zero */ 3469 if (!hsync_pulse_width || !vsync_pulse_width) { 3470 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3471 connector->base.id, connector->name); 3472 return NULL; 3473 } 3474 3475 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3476 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3477 if (!mode) 3478 return NULL; 3479 3480 goto set_size; 3481 } 3482 3483 mode = drm_mode_create(dev); 3484 if (!mode) 3485 return NULL; 3486 3487 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3488 mode->clock = 1088 * 10; 3489 else 3490 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3491 3492 mode->hdisplay = hactive; 3493 mode->hsync_start = mode->hdisplay + hsync_offset; 3494 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3495 mode->htotal = mode->hdisplay + hblank; 3496 3497 mode->vdisplay = vactive; 3498 mode->vsync_start = mode->vdisplay + vsync_offset; 3499 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3500 mode->vtotal = mode->vdisplay + vblank; 3501 3502 /* Some EDIDs have bogus h/vsync_end values */ 3503 if (mode->hsync_end > mode->htotal) { 3504 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3505 connector->base.id, connector->name, 3506 mode->hsync_end, mode->htotal); 3507 mode->hsync_end = mode->htotal; 3508 } 3509 if (mode->vsync_end > mode->vtotal) { 3510 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3511 connector->base.id, connector->name, 3512 mode->vsync_end, mode->vtotal); 3513 mode->vsync_end = mode->vtotal; 3514 } 3515 3516 drm_mode_do_interlace_quirk(mode, pt); 3517 3518 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3519 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3520 } else { 3521 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3522 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3523 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3524 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3525 } 3526 3527 set_size: 3528 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3529 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3530 3531 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3532 mode->width_mm *= 10; 3533 mode->height_mm *= 10; 3534 } 3535 3536 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3537 mode->width_mm = drm_edid->edid->width_cm * 10; 3538 mode->height_mm = drm_edid->edid->height_cm * 10; 3539 } 3540 3541 mode->type = DRM_MODE_TYPE_DRIVER; 3542 drm_mode_set_name(mode); 3543 3544 return mode; 3545 } 3546 3547 static bool 3548 mode_in_hsync_range(const struct drm_display_mode *mode, 3549 const struct edid *edid, const u8 *t) 3550 { 3551 int hsync, hmin, hmax; 3552 3553 hmin = t[7]; 3554 if (edid->revision >= 4) 3555 hmin += ((t[4] & 0x04) ? 255 : 0); 3556 hmax = t[8]; 3557 if (edid->revision >= 4) 3558 hmax += ((t[4] & 0x08) ? 255 : 0); 3559 hsync = drm_mode_hsync(mode); 3560 3561 return (hsync <= hmax && hsync >= hmin); 3562 } 3563 3564 static bool 3565 mode_in_vsync_range(const struct drm_display_mode *mode, 3566 const struct edid *edid, const u8 *t) 3567 { 3568 int vsync, vmin, vmax; 3569 3570 vmin = t[5]; 3571 if (edid->revision >= 4) 3572 vmin += ((t[4] & 0x01) ? 255 : 0); 3573 vmax = t[6]; 3574 if (edid->revision >= 4) 3575 vmax += ((t[4] & 0x02) ? 255 : 0); 3576 vsync = drm_mode_vrefresh(mode); 3577 3578 return (vsync <= vmax && vsync >= vmin); 3579 } 3580 3581 static u32 3582 range_pixel_clock(const struct edid *edid, const u8 *t) 3583 { 3584 /* unspecified */ 3585 if (t[9] == 0 || t[9] == 255) 3586 return 0; 3587 3588 /* 1.4 with CVT support gives us real precision, yay */ 3589 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3590 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3591 3592 /* 1.3 is pathetic, so fuzz up a bit */ 3593 return t[9] * 10000 + 5001; 3594 } 3595 3596 static bool mode_in_range(const struct drm_display_mode *mode, 3597 const struct drm_edid *drm_edid, 3598 const struct detailed_timing *timing) 3599 { 3600 const struct edid *edid = drm_edid->edid; 3601 u32 max_clock; 3602 const u8 *t = (const u8 *)timing; 3603 3604 if (!mode_in_hsync_range(mode, edid, t)) 3605 return false; 3606 3607 if (!mode_in_vsync_range(mode, edid, t)) 3608 return false; 3609 3610 if ((max_clock = range_pixel_clock(edid, t))) 3611 if (mode->clock > max_clock) 3612 return false; 3613 3614 /* 1.4 max horizontal check */ 3615 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3616 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3617 return false; 3618 3619 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3620 return false; 3621 3622 return true; 3623 } 3624 3625 static bool valid_inferred_mode(const struct drm_connector *connector, 3626 const struct drm_display_mode *mode) 3627 { 3628 const struct drm_display_mode *m; 3629 bool ok = false; 3630 3631 list_for_each_entry(m, &connector->probed_modes, head) { 3632 if (mode->hdisplay == m->hdisplay && 3633 mode->vdisplay == m->vdisplay && 3634 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3635 return false; /* duplicated */ 3636 if (mode->hdisplay <= m->hdisplay && 3637 mode->vdisplay <= m->vdisplay) 3638 ok = true; 3639 } 3640 return ok; 3641 } 3642 3643 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3644 const struct drm_edid *drm_edid, 3645 const struct detailed_timing *timing) 3646 { 3647 int i, modes = 0; 3648 struct drm_display_mode *newmode; 3649 struct drm_device *dev = connector->dev; 3650 3651 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3652 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3653 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3654 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3655 if (newmode) { 3656 drm_mode_probed_add(connector, newmode); 3657 modes++; 3658 } 3659 } 3660 } 3661 3662 return modes; 3663 } 3664 3665 /* fix up 1366x768 mode from 1368x768; 3666 * GFT/CVT can't express 1366 width which isn't dividable by 8 3667 */ 3668 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3669 { 3670 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3671 mode->hdisplay = 1366; 3672 mode->hsync_start--; 3673 mode->hsync_end--; 3674 drm_mode_set_name(mode); 3675 } 3676 } 3677 3678 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3679 const struct drm_edid *drm_edid, 3680 const struct detailed_timing *timing) 3681 { 3682 int i, modes = 0; 3683 struct drm_display_mode *newmode; 3684 struct drm_device *dev = connector->dev; 3685 3686 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3687 const struct minimode *m = &extra_modes[i]; 3688 3689 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3690 if (!newmode) 3691 return modes; 3692 3693 drm_mode_fixup_1366x768(newmode); 3694 if (!mode_in_range(newmode, drm_edid, timing) || 3695 !valid_inferred_mode(connector, newmode)) { 3696 drm_mode_destroy(dev, newmode); 3697 continue; 3698 } 3699 3700 drm_mode_probed_add(connector, newmode); 3701 modes++; 3702 } 3703 3704 return modes; 3705 } 3706 3707 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3708 const struct drm_edid *drm_edid, 3709 const struct detailed_timing *timing) 3710 { 3711 int i, modes = 0; 3712 struct drm_display_mode *newmode; 3713 struct drm_device *dev = connector->dev; 3714 3715 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3716 const struct minimode *m = &extra_modes[i]; 3717 3718 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3719 if (!newmode) 3720 return modes; 3721 3722 drm_mode_fixup_1366x768(newmode); 3723 if (!mode_in_range(newmode, drm_edid, timing) || 3724 !valid_inferred_mode(connector, newmode)) { 3725 drm_mode_destroy(dev, newmode); 3726 continue; 3727 } 3728 3729 drm_mode_probed_add(connector, newmode); 3730 modes++; 3731 } 3732 3733 return modes; 3734 } 3735 3736 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3737 const struct drm_edid *drm_edid, 3738 const struct detailed_timing *timing) 3739 { 3740 int i, modes = 0; 3741 struct drm_display_mode *newmode; 3742 struct drm_device *dev = connector->dev; 3743 bool rb = drm_monitor_supports_rb(drm_edid); 3744 3745 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3746 const struct minimode *m = &extra_modes[i]; 3747 3748 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3749 if (!newmode) 3750 return modes; 3751 3752 drm_mode_fixup_1366x768(newmode); 3753 if (!mode_in_range(newmode, drm_edid, timing) || 3754 !valid_inferred_mode(connector, newmode)) { 3755 drm_mode_destroy(dev, newmode); 3756 continue; 3757 } 3758 3759 drm_mode_probed_add(connector, newmode); 3760 modes++; 3761 } 3762 3763 return modes; 3764 } 3765 3766 static void 3767 do_inferred_modes(const struct detailed_timing *timing, void *c) 3768 { 3769 struct detailed_mode_closure *closure = c; 3770 const struct detailed_non_pixel *data = &timing->data.other_data; 3771 const struct detailed_data_monitor_range *range = &data->data.range; 3772 3773 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3774 return; 3775 3776 closure->modes += drm_dmt_modes_for_range(closure->connector, 3777 closure->drm_edid, 3778 timing); 3779 3780 if (closure->drm_edid->edid->revision < 2) 3781 return; /* GTF not defined yet */ 3782 3783 switch (range->flags) { 3784 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3785 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3786 closure->drm_edid, 3787 timing); 3788 break; 3789 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3790 closure->modes += drm_gtf_modes_for_range(closure->connector, 3791 closure->drm_edid, 3792 timing); 3793 break; 3794 case DRM_EDID_CVT_SUPPORT_FLAG: 3795 if (closure->drm_edid->edid->revision < 4) 3796 break; 3797 3798 closure->modes += drm_cvt_modes_for_range(closure->connector, 3799 closure->drm_edid, 3800 timing); 3801 break; 3802 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3803 default: 3804 break; 3805 } 3806 } 3807 3808 static int add_inferred_modes(struct drm_connector *connector, 3809 const struct drm_edid *drm_edid) 3810 { 3811 struct detailed_mode_closure closure = { 3812 .connector = connector, 3813 .drm_edid = drm_edid, 3814 }; 3815 3816 if (drm_edid->edid->revision >= 1) 3817 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3818 3819 return closure.modes; 3820 } 3821 3822 static int 3823 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3824 { 3825 int i, j, m, modes = 0; 3826 struct drm_display_mode *mode; 3827 const u8 *est = ((const u8 *)timing) + 6; 3828 3829 for (i = 0; i < 6; i++) { 3830 for (j = 7; j >= 0; j--) { 3831 m = (i * 8) + (7 - j); 3832 if (m >= ARRAY_SIZE(est3_modes)) 3833 break; 3834 if (est[i] & (1 << j)) { 3835 mode = drm_mode_find_dmt(connector->dev, 3836 est3_modes[m].w, 3837 est3_modes[m].h, 3838 est3_modes[m].r, 3839 est3_modes[m].rb); 3840 if (mode) { 3841 drm_mode_probed_add(connector, mode); 3842 modes++; 3843 } 3844 } 3845 } 3846 } 3847 3848 return modes; 3849 } 3850 3851 static void 3852 do_established_modes(const struct detailed_timing *timing, void *c) 3853 { 3854 struct detailed_mode_closure *closure = c; 3855 3856 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3857 return; 3858 3859 closure->modes += drm_est3_modes(closure->connector, timing); 3860 } 3861 3862 /* 3863 * Get established modes from EDID and add them. Each EDID block contains a 3864 * bitmap of the supported "established modes" list (defined above). Tease them 3865 * out and add them to the global modes list. 3866 */ 3867 static int add_established_modes(struct drm_connector *connector, 3868 const struct drm_edid *drm_edid) 3869 { 3870 struct drm_device *dev = connector->dev; 3871 const struct edid *edid = drm_edid->edid; 3872 unsigned long est_bits = edid->established_timings.t1 | 3873 (edid->established_timings.t2 << 8) | 3874 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3875 int i, modes = 0; 3876 struct detailed_mode_closure closure = { 3877 .connector = connector, 3878 .drm_edid = drm_edid, 3879 }; 3880 3881 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3882 if (est_bits & (1<<i)) { 3883 struct drm_display_mode *newmode; 3884 3885 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3886 if (newmode) { 3887 drm_mode_probed_add(connector, newmode); 3888 modes++; 3889 } 3890 } 3891 } 3892 3893 if (edid->revision >= 1) 3894 drm_for_each_detailed_block(drm_edid, do_established_modes, 3895 &closure); 3896 3897 return modes + closure.modes; 3898 } 3899 3900 static void 3901 do_standard_modes(const struct detailed_timing *timing, void *c) 3902 { 3903 struct detailed_mode_closure *closure = c; 3904 const struct detailed_non_pixel *data = &timing->data.other_data; 3905 struct drm_connector *connector = closure->connector; 3906 int i; 3907 3908 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3909 return; 3910 3911 for (i = 0; i < 6; i++) { 3912 const struct std_timing *std = &data->data.timings[i]; 3913 struct drm_display_mode *newmode; 3914 3915 newmode = drm_mode_std(connector, closure->drm_edid, std); 3916 if (newmode) { 3917 drm_mode_probed_add(connector, newmode); 3918 closure->modes++; 3919 } 3920 } 3921 } 3922 3923 /* 3924 * Get standard modes from EDID and add them. Standard modes can be calculated 3925 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3926 * add them to the list. 3927 */ 3928 static int add_standard_modes(struct drm_connector *connector, 3929 const struct drm_edid *drm_edid) 3930 { 3931 int i, modes = 0; 3932 struct detailed_mode_closure closure = { 3933 .connector = connector, 3934 .drm_edid = drm_edid, 3935 }; 3936 3937 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3938 struct drm_display_mode *newmode; 3939 3940 newmode = drm_mode_std(connector, drm_edid, 3941 &drm_edid->edid->standard_timings[i]); 3942 if (newmode) { 3943 drm_mode_probed_add(connector, newmode); 3944 modes++; 3945 } 3946 } 3947 3948 if (drm_edid->edid->revision >= 1) 3949 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3950 &closure); 3951 3952 /* XXX should also look for standard codes in VTB blocks */ 3953 3954 return modes + closure.modes; 3955 } 3956 3957 static int drm_cvt_modes(struct drm_connector *connector, 3958 const struct detailed_timing *timing) 3959 { 3960 int i, j, modes = 0; 3961 struct drm_display_mode *newmode; 3962 struct drm_device *dev = connector->dev; 3963 const struct cvt_timing *cvt; 3964 static const int rates[] = { 60, 85, 75, 60, 50 }; 3965 const u8 empty[3] = { 0, 0, 0 }; 3966 3967 for (i = 0; i < 4; i++) { 3968 int width, height; 3969 3970 cvt = &(timing->data.other_data.data.cvt[i]); 3971 3972 if (!memcmp(cvt->code, empty, 3)) 3973 continue; 3974 3975 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3976 switch (cvt->code[1] & 0x0c) { 3977 /* default - because compiler doesn't see that we've enumerated all cases */ 3978 default: 3979 case 0x00: 3980 width = height * 4 / 3; 3981 break; 3982 case 0x04: 3983 width = height * 16 / 9; 3984 break; 3985 case 0x08: 3986 width = height * 16 / 10; 3987 break; 3988 case 0x0c: 3989 width = height * 15 / 9; 3990 break; 3991 } 3992 3993 for (j = 1; j < 5; j++) { 3994 if (cvt->code[2] & (1 << j)) { 3995 newmode = drm_cvt_mode(dev, width, height, 3996 rates[j], j == 0, 3997 false, false); 3998 if (newmode) { 3999 drm_mode_probed_add(connector, newmode); 4000 modes++; 4001 } 4002 } 4003 } 4004 } 4005 4006 return modes; 4007 } 4008 4009 static void 4010 do_cvt_mode(const struct detailed_timing *timing, void *c) 4011 { 4012 struct detailed_mode_closure *closure = c; 4013 4014 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4015 return; 4016 4017 closure->modes += drm_cvt_modes(closure->connector, timing); 4018 } 4019 4020 static int 4021 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4022 { 4023 struct detailed_mode_closure closure = { 4024 .connector = connector, 4025 .drm_edid = drm_edid, 4026 }; 4027 4028 if (drm_edid->edid->revision >= 3) 4029 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4030 4031 /* XXX should also look for CVT codes in VTB blocks */ 4032 4033 return closure.modes; 4034 } 4035 4036 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4037 struct drm_display_mode *mode); 4038 4039 static void 4040 do_detailed_mode(const struct detailed_timing *timing, void *c) 4041 { 4042 struct detailed_mode_closure *closure = c; 4043 struct drm_display_mode *newmode; 4044 4045 if (!is_detailed_timing_descriptor(timing)) 4046 return; 4047 4048 newmode = drm_mode_detailed(closure->connector, 4049 closure->drm_edid, timing); 4050 if (!newmode) 4051 return; 4052 4053 if (closure->preferred) 4054 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4055 4056 /* 4057 * Detailed modes are limited to 10kHz pixel clock resolution, 4058 * so fix up anything that looks like CEA/HDMI mode, but the clock 4059 * is just slightly off. 4060 */ 4061 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4062 4063 drm_mode_probed_add(closure->connector, newmode); 4064 closure->modes++; 4065 closure->preferred = false; 4066 } 4067 4068 /* 4069 * add_detailed_modes - Add modes from detailed timings 4070 * @connector: attached connector 4071 * @drm_edid: EDID block to scan 4072 */ 4073 static int add_detailed_modes(struct drm_connector *connector, 4074 const struct drm_edid *drm_edid) 4075 { 4076 struct detailed_mode_closure closure = { 4077 .connector = connector, 4078 .drm_edid = drm_edid, 4079 }; 4080 4081 if (drm_edid->edid->revision >= 4) 4082 closure.preferred = true; /* first detailed timing is always preferred */ 4083 else 4084 closure.preferred = 4085 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4086 4087 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4088 4089 return closure.modes; 4090 } 4091 4092 /* CTA-861-H Table 60 - CTA Tag Codes */ 4093 #define CTA_DB_AUDIO 1 4094 #define CTA_DB_VIDEO 2 4095 #define CTA_DB_VENDOR 3 4096 #define CTA_DB_SPEAKER 4 4097 #define CTA_DB_EXTENDED_TAG 7 4098 4099 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4100 #define CTA_EXT_DB_VIDEO_CAP 0 4101 #define CTA_EXT_DB_VENDOR 1 4102 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4103 #define CTA_EXT_DB_420_VIDEO_DATA 14 4104 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4105 #define CTA_EXT_DB_HF_EEODB 0x78 4106 #define CTA_EXT_DB_HF_SCDB 0x79 4107 4108 #define EDID_BASIC_AUDIO (1 << 6) 4109 #define EDID_CEA_YCRCB444 (1 << 5) 4110 #define EDID_CEA_YCRCB422 (1 << 4) 4111 #define EDID_CEA_VCDB_QS (1 << 6) 4112 4113 /* 4114 * Search EDID for CEA extension block. 4115 * 4116 * FIXME: Prefer not returning pointers to raw EDID data. 4117 */ 4118 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4119 int ext_id, int *ext_index) 4120 { 4121 const u8 *edid_ext = NULL; 4122 int i; 4123 4124 /* No EDID or EDID extensions */ 4125 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4126 return NULL; 4127 4128 /* Find CEA extension */ 4129 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4130 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4131 if (edid_block_tag(edid_ext) == ext_id) 4132 break; 4133 } 4134 4135 if (i >= drm_edid_extension_block_count(drm_edid)) 4136 return NULL; 4137 4138 *ext_index = i + 1; 4139 4140 return edid_ext; 4141 } 4142 4143 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4144 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4145 { 4146 const struct displayid_block *block; 4147 struct displayid_iter iter; 4148 int ext_index = 0; 4149 bool found = false; 4150 4151 /* Look for a top level CEA extension block */ 4152 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4153 return true; 4154 4155 /* CEA blocks can also be found embedded in a DisplayID block */ 4156 displayid_iter_edid_begin(drm_edid, &iter); 4157 displayid_iter_for_each(block, &iter) { 4158 if (block->tag == DATA_BLOCK_CTA) { 4159 found = true; 4160 break; 4161 } 4162 } 4163 displayid_iter_end(&iter); 4164 4165 return found; 4166 } 4167 4168 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4169 { 4170 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4171 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4172 4173 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4174 return &edid_cea_modes_1[vic - 1]; 4175 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4176 return &edid_cea_modes_193[vic - 193]; 4177 return NULL; 4178 } 4179 4180 static u8 cea_num_vics(void) 4181 { 4182 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4183 } 4184 4185 static u8 cea_next_vic(u8 vic) 4186 { 4187 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4188 vic = 193; 4189 return vic; 4190 } 4191 4192 /* 4193 * Calculate the alternate clock for the CEA mode 4194 * (60Hz vs. 59.94Hz etc.) 4195 */ 4196 static unsigned int 4197 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4198 { 4199 unsigned int clock = cea_mode->clock; 4200 4201 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4202 return clock; 4203 4204 /* 4205 * edid_cea_modes contains the 59.94Hz 4206 * variant for 240 and 480 line modes, 4207 * and the 60Hz variant otherwise. 4208 */ 4209 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4210 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4211 else 4212 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4213 4214 return clock; 4215 } 4216 4217 static bool 4218 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4219 { 4220 /* 4221 * For certain VICs the spec allows the vertical 4222 * front porch to vary by one or two lines. 4223 * 4224 * cea_modes[] stores the variant with the shortest 4225 * vertical front porch. We can adjust the mode to 4226 * get the other variants by simply increasing the 4227 * vertical front porch length. 4228 */ 4229 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4230 cea_mode_for_vic(9)->vtotal != 262 || 4231 cea_mode_for_vic(12)->vtotal != 262 || 4232 cea_mode_for_vic(13)->vtotal != 262 || 4233 cea_mode_for_vic(23)->vtotal != 312 || 4234 cea_mode_for_vic(24)->vtotal != 312 || 4235 cea_mode_for_vic(27)->vtotal != 312 || 4236 cea_mode_for_vic(28)->vtotal != 312); 4237 4238 if (((vic == 8 || vic == 9 || 4239 vic == 12 || vic == 13) && mode->vtotal < 263) || 4240 ((vic == 23 || vic == 24 || 4241 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4242 mode->vsync_start++; 4243 mode->vsync_end++; 4244 mode->vtotal++; 4245 4246 return true; 4247 } 4248 4249 return false; 4250 } 4251 4252 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4253 unsigned int clock_tolerance) 4254 { 4255 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4256 u8 vic; 4257 4258 if (!to_match->clock) 4259 return 0; 4260 4261 if (to_match->picture_aspect_ratio) 4262 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4263 4264 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4265 struct drm_display_mode cea_mode; 4266 unsigned int clock1, clock2; 4267 4268 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4269 4270 /* Check both 60Hz and 59.94Hz */ 4271 clock1 = cea_mode.clock; 4272 clock2 = cea_mode_alternate_clock(&cea_mode); 4273 4274 if (abs(to_match->clock - clock1) > clock_tolerance && 4275 abs(to_match->clock - clock2) > clock_tolerance) 4276 continue; 4277 4278 do { 4279 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4280 return vic; 4281 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4282 } 4283 4284 return 0; 4285 } 4286 4287 /** 4288 * drm_match_cea_mode - look for a CEA mode matching given mode 4289 * @to_match: display mode 4290 * 4291 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4292 * mode. 4293 */ 4294 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4295 { 4296 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4297 u8 vic; 4298 4299 if (!to_match->clock) 4300 return 0; 4301 4302 if (to_match->picture_aspect_ratio) 4303 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4304 4305 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4306 struct drm_display_mode cea_mode; 4307 unsigned int clock1, clock2; 4308 4309 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4310 4311 /* Check both 60Hz and 59.94Hz */ 4312 clock1 = cea_mode.clock; 4313 clock2 = cea_mode_alternate_clock(&cea_mode); 4314 4315 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4316 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4317 continue; 4318 4319 do { 4320 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4321 return vic; 4322 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4323 } 4324 4325 return 0; 4326 } 4327 EXPORT_SYMBOL(drm_match_cea_mode); 4328 4329 static bool drm_valid_cea_vic(u8 vic) 4330 { 4331 return cea_mode_for_vic(vic) != NULL; 4332 } 4333 4334 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4335 { 4336 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4337 4338 if (mode) 4339 return mode->picture_aspect_ratio; 4340 4341 return HDMI_PICTURE_ASPECT_NONE; 4342 } 4343 4344 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4345 { 4346 return edid_4k_modes[video_code].picture_aspect_ratio; 4347 } 4348 4349 /* 4350 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4351 * specific block). 4352 */ 4353 static unsigned int 4354 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4355 { 4356 return cea_mode_alternate_clock(hdmi_mode); 4357 } 4358 4359 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4360 unsigned int clock_tolerance) 4361 { 4362 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4363 u8 vic; 4364 4365 if (!to_match->clock) 4366 return 0; 4367 4368 if (to_match->picture_aspect_ratio) 4369 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4370 4371 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4372 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4373 unsigned int clock1, clock2; 4374 4375 /* Make sure to also match alternate clocks */ 4376 clock1 = hdmi_mode->clock; 4377 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4378 4379 if (abs(to_match->clock - clock1) > clock_tolerance && 4380 abs(to_match->clock - clock2) > clock_tolerance) 4381 continue; 4382 4383 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4384 return vic; 4385 } 4386 4387 return 0; 4388 } 4389 4390 /* 4391 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4392 * @to_match: display mode 4393 * 4394 * An HDMI mode is one defined in the HDMI vendor specific block. 4395 * 4396 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4397 */ 4398 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4399 { 4400 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4401 u8 vic; 4402 4403 if (!to_match->clock) 4404 return 0; 4405 4406 if (to_match->picture_aspect_ratio) 4407 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4408 4409 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4410 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4411 unsigned int clock1, clock2; 4412 4413 /* Make sure to also match alternate clocks */ 4414 clock1 = hdmi_mode->clock; 4415 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4416 4417 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4418 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4419 drm_mode_match(to_match, hdmi_mode, match_flags)) 4420 return vic; 4421 } 4422 return 0; 4423 } 4424 4425 static bool drm_valid_hdmi_vic(u8 vic) 4426 { 4427 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4428 } 4429 4430 static int add_alternate_cea_modes(struct drm_connector *connector, 4431 const struct drm_edid *drm_edid) 4432 { 4433 struct drm_device *dev = connector->dev; 4434 struct drm_display_mode *mode, *tmp; 4435 LIST_HEAD(list); 4436 int modes = 0; 4437 4438 /* Don't add CTA modes if the CTA extension block is missing */ 4439 if (!drm_edid_has_cta_extension(drm_edid)) 4440 return 0; 4441 4442 /* 4443 * Go through all probed modes and create a new mode 4444 * with the alternate clock for certain CEA modes. 4445 */ 4446 list_for_each_entry(mode, &connector->probed_modes, head) { 4447 const struct drm_display_mode *cea_mode = NULL; 4448 struct drm_display_mode *newmode; 4449 u8 vic = drm_match_cea_mode(mode); 4450 unsigned int clock1, clock2; 4451 4452 if (drm_valid_cea_vic(vic)) { 4453 cea_mode = cea_mode_for_vic(vic); 4454 clock2 = cea_mode_alternate_clock(cea_mode); 4455 } else { 4456 vic = drm_match_hdmi_mode(mode); 4457 if (drm_valid_hdmi_vic(vic)) { 4458 cea_mode = &edid_4k_modes[vic]; 4459 clock2 = hdmi_mode_alternate_clock(cea_mode); 4460 } 4461 } 4462 4463 if (!cea_mode) 4464 continue; 4465 4466 clock1 = cea_mode->clock; 4467 4468 if (clock1 == clock2) 4469 continue; 4470 4471 if (mode->clock != clock1 && mode->clock != clock2) 4472 continue; 4473 4474 newmode = drm_mode_duplicate(dev, cea_mode); 4475 if (!newmode) 4476 continue; 4477 4478 /* Carry over the stereo flags */ 4479 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4480 4481 /* 4482 * The current mode could be either variant. Make 4483 * sure to pick the "other" clock for the new mode. 4484 */ 4485 if (mode->clock != clock1) 4486 newmode->clock = clock1; 4487 else 4488 newmode->clock = clock2; 4489 4490 list_add_tail(&newmode->head, &list); 4491 } 4492 4493 list_for_each_entry_safe(mode, tmp, &list, head) { 4494 list_del(&mode->head); 4495 drm_mode_probed_add(connector, mode); 4496 modes++; 4497 } 4498 4499 return modes; 4500 } 4501 4502 static u8 svd_to_vic(u8 svd) 4503 { 4504 /* 0-6 bit vic, 7th bit native mode indicator */ 4505 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4506 return svd & 127; 4507 4508 return svd; 4509 } 4510 4511 /* 4512 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4513 * the EDID, or NULL on errors. 4514 */ 4515 static struct drm_display_mode * 4516 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4517 { 4518 const struct drm_display_info *info = &connector->display_info; 4519 struct drm_device *dev = connector->dev; 4520 4521 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4522 return NULL; 4523 4524 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4525 } 4526 4527 /* 4528 * do_y420vdb_modes - Parse YCBCR 420 only modes 4529 * @connector: connector corresponding to the HDMI sink 4530 * @svds: start of the data block of CEA YCBCR 420 VDB 4531 * @len: length of the CEA YCBCR 420 VDB 4532 * 4533 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4534 * which contains modes which can be supported in YCBCR 420 4535 * output format only. 4536 */ 4537 static int do_y420vdb_modes(struct drm_connector *connector, 4538 const u8 *svds, u8 svds_len) 4539 { 4540 struct drm_device *dev = connector->dev; 4541 int modes = 0, i; 4542 4543 for (i = 0; i < svds_len; i++) { 4544 u8 vic = svd_to_vic(svds[i]); 4545 struct drm_display_mode *newmode; 4546 4547 if (!drm_valid_cea_vic(vic)) 4548 continue; 4549 4550 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4551 if (!newmode) 4552 break; 4553 drm_mode_probed_add(connector, newmode); 4554 modes++; 4555 } 4556 4557 return modes; 4558 } 4559 4560 /** 4561 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4562 * @dev: DRM device 4563 * @video_code: CEA VIC of the mode 4564 * 4565 * Creates a new mode matching the specified CEA VIC. 4566 * 4567 * Returns: A new drm_display_mode on success or NULL on failure 4568 */ 4569 struct drm_display_mode * 4570 drm_display_mode_from_cea_vic(struct drm_device *dev, 4571 u8 video_code) 4572 { 4573 const struct drm_display_mode *cea_mode; 4574 struct drm_display_mode *newmode; 4575 4576 cea_mode = cea_mode_for_vic(video_code); 4577 if (!cea_mode) 4578 return NULL; 4579 4580 newmode = drm_mode_duplicate(dev, cea_mode); 4581 if (!newmode) 4582 return NULL; 4583 4584 return newmode; 4585 } 4586 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4587 4588 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4589 static int add_cta_vdb_modes(struct drm_connector *connector) 4590 { 4591 const struct drm_display_info *info = &connector->display_info; 4592 int i, modes = 0; 4593 4594 if (!info->vics) 4595 return 0; 4596 4597 for (i = 0; i < info->vics_len; i++) { 4598 struct drm_display_mode *mode; 4599 4600 mode = drm_display_mode_from_vic_index(connector, i); 4601 if (mode) { 4602 drm_mode_probed_add(connector, mode); 4603 modes++; 4604 } 4605 } 4606 4607 return modes; 4608 } 4609 4610 struct stereo_mandatory_mode { 4611 int width, height, vrefresh; 4612 unsigned int flags; 4613 }; 4614 4615 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4616 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4617 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4618 { 1920, 1080, 50, 4619 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4620 { 1920, 1080, 60, 4621 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4622 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4623 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4624 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4625 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4626 }; 4627 4628 static bool 4629 stereo_match_mandatory(const struct drm_display_mode *mode, 4630 const struct stereo_mandatory_mode *stereo_mode) 4631 { 4632 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4633 4634 return mode->hdisplay == stereo_mode->width && 4635 mode->vdisplay == stereo_mode->height && 4636 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4637 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4638 } 4639 4640 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4641 { 4642 struct drm_device *dev = connector->dev; 4643 const struct drm_display_mode *mode; 4644 struct list_head stereo_modes; 4645 int modes = 0, i; 4646 4647 INIT_LIST_HEAD(&stereo_modes); 4648 4649 list_for_each_entry(mode, &connector->probed_modes, head) { 4650 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4651 const struct stereo_mandatory_mode *mandatory; 4652 struct drm_display_mode *new_mode; 4653 4654 if (!stereo_match_mandatory(mode, 4655 &stereo_mandatory_modes[i])) 4656 continue; 4657 4658 mandatory = &stereo_mandatory_modes[i]; 4659 new_mode = drm_mode_duplicate(dev, mode); 4660 if (!new_mode) 4661 continue; 4662 4663 new_mode->flags |= mandatory->flags; 4664 list_add_tail(&new_mode->head, &stereo_modes); 4665 modes++; 4666 } 4667 } 4668 4669 list_splice_tail(&stereo_modes, &connector->probed_modes); 4670 4671 return modes; 4672 } 4673 4674 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4675 { 4676 struct drm_device *dev = connector->dev; 4677 struct drm_display_mode *newmode; 4678 4679 if (!drm_valid_hdmi_vic(vic)) { 4680 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4681 connector->base.id, connector->name, vic); 4682 return 0; 4683 } 4684 4685 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4686 if (!newmode) 4687 return 0; 4688 4689 drm_mode_probed_add(connector, newmode); 4690 4691 return 1; 4692 } 4693 4694 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4695 int vic_index) 4696 { 4697 struct drm_display_mode *newmode; 4698 int modes = 0; 4699 4700 if (structure & (1 << 0)) { 4701 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4702 if (newmode) { 4703 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4704 drm_mode_probed_add(connector, newmode); 4705 modes++; 4706 } 4707 } 4708 if (structure & (1 << 6)) { 4709 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4710 if (newmode) { 4711 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4712 drm_mode_probed_add(connector, newmode); 4713 modes++; 4714 } 4715 } 4716 if (structure & (1 << 8)) { 4717 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4718 if (newmode) { 4719 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4720 drm_mode_probed_add(connector, newmode); 4721 modes++; 4722 } 4723 } 4724 4725 return modes; 4726 } 4727 4728 static bool hdmi_vsdb_latency_present(const u8 *db) 4729 { 4730 return db[8] & BIT(7); 4731 } 4732 4733 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4734 { 4735 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4736 } 4737 4738 static int hdmi_vsdb_latency_length(const u8 *db) 4739 { 4740 if (hdmi_vsdb_i_latency_present(db)) 4741 return 4; 4742 else if (hdmi_vsdb_latency_present(db)) 4743 return 2; 4744 else 4745 return 0; 4746 } 4747 4748 /* 4749 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4750 * @connector: connector corresponding to the HDMI sink 4751 * @db: start of the CEA vendor specific block 4752 * @len: length of the CEA block payload, ie. one can access up to db[len] 4753 * 4754 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4755 * also adds the stereo 3d modes when applicable. 4756 */ 4757 static int 4758 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4759 { 4760 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4761 u8 vic_len, hdmi_3d_len = 0; 4762 u16 mask; 4763 u16 structure_all; 4764 4765 if (len < 8) 4766 goto out; 4767 4768 /* no HDMI_Video_Present */ 4769 if (!(db[8] & (1 << 5))) 4770 goto out; 4771 4772 offset += hdmi_vsdb_latency_length(db); 4773 4774 /* the declared length is not long enough for the 2 first bytes 4775 * of additional video format capabilities */ 4776 if (len < (8 + offset + 2)) 4777 goto out; 4778 4779 /* 3D_Present */ 4780 offset++; 4781 if (db[8 + offset] & (1 << 7)) { 4782 modes += add_hdmi_mandatory_stereo_modes(connector); 4783 4784 /* 3D_Multi_present */ 4785 multi_present = (db[8 + offset] & 0x60) >> 5; 4786 } 4787 4788 offset++; 4789 vic_len = db[8 + offset] >> 5; 4790 hdmi_3d_len = db[8 + offset] & 0x1f; 4791 4792 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4793 u8 vic; 4794 4795 vic = db[9 + offset + i]; 4796 modes += add_hdmi_mode(connector, vic); 4797 } 4798 offset += 1 + vic_len; 4799 4800 if (multi_present == 1) 4801 multi_len = 2; 4802 else if (multi_present == 2) 4803 multi_len = 4; 4804 else 4805 multi_len = 0; 4806 4807 if (len < (8 + offset + hdmi_3d_len - 1)) 4808 goto out; 4809 4810 if (hdmi_3d_len < multi_len) 4811 goto out; 4812 4813 if (multi_present == 1 || multi_present == 2) { 4814 /* 3D_Structure_ALL */ 4815 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4816 4817 /* check if 3D_MASK is present */ 4818 if (multi_present == 2) 4819 mask = (db[10 + offset] << 8) | db[11 + offset]; 4820 else 4821 mask = 0xffff; 4822 4823 for (i = 0; i < 16; i++) { 4824 if (mask & (1 << i)) 4825 modes += add_3d_struct_modes(connector, 4826 structure_all, i); 4827 } 4828 } 4829 4830 offset += multi_len; 4831 4832 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4833 int vic_index; 4834 struct drm_display_mode *newmode = NULL; 4835 unsigned int newflag = 0; 4836 bool detail_present; 4837 4838 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4839 4840 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4841 break; 4842 4843 /* 2D_VIC_order_X */ 4844 vic_index = db[8 + offset + i] >> 4; 4845 4846 /* 3D_Structure_X */ 4847 switch (db[8 + offset + i] & 0x0f) { 4848 case 0: 4849 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4850 break; 4851 case 6: 4852 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4853 break; 4854 case 8: 4855 /* 3D_Detail_X */ 4856 if ((db[9 + offset + i] >> 4) == 1) 4857 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4858 break; 4859 } 4860 4861 if (newflag != 0) { 4862 newmode = drm_display_mode_from_vic_index(connector, 4863 vic_index); 4864 4865 if (newmode) { 4866 newmode->flags |= newflag; 4867 drm_mode_probed_add(connector, newmode); 4868 modes++; 4869 } 4870 } 4871 4872 if (detail_present) 4873 i++; 4874 } 4875 4876 out: 4877 return modes; 4878 } 4879 4880 static int 4881 cea_revision(const u8 *cea) 4882 { 4883 /* 4884 * FIXME is this correct for the DispID variant? 4885 * The DispID spec doesn't really specify whether 4886 * this is the revision of the CEA extension or 4887 * the DispID CEA data block. And the only value 4888 * given as an example is 0. 4889 */ 4890 return cea[1]; 4891 } 4892 4893 /* 4894 * CTA Data Block iterator. 4895 * 4896 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4897 * CTA Data Blocks. 4898 * 4899 * struct cea_db *db: 4900 * struct cea_db_iter iter; 4901 * 4902 * cea_db_iter_edid_begin(edid, &iter); 4903 * cea_db_iter_for_each(db, &iter) { 4904 * // do stuff with db 4905 * } 4906 * cea_db_iter_end(&iter); 4907 */ 4908 struct cea_db_iter { 4909 struct drm_edid_iter edid_iter; 4910 struct displayid_iter displayid_iter; 4911 4912 /* Current Data Block Collection. */ 4913 const u8 *collection; 4914 4915 /* Current Data Block index in current collection. */ 4916 int index; 4917 4918 /* End index in current collection. */ 4919 int end; 4920 }; 4921 4922 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4923 struct cea_db { 4924 u8 tag_length; 4925 u8 data[]; 4926 } __packed; 4927 4928 static int cea_db_tag(const struct cea_db *db) 4929 { 4930 return db->tag_length >> 5; 4931 } 4932 4933 static int cea_db_payload_len(const void *_db) 4934 { 4935 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4936 const struct cea_db *db = _db; 4937 4938 return db->tag_length & 0x1f; 4939 } 4940 4941 static const void *cea_db_data(const struct cea_db *db) 4942 { 4943 return db->data; 4944 } 4945 4946 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4947 { 4948 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4949 cea_db_payload_len(db) >= 1 && 4950 db->data[0] == tag; 4951 } 4952 4953 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4954 { 4955 const u8 *data = cea_db_data(db); 4956 4957 return cea_db_tag(db) == CTA_DB_VENDOR && 4958 cea_db_payload_len(db) >= 3 && 4959 oui(data[2], data[1], data[0]) == vendor_oui; 4960 } 4961 4962 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4963 struct cea_db_iter *iter) 4964 { 4965 memset(iter, 0, sizeof(*iter)); 4966 4967 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4968 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4969 } 4970 4971 static const struct cea_db * 4972 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4973 { 4974 const struct cea_db *db; 4975 4976 if (!iter->collection) 4977 return NULL; 4978 4979 db = (const struct cea_db *)&iter->collection[iter->index]; 4980 4981 if (iter->index + sizeof(*db) <= iter->end && 4982 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4983 return db; 4984 4985 return NULL; 4986 } 4987 4988 /* 4989 * References: 4990 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4991 */ 4992 static int cea_db_collection_size(const u8 *cta) 4993 { 4994 u8 d = cta[2]; 4995 4996 if (d < 4 || d > 127) 4997 return 0; 4998 4999 return d - 4; 5000 } 5001 5002 /* 5003 * References: 5004 * - VESA E-EDID v1.4 5005 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5006 */ 5007 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5008 { 5009 const u8 *ext; 5010 5011 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5012 int size; 5013 5014 /* Only support CTA Extension revision 3+ */ 5015 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5016 continue; 5017 5018 size = cea_db_collection_size(ext); 5019 if (!size) 5020 continue; 5021 5022 iter->index = 4; 5023 iter->end = iter->index + size; 5024 5025 return ext; 5026 } 5027 5028 return NULL; 5029 } 5030 5031 /* 5032 * References: 5033 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5034 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5035 * 5036 * Note that the above do not specify any connection between DisplayID Data 5037 * Block revision and CTA Extension versions. 5038 */ 5039 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5040 { 5041 const struct displayid_block *block; 5042 5043 displayid_iter_for_each(block, &iter->displayid_iter) { 5044 if (block->tag != DATA_BLOCK_CTA) 5045 continue; 5046 5047 /* 5048 * The displayid iterator has already verified the block bounds 5049 * in displayid_iter_block(). 5050 */ 5051 iter->index = sizeof(*block); 5052 iter->end = iter->index + block->num_bytes; 5053 5054 return block; 5055 } 5056 5057 return NULL; 5058 } 5059 5060 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5061 { 5062 const struct cea_db *db; 5063 5064 if (iter->collection) { 5065 /* Current collection should always be valid. */ 5066 db = __cea_db_iter_current_block(iter); 5067 if (WARN_ON(!db)) { 5068 iter->collection = NULL; 5069 return NULL; 5070 } 5071 5072 /* Next block in CTA Data Block Collection */ 5073 iter->index += sizeof(*db) + cea_db_payload_len(db); 5074 5075 db = __cea_db_iter_current_block(iter); 5076 if (db) 5077 return db; 5078 } 5079 5080 for (;;) { 5081 /* 5082 * Find the next CTA Data Block Collection. First iterate all 5083 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5084 * 5085 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5086 * Extension, it's recommended that DisplayID extensions are 5087 * exposed after all of the CTA Extensions. 5088 */ 5089 iter->collection = __cea_db_iter_edid_next(iter); 5090 if (!iter->collection) 5091 iter->collection = __cea_db_iter_displayid_next(iter); 5092 5093 if (!iter->collection) 5094 return NULL; 5095 5096 db = __cea_db_iter_current_block(iter); 5097 if (db) 5098 return db; 5099 } 5100 } 5101 5102 #define cea_db_iter_for_each(__db, __iter) \ 5103 while (((__db) = __cea_db_iter_next(__iter))) 5104 5105 static void cea_db_iter_end(struct cea_db_iter *iter) 5106 { 5107 displayid_iter_end(&iter->displayid_iter); 5108 drm_edid_iter_end(&iter->edid_iter); 5109 5110 memset(iter, 0, sizeof(*iter)); 5111 } 5112 5113 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5114 { 5115 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5116 cea_db_payload_len(db) >= 5; 5117 } 5118 5119 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5120 { 5121 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5122 cea_db_payload_len(db) >= 7; 5123 } 5124 5125 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5126 { 5127 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5128 cea_db_payload_len(db) >= 2; 5129 } 5130 5131 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5132 { 5133 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5134 cea_db_payload_len(db) == 21; 5135 } 5136 5137 static bool cea_db_is_vcdb(const struct cea_db *db) 5138 { 5139 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5140 cea_db_payload_len(db) == 2; 5141 } 5142 5143 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5144 { 5145 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5146 cea_db_payload_len(db) >= 7; 5147 } 5148 5149 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5150 { 5151 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5152 } 5153 5154 static bool cea_db_is_y420vdb(const struct cea_db *db) 5155 { 5156 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5157 } 5158 5159 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5160 { 5161 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5162 cea_db_payload_len(db) >= 3; 5163 } 5164 5165 /* 5166 * Get the HF-EEODB override extension block count from EDID. 5167 * 5168 * The passed in EDID may be partially read, as long as it has at least two 5169 * blocks (base block and one extension block) if EDID extension count is > 0. 5170 * 5171 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5172 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5173 * iterators instead. 5174 * 5175 * References: 5176 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5177 */ 5178 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5179 { 5180 const u8 *cta; 5181 5182 /* No extensions according to base block, no HF-EEODB. */ 5183 if (!edid_extension_block_count(edid)) 5184 return 0; 5185 5186 /* HF-EEODB is always in the first EDID extension block only */ 5187 cta = edid_extension_block_data(edid, 0); 5188 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5189 return 0; 5190 5191 /* Need to have the data block collection, and at least 3 bytes. */ 5192 if (cea_db_collection_size(cta) < 3) 5193 return 0; 5194 5195 /* 5196 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5197 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5198 * through 6 of Block 1 of the E-EDID. 5199 */ 5200 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5201 return 0; 5202 5203 return cta[4 + 2]; 5204 } 5205 5206 /* 5207 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5208 * 5209 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5210 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5211 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5212 * support YCBCR420 output too. 5213 */ 5214 static void parse_cta_y420cmdb(struct drm_connector *connector, 5215 const struct cea_db *db, u64 *y420cmdb_map) 5216 { 5217 struct drm_display_info *info = &connector->display_info; 5218 int i, map_len = cea_db_payload_len(db) - 1; 5219 const u8 *data = cea_db_data(db) + 1; 5220 u64 map = 0; 5221 5222 if (map_len == 0) { 5223 /* All CEA modes support ycbcr420 sampling also.*/ 5224 map = U64_MAX; 5225 goto out; 5226 } 5227 5228 /* 5229 * This map indicates which of the existing CEA block modes 5230 * from VDB can support YCBCR420 output too. So if bit=0 is 5231 * set, first mode from VDB can support YCBCR420 output too. 5232 * We will parse and keep this map, before parsing VDB itself 5233 * to avoid going through the same block again and again. 5234 * 5235 * Spec is not clear about max possible size of this block. 5236 * Clamping max bitmap block size at 8 bytes. Every byte can 5237 * address 8 CEA modes, in this way this map can address 5238 * 8*8 = first 64 SVDs. 5239 */ 5240 if (WARN_ON_ONCE(map_len > 8)) 5241 map_len = 8; 5242 5243 for (i = 0; i < map_len; i++) 5244 map |= (u64)data[i] << (8 * i); 5245 5246 out: 5247 if (map) 5248 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5249 5250 *y420cmdb_map = map; 5251 } 5252 5253 static int add_cea_modes(struct drm_connector *connector, 5254 const struct drm_edid *drm_edid) 5255 { 5256 const struct cea_db *db; 5257 struct cea_db_iter iter; 5258 int modes; 5259 5260 /* CTA VDB block VICs parsed earlier */ 5261 modes = add_cta_vdb_modes(connector); 5262 5263 cea_db_iter_edid_begin(drm_edid, &iter); 5264 cea_db_iter_for_each(db, &iter) { 5265 if (cea_db_is_hdmi_vsdb(db)) { 5266 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5267 cea_db_payload_len(db)); 5268 } else if (cea_db_is_y420vdb(db)) { 5269 const u8 *vdb420 = cea_db_data(db) + 1; 5270 5271 /* Add 4:2:0(only) modes present in EDID */ 5272 modes += do_y420vdb_modes(connector, vdb420, 5273 cea_db_payload_len(db) - 1); 5274 } 5275 } 5276 cea_db_iter_end(&iter); 5277 5278 return modes; 5279 } 5280 5281 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5282 struct drm_display_mode *mode) 5283 { 5284 const struct drm_display_mode *cea_mode; 5285 int clock1, clock2, clock; 5286 u8 vic; 5287 const char *type; 5288 5289 /* 5290 * allow 5kHz clock difference either way to account for 5291 * the 10kHz clock resolution limit of detailed timings. 5292 */ 5293 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5294 if (drm_valid_cea_vic(vic)) { 5295 type = "CEA"; 5296 cea_mode = cea_mode_for_vic(vic); 5297 clock1 = cea_mode->clock; 5298 clock2 = cea_mode_alternate_clock(cea_mode); 5299 } else { 5300 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5301 if (drm_valid_hdmi_vic(vic)) { 5302 type = "HDMI"; 5303 cea_mode = &edid_4k_modes[vic]; 5304 clock1 = cea_mode->clock; 5305 clock2 = hdmi_mode_alternate_clock(cea_mode); 5306 } else { 5307 return; 5308 } 5309 } 5310 5311 /* pick whichever is closest */ 5312 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5313 clock = clock1; 5314 else 5315 clock = clock2; 5316 5317 if (mode->clock == clock) 5318 return; 5319 5320 drm_dbg_kms(connector->dev, 5321 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5322 connector->base.id, connector->name, 5323 type, vic, mode->clock, clock); 5324 mode->clock = clock; 5325 } 5326 5327 static void drm_calculate_luminance_range(struct drm_connector *connector) 5328 { 5329 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5330 struct drm_luminance_range_info *luminance_range = 5331 &connector->display_info.luminance_range; 5332 static const u8 pre_computed_values[] = { 5333 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5334 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5335 }; 5336 u32 max_avg, min_cll, max, min, q, r; 5337 5338 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5339 return; 5340 5341 max_avg = hdr_metadata->max_fall; 5342 min_cll = hdr_metadata->min_cll; 5343 5344 /* 5345 * From the specification (CTA-861-G), for calculating the maximum 5346 * luminance we need to use: 5347 * Luminance = 50*2**(CV/32) 5348 * Where CV is a one-byte value. 5349 * For calculating this expression we may need float point precision; 5350 * to avoid this complexity level, we take advantage that CV is divided 5351 * by a constant. From the Euclids division algorithm, we know that CV 5352 * can be written as: CV = 32*q + r. Next, we replace CV in the 5353 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5354 * need to pre-compute the value of r/32. For pre-computing the values 5355 * We just used the following Ruby line: 5356 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5357 * The results of the above expressions can be verified at 5358 * pre_computed_values. 5359 */ 5360 q = max_avg >> 5; 5361 r = max_avg % 32; 5362 max = (1 << q) * pre_computed_values[r]; 5363 5364 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5365 q = DIV_ROUND_CLOSEST(min_cll, 255); 5366 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5367 5368 luminance_range->min_luminance = min; 5369 luminance_range->max_luminance = max; 5370 } 5371 5372 static uint8_t eotf_supported(const u8 *edid_ext) 5373 { 5374 return edid_ext[2] & 5375 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5376 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5377 BIT(HDMI_EOTF_SMPTE_ST2084) | 5378 BIT(HDMI_EOTF_BT_2100_HLG)); 5379 } 5380 5381 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5382 { 5383 return edid_ext[3] & 5384 BIT(HDMI_STATIC_METADATA_TYPE1); 5385 } 5386 5387 static void 5388 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5389 { 5390 u16 len; 5391 5392 len = cea_db_payload_len(db); 5393 5394 connector->hdr_sink_metadata.hdmi_type1.eotf = 5395 eotf_supported(db); 5396 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5397 hdr_metadata_type(db); 5398 5399 if (len >= 4) 5400 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5401 if (len >= 5) 5402 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5403 if (len >= 6) { 5404 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5405 5406 /* Calculate only when all values are available */ 5407 drm_calculate_luminance_range(connector); 5408 } 5409 } 5410 5411 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5412 static void 5413 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5414 { 5415 u8 len = cea_db_payload_len(db); 5416 5417 if (len >= 6 && (db[6] & (1 << 7))) 5418 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5419 5420 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5421 connector->latency_present[0] = true; 5422 connector->video_latency[0] = db[9]; 5423 connector->audio_latency[0] = db[10]; 5424 } 5425 5426 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5427 connector->latency_present[1] = true; 5428 connector->video_latency[1] = db[11]; 5429 connector->audio_latency[1] = db[12]; 5430 } 5431 5432 drm_dbg_kms(connector->dev, 5433 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5434 connector->base.id, connector->name, 5435 connector->latency_present[0], connector->latency_present[1], 5436 connector->video_latency[0], connector->video_latency[1], 5437 connector->audio_latency[0], connector->audio_latency[1]); 5438 } 5439 5440 static void 5441 monitor_name(const struct detailed_timing *timing, void *data) 5442 { 5443 const char **res = data; 5444 5445 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5446 return; 5447 5448 *res = timing->data.other_data.data.str.str; 5449 } 5450 5451 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5452 { 5453 const char *edid_name = NULL; 5454 int mnl; 5455 5456 if (!drm_edid || !name) 5457 return 0; 5458 5459 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5460 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5461 if (edid_name[mnl] == 0x0a) 5462 break; 5463 5464 name[mnl] = edid_name[mnl]; 5465 } 5466 5467 return mnl; 5468 } 5469 5470 /** 5471 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5472 * @edid: monitor EDID information 5473 * @name: pointer to a character array to hold the name of the monitor 5474 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5475 * 5476 */ 5477 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5478 { 5479 int name_length = 0; 5480 5481 if (bufsize <= 0) 5482 return; 5483 5484 if (edid) { 5485 char buf[13]; 5486 struct drm_edid drm_edid = { 5487 .edid = edid, 5488 .size = edid_size(edid), 5489 }; 5490 5491 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5492 memcpy(name, buf, name_length); 5493 } 5494 5495 name[name_length] = '\0'; 5496 } 5497 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5498 5499 static void clear_eld(struct drm_connector *connector) 5500 { 5501 memset(connector->eld, 0, sizeof(connector->eld)); 5502 5503 connector->latency_present[0] = false; 5504 connector->latency_present[1] = false; 5505 connector->video_latency[0] = 0; 5506 connector->audio_latency[0] = 0; 5507 connector->video_latency[1] = 0; 5508 connector->audio_latency[1] = 0; 5509 } 5510 5511 /* 5512 * drm_edid_to_eld - build ELD from EDID 5513 * @connector: connector corresponding to the HDMI/DP sink 5514 * @drm_edid: EDID to parse 5515 * 5516 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5517 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5518 */ 5519 static void drm_edid_to_eld(struct drm_connector *connector, 5520 const struct drm_edid *drm_edid) 5521 { 5522 const struct drm_display_info *info = &connector->display_info; 5523 const struct cea_db *db; 5524 struct cea_db_iter iter; 5525 uint8_t *eld = connector->eld; 5526 int total_sad_count = 0; 5527 int mnl; 5528 5529 if (!drm_edid) 5530 return; 5531 5532 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5533 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5534 connector->base.id, connector->name, 5535 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5536 5537 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5538 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5539 5540 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5541 5542 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5543 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5544 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5545 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5546 5547 cea_db_iter_edid_begin(drm_edid, &iter); 5548 cea_db_iter_for_each(db, &iter) { 5549 const u8 *data = cea_db_data(db); 5550 int len = cea_db_payload_len(db); 5551 int sad_count; 5552 5553 switch (cea_db_tag(db)) { 5554 case CTA_DB_AUDIO: 5555 /* Audio Data Block, contains SADs */ 5556 sad_count = min(len / 3, 15 - total_sad_count); 5557 if (sad_count >= 1) 5558 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5559 data, sad_count * 3); 5560 total_sad_count += sad_count; 5561 break; 5562 case CTA_DB_SPEAKER: 5563 /* Speaker Allocation Data Block */ 5564 if (len >= 1) 5565 eld[DRM_ELD_SPEAKER] = data[0]; 5566 break; 5567 case CTA_DB_VENDOR: 5568 /* HDMI Vendor-Specific Data Block */ 5569 if (cea_db_is_hdmi_vsdb(db)) 5570 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5571 break; 5572 default: 5573 break; 5574 } 5575 } 5576 cea_db_iter_end(&iter); 5577 5578 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5579 5580 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5581 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5582 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5583 else 5584 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5585 5586 eld[DRM_ELD_BASELINE_ELD_LEN] = 5587 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5588 5589 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5590 connector->base.id, connector->name, 5591 drm_eld_size(eld), total_sad_count); 5592 } 5593 5594 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5595 struct cea_sad **sads) 5596 { 5597 const struct cea_db *db; 5598 struct cea_db_iter iter; 5599 int count = 0; 5600 5601 cea_db_iter_edid_begin(drm_edid, &iter); 5602 cea_db_iter_for_each(db, &iter) { 5603 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5604 int j; 5605 5606 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5607 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5608 if (!*sads) 5609 return -ENOMEM; 5610 for (j = 0; j < count; j++) { 5611 const u8 *sad = &db->data[j * 3]; 5612 5613 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5614 (*sads)[j].channels = sad[0] & 0x7; 5615 (*sads)[j].freq = sad[1] & 0x7F; 5616 (*sads)[j].byte2 = sad[2]; 5617 } 5618 break; 5619 } 5620 } 5621 cea_db_iter_end(&iter); 5622 5623 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5624 5625 return count; 5626 } 5627 5628 /** 5629 * drm_edid_to_sad - extracts SADs from EDID 5630 * @edid: EDID to parse 5631 * @sads: pointer that will be set to the extracted SADs 5632 * 5633 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5634 * 5635 * Note: The returned pointer needs to be freed using kfree(). 5636 * 5637 * Return: The number of found SADs or negative number on error. 5638 */ 5639 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5640 { 5641 struct drm_edid drm_edid; 5642 5643 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5644 } 5645 EXPORT_SYMBOL(drm_edid_to_sad); 5646 5647 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5648 u8 **sadb) 5649 { 5650 const struct cea_db *db; 5651 struct cea_db_iter iter; 5652 int count = 0; 5653 5654 cea_db_iter_edid_begin(drm_edid, &iter); 5655 cea_db_iter_for_each(db, &iter) { 5656 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5657 cea_db_payload_len(db) == 3) { 5658 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5659 GFP_KERNEL); 5660 if (!*sadb) 5661 return -ENOMEM; 5662 count = cea_db_payload_len(db); 5663 break; 5664 } 5665 } 5666 cea_db_iter_end(&iter); 5667 5668 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5669 5670 return count; 5671 } 5672 5673 /** 5674 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5675 * @edid: EDID to parse 5676 * @sadb: pointer to the speaker block 5677 * 5678 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5679 * 5680 * Note: The returned pointer needs to be freed using kfree(). 5681 * 5682 * Return: The number of found Speaker Allocation Blocks or negative number on 5683 * error. 5684 */ 5685 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5686 { 5687 struct drm_edid drm_edid; 5688 5689 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5690 sadb); 5691 } 5692 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5693 5694 /** 5695 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5696 * @connector: connector associated with the HDMI/DP sink 5697 * @mode: the display mode 5698 * 5699 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5700 * the sink doesn't support audio or video. 5701 */ 5702 int drm_av_sync_delay(struct drm_connector *connector, 5703 const struct drm_display_mode *mode) 5704 { 5705 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5706 int a, v; 5707 5708 if (!connector->latency_present[0]) 5709 return 0; 5710 if (!connector->latency_present[1]) 5711 i = 0; 5712 5713 a = connector->audio_latency[i]; 5714 v = connector->video_latency[i]; 5715 5716 /* 5717 * HDMI/DP sink doesn't support audio or video? 5718 */ 5719 if (a == 255 || v == 255) 5720 return 0; 5721 5722 /* 5723 * Convert raw EDID values to millisecond. 5724 * Treat unknown latency as 0ms. 5725 */ 5726 if (a) 5727 a = min(2 * (a - 1), 500); 5728 if (v) 5729 v = min(2 * (v - 1), 500); 5730 5731 return max(v - a, 0); 5732 } 5733 EXPORT_SYMBOL(drm_av_sync_delay); 5734 5735 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5736 { 5737 const struct cea_db *db; 5738 struct cea_db_iter iter; 5739 bool hdmi = false; 5740 5741 /* 5742 * Because HDMI identifier is in Vendor Specific Block, 5743 * search it from all data blocks of CEA extension. 5744 */ 5745 cea_db_iter_edid_begin(drm_edid, &iter); 5746 cea_db_iter_for_each(db, &iter) { 5747 if (cea_db_is_hdmi_vsdb(db)) { 5748 hdmi = true; 5749 break; 5750 } 5751 } 5752 cea_db_iter_end(&iter); 5753 5754 return hdmi; 5755 } 5756 5757 /** 5758 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5759 * @edid: monitor EDID information 5760 * 5761 * Parse the CEA extension according to CEA-861-B. 5762 * 5763 * Drivers that have added the modes parsed from EDID to drm_display_info 5764 * should use &drm_display_info.is_hdmi instead of calling this function. 5765 * 5766 * Return: True if the monitor is HDMI, false if not or unknown. 5767 */ 5768 bool drm_detect_hdmi_monitor(const struct edid *edid) 5769 { 5770 struct drm_edid drm_edid; 5771 5772 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5773 } 5774 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5775 5776 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5777 { 5778 struct drm_edid_iter edid_iter; 5779 const struct cea_db *db; 5780 struct cea_db_iter iter; 5781 const u8 *edid_ext; 5782 bool has_audio = false; 5783 5784 drm_edid_iter_begin(drm_edid, &edid_iter); 5785 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5786 if (edid_ext[0] == CEA_EXT) { 5787 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5788 if (has_audio) 5789 break; 5790 } 5791 } 5792 drm_edid_iter_end(&edid_iter); 5793 5794 if (has_audio) { 5795 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5796 goto end; 5797 } 5798 5799 cea_db_iter_edid_begin(drm_edid, &iter); 5800 cea_db_iter_for_each(db, &iter) { 5801 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5802 const u8 *data = cea_db_data(db); 5803 int i; 5804 5805 for (i = 0; i < cea_db_payload_len(db); i += 3) 5806 DRM_DEBUG_KMS("CEA audio format %d\n", 5807 (data[i] >> 3) & 0xf); 5808 has_audio = true; 5809 break; 5810 } 5811 } 5812 cea_db_iter_end(&iter); 5813 5814 end: 5815 return has_audio; 5816 } 5817 5818 /** 5819 * drm_detect_monitor_audio - check monitor audio capability 5820 * @edid: EDID block to scan 5821 * 5822 * Monitor should have CEA extension block. 5823 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5824 * audio' only. If there is any audio extension block and supported 5825 * audio format, assume at least 'basic audio' support, even if 'basic 5826 * audio' is not defined in EDID. 5827 * 5828 * Return: True if the monitor supports audio, false otherwise. 5829 */ 5830 bool drm_detect_monitor_audio(const struct edid *edid) 5831 { 5832 struct drm_edid drm_edid; 5833 5834 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5835 } 5836 EXPORT_SYMBOL(drm_detect_monitor_audio); 5837 5838 5839 /** 5840 * drm_default_rgb_quant_range - default RGB quantization range 5841 * @mode: display mode 5842 * 5843 * Determine the default RGB quantization range for the mode, 5844 * as specified in CEA-861. 5845 * 5846 * Return: The default RGB quantization range for the mode 5847 */ 5848 enum hdmi_quantization_range 5849 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5850 { 5851 /* All CEA modes other than VIC 1 use limited quantization range. */ 5852 return drm_match_cea_mode(mode) > 1 ? 5853 HDMI_QUANTIZATION_RANGE_LIMITED : 5854 HDMI_QUANTIZATION_RANGE_FULL; 5855 } 5856 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5857 5858 /* CTA-861 Video Data Block (CTA VDB) */ 5859 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5860 { 5861 struct drm_display_info *info = &connector->display_info; 5862 int i, vic_index, len = cea_db_payload_len(db); 5863 const u8 *svds = cea_db_data(db); 5864 u8 *vics; 5865 5866 if (!len) 5867 return; 5868 5869 /* Gracefully handle multiple VDBs, however unlikely that is */ 5870 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5871 if (!vics) 5872 return; 5873 5874 vic_index = info->vics_len; 5875 info->vics_len += len; 5876 info->vics = vics; 5877 5878 for (i = 0; i < len; i++) { 5879 u8 vic = svd_to_vic(svds[i]); 5880 5881 if (!drm_valid_cea_vic(vic)) 5882 vic = 0; 5883 5884 info->vics[vic_index++] = vic; 5885 } 5886 } 5887 5888 /* 5889 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5890 * 5891 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5892 * using the VICs themselves. 5893 */ 5894 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5895 { 5896 struct drm_display_info *info = &connector->display_info; 5897 struct drm_hdmi_info *hdmi = &info->hdmi; 5898 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5899 5900 for (i = 0; i < len; i++) { 5901 u8 vic = info->vics[i]; 5902 5903 if (vic && y420cmdb_map & BIT_ULL(i)) 5904 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5905 } 5906 } 5907 5908 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5909 { 5910 const struct drm_display_info *info = &connector->display_info; 5911 int i; 5912 5913 if (!vic || !info->vics) 5914 return false; 5915 5916 for (i = 0; i < info->vics_len; i++) { 5917 if (info->vics[i] == vic) 5918 return true; 5919 } 5920 5921 return false; 5922 } 5923 5924 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5925 static void parse_cta_y420vdb(struct drm_connector *connector, 5926 const struct cea_db *db) 5927 { 5928 struct drm_display_info *info = &connector->display_info; 5929 struct drm_hdmi_info *hdmi = &info->hdmi; 5930 const u8 *svds = cea_db_data(db) + 1; 5931 int i; 5932 5933 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5934 u8 vic = svd_to_vic(svds[i]); 5935 5936 if (!drm_valid_cea_vic(vic)) 5937 continue; 5938 5939 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5940 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5941 } 5942 } 5943 5944 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5945 { 5946 struct drm_display_info *info = &connector->display_info; 5947 5948 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5949 connector->base.id, connector->name, db[2]); 5950 5951 if (db[2] & EDID_CEA_VCDB_QS) 5952 info->rgb_quant_range_selectable = true; 5953 } 5954 5955 static 5956 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5957 { 5958 switch (max_frl_rate) { 5959 case 1: 5960 *max_lanes = 3; 5961 *max_rate_per_lane = 3; 5962 break; 5963 case 2: 5964 *max_lanes = 3; 5965 *max_rate_per_lane = 6; 5966 break; 5967 case 3: 5968 *max_lanes = 4; 5969 *max_rate_per_lane = 6; 5970 break; 5971 case 4: 5972 *max_lanes = 4; 5973 *max_rate_per_lane = 8; 5974 break; 5975 case 5: 5976 *max_lanes = 4; 5977 *max_rate_per_lane = 10; 5978 break; 5979 case 6: 5980 *max_lanes = 4; 5981 *max_rate_per_lane = 12; 5982 break; 5983 case 0: 5984 default: 5985 *max_lanes = 0; 5986 *max_rate_per_lane = 0; 5987 } 5988 } 5989 5990 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5991 const u8 *db) 5992 { 5993 u8 dc_mask; 5994 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5995 5996 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5997 hdmi->y420_dc_modes = dc_mask; 5998 } 5999 6000 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6001 const u8 *hf_scds) 6002 { 6003 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6004 6005 if (!hdmi_dsc->v_1p2) 6006 return; 6007 6008 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6009 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6010 6011 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6012 hdmi_dsc->bpc_supported = 16; 6013 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6014 hdmi_dsc->bpc_supported = 12; 6015 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6016 hdmi_dsc->bpc_supported = 10; 6017 else 6018 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6019 hdmi_dsc->bpc_supported = 8; 6020 6021 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6022 u8 dsc_max_slices; 6023 u8 dsc_max_frl_rate; 6024 6025 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6026 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6027 &hdmi_dsc->max_frl_rate_per_lane); 6028 6029 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6030 6031 switch (dsc_max_slices) { 6032 case 1: 6033 hdmi_dsc->max_slices = 1; 6034 hdmi_dsc->clk_per_slice = 340; 6035 break; 6036 case 2: 6037 hdmi_dsc->max_slices = 2; 6038 hdmi_dsc->clk_per_slice = 340; 6039 break; 6040 case 3: 6041 hdmi_dsc->max_slices = 4; 6042 hdmi_dsc->clk_per_slice = 340; 6043 break; 6044 case 4: 6045 hdmi_dsc->max_slices = 8; 6046 hdmi_dsc->clk_per_slice = 340; 6047 break; 6048 case 5: 6049 hdmi_dsc->max_slices = 8; 6050 hdmi_dsc->clk_per_slice = 400; 6051 break; 6052 case 6: 6053 hdmi_dsc->max_slices = 12; 6054 hdmi_dsc->clk_per_slice = 400; 6055 break; 6056 case 7: 6057 hdmi_dsc->max_slices = 16; 6058 hdmi_dsc->clk_per_slice = 400; 6059 break; 6060 case 0: 6061 default: 6062 hdmi_dsc->max_slices = 0; 6063 hdmi_dsc->clk_per_slice = 0; 6064 } 6065 } 6066 6067 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6068 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6069 } 6070 6071 /* Sink Capability Data Structure */ 6072 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6073 const u8 *hf_scds) 6074 { 6075 struct drm_display_info *info = &connector->display_info; 6076 struct drm_hdmi_info *hdmi = &info->hdmi; 6077 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6078 int max_tmds_clock = 0; 6079 u8 max_frl_rate = 0; 6080 bool dsc_support = false; 6081 6082 info->has_hdmi_infoframe = true; 6083 6084 if (hf_scds[6] & 0x80) { 6085 hdmi->scdc.supported = true; 6086 if (hf_scds[6] & 0x40) 6087 hdmi->scdc.read_request = true; 6088 } 6089 6090 /* 6091 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6092 * And as per the spec, three factors confirm this: 6093 * * Availability of a HF-VSDB block in EDID (check) 6094 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6095 * * SCDC support available (let's check) 6096 * Lets check it out. 6097 */ 6098 6099 if (hf_scds[5]) { 6100 struct drm_scdc *scdc = &hdmi->scdc; 6101 6102 /* max clock is 5000 KHz times block value */ 6103 max_tmds_clock = hf_scds[5] * 5000; 6104 6105 if (max_tmds_clock > 340000) { 6106 info->max_tmds_clock = max_tmds_clock; 6107 } 6108 6109 if (scdc->supported) { 6110 scdc->scrambling.supported = true; 6111 6112 /* Few sinks support scrambling for clocks < 340M */ 6113 if ((hf_scds[6] & 0x8)) 6114 scdc->scrambling.low_rates = true; 6115 } 6116 } 6117 6118 if (hf_scds[7]) { 6119 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6120 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6121 &hdmi->max_frl_rate_per_lane); 6122 } 6123 6124 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6125 6126 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6127 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6128 dsc_support = true; 6129 } 6130 6131 drm_dbg_kms(connector->dev, 6132 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6133 connector->base.id, connector->name, 6134 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6135 } 6136 6137 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6138 const u8 *hdmi) 6139 { 6140 struct drm_display_info *info = &connector->display_info; 6141 unsigned int dc_bpc = 0; 6142 6143 /* HDMI supports at least 8 bpc */ 6144 info->bpc = 8; 6145 6146 if (cea_db_payload_len(hdmi) < 6) 6147 return; 6148 6149 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6150 dc_bpc = 10; 6151 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6152 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6153 connector->base.id, connector->name); 6154 } 6155 6156 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6157 dc_bpc = 12; 6158 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6159 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6160 connector->base.id, connector->name); 6161 } 6162 6163 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6164 dc_bpc = 16; 6165 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6166 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6167 connector->base.id, connector->name); 6168 } 6169 6170 if (dc_bpc == 0) { 6171 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6172 connector->base.id, connector->name); 6173 return; 6174 } 6175 6176 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6177 connector->base.id, connector->name, dc_bpc); 6178 info->bpc = dc_bpc; 6179 6180 /* YCRCB444 is optional according to spec. */ 6181 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6182 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6183 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6184 connector->base.id, connector->name); 6185 } 6186 6187 /* 6188 * Spec says that if any deep color mode is supported at all, 6189 * then deep color 36 bit must be supported. 6190 */ 6191 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6192 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6193 connector->base.id, connector->name); 6194 } 6195 } 6196 6197 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6198 static void 6199 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6200 { 6201 struct drm_display_info *info = &connector->display_info; 6202 u8 len = cea_db_payload_len(db); 6203 6204 info->is_hdmi = true; 6205 6206 if (len >= 6) 6207 info->dvi_dual = db[6] & 1; 6208 if (len >= 7) 6209 info->max_tmds_clock = db[7] * 5000; 6210 6211 /* 6212 * Try to infer whether the sink supports HDMI infoframes. 6213 * 6214 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6215 * supports infoframes if HDMI_Video_present is set. 6216 */ 6217 if (len >= 8 && db[8] & BIT(5)) 6218 info->has_hdmi_infoframe = true; 6219 6220 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6221 connector->base.id, connector->name, 6222 info->dvi_dual, info->max_tmds_clock); 6223 6224 drm_parse_hdmi_deep_color_info(connector, db); 6225 } 6226 6227 /* 6228 * See EDID extension for head-mounted and specialized monitors, specified at: 6229 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6230 */ 6231 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6232 const u8 *db) 6233 { 6234 struct drm_display_info *info = &connector->display_info; 6235 u8 version = db[4]; 6236 bool desktop_usage = db[5] & BIT(6); 6237 6238 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6239 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6240 info->non_desktop = true; 6241 6242 drm_dbg_kms(connector->dev, 6243 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6244 connector->base.id, connector->name, version, db[5]); 6245 } 6246 6247 static void drm_parse_cea_ext(struct drm_connector *connector, 6248 const struct drm_edid *drm_edid) 6249 { 6250 struct drm_display_info *info = &connector->display_info; 6251 struct drm_edid_iter edid_iter; 6252 const struct cea_db *db; 6253 struct cea_db_iter iter; 6254 const u8 *edid_ext; 6255 u64 y420cmdb_map = 0; 6256 6257 drm_edid_iter_begin(drm_edid, &edid_iter); 6258 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6259 if (edid_ext[0] != CEA_EXT) 6260 continue; 6261 6262 if (!info->cea_rev) 6263 info->cea_rev = edid_ext[1]; 6264 6265 if (info->cea_rev != edid_ext[1]) 6266 drm_dbg_kms(connector->dev, 6267 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6268 connector->base.id, connector->name, 6269 info->cea_rev, edid_ext[1]); 6270 6271 /* The existence of a CTA extension should imply RGB support */ 6272 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6273 if (edid_ext[3] & EDID_CEA_YCRCB444) 6274 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6275 if (edid_ext[3] & EDID_CEA_YCRCB422) 6276 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6277 if (edid_ext[3] & EDID_BASIC_AUDIO) 6278 info->has_audio = true; 6279 6280 } 6281 drm_edid_iter_end(&edid_iter); 6282 6283 cea_db_iter_edid_begin(drm_edid, &iter); 6284 cea_db_iter_for_each(db, &iter) { 6285 /* FIXME: convert parsers to use struct cea_db */ 6286 const u8 *data = (const u8 *)db; 6287 6288 if (cea_db_is_hdmi_vsdb(db)) 6289 drm_parse_hdmi_vsdb_video(connector, data); 6290 else if (cea_db_is_hdmi_forum_vsdb(db) || 6291 cea_db_is_hdmi_forum_scdb(db)) 6292 drm_parse_hdmi_forum_scds(connector, data); 6293 else if (cea_db_is_microsoft_vsdb(db)) 6294 drm_parse_microsoft_vsdb(connector, data); 6295 else if (cea_db_is_y420cmdb(db)) 6296 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6297 else if (cea_db_is_y420vdb(db)) 6298 parse_cta_y420vdb(connector, db); 6299 else if (cea_db_is_vcdb(db)) 6300 drm_parse_vcdb(connector, data); 6301 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6302 drm_parse_hdr_metadata_block(connector, data); 6303 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6304 parse_cta_vdb(connector, db); 6305 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6306 info->has_audio = true; 6307 } 6308 cea_db_iter_end(&iter); 6309 6310 if (y420cmdb_map) 6311 update_cta_y420cmdb(connector, y420cmdb_map); 6312 } 6313 6314 static 6315 void get_monitor_range(const struct detailed_timing *timing, void *c) 6316 { 6317 struct detailed_mode_closure *closure = c; 6318 struct drm_display_info *info = &closure->connector->display_info; 6319 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6320 const struct detailed_non_pixel *data = &timing->data.other_data; 6321 const struct detailed_data_monitor_range *range = &data->data.range; 6322 const struct edid *edid = closure->drm_edid->edid; 6323 6324 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6325 return; 6326 6327 /* 6328 * These limits are used to determine the VRR refresh 6329 * rate range. Only the "range limits only" variant 6330 * of the range descriptor seems to guarantee that 6331 * any and all timings are accepted by the sink, as 6332 * opposed to just timings conforming to the indicated 6333 * formula (GTF/GTF2/CVT). Thus other variants of the 6334 * range descriptor are not accepted here. 6335 */ 6336 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6337 return; 6338 6339 monitor_range->min_vfreq = range->min_vfreq; 6340 monitor_range->max_vfreq = range->max_vfreq; 6341 6342 if (edid->revision >= 4) { 6343 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6344 monitor_range->min_vfreq += 255; 6345 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6346 monitor_range->max_vfreq += 255; 6347 } 6348 } 6349 6350 static void drm_get_monitor_range(struct drm_connector *connector, 6351 const struct drm_edid *drm_edid) 6352 { 6353 const struct drm_display_info *info = &connector->display_info; 6354 struct detailed_mode_closure closure = { 6355 .connector = connector, 6356 .drm_edid = drm_edid, 6357 }; 6358 6359 if (drm_edid->edid->revision < 4) 6360 return; 6361 6362 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6363 return; 6364 6365 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6366 6367 drm_dbg_kms(connector->dev, 6368 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6369 connector->base.id, connector->name, 6370 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6371 } 6372 6373 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6374 const struct displayid_block *block) 6375 { 6376 struct displayid_vesa_vendor_specific_block *vesa = 6377 (struct displayid_vesa_vendor_specific_block *)block; 6378 struct drm_display_info *info = &connector->display_info; 6379 6380 if (block->num_bytes < 3) { 6381 drm_dbg_kms(connector->dev, 6382 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6383 connector->base.id, connector->name, block->num_bytes); 6384 return; 6385 } 6386 6387 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6388 return; 6389 6390 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6391 drm_dbg_kms(connector->dev, 6392 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6393 connector->base.id, connector->name); 6394 return; 6395 } 6396 6397 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6398 default: 6399 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6400 connector->base.id, connector->name); 6401 fallthrough; 6402 case 0: 6403 info->mso_stream_count = 0; 6404 break; 6405 case 1: 6406 info->mso_stream_count = 2; /* 2 or 4 links */ 6407 break; 6408 case 2: 6409 info->mso_stream_count = 4; /* 4 links */ 6410 break; 6411 } 6412 6413 if (!info->mso_stream_count) { 6414 info->mso_pixel_overlap = 0; 6415 return; 6416 } 6417 6418 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6419 if (info->mso_pixel_overlap > 8) { 6420 drm_dbg_kms(connector->dev, 6421 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6422 connector->base.id, connector->name, 6423 info->mso_pixel_overlap); 6424 info->mso_pixel_overlap = 8; 6425 } 6426 6427 drm_dbg_kms(connector->dev, 6428 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6429 connector->base.id, connector->name, 6430 info->mso_stream_count, info->mso_pixel_overlap); 6431 } 6432 6433 static void drm_update_mso(struct drm_connector *connector, 6434 const struct drm_edid *drm_edid) 6435 { 6436 const struct displayid_block *block; 6437 struct displayid_iter iter; 6438 6439 displayid_iter_edid_begin(drm_edid, &iter); 6440 displayid_iter_for_each(block, &iter) { 6441 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6442 drm_parse_vesa_mso_data(connector, block); 6443 } 6444 displayid_iter_end(&iter); 6445 } 6446 6447 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6448 * all of the values which would have been set from EDID 6449 */ 6450 static void drm_reset_display_info(struct drm_connector *connector) 6451 { 6452 struct drm_display_info *info = &connector->display_info; 6453 6454 info->width_mm = 0; 6455 info->height_mm = 0; 6456 6457 info->bpc = 0; 6458 info->color_formats = 0; 6459 info->cea_rev = 0; 6460 info->max_tmds_clock = 0; 6461 info->dvi_dual = false; 6462 info->is_hdmi = false; 6463 info->has_audio = false; 6464 info->has_hdmi_infoframe = false; 6465 info->rgb_quant_range_selectable = false; 6466 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6467 6468 info->edid_hdmi_rgb444_dc_modes = 0; 6469 info->edid_hdmi_ycbcr444_dc_modes = 0; 6470 6471 info->non_desktop = 0; 6472 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6473 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6474 6475 info->mso_stream_count = 0; 6476 info->mso_pixel_overlap = 0; 6477 info->max_dsc_bpp = 0; 6478 6479 kfree(info->vics); 6480 info->vics = NULL; 6481 info->vics_len = 0; 6482 6483 info->quirks = 0; 6484 } 6485 6486 static void update_displayid_info(struct drm_connector *connector, 6487 const struct drm_edid *drm_edid) 6488 { 6489 struct drm_display_info *info = &connector->display_info; 6490 const struct displayid_block *block; 6491 struct displayid_iter iter; 6492 6493 displayid_iter_edid_begin(drm_edid, &iter); 6494 displayid_iter_for_each(block, &iter) { 6495 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6496 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6497 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6498 info->non_desktop = true; 6499 6500 /* 6501 * We're only interested in the base section here, no need to 6502 * iterate further. 6503 */ 6504 break; 6505 } 6506 displayid_iter_end(&iter); 6507 } 6508 6509 static void update_display_info(struct drm_connector *connector, 6510 const struct drm_edid *drm_edid) 6511 { 6512 struct drm_display_info *info = &connector->display_info; 6513 const struct edid *edid; 6514 6515 drm_reset_display_info(connector); 6516 clear_eld(connector); 6517 6518 if (!drm_edid) 6519 return; 6520 6521 edid = drm_edid->edid; 6522 6523 info->quirks = edid_get_quirks(drm_edid); 6524 6525 info->width_mm = edid->width_cm * 10; 6526 info->height_mm = edid->height_cm * 10; 6527 6528 drm_get_monitor_range(connector, drm_edid); 6529 6530 if (edid->revision < 3) 6531 goto out; 6532 6533 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6534 goto out; 6535 6536 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6537 drm_parse_cea_ext(connector, drm_edid); 6538 6539 update_displayid_info(connector, drm_edid); 6540 6541 /* 6542 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6543 * 6544 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6545 * tells us to assume 8 bpc color depth if the EDID doesn't have 6546 * extensions which tell otherwise. 6547 */ 6548 if (info->bpc == 0 && edid->revision == 3 && 6549 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6550 info->bpc = 8; 6551 drm_dbg_kms(connector->dev, 6552 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6553 connector->base.id, connector->name, info->bpc); 6554 } 6555 6556 /* Only defined for 1.4 with digital displays */ 6557 if (edid->revision < 4) 6558 goto out; 6559 6560 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6561 case DRM_EDID_DIGITAL_DEPTH_6: 6562 info->bpc = 6; 6563 break; 6564 case DRM_EDID_DIGITAL_DEPTH_8: 6565 info->bpc = 8; 6566 break; 6567 case DRM_EDID_DIGITAL_DEPTH_10: 6568 info->bpc = 10; 6569 break; 6570 case DRM_EDID_DIGITAL_DEPTH_12: 6571 info->bpc = 12; 6572 break; 6573 case DRM_EDID_DIGITAL_DEPTH_14: 6574 info->bpc = 14; 6575 break; 6576 case DRM_EDID_DIGITAL_DEPTH_16: 6577 info->bpc = 16; 6578 break; 6579 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6580 default: 6581 info->bpc = 0; 6582 break; 6583 } 6584 6585 drm_dbg_kms(connector->dev, 6586 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6587 connector->base.id, connector->name, info->bpc); 6588 6589 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6590 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6591 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6592 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6593 6594 drm_update_mso(connector, drm_edid); 6595 6596 out: 6597 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6598 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6599 connector->base.id, connector->name, 6600 info->non_desktop ? " (redundant quirk)" : ""); 6601 info->non_desktop = true; 6602 } 6603 6604 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6605 info->max_dsc_bpp = 15; 6606 6607 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6608 info->bpc = 6; 6609 6610 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6611 info->bpc = 8; 6612 6613 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6614 info->bpc = 10; 6615 6616 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6617 info->bpc = 12; 6618 6619 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6620 drm_edid_to_eld(connector, drm_edid); 6621 } 6622 6623 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6624 struct displayid_detailed_timings_1 *timings, 6625 bool type_7) 6626 { 6627 struct drm_display_mode *mode; 6628 unsigned pixel_clock = (timings->pixel_clock[0] | 6629 (timings->pixel_clock[1] << 8) | 6630 (timings->pixel_clock[2] << 16)) + 1; 6631 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6632 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6633 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6634 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6635 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6636 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6637 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6638 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6639 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6640 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6641 6642 mode = drm_mode_create(dev); 6643 if (!mode) 6644 return NULL; 6645 6646 /* resolution is kHz for type VII, and 10 kHz for type I */ 6647 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6648 mode->hdisplay = hactive; 6649 mode->hsync_start = mode->hdisplay + hsync; 6650 mode->hsync_end = mode->hsync_start + hsync_width; 6651 mode->htotal = mode->hdisplay + hblank; 6652 6653 mode->vdisplay = vactive; 6654 mode->vsync_start = mode->vdisplay + vsync; 6655 mode->vsync_end = mode->vsync_start + vsync_width; 6656 mode->vtotal = mode->vdisplay + vblank; 6657 6658 mode->flags = 0; 6659 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6660 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6661 mode->type = DRM_MODE_TYPE_DRIVER; 6662 6663 if (timings->flags & 0x80) 6664 mode->type |= DRM_MODE_TYPE_PREFERRED; 6665 drm_mode_set_name(mode); 6666 6667 return mode; 6668 } 6669 6670 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6671 const struct displayid_block *block) 6672 { 6673 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6674 int i; 6675 int num_timings; 6676 struct drm_display_mode *newmode; 6677 int num_modes = 0; 6678 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6679 /* blocks must be multiple of 20 bytes length */ 6680 if (block->num_bytes % 20) 6681 return 0; 6682 6683 num_timings = block->num_bytes / 20; 6684 for (i = 0; i < num_timings; i++) { 6685 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6686 6687 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6688 if (!newmode) 6689 continue; 6690 6691 drm_mode_probed_add(connector, newmode); 6692 num_modes++; 6693 } 6694 return num_modes; 6695 } 6696 6697 static int add_displayid_detailed_modes(struct drm_connector *connector, 6698 const struct drm_edid *drm_edid) 6699 { 6700 const struct displayid_block *block; 6701 struct displayid_iter iter; 6702 int num_modes = 0; 6703 6704 displayid_iter_edid_begin(drm_edid, &iter); 6705 displayid_iter_for_each(block, &iter) { 6706 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6707 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6708 num_modes += add_displayid_detailed_1_modes(connector, block); 6709 } 6710 displayid_iter_end(&iter); 6711 6712 return num_modes; 6713 } 6714 6715 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6716 const struct drm_edid *drm_edid) 6717 { 6718 const struct drm_display_info *info = &connector->display_info; 6719 int num_modes = 0; 6720 6721 if (!drm_edid) 6722 return 0; 6723 6724 /* 6725 * EDID spec says modes should be preferred in this order: 6726 * - preferred detailed mode 6727 * - other detailed modes from base block 6728 * - detailed modes from extension blocks 6729 * - CVT 3-byte code modes 6730 * - standard timing codes 6731 * - established timing codes 6732 * - modes inferred from GTF or CVT range information 6733 * 6734 * We get this pretty much right. 6735 * 6736 * XXX order for additional mode types in extension blocks? 6737 */ 6738 num_modes += add_detailed_modes(connector, drm_edid); 6739 num_modes += add_cvt_modes(connector, drm_edid); 6740 num_modes += add_standard_modes(connector, drm_edid); 6741 num_modes += add_established_modes(connector, drm_edid); 6742 num_modes += add_cea_modes(connector, drm_edid); 6743 num_modes += add_alternate_cea_modes(connector, drm_edid); 6744 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6745 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6746 num_modes += add_inferred_modes(connector, drm_edid); 6747 6748 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6749 edid_fixup_preferred(connector); 6750 6751 return num_modes; 6752 } 6753 6754 static void _drm_update_tile_info(struct drm_connector *connector, 6755 const struct drm_edid *drm_edid); 6756 6757 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6758 const struct drm_edid *drm_edid) 6759 { 6760 struct drm_device *dev = connector->dev; 6761 int ret; 6762 6763 if (connector->edid_blob_ptr) { 6764 const struct edid *old_edid = connector->edid_blob_ptr->data; 6765 6766 if (old_edid) { 6767 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6768 connector->epoch_counter++; 6769 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6770 connector->base.id, connector->name, 6771 connector->epoch_counter); 6772 } 6773 } 6774 } 6775 6776 ret = drm_property_replace_global_blob(dev, 6777 &connector->edid_blob_ptr, 6778 drm_edid ? drm_edid->size : 0, 6779 drm_edid ? drm_edid->edid : NULL, 6780 &connector->base, 6781 dev->mode_config.edid_property); 6782 if (ret) { 6783 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6784 connector->base.id, connector->name, ret); 6785 goto out; 6786 } 6787 6788 ret = drm_object_property_set_value(&connector->base, 6789 dev->mode_config.non_desktop_property, 6790 connector->display_info.non_desktop); 6791 if (ret) { 6792 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6793 connector->base.id, connector->name, ret); 6794 goto out; 6795 } 6796 6797 ret = drm_connector_set_tile_property(connector); 6798 if (ret) { 6799 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6800 connector->base.id, connector->name, ret); 6801 goto out; 6802 } 6803 6804 out: 6805 return ret; 6806 } 6807 6808 /** 6809 * drm_edid_connector_update - Update connector information from EDID 6810 * @connector: Connector 6811 * @drm_edid: EDID 6812 * 6813 * Update the connector display info, ELD, HDR metadata, relevant properties, 6814 * etc. from the passed in EDID. 6815 * 6816 * If EDID is NULL, reset the information. 6817 * 6818 * Must be called before calling drm_edid_connector_add_modes(). 6819 * 6820 * Return: 0 on success, negative error on errors. 6821 */ 6822 int drm_edid_connector_update(struct drm_connector *connector, 6823 const struct drm_edid *drm_edid) 6824 { 6825 update_display_info(connector, drm_edid); 6826 6827 _drm_update_tile_info(connector, drm_edid); 6828 6829 return _drm_edid_connector_property_update(connector, drm_edid); 6830 } 6831 EXPORT_SYMBOL(drm_edid_connector_update); 6832 6833 /** 6834 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6835 * @connector: Connector 6836 * 6837 * Add the modes from the previously updated EDID property to the connector 6838 * probed modes list. 6839 * 6840 * drm_edid_connector_update() must have been called before this to update the 6841 * EDID property. 6842 * 6843 * Return: The number of modes added, or 0 if we couldn't find any. 6844 */ 6845 int drm_edid_connector_add_modes(struct drm_connector *connector) 6846 { 6847 const struct drm_edid *drm_edid = NULL; 6848 int count; 6849 6850 if (connector->edid_blob_ptr) 6851 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6852 connector->edid_blob_ptr->length); 6853 6854 count = _drm_edid_connector_add_modes(connector, drm_edid); 6855 6856 drm_edid_free(drm_edid); 6857 6858 return count; 6859 } 6860 EXPORT_SYMBOL(drm_edid_connector_add_modes); 6861 6862 /** 6863 * drm_connector_update_edid_property - update the edid property of a connector 6864 * @connector: drm connector 6865 * @edid: new value of the edid property 6866 * 6867 * This function creates a new blob modeset object and assigns its id to the 6868 * connector's edid property. 6869 * Since we also parse tile information from EDID's displayID block, we also 6870 * set the connector's tile property here. See drm_connector_set_tile_property() 6871 * for more details. 6872 * 6873 * This function is deprecated. Use drm_edid_connector_update() instead. 6874 * 6875 * Returns: 6876 * Zero on success, negative errno on failure. 6877 */ 6878 int drm_connector_update_edid_property(struct drm_connector *connector, 6879 const struct edid *edid) 6880 { 6881 struct drm_edid drm_edid; 6882 6883 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6884 } 6885 EXPORT_SYMBOL(drm_connector_update_edid_property); 6886 6887 /** 6888 * drm_add_edid_modes - add modes from EDID data, if available 6889 * @connector: connector we're probing 6890 * @edid: EDID data 6891 * 6892 * Add the specified modes to the connector's mode list. Also fills out the 6893 * &drm_display_info structure and ELD in @connector with any information which 6894 * can be derived from the edid. 6895 * 6896 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6897 * 6898 * Return: The number of modes added or 0 if we couldn't find any. 6899 */ 6900 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6901 { 6902 struct drm_edid _drm_edid; 6903 const struct drm_edid *drm_edid; 6904 6905 if (edid && !drm_edid_is_valid(edid)) { 6906 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6907 connector->base.id, connector->name); 6908 edid = NULL; 6909 } 6910 6911 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6912 6913 update_display_info(connector, drm_edid); 6914 6915 return _drm_edid_connector_add_modes(connector, drm_edid); 6916 } 6917 EXPORT_SYMBOL(drm_add_edid_modes); 6918 6919 /** 6920 * drm_add_modes_noedid - add modes for the connectors without EDID 6921 * @connector: connector we're probing 6922 * @hdisplay: the horizontal display limit 6923 * @vdisplay: the vertical display limit 6924 * 6925 * Add the specified modes to the connector's mode list. Only when the 6926 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6927 * 6928 * Return: The number of modes added or 0 if we couldn't find any. 6929 */ 6930 int drm_add_modes_noedid(struct drm_connector *connector, 6931 int hdisplay, int vdisplay) 6932 { 6933 int i, count, num_modes = 0; 6934 struct drm_display_mode *mode; 6935 struct drm_device *dev = connector->dev; 6936 6937 count = ARRAY_SIZE(drm_dmt_modes); 6938 if (hdisplay < 0) 6939 hdisplay = 0; 6940 if (vdisplay < 0) 6941 vdisplay = 0; 6942 6943 for (i = 0; i < count; i++) { 6944 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6945 6946 if (hdisplay && vdisplay) { 6947 /* 6948 * Only when two are valid, they will be used to check 6949 * whether the mode should be added to the mode list of 6950 * the connector. 6951 */ 6952 if (ptr->hdisplay > hdisplay || 6953 ptr->vdisplay > vdisplay) 6954 continue; 6955 } 6956 if (drm_mode_vrefresh(ptr) > 61) 6957 continue; 6958 mode = drm_mode_duplicate(dev, ptr); 6959 if (mode) { 6960 drm_mode_probed_add(connector, mode); 6961 num_modes++; 6962 } 6963 } 6964 return num_modes; 6965 } 6966 EXPORT_SYMBOL(drm_add_modes_noedid); 6967 6968 /** 6969 * drm_set_preferred_mode - Sets the preferred mode of a connector 6970 * @connector: connector whose mode list should be processed 6971 * @hpref: horizontal resolution of preferred mode 6972 * @vpref: vertical resolution of preferred mode 6973 * 6974 * Marks a mode as preferred if it matches the resolution specified by @hpref 6975 * and @vpref. 6976 */ 6977 void drm_set_preferred_mode(struct drm_connector *connector, 6978 int hpref, int vpref) 6979 { 6980 struct drm_display_mode *mode; 6981 6982 list_for_each_entry(mode, &connector->probed_modes, head) { 6983 if (mode->hdisplay == hpref && 6984 mode->vdisplay == vpref) 6985 mode->type |= DRM_MODE_TYPE_PREFERRED; 6986 } 6987 } 6988 EXPORT_SYMBOL(drm_set_preferred_mode); 6989 6990 static bool is_hdmi2_sink(const struct drm_connector *connector) 6991 { 6992 /* 6993 * FIXME: sil-sii8620 doesn't have a connector around when 6994 * we need one, so we have to be prepared for a NULL connector. 6995 */ 6996 if (!connector) 6997 return true; 6998 6999 return connector->display_info.hdmi.scdc.supported || 7000 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7001 } 7002 7003 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7004 const struct drm_display_mode *mode) 7005 { 7006 bool has_hdmi_infoframe = connector ? 7007 connector->display_info.has_hdmi_infoframe : false; 7008 7009 if (!has_hdmi_infoframe) 7010 return 0; 7011 7012 /* No HDMI VIC when signalling 3D video format */ 7013 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7014 return 0; 7015 7016 return drm_match_hdmi_mode(mode); 7017 } 7018 7019 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7020 const struct drm_display_mode *mode) 7021 { 7022 /* 7023 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7024 * we should send its VIC in vendor infoframes, else send the 7025 * VIC in AVI infoframes. Lets check if this mode is present in 7026 * HDMI 1.4b 4K modes 7027 */ 7028 if (drm_mode_hdmi_vic(connector, mode)) 7029 return 0; 7030 7031 return drm_match_cea_mode(mode); 7032 } 7033 7034 /* 7035 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7036 * conform to HDMI 1.4. 7037 * 7038 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7039 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7040 * 7041 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7042 * version. 7043 */ 7044 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7045 { 7046 if (!is_hdmi2_sink(connector) && vic > 64 && 7047 !cta_vdb_has_vic(connector, vic)) 7048 return 0; 7049 7050 return vic; 7051 } 7052 7053 /** 7054 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7055 * data from a DRM display mode 7056 * @frame: HDMI AVI infoframe 7057 * @connector: the connector 7058 * @mode: DRM display mode 7059 * 7060 * Return: 0 on success or a negative error code on failure. 7061 */ 7062 int 7063 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7064 const struct drm_connector *connector, 7065 const struct drm_display_mode *mode) 7066 { 7067 enum hdmi_picture_aspect picture_aspect; 7068 u8 vic, hdmi_vic; 7069 7070 if (!frame || !mode) 7071 return -EINVAL; 7072 7073 hdmi_avi_infoframe_init(frame); 7074 7075 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7076 frame->pixel_repeat = 1; 7077 7078 vic = drm_mode_cea_vic(connector, mode); 7079 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7080 7081 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7082 7083 /* 7084 * As some drivers don't support atomic, we can't use connector state. 7085 * So just initialize the frame with default values, just the same way 7086 * as it's done with other properties here. 7087 */ 7088 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7089 frame->itc = 0; 7090 7091 /* 7092 * Populate picture aspect ratio from either 7093 * user input (if specified) or from the CEA/HDMI mode lists. 7094 */ 7095 picture_aspect = mode->picture_aspect_ratio; 7096 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7097 if (vic) 7098 picture_aspect = drm_get_cea_aspect_ratio(vic); 7099 else if (hdmi_vic) 7100 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7101 } 7102 7103 /* 7104 * The infoframe can't convey anything but none, 4:3 7105 * and 16:9, so if the user has asked for anything else 7106 * we can only satisfy it by specifying the right VIC. 7107 */ 7108 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7109 if (vic) { 7110 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7111 return -EINVAL; 7112 } else if (hdmi_vic) { 7113 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7114 return -EINVAL; 7115 } else { 7116 return -EINVAL; 7117 } 7118 7119 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7120 } 7121 7122 frame->video_code = vic_for_avi_infoframe(connector, vic); 7123 frame->picture_aspect = picture_aspect; 7124 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7125 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7126 7127 return 0; 7128 } 7129 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7130 7131 /** 7132 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7133 * quantization range information 7134 * @frame: HDMI AVI infoframe 7135 * @connector: the connector 7136 * @mode: DRM display mode 7137 * @rgb_quant_range: RGB quantization range (Q) 7138 */ 7139 void 7140 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7141 const struct drm_connector *connector, 7142 const struct drm_display_mode *mode, 7143 enum hdmi_quantization_range rgb_quant_range) 7144 { 7145 const struct drm_display_info *info = &connector->display_info; 7146 7147 /* 7148 * CEA-861: 7149 * "A Source shall not send a non-zero Q value that does not correspond 7150 * to the default RGB Quantization Range for the transmitted Picture 7151 * unless the Sink indicates support for the Q bit in a Video 7152 * Capabilities Data Block." 7153 * 7154 * HDMI 2.0 recommends sending non-zero Q when it does match the 7155 * default RGB quantization range for the mode, even when QS=0. 7156 */ 7157 if (info->rgb_quant_range_selectable || 7158 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7159 frame->quantization_range = rgb_quant_range; 7160 else 7161 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7162 7163 /* 7164 * CEA-861-F: 7165 * "When transmitting any RGB colorimetry, the Source should set the 7166 * YQ-field to match the RGB Quantization Range being transmitted 7167 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7168 * set YQ=1) and the Sink shall ignore the YQ-field." 7169 * 7170 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7171 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7172 * good way to tell which version of CEA-861 the sink supports, so 7173 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7174 * on CEA-861-F. 7175 */ 7176 if (!is_hdmi2_sink(connector) || 7177 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7178 frame->ycc_quantization_range = 7179 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7180 else 7181 frame->ycc_quantization_range = 7182 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7183 } 7184 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7185 7186 static enum hdmi_3d_structure 7187 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7188 { 7189 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7190 7191 switch (layout) { 7192 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7193 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7194 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7195 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7196 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7197 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7198 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7199 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7200 case DRM_MODE_FLAG_3D_L_DEPTH: 7201 return HDMI_3D_STRUCTURE_L_DEPTH; 7202 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7203 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7204 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7205 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7206 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7207 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7208 default: 7209 return HDMI_3D_STRUCTURE_INVALID; 7210 } 7211 } 7212 7213 /** 7214 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7215 * data from a DRM display mode 7216 * @frame: HDMI vendor infoframe 7217 * @connector: the connector 7218 * @mode: DRM display mode 7219 * 7220 * Note that there's is a need to send HDMI vendor infoframes only when using a 7221 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7222 * function will return -EINVAL, error that can be safely ignored. 7223 * 7224 * Return: 0 on success or a negative error code on failure. 7225 */ 7226 int 7227 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7228 const struct drm_connector *connector, 7229 const struct drm_display_mode *mode) 7230 { 7231 /* 7232 * FIXME: sil-sii8620 doesn't have a connector around when 7233 * we need one, so we have to be prepared for a NULL connector. 7234 */ 7235 bool has_hdmi_infoframe = connector ? 7236 connector->display_info.has_hdmi_infoframe : false; 7237 int err; 7238 7239 if (!frame || !mode) 7240 return -EINVAL; 7241 7242 if (!has_hdmi_infoframe) 7243 return -EINVAL; 7244 7245 err = hdmi_vendor_infoframe_init(frame); 7246 if (err < 0) 7247 return err; 7248 7249 /* 7250 * Even if it's not absolutely necessary to send the infoframe 7251 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7252 * know that the sink can handle it. This is based on a 7253 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7254 * have trouble realizing that they should switch from 3D to 2D 7255 * mode if the source simply stops sending the infoframe when 7256 * it wants to switch from 3D to 2D. 7257 */ 7258 frame->vic = drm_mode_hdmi_vic(connector, mode); 7259 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7260 7261 return 0; 7262 } 7263 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7264 7265 static void drm_parse_tiled_block(struct drm_connector *connector, 7266 const struct displayid_block *block) 7267 { 7268 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7269 u16 w, h; 7270 u8 tile_v_loc, tile_h_loc; 7271 u8 num_v_tile, num_h_tile; 7272 struct drm_tile_group *tg; 7273 7274 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7275 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7276 7277 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7278 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7279 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7280 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7281 7282 connector->has_tile = true; 7283 if (tile->tile_cap & 0x80) 7284 connector->tile_is_single_monitor = true; 7285 7286 connector->num_h_tile = num_h_tile + 1; 7287 connector->num_v_tile = num_v_tile + 1; 7288 connector->tile_h_loc = tile_h_loc; 7289 connector->tile_v_loc = tile_v_loc; 7290 connector->tile_h_size = w + 1; 7291 connector->tile_v_size = h + 1; 7292 7293 drm_dbg_kms(connector->dev, 7294 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7295 connector->base.id, connector->name, 7296 tile->tile_cap, 7297 connector->tile_h_size, connector->tile_v_size, 7298 connector->num_h_tile, connector->num_v_tile, 7299 connector->tile_h_loc, connector->tile_v_loc, 7300 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7301 7302 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7303 if (!tg) 7304 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7305 if (!tg) 7306 return; 7307 7308 if (connector->tile_group != tg) { 7309 /* if we haven't got a pointer, 7310 take the reference, drop ref to old tile group */ 7311 if (connector->tile_group) 7312 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7313 connector->tile_group = tg; 7314 } else { 7315 /* if same tile group, then release the ref we just took. */ 7316 drm_mode_put_tile_group(connector->dev, tg); 7317 } 7318 } 7319 7320 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7321 const struct displayid_block *block) 7322 { 7323 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7324 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7325 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7326 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7327 } 7328 7329 static void _drm_update_tile_info(struct drm_connector *connector, 7330 const struct drm_edid *drm_edid) 7331 { 7332 const struct displayid_block *block; 7333 struct displayid_iter iter; 7334 7335 connector->has_tile = false; 7336 7337 displayid_iter_edid_begin(drm_edid, &iter); 7338 displayid_iter_for_each(block, &iter) { 7339 if (displayid_is_tiled_block(&iter, block)) 7340 drm_parse_tiled_block(connector, block); 7341 } 7342 displayid_iter_end(&iter); 7343 7344 if (!connector->has_tile && connector->tile_group) { 7345 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7346 connector->tile_group = NULL; 7347 } 7348 } 7349