1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static int validate_displayid(u8 *displayid, int length, int idx); 1588 1589 static int drm_edid_block_checksum(const u8 *raw_edid) 1590 { 1591 int i; 1592 u8 csum = 0, crc = 0; 1593 1594 for (i = 0; i < EDID_LENGTH - 1; i++) 1595 csum += raw_edid[i]; 1596 1597 crc = 0x100 - csum; 1598 1599 return crc; 1600 } 1601 1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1603 { 1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1605 return true; 1606 else 1607 return false; 1608 } 1609 1610 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1611 { 1612 if (memchr_inv(in_edid, 0, length)) 1613 return false; 1614 1615 return true; 1616 } 1617 1618 /** 1619 * drm_edid_are_equal - compare two edid blobs. 1620 * @edid1: pointer to first blob 1621 * @edid2: pointer to second blob 1622 * This helper can be used during probing to determine if 1623 * edid had changed. 1624 */ 1625 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1626 { 1627 int edid1_len, edid2_len; 1628 bool edid1_present = edid1 != NULL; 1629 bool edid2_present = edid2 != NULL; 1630 1631 if (edid1_present != edid2_present) 1632 return false; 1633 1634 if (edid1) { 1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1637 1638 if (edid1_len != edid2_len) 1639 return false; 1640 1641 if (memcmp(edid1, edid2, edid1_len)) 1642 return false; 1643 } 1644 1645 return true; 1646 } 1647 EXPORT_SYMBOL(drm_edid_are_equal); 1648 1649 /** 1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1651 * @raw_edid: pointer to raw EDID block 1652 * @block: type of block to validate (0 for base, extension otherwise) 1653 * @print_bad_edid: if true, dump bad EDID blocks to the console 1654 * @edid_corrupt: if true, the header or checksum is invalid 1655 * 1656 * Validate a base or extension EDID block and optionally dump bad blocks to 1657 * the console. 1658 * 1659 * Return: True if the block is valid, false otherwise. 1660 */ 1661 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1662 bool *edid_corrupt) 1663 { 1664 u8 csum; 1665 struct edid *edid = (struct edid *)raw_edid; 1666 1667 if (WARN_ON(!raw_edid)) 1668 return false; 1669 1670 if (edid_fixup > 8 || edid_fixup < 0) 1671 edid_fixup = 6; 1672 1673 if (block == 0) { 1674 int score = drm_edid_header_is_valid(raw_edid); 1675 1676 if (score == 8) { 1677 if (edid_corrupt) 1678 *edid_corrupt = false; 1679 } else if (score >= edid_fixup) { 1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1681 * The corrupt flag needs to be set here otherwise, the 1682 * fix-up code here will correct the problem, the 1683 * checksum is correct and the test fails 1684 */ 1685 if (edid_corrupt) 1686 *edid_corrupt = true; 1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1688 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1689 } else { 1690 if (edid_corrupt) 1691 *edid_corrupt = true; 1692 goto bad; 1693 } 1694 } 1695 1696 csum = drm_edid_block_checksum(raw_edid); 1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1698 if (edid_corrupt) 1699 *edid_corrupt = true; 1700 1701 /* allow CEA to slide through, switches mangle this */ 1702 if (raw_edid[0] == CEA_EXT) { 1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1705 } else { 1706 if (print_bad_edid) 1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1708 1709 goto bad; 1710 } 1711 } 1712 1713 /* per-block-type checks */ 1714 switch (raw_edid[0]) { 1715 case 0: /* base */ 1716 if (edid->version != 1) { 1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1718 goto bad; 1719 } 1720 1721 if (edid->revision > 4) 1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1723 break; 1724 1725 default: 1726 break; 1727 } 1728 1729 return true; 1730 1731 bad: 1732 if (print_bad_edid) { 1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1734 pr_notice("EDID block is all zeroes\n"); 1735 } else { 1736 pr_notice("Raw EDID:\n"); 1737 print_hex_dump(KERN_NOTICE, 1738 " \t", DUMP_PREFIX_NONE, 16, 1, 1739 raw_edid, EDID_LENGTH, false); 1740 } 1741 } 1742 return false; 1743 } 1744 EXPORT_SYMBOL(drm_edid_block_valid); 1745 1746 /** 1747 * drm_edid_is_valid - sanity check EDID data 1748 * @edid: EDID data 1749 * 1750 * Sanity-check an entire EDID record (including extensions) 1751 * 1752 * Return: True if the EDID data is valid, false otherwise. 1753 */ 1754 bool drm_edid_is_valid(struct edid *edid) 1755 { 1756 int i; 1757 u8 *raw = (u8 *)edid; 1758 1759 if (!edid) 1760 return false; 1761 1762 for (i = 0; i <= edid->extensions; i++) 1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1764 return false; 1765 1766 return true; 1767 } 1768 EXPORT_SYMBOL(drm_edid_is_valid); 1769 1770 #define DDC_SEGMENT_ADDR 0x30 1771 /** 1772 * drm_do_probe_ddc_edid() - get EDID information via I2C 1773 * @data: I2C device adapter 1774 * @buf: EDID data buffer to be filled 1775 * @block: 128 byte EDID block to start fetching from 1776 * @len: EDID data buffer length to fetch 1777 * 1778 * Try to fetch EDID information by calling I2C driver functions. 1779 * 1780 * Return: 0 on success or -1 on failure. 1781 */ 1782 static int 1783 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1784 { 1785 struct i2c_adapter *adapter = data; 1786 unsigned char start = block * EDID_LENGTH; 1787 unsigned char segment = block >> 1; 1788 unsigned char xfers = segment ? 3 : 2; 1789 int ret, retries = 5; 1790 1791 /* 1792 * The core I2C driver will automatically retry the transfer if the 1793 * adapter reports EAGAIN. However, we find that bit-banging transfers 1794 * are susceptible to errors under a heavily loaded machine and 1795 * generate spurious NAKs and timeouts. Retrying the transfer 1796 * of the individual block a few times seems to overcome this. 1797 */ 1798 do { 1799 struct i2c_msg msgs[] = { 1800 { 1801 .addr = DDC_SEGMENT_ADDR, 1802 .flags = 0, 1803 .len = 1, 1804 .buf = &segment, 1805 }, { 1806 .addr = DDC_ADDR, 1807 .flags = 0, 1808 .len = 1, 1809 .buf = &start, 1810 }, { 1811 .addr = DDC_ADDR, 1812 .flags = I2C_M_RD, 1813 .len = len, 1814 .buf = buf, 1815 } 1816 }; 1817 1818 /* 1819 * Avoid sending the segment addr to not upset non-compliant 1820 * DDC monitors. 1821 */ 1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1823 1824 if (ret == -ENXIO) { 1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1826 adapter->name); 1827 break; 1828 } 1829 } while (ret != xfers && --retries); 1830 1831 return ret == xfers ? 0 : -1; 1832 } 1833 1834 static void connector_bad_edid(struct drm_connector *connector, 1835 u8 *edid, int num_blocks) 1836 { 1837 int i; 1838 u8 num_of_ext = edid[0x7e]; 1839 1840 /* Calculate real checksum for the last edid extension block data */ 1841 connector->real_edid_checksum = 1842 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1843 1844 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1845 return; 1846 1847 drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name); 1848 for (i = 0; i < num_blocks; i++) { 1849 u8 *block = edid + i * EDID_LENGTH; 1850 char prefix[20]; 1851 1852 if (drm_edid_is_zero(block, EDID_LENGTH)) 1853 sprintf(prefix, "\t[%02x] ZERO ", i); 1854 else if (!drm_edid_block_valid(block, i, false, NULL)) 1855 sprintf(prefix, "\t[%02x] BAD ", i); 1856 else 1857 sprintf(prefix, "\t[%02x] GOOD ", i); 1858 1859 print_hex_dump(KERN_WARNING, 1860 prefix, DUMP_PREFIX_NONE, 16, 1, 1861 block, EDID_LENGTH, false); 1862 } 1863 } 1864 1865 /* Get override or firmware EDID */ 1866 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1867 { 1868 struct edid *override = NULL; 1869 1870 if (connector->override_edid) 1871 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1872 1873 if (!override) 1874 override = drm_load_edid_firmware(connector); 1875 1876 return IS_ERR(override) ? NULL : override; 1877 } 1878 1879 /** 1880 * drm_add_override_edid_modes - add modes from override/firmware EDID 1881 * @connector: connector we're probing 1882 * 1883 * Add modes from the override/firmware EDID, if available. Only to be used from 1884 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1885 * failed during drm_get_edid() and caused the override/firmware EDID to be 1886 * skipped. 1887 * 1888 * Return: The number of modes added or 0 if we couldn't find any. 1889 */ 1890 int drm_add_override_edid_modes(struct drm_connector *connector) 1891 { 1892 struct edid *override; 1893 int num_modes = 0; 1894 1895 override = drm_get_override_edid(connector); 1896 if (override) { 1897 drm_connector_update_edid_property(connector, override); 1898 num_modes = drm_add_edid_modes(connector, override); 1899 kfree(override); 1900 1901 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1902 connector->base.id, connector->name, num_modes); 1903 } 1904 1905 return num_modes; 1906 } 1907 EXPORT_SYMBOL(drm_add_override_edid_modes); 1908 1909 /** 1910 * drm_do_get_edid - get EDID data using a custom EDID block read function 1911 * @connector: connector we're probing 1912 * @get_edid_block: EDID block read function 1913 * @data: private data passed to the block read function 1914 * 1915 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1916 * exposes a different interface to read EDID blocks this function can be used 1917 * to get EDID data using a custom block read function. 1918 * 1919 * As in the general case the DDC bus is accessible by the kernel at the I2C 1920 * level, drivers must make all reasonable efforts to expose it as an I2C 1921 * adapter and use drm_get_edid() instead of abusing this function. 1922 * 1923 * The EDID may be overridden using debugfs override_edid or firmare EDID 1924 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1925 * order. Having either of them bypasses actual EDID reads. 1926 * 1927 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1928 */ 1929 struct edid *drm_do_get_edid(struct drm_connector *connector, 1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1931 size_t len), 1932 void *data) 1933 { 1934 int i, j = 0, valid_extensions = 0; 1935 u8 *edid, *new; 1936 struct edid *override; 1937 1938 override = drm_get_override_edid(connector); 1939 if (override) 1940 return override; 1941 1942 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1943 return NULL; 1944 1945 /* base block fetch */ 1946 for (i = 0; i < 4; i++) { 1947 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1948 goto out; 1949 if (drm_edid_block_valid(edid, 0, false, 1950 &connector->edid_corrupt)) 1951 break; 1952 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1953 connector->null_edid_counter++; 1954 goto carp; 1955 } 1956 } 1957 if (i == 4) 1958 goto carp; 1959 1960 /* if there's no extensions, we're done */ 1961 valid_extensions = edid[0x7e]; 1962 if (valid_extensions == 0) 1963 return (struct edid *)edid; 1964 1965 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1966 if (!new) 1967 goto out; 1968 edid = new; 1969 1970 for (j = 1; j <= edid[0x7e]; j++) { 1971 u8 *block = edid + j * EDID_LENGTH; 1972 1973 for (i = 0; i < 4; i++) { 1974 if (get_edid_block(data, block, j, EDID_LENGTH)) 1975 goto out; 1976 if (drm_edid_block_valid(block, j, false, NULL)) 1977 break; 1978 } 1979 1980 if (i == 4) 1981 valid_extensions--; 1982 } 1983 1984 if (valid_extensions != edid[0x7e]) { 1985 u8 *base; 1986 1987 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1988 1989 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1990 edid[0x7e] = valid_extensions; 1991 1992 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1993 GFP_KERNEL); 1994 if (!new) 1995 goto out; 1996 1997 base = new; 1998 for (i = 0; i <= edid[0x7e]; i++) { 1999 u8 *block = edid + i * EDID_LENGTH; 2000 2001 if (!drm_edid_block_valid(block, i, false, NULL)) 2002 continue; 2003 2004 memcpy(base, block, EDID_LENGTH); 2005 base += EDID_LENGTH; 2006 } 2007 2008 kfree(edid); 2009 edid = new; 2010 } 2011 2012 return (struct edid *)edid; 2013 2014 carp: 2015 connector_bad_edid(connector, edid, 1); 2016 out: 2017 kfree(edid); 2018 return NULL; 2019 } 2020 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2021 2022 /** 2023 * drm_probe_ddc() - probe DDC presence 2024 * @adapter: I2C adapter to probe 2025 * 2026 * Return: True on success, false on failure. 2027 */ 2028 bool 2029 drm_probe_ddc(struct i2c_adapter *adapter) 2030 { 2031 unsigned char out; 2032 2033 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2034 } 2035 EXPORT_SYMBOL(drm_probe_ddc); 2036 2037 /** 2038 * drm_get_edid - get EDID data, if available 2039 * @connector: connector we're probing 2040 * @adapter: I2C adapter to use for DDC 2041 * 2042 * Poke the given I2C channel to grab EDID data if possible. If found, 2043 * attach it to the connector. 2044 * 2045 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2046 */ 2047 struct edid *drm_get_edid(struct drm_connector *connector, 2048 struct i2c_adapter *adapter) 2049 { 2050 struct edid *edid; 2051 2052 if (connector->force == DRM_FORCE_OFF) 2053 return NULL; 2054 2055 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2056 return NULL; 2057 2058 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2059 drm_connector_update_edid_property(connector, edid); 2060 return edid; 2061 } 2062 EXPORT_SYMBOL(drm_get_edid); 2063 2064 /** 2065 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2066 * @connector: connector we're probing 2067 * @adapter: I2C adapter to use for DDC 2068 * 2069 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2070 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2071 * switch DDC to the GPU which is retrieving EDID. 2072 * 2073 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2074 */ 2075 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2076 struct i2c_adapter *adapter) 2077 { 2078 struct pci_dev *pdev = connector->dev->pdev; 2079 struct edid *edid; 2080 2081 vga_switcheroo_lock_ddc(pdev); 2082 edid = drm_get_edid(connector, adapter); 2083 vga_switcheroo_unlock_ddc(pdev); 2084 2085 return edid; 2086 } 2087 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2088 2089 /** 2090 * drm_edid_duplicate - duplicate an EDID and the extensions 2091 * @edid: EDID to duplicate 2092 * 2093 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2094 */ 2095 struct edid *drm_edid_duplicate(const struct edid *edid) 2096 { 2097 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2098 } 2099 EXPORT_SYMBOL(drm_edid_duplicate); 2100 2101 /*** EDID parsing ***/ 2102 2103 /** 2104 * edid_vendor - match a string against EDID's obfuscated vendor field 2105 * @edid: EDID to match 2106 * @vendor: vendor string 2107 * 2108 * Returns true if @vendor is in @edid, false otherwise 2109 */ 2110 static bool edid_vendor(const struct edid *edid, const char *vendor) 2111 { 2112 char edid_vendor[3]; 2113 2114 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2115 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2116 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2117 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2118 2119 return !strncmp(edid_vendor, vendor, 3); 2120 } 2121 2122 /** 2123 * edid_get_quirks - return quirk flags for a given EDID 2124 * @edid: EDID to process 2125 * 2126 * This tells subsequent routines what fixes they need to apply. 2127 */ 2128 static u32 edid_get_quirks(const struct edid *edid) 2129 { 2130 const struct edid_quirk *quirk; 2131 int i; 2132 2133 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2134 quirk = &edid_quirk_list[i]; 2135 2136 if (edid_vendor(edid, quirk->vendor) && 2137 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2138 return quirk->quirks; 2139 } 2140 2141 return 0; 2142 } 2143 2144 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2145 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2146 2147 /** 2148 * edid_fixup_preferred - set preferred modes based on quirk list 2149 * @connector: has mode list to fix up 2150 * @quirks: quirks list 2151 * 2152 * Walk the mode list for @connector, clearing the preferred status 2153 * on existing modes and setting it anew for the right mode ala @quirks. 2154 */ 2155 static void edid_fixup_preferred(struct drm_connector *connector, 2156 u32 quirks) 2157 { 2158 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2159 int target_refresh = 0; 2160 int cur_vrefresh, preferred_vrefresh; 2161 2162 if (list_empty(&connector->probed_modes)) 2163 return; 2164 2165 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2166 target_refresh = 60; 2167 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2168 target_refresh = 75; 2169 2170 preferred_mode = list_first_entry(&connector->probed_modes, 2171 struct drm_display_mode, head); 2172 2173 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2174 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2175 2176 if (cur_mode == preferred_mode) 2177 continue; 2178 2179 /* Largest mode is preferred */ 2180 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2181 preferred_mode = cur_mode; 2182 2183 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2184 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2185 /* At a given size, try to get closest to target refresh */ 2186 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2187 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2188 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2189 preferred_mode = cur_mode; 2190 } 2191 } 2192 2193 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2194 } 2195 2196 static bool 2197 mode_is_rb(const struct drm_display_mode *mode) 2198 { 2199 return (mode->htotal - mode->hdisplay == 160) && 2200 (mode->hsync_end - mode->hdisplay == 80) && 2201 (mode->hsync_end - mode->hsync_start == 32) && 2202 (mode->vsync_start - mode->vdisplay == 3); 2203 } 2204 2205 /* 2206 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2207 * @dev: Device to duplicate against 2208 * @hsize: Mode width 2209 * @vsize: Mode height 2210 * @fresh: Mode refresh rate 2211 * @rb: Mode reduced-blanking-ness 2212 * 2213 * Walk the DMT mode list looking for a match for the given parameters. 2214 * 2215 * Return: A newly allocated copy of the mode, or NULL if not found. 2216 */ 2217 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2218 int hsize, int vsize, int fresh, 2219 bool rb) 2220 { 2221 int i; 2222 2223 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2224 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2225 2226 if (hsize != ptr->hdisplay) 2227 continue; 2228 if (vsize != ptr->vdisplay) 2229 continue; 2230 if (fresh != drm_mode_vrefresh(ptr)) 2231 continue; 2232 if (rb != mode_is_rb(ptr)) 2233 continue; 2234 2235 return drm_mode_duplicate(dev, ptr); 2236 } 2237 2238 return NULL; 2239 } 2240 EXPORT_SYMBOL(drm_mode_find_dmt); 2241 2242 static bool is_display_descriptor(const u8 d[18], u8 tag) 2243 { 2244 return d[0] == 0x00 && d[1] == 0x00 && 2245 d[2] == 0x00 && d[3] == tag; 2246 } 2247 2248 static bool is_detailed_timing_descriptor(const u8 d[18]) 2249 { 2250 return d[0] != 0x00 || d[1] != 0x00; 2251 } 2252 2253 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2254 2255 static void 2256 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2257 { 2258 int i, n; 2259 u8 d = ext[0x02]; 2260 u8 *det_base = ext + d; 2261 2262 if (d < 4 || d > 127) 2263 return; 2264 2265 n = (127 - d) / 18; 2266 for (i = 0; i < n; i++) 2267 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2268 } 2269 2270 static void 2271 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2272 { 2273 unsigned int i, n = min((int)ext[0x02], 6); 2274 u8 *det_base = ext + 5; 2275 2276 if (ext[0x01] != 1) 2277 return; /* unknown version */ 2278 2279 for (i = 0; i < n; i++) 2280 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2281 } 2282 2283 static void 2284 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2285 { 2286 int i; 2287 struct edid *edid = (struct edid *)raw_edid; 2288 2289 if (edid == NULL) 2290 return; 2291 2292 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2293 cb(&(edid->detailed_timings[i]), closure); 2294 2295 for (i = 1; i <= raw_edid[0x7e]; i++) { 2296 u8 *ext = raw_edid + (i * EDID_LENGTH); 2297 2298 switch (*ext) { 2299 case CEA_EXT: 2300 cea_for_each_detailed_block(ext, cb, closure); 2301 break; 2302 case VTB_EXT: 2303 vtb_for_each_detailed_block(ext, cb, closure); 2304 break; 2305 default: 2306 break; 2307 } 2308 } 2309 } 2310 2311 static void 2312 is_rb(struct detailed_timing *t, void *data) 2313 { 2314 u8 *r = (u8 *)t; 2315 2316 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2317 return; 2318 2319 if (r[15] & 0x10) 2320 *(bool *)data = true; 2321 } 2322 2323 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2324 static bool 2325 drm_monitor_supports_rb(struct edid *edid) 2326 { 2327 if (edid->revision >= 4) { 2328 bool ret = false; 2329 2330 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2331 return ret; 2332 } 2333 2334 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2335 } 2336 2337 static void 2338 find_gtf2(struct detailed_timing *t, void *data) 2339 { 2340 u8 *r = (u8 *)t; 2341 2342 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2343 return; 2344 2345 if (r[10] == 0x02) 2346 *(u8 **)data = r; 2347 } 2348 2349 /* Secondary GTF curve kicks in above some break frequency */ 2350 static int 2351 drm_gtf2_hbreak(struct edid *edid) 2352 { 2353 u8 *r = NULL; 2354 2355 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2356 return r ? (r[12] * 2) : 0; 2357 } 2358 2359 static int 2360 drm_gtf2_2c(struct edid *edid) 2361 { 2362 u8 *r = NULL; 2363 2364 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2365 return r ? r[13] : 0; 2366 } 2367 2368 static int 2369 drm_gtf2_m(struct edid *edid) 2370 { 2371 u8 *r = NULL; 2372 2373 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2374 return r ? (r[15] << 8) + r[14] : 0; 2375 } 2376 2377 static int 2378 drm_gtf2_k(struct edid *edid) 2379 { 2380 u8 *r = NULL; 2381 2382 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2383 return r ? r[16] : 0; 2384 } 2385 2386 static int 2387 drm_gtf2_2j(struct edid *edid) 2388 { 2389 u8 *r = NULL; 2390 2391 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2392 return r ? r[17] : 0; 2393 } 2394 2395 /** 2396 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2397 * @edid: EDID block to scan 2398 */ 2399 static int standard_timing_level(struct edid *edid) 2400 { 2401 if (edid->revision >= 2) { 2402 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2403 return LEVEL_CVT; 2404 if (drm_gtf2_hbreak(edid)) 2405 return LEVEL_GTF2; 2406 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2407 return LEVEL_GTF; 2408 } 2409 return LEVEL_DMT; 2410 } 2411 2412 /* 2413 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2414 * monitors fill with ascii space (0x20) instead. 2415 */ 2416 static int 2417 bad_std_timing(u8 a, u8 b) 2418 { 2419 return (a == 0x00 && b == 0x00) || 2420 (a == 0x01 && b == 0x01) || 2421 (a == 0x20 && b == 0x20); 2422 } 2423 2424 static int drm_mode_hsync(const struct drm_display_mode *mode) 2425 { 2426 if (mode->htotal <= 0) 2427 return 0; 2428 2429 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2430 } 2431 2432 /** 2433 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2434 * @connector: connector of for the EDID block 2435 * @edid: EDID block to scan 2436 * @t: standard timing params 2437 * 2438 * Take the standard timing params (in this case width, aspect, and refresh) 2439 * and convert them into a real mode using CVT/GTF/DMT. 2440 */ 2441 static struct drm_display_mode * 2442 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2443 struct std_timing *t) 2444 { 2445 struct drm_device *dev = connector->dev; 2446 struct drm_display_mode *m, *mode = NULL; 2447 int hsize, vsize; 2448 int vrefresh_rate; 2449 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2450 >> EDID_TIMING_ASPECT_SHIFT; 2451 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2452 >> EDID_TIMING_VFREQ_SHIFT; 2453 int timing_level = standard_timing_level(edid); 2454 2455 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2456 return NULL; 2457 2458 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2459 hsize = t->hsize * 8 + 248; 2460 /* vrefresh_rate = vfreq + 60 */ 2461 vrefresh_rate = vfreq + 60; 2462 /* the vdisplay is calculated based on the aspect ratio */ 2463 if (aspect_ratio == 0) { 2464 if (edid->revision < 3) 2465 vsize = hsize; 2466 else 2467 vsize = (hsize * 10) / 16; 2468 } else if (aspect_ratio == 1) 2469 vsize = (hsize * 3) / 4; 2470 else if (aspect_ratio == 2) 2471 vsize = (hsize * 4) / 5; 2472 else 2473 vsize = (hsize * 9) / 16; 2474 2475 /* HDTV hack, part 1 */ 2476 if (vrefresh_rate == 60 && 2477 ((hsize == 1360 && vsize == 765) || 2478 (hsize == 1368 && vsize == 769))) { 2479 hsize = 1366; 2480 vsize = 768; 2481 } 2482 2483 /* 2484 * If this connector already has a mode for this size and refresh 2485 * rate (because it came from detailed or CVT info), use that 2486 * instead. This way we don't have to guess at interlace or 2487 * reduced blanking. 2488 */ 2489 list_for_each_entry(m, &connector->probed_modes, head) 2490 if (m->hdisplay == hsize && m->vdisplay == vsize && 2491 drm_mode_vrefresh(m) == vrefresh_rate) 2492 return NULL; 2493 2494 /* HDTV hack, part 2 */ 2495 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2496 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2497 false); 2498 if (!mode) 2499 return NULL; 2500 mode->hdisplay = 1366; 2501 mode->hsync_start = mode->hsync_start - 1; 2502 mode->hsync_end = mode->hsync_end - 1; 2503 return mode; 2504 } 2505 2506 /* check whether it can be found in default mode table */ 2507 if (drm_monitor_supports_rb(edid)) { 2508 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2509 true); 2510 if (mode) 2511 return mode; 2512 } 2513 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2514 if (mode) 2515 return mode; 2516 2517 /* okay, generate it */ 2518 switch (timing_level) { 2519 case LEVEL_DMT: 2520 break; 2521 case LEVEL_GTF: 2522 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2523 break; 2524 case LEVEL_GTF2: 2525 /* 2526 * This is potentially wrong if there's ever a monitor with 2527 * more than one ranges section, each claiming a different 2528 * secondary GTF curve. Please don't do that. 2529 */ 2530 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2531 if (!mode) 2532 return NULL; 2533 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2534 drm_mode_destroy(dev, mode); 2535 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2536 vrefresh_rate, 0, 0, 2537 drm_gtf2_m(edid), 2538 drm_gtf2_2c(edid), 2539 drm_gtf2_k(edid), 2540 drm_gtf2_2j(edid)); 2541 } 2542 break; 2543 case LEVEL_CVT: 2544 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2545 false); 2546 break; 2547 } 2548 return mode; 2549 } 2550 2551 /* 2552 * EDID is delightfully ambiguous about how interlaced modes are to be 2553 * encoded. Our internal representation is of frame height, but some 2554 * HDTV detailed timings are encoded as field height. 2555 * 2556 * The format list here is from CEA, in frame size. Technically we 2557 * should be checking refresh rate too. Whatever. 2558 */ 2559 static void 2560 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2561 struct detailed_pixel_timing *pt) 2562 { 2563 int i; 2564 static const struct { 2565 int w, h; 2566 } cea_interlaced[] = { 2567 { 1920, 1080 }, 2568 { 720, 480 }, 2569 { 1440, 480 }, 2570 { 2880, 480 }, 2571 { 720, 576 }, 2572 { 1440, 576 }, 2573 { 2880, 576 }, 2574 }; 2575 2576 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2577 return; 2578 2579 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2580 if ((mode->hdisplay == cea_interlaced[i].w) && 2581 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2582 mode->vdisplay *= 2; 2583 mode->vsync_start *= 2; 2584 mode->vsync_end *= 2; 2585 mode->vtotal *= 2; 2586 mode->vtotal |= 1; 2587 } 2588 } 2589 2590 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2591 } 2592 2593 /** 2594 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2595 * @dev: DRM device (needed to create new mode) 2596 * @edid: EDID block 2597 * @timing: EDID detailed timing info 2598 * @quirks: quirks to apply 2599 * 2600 * An EDID detailed timing block contains enough info for us to create and 2601 * return a new struct drm_display_mode. 2602 */ 2603 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2604 struct edid *edid, 2605 struct detailed_timing *timing, 2606 u32 quirks) 2607 { 2608 struct drm_display_mode *mode; 2609 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2610 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2611 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2612 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2613 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2614 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2615 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2616 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2617 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2618 2619 /* ignore tiny modes */ 2620 if (hactive < 64 || vactive < 64) 2621 return NULL; 2622 2623 if (pt->misc & DRM_EDID_PT_STEREO) { 2624 DRM_DEBUG_KMS("stereo mode not supported\n"); 2625 return NULL; 2626 } 2627 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2628 DRM_DEBUG_KMS("composite sync not supported\n"); 2629 } 2630 2631 /* it is incorrect if hsync/vsync width is zero */ 2632 if (!hsync_pulse_width || !vsync_pulse_width) { 2633 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2634 "Wrong Hsync/Vsync pulse width\n"); 2635 return NULL; 2636 } 2637 2638 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2639 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2640 if (!mode) 2641 return NULL; 2642 2643 goto set_size; 2644 } 2645 2646 mode = drm_mode_create(dev); 2647 if (!mode) 2648 return NULL; 2649 2650 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2651 timing->pixel_clock = cpu_to_le16(1088); 2652 2653 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2654 2655 mode->hdisplay = hactive; 2656 mode->hsync_start = mode->hdisplay + hsync_offset; 2657 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2658 mode->htotal = mode->hdisplay + hblank; 2659 2660 mode->vdisplay = vactive; 2661 mode->vsync_start = mode->vdisplay + vsync_offset; 2662 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2663 mode->vtotal = mode->vdisplay + vblank; 2664 2665 /* Some EDIDs have bogus h/vtotal values */ 2666 if (mode->hsync_end > mode->htotal) 2667 mode->htotal = mode->hsync_end + 1; 2668 if (mode->vsync_end > mode->vtotal) 2669 mode->vtotal = mode->vsync_end + 1; 2670 2671 drm_mode_do_interlace_quirk(mode, pt); 2672 2673 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2674 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2675 } 2676 2677 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2678 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2679 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2680 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2681 2682 set_size: 2683 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2684 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2685 2686 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2687 mode->width_mm *= 10; 2688 mode->height_mm *= 10; 2689 } 2690 2691 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2692 mode->width_mm = edid->width_cm * 10; 2693 mode->height_mm = edid->height_cm * 10; 2694 } 2695 2696 mode->type = DRM_MODE_TYPE_DRIVER; 2697 drm_mode_set_name(mode); 2698 2699 return mode; 2700 } 2701 2702 static bool 2703 mode_in_hsync_range(const struct drm_display_mode *mode, 2704 struct edid *edid, u8 *t) 2705 { 2706 int hsync, hmin, hmax; 2707 2708 hmin = t[7]; 2709 if (edid->revision >= 4) 2710 hmin += ((t[4] & 0x04) ? 255 : 0); 2711 hmax = t[8]; 2712 if (edid->revision >= 4) 2713 hmax += ((t[4] & 0x08) ? 255 : 0); 2714 hsync = drm_mode_hsync(mode); 2715 2716 return (hsync <= hmax && hsync >= hmin); 2717 } 2718 2719 static bool 2720 mode_in_vsync_range(const struct drm_display_mode *mode, 2721 struct edid *edid, u8 *t) 2722 { 2723 int vsync, vmin, vmax; 2724 2725 vmin = t[5]; 2726 if (edid->revision >= 4) 2727 vmin += ((t[4] & 0x01) ? 255 : 0); 2728 vmax = t[6]; 2729 if (edid->revision >= 4) 2730 vmax += ((t[4] & 0x02) ? 255 : 0); 2731 vsync = drm_mode_vrefresh(mode); 2732 2733 return (vsync <= vmax && vsync >= vmin); 2734 } 2735 2736 static u32 2737 range_pixel_clock(struct edid *edid, u8 *t) 2738 { 2739 /* unspecified */ 2740 if (t[9] == 0 || t[9] == 255) 2741 return 0; 2742 2743 /* 1.4 with CVT support gives us real precision, yay */ 2744 if (edid->revision >= 4 && t[10] == 0x04) 2745 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2746 2747 /* 1.3 is pathetic, so fuzz up a bit */ 2748 return t[9] * 10000 + 5001; 2749 } 2750 2751 static bool 2752 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2753 struct detailed_timing *timing) 2754 { 2755 u32 max_clock; 2756 u8 *t = (u8 *)timing; 2757 2758 if (!mode_in_hsync_range(mode, edid, t)) 2759 return false; 2760 2761 if (!mode_in_vsync_range(mode, edid, t)) 2762 return false; 2763 2764 if ((max_clock = range_pixel_clock(edid, t))) 2765 if (mode->clock > max_clock) 2766 return false; 2767 2768 /* 1.4 max horizontal check */ 2769 if (edid->revision >= 4 && t[10] == 0x04) 2770 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2771 return false; 2772 2773 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2774 return false; 2775 2776 return true; 2777 } 2778 2779 static bool valid_inferred_mode(const struct drm_connector *connector, 2780 const struct drm_display_mode *mode) 2781 { 2782 const struct drm_display_mode *m; 2783 bool ok = false; 2784 2785 list_for_each_entry(m, &connector->probed_modes, head) { 2786 if (mode->hdisplay == m->hdisplay && 2787 mode->vdisplay == m->vdisplay && 2788 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2789 return false; /* duplicated */ 2790 if (mode->hdisplay <= m->hdisplay && 2791 mode->vdisplay <= m->vdisplay) 2792 ok = true; 2793 } 2794 return ok; 2795 } 2796 2797 static int 2798 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2799 struct detailed_timing *timing) 2800 { 2801 int i, modes = 0; 2802 struct drm_display_mode *newmode; 2803 struct drm_device *dev = connector->dev; 2804 2805 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2806 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2807 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2808 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2809 if (newmode) { 2810 drm_mode_probed_add(connector, newmode); 2811 modes++; 2812 } 2813 } 2814 } 2815 2816 return modes; 2817 } 2818 2819 /* fix up 1366x768 mode from 1368x768; 2820 * GFT/CVT can't express 1366 width which isn't dividable by 8 2821 */ 2822 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2823 { 2824 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2825 mode->hdisplay = 1366; 2826 mode->hsync_start--; 2827 mode->hsync_end--; 2828 drm_mode_set_name(mode); 2829 } 2830 } 2831 2832 static int 2833 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2834 struct detailed_timing *timing) 2835 { 2836 int i, modes = 0; 2837 struct drm_display_mode *newmode; 2838 struct drm_device *dev = connector->dev; 2839 2840 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2841 const struct minimode *m = &extra_modes[i]; 2842 2843 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2844 if (!newmode) 2845 return modes; 2846 2847 drm_mode_fixup_1366x768(newmode); 2848 if (!mode_in_range(newmode, edid, timing) || 2849 !valid_inferred_mode(connector, newmode)) { 2850 drm_mode_destroy(dev, newmode); 2851 continue; 2852 } 2853 2854 drm_mode_probed_add(connector, newmode); 2855 modes++; 2856 } 2857 2858 return modes; 2859 } 2860 2861 static int 2862 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2863 struct detailed_timing *timing) 2864 { 2865 int i, modes = 0; 2866 struct drm_display_mode *newmode; 2867 struct drm_device *dev = connector->dev; 2868 bool rb = drm_monitor_supports_rb(edid); 2869 2870 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2871 const struct minimode *m = &extra_modes[i]; 2872 2873 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2874 if (!newmode) 2875 return modes; 2876 2877 drm_mode_fixup_1366x768(newmode); 2878 if (!mode_in_range(newmode, edid, timing) || 2879 !valid_inferred_mode(connector, newmode)) { 2880 drm_mode_destroy(dev, newmode); 2881 continue; 2882 } 2883 2884 drm_mode_probed_add(connector, newmode); 2885 modes++; 2886 } 2887 2888 return modes; 2889 } 2890 2891 static void 2892 do_inferred_modes(struct detailed_timing *timing, void *c) 2893 { 2894 struct detailed_mode_closure *closure = c; 2895 struct detailed_non_pixel *data = &timing->data.other_data; 2896 struct detailed_data_monitor_range *range = &data->data.range; 2897 2898 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2899 return; 2900 2901 closure->modes += drm_dmt_modes_for_range(closure->connector, 2902 closure->edid, 2903 timing); 2904 2905 if (!version_greater(closure->edid, 1, 1)) 2906 return; /* GTF not defined yet */ 2907 2908 switch (range->flags) { 2909 case 0x02: /* secondary gtf, XXX could do more */ 2910 case 0x00: /* default gtf */ 2911 closure->modes += drm_gtf_modes_for_range(closure->connector, 2912 closure->edid, 2913 timing); 2914 break; 2915 case 0x04: /* cvt, only in 1.4+ */ 2916 if (!version_greater(closure->edid, 1, 3)) 2917 break; 2918 2919 closure->modes += drm_cvt_modes_for_range(closure->connector, 2920 closure->edid, 2921 timing); 2922 break; 2923 case 0x01: /* just the ranges, no formula */ 2924 default: 2925 break; 2926 } 2927 } 2928 2929 static int 2930 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2931 { 2932 struct detailed_mode_closure closure = { 2933 .connector = connector, 2934 .edid = edid, 2935 }; 2936 2937 if (version_greater(edid, 1, 0)) 2938 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2939 &closure); 2940 2941 return closure.modes; 2942 } 2943 2944 static int 2945 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2946 { 2947 int i, j, m, modes = 0; 2948 struct drm_display_mode *mode; 2949 u8 *est = ((u8 *)timing) + 6; 2950 2951 for (i = 0; i < 6; i++) { 2952 for (j = 7; j >= 0; j--) { 2953 m = (i * 8) + (7 - j); 2954 if (m >= ARRAY_SIZE(est3_modes)) 2955 break; 2956 if (est[i] & (1 << j)) { 2957 mode = drm_mode_find_dmt(connector->dev, 2958 est3_modes[m].w, 2959 est3_modes[m].h, 2960 est3_modes[m].r, 2961 est3_modes[m].rb); 2962 if (mode) { 2963 drm_mode_probed_add(connector, mode); 2964 modes++; 2965 } 2966 } 2967 } 2968 } 2969 2970 return modes; 2971 } 2972 2973 static void 2974 do_established_modes(struct detailed_timing *timing, void *c) 2975 { 2976 struct detailed_mode_closure *closure = c; 2977 2978 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2979 return; 2980 2981 closure->modes += drm_est3_modes(closure->connector, timing); 2982 } 2983 2984 /** 2985 * add_established_modes - get est. modes from EDID and add them 2986 * @connector: connector to add mode(s) to 2987 * @edid: EDID block to scan 2988 * 2989 * Each EDID block contains a bitmap of the supported "established modes" list 2990 * (defined above). Tease them out and add them to the global modes list. 2991 */ 2992 static int 2993 add_established_modes(struct drm_connector *connector, struct edid *edid) 2994 { 2995 struct drm_device *dev = connector->dev; 2996 unsigned long est_bits = edid->established_timings.t1 | 2997 (edid->established_timings.t2 << 8) | 2998 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2999 int i, modes = 0; 3000 struct detailed_mode_closure closure = { 3001 .connector = connector, 3002 .edid = edid, 3003 }; 3004 3005 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3006 if (est_bits & (1<<i)) { 3007 struct drm_display_mode *newmode; 3008 3009 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3010 if (newmode) { 3011 drm_mode_probed_add(connector, newmode); 3012 modes++; 3013 } 3014 } 3015 } 3016 3017 if (version_greater(edid, 1, 0)) 3018 drm_for_each_detailed_block((u8 *)edid, 3019 do_established_modes, &closure); 3020 3021 return modes + closure.modes; 3022 } 3023 3024 static void 3025 do_standard_modes(struct detailed_timing *timing, void *c) 3026 { 3027 struct detailed_mode_closure *closure = c; 3028 struct detailed_non_pixel *data = &timing->data.other_data; 3029 struct drm_connector *connector = closure->connector; 3030 struct edid *edid = closure->edid; 3031 int i; 3032 3033 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3034 return; 3035 3036 for (i = 0; i < 6; i++) { 3037 struct std_timing *std = &data->data.timings[i]; 3038 struct drm_display_mode *newmode; 3039 3040 newmode = drm_mode_std(connector, edid, std); 3041 if (newmode) { 3042 drm_mode_probed_add(connector, newmode); 3043 closure->modes++; 3044 } 3045 } 3046 } 3047 3048 /** 3049 * add_standard_modes - get std. modes from EDID and add them 3050 * @connector: connector to add mode(s) to 3051 * @edid: EDID block to scan 3052 * 3053 * Standard modes can be calculated using the appropriate standard (DMT, 3054 * GTF or CVT. Grab them from @edid and add them to the list. 3055 */ 3056 static int 3057 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3058 { 3059 int i, modes = 0; 3060 struct detailed_mode_closure closure = { 3061 .connector = connector, 3062 .edid = edid, 3063 }; 3064 3065 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3066 struct drm_display_mode *newmode; 3067 3068 newmode = drm_mode_std(connector, edid, 3069 &edid->standard_timings[i]); 3070 if (newmode) { 3071 drm_mode_probed_add(connector, newmode); 3072 modes++; 3073 } 3074 } 3075 3076 if (version_greater(edid, 1, 0)) 3077 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3078 &closure); 3079 3080 /* XXX should also look for standard codes in VTB blocks */ 3081 3082 return modes + closure.modes; 3083 } 3084 3085 static int drm_cvt_modes(struct drm_connector *connector, 3086 struct detailed_timing *timing) 3087 { 3088 int i, j, modes = 0; 3089 struct drm_display_mode *newmode; 3090 struct drm_device *dev = connector->dev; 3091 struct cvt_timing *cvt; 3092 const int rates[] = { 60, 85, 75, 60, 50 }; 3093 const u8 empty[3] = { 0, 0, 0 }; 3094 3095 for (i = 0; i < 4; i++) { 3096 int width, height; 3097 3098 cvt = &(timing->data.other_data.data.cvt[i]); 3099 3100 if (!memcmp(cvt->code, empty, 3)) 3101 continue; 3102 3103 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3104 switch (cvt->code[1] & 0x0c) { 3105 case 0x00: 3106 width = height * 4 / 3; 3107 break; 3108 case 0x04: 3109 width = height * 16 / 9; 3110 break; 3111 case 0x08: 3112 width = height * 16 / 10; 3113 break; 3114 case 0x0c: 3115 width = height * 15 / 9; 3116 break; 3117 } 3118 3119 for (j = 1; j < 5; j++) { 3120 if (cvt->code[2] & (1 << j)) { 3121 newmode = drm_cvt_mode(dev, width, height, 3122 rates[j], j == 0, 3123 false, false); 3124 if (newmode) { 3125 drm_mode_probed_add(connector, newmode); 3126 modes++; 3127 } 3128 } 3129 } 3130 } 3131 3132 return modes; 3133 } 3134 3135 static void 3136 do_cvt_mode(struct detailed_timing *timing, void *c) 3137 { 3138 struct detailed_mode_closure *closure = c; 3139 3140 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3141 return; 3142 3143 closure->modes += drm_cvt_modes(closure->connector, timing); 3144 } 3145 3146 static int 3147 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3148 { 3149 struct detailed_mode_closure closure = { 3150 .connector = connector, 3151 .edid = edid, 3152 }; 3153 3154 if (version_greater(edid, 1, 2)) 3155 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3156 3157 /* XXX should also look for CVT codes in VTB blocks */ 3158 3159 return closure.modes; 3160 } 3161 3162 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3163 3164 static void 3165 do_detailed_mode(struct detailed_timing *timing, void *c) 3166 { 3167 struct detailed_mode_closure *closure = c; 3168 struct drm_display_mode *newmode; 3169 3170 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3171 return; 3172 3173 newmode = drm_mode_detailed(closure->connector->dev, 3174 closure->edid, timing, 3175 closure->quirks); 3176 if (!newmode) 3177 return; 3178 3179 if (closure->preferred) 3180 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3181 3182 /* 3183 * Detailed modes are limited to 10kHz pixel clock resolution, 3184 * so fix up anything that looks like CEA/HDMI mode, but the clock 3185 * is just slightly off. 3186 */ 3187 fixup_detailed_cea_mode_clock(newmode); 3188 3189 drm_mode_probed_add(closure->connector, newmode); 3190 closure->modes++; 3191 closure->preferred = false; 3192 } 3193 3194 /* 3195 * add_detailed_modes - Add modes from detailed timings 3196 * @connector: attached connector 3197 * @edid: EDID block to scan 3198 * @quirks: quirks to apply 3199 */ 3200 static int 3201 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3202 u32 quirks) 3203 { 3204 struct detailed_mode_closure closure = { 3205 .connector = connector, 3206 .edid = edid, 3207 .preferred = true, 3208 .quirks = quirks, 3209 }; 3210 3211 if (closure.preferred && !version_greater(edid, 1, 3)) 3212 closure.preferred = 3213 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3214 3215 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3216 3217 return closure.modes; 3218 } 3219 3220 #define AUDIO_BLOCK 0x01 3221 #define VIDEO_BLOCK 0x02 3222 #define VENDOR_BLOCK 0x03 3223 #define SPEAKER_BLOCK 0x04 3224 #define HDR_STATIC_METADATA_BLOCK 0x6 3225 #define USE_EXTENDED_TAG 0x07 3226 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3227 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3228 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3229 #define EDID_BASIC_AUDIO (1 << 6) 3230 #define EDID_CEA_YCRCB444 (1 << 5) 3231 #define EDID_CEA_YCRCB422 (1 << 4) 3232 #define EDID_CEA_VCDB_QS (1 << 6) 3233 3234 /* 3235 * Search EDID for CEA extension block. 3236 */ 3237 static u8 *drm_find_edid_extension(const struct edid *edid, 3238 int ext_id, int *ext_index) 3239 { 3240 u8 *edid_ext = NULL; 3241 int i; 3242 3243 /* No EDID or EDID extensions */ 3244 if (edid == NULL || edid->extensions == 0) 3245 return NULL; 3246 3247 /* Find CEA extension */ 3248 for (i = *ext_index; i < edid->extensions; i++) { 3249 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3250 if (edid_ext[0] == ext_id) 3251 break; 3252 } 3253 3254 if (i >= edid->extensions) 3255 return NULL; 3256 3257 *ext_index = i + 1; 3258 3259 return edid_ext; 3260 } 3261 3262 3263 static u8 *drm_find_displayid_extension(const struct edid *edid, 3264 int *length, int *idx, 3265 int *ext_index) 3266 { 3267 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index); 3268 struct displayid_hdr *base; 3269 int ret; 3270 3271 if (!displayid) 3272 return NULL; 3273 3274 /* EDID extensions block checksum isn't for us */ 3275 *length = EDID_LENGTH - 1; 3276 *idx = 1; 3277 3278 ret = validate_displayid(displayid, *length, *idx); 3279 if (ret) 3280 return NULL; 3281 3282 base = (struct displayid_hdr *)&displayid[*idx]; 3283 *length = *idx + sizeof(*base) + base->bytes; 3284 3285 return displayid; 3286 } 3287 3288 static u8 *drm_find_cea_extension(const struct edid *edid) 3289 { 3290 int length, idx; 3291 struct displayid_block *block; 3292 u8 *cea; 3293 u8 *displayid; 3294 int ext_index; 3295 3296 /* Look for a top level CEA extension block */ 3297 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3298 ext_index = 0; 3299 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3300 if (cea) 3301 return cea; 3302 3303 /* CEA blocks can also be found embedded in a DisplayID block */ 3304 ext_index = 0; 3305 for (;;) { 3306 displayid = drm_find_displayid_extension(edid, &length, &idx, 3307 &ext_index); 3308 if (!displayid) 3309 return NULL; 3310 3311 idx += sizeof(struct displayid_hdr); 3312 for_each_displayid_db(displayid, block, idx, length) { 3313 if (block->tag == DATA_BLOCK_CTA) 3314 return (u8 *)block; 3315 } 3316 } 3317 3318 return NULL; 3319 } 3320 3321 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3322 { 3323 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3324 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3325 3326 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3327 return &edid_cea_modes_1[vic - 1]; 3328 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3329 return &edid_cea_modes_193[vic - 193]; 3330 return NULL; 3331 } 3332 3333 static u8 cea_num_vics(void) 3334 { 3335 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3336 } 3337 3338 static u8 cea_next_vic(u8 vic) 3339 { 3340 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3341 vic = 193; 3342 return vic; 3343 } 3344 3345 /* 3346 * Calculate the alternate clock for the CEA mode 3347 * (60Hz vs. 59.94Hz etc.) 3348 */ 3349 static unsigned int 3350 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3351 { 3352 unsigned int clock = cea_mode->clock; 3353 3354 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3355 return clock; 3356 3357 /* 3358 * edid_cea_modes contains the 59.94Hz 3359 * variant for 240 and 480 line modes, 3360 * and the 60Hz variant otherwise. 3361 */ 3362 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3363 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3364 else 3365 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3366 3367 return clock; 3368 } 3369 3370 static bool 3371 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3372 { 3373 /* 3374 * For certain VICs the spec allows the vertical 3375 * front porch to vary by one or two lines. 3376 * 3377 * cea_modes[] stores the variant with the shortest 3378 * vertical front porch. We can adjust the mode to 3379 * get the other variants by simply increasing the 3380 * vertical front porch length. 3381 */ 3382 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3383 cea_mode_for_vic(9)->vtotal != 262 || 3384 cea_mode_for_vic(12)->vtotal != 262 || 3385 cea_mode_for_vic(13)->vtotal != 262 || 3386 cea_mode_for_vic(23)->vtotal != 312 || 3387 cea_mode_for_vic(24)->vtotal != 312 || 3388 cea_mode_for_vic(27)->vtotal != 312 || 3389 cea_mode_for_vic(28)->vtotal != 312); 3390 3391 if (((vic == 8 || vic == 9 || 3392 vic == 12 || vic == 13) && mode->vtotal < 263) || 3393 ((vic == 23 || vic == 24 || 3394 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3395 mode->vsync_start++; 3396 mode->vsync_end++; 3397 mode->vtotal++; 3398 3399 return true; 3400 } 3401 3402 return false; 3403 } 3404 3405 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3406 unsigned int clock_tolerance) 3407 { 3408 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3409 u8 vic; 3410 3411 if (!to_match->clock) 3412 return 0; 3413 3414 if (to_match->picture_aspect_ratio) 3415 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3416 3417 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3418 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3419 unsigned int clock1, clock2; 3420 3421 /* Check both 60Hz and 59.94Hz */ 3422 clock1 = cea_mode.clock; 3423 clock2 = cea_mode_alternate_clock(&cea_mode); 3424 3425 if (abs(to_match->clock - clock1) > clock_tolerance && 3426 abs(to_match->clock - clock2) > clock_tolerance) 3427 continue; 3428 3429 do { 3430 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3431 return vic; 3432 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3433 } 3434 3435 return 0; 3436 } 3437 3438 /** 3439 * drm_match_cea_mode - look for a CEA mode matching given mode 3440 * @to_match: display mode 3441 * 3442 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3443 * mode. 3444 */ 3445 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3446 { 3447 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3448 u8 vic; 3449 3450 if (!to_match->clock) 3451 return 0; 3452 3453 if (to_match->picture_aspect_ratio) 3454 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3455 3456 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3457 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3458 unsigned int clock1, clock2; 3459 3460 /* Check both 60Hz and 59.94Hz */ 3461 clock1 = cea_mode.clock; 3462 clock2 = cea_mode_alternate_clock(&cea_mode); 3463 3464 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3465 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3466 continue; 3467 3468 do { 3469 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3470 return vic; 3471 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3472 } 3473 3474 return 0; 3475 } 3476 EXPORT_SYMBOL(drm_match_cea_mode); 3477 3478 static bool drm_valid_cea_vic(u8 vic) 3479 { 3480 return cea_mode_for_vic(vic) != NULL; 3481 } 3482 3483 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3484 { 3485 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3486 3487 if (mode) 3488 return mode->picture_aspect_ratio; 3489 3490 return HDMI_PICTURE_ASPECT_NONE; 3491 } 3492 3493 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3494 { 3495 return edid_4k_modes[video_code].picture_aspect_ratio; 3496 } 3497 3498 /* 3499 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3500 * specific block). 3501 */ 3502 static unsigned int 3503 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3504 { 3505 return cea_mode_alternate_clock(hdmi_mode); 3506 } 3507 3508 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3509 unsigned int clock_tolerance) 3510 { 3511 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3512 u8 vic; 3513 3514 if (!to_match->clock) 3515 return 0; 3516 3517 if (to_match->picture_aspect_ratio) 3518 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3519 3520 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3521 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3522 unsigned int clock1, clock2; 3523 3524 /* Make sure to also match alternate clocks */ 3525 clock1 = hdmi_mode->clock; 3526 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3527 3528 if (abs(to_match->clock - clock1) > clock_tolerance && 3529 abs(to_match->clock - clock2) > clock_tolerance) 3530 continue; 3531 3532 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3533 return vic; 3534 } 3535 3536 return 0; 3537 } 3538 3539 /* 3540 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3541 * @to_match: display mode 3542 * 3543 * An HDMI mode is one defined in the HDMI vendor specific block. 3544 * 3545 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3546 */ 3547 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3548 { 3549 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3550 u8 vic; 3551 3552 if (!to_match->clock) 3553 return 0; 3554 3555 if (to_match->picture_aspect_ratio) 3556 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3557 3558 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3559 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3560 unsigned int clock1, clock2; 3561 3562 /* Make sure to also match alternate clocks */ 3563 clock1 = hdmi_mode->clock; 3564 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3565 3566 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3567 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3568 drm_mode_match(to_match, hdmi_mode, match_flags)) 3569 return vic; 3570 } 3571 return 0; 3572 } 3573 3574 static bool drm_valid_hdmi_vic(u8 vic) 3575 { 3576 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3577 } 3578 3579 static int 3580 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3581 { 3582 struct drm_device *dev = connector->dev; 3583 struct drm_display_mode *mode, *tmp; 3584 LIST_HEAD(list); 3585 int modes = 0; 3586 3587 /* Don't add CEA modes if the CEA extension block is missing */ 3588 if (!drm_find_cea_extension(edid)) 3589 return 0; 3590 3591 /* 3592 * Go through all probed modes and create a new mode 3593 * with the alternate clock for certain CEA modes. 3594 */ 3595 list_for_each_entry(mode, &connector->probed_modes, head) { 3596 const struct drm_display_mode *cea_mode = NULL; 3597 struct drm_display_mode *newmode; 3598 u8 vic = drm_match_cea_mode(mode); 3599 unsigned int clock1, clock2; 3600 3601 if (drm_valid_cea_vic(vic)) { 3602 cea_mode = cea_mode_for_vic(vic); 3603 clock2 = cea_mode_alternate_clock(cea_mode); 3604 } else { 3605 vic = drm_match_hdmi_mode(mode); 3606 if (drm_valid_hdmi_vic(vic)) { 3607 cea_mode = &edid_4k_modes[vic]; 3608 clock2 = hdmi_mode_alternate_clock(cea_mode); 3609 } 3610 } 3611 3612 if (!cea_mode) 3613 continue; 3614 3615 clock1 = cea_mode->clock; 3616 3617 if (clock1 == clock2) 3618 continue; 3619 3620 if (mode->clock != clock1 && mode->clock != clock2) 3621 continue; 3622 3623 newmode = drm_mode_duplicate(dev, cea_mode); 3624 if (!newmode) 3625 continue; 3626 3627 /* Carry over the stereo flags */ 3628 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3629 3630 /* 3631 * The current mode could be either variant. Make 3632 * sure to pick the "other" clock for the new mode. 3633 */ 3634 if (mode->clock != clock1) 3635 newmode->clock = clock1; 3636 else 3637 newmode->clock = clock2; 3638 3639 list_add_tail(&newmode->head, &list); 3640 } 3641 3642 list_for_each_entry_safe(mode, tmp, &list, head) { 3643 list_del(&mode->head); 3644 drm_mode_probed_add(connector, mode); 3645 modes++; 3646 } 3647 3648 return modes; 3649 } 3650 3651 static u8 svd_to_vic(u8 svd) 3652 { 3653 /* 0-6 bit vic, 7th bit native mode indicator */ 3654 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3655 return svd & 127; 3656 3657 return svd; 3658 } 3659 3660 static struct drm_display_mode * 3661 drm_display_mode_from_vic_index(struct drm_connector *connector, 3662 const u8 *video_db, u8 video_len, 3663 u8 video_index) 3664 { 3665 struct drm_device *dev = connector->dev; 3666 struct drm_display_mode *newmode; 3667 u8 vic; 3668 3669 if (video_db == NULL || video_index >= video_len) 3670 return NULL; 3671 3672 /* CEA modes are numbered 1..127 */ 3673 vic = svd_to_vic(video_db[video_index]); 3674 if (!drm_valid_cea_vic(vic)) 3675 return NULL; 3676 3677 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3678 if (!newmode) 3679 return NULL; 3680 3681 return newmode; 3682 } 3683 3684 /* 3685 * do_y420vdb_modes - Parse YCBCR 420 only modes 3686 * @connector: connector corresponding to the HDMI sink 3687 * @svds: start of the data block of CEA YCBCR 420 VDB 3688 * @len: length of the CEA YCBCR 420 VDB 3689 * 3690 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3691 * which contains modes which can be supported in YCBCR 420 3692 * output format only. 3693 */ 3694 static int do_y420vdb_modes(struct drm_connector *connector, 3695 const u8 *svds, u8 svds_len) 3696 { 3697 int modes = 0, i; 3698 struct drm_device *dev = connector->dev; 3699 struct drm_display_info *info = &connector->display_info; 3700 struct drm_hdmi_info *hdmi = &info->hdmi; 3701 3702 for (i = 0; i < svds_len; i++) { 3703 u8 vic = svd_to_vic(svds[i]); 3704 struct drm_display_mode *newmode; 3705 3706 if (!drm_valid_cea_vic(vic)) 3707 continue; 3708 3709 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3710 if (!newmode) 3711 break; 3712 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3713 drm_mode_probed_add(connector, newmode); 3714 modes++; 3715 } 3716 3717 if (modes > 0) 3718 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3719 return modes; 3720 } 3721 3722 /* 3723 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3724 * @connector: connector corresponding to the HDMI sink 3725 * @vic: CEA vic for the video mode to be added in the map 3726 * 3727 * Makes an entry for a videomode in the YCBCR 420 bitmap 3728 */ 3729 static void 3730 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3731 { 3732 u8 vic = svd_to_vic(svd); 3733 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3734 3735 if (!drm_valid_cea_vic(vic)) 3736 return; 3737 3738 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3739 } 3740 3741 /** 3742 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3743 * @dev: DRM device 3744 * @vic: CEA VIC of the mode 3745 * 3746 * Creates a new mode matching the specified CEA VIC. 3747 * 3748 * Returns: A new drm_display_mode on success or NULL on failure 3749 */ 3750 struct drm_display_mode * 3751 drm_display_mode_from_cea_vic(struct drm_device *dev, 3752 u8 video_code) 3753 { 3754 const struct drm_display_mode *cea_mode; 3755 struct drm_display_mode *newmode; 3756 3757 cea_mode = cea_mode_for_vic(video_code); 3758 if (!cea_mode) 3759 return NULL; 3760 3761 newmode = drm_mode_duplicate(dev, cea_mode); 3762 if (!newmode) 3763 return NULL; 3764 3765 return newmode; 3766 } 3767 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3768 3769 static int 3770 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3771 { 3772 int i, modes = 0; 3773 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3774 3775 for (i = 0; i < len; i++) { 3776 struct drm_display_mode *mode; 3777 3778 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3779 if (mode) { 3780 /* 3781 * YCBCR420 capability block contains a bitmap which 3782 * gives the index of CEA modes from CEA VDB, which 3783 * can support YCBCR 420 sampling output also (apart 3784 * from RGB/YCBCR444 etc). 3785 * For example, if the bit 0 in bitmap is set, 3786 * first mode in VDB can support YCBCR420 output too. 3787 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3788 */ 3789 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3790 drm_add_cmdb_modes(connector, db[i]); 3791 3792 drm_mode_probed_add(connector, mode); 3793 modes++; 3794 } 3795 } 3796 3797 return modes; 3798 } 3799 3800 struct stereo_mandatory_mode { 3801 int width, height, vrefresh; 3802 unsigned int flags; 3803 }; 3804 3805 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3806 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3807 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3808 { 1920, 1080, 50, 3809 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3810 { 1920, 1080, 60, 3811 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3812 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3813 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3814 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3815 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3816 }; 3817 3818 static bool 3819 stereo_match_mandatory(const struct drm_display_mode *mode, 3820 const struct stereo_mandatory_mode *stereo_mode) 3821 { 3822 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3823 3824 return mode->hdisplay == stereo_mode->width && 3825 mode->vdisplay == stereo_mode->height && 3826 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3827 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3828 } 3829 3830 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3831 { 3832 struct drm_device *dev = connector->dev; 3833 const struct drm_display_mode *mode; 3834 struct list_head stereo_modes; 3835 int modes = 0, i; 3836 3837 INIT_LIST_HEAD(&stereo_modes); 3838 3839 list_for_each_entry(mode, &connector->probed_modes, head) { 3840 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3841 const struct stereo_mandatory_mode *mandatory; 3842 struct drm_display_mode *new_mode; 3843 3844 if (!stereo_match_mandatory(mode, 3845 &stereo_mandatory_modes[i])) 3846 continue; 3847 3848 mandatory = &stereo_mandatory_modes[i]; 3849 new_mode = drm_mode_duplicate(dev, mode); 3850 if (!new_mode) 3851 continue; 3852 3853 new_mode->flags |= mandatory->flags; 3854 list_add_tail(&new_mode->head, &stereo_modes); 3855 modes++; 3856 } 3857 } 3858 3859 list_splice_tail(&stereo_modes, &connector->probed_modes); 3860 3861 return modes; 3862 } 3863 3864 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3865 { 3866 struct drm_device *dev = connector->dev; 3867 struct drm_display_mode *newmode; 3868 3869 if (!drm_valid_hdmi_vic(vic)) { 3870 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3871 return 0; 3872 } 3873 3874 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3875 if (!newmode) 3876 return 0; 3877 3878 drm_mode_probed_add(connector, newmode); 3879 3880 return 1; 3881 } 3882 3883 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3884 const u8 *video_db, u8 video_len, u8 video_index) 3885 { 3886 struct drm_display_mode *newmode; 3887 int modes = 0; 3888 3889 if (structure & (1 << 0)) { 3890 newmode = drm_display_mode_from_vic_index(connector, video_db, 3891 video_len, 3892 video_index); 3893 if (newmode) { 3894 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3895 drm_mode_probed_add(connector, newmode); 3896 modes++; 3897 } 3898 } 3899 if (structure & (1 << 6)) { 3900 newmode = drm_display_mode_from_vic_index(connector, video_db, 3901 video_len, 3902 video_index); 3903 if (newmode) { 3904 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3905 drm_mode_probed_add(connector, newmode); 3906 modes++; 3907 } 3908 } 3909 if (structure & (1 << 8)) { 3910 newmode = drm_display_mode_from_vic_index(connector, video_db, 3911 video_len, 3912 video_index); 3913 if (newmode) { 3914 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3915 drm_mode_probed_add(connector, newmode); 3916 modes++; 3917 } 3918 } 3919 3920 return modes; 3921 } 3922 3923 /* 3924 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3925 * @connector: connector corresponding to the HDMI sink 3926 * @db: start of the CEA vendor specific block 3927 * @len: length of the CEA block payload, ie. one can access up to db[len] 3928 * 3929 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3930 * also adds the stereo 3d modes when applicable. 3931 */ 3932 static int 3933 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3934 const u8 *video_db, u8 video_len) 3935 { 3936 struct drm_display_info *info = &connector->display_info; 3937 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3938 u8 vic_len, hdmi_3d_len = 0; 3939 u16 mask; 3940 u16 structure_all; 3941 3942 if (len < 8) 3943 goto out; 3944 3945 /* no HDMI_Video_Present */ 3946 if (!(db[8] & (1 << 5))) 3947 goto out; 3948 3949 /* Latency_Fields_Present */ 3950 if (db[8] & (1 << 7)) 3951 offset += 2; 3952 3953 /* I_Latency_Fields_Present */ 3954 if (db[8] & (1 << 6)) 3955 offset += 2; 3956 3957 /* the declared length is not long enough for the 2 first bytes 3958 * of additional video format capabilities */ 3959 if (len < (8 + offset + 2)) 3960 goto out; 3961 3962 /* 3D_Present */ 3963 offset++; 3964 if (db[8 + offset] & (1 << 7)) { 3965 modes += add_hdmi_mandatory_stereo_modes(connector); 3966 3967 /* 3D_Multi_present */ 3968 multi_present = (db[8 + offset] & 0x60) >> 5; 3969 } 3970 3971 offset++; 3972 vic_len = db[8 + offset] >> 5; 3973 hdmi_3d_len = db[8 + offset] & 0x1f; 3974 3975 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3976 u8 vic; 3977 3978 vic = db[9 + offset + i]; 3979 modes += add_hdmi_mode(connector, vic); 3980 } 3981 offset += 1 + vic_len; 3982 3983 if (multi_present == 1) 3984 multi_len = 2; 3985 else if (multi_present == 2) 3986 multi_len = 4; 3987 else 3988 multi_len = 0; 3989 3990 if (len < (8 + offset + hdmi_3d_len - 1)) 3991 goto out; 3992 3993 if (hdmi_3d_len < multi_len) 3994 goto out; 3995 3996 if (multi_present == 1 || multi_present == 2) { 3997 /* 3D_Structure_ALL */ 3998 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3999 4000 /* check if 3D_MASK is present */ 4001 if (multi_present == 2) 4002 mask = (db[10 + offset] << 8) | db[11 + offset]; 4003 else 4004 mask = 0xffff; 4005 4006 for (i = 0; i < 16; i++) { 4007 if (mask & (1 << i)) 4008 modes += add_3d_struct_modes(connector, 4009 structure_all, 4010 video_db, 4011 video_len, i); 4012 } 4013 } 4014 4015 offset += multi_len; 4016 4017 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4018 int vic_index; 4019 struct drm_display_mode *newmode = NULL; 4020 unsigned int newflag = 0; 4021 bool detail_present; 4022 4023 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4024 4025 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4026 break; 4027 4028 /* 2D_VIC_order_X */ 4029 vic_index = db[8 + offset + i] >> 4; 4030 4031 /* 3D_Structure_X */ 4032 switch (db[8 + offset + i] & 0x0f) { 4033 case 0: 4034 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4035 break; 4036 case 6: 4037 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4038 break; 4039 case 8: 4040 /* 3D_Detail_X */ 4041 if ((db[9 + offset + i] >> 4) == 1) 4042 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4043 break; 4044 } 4045 4046 if (newflag != 0) { 4047 newmode = drm_display_mode_from_vic_index(connector, 4048 video_db, 4049 video_len, 4050 vic_index); 4051 4052 if (newmode) { 4053 newmode->flags |= newflag; 4054 drm_mode_probed_add(connector, newmode); 4055 modes++; 4056 } 4057 } 4058 4059 if (detail_present) 4060 i++; 4061 } 4062 4063 out: 4064 if (modes > 0) 4065 info->has_hdmi_infoframe = true; 4066 return modes; 4067 } 4068 4069 static int 4070 cea_db_payload_len(const u8 *db) 4071 { 4072 return db[0] & 0x1f; 4073 } 4074 4075 static int 4076 cea_db_extended_tag(const u8 *db) 4077 { 4078 return db[1]; 4079 } 4080 4081 static int 4082 cea_db_tag(const u8 *db) 4083 { 4084 return db[0] >> 5; 4085 } 4086 4087 static int 4088 cea_revision(const u8 *cea) 4089 { 4090 /* 4091 * FIXME is this correct for the DispID variant? 4092 * The DispID spec doesn't really specify whether 4093 * this is the revision of the CEA extension or 4094 * the DispID CEA data block. And the only value 4095 * given as an example is 0. 4096 */ 4097 return cea[1]; 4098 } 4099 4100 static int 4101 cea_db_offsets(const u8 *cea, int *start, int *end) 4102 { 4103 /* DisplayID CTA extension blocks and top-level CEA EDID 4104 * block header definitions differ in the following bytes: 4105 * 1) Byte 2 of the header specifies length differently, 4106 * 2) Byte 3 is only present in the CEA top level block. 4107 * 4108 * The different definitions for byte 2 follow. 4109 * 4110 * DisplayID CTA extension block defines byte 2 as: 4111 * Number of payload bytes 4112 * 4113 * CEA EDID block defines byte 2 as: 4114 * Byte number (decimal) within this block where the 18-byte 4115 * DTDs begin. If no non-DTD data is present in this extension 4116 * block, the value should be set to 04h (the byte after next). 4117 * If set to 00h, there are no DTDs present in this block and 4118 * no non-DTD data. 4119 */ 4120 if (cea[0] == DATA_BLOCK_CTA) { 4121 /* 4122 * for_each_displayid_db() has already verified 4123 * that these stay within expected bounds. 4124 */ 4125 *start = 3; 4126 *end = *start + cea[2]; 4127 } else if (cea[0] == CEA_EXT) { 4128 /* Data block offset in CEA extension block */ 4129 *start = 4; 4130 *end = cea[2]; 4131 if (*end == 0) 4132 *end = 127; 4133 if (*end < 4 || *end > 127) 4134 return -ERANGE; 4135 } else { 4136 return -EOPNOTSUPP; 4137 } 4138 4139 return 0; 4140 } 4141 4142 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4143 { 4144 int hdmi_id; 4145 4146 if (cea_db_tag(db) != VENDOR_BLOCK) 4147 return false; 4148 4149 if (cea_db_payload_len(db) < 5) 4150 return false; 4151 4152 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4153 4154 return hdmi_id == HDMI_IEEE_OUI; 4155 } 4156 4157 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4158 { 4159 unsigned int oui; 4160 4161 if (cea_db_tag(db) != VENDOR_BLOCK) 4162 return false; 4163 4164 if (cea_db_payload_len(db) < 7) 4165 return false; 4166 4167 oui = db[3] << 16 | db[2] << 8 | db[1]; 4168 4169 return oui == HDMI_FORUM_IEEE_OUI; 4170 } 4171 4172 static bool cea_db_is_vcdb(const u8 *db) 4173 { 4174 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4175 return false; 4176 4177 if (cea_db_payload_len(db) != 2) 4178 return false; 4179 4180 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4181 return false; 4182 4183 return true; 4184 } 4185 4186 static bool cea_db_is_y420cmdb(const u8 *db) 4187 { 4188 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4189 return false; 4190 4191 if (!cea_db_payload_len(db)) 4192 return false; 4193 4194 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4195 return false; 4196 4197 return true; 4198 } 4199 4200 static bool cea_db_is_y420vdb(const u8 *db) 4201 { 4202 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4203 return false; 4204 4205 if (!cea_db_payload_len(db)) 4206 return false; 4207 4208 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4209 return false; 4210 4211 return true; 4212 } 4213 4214 #define for_each_cea_db(cea, i, start, end) \ 4215 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4216 4217 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4218 const u8 *db) 4219 { 4220 struct drm_display_info *info = &connector->display_info; 4221 struct drm_hdmi_info *hdmi = &info->hdmi; 4222 u8 map_len = cea_db_payload_len(db) - 1; 4223 u8 count; 4224 u64 map = 0; 4225 4226 if (map_len == 0) { 4227 /* All CEA modes support ycbcr420 sampling also.*/ 4228 hdmi->y420_cmdb_map = U64_MAX; 4229 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4230 return; 4231 } 4232 4233 /* 4234 * This map indicates which of the existing CEA block modes 4235 * from VDB can support YCBCR420 output too. So if bit=0 is 4236 * set, first mode from VDB can support YCBCR420 output too. 4237 * We will parse and keep this map, before parsing VDB itself 4238 * to avoid going through the same block again and again. 4239 * 4240 * Spec is not clear about max possible size of this block. 4241 * Clamping max bitmap block size at 8 bytes. Every byte can 4242 * address 8 CEA modes, in this way this map can address 4243 * 8*8 = first 64 SVDs. 4244 */ 4245 if (WARN_ON_ONCE(map_len > 8)) 4246 map_len = 8; 4247 4248 for (count = 0; count < map_len; count++) 4249 map |= (u64)db[2 + count] << (8 * count); 4250 4251 if (map) 4252 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4253 4254 hdmi->y420_cmdb_map = map; 4255 } 4256 4257 static int 4258 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4259 { 4260 const u8 *cea = drm_find_cea_extension(edid); 4261 const u8 *db, *hdmi = NULL, *video = NULL; 4262 u8 dbl, hdmi_len, video_len = 0; 4263 int modes = 0; 4264 4265 if (cea && cea_revision(cea) >= 3) { 4266 int i, start, end; 4267 4268 if (cea_db_offsets(cea, &start, &end)) 4269 return 0; 4270 4271 for_each_cea_db(cea, i, start, end) { 4272 db = &cea[i]; 4273 dbl = cea_db_payload_len(db); 4274 4275 if (cea_db_tag(db) == VIDEO_BLOCK) { 4276 video = db + 1; 4277 video_len = dbl; 4278 modes += do_cea_modes(connector, video, dbl); 4279 } else if (cea_db_is_hdmi_vsdb(db)) { 4280 hdmi = db; 4281 hdmi_len = dbl; 4282 } else if (cea_db_is_y420vdb(db)) { 4283 const u8 *vdb420 = &db[2]; 4284 4285 /* Add 4:2:0(only) modes present in EDID */ 4286 modes += do_y420vdb_modes(connector, 4287 vdb420, 4288 dbl - 1); 4289 } 4290 } 4291 } 4292 4293 /* 4294 * We parse the HDMI VSDB after having added the cea modes as we will 4295 * be patching their flags when the sink supports stereo 3D. 4296 */ 4297 if (hdmi) 4298 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4299 video_len); 4300 4301 return modes; 4302 } 4303 4304 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4305 { 4306 const struct drm_display_mode *cea_mode; 4307 int clock1, clock2, clock; 4308 u8 vic; 4309 const char *type; 4310 4311 /* 4312 * allow 5kHz clock difference either way to account for 4313 * the 10kHz clock resolution limit of detailed timings. 4314 */ 4315 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4316 if (drm_valid_cea_vic(vic)) { 4317 type = "CEA"; 4318 cea_mode = cea_mode_for_vic(vic); 4319 clock1 = cea_mode->clock; 4320 clock2 = cea_mode_alternate_clock(cea_mode); 4321 } else { 4322 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4323 if (drm_valid_hdmi_vic(vic)) { 4324 type = "HDMI"; 4325 cea_mode = &edid_4k_modes[vic]; 4326 clock1 = cea_mode->clock; 4327 clock2 = hdmi_mode_alternate_clock(cea_mode); 4328 } else { 4329 return; 4330 } 4331 } 4332 4333 /* pick whichever is closest */ 4334 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4335 clock = clock1; 4336 else 4337 clock = clock2; 4338 4339 if (mode->clock == clock) 4340 return; 4341 4342 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4343 type, vic, mode->clock, clock); 4344 mode->clock = clock; 4345 } 4346 4347 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4348 { 4349 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4350 return false; 4351 4352 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4353 return false; 4354 4355 if (cea_db_payload_len(db) < 3) 4356 return false; 4357 4358 return true; 4359 } 4360 4361 static uint8_t eotf_supported(const u8 *edid_ext) 4362 { 4363 return edid_ext[2] & 4364 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4365 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4366 BIT(HDMI_EOTF_SMPTE_ST2084) | 4367 BIT(HDMI_EOTF_BT_2100_HLG)); 4368 } 4369 4370 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4371 { 4372 return edid_ext[3] & 4373 BIT(HDMI_STATIC_METADATA_TYPE1); 4374 } 4375 4376 static void 4377 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4378 { 4379 u16 len; 4380 4381 len = cea_db_payload_len(db); 4382 4383 connector->hdr_sink_metadata.hdmi_type1.eotf = 4384 eotf_supported(db); 4385 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4386 hdr_metadata_type(db); 4387 4388 if (len >= 4) 4389 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4390 if (len >= 5) 4391 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4392 if (len >= 6) 4393 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4394 } 4395 4396 static void 4397 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4398 { 4399 u8 len = cea_db_payload_len(db); 4400 4401 if (len >= 6 && (db[6] & (1 << 7))) 4402 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4403 if (len >= 8) { 4404 connector->latency_present[0] = db[8] >> 7; 4405 connector->latency_present[1] = (db[8] >> 6) & 1; 4406 } 4407 if (len >= 9) 4408 connector->video_latency[0] = db[9]; 4409 if (len >= 10) 4410 connector->audio_latency[0] = db[10]; 4411 if (len >= 11) 4412 connector->video_latency[1] = db[11]; 4413 if (len >= 12) 4414 connector->audio_latency[1] = db[12]; 4415 4416 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4417 "video latency %d %d, " 4418 "audio latency %d %d\n", 4419 connector->latency_present[0], 4420 connector->latency_present[1], 4421 connector->video_latency[0], 4422 connector->video_latency[1], 4423 connector->audio_latency[0], 4424 connector->audio_latency[1]); 4425 } 4426 4427 static void 4428 monitor_name(struct detailed_timing *t, void *data) 4429 { 4430 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4431 return; 4432 4433 *(u8 **)data = t->data.other_data.data.str.str; 4434 } 4435 4436 static int get_monitor_name(struct edid *edid, char name[13]) 4437 { 4438 char *edid_name = NULL; 4439 int mnl; 4440 4441 if (!edid || !name) 4442 return 0; 4443 4444 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4445 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4446 if (edid_name[mnl] == 0x0a) 4447 break; 4448 4449 name[mnl] = edid_name[mnl]; 4450 } 4451 4452 return mnl; 4453 } 4454 4455 /** 4456 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4457 * @edid: monitor EDID information 4458 * @name: pointer to a character array to hold the name of the monitor 4459 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4460 * 4461 */ 4462 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4463 { 4464 int name_length; 4465 char buf[13]; 4466 4467 if (bufsize <= 0) 4468 return; 4469 4470 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4471 memcpy(name, buf, name_length); 4472 name[name_length] = '\0'; 4473 } 4474 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4475 4476 static void clear_eld(struct drm_connector *connector) 4477 { 4478 memset(connector->eld, 0, sizeof(connector->eld)); 4479 4480 connector->latency_present[0] = false; 4481 connector->latency_present[1] = false; 4482 connector->video_latency[0] = 0; 4483 connector->audio_latency[0] = 0; 4484 connector->video_latency[1] = 0; 4485 connector->audio_latency[1] = 0; 4486 } 4487 4488 /* 4489 * drm_edid_to_eld - build ELD from EDID 4490 * @connector: connector corresponding to the HDMI/DP sink 4491 * @edid: EDID to parse 4492 * 4493 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4494 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4495 */ 4496 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4497 { 4498 uint8_t *eld = connector->eld; 4499 u8 *cea; 4500 u8 *db; 4501 int total_sad_count = 0; 4502 int mnl; 4503 int dbl; 4504 4505 clear_eld(connector); 4506 4507 if (!edid) 4508 return; 4509 4510 cea = drm_find_cea_extension(edid); 4511 if (!cea) { 4512 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4513 return; 4514 } 4515 4516 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4517 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4518 4519 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4520 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4521 4522 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4523 4524 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4525 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4526 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4527 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4528 4529 if (cea_revision(cea) >= 3) { 4530 int i, start, end; 4531 int sad_count; 4532 4533 if (cea_db_offsets(cea, &start, &end)) { 4534 start = 0; 4535 end = 0; 4536 } 4537 4538 for_each_cea_db(cea, i, start, end) { 4539 db = &cea[i]; 4540 dbl = cea_db_payload_len(db); 4541 4542 switch (cea_db_tag(db)) { 4543 case AUDIO_BLOCK: 4544 /* Audio Data Block, contains SADs */ 4545 sad_count = min(dbl / 3, 15 - total_sad_count); 4546 if (sad_count >= 1) 4547 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4548 &db[1], sad_count * 3); 4549 total_sad_count += sad_count; 4550 break; 4551 case SPEAKER_BLOCK: 4552 /* Speaker Allocation Data Block */ 4553 if (dbl >= 1) 4554 eld[DRM_ELD_SPEAKER] = db[1]; 4555 break; 4556 case VENDOR_BLOCK: 4557 /* HDMI Vendor-Specific Data Block */ 4558 if (cea_db_is_hdmi_vsdb(db)) 4559 drm_parse_hdmi_vsdb_audio(connector, db); 4560 break; 4561 default: 4562 break; 4563 } 4564 } 4565 } 4566 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4567 4568 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4569 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4570 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4571 else 4572 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4573 4574 eld[DRM_ELD_BASELINE_ELD_LEN] = 4575 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4576 4577 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4578 drm_eld_size(eld), total_sad_count); 4579 } 4580 4581 /** 4582 * drm_edid_to_sad - extracts SADs from EDID 4583 * @edid: EDID to parse 4584 * @sads: pointer that will be set to the extracted SADs 4585 * 4586 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4587 * 4588 * Note: The returned pointer needs to be freed using kfree(). 4589 * 4590 * Return: The number of found SADs or negative number on error. 4591 */ 4592 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4593 { 4594 int count = 0; 4595 int i, start, end, dbl; 4596 u8 *cea; 4597 4598 cea = drm_find_cea_extension(edid); 4599 if (!cea) { 4600 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4601 return 0; 4602 } 4603 4604 if (cea_revision(cea) < 3) { 4605 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4606 return 0; 4607 } 4608 4609 if (cea_db_offsets(cea, &start, &end)) { 4610 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4611 return -EPROTO; 4612 } 4613 4614 for_each_cea_db(cea, i, start, end) { 4615 u8 *db = &cea[i]; 4616 4617 if (cea_db_tag(db) == AUDIO_BLOCK) { 4618 int j; 4619 4620 dbl = cea_db_payload_len(db); 4621 4622 count = dbl / 3; /* SAD is 3B */ 4623 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4624 if (!*sads) 4625 return -ENOMEM; 4626 for (j = 0; j < count; j++) { 4627 u8 *sad = &db[1 + j * 3]; 4628 4629 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4630 (*sads)[j].channels = sad[0] & 0x7; 4631 (*sads)[j].freq = sad[1] & 0x7F; 4632 (*sads)[j].byte2 = sad[2]; 4633 } 4634 break; 4635 } 4636 } 4637 4638 return count; 4639 } 4640 EXPORT_SYMBOL(drm_edid_to_sad); 4641 4642 /** 4643 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4644 * @edid: EDID to parse 4645 * @sadb: pointer to the speaker block 4646 * 4647 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4648 * 4649 * Note: The returned pointer needs to be freed using kfree(). 4650 * 4651 * Return: The number of found Speaker Allocation Blocks or negative number on 4652 * error. 4653 */ 4654 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4655 { 4656 int count = 0; 4657 int i, start, end, dbl; 4658 const u8 *cea; 4659 4660 cea = drm_find_cea_extension(edid); 4661 if (!cea) { 4662 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4663 return 0; 4664 } 4665 4666 if (cea_revision(cea) < 3) { 4667 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4668 return 0; 4669 } 4670 4671 if (cea_db_offsets(cea, &start, &end)) { 4672 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4673 return -EPROTO; 4674 } 4675 4676 for_each_cea_db(cea, i, start, end) { 4677 const u8 *db = &cea[i]; 4678 4679 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4680 dbl = cea_db_payload_len(db); 4681 4682 /* Speaker Allocation Data Block */ 4683 if (dbl == 3) { 4684 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4685 if (!*sadb) 4686 return -ENOMEM; 4687 count = dbl; 4688 break; 4689 } 4690 } 4691 } 4692 4693 return count; 4694 } 4695 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4696 4697 /** 4698 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4699 * @connector: connector associated with the HDMI/DP sink 4700 * @mode: the display mode 4701 * 4702 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4703 * the sink doesn't support audio or video. 4704 */ 4705 int drm_av_sync_delay(struct drm_connector *connector, 4706 const struct drm_display_mode *mode) 4707 { 4708 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4709 int a, v; 4710 4711 if (!connector->latency_present[0]) 4712 return 0; 4713 if (!connector->latency_present[1]) 4714 i = 0; 4715 4716 a = connector->audio_latency[i]; 4717 v = connector->video_latency[i]; 4718 4719 /* 4720 * HDMI/DP sink doesn't support audio or video? 4721 */ 4722 if (a == 255 || v == 255) 4723 return 0; 4724 4725 /* 4726 * Convert raw EDID values to millisecond. 4727 * Treat unknown latency as 0ms. 4728 */ 4729 if (a) 4730 a = min(2 * (a - 1), 500); 4731 if (v) 4732 v = min(2 * (v - 1), 500); 4733 4734 return max(v - a, 0); 4735 } 4736 EXPORT_SYMBOL(drm_av_sync_delay); 4737 4738 /** 4739 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4740 * @edid: monitor EDID information 4741 * 4742 * Parse the CEA extension according to CEA-861-B. 4743 * 4744 * Drivers that have added the modes parsed from EDID to drm_display_info 4745 * should use &drm_display_info.is_hdmi instead of calling this function. 4746 * 4747 * Return: True if the monitor is HDMI, false if not or unknown. 4748 */ 4749 bool drm_detect_hdmi_monitor(struct edid *edid) 4750 { 4751 u8 *edid_ext; 4752 int i; 4753 int start_offset, end_offset; 4754 4755 edid_ext = drm_find_cea_extension(edid); 4756 if (!edid_ext) 4757 return false; 4758 4759 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4760 return false; 4761 4762 /* 4763 * Because HDMI identifier is in Vendor Specific Block, 4764 * search it from all data blocks of CEA extension. 4765 */ 4766 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4767 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4768 return true; 4769 } 4770 4771 return false; 4772 } 4773 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4774 4775 /** 4776 * drm_detect_monitor_audio - check monitor audio capability 4777 * @edid: EDID block to scan 4778 * 4779 * Monitor should have CEA extension block. 4780 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4781 * audio' only. If there is any audio extension block and supported 4782 * audio format, assume at least 'basic audio' support, even if 'basic 4783 * audio' is not defined in EDID. 4784 * 4785 * Return: True if the monitor supports audio, false otherwise. 4786 */ 4787 bool drm_detect_monitor_audio(struct edid *edid) 4788 { 4789 u8 *edid_ext; 4790 int i, j; 4791 bool has_audio = false; 4792 int start_offset, end_offset; 4793 4794 edid_ext = drm_find_cea_extension(edid); 4795 if (!edid_ext) 4796 goto end; 4797 4798 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4799 4800 if (has_audio) { 4801 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4802 goto end; 4803 } 4804 4805 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4806 goto end; 4807 4808 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4809 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4810 has_audio = true; 4811 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4812 DRM_DEBUG_KMS("CEA audio format %d\n", 4813 (edid_ext[i + j] >> 3) & 0xf); 4814 goto end; 4815 } 4816 } 4817 end: 4818 return has_audio; 4819 } 4820 EXPORT_SYMBOL(drm_detect_monitor_audio); 4821 4822 4823 /** 4824 * drm_default_rgb_quant_range - default RGB quantization range 4825 * @mode: display mode 4826 * 4827 * Determine the default RGB quantization range for the mode, 4828 * as specified in CEA-861. 4829 * 4830 * Return: The default RGB quantization range for the mode 4831 */ 4832 enum hdmi_quantization_range 4833 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4834 { 4835 /* All CEA modes other than VIC 1 use limited quantization range. */ 4836 return drm_match_cea_mode(mode) > 1 ? 4837 HDMI_QUANTIZATION_RANGE_LIMITED : 4838 HDMI_QUANTIZATION_RANGE_FULL; 4839 } 4840 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4841 4842 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4843 { 4844 struct drm_display_info *info = &connector->display_info; 4845 4846 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4847 4848 if (db[2] & EDID_CEA_VCDB_QS) 4849 info->rgb_quant_range_selectable = true; 4850 } 4851 4852 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4853 const u8 *db) 4854 { 4855 u8 dc_mask; 4856 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4857 4858 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4859 hdmi->y420_dc_modes = dc_mask; 4860 } 4861 4862 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4863 const u8 *hf_vsdb) 4864 { 4865 struct drm_display_info *display = &connector->display_info; 4866 struct drm_hdmi_info *hdmi = &display->hdmi; 4867 4868 display->has_hdmi_infoframe = true; 4869 4870 if (hf_vsdb[6] & 0x80) { 4871 hdmi->scdc.supported = true; 4872 if (hf_vsdb[6] & 0x40) 4873 hdmi->scdc.read_request = true; 4874 } 4875 4876 /* 4877 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4878 * And as per the spec, three factors confirm this: 4879 * * Availability of a HF-VSDB block in EDID (check) 4880 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4881 * * SCDC support available (let's check) 4882 * Lets check it out. 4883 */ 4884 4885 if (hf_vsdb[5]) { 4886 /* max clock is 5000 KHz times block value */ 4887 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4888 struct drm_scdc *scdc = &hdmi->scdc; 4889 4890 if (max_tmds_clock > 340000) { 4891 display->max_tmds_clock = max_tmds_clock; 4892 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4893 display->max_tmds_clock); 4894 } 4895 4896 if (scdc->supported) { 4897 scdc->scrambling.supported = true; 4898 4899 /* Few sinks support scrambling for clocks < 340M */ 4900 if ((hf_vsdb[6] & 0x8)) 4901 scdc->scrambling.low_rates = true; 4902 } 4903 } 4904 4905 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4906 } 4907 4908 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4909 const u8 *hdmi) 4910 { 4911 struct drm_display_info *info = &connector->display_info; 4912 unsigned int dc_bpc = 0; 4913 4914 /* HDMI supports at least 8 bpc */ 4915 info->bpc = 8; 4916 4917 if (cea_db_payload_len(hdmi) < 6) 4918 return; 4919 4920 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4921 dc_bpc = 10; 4922 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4923 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4924 connector->name); 4925 } 4926 4927 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4928 dc_bpc = 12; 4929 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4930 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4931 connector->name); 4932 } 4933 4934 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4935 dc_bpc = 16; 4936 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4937 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4938 connector->name); 4939 } 4940 4941 if (dc_bpc == 0) { 4942 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4943 connector->name); 4944 return; 4945 } 4946 4947 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4948 connector->name, dc_bpc); 4949 info->bpc = dc_bpc; 4950 4951 /* 4952 * Deep color support mandates RGB444 support for all video 4953 * modes and forbids YCRCB422 support for all video modes per 4954 * HDMI 1.3 spec. 4955 */ 4956 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4957 4958 /* YCRCB444 is optional according to spec. */ 4959 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4960 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4961 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4962 connector->name); 4963 } 4964 4965 /* 4966 * Spec says that if any deep color mode is supported at all, 4967 * then deep color 36 bit must be supported. 4968 */ 4969 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4970 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4971 connector->name); 4972 } 4973 } 4974 4975 static void 4976 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4977 { 4978 struct drm_display_info *info = &connector->display_info; 4979 u8 len = cea_db_payload_len(db); 4980 4981 info->is_hdmi = true; 4982 4983 if (len >= 6) 4984 info->dvi_dual = db[6] & 1; 4985 if (len >= 7) 4986 info->max_tmds_clock = db[7] * 5000; 4987 4988 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4989 "max TMDS clock %d kHz\n", 4990 info->dvi_dual, 4991 info->max_tmds_clock); 4992 4993 drm_parse_hdmi_deep_color_info(connector, db); 4994 } 4995 4996 static void drm_parse_cea_ext(struct drm_connector *connector, 4997 const struct edid *edid) 4998 { 4999 struct drm_display_info *info = &connector->display_info; 5000 const u8 *edid_ext; 5001 int i, start, end; 5002 5003 edid_ext = drm_find_cea_extension(edid); 5004 if (!edid_ext) 5005 return; 5006 5007 info->cea_rev = edid_ext[1]; 5008 5009 /* The existence of a CEA block should imply RGB support */ 5010 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5011 if (edid_ext[3] & EDID_CEA_YCRCB444) 5012 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5013 if (edid_ext[3] & EDID_CEA_YCRCB422) 5014 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5015 5016 if (cea_db_offsets(edid_ext, &start, &end)) 5017 return; 5018 5019 for_each_cea_db(edid_ext, i, start, end) { 5020 const u8 *db = &edid_ext[i]; 5021 5022 if (cea_db_is_hdmi_vsdb(db)) 5023 drm_parse_hdmi_vsdb_video(connector, db); 5024 if (cea_db_is_hdmi_forum_vsdb(db)) 5025 drm_parse_hdmi_forum_vsdb(connector, db); 5026 if (cea_db_is_y420cmdb(db)) 5027 drm_parse_y420cmdb_bitmap(connector, db); 5028 if (cea_db_is_vcdb(db)) 5029 drm_parse_vcdb(connector, db); 5030 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5031 drm_parse_hdr_metadata_block(connector, db); 5032 } 5033 } 5034 5035 static 5036 void get_monitor_range(struct detailed_timing *timing, 5037 void *info_monitor_range) 5038 { 5039 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5040 const struct detailed_non_pixel *data = &timing->data.other_data; 5041 const struct detailed_data_monitor_range *range = &data->data.range; 5042 5043 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 5044 return; 5045 5046 /* 5047 * Check for flag range limits only. If flag == 1 then 5048 * no additional timing information provided. 5049 * Default GTF, GTF Secondary curve and CVT are not 5050 * supported 5051 */ 5052 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5053 return; 5054 5055 monitor_range->min_vfreq = range->min_vfreq; 5056 monitor_range->max_vfreq = range->max_vfreq; 5057 } 5058 5059 static 5060 void drm_get_monitor_range(struct drm_connector *connector, 5061 const struct edid *edid) 5062 { 5063 struct drm_display_info *info = &connector->display_info; 5064 5065 if (!version_greater(edid, 1, 1)) 5066 return; 5067 5068 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 5069 &info->monitor_range); 5070 5071 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5072 info->monitor_range.min_vfreq, 5073 info->monitor_range.max_vfreq); 5074 } 5075 5076 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5077 * all of the values which would have been set from EDID 5078 */ 5079 void 5080 drm_reset_display_info(struct drm_connector *connector) 5081 { 5082 struct drm_display_info *info = &connector->display_info; 5083 5084 info->width_mm = 0; 5085 info->height_mm = 0; 5086 5087 info->bpc = 0; 5088 info->color_formats = 0; 5089 info->cea_rev = 0; 5090 info->max_tmds_clock = 0; 5091 info->dvi_dual = false; 5092 info->is_hdmi = false; 5093 info->has_hdmi_infoframe = false; 5094 info->rgb_quant_range_selectable = false; 5095 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5096 5097 info->non_desktop = 0; 5098 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5099 } 5100 5101 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5102 { 5103 struct drm_display_info *info = &connector->display_info; 5104 5105 u32 quirks = edid_get_quirks(edid); 5106 5107 drm_reset_display_info(connector); 5108 5109 info->width_mm = edid->width_cm * 10; 5110 info->height_mm = edid->height_cm * 10; 5111 5112 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5113 5114 drm_get_monitor_range(connector, edid); 5115 5116 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5117 5118 if (edid->revision < 3) 5119 return quirks; 5120 5121 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5122 return quirks; 5123 5124 drm_parse_cea_ext(connector, edid); 5125 5126 /* 5127 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5128 * 5129 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5130 * tells us to assume 8 bpc color depth if the EDID doesn't have 5131 * extensions which tell otherwise. 5132 */ 5133 if (info->bpc == 0 && edid->revision == 3 && 5134 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5135 info->bpc = 8; 5136 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5137 connector->name, info->bpc); 5138 } 5139 5140 /* Only defined for 1.4 with digital displays */ 5141 if (edid->revision < 4) 5142 return quirks; 5143 5144 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5145 case DRM_EDID_DIGITAL_DEPTH_6: 5146 info->bpc = 6; 5147 break; 5148 case DRM_EDID_DIGITAL_DEPTH_8: 5149 info->bpc = 8; 5150 break; 5151 case DRM_EDID_DIGITAL_DEPTH_10: 5152 info->bpc = 10; 5153 break; 5154 case DRM_EDID_DIGITAL_DEPTH_12: 5155 info->bpc = 12; 5156 break; 5157 case DRM_EDID_DIGITAL_DEPTH_14: 5158 info->bpc = 14; 5159 break; 5160 case DRM_EDID_DIGITAL_DEPTH_16: 5161 info->bpc = 16; 5162 break; 5163 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5164 default: 5165 info->bpc = 0; 5166 break; 5167 } 5168 5169 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5170 connector->name, info->bpc); 5171 5172 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5173 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5174 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5175 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5176 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5177 return quirks; 5178 } 5179 5180 static int validate_displayid(u8 *displayid, int length, int idx) 5181 { 5182 int i, dispid_length; 5183 u8 csum = 0; 5184 struct displayid_hdr *base; 5185 5186 base = (struct displayid_hdr *)&displayid[idx]; 5187 5188 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5189 base->rev, base->bytes, base->prod_id, base->ext_count); 5190 5191 /* +1 for DispID checksum */ 5192 dispid_length = sizeof(*base) + base->bytes + 1; 5193 if (dispid_length > length - idx) 5194 return -EINVAL; 5195 5196 for (i = 0; i < dispid_length; i++) 5197 csum += displayid[idx + i]; 5198 if (csum) { 5199 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5200 return -EINVAL; 5201 } 5202 5203 return 0; 5204 } 5205 5206 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5207 struct displayid_detailed_timings_1 *timings) 5208 { 5209 struct drm_display_mode *mode; 5210 unsigned pixel_clock = (timings->pixel_clock[0] | 5211 (timings->pixel_clock[1] << 8) | 5212 (timings->pixel_clock[2] << 16)) + 1; 5213 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5214 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5215 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5216 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5217 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5218 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5219 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5220 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5221 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5222 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5223 5224 mode = drm_mode_create(dev); 5225 if (!mode) 5226 return NULL; 5227 5228 mode->clock = pixel_clock * 10; 5229 mode->hdisplay = hactive; 5230 mode->hsync_start = mode->hdisplay + hsync; 5231 mode->hsync_end = mode->hsync_start + hsync_width; 5232 mode->htotal = mode->hdisplay + hblank; 5233 5234 mode->vdisplay = vactive; 5235 mode->vsync_start = mode->vdisplay + vsync; 5236 mode->vsync_end = mode->vsync_start + vsync_width; 5237 mode->vtotal = mode->vdisplay + vblank; 5238 5239 mode->flags = 0; 5240 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5241 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5242 mode->type = DRM_MODE_TYPE_DRIVER; 5243 5244 if (timings->flags & 0x80) 5245 mode->type |= DRM_MODE_TYPE_PREFERRED; 5246 drm_mode_set_name(mode); 5247 5248 return mode; 5249 } 5250 5251 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5252 struct displayid_block *block) 5253 { 5254 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5255 int i; 5256 int num_timings; 5257 struct drm_display_mode *newmode; 5258 int num_modes = 0; 5259 /* blocks must be multiple of 20 bytes length */ 5260 if (block->num_bytes % 20) 5261 return 0; 5262 5263 num_timings = block->num_bytes / 20; 5264 for (i = 0; i < num_timings; i++) { 5265 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5266 5267 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5268 if (!newmode) 5269 continue; 5270 5271 drm_mode_probed_add(connector, newmode); 5272 num_modes++; 5273 } 5274 return num_modes; 5275 } 5276 5277 static int add_displayid_detailed_modes(struct drm_connector *connector, 5278 struct edid *edid) 5279 { 5280 u8 *displayid; 5281 int length, idx; 5282 struct displayid_block *block; 5283 int num_modes = 0; 5284 int ext_index = 0; 5285 5286 for (;;) { 5287 displayid = drm_find_displayid_extension(edid, &length, &idx, 5288 &ext_index); 5289 if (!displayid) 5290 break; 5291 5292 idx += sizeof(struct displayid_hdr); 5293 for_each_displayid_db(displayid, block, idx, length) { 5294 switch (block->tag) { 5295 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5296 num_modes += add_displayid_detailed_1_modes(connector, block); 5297 break; 5298 } 5299 } 5300 } 5301 5302 return num_modes; 5303 } 5304 5305 /** 5306 * drm_add_edid_modes - add modes from EDID data, if available 5307 * @connector: connector we're probing 5308 * @edid: EDID data 5309 * 5310 * Add the specified modes to the connector's mode list. Also fills out the 5311 * &drm_display_info structure and ELD in @connector with any information which 5312 * can be derived from the edid. 5313 * 5314 * Return: The number of modes added or 0 if we couldn't find any. 5315 */ 5316 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5317 { 5318 int num_modes = 0; 5319 u32 quirks; 5320 5321 if (edid == NULL) { 5322 clear_eld(connector); 5323 return 0; 5324 } 5325 if (!drm_edid_is_valid(edid)) { 5326 clear_eld(connector); 5327 drm_warn(connector->dev, "%s: EDID invalid.\n", 5328 connector->name); 5329 return 0; 5330 } 5331 5332 drm_edid_to_eld(connector, edid); 5333 5334 /* 5335 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5336 * To avoid multiple parsing of same block, lets parse that map 5337 * from sink info, before parsing CEA modes. 5338 */ 5339 quirks = drm_add_display_info(connector, edid); 5340 5341 /* 5342 * EDID spec says modes should be preferred in this order: 5343 * - preferred detailed mode 5344 * - other detailed modes from base block 5345 * - detailed modes from extension blocks 5346 * - CVT 3-byte code modes 5347 * - standard timing codes 5348 * - established timing codes 5349 * - modes inferred from GTF or CVT range information 5350 * 5351 * We get this pretty much right. 5352 * 5353 * XXX order for additional mode types in extension blocks? 5354 */ 5355 num_modes += add_detailed_modes(connector, edid, quirks); 5356 num_modes += add_cvt_modes(connector, edid); 5357 num_modes += add_standard_modes(connector, edid); 5358 num_modes += add_established_modes(connector, edid); 5359 num_modes += add_cea_modes(connector, edid); 5360 num_modes += add_alternate_cea_modes(connector, edid); 5361 num_modes += add_displayid_detailed_modes(connector, edid); 5362 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5363 num_modes += add_inferred_modes(connector, edid); 5364 5365 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5366 edid_fixup_preferred(connector, quirks); 5367 5368 if (quirks & EDID_QUIRK_FORCE_6BPC) 5369 connector->display_info.bpc = 6; 5370 5371 if (quirks & EDID_QUIRK_FORCE_8BPC) 5372 connector->display_info.bpc = 8; 5373 5374 if (quirks & EDID_QUIRK_FORCE_10BPC) 5375 connector->display_info.bpc = 10; 5376 5377 if (quirks & EDID_QUIRK_FORCE_12BPC) 5378 connector->display_info.bpc = 12; 5379 5380 return num_modes; 5381 } 5382 EXPORT_SYMBOL(drm_add_edid_modes); 5383 5384 /** 5385 * drm_add_modes_noedid - add modes for the connectors without EDID 5386 * @connector: connector we're probing 5387 * @hdisplay: the horizontal display limit 5388 * @vdisplay: the vertical display limit 5389 * 5390 * Add the specified modes to the connector's mode list. Only when the 5391 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5392 * 5393 * Return: The number of modes added or 0 if we couldn't find any. 5394 */ 5395 int drm_add_modes_noedid(struct drm_connector *connector, 5396 int hdisplay, int vdisplay) 5397 { 5398 int i, count, num_modes = 0; 5399 struct drm_display_mode *mode; 5400 struct drm_device *dev = connector->dev; 5401 5402 count = ARRAY_SIZE(drm_dmt_modes); 5403 if (hdisplay < 0) 5404 hdisplay = 0; 5405 if (vdisplay < 0) 5406 vdisplay = 0; 5407 5408 for (i = 0; i < count; i++) { 5409 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5410 5411 if (hdisplay && vdisplay) { 5412 /* 5413 * Only when two are valid, they will be used to check 5414 * whether the mode should be added to the mode list of 5415 * the connector. 5416 */ 5417 if (ptr->hdisplay > hdisplay || 5418 ptr->vdisplay > vdisplay) 5419 continue; 5420 } 5421 if (drm_mode_vrefresh(ptr) > 61) 5422 continue; 5423 mode = drm_mode_duplicate(dev, ptr); 5424 if (mode) { 5425 drm_mode_probed_add(connector, mode); 5426 num_modes++; 5427 } 5428 } 5429 return num_modes; 5430 } 5431 EXPORT_SYMBOL(drm_add_modes_noedid); 5432 5433 /** 5434 * drm_set_preferred_mode - Sets the preferred mode of a connector 5435 * @connector: connector whose mode list should be processed 5436 * @hpref: horizontal resolution of preferred mode 5437 * @vpref: vertical resolution of preferred mode 5438 * 5439 * Marks a mode as preferred if it matches the resolution specified by @hpref 5440 * and @vpref. 5441 */ 5442 void drm_set_preferred_mode(struct drm_connector *connector, 5443 int hpref, int vpref) 5444 { 5445 struct drm_display_mode *mode; 5446 5447 list_for_each_entry(mode, &connector->probed_modes, head) { 5448 if (mode->hdisplay == hpref && 5449 mode->vdisplay == vpref) 5450 mode->type |= DRM_MODE_TYPE_PREFERRED; 5451 } 5452 } 5453 EXPORT_SYMBOL(drm_set_preferred_mode); 5454 5455 static bool is_hdmi2_sink(const struct drm_connector *connector) 5456 { 5457 /* 5458 * FIXME: sil-sii8620 doesn't have a connector around when 5459 * we need one, so we have to be prepared for a NULL connector. 5460 */ 5461 if (!connector) 5462 return true; 5463 5464 return connector->display_info.hdmi.scdc.supported || 5465 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5466 } 5467 5468 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5469 { 5470 return sink_eotf & BIT(output_eotf); 5471 } 5472 5473 /** 5474 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5475 * HDR metadata from userspace 5476 * @frame: HDMI DRM infoframe 5477 * @conn_state: Connector state containing HDR metadata 5478 * 5479 * Return: 0 on success or a negative error code on failure. 5480 */ 5481 int 5482 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5483 const struct drm_connector_state *conn_state) 5484 { 5485 struct drm_connector *connector; 5486 struct hdr_output_metadata *hdr_metadata; 5487 int err; 5488 5489 if (!frame || !conn_state) 5490 return -EINVAL; 5491 5492 connector = conn_state->connector; 5493 5494 if (!conn_state->hdr_output_metadata) 5495 return -EINVAL; 5496 5497 hdr_metadata = conn_state->hdr_output_metadata->data; 5498 5499 if (!hdr_metadata || !connector) 5500 return -EINVAL; 5501 5502 /* Sink EOTF is Bit map while infoframe is absolute values */ 5503 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5504 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5505 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5506 return -EINVAL; 5507 } 5508 5509 err = hdmi_drm_infoframe_init(frame); 5510 if (err < 0) 5511 return err; 5512 5513 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5514 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5515 5516 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5517 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5518 BUILD_BUG_ON(sizeof(frame->white_point) != 5519 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5520 5521 memcpy(&frame->display_primaries, 5522 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5523 sizeof(frame->display_primaries)); 5524 5525 memcpy(&frame->white_point, 5526 &hdr_metadata->hdmi_metadata_type1.white_point, 5527 sizeof(frame->white_point)); 5528 5529 frame->max_display_mastering_luminance = 5530 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5531 frame->min_display_mastering_luminance = 5532 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5533 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5534 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5535 5536 return 0; 5537 } 5538 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5539 5540 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5541 const struct drm_display_mode *mode) 5542 { 5543 bool has_hdmi_infoframe = connector ? 5544 connector->display_info.has_hdmi_infoframe : false; 5545 5546 if (!has_hdmi_infoframe) 5547 return 0; 5548 5549 /* No HDMI VIC when signalling 3D video format */ 5550 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5551 return 0; 5552 5553 return drm_match_hdmi_mode(mode); 5554 } 5555 5556 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5557 const struct drm_display_mode *mode) 5558 { 5559 u8 vic; 5560 5561 /* 5562 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5563 * we should send its VIC in vendor infoframes, else send the 5564 * VIC in AVI infoframes. Lets check if this mode is present in 5565 * HDMI 1.4b 4K modes 5566 */ 5567 if (drm_mode_hdmi_vic(connector, mode)) 5568 return 0; 5569 5570 vic = drm_match_cea_mode(mode); 5571 5572 /* 5573 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5574 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5575 * have to make sure we dont break HDMI 1.4 sinks. 5576 */ 5577 if (!is_hdmi2_sink(connector) && vic > 64) 5578 return 0; 5579 5580 return vic; 5581 } 5582 5583 /** 5584 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5585 * data from a DRM display mode 5586 * @frame: HDMI AVI infoframe 5587 * @connector: the connector 5588 * @mode: DRM display mode 5589 * 5590 * Return: 0 on success or a negative error code on failure. 5591 */ 5592 int 5593 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5594 const struct drm_connector *connector, 5595 const struct drm_display_mode *mode) 5596 { 5597 enum hdmi_picture_aspect picture_aspect; 5598 u8 vic, hdmi_vic; 5599 5600 if (!frame || !mode) 5601 return -EINVAL; 5602 5603 hdmi_avi_infoframe_init(frame); 5604 5605 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5606 frame->pixel_repeat = 1; 5607 5608 vic = drm_mode_cea_vic(connector, mode); 5609 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5610 5611 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5612 5613 /* 5614 * As some drivers don't support atomic, we can't use connector state. 5615 * So just initialize the frame with default values, just the same way 5616 * as it's done with other properties here. 5617 */ 5618 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5619 frame->itc = 0; 5620 5621 /* 5622 * Populate picture aspect ratio from either 5623 * user input (if specified) or from the CEA/HDMI mode lists. 5624 */ 5625 picture_aspect = mode->picture_aspect_ratio; 5626 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5627 if (vic) 5628 picture_aspect = drm_get_cea_aspect_ratio(vic); 5629 else if (hdmi_vic) 5630 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5631 } 5632 5633 /* 5634 * The infoframe can't convey anything but none, 4:3 5635 * and 16:9, so if the user has asked for anything else 5636 * we can only satisfy it by specifying the right VIC. 5637 */ 5638 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5639 if (vic) { 5640 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5641 return -EINVAL; 5642 } else if (hdmi_vic) { 5643 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5644 return -EINVAL; 5645 } else { 5646 return -EINVAL; 5647 } 5648 5649 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5650 } 5651 5652 frame->video_code = vic; 5653 frame->picture_aspect = picture_aspect; 5654 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5655 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5656 5657 return 0; 5658 } 5659 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5660 5661 /* HDMI Colorspace Spec Definitions */ 5662 #define FULL_COLORIMETRY_MASK 0x1FF 5663 #define NORMAL_COLORIMETRY_MASK 0x3 5664 #define EXTENDED_COLORIMETRY_MASK 0x7 5665 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5666 5667 #define C(x) ((x) << 0) 5668 #define EC(x) ((x) << 2) 5669 #define ACE(x) ((x) << 5) 5670 5671 #define HDMI_COLORIMETRY_NO_DATA 0x0 5672 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5673 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5674 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5675 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5676 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5677 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5678 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5679 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5680 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5681 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5682 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5683 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5684 5685 static const u32 hdmi_colorimetry_val[] = { 5686 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5687 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5688 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5689 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5690 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5691 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5692 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5693 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5694 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5695 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5696 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5697 }; 5698 5699 #undef C 5700 #undef EC 5701 #undef ACE 5702 5703 /** 5704 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5705 * colorspace information 5706 * @frame: HDMI AVI infoframe 5707 * @conn_state: connector state 5708 */ 5709 void 5710 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5711 const struct drm_connector_state *conn_state) 5712 { 5713 u32 colorimetry_val; 5714 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5715 5716 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5717 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5718 else 5719 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5720 5721 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5722 /* 5723 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5724 * structure and extend it in drivers/video/hdmi 5725 */ 5726 frame->extended_colorimetry = (colorimetry_val >> 2) & 5727 EXTENDED_COLORIMETRY_MASK; 5728 } 5729 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5730 5731 /** 5732 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5733 * quantization range information 5734 * @frame: HDMI AVI infoframe 5735 * @connector: the connector 5736 * @mode: DRM display mode 5737 * @rgb_quant_range: RGB quantization range (Q) 5738 */ 5739 void 5740 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5741 const struct drm_connector *connector, 5742 const struct drm_display_mode *mode, 5743 enum hdmi_quantization_range rgb_quant_range) 5744 { 5745 const struct drm_display_info *info = &connector->display_info; 5746 5747 /* 5748 * CEA-861: 5749 * "A Source shall not send a non-zero Q value that does not correspond 5750 * to the default RGB Quantization Range for the transmitted Picture 5751 * unless the Sink indicates support for the Q bit in a Video 5752 * Capabilities Data Block." 5753 * 5754 * HDMI 2.0 recommends sending non-zero Q when it does match the 5755 * default RGB quantization range for the mode, even when QS=0. 5756 */ 5757 if (info->rgb_quant_range_selectable || 5758 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5759 frame->quantization_range = rgb_quant_range; 5760 else 5761 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5762 5763 /* 5764 * CEA-861-F: 5765 * "When transmitting any RGB colorimetry, the Source should set the 5766 * YQ-field to match the RGB Quantization Range being transmitted 5767 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5768 * set YQ=1) and the Sink shall ignore the YQ-field." 5769 * 5770 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5771 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5772 * good way to tell which version of CEA-861 the sink supports, so 5773 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5774 * on on CEA-861-F. 5775 */ 5776 if (!is_hdmi2_sink(connector) || 5777 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5778 frame->ycc_quantization_range = 5779 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5780 else 5781 frame->ycc_quantization_range = 5782 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5783 } 5784 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5785 5786 /** 5787 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5788 * bar information 5789 * @frame: HDMI AVI infoframe 5790 * @conn_state: connector state 5791 */ 5792 void 5793 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5794 const struct drm_connector_state *conn_state) 5795 { 5796 frame->right_bar = conn_state->tv.margins.right; 5797 frame->left_bar = conn_state->tv.margins.left; 5798 frame->top_bar = conn_state->tv.margins.top; 5799 frame->bottom_bar = conn_state->tv.margins.bottom; 5800 } 5801 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5802 5803 static enum hdmi_3d_structure 5804 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5805 { 5806 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5807 5808 switch (layout) { 5809 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5810 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5811 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5812 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5813 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5814 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5815 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5816 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5817 case DRM_MODE_FLAG_3D_L_DEPTH: 5818 return HDMI_3D_STRUCTURE_L_DEPTH; 5819 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5820 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5821 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5822 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5823 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5824 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5825 default: 5826 return HDMI_3D_STRUCTURE_INVALID; 5827 } 5828 } 5829 5830 /** 5831 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5832 * data from a DRM display mode 5833 * @frame: HDMI vendor infoframe 5834 * @connector: the connector 5835 * @mode: DRM display mode 5836 * 5837 * Note that there's is a need to send HDMI vendor infoframes only when using a 5838 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5839 * function will return -EINVAL, error that can be safely ignored. 5840 * 5841 * Return: 0 on success or a negative error code on failure. 5842 */ 5843 int 5844 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5845 const struct drm_connector *connector, 5846 const struct drm_display_mode *mode) 5847 { 5848 /* 5849 * FIXME: sil-sii8620 doesn't have a connector around when 5850 * we need one, so we have to be prepared for a NULL connector. 5851 */ 5852 bool has_hdmi_infoframe = connector ? 5853 connector->display_info.has_hdmi_infoframe : false; 5854 int err; 5855 5856 if (!frame || !mode) 5857 return -EINVAL; 5858 5859 if (!has_hdmi_infoframe) 5860 return -EINVAL; 5861 5862 err = hdmi_vendor_infoframe_init(frame); 5863 if (err < 0) 5864 return err; 5865 5866 /* 5867 * Even if it's not absolutely necessary to send the infoframe 5868 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5869 * know that the sink can handle it. This is based on a 5870 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5871 * have trouble realizing that they shuld switch from 3D to 2D 5872 * mode if the source simply stops sending the infoframe when 5873 * it wants to switch from 3D to 2D. 5874 */ 5875 frame->vic = drm_mode_hdmi_vic(connector, mode); 5876 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5877 5878 return 0; 5879 } 5880 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5881 5882 static void drm_parse_tiled_block(struct drm_connector *connector, 5883 const struct displayid_block *block) 5884 { 5885 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5886 u16 w, h; 5887 u8 tile_v_loc, tile_h_loc; 5888 u8 num_v_tile, num_h_tile; 5889 struct drm_tile_group *tg; 5890 5891 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5892 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5893 5894 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5895 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5896 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5897 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5898 5899 connector->has_tile = true; 5900 if (tile->tile_cap & 0x80) 5901 connector->tile_is_single_monitor = true; 5902 5903 connector->num_h_tile = num_h_tile + 1; 5904 connector->num_v_tile = num_v_tile + 1; 5905 connector->tile_h_loc = tile_h_loc; 5906 connector->tile_v_loc = tile_v_loc; 5907 connector->tile_h_size = w + 1; 5908 connector->tile_v_size = h + 1; 5909 5910 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5911 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5912 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5913 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5914 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5915 5916 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5917 if (!tg) 5918 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5919 if (!tg) 5920 return; 5921 5922 if (connector->tile_group != tg) { 5923 /* if we haven't got a pointer, 5924 take the reference, drop ref to old tile group */ 5925 if (connector->tile_group) 5926 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5927 connector->tile_group = tg; 5928 } else { 5929 /* if same tile group, then release the ref we just took. */ 5930 drm_mode_put_tile_group(connector->dev, tg); 5931 } 5932 } 5933 5934 static void drm_displayid_parse_tiled(struct drm_connector *connector, 5935 const u8 *displayid, int length, int idx) 5936 { 5937 const struct displayid_block *block; 5938 5939 idx += sizeof(struct displayid_hdr); 5940 for_each_displayid_db(displayid, block, idx, length) { 5941 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5942 block->tag, block->rev, block->num_bytes); 5943 5944 switch (block->tag) { 5945 case DATA_BLOCK_TILED_DISPLAY: 5946 drm_parse_tiled_block(connector, block); 5947 break; 5948 default: 5949 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5950 break; 5951 } 5952 } 5953 } 5954 5955 void drm_update_tile_info(struct drm_connector *connector, 5956 const struct edid *edid) 5957 { 5958 const void *displayid = NULL; 5959 int ext_index = 0; 5960 int length, idx; 5961 5962 connector->has_tile = false; 5963 for (;;) { 5964 displayid = drm_find_displayid_extension(edid, &length, &idx, 5965 &ext_index); 5966 if (!displayid) 5967 break; 5968 5969 drm_displayid_parse_tiled(connector, displayid, length, idx); 5970 } 5971 5972 if (!connector->has_tile && connector->tile_group) { 5973 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5974 connector->tile_group = NULL; 5975 } 5976 } 5977