1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <drm/drmP.h> 36 #include <drm/drm_edid.h> 37 38 #define version_greater(edid, maj, min) \ 39 (((edid)->version > (maj)) || \ 40 ((edid)->version == (maj) && (edid)->revision > (min))) 41 42 #define EDID_EST_TIMINGS 16 43 #define EDID_STD_TIMINGS 8 44 #define EDID_DETAILED_TIMINGS 4 45 46 /* 47 * EDID blocks out in the wild have a variety of bugs, try to collect 48 * them here (note that userspace may work around broken monitors first, 49 * but fixes should make their way here so that the kernel "just works" 50 * on as many displays as possible). 51 */ 52 53 /* First detailed mode wrong, use largest 60Hz mode */ 54 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 55 /* Reported 135MHz pixel clock is too high, needs adjustment */ 56 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 57 /* Prefer the largest mode at 75 Hz */ 58 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 59 /* Detail timing is in cm not mm */ 60 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 61 /* Detailed timing descriptors have bogus size values, so just take the 62 * maximum size and use that. 63 */ 64 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 65 /* Monitor forgot to set the first detailed is preferred bit. */ 66 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 67 /* use +hsync +vsync for detailed mode */ 68 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 69 /* Force reduced-blanking timings for detailed modes */ 70 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 71 /* Force 8bpc */ 72 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 73 /* Force 12bpc */ 74 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 75 76 struct detailed_mode_closure { 77 struct drm_connector *connector; 78 struct edid *edid; 79 bool preferred; 80 u32 quirks; 81 int modes; 82 }; 83 84 #define LEVEL_DMT 0 85 #define LEVEL_GTF 1 86 #define LEVEL_GTF2 2 87 #define LEVEL_CVT 3 88 89 static struct edid_quirk { 90 char vendor[4]; 91 int product_id; 92 u32 quirks; 93 } edid_quirk_list[] = { 94 /* Acer AL1706 */ 95 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Acer F51 */ 97 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 98 /* Unknown Acer */ 99 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 100 101 /* Belinea 10 15 55 */ 102 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 103 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 104 105 /* Envision Peripherals, Inc. EN-7100e */ 106 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 107 /* Envision EN2028 */ 108 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 109 110 /* Funai Electronics PM36B */ 111 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 112 EDID_QUIRK_DETAILED_IN_CM }, 113 114 /* LG Philips LCD LP154W01-A5 */ 115 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 116 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 117 118 /* Philips 107p5 CRT */ 119 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 120 121 /* Proview AY765C */ 122 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 123 124 /* Samsung SyncMaster 205BW. Note: irony */ 125 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 126 /* Samsung SyncMaster 22[5-6]BW */ 127 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 128 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 129 130 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 131 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 132 133 /* ViewSonic VA2026w */ 134 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 135 136 /* Medion MD 30217 PG */ 137 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 138 139 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 140 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 141 }; 142 143 /* 144 * Autogenerated from the DMT spec. 145 * This table is copied from xfree86/modes/xf86EdidModes.c. 146 */ 147 static const struct drm_display_mode drm_dmt_modes[] = { 148 /* 640x350@85Hz */ 149 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 150 736, 832, 0, 350, 382, 385, 445, 0, 151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 152 /* 640x400@85Hz */ 153 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 154 736, 832, 0, 400, 401, 404, 445, 0, 155 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 156 /* 720x400@85Hz */ 157 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 158 828, 936, 0, 400, 401, 404, 446, 0, 159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 160 /* 640x480@60Hz */ 161 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 162 752, 800, 0, 480, 489, 492, 525, 0, 163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 164 /* 640x480@72Hz */ 165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 166 704, 832, 0, 480, 489, 492, 520, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 168 /* 640x480@75Hz */ 169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 170 720, 840, 0, 480, 481, 484, 500, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 172 /* 640x480@85Hz */ 173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 174 752, 832, 0, 480, 481, 484, 509, 0, 175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 800x600@56Hz */ 177 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 178 896, 1024, 0, 600, 601, 603, 625, 0, 179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 180 /* 800x600@60Hz */ 181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 182 968, 1056, 0, 600, 601, 605, 628, 0, 183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 184 /* 800x600@72Hz */ 185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 186 976, 1040, 0, 600, 637, 643, 666, 0, 187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 188 /* 800x600@75Hz */ 189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 190 896, 1056, 0, 600, 601, 604, 625, 0, 191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 192 /* 800x600@85Hz */ 193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 194 896, 1048, 0, 600, 601, 604, 631, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 196 /* 800x600@120Hz RB */ 197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 198 880, 960, 0, 600, 603, 607, 636, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 200 /* 848x480@60Hz */ 201 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 202 976, 1088, 0, 480, 486, 494, 517, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 204 /* 1024x768@43Hz, interlace */ 205 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 206 1208, 1264, 0, 768, 768, 772, 817, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 208 DRM_MODE_FLAG_INTERLACE) }, 209 /* 1024x768@60Hz */ 210 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 211 1184, 1344, 0, 768, 771, 777, 806, 0, 212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 213 /* 1024x768@70Hz */ 214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 215 1184, 1328, 0, 768, 771, 777, 806, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 217 /* 1024x768@75Hz */ 218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 219 1136, 1312, 0, 768, 769, 772, 800, 0, 220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 221 /* 1024x768@85Hz */ 222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 223 1168, 1376, 0, 768, 769, 772, 808, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 225 /* 1024x768@120Hz RB */ 226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 227 1104, 1184, 0, 768, 771, 775, 813, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 1152x864@75Hz */ 230 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 231 1344, 1600, 0, 864, 865, 868, 900, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 1280x768@60Hz RB */ 234 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 235 1360, 1440, 0, 768, 771, 778, 790, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 1280x768@60Hz */ 238 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 239 1472, 1664, 0, 768, 771, 778, 798, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 1280x768@75Hz */ 242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 243 1488, 1696, 0, 768, 771, 778, 805, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 1280x768@85Hz */ 246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 247 1496, 1712, 0, 768, 771, 778, 809, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 1280x768@120Hz RB */ 250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 251 1360, 1440, 0, 768, 771, 778, 813, 0, 252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 1280x800@60Hz RB */ 254 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 255 1360, 1440, 0, 800, 803, 809, 823, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 1280x800@60Hz */ 258 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 259 1480, 1680, 0, 800, 803, 809, 831, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 1280x800@75Hz */ 262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 263 1488, 1696, 0, 800, 803, 809, 838, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 1280x800@85Hz */ 266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 267 1496, 1712, 0, 800, 803, 809, 843, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 1280x800@120Hz RB */ 270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 271 1360, 1440, 0, 800, 803, 809, 847, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 273 /* 1280x960@60Hz */ 274 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 275 1488, 1800, 0, 960, 961, 964, 1000, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 1280x960@85Hz */ 278 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 279 1504, 1728, 0, 960, 961, 964, 1011, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 1280x960@120Hz RB */ 282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 283 1360, 1440, 0, 960, 963, 967, 1017, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 285 /* 1280x1024@60Hz */ 286 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 287 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 1280x1024@75Hz */ 290 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 291 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 293 /* 1280x1024@85Hz */ 294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 295 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 1280x1024@120Hz RB */ 298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 299 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 301 /* 1360x768@60Hz */ 302 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 303 1536, 1792, 0, 768, 771, 777, 795, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 1360x768@120Hz RB */ 306 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 307 1440, 1520, 0, 768, 771, 776, 813, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 1400x1050@60Hz RB */ 310 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 311 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 1400x1050@60Hz */ 314 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 315 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 1400x1050@75Hz */ 318 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 319 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 1400x1050@85Hz */ 322 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 323 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 1400x1050@120Hz RB */ 326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 327 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 329 /* 1440x900@60Hz RB */ 330 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 331 1520, 1600, 0, 900, 903, 909, 926, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 1440x900@60Hz */ 334 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 335 1672, 1904, 0, 900, 903, 909, 934, 0, 336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 1440x900@75Hz */ 338 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 339 1688, 1936, 0, 900, 903, 909, 942, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 1440x900@85Hz */ 342 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 343 1696, 1952, 0, 900, 903, 909, 948, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 1440x900@120Hz RB */ 346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 347 1520, 1600, 0, 900, 903, 909, 953, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 1600x1200@60Hz */ 350 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 351 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 1600x1200@65Hz */ 354 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 355 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 1600x1200@70Hz */ 358 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 359 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 1600x1200@75Hz */ 362 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 363 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 1600x1200@85Hz */ 366 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 367 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 1600x1200@120Hz RB */ 370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 371 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 373 /* 1680x1050@60Hz RB */ 374 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 375 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 377 /* 1680x1050@60Hz */ 378 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 379 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 1680x1050@75Hz */ 382 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 383 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 1680x1050@85Hz */ 386 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 387 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 1680x1050@120Hz RB */ 390 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 391 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 393 /* 1792x1344@60Hz */ 394 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 395 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 396 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 1792x1344@75Hz */ 398 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 399 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 1792x1344@120Hz RB */ 402 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 403 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 405 /* 1856x1392@60Hz */ 406 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 407 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 1856x1392@75Hz */ 410 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 411 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 1856x1392@120Hz RB */ 414 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 415 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 1920x1200@60Hz RB */ 418 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 419 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 1920x1200@60Hz */ 422 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 423 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 1920x1200@75Hz */ 426 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 427 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 1920x1200@85Hz */ 430 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 431 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 1920x1200@120Hz RB */ 434 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 435 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 1920x1440@60Hz */ 438 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 439 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 1920x1440@75Hz */ 442 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 443 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 1920x1440@120Hz RB */ 446 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 447 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 449 /* 2560x1600@60Hz RB */ 450 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 451 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 453 /* 2560x1600@60Hz */ 454 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 455 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 2560x1600@75HZ */ 458 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 459 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 2560x1600@85HZ */ 462 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 463 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 2560x1600@120Hz RB */ 466 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 467 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 }; 470 471 /* 472 * These more or less come from the DMT spec. The 720x400 modes are 473 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 474 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 475 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 476 * mode. 477 * 478 * The DMT modes have been fact-checked; the rest are mild guesses. 479 */ 480 static const struct drm_display_mode edid_est_modes[] = { 481 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 482 968, 1056, 0, 600, 601, 605, 628, 0, 483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 484 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 485 896, 1024, 0, 600, 601, 603, 625, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 487 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 488 720, 840, 0, 480, 481, 484, 500, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 490 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 491 704, 832, 0, 480, 489, 491, 520, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 493 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 494 768, 864, 0, 480, 483, 486, 525, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 496 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 497 752, 800, 0, 480, 490, 492, 525, 0, 498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 499 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 500 846, 900, 0, 400, 421, 423, 449, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 502 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 503 846, 900, 0, 400, 412, 414, 449, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 505 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 506 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 508 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 509 1136, 1312, 0, 768, 769, 772, 800, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 511 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 512 1184, 1328, 0, 768, 771, 777, 806, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 514 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 515 1184, 1344, 0, 768, 771, 777, 806, 0, 516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 517 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 518 1208, 1264, 0, 768, 768, 776, 817, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 520 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 521 928, 1152, 0, 624, 625, 628, 667, 0, 522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 523 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 524 896, 1056, 0, 600, 601, 604, 625, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 527 976, 1040, 0, 600, 637, 643, 666, 0, 528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 529 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 530 1344, 1600, 0, 864, 865, 868, 900, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 532 }; 533 534 struct minimode { 535 short w; 536 short h; 537 short r; 538 short rb; 539 }; 540 541 static const struct minimode est3_modes[] = { 542 /* byte 6 */ 543 { 640, 350, 85, 0 }, 544 { 640, 400, 85, 0 }, 545 { 720, 400, 85, 0 }, 546 { 640, 480, 85, 0 }, 547 { 848, 480, 60, 0 }, 548 { 800, 600, 85, 0 }, 549 { 1024, 768, 85, 0 }, 550 { 1152, 864, 75, 0 }, 551 /* byte 7 */ 552 { 1280, 768, 60, 1 }, 553 { 1280, 768, 60, 0 }, 554 { 1280, 768, 75, 0 }, 555 { 1280, 768, 85, 0 }, 556 { 1280, 960, 60, 0 }, 557 { 1280, 960, 85, 0 }, 558 { 1280, 1024, 60, 0 }, 559 { 1280, 1024, 85, 0 }, 560 /* byte 8 */ 561 { 1360, 768, 60, 0 }, 562 { 1440, 900, 60, 1 }, 563 { 1440, 900, 60, 0 }, 564 { 1440, 900, 75, 0 }, 565 { 1440, 900, 85, 0 }, 566 { 1400, 1050, 60, 1 }, 567 { 1400, 1050, 60, 0 }, 568 { 1400, 1050, 75, 0 }, 569 /* byte 9 */ 570 { 1400, 1050, 85, 0 }, 571 { 1680, 1050, 60, 1 }, 572 { 1680, 1050, 60, 0 }, 573 { 1680, 1050, 75, 0 }, 574 { 1680, 1050, 85, 0 }, 575 { 1600, 1200, 60, 0 }, 576 { 1600, 1200, 65, 0 }, 577 { 1600, 1200, 70, 0 }, 578 /* byte 10 */ 579 { 1600, 1200, 75, 0 }, 580 { 1600, 1200, 85, 0 }, 581 { 1792, 1344, 60, 0 }, 582 { 1792, 1344, 75, 0 }, 583 { 1856, 1392, 60, 0 }, 584 { 1856, 1392, 75, 0 }, 585 { 1920, 1200, 60, 1 }, 586 { 1920, 1200, 60, 0 }, 587 /* byte 11 */ 588 { 1920, 1200, 75, 0 }, 589 { 1920, 1200, 85, 0 }, 590 { 1920, 1440, 60, 0 }, 591 { 1920, 1440, 75, 0 }, 592 }; 593 594 static const struct minimode extra_modes[] = { 595 { 1024, 576, 60, 0 }, 596 { 1366, 768, 60, 0 }, 597 { 1600, 900, 60, 0 }, 598 { 1680, 945, 60, 0 }, 599 { 1920, 1080, 60, 0 }, 600 { 2048, 1152, 60, 0 }, 601 { 2048, 1536, 60, 0 }, 602 }; 603 604 /* 605 * Probably taken from CEA-861 spec. 606 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 607 */ 608 static const struct drm_display_mode edid_cea_modes[] = { 609 /* 1 - 640x480@60Hz */ 610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 611 752, 800, 0, 480, 490, 492, 525, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 613 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 614 /* 2 - 720x480@60Hz */ 615 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 616 798, 858, 0, 480, 489, 495, 525, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 618 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 619 /* 3 - 720x480@60Hz */ 620 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 621 798, 858, 0, 480, 489, 495, 525, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 623 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 624 /* 4 - 1280x720@60Hz */ 625 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 626 1430, 1650, 0, 720, 725, 730, 750, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 628 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 629 /* 5 - 1920x1080i@60Hz */ 630 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 631 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 633 DRM_MODE_FLAG_INTERLACE), 634 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 635 /* 6 - 720(1440)x480i@60Hz */ 636 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 637 801, 858, 0, 480, 488, 494, 525, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 639 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 640 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 641 /* 7 - 720(1440)x480i@60Hz */ 642 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 643 801, 858, 0, 480, 488, 494, 525, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 645 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 646 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 647 /* 8 - 720(1440)x240@60Hz */ 648 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 649 801, 858, 0, 240, 244, 247, 262, 0, 650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 651 DRM_MODE_FLAG_DBLCLK), 652 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 653 /* 9 - 720(1440)x240@60Hz */ 654 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 655 801, 858, 0, 240, 244, 247, 262, 0, 656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 657 DRM_MODE_FLAG_DBLCLK), 658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 659 /* 10 - 2880x480i@60Hz */ 660 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 661 3204, 3432, 0, 480, 488, 494, 525, 0, 662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 663 DRM_MODE_FLAG_INTERLACE), 664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 665 /* 11 - 2880x480i@60Hz */ 666 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 667 3204, 3432, 0, 480, 488, 494, 525, 0, 668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 669 DRM_MODE_FLAG_INTERLACE), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 12 - 2880x240@60Hz */ 672 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 673 3204, 3432, 0, 240, 244, 247, 262, 0, 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 675 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 676 /* 13 - 2880x240@60Hz */ 677 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 678 3204, 3432, 0, 240, 244, 247, 262, 0, 679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 681 /* 14 - 1440x480@60Hz */ 682 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 683 1596, 1716, 0, 480, 489, 495, 525, 0, 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 686 /* 15 - 1440x480@60Hz */ 687 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 688 1596, 1716, 0, 480, 489, 495, 525, 0, 689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 691 /* 16 - 1920x1080@60Hz */ 692 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 693 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 696 /* 17 - 720x576@50Hz */ 697 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 698 796, 864, 0, 576, 581, 586, 625, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 700 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 701 /* 18 - 720x576@50Hz */ 702 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 703 796, 864, 0, 576, 581, 586, 625, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 705 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 706 /* 19 - 1280x720@50Hz */ 707 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 708 1760, 1980, 0, 720, 725, 730, 750, 0, 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 710 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 711 /* 20 - 1920x1080i@50Hz */ 712 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 713 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 715 DRM_MODE_FLAG_INTERLACE), 716 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 717 /* 21 - 720(1440)x576i@50Hz */ 718 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 719 795, 864, 0, 576, 580, 586, 625, 0, 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 721 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 722 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 22 - 720(1440)x576i@50Hz */ 724 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 725 795, 864, 0, 576, 580, 586, 625, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 727 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 728 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 729 /* 23 - 720(1440)x288@50Hz */ 730 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 731 795, 864, 0, 288, 290, 293, 312, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 733 DRM_MODE_FLAG_DBLCLK), 734 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 735 /* 24 - 720(1440)x288@50Hz */ 736 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 737 795, 864, 0, 288, 290, 293, 312, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 739 DRM_MODE_FLAG_DBLCLK), 740 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 25 - 2880x576i@50Hz */ 742 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 743 3180, 3456, 0, 576, 580, 586, 625, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 745 DRM_MODE_FLAG_INTERLACE), 746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 747 /* 26 - 2880x576i@50Hz */ 748 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 749 3180, 3456, 0, 576, 580, 586, 625, 0, 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 27 - 2880x288@50Hz */ 754 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 755 3180, 3456, 0, 288, 290, 293, 312, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 757 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 758 /* 28 - 2880x288@50Hz */ 759 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 760 3180, 3456, 0, 288, 290, 293, 312, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 763 /* 29 - 1440x576@50Hz */ 764 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 765 1592, 1728, 0, 576, 581, 586, 625, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 768 /* 30 - 1440x576@50Hz */ 769 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 770 1592, 1728, 0, 576, 581, 586, 625, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 31 - 1920x1080@50Hz */ 774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 775 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 32 - 1920x1080@24Hz */ 779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 780 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 782 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 783 /* 33 - 1920x1080@25Hz */ 784 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 785 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 787 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 34 - 1920x1080@30Hz */ 789 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 790 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 792 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 35 - 2880x480@60Hz */ 794 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 795 3192, 3432, 0, 480, 489, 495, 525, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 36 - 2880x480@60Hz */ 799 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 800 3192, 3432, 0, 480, 489, 495, 525, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 803 /* 37 - 2880x576@50Hz */ 804 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 805 3184, 3456, 0, 576, 581, 586, 625, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 808 /* 38 - 2880x576@50Hz */ 809 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 810 3184, 3456, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 39 - 1920x1080i@50Hz */ 814 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 815 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 817 DRM_MODE_FLAG_INTERLACE), 818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 819 /* 40 - 1920x1080i@100Hz */ 820 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 821 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 823 DRM_MODE_FLAG_INTERLACE), 824 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 41 - 1280x720@100Hz */ 826 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 827 1760, 1980, 0, 720, 725, 730, 750, 0, 828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 829 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 830 /* 42 - 720x576@100Hz */ 831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 832 796, 864, 0, 576, 581, 586, 625, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 834 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 835 /* 43 - 720x576@100Hz */ 836 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 837 796, 864, 0, 576, 581, 586, 625, 0, 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 839 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 44 - 720(1440)x576i@100Hz */ 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 842 795, 864, 0, 576, 580, 586, 625, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 845 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 846 /* 45 - 720(1440)x576i@100Hz */ 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 848 795, 864, 0, 576, 580, 586, 625, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 851 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 852 /* 46 - 1920x1080i@120Hz */ 853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 854 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 856 DRM_MODE_FLAG_INTERLACE), 857 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 47 - 1280x720@120Hz */ 859 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 860 1430, 1650, 0, 720, 725, 730, 750, 0, 861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 862 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 48 - 720x480@120Hz */ 864 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 865 798, 858, 0, 480, 489, 495, 525, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 49 - 720x480@120Hz */ 869 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 870 798, 858, 0, 480, 489, 495, 525, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 50 - 720(1440)x480i@120Hz */ 874 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 875 801, 858, 0, 480, 488, 494, 525, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 878 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 879 /* 51 - 720(1440)x480i@120Hz */ 880 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 881 801, 858, 0, 480, 488, 494, 525, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 883 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 884 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 52 - 720x576@200Hz */ 886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 887 796, 864, 0, 576, 581, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 53 - 720x576@200Hz */ 891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 892 796, 864, 0, 576, 581, 586, 625, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 54 - 720(1440)x576i@200Hz */ 896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 897 795, 864, 0, 576, 580, 586, 625, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 900 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 901 /* 55 - 720(1440)x576i@200Hz */ 902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 903 795, 864, 0, 576, 580, 586, 625, 0, 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 906 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 56 - 720x480@240Hz */ 908 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 909 798, 858, 0, 480, 489, 495, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 911 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 912 /* 57 - 720x480@240Hz */ 913 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 914 798, 858, 0, 480, 489, 495, 525, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 917 /* 58 - 720(1440)x480i@240 */ 918 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 919 801, 858, 0, 480, 488, 494, 525, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 921 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 922 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 923 /* 59 - 720(1440)x480i@240 */ 924 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 925 801, 858, 0, 480, 488, 494, 525, 0, 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 928 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 60 - 1280x720@24Hz */ 930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 931 3080, 3300, 0, 720, 725, 730, 750, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 61 - 1280x720@25Hz */ 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 936 3740, 3960, 0, 720, 725, 730, 750, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 62 - 1280x720@30Hz */ 940 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 941 3080, 3300, 0, 720, 725, 730, 750, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 944 /* 63 - 1920x1080@120Hz */ 945 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 946 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 64 - 1920x1080@100Hz */ 950 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 951 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 }; 955 956 /* 957 * HDMI 1.4 4k modes. 958 */ 959 static const struct drm_display_mode edid_4k_modes[] = { 960 /* 1 - 3840x2160@30Hz */ 961 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 962 3840, 4016, 4104, 4400, 0, 963 2160, 2168, 2178, 2250, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 965 .vrefresh = 30, }, 966 /* 2 - 3840x2160@25Hz */ 967 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 968 3840, 4896, 4984, 5280, 0, 969 2160, 2168, 2178, 2250, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 971 .vrefresh = 25, }, 972 /* 3 - 3840x2160@24Hz */ 973 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 974 3840, 5116, 5204, 5500, 0, 975 2160, 2168, 2178, 2250, 0, 976 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 977 .vrefresh = 24, }, 978 /* 4 - 4096x2160@24Hz (SMPTE) */ 979 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 980 4096, 5116, 5204, 5500, 0, 981 2160, 2168, 2178, 2250, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 983 .vrefresh = 24, }, 984 }; 985 986 /*** DDC fetch and block validation ***/ 987 988 static const u8 edid_header[] = { 989 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 990 }; 991 992 /** 993 * drm_edid_header_is_valid - sanity check the header of the base EDID block 994 * @raw_edid: pointer to raw base EDID block 995 * 996 * Sanity check the header of the base EDID block. 997 * 998 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 999 */ 1000 int drm_edid_header_is_valid(const u8 *raw_edid) 1001 { 1002 int i, score = 0; 1003 1004 for (i = 0; i < sizeof(edid_header); i++) 1005 if (raw_edid[i] == edid_header[i]) 1006 score++; 1007 1008 return score; 1009 } 1010 EXPORT_SYMBOL(drm_edid_header_is_valid); 1011 1012 static int edid_fixup __read_mostly = 6; 1013 module_param_named(edid_fixup, edid_fixup, int, 0400); 1014 MODULE_PARM_DESC(edid_fixup, 1015 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1016 1017 /** 1018 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1019 * @raw_edid: pointer to raw EDID block 1020 * @block: type of block to validate (0 for base, extension otherwise) 1021 * @print_bad_edid: if true, dump bad EDID blocks to the console 1022 * 1023 * Validate a base or extension EDID block and optionally dump bad blocks to 1024 * the console. 1025 * 1026 * Return: True if the block is valid, false otherwise. 1027 */ 1028 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) 1029 { 1030 int i; 1031 u8 csum = 0; 1032 struct edid *edid = (struct edid *)raw_edid; 1033 1034 if (WARN_ON(!raw_edid)) 1035 return false; 1036 1037 if (edid_fixup > 8 || edid_fixup < 0) 1038 edid_fixup = 6; 1039 1040 if (block == 0) { 1041 int score = drm_edid_header_is_valid(raw_edid); 1042 if (score == 8) ; 1043 else if (score >= edid_fixup) { 1044 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1045 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1046 } else { 1047 goto bad; 1048 } 1049 } 1050 1051 for (i = 0; i < EDID_LENGTH; i++) 1052 csum += raw_edid[i]; 1053 if (csum) { 1054 if (print_bad_edid) { 1055 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1056 } 1057 1058 /* allow CEA to slide through, switches mangle this */ 1059 if (raw_edid[0] != 0x02) 1060 goto bad; 1061 } 1062 1063 /* per-block-type checks */ 1064 switch (raw_edid[0]) { 1065 case 0: /* base */ 1066 if (edid->version != 1) { 1067 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1068 goto bad; 1069 } 1070 1071 if (edid->revision > 4) 1072 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1073 break; 1074 1075 default: 1076 break; 1077 } 1078 1079 return true; 1080 1081 bad: 1082 if (print_bad_edid) { 1083 printk(KERN_ERR "Raw EDID:\n"); 1084 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1085 raw_edid, EDID_LENGTH, false); 1086 } 1087 return false; 1088 } 1089 EXPORT_SYMBOL(drm_edid_block_valid); 1090 1091 /** 1092 * drm_edid_is_valid - sanity check EDID data 1093 * @edid: EDID data 1094 * 1095 * Sanity-check an entire EDID record (including extensions) 1096 * 1097 * Return: True if the EDID data is valid, false otherwise. 1098 */ 1099 bool drm_edid_is_valid(struct edid *edid) 1100 { 1101 int i; 1102 u8 *raw = (u8 *)edid; 1103 1104 if (!edid) 1105 return false; 1106 1107 for (i = 0; i <= edid->extensions; i++) 1108 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) 1109 return false; 1110 1111 return true; 1112 } 1113 EXPORT_SYMBOL(drm_edid_is_valid); 1114 1115 #define DDC_SEGMENT_ADDR 0x30 1116 /** 1117 * drm_do_probe_ddc_edid() - get EDID information via I2C 1118 * @adapter: I2C device adaptor 1119 * @buf: EDID data buffer to be filled 1120 * @block: 128 byte EDID block to start fetching from 1121 * @len: EDID data buffer length to fetch 1122 * 1123 * Try to fetch EDID information by calling I2C driver functions. 1124 * 1125 * Return: 0 on success or -1 on failure. 1126 */ 1127 static int 1128 drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, 1129 int block, int len) 1130 { 1131 unsigned char start = block * EDID_LENGTH; 1132 unsigned char segment = block >> 1; 1133 unsigned char xfers = segment ? 3 : 2; 1134 int ret, retries = 5; 1135 1136 /* 1137 * The core I2C driver will automatically retry the transfer if the 1138 * adapter reports EAGAIN. However, we find that bit-banging transfers 1139 * are susceptible to errors under a heavily loaded machine and 1140 * generate spurious NAKs and timeouts. Retrying the transfer 1141 * of the individual block a few times seems to overcome this. 1142 */ 1143 do { 1144 struct i2c_msg msgs[] = { 1145 { 1146 .addr = DDC_SEGMENT_ADDR, 1147 .flags = 0, 1148 .len = 1, 1149 .buf = &segment, 1150 }, { 1151 .addr = DDC_ADDR, 1152 .flags = 0, 1153 .len = 1, 1154 .buf = &start, 1155 }, { 1156 .addr = DDC_ADDR, 1157 .flags = I2C_M_RD, 1158 .len = len, 1159 .buf = buf, 1160 } 1161 }; 1162 1163 /* 1164 * Avoid sending the segment addr to not upset non-compliant 1165 * DDC monitors. 1166 */ 1167 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1168 1169 if (ret == -ENXIO) { 1170 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1171 adapter->name); 1172 break; 1173 } 1174 } while (ret != xfers && --retries); 1175 1176 return ret == xfers ? 0 : -1; 1177 } 1178 1179 static bool drm_edid_is_zero(u8 *in_edid, int length) 1180 { 1181 if (memchr_inv(in_edid, 0, length)) 1182 return false; 1183 1184 return true; 1185 } 1186 1187 static u8 * 1188 drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 1189 { 1190 int i, j = 0, valid_extensions = 0; 1191 u8 *block, *new; 1192 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1193 1194 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1195 return NULL; 1196 1197 /* base block fetch */ 1198 for (i = 0; i < 4; i++) { 1199 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) 1200 goto out; 1201 if (drm_edid_block_valid(block, 0, print_bad_edid)) 1202 break; 1203 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1204 connector->null_edid_counter++; 1205 goto carp; 1206 } 1207 } 1208 if (i == 4) 1209 goto carp; 1210 1211 /* if there's no extensions, we're done */ 1212 if (block[0x7e] == 0) 1213 return block; 1214 1215 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1216 if (!new) 1217 goto out; 1218 block = new; 1219 1220 for (j = 1; j <= block[0x7e]; j++) { 1221 for (i = 0; i < 4; i++) { 1222 if (drm_do_probe_ddc_edid(adapter, 1223 block + (valid_extensions + 1) * EDID_LENGTH, 1224 j, EDID_LENGTH)) 1225 goto out; 1226 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { 1227 valid_extensions++; 1228 break; 1229 } 1230 } 1231 1232 if (i == 4 && print_bad_edid) { 1233 dev_warn(connector->dev->dev, 1234 "%s: Ignoring invalid EDID block %d.\n", 1235 connector->name, j); 1236 1237 connector->bad_edid_counter++; 1238 } 1239 } 1240 1241 if (valid_extensions != block[0x7e]) { 1242 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1243 block[0x7e] = valid_extensions; 1244 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1245 if (!new) 1246 goto out; 1247 block = new; 1248 } 1249 1250 return block; 1251 1252 carp: 1253 if (print_bad_edid) { 1254 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1255 connector->name, j); 1256 } 1257 connector->bad_edid_counter++; 1258 1259 out: 1260 kfree(block); 1261 return NULL; 1262 } 1263 1264 /** 1265 * drm_probe_ddc() - probe DDC presence 1266 * @adapter: I2C adapter to probe 1267 * 1268 * Return: True on success, false on failure. 1269 */ 1270 bool 1271 drm_probe_ddc(struct i2c_adapter *adapter) 1272 { 1273 unsigned char out; 1274 1275 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1276 } 1277 EXPORT_SYMBOL(drm_probe_ddc); 1278 1279 /** 1280 * drm_get_edid - get EDID data, if available 1281 * @connector: connector we're probing 1282 * @adapter: I2C adapter to use for DDC 1283 * 1284 * Poke the given I2C channel to grab EDID data if possible. If found, 1285 * attach it to the connector. 1286 * 1287 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1288 */ 1289 struct edid *drm_get_edid(struct drm_connector *connector, 1290 struct i2c_adapter *adapter) 1291 { 1292 struct edid *edid = NULL; 1293 1294 if (drm_probe_ddc(adapter)) 1295 edid = (struct edid *)drm_do_get_edid(connector, adapter); 1296 1297 return edid; 1298 } 1299 EXPORT_SYMBOL(drm_get_edid); 1300 1301 /** 1302 * drm_edid_duplicate - duplicate an EDID and the extensions 1303 * @edid: EDID to duplicate 1304 * 1305 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1306 */ 1307 struct edid *drm_edid_duplicate(const struct edid *edid) 1308 { 1309 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1310 } 1311 EXPORT_SYMBOL(drm_edid_duplicate); 1312 1313 /*** EDID parsing ***/ 1314 1315 /** 1316 * edid_vendor - match a string against EDID's obfuscated vendor field 1317 * @edid: EDID to match 1318 * @vendor: vendor string 1319 * 1320 * Returns true if @vendor is in @edid, false otherwise 1321 */ 1322 static bool edid_vendor(struct edid *edid, char *vendor) 1323 { 1324 char edid_vendor[3]; 1325 1326 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1327 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1328 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1329 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1330 1331 return !strncmp(edid_vendor, vendor, 3); 1332 } 1333 1334 /** 1335 * edid_get_quirks - return quirk flags for a given EDID 1336 * @edid: EDID to process 1337 * 1338 * This tells subsequent routines what fixes they need to apply. 1339 */ 1340 static u32 edid_get_quirks(struct edid *edid) 1341 { 1342 struct edid_quirk *quirk; 1343 int i; 1344 1345 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1346 quirk = &edid_quirk_list[i]; 1347 1348 if (edid_vendor(edid, quirk->vendor) && 1349 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1350 return quirk->quirks; 1351 } 1352 1353 return 0; 1354 } 1355 1356 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1357 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1358 1359 /** 1360 * edid_fixup_preferred - set preferred modes based on quirk list 1361 * @connector: has mode list to fix up 1362 * @quirks: quirks list 1363 * 1364 * Walk the mode list for @connector, clearing the preferred status 1365 * on existing modes and setting it anew for the right mode ala @quirks. 1366 */ 1367 static void edid_fixup_preferred(struct drm_connector *connector, 1368 u32 quirks) 1369 { 1370 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1371 int target_refresh = 0; 1372 int cur_vrefresh, preferred_vrefresh; 1373 1374 if (list_empty(&connector->probed_modes)) 1375 return; 1376 1377 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1378 target_refresh = 60; 1379 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1380 target_refresh = 75; 1381 1382 preferred_mode = list_first_entry(&connector->probed_modes, 1383 struct drm_display_mode, head); 1384 1385 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1386 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1387 1388 if (cur_mode == preferred_mode) 1389 continue; 1390 1391 /* Largest mode is preferred */ 1392 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1393 preferred_mode = cur_mode; 1394 1395 cur_vrefresh = cur_mode->vrefresh ? 1396 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1397 preferred_vrefresh = preferred_mode->vrefresh ? 1398 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1399 /* At a given size, try to get closest to target refresh */ 1400 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1401 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1402 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1403 preferred_mode = cur_mode; 1404 } 1405 } 1406 1407 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1408 } 1409 1410 static bool 1411 mode_is_rb(const struct drm_display_mode *mode) 1412 { 1413 return (mode->htotal - mode->hdisplay == 160) && 1414 (mode->hsync_end - mode->hdisplay == 80) && 1415 (mode->hsync_end - mode->hsync_start == 32) && 1416 (mode->vsync_start - mode->vdisplay == 3); 1417 } 1418 1419 /* 1420 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1421 * @dev: Device to duplicate against 1422 * @hsize: Mode width 1423 * @vsize: Mode height 1424 * @fresh: Mode refresh rate 1425 * @rb: Mode reduced-blanking-ness 1426 * 1427 * Walk the DMT mode list looking for a match for the given parameters. 1428 * 1429 * Return: A newly allocated copy of the mode, or NULL if not found. 1430 */ 1431 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1432 int hsize, int vsize, int fresh, 1433 bool rb) 1434 { 1435 int i; 1436 1437 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1438 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1439 if (hsize != ptr->hdisplay) 1440 continue; 1441 if (vsize != ptr->vdisplay) 1442 continue; 1443 if (fresh != drm_mode_vrefresh(ptr)) 1444 continue; 1445 if (rb != mode_is_rb(ptr)) 1446 continue; 1447 1448 return drm_mode_duplicate(dev, ptr); 1449 } 1450 1451 return NULL; 1452 } 1453 EXPORT_SYMBOL(drm_mode_find_dmt); 1454 1455 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1456 1457 static void 1458 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1459 { 1460 int i, n = 0; 1461 u8 d = ext[0x02]; 1462 u8 *det_base = ext + d; 1463 1464 n = (127 - d) / 18; 1465 for (i = 0; i < n; i++) 1466 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1467 } 1468 1469 static void 1470 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1471 { 1472 unsigned int i, n = min((int)ext[0x02], 6); 1473 u8 *det_base = ext + 5; 1474 1475 if (ext[0x01] != 1) 1476 return; /* unknown version */ 1477 1478 for (i = 0; i < n; i++) 1479 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1480 } 1481 1482 static void 1483 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1484 { 1485 int i; 1486 struct edid *edid = (struct edid *)raw_edid; 1487 1488 if (edid == NULL) 1489 return; 1490 1491 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1492 cb(&(edid->detailed_timings[i]), closure); 1493 1494 for (i = 1; i <= raw_edid[0x7e]; i++) { 1495 u8 *ext = raw_edid + (i * EDID_LENGTH); 1496 switch (*ext) { 1497 case CEA_EXT: 1498 cea_for_each_detailed_block(ext, cb, closure); 1499 break; 1500 case VTB_EXT: 1501 vtb_for_each_detailed_block(ext, cb, closure); 1502 break; 1503 default: 1504 break; 1505 } 1506 } 1507 } 1508 1509 static void 1510 is_rb(struct detailed_timing *t, void *data) 1511 { 1512 u8 *r = (u8 *)t; 1513 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1514 if (r[15] & 0x10) 1515 *(bool *)data = true; 1516 } 1517 1518 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1519 static bool 1520 drm_monitor_supports_rb(struct edid *edid) 1521 { 1522 if (edid->revision >= 4) { 1523 bool ret = false; 1524 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1525 return ret; 1526 } 1527 1528 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1529 } 1530 1531 static void 1532 find_gtf2(struct detailed_timing *t, void *data) 1533 { 1534 u8 *r = (u8 *)t; 1535 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1536 *(u8 **)data = r; 1537 } 1538 1539 /* Secondary GTF curve kicks in above some break frequency */ 1540 static int 1541 drm_gtf2_hbreak(struct edid *edid) 1542 { 1543 u8 *r = NULL; 1544 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1545 return r ? (r[12] * 2) : 0; 1546 } 1547 1548 static int 1549 drm_gtf2_2c(struct edid *edid) 1550 { 1551 u8 *r = NULL; 1552 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1553 return r ? r[13] : 0; 1554 } 1555 1556 static int 1557 drm_gtf2_m(struct edid *edid) 1558 { 1559 u8 *r = NULL; 1560 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1561 return r ? (r[15] << 8) + r[14] : 0; 1562 } 1563 1564 static int 1565 drm_gtf2_k(struct edid *edid) 1566 { 1567 u8 *r = NULL; 1568 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1569 return r ? r[16] : 0; 1570 } 1571 1572 static int 1573 drm_gtf2_2j(struct edid *edid) 1574 { 1575 u8 *r = NULL; 1576 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1577 return r ? r[17] : 0; 1578 } 1579 1580 /** 1581 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1582 * @edid: EDID block to scan 1583 */ 1584 static int standard_timing_level(struct edid *edid) 1585 { 1586 if (edid->revision >= 2) { 1587 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1588 return LEVEL_CVT; 1589 if (drm_gtf2_hbreak(edid)) 1590 return LEVEL_GTF2; 1591 return LEVEL_GTF; 1592 } 1593 return LEVEL_DMT; 1594 } 1595 1596 /* 1597 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1598 * monitors fill with ascii space (0x20) instead. 1599 */ 1600 static int 1601 bad_std_timing(u8 a, u8 b) 1602 { 1603 return (a == 0x00 && b == 0x00) || 1604 (a == 0x01 && b == 0x01) || 1605 (a == 0x20 && b == 0x20); 1606 } 1607 1608 /** 1609 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1610 * @connector: connector of for the EDID block 1611 * @edid: EDID block to scan 1612 * @t: standard timing params 1613 * 1614 * Take the standard timing params (in this case width, aspect, and refresh) 1615 * and convert them into a real mode using CVT/GTF/DMT. 1616 */ 1617 static struct drm_display_mode * 1618 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1619 struct std_timing *t) 1620 { 1621 struct drm_device *dev = connector->dev; 1622 struct drm_display_mode *m, *mode = NULL; 1623 int hsize, vsize; 1624 int vrefresh_rate; 1625 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1626 >> EDID_TIMING_ASPECT_SHIFT; 1627 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1628 >> EDID_TIMING_VFREQ_SHIFT; 1629 int timing_level = standard_timing_level(edid); 1630 1631 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1632 return NULL; 1633 1634 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1635 hsize = t->hsize * 8 + 248; 1636 /* vrefresh_rate = vfreq + 60 */ 1637 vrefresh_rate = vfreq + 60; 1638 /* the vdisplay is calculated based on the aspect ratio */ 1639 if (aspect_ratio == 0) { 1640 if (edid->revision < 3) 1641 vsize = hsize; 1642 else 1643 vsize = (hsize * 10) / 16; 1644 } else if (aspect_ratio == 1) 1645 vsize = (hsize * 3) / 4; 1646 else if (aspect_ratio == 2) 1647 vsize = (hsize * 4) / 5; 1648 else 1649 vsize = (hsize * 9) / 16; 1650 1651 /* HDTV hack, part 1 */ 1652 if (vrefresh_rate == 60 && 1653 ((hsize == 1360 && vsize == 765) || 1654 (hsize == 1368 && vsize == 769))) { 1655 hsize = 1366; 1656 vsize = 768; 1657 } 1658 1659 /* 1660 * If this connector already has a mode for this size and refresh 1661 * rate (because it came from detailed or CVT info), use that 1662 * instead. This way we don't have to guess at interlace or 1663 * reduced blanking. 1664 */ 1665 list_for_each_entry(m, &connector->probed_modes, head) 1666 if (m->hdisplay == hsize && m->vdisplay == vsize && 1667 drm_mode_vrefresh(m) == vrefresh_rate) 1668 return NULL; 1669 1670 /* HDTV hack, part 2 */ 1671 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1672 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1673 false); 1674 mode->hdisplay = 1366; 1675 mode->hsync_start = mode->hsync_start - 1; 1676 mode->hsync_end = mode->hsync_end - 1; 1677 return mode; 1678 } 1679 1680 /* check whether it can be found in default mode table */ 1681 if (drm_monitor_supports_rb(edid)) { 1682 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1683 true); 1684 if (mode) 1685 return mode; 1686 } 1687 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1688 if (mode) 1689 return mode; 1690 1691 /* okay, generate it */ 1692 switch (timing_level) { 1693 case LEVEL_DMT: 1694 break; 1695 case LEVEL_GTF: 1696 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1697 break; 1698 case LEVEL_GTF2: 1699 /* 1700 * This is potentially wrong if there's ever a monitor with 1701 * more than one ranges section, each claiming a different 1702 * secondary GTF curve. Please don't do that. 1703 */ 1704 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1705 if (!mode) 1706 return NULL; 1707 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1708 drm_mode_destroy(dev, mode); 1709 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1710 vrefresh_rate, 0, 0, 1711 drm_gtf2_m(edid), 1712 drm_gtf2_2c(edid), 1713 drm_gtf2_k(edid), 1714 drm_gtf2_2j(edid)); 1715 } 1716 break; 1717 case LEVEL_CVT: 1718 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1719 false); 1720 break; 1721 } 1722 return mode; 1723 } 1724 1725 /* 1726 * EDID is delightfully ambiguous about how interlaced modes are to be 1727 * encoded. Our internal representation is of frame height, but some 1728 * HDTV detailed timings are encoded as field height. 1729 * 1730 * The format list here is from CEA, in frame size. Technically we 1731 * should be checking refresh rate too. Whatever. 1732 */ 1733 static void 1734 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1735 struct detailed_pixel_timing *pt) 1736 { 1737 int i; 1738 static const struct { 1739 int w, h; 1740 } cea_interlaced[] = { 1741 { 1920, 1080 }, 1742 { 720, 480 }, 1743 { 1440, 480 }, 1744 { 2880, 480 }, 1745 { 720, 576 }, 1746 { 1440, 576 }, 1747 { 2880, 576 }, 1748 }; 1749 1750 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1751 return; 1752 1753 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1754 if ((mode->hdisplay == cea_interlaced[i].w) && 1755 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1756 mode->vdisplay *= 2; 1757 mode->vsync_start *= 2; 1758 mode->vsync_end *= 2; 1759 mode->vtotal *= 2; 1760 mode->vtotal |= 1; 1761 } 1762 } 1763 1764 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1765 } 1766 1767 /** 1768 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1769 * @dev: DRM device (needed to create new mode) 1770 * @edid: EDID block 1771 * @timing: EDID detailed timing info 1772 * @quirks: quirks to apply 1773 * 1774 * An EDID detailed timing block contains enough info for us to create and 1775 * return a new struct drm_display_mode. 1776 */ 1777 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1778 struct edid *edid, 1779 struct detailed_timing *timing, 1780 u32 quirks) 1781 { 1782 struct drm_display_mode *mode; 1783 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1784 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1785 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1786 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1787 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1788 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1789 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1790 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1791 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1792 1793 /* ignore tiny modes */ 1794 if (hactive < 64 || vactive < 64) 1795 return NULL; 1796 1797 if (pt->misc & DRM_EDID_PT_STEREO) { 1798 DRM_DEBUG_KMS("stereo mode not supported\n"); 1799 return NULL; 1800 } 1801 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1802 DRM_DEBUG_KMS("composite sync not supported\n"); 1803 } 1804 1805 /* it is incorrect if hsync/vsync width is zero */ 1806 if (!hsync_pulse_width || !vsync_pulse_width) { 1807 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1808 "Wrong Hsync/Vsync pulse width\n"); 1809 return NULL; 1810 } 1811 1812 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1813 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1814 if (!mode) 1815 return NULL; 1816 1817 goto set_size; 1818 } 1819 1820 mode = drm_mode_create(dev); 1821 if (!mode) 1822 return NULL; 1823 1824 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1825 timing->pixel_clock = cpu_to_le16(1088); 1826 1827 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1828 1829 mode->hdisplay = hactive; 1830 mode->hsync_start = mode->hdisplay + hsync_offset; 1831 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1832 mode->htotal = mode->hdisplay + hblank; 1833 1834 mode->vdisplay = vactive; 1835 mode->vsync_start = mode->vdisplay + vsync_offset; 1836 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1837 mode->vtotal = mode->vdisplay + vblank; 1838 1839 /* Some EDIDs have bogus h/vtotal values */ 1840 if (mode->hsync_end > mode->htotal) 1841 mode->htotal = mode->hsync_end + 1; 1842 if (mode->vsync_end > mode->vtotal) 1843 mode->vtotal = mode->vsync_end + 1; 1844 1845 drm_mode_do_interlace_quirk(mode, pt); 1846 1847 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1848 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1849 } 1850 1851 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1852 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1853 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1854 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1855 1856 set_size: 1857 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1858 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1859 1860 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1861 mode->width_mm *= 10; 1862 mode->height_mm *= 10; 1863 } 1864 1865 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1866 mode->width_mm = edid->width_cm * 10; 1867 mode->height_mm = edid->height_cm * 10; 1868 } 1869 1870 mode->type = DRM_MODE_TYPE_DRIVER; 1871 mode->vrefresh = drm_mode_vrefresh(mode); 1872 drm_mode_set_name(mode); 1873 1874 return mode; 1875 } 1876 1877 static bool 1878 mode_in_hsync_range(const struct drm_display_mode *mode, 1879 struct edid *edid, u8 *t) 1880 { 1881 int hsync, hmin, hmax; 1882 1883 hmin = t[7]; 1884 if (edid->revision >= 4) 1885 hmin += ((t[4] & 0x04) ? 255 : 0); 1886 hmax = t[8]; 1887 if (edid->revision >= 4) 1888 hmax += ((t[4] & 0x08) ? 255 : 0); 1889 hsync = drm_mode_hsync(mode); 1890 1891 return (hsync <= hmax && hsync >= hmin); 1892 } 1893 1894 static bool 1895 mode_in_vsync_range(const struct drm_display_mode *mode, 1896 struct edid *edid, u8 *t) 1897 { 1898 int vsync, vmin, vmax; 1899 1900 vmin = t[5]; 1901 if (edid->revision >= 4) 1902 vmin += ((t[4] & 0x01) ? 255 : 0); 1903 vmax = t[6]; 1904 if (edid->revision >= 4) 1905 vmax += ((t[4] & 0x02) ? 255 : 0); 1906 vsync = drm_mode_vrefresh(mode); 1907 1908 return (vsync <= vmax && vsync >= vmin); 1909 } 1910 1911 static u32 1912 range_pixel_clock(struct edid *edid, u8 *t) 1913 { 1914 /* unspecified */ 1915 if (t[9] == 0 || t[9] == 255) 1916 return 0; 1917 1918 /* 1.4 with CVT support gives us real precision, yay */ 1919 if (edid->revision >= 4 && t[10] == 0x04) 1920 return (t[9] * 10000) - ((t[12] >> 2) * 250); 1921 1922 /* 1.3 is pathetic, so fuzz up a bit */ 1923 return t[9] * 10000 + 5001; 1924 } 1925 1926 static bool 1927 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 1928 struct detailed_timing *timing) 1929 { 1930 u32 max_clock; 1931 u8 *t = (u8 *)timing; 1932 1933 if (!mode_in_hsync_range(mode, edid, t)) 1934 return false; 1935 1936 if (!mode_in_vsync_range(mode, edid, t)) 1937 return false; 1938 1939 if ((max_clock = range_pixel_clock(edid, t))) 1940 if (mode->clock > max_clock) 1941 return false; 1942 1943 /* 1.4 max horizontal check */ 1944 if (edid->revision >= 4 && t[10] == 0x04) 1945 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 1946 return false; 1947 1948 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 1949 return false; 1950 1951 return true; 1952 } 1953 1954 static bool valid_inferred_mode(const struct drm_connector *connector, 1955 const struct drm_display_mode *mode) 1956 { 1957 struct drm_display_mode *m; 1958 bool ok = false; 1959 1960 list_for_each_entry(m, &connector->probed_modes, head) { 1961 if (mode->hdisplay == m->hdisplay && 1962 mode->vdisplay == m->vdisplay && 1963 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 1964 return false; /* duplicated */ 1965 if (mode->hdisplay <= m->hdisplay && 1966 mode->vdisplay <= m->vdisplay) 1967 ok = true; 1968 } 1969 return ok; 1970 } 1971 1972 static int 1973 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1974 struct detailed_timing *timing) 1975 { 1976 int i, modes = 0; 1977 struct drm_display_mode *newmode; 1978 struct drm_device *dev = connector->dev; 1979 1980 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1981 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 1982 valid_inferred_mode(connector, drm_dmt_modes + i)) { 1983 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 1984 if (newmode) { 1985 drm_mode_probed_add(connector, newmode); 1986 modes++; 1987 } 1988 } 1989 } 1990 1991 return modes; 1992 } 1993 1994 /* fix up 1366x768 mode from 1368x768; 1995 * GFT/CVT can't express 1366 width which isn't dividable by 8 1996 */ 1997 static void fixup_mode_1366x768(struct drm_display_mode *mode) 1998 { 1999 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2000 mode->hdisplay = 1366; 2001 mode->hsync_start--; 2002 mode->hsync_end--; 2003 drm_mode_set_name(mode); 2004 } 2005 } 2006 2007 static int 2008 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2009 struct detailed_timing *timing) 2010 { 2011 int i, modes = 0; 2012 struct drm_display_mode *newmode; 2013 struct drm_device *dev = connector->dev; 2014 2015 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2016 const struct minimode *m = &extra_modes[i]; 2017 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2018 if (!newmode) 2019 return modes; 2020 2021 fixup_mode_1366x768(newmode); 2022 if (!mode_in_range(newmode, edid, timing) || 2023 !valid_inferred_mode(connector, newmode)) { 2024 drm_mode_destroy(dev, newmode); 2025 continue; 2026 } 2027 2028 drm_mode_probed_add(connector, newmode); 2029 modes++; 2030 } 2031 2032 return modes; 2033 } 2034 2035 static int 2036 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2037 struct detailed_timing *timing) 2038 { 2039 int i, modes = 0; 2040 struct drm_display_mode *newmode; 2041 struct drm_device *dev = connector->dev; 2042 bool rb = drm_monitor_supports_rb(edid); 2043 2044 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2045 const struct minimode *m = &extra_modes[i]; 2046 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2047 if (!newmode) 2048 return modes; 2049 2050 fixup_mode_1366x768(newmode); 2051 if (!mode_in_range(newmode, edid, timing) || 2052 !valid_inferred_mode(connector, newmode)) { 2053 drm_mode_destroy(dev, newmode); 2054 continue; 2055 } 2056 2057 drm_mode_probed_add(connector, newmode); 2058 modes++; 2059 } 2060 2061 return modes; 2062 } 2063 2064 static void 2065 do_inferred_modes(struct detailed_timing *timing, void *c) 2066 { 2067 struct detailed_mode_closure *closure = c; 2068 struct detailed_non_pixel *data = &timing->data.other_data; 2069 struct detailed_data_monitor_range *range = &data->data.range; 2070 2071 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2072 return; 2073 2074 closure->modes += drm_dmt_modes_for_range(closure->connector, 2075 closure->edid, 2076 timing); 2077 2078 if (!version_greater(closure->edid, 1, 1)) 2079 return; /* GTF not defined yet */ 2080 2081 switch (range->flags) { 2082 case 0x02: /* secondary gtf, XXX could do more */ 2083 case 0x00: /* default gtf */ 2084 closure->modes += drm_gtf_modes_for_range(closure->connector, 2085 closure->edid, 2086 timing); 2087 break; 2088 case 0x04: /* cvt, only in 1.4+ */ 2089 if (!version_greater(closure->edid, 1, 3)) 2090 break; 2091 2092 closure->modes += drm_cvt_modes_for_range(closure->connector, 2093 closure->edid, 2094 timing); 2095 break; 2096 case 0x01: /* just the ranges, no formula */ 2097 default: 2098 break; 2099 } 2100 } 2101 2102 static int 2103 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2104 { 2105 struct detailed_mode_closure closure = { 2106 .connector = connector, 2107 .edid = edid, 2108 }; 2109 2110 if (version_greater(edid, 1, 0)) 2111 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2112 &closure); 2113 2114 return closure.modes; 2115 } 2116 2117 static int 2118 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2119 { 2120 int i, j, m, modes = 0; 2121 struct drm_display_mode *mode; 2122 u8 *est = ((u8 *)timing) + 5; 2123 2124 for (i = 0; i < 6; i++) { 2125 for (j = 7; j >= 0; j--) { 2126 m = (i * 8) + (7 - j); 2127 if (m >= ARRAY_SIZE(est3_modes)) 2128 break; 2129 if (est[i] & (1 << j)) { 2130 mode = drm_mode_find_dmt(connector->dev, 2131 est3_modes[m].w, 2132 est3_modes[m].h, 2133 est3_modes[m].r, 2134 est3_modes[m].rb); 2135 if (mode) { 2136 drm_mode_probed_add(connector, mode); 2137 modes++; 2138 } 2139 } 2140 } 2141 } 2142 2143 return modes; 2144 } 2145 2146 static void 2147 do_established_modes(struct detailed_timing *timing, void *c) 2148 { 2149 struct detailed_mode_closure *closure = c; 2150 struct detailed_non_pixel *data = &timing->data.other_data; 2151 2152 if (data->type == EDID_DETAIL_EST_TIMINGS) 2153 closure->modes += drm_est3_modes(closure->connector, timing); 2154 } 2155 2156 /** 2157 * add_established_modes - get est. modes from EDID and add them 2158 * @connector: connector to add mode(s) to 2159 * @edid: EDID block to scan 2160 * 2161 * Each EDID block contains a bitmap of the supported "established modes" list 2162 * (defined above). Tease them out and add them to the global modes list. 2163 */ 2164 static int 2165 add_established_modes(struct drm_connector *connector, struct edid *edid) 2166 { 2167 struct drm_device *dev = connector->dev; 2168 unsigned long est_bits = edid->established_timings.t1 | 2169 (edid->established_timings.t2 << 8) | 2170 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2171 int i, modes = 0; 2172 struct detailed_mode_closure closure = { 2173 .connector = connector, 2174 .edid = edid, 2175 }; 2176 2177 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2178 if (est_bits & (1<<i)) { 2179 struct drm_display_mode *newmode; 2180 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2181 if (newmode) { 2182 drm_mode_probed_add(connector, newmode); 2183 modes++; 2184 } 2185 } 2186 } 2187 2188 if (version_greater(edid, 1, 0)) 2189 drm_for_each_detailed_block((u8 *)edid, 2190 do_established_modes, &closure); 2191 2192 return modes + closure.modes; 2193 } 2194 2195 static void 2196 do_standard_modes(struct detailed_timing *timing, void *c) 2197 { 2198 struct detailed_mode_closure *closure = c; 2199 struct detailed_non_pixel *data = &timing->data.other_data; 2200 struct drm_connector *connector = closure->connector; 2201 struct edid *edid = closure->edid; 2202 2203 if (data->type == EDID_DETAIL_STD_MODES) { 2204 int i; 2205 for (i = 0; i < 6; i++) { 2206 struct std_timing *std; 2207 struct drm_display_mode *newmode; 2208 2209 std = &data->data.timings[i]; 2210 newmode = drm_mode_std(connector, edid, std); 2211 if (newmode) { 2212 drm_mode_probed_add(connector, newmode); 2213 closure->modes++; 2214 } 2215 } 2216 } 2217 } 2218 2219 /** 2220 * add_standard_modes - get std. modes from EDID and add them 2221 * @connector: connector to add mode(s) to 2222 * @edid: EDID block to scan 2223 * 2224 * Standard modes can be calculated using the appropriate standard (DMT, 2225 * GTF or CVT. Grab them from @edid and add them to the list. 2226 */ 2227 static int 2228 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2229 { 2230 int i, modes = 0; 2231 struct detailed_mode_closure closure = { 2232 .connector = connector, 2233 .edid = edid, 2234 }; 2235 2236 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2237 struct drm_display_mode *newmode; 2238 2239 newmode = drm_mode_std(connector, edid, 2240 &edid->standard_timings[i]); 2241 if (newmode) { 2242 drm_mode_probed_add(connector, newmode); 2243 modes++; 2244 } 2245 } 2246 2247 if (version_greater(edid, 1, 0)) 2248 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2249 &closure); 2250 2251 /* XXX should also look for standard codes in VTB blocks */ 2252 2253 return modes + closure.modes; 2254 } 2255 2256 static int drm_cvt_modes(struct drm_connector *connector, 2257 struct detailed_timing *timing) 2258 { 2259 int i, j, modes = 0; 2260 struct drm_display_mode *newmode; 2261 struct drm_device *dev = connector->dev; 2262 struct cvt_timing *cvt; 2263 const int rates[] = { 60, 85, 75, 60, 50 }; 2264 const u8 empty[3] = { 0, 0, 0 }; 2265 2266 for (i = 0; i < 4; i++) { 2267 int uninitialized_var(width), height; 2268 cvt = &(timing->data.other_data.data.cvt[i]); 2269 2270 if (!memcmp(cvt->code, empty, 3)) 2271 continue; 2272 2273 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2274 switch (cvt->code[1] & 0x0c) { 2275 case 0x00: 2276 width = height * 4 / 3; 2277 break; 2278 case 0x04: 2279 width = height * 16 / 9; 2280 break; 2281 case 0x08: 2282 width = height * 16 / 10; 2283 break; 2284 case 0x0c: 2285 width = height * 15 / 9; 2286 break; 2287 } 2288 2289 for (j = 1; j < 5; j++) { 2290 if (cvt->code[2] & (1 << j)) { 2291 newmode = drm_cvt_mode(dev, width, height, 2292 rates[j], j == 0, 2293 false, false); 2294 if (newmode) { 2295 drm_mode_probed_add(connector, newmode); 2296 modes++; 2297 } 2298 } 2299 } 2300 } 2301 2302 return modes; 2303 } 2304 2305 static void 2306 do_cvt_mode(struct detailed_timing *timing, void *c) 2307 { 2308 struct detailed_mode_closure *closure = c; 2309 struct detailed_non_pixel *data = &timing->data.other_data; 2310 2311 if (data->type == EDID_DETAIL_CVT_3BYTE) 2312 closure->modes += drm_cvt_modes(closure->connector, timing); 2313 } 2314 2315 static int 2316 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2317 { 2318 struct detailed_mode_closure closure = { 2319 .connector = connector, 2320 .edid = edid, 2321 }; 2322 2323 if (version_greater(edid, 1, 2)) 2324 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2325 2326 /* XXX should also look for CVT codes in VTB blocks */ 2327 2328 return closure.modes; 2329 } 2330 2331 static void 2332 do_detailed_mode(struct detailed_timing *timing, void *c) 2333 { 2334 struct detailed_mode_closure *closure = c; 2335 struct drm_display_mode *newmode; 2336 2337 if (timing->pixel_clock) { 2338 newmode = drm_mode_detailed(closure->connector->dev, 2339 closure->edid, timing, 2340 closure->quirks); 2341 if (!newmode) 2342 return; 2343 2344 if (closure->preferred) 2345 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2346 2347 drm_mode_probed_add(closure->connector, newmode); 2348 closure->modes++; 2349 closure->preferred = 0; 2350 } 2351 } 2352 2353 /* 2354 * add_detailed_modes - Add modes from detailed timings 2355 * @connector: attached connector 2356 * @edid: EDID block to scan 2357 * @quirks: quirks to apply 2358 */ 2359 static int 2360 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2361 u32 quirks) 2362 { 2363 struct detailed_mode_closure closure = { 2364 .connector = connector, 2365 .edid = edid, 2366 .preferred = 1, 2367 .quirks = quirks, 2368 }; 2369 2370 if (closure.preferred && !version_greater(edid, 1, 3)) 2371 closure.preferred = 2372 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2373 2374 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2375 2376 return closure.modes; 2377 } 2378 2379 #define AUDIO_BLOCK 0x01 2380 #define VIDEO_BLOCK 0x02 2381 #define VENDOR_BLOCK 0x03 2382 #define SPEAKER_BLOCK 0x04 2383 #define VIDEO_CAPABILITY_BLOCK 0x07 2384 #define EDID_BASIC_AUDIO (1 << 6) 2385 #define EDID_CEA_YCRCB444 (1 << 5) 2386 #define EDID_CEA_YCRCB422 (1 << 4) 2387 #define EDID_CEA_VCDB_QS (1 << 6) 2388 2389 /* 2390 * Search EDID for CEA extension block. 2391 */ 2392 static u8 *drm_find_cea_extension(struct edid *edid) 2393 { 2394 u8 *edid_ext = NULL; 2395 int i; 2396 2397 /* No EDID or EDID extensions */ 2398 if (edid == NULL || edid->extensions == 0) 2399 return NULL; 2400 2401 /* Find CEA extension */ 2402 for (i = 0; i < edid->extensions; i++) { 2403 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2404 if (edid_ext[0] == CEA_EXT) 2405 break; 2406 } 2407 2408 if (i == edid->extensions) 2409 return NULL; 2410 2411 return edid_ext; 2412 } 2413 2414 /* 2415 * Calculate the alternate clock for the CEA mode 2416 * (60Hz vs. 59.94Hz etc.) 2417 */ 2418 static unsigned int 2419 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2420 { 2421 unsigned int clock = cea_mode->clock; 2422 2423 if (cea_mode->vrefresh % 6 != 0) 2424 return clock; 2425 2426 /* 2427 * edid_cea_modes contains the 59.94Hz 2428 * variant for 240 and 480 line modes, 2429 * and the 60Hz variant otherwise. 2430 */ 2431 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2432 clock = clock * 1001 / 1000; 2433 else 2434 clock = DIV_ROUND_UP(clock * 1000, 1001); 2435 2436 return clock; 2437 } 2438 2439 /** 2440 * drm_match_cea_mode - look for a CEA mode matching given mode 2441 * @to_match: display mode 2442 * 2443 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2444 * mode. 2445 */ 2446 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2447 { 2448 u8 mode; 2449 2450 if (!to_match->clock) 2451 return 0; 2452 2453 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2454 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2455 unsigned int clock1, clock2; 2456 2457 /* Check both 60Hz and 59.94Hz */ 2458 clock1 = cea_mode->clock; 2459 clock2 = cea_mode_alternate_clock(cea_mode); 2460 2461 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2462 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2463 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2464 return mode + 1; 2465 } 2466 return 0; 2467 } 2468 EXPORT_SYMBOL(drm_match_cea_mode); 2469 2470 /** 2471 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2472 * the input VIC from the CEA mode list 2473 * @video_code: ID given to each of the CEA modes 2474 * 2475 * Returns picture aspect ratio 2476 */ 2477 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2478 { 2479 /* return picture aspect ratio for video_code - 1 to access the 2480 * right array element 2481 */ 2482 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2483 } 2484 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2485 2486 /* 2487 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2488 * specific block). 2489 * 2490 * It's almost like cea_mode_alternate_clock(), we just need to add an 2491 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2492 * one. 2493 */ 2494 static unsigned int 2495 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2496 { 2497 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2498 return hdmi_mode->clock; 2499 2500 return cea_mode_alternate_clock(hdmi_mode); 2501 } 2502 2503 /* 2504 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2505 * @to_match: display mode 2506 * 2507 * An HDMI mode is one defined in the HDMI vendor specific block. 2508 * 2509 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2510 */ 2511 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2512 { 2513 u8 mode; 2514 2515 if (!to_match->clock) 2516 return 0; 2517 2518 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2519 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2520 unsigned int clock1, clock2; 2521 2522 /* Make sure to also match alternate clocks */ 2523 clock1 = hdmi_mode->clock; 2524 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2525 2526 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2527 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2528 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2529 return mode + 1; 2530 } 2531 return 0; 2532 } 2533 2534 static int 2535 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2536 { 2537 struct drm_device *dev = connector->dev; 2538 struct drm_display_mode *mode, *tmp; 2539 LIST_HEAD(list); 2540 int modes = 0; 2541 2542 /* Don't add CEA modes if the CEA extension block is missing */ 2543 if (!drm_find_cea_extension(edid)) 2544 return 0; 2545 2546 /* 2547 * Go through all probed modes and create a new mode 2548 * with the alternate clock for certain CEA modes. 2549 */ 2550 list_for_each_entry(mode, &connector->probed_modes, head) { 2551 const struct drm_display_mode *cea_mode = NULL; 2552 struct drm_display_mode *newmode; 2553 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2554 unsigned int clock1, clock2; 2555 2556 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2557 cea_mode = &edid_cea_modes[mode_idx]; 2558 clock2 = cea_mode_alternate_clock(cea_mode); 2559 } else { 2560 mode_idx = drm_match_hdmi_mode(mode) - 1; 2561 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2562 cea_mode = &edid_4k_modes[mode_idx]; 2563 clock2 = hdmi_mode_alternate_clock(cea_mode); 2564 } 2565 } 2566 2567 if (!cea_mode) 2568 continue; 2569 2570 clock1 = cea_mode->clock; 2571 2572 if (clock1 == clock2) 2573 continue; 2574 2575 if (mode->clock != clock1 && mode->clock != clock2) 2576 continue; 2577 2578 newmode = drm_mode_duplicate(dev, cea_mode); 2579 if (!newmode) 2580 continue; 2581 2582 /* Carry over the stereo flags */ 2583 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2584 2585 /* 2586 * The current mode could be either variant. Make 2587 * sure to pick the "other" clock for the new mode. 2588 */ 2589 if (mode->clock != clock1) 2590 newmode->clock = clock1; 2591 else 2592 newmode->clock = clock2; 2593 2594 list_add_tail(&newmode->head, &list); 2595 } 2596 2597 list_for_each_entry_safe(mode, tmp, &list, head) { 2598 list_del(&mode->head); 2599 drm_mode_probed_add(connector, mode); 2600 modes++; 2601 } 2602 2603 return modes; 2604 } 2605 2606 static struct drm_display_mode * 2607 drm_display_mode_from_vic_index(struct drm_connector *connector, 2608 const u8 *video_db, u8 video_len, 2609 u8 video_index) 2610 { 2611 struct drm_device *dev = connector->dev; 2612 struct drm_display_mode *newmode; 2613 u8 cea_mode; 2614 2615 if (video_db == NULL || video_index >= video_len) 2616 return NULL; 2617 2618 /* CEA modes are numbered 1..127 */ 2619 cea_mode = (video_db[video_index] & 127) - 1; 2620 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2621 return NULL; 2622 2623 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2624 if (!newmode) 2625 return NULL; 2626 2627 newmode->vrefresh = 0; 2628 2629 return newmode; 2630 } 2631 2632 static int 2633 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2634 { 2635 int i, modes = 0; 2636 2637 for (i = 0; i < len; i++) { 2638 struct drm_display_mode *mode; 2639 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2640 if (mode) { 2641 drm_mode_probed_add(connector, mode); 2642 modes++; 2643 } 2644 } 2645 2646 return modes; 2647 } 2648 2649 struct stereo_mandatory_mode { 2650 int width, height, vrefresh; 2651 unsigned int flags; 2652 }; 2653 2654 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2655 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2656 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2657 { 1920, 1080, 50, 2658 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2659 { 1920, 1080, 60, 2660 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2661 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2662 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2663 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2664 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2665 }; 2666 2667 static bool 2668 stereo_match_mandatory(const struct drm_display_mode *mode, 2669 const struct stereo_mandatory_mode *stereo_mode) 2670 { 2671 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2672 2673 return mode->hdisplay == stereo_mode->width && 2674 mode->vdisplay == stereo_mode->height && 2675 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2676 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2677 } 2678 2679 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2680 { 2681 struct drm_device *dev = connector->dev; 2682 const struct drm_display_mode *mode; 2683 struct list_head stereo_modes; 2684 int modes = 0, i; 2685 2686 INIT_LIST_HEAD(&stereo_modes); 2687 2688 list_for_each_entry(mode, &connector->probed_modes, head) { 2689 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2690 const struct stereo_mandatory_mode *mandatory; 2691 struct drm_display_mode *new_mode; 2692 2693 if (!stereo_match_mandatory(mode, 2694 &stereo_mandatory_modes[i])) 2695 continue; 2696 2697 mandatory = &stereo_mandatory_modes[i]; 2698 new_mode = drm_mode_duplicate(dev, mode); 2699 if (!new_mode) 2700 continue; 2701 2702 new_mode->flags |= mandatory->flags; 2703 list_add_tail(&new_mode->head, &stereo_modes); 2704 modes++; 2705 } 2706 } 2707 2708 list_splice_tail(&stereo_modes, &connector->probed_modes); 2709 2710 return modes; 2711 } 2712 2713 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2714 { 2715 struct drm_device *dev = connector->dev; 2716 struct drm_display_mode *newmode; 2717 2718 vic--; /* VICs start at 1 */ 2719 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2720 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2721 return 0; 2722 } 2723 2724 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2725 if (!newmode) 2726 return 0; 2727 2728 drm_mode_probed_add(connector, newmode); 2729 2730 return 1; 2731 } 2732 2733 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2734 const u8 *video_db, u8 video_len, u8 video_index) 2735 { 2736 struct drm_display_mode *newmode; 2737 int modes = 0; 2738 2739 if (structure & (1 << 0)) { 2740 newmode = drm_display_mode_from_vic_index(connector, video_db, 2741 video_len, 2742 video_index); 2743 if (newmode) { 2744 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2745 drm_mode_probed_add(connector, newmode); 2746 modes++; 2747 } 2748 } 2749 if (structure & (1 << 6)) { 2750 newmode = drm_display_mode_from_vic_index(connector, video_db, 2751 video_len, 2752 video_index); 2753 if (newmode) { 2754 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2755 drm_mode_probed_add(connector, newmode); 2756 modes++; 2757 } 2758 } 2759 if (structure & (1 << 8)) { 2760 newmode = drm_display_mode_from_vic_index(connector, video_db, 2761 video_len, 2762 video_index); 2763 if (newmode) { 2764 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2765 drm_mode_probed_add(connector, newmode); 2766 modes++; 2767 } 2768 } 2769 2770 return modes; 2771 } 2772 2773 /* 2774 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2775 * @connector: connector corresponding to the HDMI sink 2776 * @db: start of the CEA vendor specific block 2777 * @len: length of the CEA block payload, ie. one can access up to db[len] 2778 * 2779 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2780 * also adds the stereo 3d modes when applicable. 2781 */ 2782 static int 2783 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2784 const u8 *video_db, u8 video_len) 2785 { 2786 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2787 u8 vic_len, hdmi_3d_len = 0; 2788 u16 mask; 2789 u16 structure_all; 2790 2791 if (len < 8) 2792 goto out; 2793 2794 /* no HDMI_Video_Present */ 2795 if (!(db[8] & (1 << 5))) 2796 goto out; 2797 2798 /* Latency_Fields_Present */ 2799 if (db[8] & (1 << 7)) 2800 offset += 2; 2801 2802 /* I_Latency_Fields_Present */ 2803 if (db[8] & (1 << 6)) 2804 offset += 2; 2805 2806 /* the declared length is not long enough for the 2 first bytes 2807 * of additional video format capabilities */ 2808 if (len < (8 + offset + 2)) 2809 goto out; 2810 2811 /* 3D_Present */ 2812 offset++; 2813 if (db[8 + offset] & (1 << 7)) { 2814 modes += add_hdmi_mandatory_stereo_modes(connector); 2815 2816 /* 3D_Multi_present */ 2817 multi_present = (db[8 + offset] & 0x60) >> 5; 2818 } 2819 2820 offset++; 2821 vic_len = db[8 + offset] >> 5; 2822 hdmi_3d_len = db[8 + offset] & 0x1f; 2823 2824 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2825 u8 vic; 2826 2827 vic = db[9 + offset + i]; 2828 modes += add_hdmi_mode(connector, vic); 2829 } 2830 offset += 1 + vic_len; 2831 2832 if (multi_present == 1) 2833 multi_len = 2; 2834 else if (multi_present == 2) 2835 multi_len = 4; 2836 else 2837 multi_len = 0; 2838 2839 if (len < (8 + offset + hdmi_3d_len - 1)) 2840 goto out; 2841 2842 if (hdmi_3d_len < multi_len) 2843 goto out; 2844 2845 if (multi_present == 1 || multi_present == 2) { 2846 /* 3D_Structure_ALL */ 2847 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2848 2849 /* check if 3D_MASK is present */ 2850 if (multi_present == 2) 2851 mask = (db[10 + offset] << 8) | db[11 + offset]; 2852 else 2853 mask = 0xffff; 2854 2855 for (i = 0; i < 16; i++) { 2856 if (mask & (1 << i)) 2857 modes += add_3d_struct_modes(connector, 2858 structure_all, 2859 video_db, 2860 video_len, i); 2861 } 2862 } 2863 2864 offset += multi_len; 2865 2866 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2867 int vic_index; 2868 struct drm_display_mode *newmode = NULL; 2869 unsigned int newflag = 0; 2870 bool detail_present; 2871 2872 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2873 2874 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2875 break; 2876 2877 /* 2D_VIC_order_X */ 2878 vic_index = db[8 + offset + i] >> 4; 2879 2880 /* 3D_Structure_X */ 2881 switch (db[8 + offset + i] & 0x0f) { 2882 case 0: 2883 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2884 break; 2885 case 6: 2886 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2887 break; 2888 case 8: 2889 /* 3D_Detail_X */ 2890 if ((db[9 + offset + i] >> 4) == 1) 2891 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2892 break; 2893 } 2894 2895 if (newflag != 0) { 2896 newmode = drm_display_mode_from_vic_index(connector, 2897 video_db, 2898 video_len, 2899 vic_index); 2900 2901 if (newmode) { 2902 newmode->flags |= newflag; 2903 drm_mode_probed_add(connector, newmode); 2904 modes++; 2905 } 2906 } 2907 2908 if (detail_present) 2909 i++; 2910 } 2911 2912 out: 2913 return modes; 2914 } 2915 2916 static int 2917 cea_db_payload_len(const u8 *db) 2918 { 2919 return db[0] & 0x1f; 2920 } 2921 2922 static int 2923 cea_db_tag(const u8 *db) 2924 { 2925 return db[0] >> 5; 2926 } 2927 2928 static int 2929 cea_revision(const u8 *cea) 2930 { 2931 return cea[1]; 2932 } 2933 2934 static int 2935 cea_db_offsets(const u8 *cea, int *start, int *end) 2936 { 2937 /* Data block offset in CEA extension block */ 2938 *start = 4; 2939 *end = cea[2]; 2940 if (*end == 0) 2941 *end = 127; 2942 if (*end < 4 || *end > 127) 2943 return -ERANGE; 2944 return 0; 2945 } 2946 2947 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2948 { 2949 int hdmi_id; 2950 2951 if (cea_db_tag(db) != VENDOR_BLOCK) 2952 return false; 2953 2954 if (cea_db_payload_len(db) < 5) 2955 return false; 2956 2957 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2958 2959 return hdmi_id == HDMI_IEEE_OUI; 2960 } 2961 2962 #define for_each_cea_db(cea, i, start, end) \ 2963 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2964 2965 static int 2966 add_cea_modes(struct drm_connector *connector, struct edid *edid) 2967 { 2968 const u8 *cea = drm_find_cea_extension(edid); 2969 const u8 *db, *hdmi = NULL, *video = NULL; 2970 u8 dbl, hdmi_len, video_len = 0; 2971 int modes = 0; 2972 2973 if (cea && cea_revision(cea) >= 3) { 2974 int i, start, end; 2975 2976 if (cea_db_offsets(cea, &start, &end)) 2977 return 0; 2978 2979 for_each_cea_db(cea, i, start, end) { 2980 db = &cea[i]; 2981 dbl = cea_db_payload_len(db); 2982 2983 if (cea_db_tag(db) == VIDEO_BLOCK) { 2984 video = db + 1; 2985 video_len = dbl; 2986 modes += do_cea_modes(connector, video, dbl); 2987 } 2988 else if (cea_db_is_hdmi_vsdb(db)) { 2989 hdmi = db; 2990 hdmi_len = dbl; 2991 } 2992 } 2993 } 2994 2995 /* 2996 * We parse the HDMI VSDB after having added the cea modes as we will 2997 * be patching their flags when the sink supports stereo 3D. 2998 */ 2999 if (hdmi) 3000 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3001 video_len); 3002 3003 return modes; 3004 } 3005 3006 static void 3007 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3008 { 3009 u8 len = cea_db_payload_len(db); 3010 3011 if (len >= 6) { 3012 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3013 connector->dvi_dual = db[6] & 1; 3014 } 3015 if (len >= 7) 3016 connector->max_tmds_clock = db[7] * 5; 3017 if (len >= 8) { 3018 connector->latency_present[0] = db[8] >> 7; 3019 connector->latency_present[1] = (db[8] >> 6) & 1; 3020 } 3021 if (len >= 9) 3022 connector->video_latency[0] = db[9]; 3023 if (len >= 10) 3024 connector->audio_latency[0] = db[10]; 3025 if (len >= 11) 3026 connector->video_latency[1] = db[11]; 3027 if (len >= 12) 3028 connector->audio_latency[1] = db[12]; 3029 3030 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3031 "max TMDS clock %d, " 3032 "latency present %d %d, " 3033 "video latency %d %d, " 3034 "audio latency %d %d\n", 3035 connector->dvi_dual, 3036 connector->max_tmds_clock, 3037 (int) connector->latency_present[0], 3038 (int) connector->latency_present[1], 3039 connector->video_latency[0], 3040 connector->video_latency[1], 3041 connector->audio_latency[0], 3042 connector->audio_latency[1]); 3043 } 3044 3045 static void 3046 monitor_name(struct detailed_timing *t, void *data) 3047 { 3048 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3049 *(u8 **)data = t->data.other_data.data.str.str; 3050 } 3051 3052 /** 3053 * drm_edid_to_eld - build ELD from EDID 3054 * @connector: connector corresponding to the HDMI/DP sink 3055 * @edid: EDID to parse 3056 * 3057 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3058 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3059 * fill in. 3060 */ 3061 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3062 { 3063 uint8_t *eld = connector->eld; 3064 u8 *cea; 3065 u8 *name; 3066 u8 *db; 3067 int sad_count = 0; 3068 int mnl; 3069 int dbl; 3070 3071 memset(eld, 0, sizeof(connector->eld)); 3072 3073 cea = drm_find_cea_extension(edid); 3074 if (!cea) { 3075 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3076 return; 3077 } 3078 3079 name = NULL; 3080 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3081 for (mnl = 0; name && mnl < 13; mnl++) { 3082 if (name[mnl] == 0x0a) 3083 break; 3084 eld[20 + mnl] = name[mnl]; 3085 } 3086 eld[4] = (cea[1] << 5) | mnl; 3087 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3088 3089 eld[0] = 2 << 3; /* ELD version: 2 */ 3090 3091 eld[16] = edid->mfg_id[0]; 3092 eld[17] = edid->mfg_id[1]; 3093 eld[18] = edid->prod_code[0]; 3094 eld[19] = edid->prod_code[1]; 3095 3096 if (cea_revision(cea) >= 3) { 3097 int i, start, end; 3098 3099 if (cea_db_offsets(cea, &start, &end)) { 3100 start = 0; 3101 end = 0; 3102 } 3103 3104 for_each_cea_db(cea, i, start, end) { 3105 db = &cea[i]; 3106 dbl = cea_db_payload_len(db); 3107 3108 switch (cea_db_tag(db)) { 3109 case AUDIO_BLOCK: 3110 /* Audio Data Block, contains SADs */ 3111 sad_count = dbl / 3; 3112 if (dbl >= 1) 3113 memcpy(eld + 20 + mnl, &db[1], dbl); 3114 break; 3115 case SPEAKER_BLOCK: 3116 /* Speaker Allocation Data Block */ 3117 if (dbl >= 1) 3118 eld[7] = db[1]; 3119 break; 3120 case VENDOR_BLOCK: 3121 /* HDMI Vendor-Specific Data Block */ 3122 if (cea_db_is_hdmi_vsdb(db)) 3123 parse_hdmi_vsdb(connector, db); 3124 break; 3125 default: 3126 break; 3127 } 3128 } 3129 } 3130 eld[5] |= sad_count << 4; 3131 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3132 3133 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3134 } 3135 EXPORT_SYMBOL(drm_edid_to_eld); 3136 3137 /** 3138 * drm_edid_to_sad - extracts SADs from EDID 3139 * @edid: EDID to parse 3140 * @sads: pointer that will be set to the extracted SADs 3141 * 3142 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3143 * 3144 * Note: The returned pointer needs to be freed using kfree(). 3145 * 3146 * Return: The number of found SADs or negative number on error. 3147 */ 3148 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3149 { 3150 int count = 0; 3151 int i, start, end, dbl; 3152 u8 *cea; 3153 3154 cea = drm_find_cea_extension(edid); 3155 if (!cea) { 3156 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3157 return -ENOENT; 3158 } 3159 3160 if (cea_revision(cea) < 3) { 3161 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3162 return -ENOTSUPP; 3163 } 3164 3165 if (cea_db_offsets(cea, &start, &end)) { 3166 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3167 return -EPROTO; 3168 } 3169 3170 for_each_cea_db(cea, i, start, end) { 3171 u8 *db = &cea[i]; 3172 3173 if (cea_db_tag(db) == AUDIO_BLOCK) { 3174 int j; 3175 dbl = cea_db_payload_len(db); 3176 3177 count = dbl / 3; /* SAD is 3B */ 3178 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3179 if (!*sads) 3180 return -ENOMEM; 3181 for (j = 0; j < count; j++) { 3182 u8 *sad = &db[1 + j * 3]; 3183 3184 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3185 (*sads)[j].channels = sad[0] & 0x7; 3186 (*sads)[j].freq = sad[1] & 0x7F; 3187 (*sads)[j].byte2 = sad[2]; 3188 } 3189 break; 3190 } 3191 } 3192 3193 return count; 3194 } 3195 EXPORT_SYMBOL(drm_edid_to_sad); 3196 3197 /** 3198 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3199 * @edid: EDID to parse 3200 * @sadb: pointer to the speaker block 3201 * 3202 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3203 * 3204 * Note: The returned pointer needs to be freed using kfree(). 3205 * 3206 * Return: The number of found Speaker Allocation Blocks or negative number on 3207 * error. 3208 */ 3209 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3210 { 3211 int count = 0; 3212 int i, start, end, dbl; 3213 const u8 *cea; 3214 3215 cea = drm_find_cea_extension(edid); 3216 if (!cea) { 3217 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3218 return -ENOENT; 3219 } 3220 3221 if (cea_revision(cea) < 3) { 3222 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3223 return -ENOTSUPP; 3224 } 3225 3226 if (cea_db_offsets(cea, &start, &end)) { 3227 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3228 return -EPROTO; 3229 } 3230 3231 for_each_cea_db(cea, i, start, end) { 3232 const u8 *db = &cea[i]; 3233 3234 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3235 dbl = cea_db_payload_len(db); 3236 3237 /* Speaker Allocation Data Block */ 3238 if (dbl == 3) { 3239 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3240 if (!*sadb) 3241 return -ENOMEM; 3242 count = dbl; 3243 break; 3244 } 3245 } 3246 } 3247 3248 return count; 3249 } 3250 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3251 3252 /** 3253 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3254 * @connector: connector associated with the HDMI/DP sink 3255 * @mode: the display mode 3256 * 3257 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3258 * the sink doesn't support audio or video. 3259 */ 3260 int drm_av_sync_delay(struct drm_connector *connector, 3261 struct drm_display_mode *mode) 3262 { 3263 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3264 int a, v; 3265 3266 if (!connector->latency_present[0]) 3267 return 0; 3268 if (!connector->latency_present[1]) 3269 i = 0; 3270 3271 a = connector->audio_latency[i]; 3272 v = connector->video_latency[i]; 3273 3274 /* 3275 * HDMI/DP sink doesn't support audio or video? 3276 */ 3277 if (a == 255 || v == 255) 3278 return 0; 3279 3280 /* 3281 * Convert raw EDID values to millisecond. 3282 * Treat unknown latency as 0ms. 3283 */ 3284 if (a) 3285 a = min(2 * (a - 1), 500); 3286 if (v) 3287 v = min(2 * (v - 1), 500); 3288 3289 return max(v - a, 0); 3290 } 3291 EXPORT_SYMBOL(drm_av_sync_delay); 3292 3293 /** 3294 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3295 * @encoder: the encoder just changed display mode 3296 * @mode: the adjusted display mode 3297 * 3298 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3299 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3300 * 3301 * Return: The connector associated with the first HDMI/DP sink that has ELD 3302 * attached to it. 3303 */ 3304 struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 3305 struct drm_display_mode *mode) 3306 { 3307 struct drm_connector *connector; 3308 struct drm_device *dev = encoder->dev; 3309 3310 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3311 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3312 3313 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 3314 if (connector->encoder == encoder && connector->eld[0]) 3315 return connector; 3316 3317 return NULL; 3318 } 3319 EXPORT_SYMBOL(drm_select_eld); 3320 3321 /** 3322 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3323 * @edid: monitor EDID information 3324 * 3325 * Parse the CEA extension according to CEA-861-B. 3326 * 3327 * Return: True if the monitor is HDMI, false if not or unknown. 3328 */ 3329 bool drm_detect_hdmi_monitor(struct edid *edid) 3330 { 3331 u8 *edid_ext; 3332 int i; 3333 int start_offset, end_offset; 3334 3335 edid_ext = drm_find_cea_extension(edid); 3336 if (!edid_ext) 3337 return false; 3338 3339 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3340 return false; 3341 3342 /* 3343 * Because HDMI identifier is in Vendor Specific Block, 3344 * search it from all data blocks of CEA extension. 3345 */ 3346 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3347 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3348 return true; 3349 } 3350 3351 return false; 3352 } 3353 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3354 3355 /** 3356 * drm_detect_monitor_audio - check monitor audio capability 3357 * @edid: EDID block to scan 3358 * 3359 * Monitor should have CEA extension block. 3360 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3361 * audio' only. If there is any audio extension block and supported 3362 * audio format, assume at least 'basic audio' support, even if 'basic 3363 * audio' is not defined in EDID. 3364 * 3365 * Return: True if the monitor supports audio, false otherwise. 3366 */ 3367 bool drm_detect_monitor_audio(struct edid *edid) 3368 { 3369 u8 *edid_ext; 3370 int i, j; 3371 bool has_audio = false; 3372 int start_offset, end_offset; 3373 3374 edid_ext = drm_find_cea_extension(edid); 3375 if (!edid_ext) 3376 goto end; 3377 3378 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3379 3380 if (has_audio) { 3381 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3382 goto end; 3383 } 3384 3385 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3386 goto end; 3387 3388 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3389 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3390 has_audio = true; 3391 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3392 DRM_DEBUG_KMS("CEA audio format %d\n", 3393 (edid_ext[i + j] >> 3) & 0xf); 3394 goto end; 3395 } 3396 } 3397 end: 3398 return has_audio; 3399 } 3400 EXPORT_SYMBOL(drm_detect_monitor_audio); 3401 3402 /** 3403 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3404 * @edid: EDID block to scan 3405 * 3406 * Check whether the monitor reports the RGB quantization range selection 3407 * as supported. The AVI infoframe can then be used to inform the monitor 3408 * which quantization range (full or limited) is used. 3409 * 3410 * Return: True if the RGB quantization range is selectable, false otherwise. 3411 */ 3412 bool drm_rgb_quant_range_selectable(struct edid *edid) 3413 { 3414 u8 *edid_ext; 3415 int i, start, end; 3416 3417 edid_ext = drm_find_cea_extension(edid); 3418 if (!edid_ext) 3419 return false; 3420 3421 if (cea_db_offsets(edid_ext, &start, &end)) 3422 return false; 3423 3424 for_each_cea_db(edid_ext, i, start, end) { 3425 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3426 cea_db_payload_len(&edid_ext[i]) == 2) { 3427 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3428 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3429 } 3430 } 3431 3432 return false; 3433 } 3434 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3435 3436 /** 3437 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3438 * hdmi deep color modes and update drm_display_info if so. 3439 * @edid: monitor EDID information 3440 * @info: Updated with maximum supported deep color bpc and color format 3441 * if deep color supported. 3442 * @connector: DRM connector, used only for debug output 3443 * 3444 * Parse the CEA extension according to CEA-861-B. 3445 * Return true if HDMI deep color supported, false if not or unknown. 3446 */ 3447 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3448 struct drm_display_info *info, 3449 struct drm_connector *connector) 3450 { 3451 u8 *edid_ext, *hdmi; 3452 int i; 3453 int start_offset, end_offset; 3454 unsigned int dc_bpc = 0; 3455 3456 edid_ext = drm_find_cea_extension(edid); 3457 if (!edid_ext) 3458 return false; 3459 3460 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3461 return false; 3462 3463 /* 3464 * Because HDMI identifier is in Vendor Specific Block, 3465 * search it from all data blocks of CEA extension. 3466 */ 3467 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3468 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3469 /* HDMI supports at least 8 bpc */ 3470 info->bpc = 8; 3471 3472 hdmi = &edid_ext[i]; 3473 if (cea_db_payload_len(hdmi) < 6) 3474 return false; 3475 3476 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3477 dc_bpc = 10; 3478 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3479 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3480 connector->name); 3481 } 3482 3483 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3484 dc_bpc = 12; 3485 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3486 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3487 connector->name); 3488 } 3489 3490 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3491 dc_bpc = 16; 3492 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3493 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3494 connector->name); 3495 } 3496 3497 if (dc_bpc > 0) { 3498 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3499 connector->name, dc_bpc); 3500 info->bpc = dc_bpc; 3501 3502 /* 3503 * Deep color support mandates RGB444 support for all video 3504 * modes and forbids YCRCB422 support for all video modes per 3505 * HDMI 1.3 spec. 3506 */ 3507 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3508 3509 /* YCRCB444 is optional according to spec. */ 3510 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3511 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3512 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3513 connector->name); 3514 } 3515 3516 /* 3517 * Spec says that if any deep color mode is supported at all, 3518 * then deep color 36 bit must be supported. 3519 */ 3520 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3521 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3522 connector->name); 3523 } 3524 3525 return true; 3526 } 3527 else { 3528 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3529 connector->name); 3530 } 3531 } 3532 } 3533 3534 return false; 3535 } 3536 3537 /** 3538 * drm_add_display_info - pull display info out if present 3539 * @edid: EDID data 3540 * @info: display info (attached to connector) 3541 * @connector: connector whose edid is used to build display info 3542 * 3543 * Grab any available display info and stuff it into the drm_display_info 3544 * structure that's part of the connector. Useful for tracking bpp and 3545 * color spaces. 3546 */ 3547 static void drm_add_display_info(struct edid *edid, 3548 struct drm_display_info *info, 3549 struct drm_connector *connector) 3550 { 3551 u8 *edid_ext; 3552 3553 info->width_mm = edid->width_cm * 10; 3554 info->height_mm = edid->height_cm * 10; 3555 3556 /* driver figures it out in this case */ 3557 info->bpc = 0; 3558 info->color_formats = 0; 3559 3560 if (edid->revision < 3) 3561 return; 3562 3563 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3564 return; 3565 3566 /* Get data from CEA blocks if present */ 3567 edid_ext = drm_find_cea_extension(edid); 3568 if (edid_ext) { 3569 info->cea_rev = edid_ext[1]; 3570 3571 /* The existence of a CEA block should imply RGB support */ 3572 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3573 if (edid_ext[3] & EDID_CEA_YCRCB444) 3574 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3575 if (edid_ext[3] & EDID_CEA_YCRCB422) 3576 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3577 } 3578 3579 /* HDMI deep color modes supported? Assign to info, if so */ 3580 drm_assign_hdmi_deep_color_info(edid, info, connector); 3581 3582 /* Only defined for 1.4 with digital displays */ 3583 if (edid->revision < 4) 3584 return; 3585 3586 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3587 case DRM_EDID_DIGITAL_DEPTH_6: 3588 info->bpc = 6; 3589 break; 3590 case DRM_EDID_DIGITAL_DEPTH_8: 3591 info->bpc = 8; 3592 break; 3593 case DRM_EDID_DIGITAL_DEPTH_10: 3594 info->bpc = 10; 3595 break; 3596 case DRM_EDID_DIGITAL_DEPTH_12: 3597 info->bpc = 12; 3598 break; 3599 case DRM_EDID_DIGITAL_DEPTH_14: 3600 info->bpc = 14; 3601 break; 3602 case DRM_EDID_DIGITAL_DEPTH_16: 3603 info->bpc = 16; 3604 break; 3605 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3606 default: 3607 info->bpc = 0; 3608 break; 3609 } 3610 3611 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3612 connector->name, info->bpc); 3613 3614 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3615 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3616 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3617 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3618 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3619 } 3620 3621 /** 3622 * drm_add_edid_modes - add modes from EDID data, if available 3623 * @connector: connector we're probing 3624 * @edid: EDID data 3625 * 3626 * Add the specified modes to the connector's mode list. 3627 * 3628 * Return: The number of modes added or 0 if we couldn't find any. 3629 */ 3630 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3631 { 3632 int num_modes = 0; 3633 u32 quirks; 3634 3635 if (edid == NULL) { 3636 return 0; 3637 } 3638 if (!drm_edid_is_valid(edid)) { 3639 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3640 connector->name); 3641 return 0; 3642 } 3643 3644 quirks = edid_get_quirks(edid); 3645 3646 /* 3647 * EDID spec says modes should be preferred in this order: 3648 * - preferred detailed mode 3649 * - other detailed modes from base block 3650 * - detailed modes from extension blocks 3651 * - CVT 3-byte code modes 3652 * - standard timing codes 3653 * - established timing codes 3654 * - modes inferred from GTF or CVT range information 3655 * 3656 * We get this pretty much right. 3657 * 3658 * XXX order for additional mode types in extension blocks? 3659 */ 3660 num_modes += add_detailed_modes(connector, edid, quirks); 3661 num_modes += add_cvt_modes(connector, edid); 3662 num_modes += add_standard_modes(connector, edid); 3663 num_modes += add_established_modes(connector, edid); 3664 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3665 num_modes += add_inferred_modes(connector, edid); 3666 num_modes += add_cea_modes(connector, edid); 3667 num_modes += add_alternate_cea_modes(connector, edid); 3668 3669 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3670 edid_fixup_preferred(connector, quirks); 3671 3672 drm_add_display_info(edid, &connector->display_info, connector); 3673 3674 if (quirks & EDID_QUIRK_FORCE_8BPC) 3675 connector->display_info.bpc = 8; 3676 3677 if (quirks & EDID_QUIRK_FORCE_12BPC) 3678 connector->display_info.bpc = 12; 3679 3680 return num_modes; 3681 } 3682 EXPORT_SYMBOL(drm_add_edid_modes); 3683 3684 /** 3685 * drm_add_modes_noedid - add modes for the connectors without EDID 3686 * @connector: connector we're probing 3687 * @hdisplay: the horizontal display limit 3688 * @vdisplay: the vertical display limit 3689 * 3690 * Add the specified modes to the connector's mode list. Only when the 3691 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3692 * 3693 * Return: The number of modes added or 0 if we couldn't find any. 3694 */ 3695 int drm_add_modes_noedid(struct drm_connector *connector, 3696 int hdisplay, int vdisplay) 3697 { 3698 int i, count, num_modes = 0; 3699 struct drm_display_mode *mode; 3700 struct drm_device *dev = connector->dev; 3701 3702 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); 3703 if (hdisplay < 0) 3704 hdisplay = 0; 3705 if (vdisplay < 0) 3706 vdisplay = 0; 3707 3708 for (i = 0; i < count; i++) { 3709 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3710 if (hdisplay && vdisplay) { 3711 /* 3712 * Only when two are valid, they will be used to check 3713 * whether the mode should be added to the mode list of 3714 * the connector. 3715 */ 3716 if (ptr->hdisplay > hdisplay || 3717 ptr->vdisplay > vdisplay) 3718 continue; 3719 } 3720 if (drm_mode_vrefresh(ptr) > 61) 3721 continue; 3722 mode = drm_mode_duplicate(dev, ptr); 3723 if (mode) { 3724 drm_mode_probed_add(connector, mode); 3725 num_modes++; 3726 } 3727 } 3728 return num_modes; 3729 } 3730 EXPORT_SYMBOL(drm_add_modes_noedid); 3731 3732 /** 3733 * drm_set_preferred_mode - Sets the preferred mode of a connector 3734 * @connector: connector whose mode list should be processed 3735 * @hpref: horizontal resolution of preferred mode 3736 * @vpref: vertical resolution of preferred mode 3737 * 3738 * Marks a mode as preferred if it matches the resolution specified by @hpref 3739 * and @vpref. 3740 */ 3741 void drm_set_preferred_mode(struct drm_connector *connector, 3742 int hpref, int vpref) 3743 { 3744 struct drm_display_mode *mode; 3745 3746 list_for_each_entry(mode, &connector->probed_modes, head) { 3747 if (mode->hdisplay == hpref && 3748 mode->vdisplay == vpref) 3749 mode->type |= DRM_MODE_TYPE_PREFERRED; 3750 } 3751 } 3752 EXPORT_SYMBOL(drm_set_preferred_mode); 3753 3754 /** 3755 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3756 * data from a DRM display mode 3757 * @frame: HDMI AVI infoframe 3758 * @mode: DRM display mode 3759 * 3760 * Return: 0 on success or a negative error code on failure. 3761 */ 3762 int 3763 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3764 const struct drm_display_mode *mode) 3765 { 3766 int err; 3767 3768 if (!frame || !mode) 3769 return -EINVAL; 3770 3771 err = hdmi_avi_infoframe_init(frame); 3772 if (err < 0) 3773 return err; 3774 3775 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3776 frame->pixel_repeat = 1; 3777 3778 frame->video_code = drm_match_cea_mode(mode); 3779 3780 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3781 3782 /* 3783 * Populate picture aspect ratio from either 3784 * user input (if specified) or from the CEA mode list. 3785 */ 3786 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 3787 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 3788 frame->picture_aspect = mode->picture_aspect_ratio; 3789 else if (frame->video_code > 0) 3790 frame->picture_aspect = drm_get_cea_aspect_ratio( 3791 frame->video_code); 3792 3793 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3794 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3795 3796 return 0; 3797 } 3798 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3799 3800 static enum hdmi_3d_structure 3801 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3802 { 3803 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3804 3805 switch (layout) { 3806 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3807 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3808 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3809 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3810 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3811 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3812 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3813 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 3814 case DRM_MODE_FLAG_3D_L_DEPTH: 3815 return HDMI_3D_STRUCTURE_L_DEPTH; 3816 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 3817 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 3818 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 3819 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 3820 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 3821 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 3822 default: 3823 return HDMI_3D_STRUCTURE_INVALID; 3824 } 3825 } 3826 3827 /** 3828 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 3829 * data from a DRM display mode 3830 * @frame: HDMI vendor infoframe 3831 * @mode: DRM display mode 3832 * 3833 * Note that there's is a need to send HDMI vendor infoframes only when using a 3834 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 3835 * function will return -EINVAL, error that can be safely ignored. 3836 * 3837 * Return: 0 on success or a negative error code on failure. 3838 */ 3839 int 3840 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 3841 const struct drm_display_mode *mode) 3842 { 3843 int err; 3844 u32 s3d_flags; 3845 u8 vic; 3846 3847 if (!frame || !mode) 3848 return -EINVAL; 3849 3850 vic = drm_match_hdmi_mode(mode); 3851 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 3852 3853 if (!vic && !s3d_flags) 3854 return -EINVAL; 3855 3856 if (vic && s3d_flags) 3857 return -EINVAL; 3858 3859 err = hdmi_vendor_infoframe_init(frame); 3860 if (err < 0) 3861 return err; 3862 3863 if (vic) 3864 frame->vic = vic; 3865 else 3866 frame->s3d_struct = s3d_structure_from_display_mode(mode); 3867 3868 return 0; 3869 } 3870 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 3871