1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static int validate_displayid(u8 *displayid, int length, int idx); 1588 1589 static int drm_edid_block_checksum(const u8 *raw_edid) 1590 { 1591 int i; 1592 u8 csum = 0, crc = 0; 1593 1594 for (i = 0; i < EDID_LENGTH - 1; i++) 1595 csum += raw_edid[i]; 1596 1597 crc = 0x100 - csum; 1598 1599 return crc; 1600 } 1601 1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1603 { 1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1605 return true; 1606 else 1607 return false; 1608 } 1609 1610 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1611 { 1612 if (memchr_inv(in_edid, 0, length)) 1613 return false; 1614 1615 return true; 1616 } 1617 1618 /** 1619 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1620 * @raw_edid: pointer to raw EDID block 1621 * @block: type of block to validate (0 for base, extension otherwise) 1622 * @print_bad_edid: if true, dump bad EDID blocks to the console 1623 * @edid_corrupt: if true, the header or checksum is invalid 1624 * 1625 * Validate a base or extension EDID block and optionally dump bad blocks to 1626 * the console. 1627 * 1628 * Return: True if the block is valid, false otherwise. 1629 */ 1630 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1631 bool *edid_corrupt) 1632 { 1633 u8 csum; 1634 struct edid *edid = (struct edid *)raw_edid; 1635 1636 if (WARN_ON(!raw_edid)) 1637 return false; 1638 1639 if (edid_fixup > 8 || edid_fixup < 0) 1640 edid_fixup = 6; 1641 1642 if (block == 0) { 1643 int score = drm_edid_header_is_valid(raw_edid); 1644 if (score == 8) { 1645 if (edid_corrupt) 1646 *edid_corrupt = false; 1647 } else if (score >= edid_fixup) { 1648 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1649 * The corrupt flag needs to be set here otherwise, the 1650 * fix-up code here will correct the problem, the 1651 * checksum is correct and the test fails 1652 */ 1653 if (edid_corrupt) 1654 *edid_corrupt = true; 1655 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1656 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1657 } else { 1658 if (edid_corrupt) 1659 *edid_corrupt = true; 1660 goto bad; 1661 } 1662 } 1663 1664 csum = drm_edid_block_checksum(raw_edid); 1665 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1666 if (edid_corrupt) 1667 *edid_corrupt = true; 1668 1669 /* allow CEA to slide through, switches mangle this */ 1670 if (raw_edid[0] == CEA_EXT) { 1671 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1672 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1673 } else { 1674 if (print_bad_edid) 1675 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1676 1677 goto bad; 1678 } 1679 } 1680 1681 /* per-block-type checks */ 1682 switch (raw_edid[0]) { 1683 case 0: /* base */ 1684 if (edid->version != 1) { 1685 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1686 goto bad; 1687 } 1688 1689 if (edid->revision > 4) 1690 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1691 break; 1692 1693 default: 1694 break; 1695 } 1696 1697 return true; 1698 1699 bad: 1700 if (print_bad_edid) { 1701 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1702 pr_notice("EDID block is all zeroes\n"); 1703 } else { 1704 pr_notice("Raw EDID:\n"); 1705 print_hex_dump(KERN_NOTICE, 1706 " \t", DUMP_PREFIX_NONE, 16, 1, 1707 raw_edid, EDID_LENGTH, false); 1708 } 1709 } 1710 return false; 1711 } 1712 EXPORT_SYMBOL(drm_edid_block_valid); 1713 1714 /** 1715 * drm_edid_is_valid - sanity check EDID data 1716 * @edid: EDID data 1717 * 1718 * Sanity-check an entire EDID record (including extensions) 1719 * 1720 * Return: True if the EDID data is valid, false otherwise. 1721 */ 1722 bool drm_edid_is_valid(struct edid *edid) 1723 { 1724 int i; 1725 u8 *raw = (u8 *)edid; 1726 1727 if (!edid) 1728 return false; 1729 1730 for (i = 0; i <= edid->extensions; i++) 1731 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1732 return false; 1733 1734 return true; 1735 } 1736 EXPORT_SYMBOL(drm_edid_is_valid); 1737 1738 #define DDC_SEGMENT_ADDR 0x30 1739 /** 1740 * drm_do_probe_ddc_edid() - get EDID information via I2C 1741 * @data: I2C device adapter 1742 * @buf: EDID data buffer to be filled 1743 * @block: 128 byte EDID block to start fetching from 1744 * @len: EDID data buffer length to fetch 1745 * 1746 * Try to fetch EDID information by calling I2C driver functions. 1747 * 1748 * Return: 0 on success or -1 on failure. 1749 */ 1750 static int 1751 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1752 { 1753 struct i2c_adapter *adapter = data; 1754 unsigned char start = block * EDID_LENGTH; 1755 unsigned char segment = block >> 1; 1756 unsigned char xfers = segment ? 3 : 2; 1757 int ret, retries = 5; 1758 1759 /* 1760 * The core I2C driver will automatically retry the transfer if the 1761 * adapter reports EAGAIN. However, we find that bit-banging transfers 1762 * are susceptible to errors under a heavily loaded machine and 1763 * generate spurious NAKs and timeouts. Retrying the transfer 1764 * of the individual block a few times seems to overcome this. 1765 */ 1766 do { 1767 struct i2c_msg msgs[] = { 1768 { 1769 .addr = DDC_SEGMENT_ADDR, 1770 .flags = 0, 1771 .len = 1, 1772 .buf = &segment, 1773 }, { 1774 .addr = DDC_ADDR, 1775 .flags = 0, 1776 .len = 1, 1777 .buf = &start, 1778 }, { 1779 .addr = DDC_ADDR, 1780 .flags = I2C_M_RD, 1781 .len = len, 1782 .buf = buf, 1783 } 1784 }; 1785 1786 /* 1787 * Avoid sending the segment addr to not upset non-compliant 1788 * DDC monitors. 1789 */ 1790 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1791 1792 if (ret == -ENXIO) { 1793 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1794 adapter->name); 1795 break; 1796 } 1797 } while (ret != xfers && --retries); 1798 1799 return ret == xfers ? 0 : -1; 1800 } 1801 1802 static void connector_bad_edid(struct drm_connector *connector, 1803 u8 *edid, int num_blocks) 1804 { 1805 int i; 1806 u8 num_of_ext = edid[0x7e]; 1807 1808 /* Calculate real checksum for the last edid extension block data */ 1809 connector->real_edid_checksum = 1810 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1811 1812 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1813 return; 1814 1815 dev_warn(connector->dev->dev, 1816 "%s: EDID is invalid:\n", 1817 connector->name); 1818 for (i = 0; i < num_blocks; i++) { 1819 u8 *block = edid + i * EDID_LENGTH; 1820 char prefix[20]; 1821 1822 if (drm_edid_is_zero(block, EDID_LENGTH)) 1823 sprintf(prefix, "\t[%02x] ZERO ", i); 1824 else if (!drm_edid_block_valid(block, i, false, NULL)) 1825 sprintf(prefix, "\t[%02x] BAD ", i); 1826 else 1827 sprintf(prefix, "\t[%02x] GOOD ", i); 1828 1829 print_hex_dump(KERN_WARNING, 1830 prefix, DUMP_PREFIX_NONE, 16, 1, 1831 block, EDID_LENGTH, false); 1832 } 1833 } 1834 1835 /* Get override or firmware EDID */ 1836 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1837 { 1838 struct edid *override = NULL; 1839 1840 if (connector->override_edid) 1841 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1842 1843 if (!override) 1844 override = drm_load_edid_firmware(connector); 1845 1846 return IS_ERR(override) ? NULL : override; 1847 } 1848 1849 /** 1850 * drm_add_override_edid_modes - add modes from override/firmware EDID 1851 * @connector: connector we're probing 1852 * 1853 * Add modes from the override/firmware EDID, if available. Only to be used from 1854 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1855 * failed during drm_get_edid() and caused the override/firmware EDID to be 1856 * skipped. 1857 * 1858 * Return: The number of modes added or 0 if we couldn't find any. 1859 */ 1860 int drm_add_override_edid_modes(struct drm_connector *connector) 1861 { 1862 struct edid *override; 1863 int num_modes = 0; 1864 1865 override = drm_get_override_edid(connector); 1866 if (override) { 1867 drm_connector_update_edid_property(connector, override); 1868 num_modes = drm_add_edid_modes(connector, override); 1869 kfree(override); 1870 1871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1872 connector->base.id, connector->name, num_modes); 1873 } 1874 1875 return num_modes; 1876 } 1877 EXPORT_SYMBOL(drm_add_override_edid_modes); 1878 1879 /** 1880 * drm_do_get_edid - get EDID data using a custom EDID block read function 1881 * @connector: connector we're probing 1882 * @get_edid_block: EDID block read function 1883 * @data: private data passed to the block read function 1884 * 1885 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1886 * exposes a different interface to read EDID blocks this function can be used 1887 * to get EDID data using a custom block read function. 1888 * 1889 * As in the general case the DDC bus is accessible by the kernel at the I2C 1890 * level, drivers must make all reasonable efforts to expose it as an I2C 1891 * adapter and use drm_get_edid() instead of abusing this function. 1892 * 1893 * The EDID may be overridden using debugfs override_edid or firmare EDID 1894 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1895 * order. Having either of them bypasses actual EDID reads. 1896 * 1897 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1898 */ 1899 struct edid *drm_do_get_edid(struct drm_connector *connector, 1900 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1901 size_t len), 1902 void *data) 1903 { 1904 int i, j = 0, valid_extensions = 0; 1905 u8 *edid, *new; 1906 struct edid *override; 1907 1908 override = drm_get_override_edid(connector); 1909 if (override) 1910 return override; 1911 1912 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1913 return NULL; 1914 1915 /* base block fetch */ 1916 for (i = 0; i < 4; i++) { 1917 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1918 goto out; 1919 if (drm_edid_block_valid(edid, 0, false, 1920 &connector->edid_corrupt)) 1921 break; 1922 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1923 connector->null_edid_counter++; 1924 goto carp; 1925 } 1926 } 1927 if (i == 4) 1928 goto carp; 1929 1930 /* if there's no extensions, we're done */ 1931 valid_extensions = edid[0x7e]; 1932 if (valid_extensions == 0) 1933 return (struct edid *)edid; 1934 1935 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1936 if (!new) 1937 goto out; 1938 edid = new; 1939 1940 for (j = 1; j <= edid[0x7e]; j++) { 1941 u8 *block = edid + j * EDID_LENGTH; 1942 1943 for (i = 0; i < 4; i++) { 1944 if (get_edid_block(data, block, j, EDID_LENGTH)) 1945 goto out; 1946 if (drm_edid_block_valid(block, j, false, NULL)) 1947 break; 1948 } 1949 1950 if (i == 4) 1951 valid_extensions--; 1952 } 1953 1954 if (valid_extensions != edid[0x7e]) { 1955 u8 *base; 1956 1957 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1958 1959 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1960 edid[0x7e] = valid_extensions; 1961 1962 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1963 GFP_KERNEL); 1964 if (!new) 1965 goto out; 1966 1967 base = new; 1968 for (i = 0; i <= edid[0x7e]; i++) { 1969 u8 *block = edid + i * EDID_LENGTH; 1970 1971 if (!drm_edid_block_valid(block, i, false, NULL)) 1972 continue; 1973 1974 memcpy(base, block, EDID_LENGTH); 1975 base += EDID_LENGTH; 1976 } 1977 1978 kfree(edid); 1979 edid = new; 1980 } 1981 1982 return (struct edid *)edid; 1983 1984 carp: 1985 connector_bad_edid(connector, edid, 1); 1986 out: 1987 kfree(edid); 1988 return NULL; 1989 } 1990 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1991 1992 /** 1993 * drm_probe_ddc() - probe DDC presence 1994 * @adapter: I2C adapter to probe 1995 * 1996 * Return: True on success, false on failure. 1997 */ 1998 bool 1999 drm_probe_ddc(struct i2c_adapter *adapter) 2000 { 2001 unsigned char out; 2002 2003 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2004 } 2005 EXPORT_SYMBOL(drm_probe_ddc); 2006 2007 /** 2008 * drm_get_edid - get EDID data, if available 2009 * @connector: connector we're probing 2010 * @adapter: I2C adapter to use for DDC 2011 * 2012 * Poke the given I2C channel to grab EDID data if possible. If found, 2013 * attach it to the connector. 2014 * 2015 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2016 */ 2017 struct edid *drm_get_edid(struct drm_connector *connector, 2018 struct i2c_adapter *adapter) 2019 { 2020 if (connector->force == DRM_FORCE_OFF) 2021 return NULL; 2022 2023 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2024 return NULL; 2025 2026 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2027 } 2028 EXPORT_SYMBOL(drm_get_edid); 2029 2030 /** 2031 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2032 * @connector: connector we're probing 2033 * @adapter: I2C adapter to use for DDC 2034 * 2035 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2036 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2037 * switch DDC to the GPU which is retrieving EDID. 2038 * 2039 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2040 */ 2041 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2042 struct i2c_adapter *adapter) 2043 { 2044 struct pci_dev *pdev = connector->dev->pdev; 2045 struct edid *edid; 2046 2047 vga_switcheroo_lock_ddc(pdev); 2048 edid = drm_get_edid(connector, adapter); 2049 vga_switcheroo_unlock_ddc(pdev); 2050 2051 return edid; 2052 } 2053 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2054 2055 /** 2056 * drm_edid_duplicate - duplicate an EDID and the extensions 2057 * @edid: EDID to duplicate 2058 * 2059 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2060 */ 2061 struct edid *drm_edid_duplicate(const struct edid *edid) 2062 { 2063 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2064 } 2065 EXPORT_SYMBOL(drm_edid_duplicate); 2066 2067 /*** EDID parsing ***/ 2068 2069 /** 2070 * edid_vendor - match a string against EDID's obfuscated vendor field 2071 * @edid: EDID to match 2072 * @vendor: vendor string 2073 * 2074 * Returns true if @vendor is in @edid, false otherwise 2075 */ 2076 static bool edid_vendor(const struct edid *edid, const char *vendor) 2077 { 2078 char edid_vendor[3]; 2079 2080 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2081 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2082 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2083 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2084 2085 return !strncmp(edid_vendor, vendor, 3); 2086 } 2087 2088 /** 2089 * edid_get_quirks - return quirk flags for a given EDID 2090 * @edid: EDID to process 2091 * 2092 * This tells subsequent routines what fixes they need to apply. 2093 */ 2094 static u32 edid_get_quirks(const struct edid *edid) 2095 { 2096 const struct edid_quirk *quirk; 2097 int i; 2098 2099 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2100 quirk = &edid_quirk_list[i]; 2101 2102 if (edid_vendor(edid, quirk->vendor) && 2103 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2104 return quirk->quirks; 2105 } 2106 2107 return 0; 2108 } 2109 2110 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2111 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2112 2113 /** 2114 * edid_fixup_preferred - set preferred modes based on quirk list 2115 * @connector: has mode list to fix up 2116 * @quirks: quirks list 2117 * 2118 * Walk the mode list for @connector, clearing the preferred status 2119 * on existing modes and setting it anew for the right mode ala @quirks. 2120 */ 2121 static void edid_fixup_preferred(struct drm_connector *connector, 2122 u32 quirks) 2123 { 2124 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2125 int target_refresh = 0; 2126 int cur_vrefresh, preferred_vrefresh; 2127 2128 if (list_empty(&connector->probed_modes)) 2129 return; 2130 2131 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2132 target_refresh = 60; 2133 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2134 target_refresh = 75; 2135 2136 preferred_mode = list_first_entry(&connector->probed_modes, 2137 struct drm_display_mode, head); 2138 2139 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2140 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2141 2142 if (cur_mode == preferred_mode) 2143 continue; 2144 2145 /* Largest mode is preferred */ 2146 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2147 preferred_mode = cur_mode; 2148 2149 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2150 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2151 /* At a given size, try to get closest to target refresh */ 2152 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2153 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2154 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2155 preferred_mode = cur_mode; 2156 } 2157 } 2158 2159 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2160 } 2161 2162 static bool 2163 mode_is_rb(const struct drm_display_mode *mode) 2164 { 2165 return (mode->htotal - mode->hdisplay == 160) && 2166 (mode->hsync_end - mode->hdisplay == 80) && 2167 (mode->hsync_end - mode->hsync_start == 32) && 2168 (mode->vsync_start - mode->vdisplay == 3); 2169 } 2170 2171 /* 2172 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2173 * @dev: Device to duplicate against 2174 * @hsize: Mode width 2175 * @vsize: Mode height 2176 * @fresh: Mode refresh rate 2177 * @rb: Mode reduced-blanking-ness 2178 * 2179 * Walk the DMT mode list looking for a match for the given parameters. 2180 * 2181 * Return: A newly allocated copy of the mode, or NULL if not found. 2182 */ 2183 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2184 int hsize, int vsize, int fresh, 2185 bool rb) 2186 { 2187 int i; 2188 2189 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2190 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2191 if (hsize != ptr->hdisplay) 2192 continue; 2193 if (vsize != ptr->vdisplay) 2194 continue; 2195 if (fresh != drm_mode_vrefresh(ptr)) 2196 continue; 2197 if (rb != mode_is_rb(ptr)) 2198 continue; 2199 2200 return drm_mode_duplicate(dev, ptr); 2201 } 2202 2203 return NULL; 2204 } 2205 EXPORT_SYMBOL(drm_mode_find_dmt); 2206 2207 static bool is_display_descriptor(const u8 d[18], u8 tag) 2208 { 2209 return d[0] == 0x00 && d[1] == 0x00 && 2210 d[2] == 0x00 && d[3] == tag; 2211 } 2212 2213 static bool is_detailed_timing_descriptor(const u8 d[18]) 2214 { 2215 return d[0] != 0x00 || d[1] != 0x00; 2216 } 2217 2218 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2219 2220 static void 2221 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2222 { 2223 int i, n; 2224 u8 d = ext[0x02]; 2225 u8 *det_base = ext + d; 2226 2227 if (d < 4 || d > 127) 2228 return; 2229 2230 n = (127 - d) / 18; 2231 for (i = 0; i < n; i++) 2232 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2233 } 2234 2235 static void 2236 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2237 { 2238 unsigned int i, n = min((int)ext[0x02], 6); 2239 u8 *det_base = ext + 5; 2240 2241 if (ext[0x01] != 1) 2242 return; /* unknown version */ 2243 2244 for (i = 0; i < n; i++) 2245 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2246 } 2247 2248 static void 2249 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2250 { 2251 int i; 2252 struct edid *edid = (struct edid *)raw_edid; 2253 2254 if (edid == NULL) 2255 return; 2256 2257 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2258 cb(&(edid->detailed_timings[i]), closure); 2259 2260 for (i = 1; i <= raw_edid[0x7e]; i++) { 2261 u8 *ext = raw_edid + (i * EDID_LENGTH); 2262 switch (*ext) { 2263 case CEA_EXT: 2264 cea_for_each_detailed_block(ext, cb, closure); 2265 break; 2266 case VTB_EXT: 2267 vtb_for_each_detailed_block(ext, cb, closure); 2268 break; 2269 default: 2270 break; 2271 } 2272 } 2273 } 2274 2275 static void 2276 is_rb(struct detailed_timing *t, void *data) 2277 { 2278 u8 *r = (u8 *)t; 2279 2280 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2281 return; 2282 2283 if (r[15] & 0x10) 2284 *(bool *)data = true; 2285 } 2286 2287 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2288 static bool 2289 drm_monitor_supports_rb(struct edid *edid) 2290 { 2291 if (edid->revision >= 4) { 2292 bool ret = false; 2293 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2294 return ret; 2295 } 2296 2297 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2298 } 2299 2300 static void 2301 find_gtf2(struct detailed_timing *t, void *data) 2302 { 2303 u8 *r = (u8 *)t; 2304 2305 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2306 return; 2307 2308 if (r[10] == 0x02) 2309 *(u8 **)data = r; 2310 } 2311 2312 /* Secondary GTF curve kicks in above some break frequency */ 2313 static int 2314 drm_gtf2_hbreak(struct edid *edid) 2315 { 2316 u8 *r = NULL; 2317 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2318 return r ? (r[12] * 2) : 0; 2319 } 2320 2321 static int 2322 drm_gtf2_2c(struct edid *edid) 2323 { 2324 u8 *r = NULL; 2325 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2326 return r ? r[13] : 0; 2327 } 2328 2329 static int 2330 drm_gtf2_m(struct edid *edid) 2331 { 2332 u8 *r = NULL; 2333 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2334 return r ? (r[15] << 8) + r[14] : 0; 2335 } 2336 2337 static int 2338 drm_gtf2_k(struct edid *edid) 2339 { 2340 u8 *r = NULL; 2341 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2342 return r ? r[16] : 0; 2343 } 2344 2345 static int 2346 drm_gtf2_2j(struct edid *edid) 2347 { 2348 u8 *r = NULL; 2349 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2350 return r ? r[17] : 0; 2351 } 2352 2353 /** 2354 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2355 * @edid: EDID block to scan 2356 */ 2357 static int standard_timing_level(struct edid *edid) 2358 { 2359 if (edid->revision >= 2) { 2360 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2361 return LEVEL_CVT; 2362 if (drm_gtf2_hbreak(edid)) 2363 return LEVEL_GTF2; 2364 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2365 return LEVEL_GTF; 2366 } 2367 return LEVEL_DMT; 2368 } 2369 2370 /* 2371 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2372 * monitors fill with ascii space (0x20) instead. 2373 */ 2374 static int 2375 bad_std_timing(u8 a, u8 b) 2376 { 2377 return (a == 0x00 && b == 0x00) || 2378 (a == 0x01 && b == 0x01) || 2379 (a == 0x20 && b == 0x20); 2380 } 2381 2382 static int drm_mode_hsync(const struct drm_display_mode *mode) 2383 { 2384 if (mode->htotal <= 0) 2385 return 0; 2386 2387 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2388 } 2389 2390 /** 2391 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2392 * @connector: connector of for the EDID block 2393 * @edid: EDID block to scan 2394 * @t: standard timing params 2395 * 2396 * Take the standard timing params (in this case width, aspect, and refresh) 2397 * and convert them into a real mode using CVT/GTF/DMT. 2398 */ 2399 static struct drm_display_mode * 2400 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2401 struct std_timing *t) 2402 { 2403 struct drm_device *dev = connector->dev; 2404 struct drm_display_mode *m, *mode = NULL; 2405 int hsize, vsize; 2406 int vrefresh_rate; 2407 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2408 >> EDID_TIMING_ASPECT_SHIFT; 2409 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2410 >> EDID_TIMING_VFREQ_SHIFT; 2411 int timing_level = standard_timing_level(edid); 2412 2413 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2414 return NULL; 2415 2416 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2417 hsize = t->hsize * 8 + 248; 2418 /* vrefresh_rate = vfreq + 60 */ 2419 vrefresh_rate = vfreq + 60; 2420 /* the vdisplay is calculated based on the aspect ratio */ 2421 if (aspect_ratio == 0) { 2422 if (edid->revision < 3) 2423 vsize = hsize; 2424 else 2425 vsize = (hsize * 10) / 16; 2426 } else if (aspect_ratio == 1) 2427 vsize = (hsize * 3) / 4; 2428 else if (aspect_ratio == 2) 2429 vsize = (hsize * 4) / 5; 2430 else 2431 vsize = (hsize * 9) / 16; 2432 2433 /* HDTV hack, part 1 */ 2434 if (vrefresh_rate == 60 && 2435 ((hsize == 1360 && vsize == 765) || 2436 (hsize == 1368 && vsize == 769))) { 2437 hsize = 1366; 2438 vsize = 768; 2439 } 2440 2441 /* 2442 * If this connector already has a mode for this size and refresh 2443 * rate (because it came from detailed or CVT info), use that 2444 * instead. This way we don't have to guess at interlace or 2445 * reduced blanking. 2446 */ 2447 list_for_each_entry(m, &connector->probed_modes, head) 2448 if (m->hdisplay == hsize && m->vdisplay == vsize && 2449 drm_mode_vrefresh(m) == vrefresh_rate) 2450 return NULL; 2451 2452 /* HDTV hack, part 2 */ 2453 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2454 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2455 false); 2456 if (!mode) 2457 return NULL; 2458 mode->hdisplay = 1366; 2459 mode->hsync_start = mode->hsync_start - 1; 2460 mode->hsync_end = mode->hsync_end - 1; 2461 return mode; 2462 } 2463 2464 /* check whether it can be found in default mode table */ 2465 if (drm_monitor_supports_rb(edid)) { 2466 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2467 true); 2468 if (mode) 2469 return mode; 2470 } 2471 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2472 if (mode) 2473 return mode; 2474 2475 /* okay, generate it */ 2476 switch (timing_level) { 2477 case LEVEL_DMT: 2478 break; 2479 case LEVEL_GTF: 2480 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2481 break; 2482 case LEVEL_GTF2: 2483 /* 2484 * This is potentially wrong if there's ever a monitor with 2485 * more than one ranges section, each claiming a different 2486 * secondary GTF curve. Please don't do that. 2487 */ 2488 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2489 if (!mode) 2490 return NULL; 2491 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2492 drm_mode_destroy(dev, mode); 2493 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2494 vrefresh_rate, 0, 0, 2495 drm_gtf2_m(edid), 2496 drm_gtf2_2c(edid), 2497 drm_gtf2_k(edid), 2498 drm_gtf2_2j(edid)); 2499 } 2500 break; 2501 case LEVEL_CVT: 2502 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2503 false); 2504 break; 2505 } 2506 return mode; 2507 } 2508 2509 /* 2510 * EDID is delightfully ambiguous about how interlaced modes are to be 2511 * encoded. Our internal representation is of frame height, but some 2512 * HDTV detailed timings are encoded as field height. 2513 * 2514 * The format list here is from CEA, in frame size. Technically we 2515 * should be checking refresh rate too. Whatever. 2516 */ 2517 static void 2518 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2519 struct detailed_pixel_timing *pt) 2520 { 2521 int i; 2522 static const struct { 2523 int w, h; 2524 } cea_interlaced[] = { 2525 { 1920, 1080 }, 2526 { 720, 480 }, 2527 { 1440, 480 }, 2528 { 2880, 480 }, 2529 { 720, 576 }, 2530 { 1440, 576 }, 2531 { 2880, 576 }, 2532 }; 2533 2534 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2535 return; 2536 2537 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2538 if ((mode->hdisplay == cea_interlaced[i].w) && 2539 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2540 mode->vdisplay *= 2; 2541 mode->vsync_start *= 2; 2542 mode->vsync_end *= 2; 2543 mode->vtotal *= 2; 2544 mode->vtotal |= 1; 2545 } 2546 } 2547 2548 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2549 } 2550 2551 /** 2552 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2553 * @dev: DRM device (needed to create new mode) 2554 * @edid: EDID block 2555 * @timing: EDID detailed timing info 2556 * @quirks: quirks to apply 2557 * 2558 * An EDID detailed timing block contains enough info for us to create and 2559 * return a new struct drm_display_mode. 2560 */ 2561 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2562 struct edid *edid, 2563 struct detailed_timing *timing, 2564 u32 quirks) 2565 { 2566 struct drm_display_mode *mode; 2567 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2568 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2569 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2570 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2571 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2572 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2573 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2574 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2575 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2576 2577 /* ignore tiny modes */ 2578 if (hactive < 64 || vactive < 64) 2579 return NULL; 2580 2581 if (pt->misc & DRM_EDID_PT_STEREO) { 2582 DRM_DEBUG_KMS("stereo mode not supported\n"); 2583 return NULL; 2584 } 2585 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2586 DRM_DEBUG_KMS("composite sync not supported\n"); 2587 } 2588 2589 /* it is incorrect if hsync/vsync width is zero */ 2590 if (!hsync_pulse_width || !vsync_pulse_width) { 2591 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2592 "Wrong Hsync/Vsync pulse width\n"); 2593 return NULL; 2594 } 2595 2596 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2597 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2598 if (!mode) 2599 return NULL; 2600 2601 goto set_size; 2602 } 2603 2604 mode = drm_mode_create(dev); 2605 if (!mode) 2606 return NULL; 2607 2608 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2609 timing->pixel_clock = cpu_to_le16(1088); 2610 2611 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2612 2613 mode->hdisplay = hactive; 2614 mode->hsync_start = mode->hdisplay + hsync_offset; 2615 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2616 mode->htotal = mode->hdisplay + hblank; 2617 2618 mode->vdisplay = vactive; 2619 mode->vsync_start = mode->vdisplay + vsync_offset; 2620 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2621 mode->vtotal = mode->vdisplay + vblank; 2622 2623 /* Some EDIDs have bogus h/vtotal values */ 2624 if (mode->hsync_end > mode->htotal) 2625 mode->htotal = mode->hsync_end + 1; 2626 if (mode->vsync_end > mode->vtotal) 2627 mode->vtotal = mode->vsync_end + 1; 2628 2629 drm_mode_do_interlace_quirk(mode, pt); 2630 2631 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2632 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2633 } 2634 2635 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2636 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2637 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2638 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2639 2640 set_size: 2641 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2642 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2643 2644 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2645 mode->width_mm *= 10; 2646 mode->height_mm *= 10; 2647 } 2648 2649 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2650 mode->width_mm = edid->width_cm * 10; 2651 mode->height_mm = edid->height_cm * 10; 2652 } 2653 2654 mode->type = DRM_MODE_TYPE_DRIVER; 2655 drm_mode_set_name(mode); 2656 2657 return mode; 2658 } 2659 2660 static bool 2661 mode_in_hsync_range(const struct drm_display_mode *mode, 2662 struct edid *edid, u8 *t) 2663 { 2664 int hsync, hmin, hmax; 2665 2666 hmin = t[7]; 2667 if (edid->revision >= 4) 2668 hmin += ((t[4] & 0x04) ? 255 : 0); 2669 hmax = t[8]; 2670 if (edid->revision >= 4) 2671 hmax += ((t[4] & 0x08) ? 255 : 0); 2672 hsync = drm_mode_hsync(mode); 2673 2674 return (hsync <= hmax && hsync >= hmin); 2675 } 2676 2677 static bool 2678 mode_in_vsync_range(const struct drm_display_mode *mode, 2679 struct edid *edid, u8 *t) 2680 { 2681 int vsync, vmin, vmax; 2682 2683 vmin = t[5]; 2684 if (edid->revision >= 4) 2685 vmin += ((t[4] & 0x01) ? 255 : 0); 2686 vmax = t[6]; 2687 if (edid->revision >= 4) 2688 vmax += ((t[4] & 0x02) ? 255 : 0); 2689 vsync = drm_mode_vrefresh(mode); 2690 2691 return (vsync <= vmax && vsync >= vmin); 2692 } 2693 2694 static u32 2695 range_pixel_clock(struct edid *edid, u8 *t) 2696 { 2697 /* unspecified */ 2698 if (t[9] == 0 || t[9] == 255) 2699 return 0; 2700 2701 /* 1.4 with CVT support gives us real precision, yay */ 2702 if (edid->revision >= 4 && t[10] == 0x04) 2703 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2704 2705 /* 1.3 is pathetic, so fuzz up a bit */ 2706 return t[9] * 10000 + 5001; 2707 } 2708 2709 static bool 2710 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2711 struct detailed_timing *timing) 2712 { 2713 u32 max_clock; 2714 u8 *t = (u8 *)timing; 2715 2716 if (!mode_in_hsync_range(mode, edid, t)) 2717 return false; 2718 2719 if (!mode_in_vsync_range(mode, edid, t)) 2720 return false; 2721 2722 if ((max_clock = range_pixel_clock(edid, t))) 2723 if (mode->clock > max_clock) 2724 return false; 2725 2726 /* 1.4 max horizontal check */ 2727 if (edid->revision >= 4 && t[10] == 0x04) 2728 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2729 return false; 2730 2731 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2732 return false; 2733 2734 return true; 2735 } 2736 2737 static bool valid_inferred_mode(const struct drm_connector *connector, 2738 const struct drm_display_mode *mode) 2739 { 2740 const struct drm_display_mode *m; 2741 bool ok = false; 2742 2743 list_for_each_entry(m, &connector->probed_modes, head) { 2744 if (mode->hdisplay == m->hdisplay && 2745 mode->vdisplay == m->vdisplay && 2746 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2747 return false; /* duplicated */ 2748 if (mode->hdisplay <= m->hdisplay && 2749 mode->vdisplay <= m->vdisplay) 2750 ok = true; 2751 } 2752 return ok; 2753 } 2754 2755 static int 2756 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2757 struct detailed_timing *timing) 2758 { 2759 int i, modes = 0; 2760 struct drm_display_mode *newmode; 2761 struct drm_device *dev = connector->dev; 2762 2763 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2764 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2765 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2766 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2767 if (newmode) { 2768 drm_mode_probed_add(connector, newmode); 2769 modes++; 2770 } 2771 } 2772 } 2773 2774 return modes; 2775 } 2776 2777 /* fix up 1366x768 mode from 1368x768; 2778 * GFT/CVT can't express 1366 width which isn't dividable by 8 2779 */ 2780 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2781 { 2782 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2783 mode->hdisplay = 1366; 2784 mode->hsync_start--; 2785 mode->hsync_end--; 2786 drm_mode_set_name(mode); 2787 } 2788 } 2789 2790 static int 2791 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2792 struct detailed_timing *timing) 2793 { 2794 int i, modes = 0; 2795 struct drm_display_mode *newmode; 2796 struct drm_device *dev = connector->dev; 2797 2798 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2799 const struct minimode *m = &extra_modes[i]; 2800 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2801 if (!newmode) 2802 return modes; 2803 2804 drm_mode_fixup_1366x768(newmode); 2805 if (!mode_in_range(newmode, edid, timing) || 2806 !valid_inferred_mode(connector, newmode)) { 2807 drm_mode_destroy(dev, newmode); 2808 continue; 2809 } 2810 2811 drm_mode_probed_add(connector, newmode); 2812 modes++; 2813 } 2814 2815 return modes; 2816 } 2817 2818 static int 2819 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2820 struct detailed_timing *timing) 2821 { 2822 int i, modes = 0; 2823 struct drm_display_mode *newmode; 2824 struct drm_device *dev = connector->dev; 2825 bool rb = drm_monitor_supports_rb(edid); 2826 2827 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2828 const struct minimode *m = &extra_modes[i]; 2829 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2830 if (!newmode) 2831 return modes; 2832 2833 drm_mode_fixup_1366x768(newmode); 2834 if (!mode_in_range(newmode, edid, timing) || 2835 !valid_inferred_mode(connector, newmode)) { 2836 drm_mode_destroy(dev, newmode); 2837 continue; 2838 } 2839 2840 drm_mode_probed_add(connector, newmode); 2841 modes++; 2842 } 2843 2844 return modes; 2845 } 2846 2847 static void 2848 do_inferred_modes(struct detailed_timing *timing, void *c) 2849 { 2850 struct detailed_mode_closure *closure = c; 2851 struct detailed_non_pixel *data = &timing->data.other_data; 2852 struct detailed_data_monitor_range *range = &data->data.range; 2853 2854 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2855 return; 2856 2857 closure->modes += drm_dmt_modes_for_range(closure->connector, 2858 closure->edid, 2859 timing); 2860 2861 if (!version_greater(closure->edid, 1, 1)) 2862 return; /* GTF not defined yet */ 2863 2864 switch (range->flags) { 2865 case 0x02: /* secondary gtf, XXX could do more */ 2866 case 0x00: /* default gtf */ 2867 closure->modes += drm_gtf_modes_for_range(closure->connector, 2868 closure->edid, 2869 timing); 2870 break; 2871 case 0x04: /* cvt, only in 1.4+ */ 2872 if (!version_greater(closure->edid, 1, 3)) 2873 break; 2874 2875 closure->modes += drm_cvt_modes_for_range(closure->connector, 2876 closure->edid, 2877 timing); 2878 break; 2879 case 0x01: /* just the ranges, no formula */ 2880 default: 2881 break; 2882 } 2883 } 2884 2885 static int 2886 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2887 { 2888 struct detailed_mode_closure closure = { 2889 .connector = connector, 2890 .edid = edid, 2891 }; 2892 2893 if (version_greater(edid, 1, 0)) 2894 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2895 &closure); 2896 2897 return closure.modes; 2898 } 2899 2900 static int 2901 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2902 { 2903 int i, j, m, modes = 0; 2904 struct drm_display_mode *mode; 2905 u8 *est = ((u8 *)timing) + 6; 2906 2907 for (i = 0; i < 6; i++) { 2908 for (j = 7; j >= 0; j--) { 2909 m = (i * 8) + (7 - j); 2910 if (m >= ARRAY_SIZE(est3_modes)) 2911 break; 2912 if (est[i] & (1 << j)) { 2913 mode = drm_mode_find_dmt(connector->dev, 2914 est3_modes[m].w, 2915 est3_modes[m].h, 2916 est3_modes[m].r, 2917 est3_modes[m].rb); 2918 if (mode) { 2919 drm_mode_probed_add(connector, mode); 2920 modes++; 2921 } 2922 } 2923 } 2924 } 2925 2926 return modes; 2927 } 2928 2929 static void 2930 do_established_modes(struct detailed_timing *timing, void *c) 2931 { 2932 struct detailed_mode_closure *closure = c; 2933 2934 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2935 return; 2936 2937 closure->modes += drm_est3_modes(closure->connector, timing); 2938 } 2939 2940 /** 2941 * add_established_modes - get est. modes from EDID and add them 2942 * @connector: connector to add mode(s) to 2943 * @edid: EDID block to scan 2944 * 2945 * Each EDID block contains a bitmap of the supported "established modes" list 2946 * (defined above). Tease them out and add them to the global modes list. 2947 */ 2948 static int 2949 add_established_modes(struct drm_connector *connector, struct edid *edid) 2950 { 2951 struct drm_device *dev = connector->dev; 2952 unsigned long est_bits = edid->established_timings.t1 | 2953 (edid->established_timings.t2 << 8) | 2954 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2955 int i, modes = 0; 2956 struct detailed_mode_closure closure = { 2957 .connector = connector, 2958 .edid = edid, 2959 }; 2960 2961 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2962 if (est_bits & (1<<i)) { 2963 struct drm_display_mode *newmode; 2964 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2965 if (newmode) { 2966 drm_mode_probed_add(connector, newmode); 2967 modes++; 2968 } 2969 } 2970 } 2971 2972 if (version_greater(edid, 1, 0)) 2973 drm_for_each_detailed_block((u8 *)edid, 2974 do_established_modes, &closure); 2975 2976 return modes + closure.modes; 2977 } 2978 2979 static void 2980 do_standard_modes(struct detailed_timing *timing, void *c) 2981 { 2982 struct detailed_mode_closure *closure = c; 2983 struct detailed_non_pixel *data = &timing->data.other_data; 2984 struct drm_connector *connector = closure->connector; 2985 struct edid *edid = closure->edid; 2986 int i; 2987 2988 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 2989 return; 2990 2991 for (i = 0; i < 6; i++) { 2992 struct std_timing *std = &data->data.timings[i]; 2993 struct drm_display_mode *newmode; 2994 2995 newmode = drm_mode_std(connector, edid, std); 2996 if (newmode) { 2997 drm_mode_probed_add(connector, newmode); 2998 closure->modes++; 2999 } 3000 } 3001 } 3002 3003 /** 3004 * add_standard_modes - get std. modes from EDID and add them 3005 * @connector: connector to add mode(s) to 3006 * @edid: EDID block to scan 3007 * 3008 * Standard modes can be calculated using the appropriate standard (DMT, 3009 * GTF or CVT. Grab them from @edid and add them to the list. 3010 */ 3011 static int 3012 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3013 { 3014 int i, modes = 0; 3015 struct detailed_mode_closure closure = { 3016 .connector = connector, 3017 .edid = edid, 3018 }; 3019 3020 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3021 struct drm_display_mode *newmode; 3022 3023 newmode = drm_mode_std(connector, edid, 3024 &edid->standard_timings[i]); 3025 if (newmode) { 3026 drm_mode_probed_add(connector, newmode); 3027 modes++; 3028 } 3029 } 3030 3031 if (version_greater(edid, 1, 0)) 3032 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3033 &closure); 3034 3035 /* XXX should also look for standard codes in VTB blocks */ 3036 3037 return modes + closure.modes; 3038 } 3039 3040 static int drm_cvt_modes(struct drm_connector *connector, 3041 struct detailed_timing *timing) 3042 { 3043 int i, j, modes = 0; 3044 struct drm_display_mode *newmode; 3045 struct drm_device *dev = connector->dev; 3046 struct cvt_timing *cvt; 3047 const int rates[] = { 60, 85, 75, 60, 50 }; 3048 const u8 empty[3] = { 0, 0, 0 }; 3049 3050 for (i = 0; i < 4; i++) { 3051 int uninitialized_var(width), height; 3052 cvt = &(timing->data.other_data.data.cvt[i]); 3053 3054 if (!memcmp(cvt->code, empty, 3)) 3055 continue; 3056 3057 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3058 switch (cvt->code[1] & 0x0c) { 3059 case 0x00: 3060 width = height * 4 / 3; 3061 break; 3062 case 0x04: 3063 width = height * 16 / 9; 3064 break; 3065 case 0x08: 3066 width = height * 16 / 10; 3067 break; 3068 case 0x0c: 3069 width = height * 15 / 9; 3070 break; 3071 } 3072 3073 for (j = 1; j < 5; j++) { 3074 if (cvt->code[2] & (1 << j)) { 3075 newmode = drm_cvt_mode(dev, width, height, 3076 rates[j], j == 0, 3077 false, false); 3078 if (newmode) { 3079 drm_mode_probed_add(connector, newmode); 3080 modes++; 3081 } 3082 } 3083 } 3084 } 3085 3086 return modes; 3087 } 3088 3089 static void 3090 do_cvt_mode(struct detailed_timing *timing, void *c) 3091 { 3092 struct detailed_mode_closure *closure = c; 3093 3094 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3095 return; 3096 3097 closure->modes += drm_cvt_modes(closure->connector, timing); 3098 } 3099 3100 static int 3101 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3102 { 3103 struct detailed_mode_closure closure = { 3104 .connector = connector, 3105 .edid = edid, 3106 }; 3107 3108 if (version_greater(edid, 1, 2)) 3109 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3110 3111 /* XXX should also look for CVT codes in VTB blocks */ 3112 3113 return closure.modes; 3114 } 3115 3116 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3117 3118 static void 3119 do_detailed_mode(struct detailed_timing *timing, void *c) 3120 { 3121 struct detailed_mode_closure *closure = c; 3122 struct drm_display_mode *newmode; 3123 3124 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3125 return; 3126 3127 newmode = drm_mode_detailed(closure->connector->dev, 3128 closure->edid, timing, 3129 closure->quirks); 3130 if (!newmode) 3131 return; 3132 3133 if (closure->preferred) 3134 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3135 3136 /* 3137 * Detailed modes are limited to 10kHz pixel clock resolution, 3138 * so fix up anything that looks like CEA/HDMI mode, but the clock 3139 * is just slightly off. 3140 */ 3141 fixup_detailed_cea_mode_clock(newmode); 3142 3143 drm_mode_probed_add(closure->connector, newmode); 3144 closure->modes++; 3145 closure->preferred = false; 3146 } 3147 3148 /* 3149 * add_detailed_modes - Add modes from detailed timings 3150 * @connector: attached connector 3151 * @edid: EDID block to scan 3152 * @quirks: quirks to apply 3153 */ 3154 static int 3155 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3156 u32 quirks) 3157 { 3158 struct detailed_mode_closure closure = { 3159 .connector = connector, 3160 .edid = edid, 3161 .preferred = true, 3162 .quirks = quirks, 3163 }; 3164 3165 if (closure.preferred && !version_greater(edid, 1, 3)) 3166 closure.preferred = 3167 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3168 3169 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3170 3171 return closure.modes; 3172 } 3173 3174 #define AUDIO_BLOCK 0x01 3175 #define VIDEO_BLOCK 0x02 3176 #define VENDOR_BLOCK 0x03 3177 #define SPEAKER_BLOCK 0x04 3178 #define HDR_STATIC_METADATA_BLOCK 0x6 3179 #define USE_EXTENDED_TAG 0x07 3180 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3181 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3182 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3183 #define EDID_BASIC_AUDIO (1 << 6) 3184 #define EDID_CEA_YCRCB444 (1 << 5) 3185 #define EDID_CEA_YCRCB422 (1 << 4) 3186 #define EDID_CEA_VCDB_QS (1 << 6) 3187 3188 /* 3189 * Search EDID for CEA extension block. 3190 */ 3191 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3192 { 3193 u8 *edid_ext = NULL; 3194 int i; 3195 3196 /* No EDID or EDID extensions */ 3197 if (edid == NULL || edid->extensions == 0) 3198 return NULL; 3199 3200 /* Find CEA extension */ 3201 for (i = 0; i < edid->extensions; i++) { 3202 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3203 if (edid_ext[0] == ext_id) 3204 break; 3205 } 3206 3207 if (i == edid->extensions) 3208 return NULL; 3209 3210 return edid_ext; 3211 } 3212 3213 3214 static u8 *drm_find_displayid_extension(const struct edid *edid, 3215 int *length, int *idx) 3216 { 3217 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT); 3218 struct displayid_hdr *base; 3219 int ret; 3220 3221 if (!displayid) 3222 return NULL; 3223 3224 /* EDID extensions block checksum isn't for us */ 3225 *length = EDID_LENGTH - 1; 3226 *idx = 1; 3227 3228 ret = validate_displayid(displayid, *length, *idx); 3229 if (ret) 3230 return NULL; 3231 3232 base = (struct displayid_hdr *)&displayid[*idx]; 3233 *length = *idx + sizeof(*base) + base->bytes; 3234 3235 return displayid; 3236 } 3237 3238 static u8 *drm_find_cea_extension(const struct edid *edid) 3239 { 3240 int length, idx; 3241 struct displayid_block *block; 3242 u8 *cea; 3243 u8 *displayid; 3244 3245 /* Look for a top level CEA extension block */ 3246 cea = drm_find_edid_extension(edid, CEA_EXT); 3247 if (cea) 3248 return cea; 3249 3250 /* CEA blocks can also be found embedded in a DisplayID block */ 3251 displayid = drm_find_displayid_extension(edid, &length, &idx); 3252 if (!displayid) 3253 return NULL; 3254 3255 idx += sizeof(struct displayid_hdr); 3256 for_each_displayid_db(displayid, block, idx, length) { 3257 if (block->tag == DATA_BLOCK_CTA) { 3258 cea = (u8 *)block; 3259 break; 3260 } 3261 } 3262 3263 return cea; 3264 } 3265 3266 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3267 { 3268 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3269 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3270 3271 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3272 return &edid_cea_modes_1[vic - 1]; 3273 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3274 return &edid_cea_modes_193[vic - 193]; 3275 return NULL; 3276 } 3277 3278 static u8 cea_num_vics(void) 3279 { 3280 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3281 } 3282 3283 static u8 cea_next_vic(u8 vic) 3284 { 3285 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3286 vic = 193; 3287 return vic; 3288 } 3289 3290 /* 3291 * Calculate the alternate clock for the CEA mode 3292 * (60Hz vs. 59.94Hz etc.) 3293 */ 3294 static unsigned int 3295 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3296 { 3297 unsigned int clock = cea_mode->clock; 3298 3299 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3300 return clock; 3301 3302 /* 3303 * edid_cea_modes contains the 59.94Hz 3304 * variant for 240 and 480 line modes, 3305 * and the 60Hz variant otherwise. 3306 */ 3307 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3308 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3309 else 3310 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3311 3312 return clock; 3313 } 3314 3315 static bool 3316 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3317 { 3318 /* 3319 * For certain VICs the spec allows the vertical 3320 * front porch to vary by one or two lines. 3321 * 3322 * cea_modes[] stores the variant with the shortest 3323 * vertical front porch. We can adjust the mode to 3324 * get the other variants by simply increasing the 3325 * vertical front porch length. 3326 */ 3327 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3328 cea_mode_for_vic(9)->vtotal != 262 || 3329 cea_mode_for_vic(12)->vtotal != 262 || 3330 cea_mode_for_vic(13)->vtotal != 262 || 3331 cea_mode_for_vic(23)->vtotal != 312 || 3332 cea_mode_for_vic(24)->vtotal != 312 || 3333 cea_mode_for_vic(27)->vtotal != 312 || 3334 cea_mode_for_vic(28)->vtotal != 312); 3335 3336 if (((vic == 8 || vic == 9 || 3337 vic == 12 || vic == 13) && mode->vtotal < 263) || 3338 ((vic == 23 || vic == 24 || 3339 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3340 mode->vsync_start++; 3341 mode->vsync_end++; 3342 mode->vtotal++; 3343 3344 return true; 3345 } 3346 3347 return false; 3348 } 3349 3350 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3351 unsigned int clock_tolerance) 3352 { 3353 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3354 u8 vic; 3355 3356 if (!to_match->clock) 3357 return 0; 3358 3359 if (to_match->picture_aspect_ratio) 3360 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3361 3362 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3363 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3364 unsigned int clock1, clock2; 3365 3366 /* Check both 60Hz and 59.94Hz */ 3367 clock1 = cea_mode.clock; 3368 clock2 = cea_mode_alternate_clock(&cea_mode); 3369 3370 if (abs(to_match->clock - clock1) > clock_tolerance && 3371 abs(to_match->clock - clock2) > clock_tolerance) 3372 continue; 3373 3374 do { 3375 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3376 return vic; 3377 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3378 } 3379 3380 return 0; 3381 } 3382 3383 /** 3384 * drm_match_cea_mode - look for a CEA mode matching given mode 3385 * @to_match: display mode 3386 * 3387 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3388 * mode. 3389 */ 3390 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3391 { 3392 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3393 u8 vic; 3394 3395 if (!to_match->clock) 3396 return 0; 3397 3398 if (to_match->picture_aspect_ratio) 3399 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3400 3401 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3402 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3403 unsigned int clock1, clock2; 3404 3405 /* Check both 60Hz and 59.94Hz */ 3406 clock1 = cea_mode.clock; 3407 clock2 = cea_mode_alternate_clock(&cea_mode); 3408 3409 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3410 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3411 continue; 3412 3413 do { 3414 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3415 return vic; 3416 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3417 } 3418 3419 return 0; 3420 } 3421 EXPORT_SYMBOL(drm_match_cea_mode); 3422 3423 static bool drm_valid_cea_vic(u8 vic) 3424 { 3425 return cea_mode_for_vic(vic) != NULL; 3426 } 3427 3428 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3429 { 3430 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3431 3432 if (mode) 3433 return mode->picture_aspect_ratio; 3434 3435 return HDMI_PICTURE_ASPECT_NONE; 3436 } 3437 3438 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3439 { 3440 return edid_4k_modes[video_code].picture_aspect_ratio; 3441 } 3442 3443 /* 3444 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3445 * specific block). 3446 */ 3447 static unsigned int 3448 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3449 { 3450 return cea_mode_alternate_clock(hdmi_mode); 3451 } 3452 3453 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3454 unsigned int clock_tolerance) 3455 { 3456 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3457 u8 vic; 3458 3459 if (!to_match->clock) 3460 return 0; 3461 3462 if (to_match->picture_aspect_ratio) 3463 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3464 3465 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3466 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3467 unsigned int clock1, clock2; 3468 3469 /* Make sure to also match alternate clocks */ 3470 clock1 = hdmi_mode->clock; 3471 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3472 3473 if (abs(to_match->clock - clock1) > clock_tolerance && 3474 abs(to_match->clock - clock2) > clock_tolerance) 3475 continue; 3476 3477 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3478 return vic; 3479 } 3480 3481 return 0; 3482 } 3483 3484 /* 3485 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3486 * @to_match: display mode 3487 * 3488 * An HDMI mode is one defined in the HDMI vendor specific block. 3489 * 3490 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3491 */ 3492 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3493 { 3494 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3495 u8 vic; 3496 3497 if (!to_match->clock) 3498 return 0; 3499 3500 if (to_match->picture_aspect_ratio) 3501 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3502 3503 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3504 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3505 unsigned int clock1, clock2; 3506 3507 /* Make sure to also match alternate clocks */ 3508 clock1 = hdmi_mode->clock; 3509 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3510 3511 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3512 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3513 drm_mode_match(to_match, hdmi_mode, match_flags)) 3514 return vic; 3515 } 3516 return 0; 3517 } 3518 3519 static bool drm_valid_hdmi_vic(u8 vic) 3520 { 3521 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3522 } 3523 3524 static int 3525 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3526 { 3527 struct drm_device *dev = connector->dev; 3528 struct drm_display_mode *mode, *tmp; 3529 LIST_HEAD(list); 3530 int modes = 0; 3531 3532 /* Don't add CEA modes if the CEA extension block is missing */ 3533 if (!drm_find_cea_extension(edid)) 3534 return 0; 3535 3536 /* 3537 * Go through all probed modes and create a new mode 3538 * with the alternate clock for certain CEA modes. 3539 */ 3540 list_for_each_entry(mode, &connector->probed_modes, head) { 3541 const struct drm_display_mode *cea_mode = NULL; 3542 struct drm_display_mode *newmode; 3543 u8 vic = drm_match_cea_mode(mode); 3544 unsigned int clock1, clock2; 3545 3546 if (drm_valid_cea_vic(vic)) { 3547 cea_mode = cea_mode_for_vic(vic); 3548 clock2 = cea_mode_alternate_clock(cea_mode); 3549 } else { 3550 vic = drm_match_hdmi_mode(mode); 3551 if (drm_valid_hdmi_vic(vic)) { 3552 cea_mode = &edid_4k_modes[vic]; 3553 clock2 = hdmi_mode_alternate_clock(cea_mode); 3554 } 3555 } 3556 3557 if (!cea_mode) 3558 continue; 3559 3560 clock1 = cea_mode->clock; 3561 3562 if (clock1 == clock2) 3563 continue; 3564 3565 if (mode->clock != clock1 && mode->clock != clock2) 3566 continue; 3567 3568 newmode = drm_mode_duplicate(dev, cea_mode); 3569 if (!newmode) 3570 continue; 3571 3572 /* Carry over the stereo flags */ 3573 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3574 3575 /* 3576 * The current mode could be either variant. Make 3577 * sure to pick the "other" clock for the new mode. 3578 */ 3579 if (mode->clock != clock1) 3580 newmode->clock = clock1; 3581 else 3582 newmode->clock = clock2; 3583 3584 list_add_tail(&newmode->head, &list); 3585 } 3586 3587 list_for_each_entry_safe(mode, tmp, &list, head) { 3588 list_del(&mode->head); 3589 drm_mode_probed_add(connector, mode); 3590 modes++; 3591 } 3592 3593 return modes; 3594 } 3595 3596 static u8 svd_to_vic(u8 svd) 3597 { 3598 /* 0-6 bit vic, 7th bit native mode indicator */ 3599 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3600 return svd & 127; 3601 3602 return svd; 3603 } 3604 3605 static struct drm_display_mode * 3606 drm_display_mode_from_vic_index(struct drm_connector *connector, 3607 const u8 *video_db, u8 video_len, 3608 u8 video_index) 3609 { 3610 struct drm_device *dev = connector->dev; 3611 struct drm_display_mode *newmode; 3612 u8 vic; 3613 3614 if (video_db == NULL || video_index >= video_len) 3615 return NULL; 3616 3617 /* CEA modes are numbered 1..127 */ 3618 vic = svd_to_vic(video_db[video_index]); 3619 if (!drm_valid_cea_vic(vic)) 3620 return NULL; 3621 3622 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3623 if (!newmode) 3624 return NULL; 3625 3626 return newmode; 3627 } 3628 3629 /* 3630 * do_y420vdb_modes - Parse YCBCR 420 only modes 3631 * @connector: connector corresponding to the HDMI sink 3632 * @svds: start of the data block of CEA YCBCR 420 VDB 3633 * @len: length of the CEA YCBCR 420 VDB 3634 * 3635 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3636 * which contains modes which can be supported in YCBCR 420 3637 * output format only. 3638 */ 3639 static int do_y420vdb_modes(struct drm_connector *connector, 3640 const u8 *svds, u8 svds_len) 3641 { 3642 int modes = 0, i; 3643 struct drm_device *dev = connector->dev; 3644 struct drm_display_info *info = &connector->display_info; 3645 struct drm_hdmi_info *hdmi = &info->hdmi; 3646 3647 for (i = 0; i < svds_len; i++) { 3648 u8 vic = svd_to_vic(svds[i]); 3649 struct drm_display_mode *newmode; 3650 3651 if (!drm_valid_cea_vic(vic)) 3652 continue; 3653 3654 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3655 if (!newmode) 3656 break; 3657 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3658 drm_mode_probed_add(connector, newmode); 3659 modes++; 3660 } 3661 3662 if (modes > 0) 3663 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3664 return modes; 3665 } 3666 3667 /* 3668 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3669 * @connector: connector corresponding to the HDMI sink 3670 * @vic: CEA vic for the video mode to be added in the map 3671 * 3672 * Makes an entry for a videomode in the YCBCR 420 bitmap 3673 */ 3674 static void 3675 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3676 { 3677 u8 vic = svd_to_vic(svd); 3678 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3679 3680 if (!drm_valid_cea_vic(vic)) 3681 return; 3682 3683 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3684 } 3685 3686 static int 3687 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3688 { 3689 int i, modes = 0; 3690 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3691 3692 for (i = 0; i < len; i++) { 3693 struct drm_display_mode *mode; 3694 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3695 if (mode) { 3696 /* 3697 * YCBCR420 capability block contains a bitmap which 3698 * gives the index of CEA modes from CEA VDB, which 3699 * can support YCBCR 420 sampling output also (apart 3700 * from RGB/YCBCR444 etc). 3701 * For example, if the bit 0 in bitmap is set, 3702 * first mode in VDB can support YCBCR420 output too. 3703 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3704 */ 3705 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3706 drm_add_cmdb_modes(connector, db[i]); 3707 3708 drm_mode_probed_add(connector, mode); 3709 modes++; 3710 } 3711 } 3712 3713 return modes; 3714 } 3715 3716 struct stereo_mandatory_mode { 3717 int width, height, vrefresh; 3718 unsigned int flags; 3719 }; 3720 3721 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3722 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3723 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3724 { 1920, 1080, 50, 3725 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3726 { 1920, 1080, 60, 3727 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3728 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3729 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3730 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3731 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3732 }; 3733 3734 static bool 3735 stereo_match_mandatory(const struct drm_display_mode *mode, 3736 const struct stereo_mandatory_mode *stereo_mode) 3737 { 3738 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3739 3740 return mode->hdisplay == stereo_mode->width && 3741 mode->vdisplay == stereo_mode->height && 3742 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3743 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3744 } 3745 3746 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3747 { 3748 struct drm_device *dev = connector->dev; 3749 const struct drm_display_mode *mode; 3750 struct list_head stereo_modes; 3751 int modes = 0, i; 3752 3753 INIT_LIST_HEAD(&stereo_modes); 3754 3755 list_for_each_entry(mode, &connector->probed_modes, head) { 3756 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3757 const struct stereo_mandatory_mode *mandatory; 3758 struct drm_display_mode *new_mode; 3759 3760 if (!stereo_match_mandatory(mode, 3761 &stereo_mandatory_modes[i])) 3762 continue; 3763 3764 mandatory = &stereo_mandatory_modes[i]; 3765 new_mode = drm_mode_duplicate(dev, mode); 3766 if (!new_mode) 3767 continue; 3768 3769 new_mode->flags |= mandatory->flags; 3770 list_add_tail(&new_mode->head, &stereo_modes); 3771 modes++; 3772 } 3773 } 3774 3775 list_splice_tail(&stereo_modes, &connector->probed_modes); 3776 3777 return modes; 3778 } 3779 3780 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3781 { 3782 struct drm_device *dev = connector->dev; 3783 struct drm_display_mode *newmode; 3784 3785 if (!drm_valid_hdmi_vic(vic)) { 3786 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3787 return 0; 3788 } 3789 3790 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3791 if (!newmode) 3792 return 0; 3793 3794 drm_mode_probed_add(connector, newmode); 3795 3796 return 1; 3797 } 3798 3799 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3800 const u8 *video_db, u8 video_len, u8 video_index) 3801 { 3802 struct drm_display_mode *newmode; 3803 int modes = 0; 3804 3805 if (structure & (1 << 0)) { 3806 newmode = drm_display_mode_from_vic_index(connector, video_db, 3807 video_len, 3808 video_index); 3809 if (newmode) { 3810 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3811 drm_mode_probed_add(connector, newmode); 3812 modes++; 3813 } 3814 } 3815 if (structure & (1 << 6)) { 3816 newmode = drm_display_mode_from_vic_index(connector, video_db, 3817 video_len, 3818 video_index); 3819 if (newmode) { 3820 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3821 drm_mode_probed_add(connector, newmode); 3822 modes++; 3823 } 3824 } 3825 if (structure & (1 << 8)) { 3826 newmode = drm_display_mode_from_vic_index(connector, video_db, 3827 video_len, 3828 video_index); 3829 if (newmode) { 3830 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3831 drm_mode_probed_add(connector, newmode); 3832 modes++; 3833 } 3834 } 3835 3836 return modes; 3837 } 3838 3839 /* 3840 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3841 * @connector: connector corresponding to the HDMI sink 3842 * @db: start of the CEA vendor specific block 3843 * @len: length of the CEA block payload, ie. one can access up to db[len] 3844 * 3845 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3846 * also adds the stereo 3d modes when applicable. 3847 */ 3848 static int 3849 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3850 const u8 *video_db, u8 video_len) 3851 { 3852 struct drm_display_info *info = &connector->display_info; 3853 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3854 u8 vic_len, hdmi_3d_len = 0; 3855 u16 mask; 3856 u16 structure_all; 3857 3858 if (len < 8) 3859 goto out; 3860 3861 /* no HDMI_Video_Present */ 3862 if (!(db[8] & (1 << 5))) 3863 goto out; 3864 3865 /* Latency_Fields_Present */ 3866 if (db[8] & (1 << 7)) 3867 offset += 2; 3868 3869 /* I_Latency_Fields_Present */ 3870 if (db[8] & (1 << 6)) 3871 offset += 2; 3872 3873 /* the declared length is not long enough for the 2 first bytes 3874 * of additional video format capabilities */ 3875 if (len < (8 + offset + 2)) 3876 goto out; 3877 3878 /* 3D_Present */ 3879 offset++; 3880 if (db[8 + offset] & (1 << 7)) { 3881 modes += add_hdmi_mandatory_stereo_modes(connector); 3882 3883 /* 3D_Multi_present */ 3884 multi_present = (db[8 + offset] & 0x60) >> 5; 3885 } 3886 3887 offset++; 3888 vic_len = db[8 + offset] >> 5; 3889 hdmi_3d_len = db[8 + offset] & 0x1f; 3890 3891 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3892 u8 vic; 3893 3894 vic = db[9 + offset + i]; 3895 modes += add_hdmi_mode(connector, vic); 3896 } 3897 offset += 1 + vic_len; 3898 3899 if (multi_present == 1) 3900 multi_len = 2; 3901 else if (multi_present == 2) 3902 multi_len = 4; 3903 else 3904 multi_len = 0; 3905 3906 if (len < (8 + offset + hdmi_3d_len - 1)) 3907 goto out; 3908 3909 if (hdmi_3d_len < multi_len) 3910 goto out; 3911 3912 if (multi_present == 1 || multi_present == 2) { 3913 /* 3D_Structure_ALL */ 3914 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3915 3916 /* check if 3D_MASK is present */ 3917 if (multi_present == 2) 3918 mask = (db[10 + offset] << 8) | db[11 + offset]; 3919 else 3920 mask = 0xffff; 3921 3922 for (i = 0; i < 16; i++) { 3923 if (mask & (1 << i)) 3924 modes += add_3d_struct_modes(connector, 3925 structure_all, 3926 video_db, 3927 video_len, i); 3928 } 3929 } 3930 3931 offset += multi_len; 3932 3933 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3934 int vic_index; 3935 struct drm_display_mode *newmode = NULL; 3936 unsigned int newflag = 0; 3937 bool detail_present; 3938 3939 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3940 3941 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3942 break; 3943 3944 /* 2D_VIC_order_X */ 3945 vic_index = db[8 + offset + i] >> 4; 3946 3947 /* 3D_Structure_X */ 3948 switch (db[8 + offset + i] & 0x0f) { 3949 case 0: 3950 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3951 break; 3952 case 6: 3953 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3954 break; 3955 case 8: 3956 /* 3D_Detail_X */ 3957 if ((db[9 + offset + i] >> 4) == 1) 3958 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3959 break; 3960 } 3961 3962 if (newflag != 0) { 3963 newmode = drm_display_mode_from_vic_index(connector, 3964 video_db, 3965 video_len, 3966 vic_index); 3967 3968 if (newmode) { 3969 newmode->flags |= newflag; 3970 drm_mode_probed_add(connector, newmode); 3971 modes++; 3972 } 3973 } 3974 3975 if (detail_present) 3976 i++; 3977 } 3978 3979 out: 3980 if (modes > 0) 3981 info->has_hdmi_infoframe = true; 3982 return modes; 3983 } 3984 3985 static int 3986 cea_db_payload_len(const u8 *db) 3987 { 3988 return db[0] & 0x1f; 3989 } 3990 3991 static int 3992 cea_db_extended_tag(const u8 *db) 3993 { 3994 return db[1]; 3995 } 3996 3997 static int 3998 cea_db_tag(const u8 *db) 3999 { 4000 return db[0] >> 5; 4001 } 4002 4003 static int 4004 cea_revision(const u8 *cea) 4005 { 4006 /* 4007 * FIXME is this correct for the DispID variant? 4008 * The DispID spec doesn't really specify whether 4009 * this is the revision of the CEA extension or 4010 * the DispID CEA data block. And the only value 4011 * given as an example is 0. 4012 */ 4013 return cea[1]; 4014 } 4015 4016 static int 4017 cea_db_offsets(const u8 *cea, int *start, int *end) 4018 { 4019 /* DisplayID CTA extension blocks and top-level CEA EDID 4020 * block header definitions differ in the following bytes: 4021 * 1) Byte 2 of the header specifies length differently, 4022 * 2) Byte 3 is only present in the CEA top level block. 4023 * 4024 * The different definitions for byte 2 follow. 4025 * 4026 * DisplayID CTA extension block defines byte 2 as: 4027 * Number of payload bytes 4028 * 4029 * CEA EDID block defines byte 2 as: 4030 * Byte number (decimal) within this block where the 18-byte 4031 * DTDs begin. If no non-DTD data is present in this extension 4032 * block, the value should be set to 04h (the byte after next). 4033 * If set to 00h, there are no DTDs present in this block and 4034 * no non-DTD data. 4035 */ 4036 if (cea[0] == DATA_BLOCK_CTA) { 4037 /* 4038 * for_each_displayid_db() has already verified 4039 * that these stay within expected bounds. 4040 */ 4041 *start = 3; 4042 *end = *start + cea[2]; 4043 } else if (cea[0] == CEA_EXT) { 4044 /* Data block offset in CEA extension block */ 4045 *start = 4; 4046 *end = cea[2]; 4047 if (*end == 0) 4048 *end = 127; 4049 if (*end < 4 || *end > 127) 4050 return -ERANGE; 4051 } else { 4052 return -EOPNOTSUPP; 4053 } 4054 4055 return 0; 4056 } 4057 4058 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4059 { 4060 int hdmi_id; 4061 4062 if (cea_db_tag(db) != VENDOR_BLOCK) 4063 return false; 4064 4065 if (cea_db_payload_len(db) < 5) 4066 return false; 4067 4068 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4069 4070 return hdmi_id == HDMI_IEEE_OUI; 4071 } 4072 4073 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4074 { 4075 unsigned int oui; 4076 4077 if (cea_db_tag(db) != VENDOR_BLOCK) 4078 return false; 4079 4080 if (cea_db_payload_len(db) < 7) 4081 return false; 4082 4083 oui = db[3] << 16 | db[2] << 8 | db[1]; 4084 4085 return oui == HDMI_FORUM_IEEE_OUI; 4086 } 4087 4088 static bool cea_db_is_vcdb(const u8 *db) 4089 { 4090 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4091 return false; 4092 4093 if (cea_db_payload_len(db) != 2) 4094 return false; 4095 4096 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4097 return false; 4098 4099 return true; 4100 } 4101 4102 static bool cea_db_is_y420cmdb(const u8 *db) 4103 { 4104 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4105 return false; 4106 4107 if (!cea_db_payload_len(db)) 4108 return false; 4109 4110 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4111 return false; 4112 4113 return true; 4114 } 4115 4116 static bool cea_db_is_y420vdb(const u8 *db) 4117 { 4118 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4119 return false; 4120 4121 if (!cea_db_payload_len(db)) 4122 return false; 4123 4124 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4125 return false; 4126 4127 return true; 4128 } 4129 4130 #define for_each_cea_db(cea, i, start, end) \ 4131 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4132 4133 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4134 const u8 *db) 4135 { 4136 struct drm_display_info *info = &connector->display_info; 4137 struct drm_hdmi_info *hdmi = &info->hdmi; 4138 u8 map_len = cea_db_payload_len(db) - 1; 4139 u8 count; 4140 u64 map = 0; 4141 4142 if (map_len == 0) { 4143 /* All CEA modes support ycbcr420 sampling also.*/ 4144 hdmi->y420_cmdb_map = U64_MAX; 4145 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4146 return; 4147 } 4148 4149 /* 4150 * This map indicates which of the existing CEA block modes 4151 * from VDB can support YCBCR420 output too. So if bit=0 is 4152 * set, first mode from VDB can support YCBCR420 output too. 4153 * We will parse and keep this map, before parsing VDB itself 4154 * to avoid going through the same block again and again. 4155 * 4156 * Spec is not clear about max possible size of this block. 4157 * Clamping max bitmap block size at 8 bytes. Every byte can 4158 * address 8 CEA modes, in this way this map can address 4159 * 8*8 = first 64 SVDs. 4160 */ 4161 if (WARN_ON_ONCE(map_len > 8)) 4162 map_len = 8; 4163 4164 for (count = 0; count < map_len; count++) 4165 map |= (u64)db[2 + count] << (8 * count); 4166 4167 if (map) 4168 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4169 4170 hdmi->y420_cmdb_map = map; 4171 } 4172 4173 static int 4174 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4175 { 4176 const u8 *cea = drm_find_cea_extension(edid); 4177 const u8 *db, *hdmi = NULL, *video = NULL; 4178 u8 dbl, hdmi_len, video_len = 0; 4179 int modes = 0; 4180 4181 if (cea && cea_revision(cea) >= 3) { 4182 int i, start, end; 4183 4184 if (cea_db_offsets(cea, &start, &end)) 4185 return 0; 4186 4187 for_each_cea_db(cea, i, start, end) { 4188 db = &cea[i]; 4189 dbl = cea_db_payload_len(db); 4190 4191 if (cea_db_tag(db) == VIDEO_BLOCK) { 4192 video = db + 1; 4193 video_len = dbl; 4194 modes += do_cea_modes(connector, video, dbl); 4195 } else if (cea_db_is_hdmi_vsdb(db)) { 4196 hdmi = db; 4197 hdmi_len = dbl; 4198 } else if (cea_db_is_y420vdb(db)) { 4199 const u8 *vdb420 = &db[2]; 4200 4201 /* Add 4:2:0(only) modes present in EDID */ 4202 modes += do_y420vdb_modes(connector, 4203 vdb420, 4204 dbl - 1); 4205 } 4206 } 4207 } 4208 4209 /* 4210 * We parse the HDMI VSDB after having added the cea modes as we will 4211 * be patching their flags when the sink supports stereo 3D. 4212 */ 4213 if (hdmi) 4214 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4215 video_len); 4216 4217 return modes; 4218 } 4219 4220 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4221 { 4222 const struct drm_display_mode *cea_mode; 4223 int clock1, clock2, clock; 4224 u8 vic; 4225 const char *type; 4226 4227 /* 4228 * allow 5kHz clock difference either way to account for 4229 * the 10kHz clock resolution limit of detailed timings. 4230 */ 4231 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4232 if (drm_valid_cea_vic(vic)) { 4233 type = "CEA"; 4234 cea_mode = cea_mode_for_vic(vic); 4235 clock1 = cea_mode->clock; 4236 clock2 = cea_mode_alternate_clock(cea_mode); 4237 } else { 4238 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4239 if (drm_valid_hdmi_vic(vic)) { 4240 type = "HDMI"; 4241 cea_mode = &edid_4k_modes[vic]; 4242 clock1 = cea_mode->clock; 4243 clock2 = hdmi_mode_alternate_clock(cea_mode); 4244 } else { 4245 return; 4246 } 4247 } 4248 4249 /* pick whichever is closest */ 4250 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4251 clock = clock1; 4252 else 4253 clock = clock2; 4254 4255 if (mode->clock == clock) 4256 return; 4257 4258 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4259 type, vic, mode->clock, clock); 4260 mode->clock = clock; 4261 } 4262 4263 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4264 { 4265 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4266 return false; 4267 4268 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4269 return false; 4270 4271 if (cea_db_payload_len(db) < 3) 4272 return false; 4273 4274 return true; 4275 } 4276 4277 static uint8_t eotf_supported(const u8 *edid_ext) 4278 { 4279 return edid_ext[2] & 4280 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4281 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4282 BIT(HDMI_EOTF_SMPTE_ST2084) | 4283 BIT(HDMI_EOTF_BT_2100_HLG)); 4284 } 4285 4286 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4287 { 4288 return edid_ext[3] & 4289 BIT(HDMI_STATIC_METADATA_TYPE1); 4290 } 4291 4292 static void 4293 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4294 { 4295 u16 len; 4296 4297 len = cea_db_payload_len(db); 4298 4299 connector->hdr_sink_metadata.hdmi_type1.eotf = 4300 eotf_supported(db); 4301 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4302 hdr_metadata_type(db); 4303 4304 if (len >= 4) 4305 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4306 if (len >= 5) 4307 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4308 if (len >= 6) 4309 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4310 } 4311 4312 static void 4313 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4314 { 4315 u8 len = cea_db_payload_len(db); 4316 4317 if (len >= 6 && (db[6] & (1 << 7))) 4318 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4319 if (len >= 8) { 4320 connector->latency_present[0] = db[8] >> 7; 4321 connector->latency_present[1] = (db[8] >> 6) & 1; 4322 } 4323 if (len >= 9) 4324 connector->video_latency[0] = db[9]; 4325 if (len >= 10) 4326 connector->audio_latency[0] = db[10]; 4327 if (len >= 11) 4328 connector->video_latency[1] = db[11]; 4329 if (len >= 12) 4330 connector->audio_latency[1] = db[12]; 4331 4332 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4333 "video latency %d %d, " 4334 "audio latency %d %d\n", 4335 connector->latency_present[0], 4336 connector->latency_present[1], 4337 connector->video_latency[0], 4338 connector->video_latency[1], 4339 connector->audio_latency[0], 4340 connector->audio_latency[1]); 4341 } 4342 4343 static void 4344 monitor_name(struct detailed_timing *t, void *data) 4345 { 4346 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4347 return; 4348 4349 *(u8 **)data = t->data.other_data.data.str.str; 4350 } 4351 4352 static int get_monitor_name(struct edid *edid, char name[13]) 4353 { 4354 char *edid_name = NULL; 4355 int mnl; 4356 4357 if (!edid || !name) 4358 return 0; 4359 4360 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4361 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4362 if (edid_name[mnl] == 0x0a) 4363 break; 4364 4365 name[mnl] = edid_name[mnl]; 4366 } 4367 4368 return mnl; 4369 } 4370 4371 /** 4372 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4373 * @edid: monitor EDID information 4374 * @name: pointer to a character array to hold the name of the monitor 4375 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4376 * 4377 */ 4378 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4379 { 4380 int name_length; 4381 char buf[13]; 4382 4383 if (bufsize <= 0) 4384 return; 4385 4386 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4387 memcpy(name, buf, name_length); 4388 name[name_length] = '\0'; 4389 } 4390 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4391 4392 static void clear_eld(struct drm_connector *connector) 4393 { 4394 memset(connector->eld, 0, sizeof(connector->eld)); 4395 4396 connector->latency_present[0] = false; 4397 connector->latency_present[1] = false; 4398 connector->video_latency[0] = 0; 4399 connector->audio_latency[0] = 0; 4400 connector->video_latency[1] = 0; 4401 connector->audio_latency[1] = 0; 4402 } 4403 4404 /* 4405 * drm_edid_to_eld - build ELD from EDID 4406 * @connector: connector corresponding to the HDMI/DP sink 4407 * @edid: EDID to parse 4408 * 4409 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4410 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4411 */ 4412 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4413 { 4414 uint8_t *eld = connector->eld; 4415 u8 *cea; 4416 u8 *db; 4417 int total_sad_count = 0; 4418 int mnl; 4419 int dbl; 4420 4421 clear_eld(connector); 4422 4423 if (!edid) 4424 return; 4425 4426 cea = drm_find_cea_extension(edid); 4427 if (!cea) { 4428 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4429 return; 4430 } 4431 4432 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4433 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4434 4435 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4436 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4437 4438 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4439 4440 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4441 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4442 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4443 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4444 4445 if (cea_revision(cea) >= 3) { 4446 int i, start, end; 4447 int sad_count; 4448 4449 if (cea_db_offsets(cea, &start, &end)) { 4450 start = 0; 4451 end = 0; 4452 } 4453 4454 for_each_cea_db(cea, i, start, end) { 4455 db = &cea[i]; 4456 dbl = cea_db_payload_len(db); 4457 4458 switch (cea_db_tag(db)) { 4459 case AUDIO_BLOCK: 4460 /* Audio Data Block, contains SADs */ 4461 sad_count = min(dbl / 3, 15 - total_sad_count); 4462 if (sad_count >= 1) 4463 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4464 &db[1], sad_count * 3); 4465 total_sad_count += sad_count; 4466 break; 4467 case SPEAKER_BLOCK: 4468 /* Speaker Allocation Data Block */ 4469 if (dbl >= 1) 4470 eld[DRM_ELD_SPEAKER] = db[1]; 4471 break; 4472 case VENDOR_BLOCK: 4473 /* HDMI Vendor-Specific Data Block */ 4474 if (cea_db_is_hdmi_vsdb(db)) 4475 drm_parse_hdmi_vsdb_audio(connector, db); 4476 break; 4477 default: 4478 break; 4479 } 4480 } 4481 } 4482 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4483 4484 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4485 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4486 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4487 else 4488 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4489 4490 eld[DRM_ELD_BASELINE_ELD_LEN] = 4491 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4492 4493 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4494 drm_eld_size(eld), total_sad_count); 4495 } 4496 4497 /** 4498 * drm_edid_to_sad - extracts SADs from EDID 4499 * @edid: EDID to parse 4500 * @sads: pointer that will be set to the extracted SADs 4501 * 4502 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4503 * 4504 * Note: The returned pointer needs to be freed using kfree(). 4505 * 4506 * Return: The number of found SADs or negative number on error. 4507 */ 4508 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4509 { 4510 int count = 0; 4511 int i, start, end, dbl; 4512 u8 *cea; 4513 4514 cea = drm_find_cea_extension(edid); 4515 if (!cea) { 4516 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4517 return 0; 4518 } 4519 4520 if (cea_revision(cea) < 3) { 4521 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4522 return 0; 4523 } 4524 4525 if (cea_db_offsets(cea, &start, &end)) { 4526 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4527 return -EPROTO; 4528 } 4529 4530 for_each_cea_db(cea, i, start, end) { 4531 u8 *db = &cea[i]; 4532 4533 if (cea_db_tag(db) == AUDIO_BLOCK) { 4534 int j; 4535 dbl = cea_db_payload_len(db); 4536 4537 count = dbl / 3; /* SAD is 3B */ 4538 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4539 if (!*sads) 4540 return -ENOMEM; 4541 for (j = 0; j < count; j++) { 4542 u8 *sad = &db[1 + j * 3]; 4543 4544 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4545 (*sads)[j].channels = sad[0] & 0x7; 4546 (*sads)[j].freq = sad[1] & 0x7F; 4547 (*sads)[j].byte2 = sad[2]; 4548 } 4549 break; 4550 } 4551 } 4552 4553 return count; 4554 } 4555 EXPORT_SYMBOL(drm_edid_to_sad); 4556 4557 /** 4558 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4559 * @edid: EDID to parse 4560 * @sadb: pointer to the speaker block 4561 * 4562 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4563 * 4564 * Note: The returned pointer needs to be freed using kfree(). 4565 * 4566 * Return: The number of found Speaker Allocation Blocks or negative number on 4567 * error. 4568 */ 4569 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4570 { 4571 int count = 0; 4572 int i, start, end, dbl; 4573 const u8 *cea; 4574 4575 cea = drm_find_cea_extension(edid); 4576 if (!cea) { 4577 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4578 return 0; 4579 } 4580 4581 if (cea_revision(cea) < 3) { 4582 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4583 return 0; 4584 } 4585 4586 if (cea_db_offsets(cea, &start, &end)) { 4587 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4588 return -EPROTO; 4589 } 4590 4591 for_each_cea_db(cea, i, start, end) { 4592 const u8 *db = &cea[i]; 4593 4594 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4595 dbl = cea_db_payload_len(db); 4596 4597 /* Speaker Allocation Data Block */ 4598 if (dbl == 3) { 4599 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4600 if (!*sadb) 4601 return -ENOMEM; 4602 count = dbl; 4603 break; 4604 } 4605 } 4606 } 4607 4608 return count; 4609 } 4610 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4611 4612 /** 4613 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4614 * @connector: connector associated with the HDMI/DP sink 4615 * @mode: the display mode 4616 * 4617 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4618 * the sink doesn't support audio or video. 4619 */ 4620 int drm_av_sync_delay(struct drm_connector *connector, 4621 const struct drm_display_mode *mode) 4622 { 4623 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4624 int a, v; 4625 4626 if (!connector->latency_present[0]) 4627 return 0; 4628 if (!connector->latency_present[1]) 4629 i = 0; 4630 4631 a = connector->audio_latency[i]; 4632 v = connector->video_latency[i]; 4633 4634 /* 4635 * HDMI/DP sink doesn't support audio or video? 4636 */ 4637 if (a == 255 || v == 255) 4638 return 0; 4639 4640 /* 4641 * Convert raw EDID values to millisecond. 4642 * Treat unknown latency as 0ms. 4643 */ 4644 if (a) 4645 a = min(2 * (a - 1), 500); 4646 if (v) 4647 v = min(2 * (v - 1), 500); 4648 4649 return max(v - a, 0); 4650 } 4651 EXPORT_SYMBOL(drm_av_sync_delay); 4652 4653 /** 4654 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4655 * @edid: monitor EDID information 4656 * 4657 * Parse the CEA extension according to CEA-861-B. 4658 * 4659 * Drivers that have added the modes parsed from EDID to drm_display_info 4660 * should use &drm_display_info.is_hdmi instead of calling this function. 4661 * 4662 * Return: True if the monitor is HDMI, false if not or unknown. 4663 */ 4664 bool drm_detect_hdmi_monitor(struct edid *edid) 4665 { 4666 u8 *edid_ext; 4667 int i; 4668 int start_offset, end_offset; 4669 4670 edid_ext = drm_find_cea_extension(edid); 4671 if (!edid_ext) 4672 return false; 4673 4674 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4675 return false; 4676 4677 /* 4678 * Because HDMI identifier is in Vendor Specific Block, 4679 * search it from all data blocks of CEA extension. 4680 */ 4681 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4682 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4683 return true; 4684 } 4685 4686 return false; 4687 } 4688 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4689 4690 /** 4691 * drm_detect_monitor_audio - check monitor audio capability 4692 * @edid: EDID block to scan 4693 * 4694 * Monitor should have CEA extension block. 4695 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4696 * audio' only. If there is any audio extension block and supported 4697 * audio format, assume at least 'basic audio' support, even if 'basic 4698 * audio' is not defined in EDID. 4699 * 4700 * Return: True if the monitor supports audio, false otherwise. 4701 */ 4702 bool drm_detect_monitor_audio(struct edid *edid) 4703 { 4704 u8 *edid_ext; 4705 int i, j; 4706 bool has_audio = false; 4707 int start_offset, end_offset; 4708 4709 edid_ext = drm_find_cea_extension(edid); 4710 if (!edid_ext) 4711 goto end; 4712 4713 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4714 4715 if (has_audio) { 4716 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4717 goto end; 4718 } 4719 4720 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4721 goto end; 4722 4723 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4724 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4725 has_audio = true; 4726 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4727 DRM_DEBUG_KMS("CEA audio format %d\n", 4728 (edid_ext[i + j] >> 3) & 0xf); 4729 goto end; 4730 } 4731 } 4732 end: 4733 return has_audio; 4734 } 4735 EXPORT_SYMBOL(drm_detect_monitor_audio); 4736 4737 4738 /** 4739 * drm_default_rgb_quant_range - default RGB quantization range 4740 * @mode: display mode 4741 * 4742 * Determine the default RGB quantization range for the mode, 4743 * as specified in CEA-861. 4744 * 4745 * Return: The default RGB quantization range for the mode 4746 */ 4747 enum hdmi_quantization_range 4748 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4749 { 4750 /* All CEA modes other than VIC 1 use limited quantization range. */ 4751 return drm_match_cea_mode(mode) > 1 ? 4752 HDMI_QUANTIZATION_RANGE_LIMITED : 4753 HDMI_QUANTIZATION_RANGE_FULL; 4754 } 4755 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4756 4757 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4758 { 4759 struct drm_display_info *info = &connector->display_info; 4760 4761 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4762 4763 if (db[2] & EDID_CEA_VCDB_QS) 4764 info->rgb_quant_range_selectable = true; 4765 } 4766 4767 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4768 const u8 *db) 4769 { 4770 u8 dc_mask; 4771 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4772 4773 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4774 hdmi->y420_dc_modes = dc_mask; 4775 } 4776 4777 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4778 const u8 *hf_vsdb) 4779 { 4780 struct drm_display_info *display = &connector->display_info; 4781 struct drm_hdmi_info *hdmi = &display->hdmi; 4782 4783 display->has_hdmi_infoframe = true; 4784 4785 if (hf_vsdb[6] & 0x80) { 4786 hdmi->scdc.supported = true; 4787 if (hf_vsdb[6] & 0x40) 4788 hdmi->scdc.read_request = true; 4789 } 4790 4791 /* 4792 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4793 * And as per the spec, three factors confirm this: 4794 * * Availability of a HF-VSDB block in EDID (check) 4795 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4796 * * SCDC support available (let's check) 4797 * Lets check it out. 4798 */ 4799 4800 if (hf_vsdb[5]) { 4801 /* max clock is 5000 KHz times block value */ 4802 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4803 struct drm_scdc *scdc = &hdmi->scdc; 4804 4805 if (max_tmds_clock > 340000) { 4806 display->max_tmds_clock = max_tmds_clock; 4807 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4808 display->max_tmds_clock); 4809 } 4810 4811 if (scdc->supported) { 4812 scdc->scrambling.supported = true; 4813 4814 /* Few sinks support scrambling for clocks < 340M */ 4815 if ((hf_vsdb[6] & 0x8)) 4816 scdc->scrambling.low_rates = true; 4817 } 4818 } 4819 4820 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4821 } 4822 4823 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4824 const u8 *hdmi) 4825 { 4826 struct drm_display_info *info = &connector->display_info; 4827 unsigned int dc_bpc = 0; 4828 4829 /* HDMI supports at least 8 bpc */ 4830 info->bpc = 8; 4831 4832 if (cea_db_payload_len(hdmi) < 6) 4833 return; 4834 4835 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4836 dc_bpc = 10; 4837 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4838 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4839 connector->name); 4840 } 4841 4842 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4843 dc_bpc = 12; 4844 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4845 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4846 connector->name); 4847 } 4848 4849 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4850 dc_bpc = 16; 4851 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4852 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4853 connector->name); 4854 } 4855 4856 if (dc_bpc == 0) { 4857 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4858 connector->name); 4859 return; 4860 } 4861 4862 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4863 connector->name, dc_bpc); 4864 info->bpc = dc_bpc; 4865 4866 /* 4867 * Deep color support mandates RGB444 support for all video 4868 * modes and forbids YCRCB422 support for all video modes per 4869 * HDMI 1.3 spec. 4870 */ 4871 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4872 4873 /* YCRCB444 is optional according to spec. */ 4874 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4875 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4876 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4877 connector->name); 4878 } 4879 4880 /* 4881 * Spec says that if any deep color mode is supported at all, 4882 * then deep color 36 bit must be supported. 4883 */ 4884 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4885 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4886 connector->name); 4887 } 4888 } 4889 4890 static void 4891 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4892 { 4893 struct drm_display_info *info = &connector->display_info; 4894 u8 len = cea_db_payload_len(db); 4895 4896 info->is_hdmi = true; 4897 4898 if (len >= 6) 4899 info->dvi_dual = db[6] & 1; 4900 if (len >= 7) 4901 info->max_tmds_clock = db[7] * 5000; 4902 4903 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4904 "max TMDS clock %d kHz\n", 4905 info->dvi_dual, 4906 info->max_tmds_clock); 4907 4908 drm_parse_hdmi_deep_color_info(connector, db); 4909 } 4910 4911 static void drm_parse_cea_ext(struct drm_connector *connector, 4912 const struct edid *edid) 4913 { 4914 struct drm_display_info *info = &connector->display_info; 4915 const u8 *edid_ext; 4916 int i, start, end; 4917 4918 edid_ext = drm_find_cea_extension(edid); 4919 if (!edid_ext) 4920 return; 4921 4922 info->cea_rev = edid_ext[1]; 4923 4924 /* The existence of a CEA block should imply RGB support */ 4925 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4926 if (edid_ext[3] & EDID_CEA_YCRCB444) 4927 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4928 if (edid_ext[3] & EDID_CEA_YCRCB422) 4929 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4930 4931 if (cea_db_offsets(edid_ext, &start, &end)) 4932 return; 4933 4934 for_each_cea_db(edid_ext, i, start, end) { 4935 const u8 *db = &edid_ext[i]; 4936 4937 if (cea_db_is_hdmi_vsdb(db)) 4938 drm_parse_hdmi_vsdb_video(connector, db); 4939 if (cea_db_is_hdmi_forum_vsdb(db)) 4940 drm_parse_hdmi_forum_vsdb(connector, db); 4941 if (cea_db_is_y420cmdb(db)) 4942 drm_parse_y420cmdb_bitmap(connector, db); 4943 if (cea_db_is_vcdb(db)) 4944 drm_parse_vcdb(connector, db); 4945 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4946 drm_parse_hdr_metadata_block(connector, db); 4947 } 4948 } 4949 4950 static 4951 void get_monitor_range(struct detailed_timing *timing, 4952 void *info_monitor_range) 4953 { 4954 struct drm_monitor_range_info *monitor_range = info_monitor_range; 4955 const struct detailed_non_pixel *data = &timing->data.other_data; 4956 const struct detailed_data_monitor_range *range = &data->data.range; 4957 4958 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 4959 return; 4960 4961 /* 4962 * Check for flag range limits only. If flag == 1 then 4963 * no additional timing information provided. 4964 * Default GTF, GTF Secondary curve and CVT are not 4965 * supported 4966 */ 4967 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 4968 return; 4969 4970 monitor_range->min_vfreq = range->min_vfreq; 4971 monitor_range->max_vfreq = range->max_vfreq; 4972 } 4973 4974 static 4975 void drm_get_monitor_range(struct drm_connector *connector, 4976 const struct edid *edid) 4977 { 4978 struct drm_display_info *info = &connector->display_info; 4979 4980 if (!version_greater(edid, 1, 1)) 4981 return; 4982 4983 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 4984 &info->monitor_range); 4985 4986 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 4987 info->monitor_range.min_vfreq, 4988 info->monitor_range.max_vfreq); 4989 } 4990 4991 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4992 * all of the values which would have been set from EDID 4993 */ 4994 void 4995 drm_reset_display_info(struct drm_connector *connector) 4996 { 4997 struct drm_display_info *info = &connector->display_info; 4998 4999 info->width_mm = 0; 5000 info->height_mm = 0; 5001 5002 info->bpc = 0; 5003 info->color_formats = 0; 5004 info->cea_rev = 0; 5005 info->max_tmds_clock = 0; 5006 info->dvi_dual = false; 5007 info->is_hdmi = false; 5008 info->has_hdmi_infoframe = false; 5009 info->rgb_quant_range_selectable = false; 5010 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5011 5012 info->non_desktop = 0; 5013 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5014 } 5015 5016 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5017 { 5018 struct drm_display_info *info = &connector->display_info; 5019 5020 u32 quirks = edid_get_quirks(edid); 5021 5022 drm_reset_display_info(connector); 5023 5024 info->width_mm = edid->width_cm * 10; 5025 info->height_mm = edid->height_cm * 10; 5026 5027 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5028 5029 drm_get_monitor_range(connector, edid); 5030 5031 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5032 5033 if (edid->revision < 3) 5034 return quirks; 5035 5036 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5037 return quirks; 5038 5039 drm_parse_cea_ext(connector, edid); 5040 5041 /* 5042 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5043 * 5044 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5045 * tells us to assume 8 bpc color depth if the EDID doesn't have 5046 * extensions which tell otherwise. 5047 */ 5048 if (info->bpc == 0 && edid->revision == 3 && 5049 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5050 info->bpc = 8; 5051 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5052 connector->name, info->bpc); 5053 } 5054 5055 /* Only defined for 1.4 with digital displays */ 5056 if (edid->revision < 4) 5057 return quirks; 5058 5059 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5060 case DRM_EDID_DIGITAL_DEPTH_6: 5061 info->bpc = 6; 5062 break; 5063 case DRM_EDID_DIGITAL_DEPTH_8: 5064 info->bpc = 8; 5065 break; 5066 case DRM_EDID_DIGITAL_DEPTH_10: 5067 info->bpc = 10; 5068 break; 5069 case DRM_EDID_DIGITAL_DEPTH_12: 5070 info->bpc = 12; 5071 break; 5072 case DRM_EDID_DIGITAL_DEPTH_14: 5073 info->bpc = 14; 5074 break; 5075 case DRM_EDID_DIGITAL_DEPTH_16: 5076 info->bpc = 16; 5077 break; 5078 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5079 default: 5080 info->bpc = 0; 5081 break; 5082 } 5083 5084 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5085 connector->name, info->bpc); 5086 5087 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5088 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5089 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5090 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5091 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5092 return quirks; 5093 } 5094 5095 static int validate_displayid(u8 *displayid, int length, int idx) 5096 { 5097 int i, dispid_length; 5098 u8 csum = 0; 5099 struct displayid_hdr *base; 5100 5101 base = (struct displayid_hdr *)&displayid[idx]; 5102 5103 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5104 base->rev, base->bytes, base->prod_id, base->ext_count); 5105 5106 /* +1 for DispID checksum */ 5107 dispid_length = sizeof(*base) + base->bytes + 1; 5108 if (dispid_length > length - idx) 5109 return -EINVAL; 5110 5111 for (i = 0; i < dispid_length; i++) 5112 csum += displayid[idx + i]; 5113 if (csum) { 5114 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5115 return -EINVAL; 5116 } 5117 5118 return 0; 5119 } 5120 5121 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5122 struct displayid_detailed_timings_1 *timings) 5123 { 5124 struct drm_display_mode *mode; 5125 unsigned pixel_clock = (timings->pixel_clock[0] | 5126 (timings->pixel_clock[1] << 8) | 5127 (timings->pixel_clock[2] << 16)) + 1; 5128 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5129 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5130 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5131 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5132 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5133 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5134 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5135 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5136 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5137 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5138 mode = drm_mode_create(dev); 5139 if (!mode) 5140 return NULL; 5141 5142 mode->clock = pixel_clock * 10; 5143 mode->hdisplay = hactive; 5144 mode->hsync_start = mode->hdisplay + hsync; 5145 mode->hsync_end = mode->hsync_start + hsync_width; 5146 mode->htotal = mode->hdisplay + hblank; 5147 5148 mode->vdisplay = vactive; 5149 mode->vsync_start = mode->vdisplay + vsync; 5150 mode->vsync_end = mode->vsync_start + vsync_width; 5151 mode->vtotal = mode->vdisplay + vblank; 5152 5153 mode->flags = 0; 5154 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5155 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5156 mode->type = DRM_MODE_TYPE_DRIVER; 5157 5158 if (timings->flags & 0x80) 5159 mode->type |= DRM_MODE_TYPE_PREFERRED; 5160 drm_mode_set_name(mode); 5161 5162 return mode; 5163 } 5164 5165 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5166 struct displayid_block *block) 5167 { 5168 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5169 int i; 5170 int num_timings; 5171 struct drm_display_mode *newmode; 5172 int num_modes = 0; 5173 /* blocks must be multiple of 20 bytes length */ 5174 if (block->num_bytes % 20) 5175 return 0; 5176 5177 num_timings = block->num_bytes / 20; 5178 for (i = 0; i < num_timings; i++) { 5179 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5180 5181 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5182 if (!newmode) 5183 continue; 5184 5185 drm_mode_probed_add(connector, newmode); 5186 num_modes++; 5187 } 5188 return num_modes; 5189 } 5190 5191 static int add_displayid_detailed_modes(struct drm_connector *connector, 5192 struct edid *edid) 5193 { 5194 u8 *displayid; 5195 int length, idx; 5196 struct displayid_block *block; 5197 int num_modes = 0; 5198 5199 displayid = drm_find_displayid_extension(edid, &length, &idx); 5200 if (!displayid) 5201 return 0; 5202 5203 idx += sizeof(struct displayid_hdr); 5204 for_each_displayid_db(displayid, block, idx, length) { 5205 switch (block->tag) { 5206 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5207 num_modes += add_displayid_detailed_1_modes(connector, block); 5208 break; 5209 } 5210 } 5211 return num_modes; 5212 } 5213 5214 /** 5215 * drm_add_edid_modes - add modes from EDID data, if available 5216 * @connector: connector we're probing 5217 * @edid: EDID data 5218 * 5219 * Add the specified modes to the connector's mode list. Also fills out the 5220 * &drm_display_info structure and ELD in @connector with any information which 5221 * can be derived from the edid. 5222 * 5223 * Return: The number of modes added or 0 if we couldn't find any. 5224 */ 5225 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5226 { 5227 int num_modes = 0; 5228 u32 quirks; 5229 5230 if (edid == NULL) { 5231 clear_eld(connector); 5232 return 0; 5233 } 5234 if (!drm_edid_is_valid(edid)) { 5235 clear_eld(connector); 5236 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5237 connector->name); 5238 return 0; 5239 } 5240 5241 drm_edid_to_eld(connector, edid); 5242 5243 /* 5244 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5245 * To avoid multiple parsing of same block, lets parse that map 5246 * from sink info, before parsing CEA modes. 5247 */ 5248 quirks = drm_add_display_info(connector, edid); 5249 5250 /* 5251 * EDID spec says modes should be preferred in this order: 5252 * - preferred detailed mode 5253 * - other detailed modes from base block 5254 * - detailed modes from extension blocks 5255 * - CVT 3-byte code modes 5256 * - standard timing codes 5257 * - established timing codes 5258 * - modes inferred from GTF or CVT range information 5259 * 5260 * We get this pretty much right. 5261 * 5262 * XXX order for additional mode types in extension blocks? 5263 */ 5264 num_modes += add_detailed_modes(connector, edid, quirks); 5265 num_modes += add_cvt_modes(connector, edid); 5266 num_modes += add_standard_modes(connector, edid); 5267 num_modes += add_established_modes(connector, edid); 5268 num_modes += add_cea_modes(connector, edid); 5269 num_modes += add_alternate_cea_modes(connector, edid); 5270 num_modes += add_displayid_detailed_modes(connector, edid); 5271 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5272 num_modes += add_inferred_modes(connector, edid); 5273 5274 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5275 edid_fixup_preferred(connector, quirks); 5276 5277 if (quirks & EDID_QUIRK_FORCE_6BPC) 5278 connector->display_info.bpc = 6; 5279 5280 if (quirks & EDID_QUIRK_FORCE_8BPC) 5281 connector->display_info.bpc = 8; 5282 5283 if (quirks & EDID_QUIRK_FORCE_10BPC) 5284 connector->display_info.bpc = 10; 5285 5286 if (quirks & EDID_QUIRK_FORCE_12BPC) 5287 connector->display_info.bpc = 12; 5288 5289 return num_modes; 5290 } 5291 EXPORT_SYMBOL(drm_add_edid_modes); 5292 5293 /** 5294 * drm_add_modes_noedid - add modes for the connectors without EDID 5295 * @connector: connector we're probing 5296 * @hdisplay: the horizontal display limit 5297 * @vdisplay: the vertical display limit 5298 * 5299 * Add the specified modes to the connector's mode list. Only when the 5300 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5301 * 5302 * Return: The number of modes added or 0 if we couldn't find any. 5303 */ 5304 int drm_add_modes_noedid(struct drm_connector *connector, 5305 int hdisplay, int vdisplay) 5306 { 5307 int i, count, num_modes = 0; 5308 struct drm_display_mode *mode; 5309 struct drm_device *dev = connector->dev; 5310 5311 count = ARRAY_SIZE(drm_dmt_modes); 5312 if (hdisplay < 0) 5313 hdisplay = 0; 5314 if (vdisplay < 0) 5315 vdisplay = 0; 5316 5317 for (i = 0; i < count; i++) { 5318 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5319 if (hdisplay && vdisplay) { 5320 /* 5321 * Only when two are valid, they will be used to check 5322 * whether the mode should be added to the mode list of 5323 * the connector. 5324 */ 5325 if (ptr->hdisplay > hdisplay || 5326 ptr->vdisplay > vdisplay) 5327 continue; 5328 } 5329 if (drm_mode_vrefresh(ptr) > 61) 5330 continue; 5331 mode = drm_mode_duplicate(dev, ptr); 5332 if (mode) { 5333 drm_mode_probed_add(connector, mode); 5334 num_modes++; 5335 } 5336 } 5337 return num_modes; 5338 } 5339 EXPORT_SYMBOL(drm_add_modes_noedid); 5340 5341 /** 5342 * drm_set_preferred_mode - Sets the preferred mode of a connector 5343 * @connector: connector whose mode list should be processed 5344 * @hpref: horizontal resolution of preferred mode 5345 * @vpref: vertical resolution of preferred mode 5346 * 5347 * Marks a mode as preferred if it matches the resolution specified by @hpref 5348 * and @vpref. 5349 */ 5350 void drm_set_preferred_mode(struct drm_connector *connector, 5351 int hpref, int vpref) 5352 { 5353 struct drm_display_mode *mode; 5354 5355 list_for_each_entry(mode, &connector->probed_modes, head) { 5356 if (mode->hdisplay == hpref && 5357 mode->vdisplay == vpref) 5358 mode->type |= DRM_MODE_TYPE_PREFERRED; 5359 } 5360 } 5361 EXPORT_SYMBOL(drm_set_preferred_mode); 5362 5363 static bool is_hdmi2_sink(const struct drm_connector *connector) 5364 { 5365 /* 5366 * FIXME: sil-sii8620 doesn't have a connector around when 5367 * we need one, so we have to be prepared for a NULL connector. 5368 */ 5369 if (!connector) 5370 return true; 5371 5372 return connector->display_info.hdmi.scdc.supported || 5373 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5374 } 5375 5376 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5377 { 5378 return sink_eotf & BIT(output_eotf); 5379 } 5380 5381 /** 5382 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5383 * HDR metadata from userspace 5384 * @frame: HDMI DRM infoframe 5385 * @conn_state: Connector state containing HDR metadata 5386 * 5387 * Return: 0 on success or a negative error code on failure. 5388 */ 5389 int 5390 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5391 const struct drm_connector_state *conn_state) 5392 { 5393 struct drm_connector *connector; 5394 struct hdr_output_metadata *hdr_metadata; 5395 int err; 5396 5397 if (!frame || !conn_state) 5398 return -EINVAL; 5399 5400 connector = conn_state->connector; 5401 5402 if (!conn_state->hdr_output_metadata) 5403 return -EINVAL; 5404 5405 hdr_metadata = conn_state->hdr_output_metadata->data; 5406 5407 if (!hdr_metadata || !connector) 5408 return -EINVAL; 5409 5410 /* Sink EOTF is Bit map while infoframe is absolute values */ 5411 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5412 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5413 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5414 return -EINVAL; 5415 } 5416 5417 err = hdmi_drm_infoframe_init(frame); 5418 if (err < 0) 5419 return err; 5420 5421 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5422 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5423 5424 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5425 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5426 BUILD_BUG_ON(sizeof(frame->white_point) != 5427 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5428 5429 memcpy(&frame->display_primaries, 5430 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5431 sizeof(frame->display_primaries)); 5432 5433 memcpy(&frame->white_point, 5434 &hdr_metadata->hdmi_metadata_type1.white_point, 5435 sizeof(frame->white_point)); 5436 5437 frame->max_display_mastering_luminance = 5438 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5439 frame->min_display_mastering_luminance = 5440 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5441 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5442 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5443 5444 return 0; 5445 } 5446 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5447 5448 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5449 const struct drm_display_mode *mode) 5450 { 5451 bool has_hdmi_infoframe = connector ? 5452 connector->display_info.has_hdmi_infoframe : false; 5453 5454 if (!has_hdmi_infoframe) 5455 return 0; 5456 5457 /* No HDMI VIC when signalling 3D video format */ 5458 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5459 return 0; 5460 5461 return drm_match_hdmi_mode(mode); 5462 } 5463 5464 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5465 const struct drm_display_mode *mode) 5466 { 5467 u8 vic; 5468 5469 /* 5470 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5471 * we should send its VIC in vendor infoframes, else send the 5472 * VIC in AVI infoframes. Lets check if this mode is present in 5473 * HDMI 1.4b 4K modes 5474 */ 5475 if (drm_mode_hdmi_vic(connector, mode)) 5476 return 0; 5477 5478 vic = drm_match_cea_mode(mode); 5479 5480 /* 5481 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5482 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5483 * have to make sure we dont break HDMI 1.4 sinks. 5484 */ 5485 if (!is_hdmi2_sink(connector) && vic > 64) 5486 return 0; 5487 5488 return vic; 5489 } 5490 5491 /** 5492 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5493 * data from a DRM display mode 5494 * @frame: HDMI AVI infoframe 5495 * @connector: the connector 5496 * @mode: DRM display mode 5497 * 5498 * Return: 0 on success or a negative error code on failure. 5499 */ 5500 int 5501 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5502 const struct drm_connector *connector, 5503 const struct drm_display_mode *mode) 5504 { 5505 enum hdmi_picture_aspect picture_aspect; 5506 u8 vic, hdmi_vic; 5507 5508 if (!frame || !mode) 5509 return -EINVAL; 5510 5511 hdmi_avi_infoframe_init(frame); 5512 5513 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5514 frame->pixel_repeat = 1; 5515 5516 vic = drm_mode_cea_vic(connector, mode); 5517 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5518 5519 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5520 5521 /* 5522 * As some drivers don't support atomic, we can't use connector state. 5523 * So just initialize the frame with default values, just the same way 5524 * as it's done with other properties here. 5525 */ 5526 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5527 frame->itc = 0; 5528 5529 /* 5530 * Populate picture aspect ratio from either 5531 * user input (if specified) or from the CEA/HDMI mode lists. 5532 */ 5533 picture_aspect = mode->picture_aspect_ratio; 5534 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5535 if (vic) 5536 picture_aspect = drm_get_cea_aspect_ratio(vic); 5537 else if (hdmi_vic) 5538 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5539 } 5540 5541 /* 5542 * The infoframe can't convey anything but none, 4:3 5543 * and 16:9, so if the user has asked for anything else 5544 * we can only satisfy it by specifying the right VIC. 5545 */ 5546 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5547 if (vic) { 5548 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5549 return -EINVAL; 5550 } else if (hdmi_vic) { 5551 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5552 return -EINVAL; 5553 } else { 5554 return -EINVAL; 5555 } 5556 5557 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5558 } 5559 5560 frame->video_code = vic; 5561 frame->picture_aspect = picture_aspect; 5562 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5563 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5564 5565 return 0; 5566 } 5567 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5568 5569 /* HDMI Colorspace Spec Definitions */ 5570 #define FULL_COLORIMETRY_MASK 0x1FF 5571 #define NORMAL_COLORIMETRY_MASK 0x3 5572 #define EXTENDED_COLORIMETRY_MASK 0x7 5573 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5574 5575 #define C(x) ((x) << 0) 5576 #define EC(x) ((x) << 2) 5577 #define ACE(x) ((x) << 5) 5578 5579 #define HDMI_COLORIMETRY_NO_DATA 0x0 5580 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5581 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5582 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5583 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5584 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5585 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5586 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5587 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5588 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5589 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5590 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5591 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5592 5593 static const u32 hdmi_colorimetry_val[] = { 5594 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5595 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5596 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5597 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5598 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5599 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5600 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5601 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5602 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5603 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5604 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5605 }; 5606 5607 #undef C 5608 #undef EC 5609 #undef ACE 5610 5611 /** 5612 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5613 * colorspace information 5614 * @frame: HDMI AVI infoframe 5615 * @conn_state: connector state 5616 */ 5617 void 5618 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5619 const struct drm_connector_state *conn_state) 5620 { 5621 u32 colorimetry_val; 5622 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5623 5624 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5625 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5626 else 5627 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5628 5629 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5630 /* 5631 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5632 * structure and extend it in drivers/video/hdmi 5633 */ 5634 frame->extended_colorimetry = (colorimetry_val >> 2) & 5635 EXTENDED_COLORIMETRY_MASK; 5636 } 5637 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5638 5639 /** 5640 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5641 * quantization range information 5642 * @frame: HDMI AVI infoframe 5643 * @connector: the connector 5644 * @mode: DRM display mode 5645 * @rgb_quant_range: RGB quantization range (Q) 5646 */ 5647 void 5648 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5649 const struct drm_connector *connector, 5650 const struct drm_display_mode *mode, 5651 enum hdmi_quantization_range rgb_quant_range) 5652 { 5653 const struct drm_display_info *info = &connector->display_info; 5654 5655 /* 5656 * CEA-861: 5657 * "A Source shall not send a non-zero Q value that does not correspond 5658 * to the default RGB Quantization Range for the transmitted Picture 5659 * unless the Sink indicates support for the Q bit in a Video 5660 * Capabilities Data Block." 5661 * 5662 * HDMI 2.0 recommends sending non-zero Q when it does match the 5663 * default RGB quantization range for the mode, even when QS=0. 5664 */ 5665 if (info->rgb_quant_range_selectable || 5666 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5667 frame->quantization_range = rgb_quant_range; 5668 else 5669 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5670 5671 /* 5672 * CEA-861-F: 5673 * "When transmitting any RGB colorimetry, the Source should set the 5674 * YQ-field to match the RGB Quantization Range being transmitted 5675 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5676 * set YQ=1) and the Sink shall ignore the YQ-field." 5677 * 5678 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5679 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5680 * good way to tell which version of CEA-861 the sink supports, so 5681 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5682 * on on CEA-861-F. 5683 */ 5684 if (!is_hdmi2_sink(connector) || 5685 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5686 frame->ycc_quantization_range = 5687 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5688 else 5689 frame->ycc_quantization_range = 5690 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5691 } 5692 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5693 5694 /** 5695 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5696 * bar information 5697 * @frame: HDMI AVI infoframe 5698 * @conn_state: connector state 5699 */ 5700 void 5701 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5702 const struct drm_connector_state *conn_state) 5703 { 5704 frame->right_bar = conn_state->tv.margins.right; 5705 frame->left_bar = conn_state->tv.margins.left; 5706 frame->top_bar = conn_state->tv.margins.top; 5707 frame->bottom_bar = conn_state->tv.margins.bottom; 5708 } 5709 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5710 5711 static enum hdmi_3d_structure 5712 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5713 { 5714 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5715 5716 switch (layout) { 5717 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5718 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5719 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5720 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5721 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5722 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5723 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5724 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5725 case DRM_MODE_FLAG_3D_L_DEPTH: 5726 return HDMI_3D_STRUCTURE_L_DEPTH; 5727 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5728 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5729 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5730 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5731 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5732 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5733 default: 5734 return HDMI_3D_STRUCTURE_INVALID; 5735 } 5736 } 5737 5738 /** 5739 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5740 * data from a DRM display mode 5741 * @frame: HDMI vendor infoframe 5742 * @connector: the connector 5743 * @mode: DRM display mode 5744 * 5745 * Note that there's is a need to send HDMI vendor infoframes only when using a 5746 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5747 * function will return -EINVAL, error that can be safely ignored. 5748 * 5749 * Return: 0 on success or a negative error code on failure. 5750 */ 5751 int 5752 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5753 const struct drm_connector *connector, 5754 const struct drm_display_mode *mode) 5755 { 5756 /* 5757 * FIXME: sil-sii8620 doesn't have a connector around when 5758 * we need one, so we have to be prepared for a NULL connector. 5759 */ 5760 bool has_hdmi_infoframe = connector ? 5761 connector->display_info.has_hdmi_infoframe : false; 5762 int err; 5763 5764 if (!frame || !mode) 5765 return -EINVAL; 5766 5767 if (!has_hdmi_infoframe) 5768 return -EINVAL; 5769 5770 err = hdmi_vendor_infoframe_init(frame); 5771 if (err < 0) 5772 return err; 5773 5774 /* 5775 * Even if it's not absolutely necessary to send the infoframe 5776 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5777 * know that the sink can handle it. This is based on a 5778 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5779 * have trouble realizing that they shuld switch from 3D to 2D 5780 * mode if the source simply stops sending the infoframe when 5781 * it wants to switch from 3D to 2D. 5782 */ 5783 frame->vic = drm_mode_hdmi_vic(connector, mode); 5784 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5785 5786 return 0; 5787 } 5788 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5789 5790 static int drm_parse_tiled_block(struct drm_connector *connector, 5791 const struct displayid_block *block) 5792 { 5793 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5794 u16 w, h; 5795 u8 tile_v_loc, tile_h_loc; 5796 u8 num_v_tile, num_h_tile; 5797 struct drm_tile_group *tg; 5798 5799 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5800 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5801 5802 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5803 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5804 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5805 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5806 5807 connector->has_tile = true; 5808 if (tile->tile_cap & 0x80) 5809 connector->tile_is_single_monitor = true; 5810 5811 connector->num_h_tile = num_h_tile + 1; 5812 connector->num_v_tile = num_v_tile + 1; 5813 connector->tile_h_loc = tile_h_loc; 5814 connector->tile_v_loc = tile_v_loc; 5815 connector->tile_h_size = w + 1; 5816 connector->tile_v_size = h + 1; 5817 5818 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5819 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5820 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5821 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5822 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5823 5824 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5825 if (!tg) { 5826 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5827 } 5828 if (!tg) 5829 return -ENOMEM; 5830 5831 if (connector->tile_group != tg) { 5832 /* if we haven't got a pointer, 5833 take the reference, drop ref to old tile group */ 5834 if (connector->tile_group) { 5835 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5836 } 5837 connector->tile_group = tg; 5838 } else 5839 /* if same tile group, then release the ref we just took. */ 5840 drm_mode_put_tile_group(connector->dev, tg); 5841 return 0; 5842 } 5843 5844 static int drm_displayid_parse_tiled(struct drm_connector *connector, 5845 const u8 *displayid, int length, int idx) 5846 { 5847 const struct displayid_block *block; 5848 int ret; 5849 5850 idx += sizeof(struct displayid_hdr); 5851 for_each_displayid_db(displayid, block, idx, length) { 5852 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5853 block->tag, block->rev, block->num_bytes); 5854 5855 switch (block->tag) { 5856 case DATA_BLOCK_TILED_DISPLAY: 5857 ret = drm_parse_tiled_block(connector, block); 5858 if (ret) 5859 return ret; 5860 break; 5861 default: 5862 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5863 break; 5864 } 5865 } 5866 return 0; 5867 } 5868 5869 void drm_update_tile_info(struct drm_connector *connector, 5870 const struct edid *edid) 5871 { 5872 const void *displayid = NULL; 5873 int length, idx; 5874 int ret; 5875 5876 connector->has_tile = false; 5877 displayid = drm_find_displayid_extension(edid, &length, &idx); 5878 if (!displayid) { 5879 /* drop reference to any tile group we had */ 5880 goto out_drop_ref; 5881 } 5882 5883 ret = drm_displayid_parse_tiled(connector, displayid, length, idx); 5884 if (ret < 0) 5885 goto out_drop_ref; 5886 if (!connector->has_tile) 5887 goto out_drop_ref; 5888 return; 5889 out_drop_ref: 5890 if (connector->tile_group) { 5891 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5892 connector->tile_group = NULL; 5893 } 5894 return; 5895 } 5896