1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static int validate_displayid(u8 *displayid, int length, int idx); 1588 1589 static int drm_edid_block_checksum(const u8 *raw_edid) 1590 { 1591 int i; 1592 u8 csum = 0, crc = 0; 1593 1594 for (i = 0; i < EDID_LENGTH - 1; i++) 1595 csum += raw_edid[i]; 1596 1597 crc = 0x100 - csum; 1598 1599 return crc; 1600 } 1601 1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1603 { 1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1605 return true; 1606 else 1607 return false; 1608 } 1609 1610 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1611 { 1612 if (memchr_inv(in_edid, 0, length)) 1613 return false; 1614 1615 return true; 1616 } 1617 1618 /** 1619 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1620 * @raw_edid: pointer to raw EDID block 1621 * @block: type of block to validate (0 for base, extension otherwise) 1622 * @print_bad_edid: if true, dump bad EDID blocks to the console 1623 * @edid_corrupt: if true, the header or checksum is invalid 1624 * 1625 * Validate a base or extension EDID block and optionally dump bad blocks to 1626 * the console. 1627 * 1628 * Return: True if the block is valid, false otherwise. 1629 */ 1630 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1631 bool *edid_corrupt) 1632 { 1633 u8 csum; 1634 struct edid *edid = (struct edid *)raw_edid; 1635 1636 if (WARN_ON(!raw_edid)) 1637 return false; 1638 1639 if (edid_fixup > 8 || edid_fixup < 0) 1640 edid_fixup = 6; 1641 1642 if (block == 0) { 1643 int score = drm_edid_header_is_valid(raw_edid); 1644 if (score == 8) { 1645 if (edid_corrupt) 1646 *edid_corrupt = false; 1647 } else if (score >= edid_fixup) { 1648 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1649 * The corrupt flag needs to be set here otherwise, the 1650 * fix-up code here will correct the problem, the 1651 * checksum is correct and the test fails 1652 */ 1653 if (edid_corrupt) 1654 *edid_corrupt = true; 1655 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1656 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1657 } else { 1658 if (edid_corrupt) 1659 *edid_corrupt = true; 1660 goto bad; 1661 } 1662 } 1663 1664 csum = drm_edid_block_checksum(raw_edid); 1665 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1666 if (edid_corrupt) 1667 *edid_corrupt = true; 1668 1669 /* allow CEA to slide through, switches mangle this */ 1670 if (raw_edid[0] == CEA_EXT) { 1671 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1672 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1673 } else { 1674 if (print_bad_edid) 1675 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1676 1677 goto bad; 1678 } 1679 } 1680 1681 /* per-block-type checks */ 1682 switch (raw_edid[0]) { 1683 case 0: /* base */ 1684 if (edid->version != 1) { 1685 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1686 goto bad; 1687 } 1688 1689 if (edid->revision > 4) 1690 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1691 break; 1692 1693 default: 1694 break; 1695 } 1696 1697 return true; 1698 1699 bad: 1700 if (print_bad_edid) { 1701 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1702 pr_notice("EDID block is all zeroes\n"); 1703 } else { 1704 pr_notice("Raw EDID:\n"); 1705 print_hex_dump(KERN_NOTICE, 1706 " \t", DUMP_PREFIX_NONE, 16, 1, 1707 raw_edid, EDID_LENGTH, false); 1708 } 1709 } 1710 return false; 1711 } 1712 EXPORT_SYMBOL(drm_edid_block_valid); 1713 1714 /** 1715 * drm_edid_is_valid - sanity check EDID data 1716 * @edid: EDID data 1717 * 1718 * Sanity-check an entire EDID record (including extensions) 1719 * 1720 * Return: True if the EDID data is valid, false otherwise. 1721 */ 1722 bool drm_edid_is_valid(struct edid *edid) 1723 { 1724 int i; 1725 u8 *raw = (u8 *)edid; 1726 1727 if (!edid) 1728 return false; 1729 1730 for (i = 0; i <= edid->extensions; i++) 1731 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1732 return false; 1733 1734 return true; 1735 } 1736 EXPORT_SYMBOL(drm_edid_is_valid); 1737 1738 #define DDC_SEGMENT_ADDR 0x30 1739 /** 1740 * drm_do_probe_ddc_edid() - get EDID information via I2C 1741 * @data: I2C device adapter 1742 * @buf: EDID data buffer to be filled 1743 * @block: 128 byte EDID block to start fetching from 1744 * @len: EDID data buffer length to fetch 1745 * 1746 * Try to fetch EDID information by calling I2C driver functions. 1747 * 1748 * Return: 0 on success or -1 on failure. 1749 */ 1750 static int 1751 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1752 { 1753 struct i2c_adapter *adapter = data; 1754 unsigned char start = block * EDID_LENGTH; 1755 unsigned char segment = block >> 1; 1756 unsigned char xfers = segment ? 3 : 2; 1757 int ret, retries = 5; 1758 1759 /* 1760 * The core I2C driver will automatically retry the transfer if the 1761 * adapter reports EAGAIN. However, we find that bit-banging transfers 1762 * are susceptible to errors under a heavily loaded machine and 1763 * generate spurious NAKs and timeouts. Retrying the transfer 1764 * of the individual block a few times seems to overcome this. 1765 */ 1766 do { 1767 struct i2c_msg msgs[] = { 1768 { 1769 .addr = DDC_SEGMENT_ADDR, 1770 .flags = 0, 1771 .len = 1, 1772 .buf = &segment, 1773 }, { 1774 .addr = DDC_ADDR, 1775 .flags = 0, 1776 .len = 1, 1777 .buf = &start, 1778 }, { 1779 .addr = DDC_ADDR, 1780 .flags = I2C_M_RD, 1781 .len = len, 1782 .buf = buf, 1783 } 1784 }; 1785 1786 /* 1787 * Avoid sending the segment addr to not upset non-compliant 1788 * DDC monitors. 1789 */ 1790 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1791 1792 if (ret == -ENXIO) { 1793 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1794 adapter->name); 1795 break; 1796 } 1797 } while (ret != xfers && --retries); 1798 1799 return ret == xfers ? 0 : -1; 1800 } 1801 1802 static void connector_bad_edid(struct drm_connector *connector, 1803 u8 *edid, int num_blocks) 1804 { 1805 int i; 1806 u8 num_of_ext = edid[0x7e]; 1807 1808 /* Calculate real checksum for the last edid extension block data */ 1809 connector->real_edid_checksum = 1810 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1811 1812 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1813 return; 1814 1815 dev_warn(connector->dev->dev, 1816 "%s: EDID is invalid:\n", 1817 connector->name); 1818 for (i = 0; i < num_blocks; i++) { 1819 u8 *block = edid + i * EDID_LENGTH; 1820 char prefix[20]; 1821 1822 if (drm_edid_is_zero(block, EDID_LENGTH)) 1823 sprintf(prefix, "\t[%02x] ZERO ", i); 1824 else if (!drm_edid_block_valid(block, i, false, NULL)) 1825 sprintf(prefix, "\t[%02x] BAD ", i); 1826 else 1827 sprintf(prefix, "\t[%02x] GOOD ", i); 1828 1829 print_hex_dump(KERN_WARNING, 1830 prefix, DUMP_PREFIX_NONE, 16, 1, 1831 block, EDID_LENGTH, false); 1832 } 1833 } 1834 1835 /* Get override or firmware EDID */ 1836 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1837 { 1838 struct edid *override = NULL; 1839 1840 if (connector->override_edid) 1841 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1842 1843 if (!override) 1844 override = drm_load_edid_firmware(connector); 1845 1846 return IS_ERR(override) ? NULL : override; 1847 } 1848 1849 /** 1850 * drm_add_override_edid_modes - add modes from override/firmware EDID 1851 * @connector: connector we're probing 1852 * 1853 * Add modes from the override/firmware EDID, if available. Only to be used from 1854 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1855 * failed during drm_get_edid() and caused the override/firmware EDID to be 1856 * skipped. 1857 * 1858 * Return: The number of modes added or 0 if we couldn't find any. 1859 */ 1860 int drm_add_override_edid_modes(struct drm_connector *connector) 1861 { 1862 struct edid *override; 1863 int num_modes = 0; 1864 1865 override = drm_get_override_edid(connector); 1866 if (override) { 1867 drm_connector_update_edid_property(connector, override); 1868 num_modes = drm_add_edid_modes(connector, override); 1869 kfree(override); 1870 1871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1872 connector->base.id, connector->name, num_modes); 1873 } 1874 1875 return num_modes; 1876 } 1877 EXPORT_SYMBOL(drm_add_override_edid_modes); 1878 1879 /** 1880 * drm_do_get_edid - get EDID data using a custom EDID block read function 1881 * @connector: connector we're probing 1882 * @get_edid_block: EDID block read function 1883 * @data: private data passed to the block read function 1884 * 1885 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1886 * exposes a different interface to read EDID blocks this function can be used 1887 * to get EDID data using a custom block read function. 1888 * 1889 * As in the general case the DDC bus is accessible by the kernel at the I2C 1890 * level, drivers must make all reasonable efforts to expose it as an I2C 1891 * adapter and use drm_get_edid() instead of abusing this function. 1892 * 1893 * The EDID may be overridden using debugfs override_edid or firmare EDID 1894 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1895 * order. Having either of them bypasses actual EDID reads. 1896 * 1897 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1898 */ 1899 struct edid *drm_do_get_edid(struct drm_connector *connector, 1900 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1901 size_t len), 1902 void *data) 1903 { 1904 int i, j = 0, valid_extensions = 0; 1905 u8 *edid, *new; 1906 struct edid *override; 1907 1908 override = drm_get_override_edid(connector); 1909 if (override) 1910 return override; 1911 1912 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1913 return NULL; 1914 1915 /* base block fetch */ 1916 for (i = 0; i < 4; i++) { 1917 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1918 goto out; 1919 if (drm_edid_block_valid(edid, 0, false, 1920 &connector->edid_corrupt)) 1921 break; 1922 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1923 connector->null_edid_counter++; 1924 goto carp; 1925 } 1926 } 1927 if (i == 4) 1928 goto carp; 1929 1930 /* if there's no extensions, we're done */ 1931 valid_extensions = edid[0x7e]; 1932 if (valid_extensions == 0) 1933 return (struct edid *)edid; 1934 1935 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1936 if (!new) 1937 goto out; 1938 edid = new; 1939 1940 for (j = 1; j <= edid[0x7e]; j++) { 1941 u8 *block = edid + j * EDID_LENGTH; 1942 1943 for (i = 0; i < 4; i++) { 1944 if (get_edid_block(data, block, j, EDID_LENGTH)) 1945 goto out; 1946 if (drm_edid_block_valid(block, j, false, NULL)) 1947 break; 1948 } 1949 1950 if (i == 4) 1951 valid_extensions--; 1952 } 1953 1954 if (valid_extensions != edid[0x7e]) { 1955 u8 *base; 1956 1957 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1958 1959 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1960 edid[0x7e] = valid_extensions; 1961 1962 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1963 GFP_KERNEL); 1964 if (!new) 1965 goto out; 1966 1967 base = new; 1968 for (i = 0; i <= edid[0x7e]; i++) { 1969 u8 *block = edid + i * EDID_LENGTH; 1970 1971 if (!drm_edid_block_valid(block, i, false, NULL)) 1972 continue; 1973 1974 memcpy(base, block, EDID_LENGTH); 1975 base += EDID_LENGTH; 1976 } 1977 1978 kfree(edid); 1979 edid = new; 1980 } 1981 1982 return (struct edid *)edid; 1983 1984 carp: 1985 connector_bad_edid(connector, edid, 1); 1986 out: 1987 kfree(edid); 1988 return NULL; 1989 } 1990 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1991 1992 /** 1993 * drm_probe_ddc() - probe DDC presence 1994 * @adapter: I2C adapter to probe 1995 * 1996 * Return: True on success, false on failure. 1997 */ 1998 bool 1999 drm_probe_ddc(struct i2c_adapter *adapter) 2000 { 2001 unsigned char out; 2002 2003 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2004 } 2005 EXPORT_SYMBOL(drm_probe_ddc); 2006 2007 /** 2008 * drm_get_edid - get EDID data, if available 2009 * @connector: connector we're probing 2010 * @adapter: I2C adapter to use for DDC 2011 * 2012 * Poke the given I2C channel to grab EDID data if possible. If found, 2013 * attach it to the connector. 2014 * 2015 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2016 */ 2017 struct edid *drm_get_edid(struct drm_connector *connector, 2018 struct i2c_adapter *adapter) 2019 { 2020 if (connector->force == DRM_FORCE_OFF) 2021 return NULL; 2022 2023 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2024 return NULL; 2025 2026 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2027 } 2028 EXPORT_SYMBOL(drm_get_edid); 2029 2030 /** 2031 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2032 * @connector: connector we're probing 2033 * @adapter: I2C adapter to use for DDC 2034 * 2035 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2036 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2037 * switch DDC to the GPU which is retrieving EDID. 2038 * 2039 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2040 */ 2041 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2042 struct i2c_adapter *adapter) 2043 { 2044 struct pci_dev *pdev = connector->dev->pdev; 2045 struct edid *edid; 2046 2047 vga_switcheroo_lock_ddc(pdev); 2048 edid = drm_get_edid(connector, adapter); 2049 vga_switcheroo_unlock_ddc(pdev); 2050 2051 return edid; 2052 } 2053 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2054 2055 /** 2056 * drm_edid_duplicate - duplicate an EDID and the extensions 2057 * @edid: EDID to duplicate 2058 * 2059 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2060 */ 2061 struct edid *drm_edid_duplicate(const struct edid *edid) 2062 { 2063 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2064 } 2065 EXPORT_SYMBOL(drm_edid_duplicate); 2066 2067 /*** EDID parsing ***/ 2068 2069 /** 2070 * edid_vendor - match a string against EDID's obfuscated vendor field 2071 * @edid: EDID to match 2072 * @vendor: vendor string 2073 * 2074 * Returns true if @vendor is in @edid, false otherwise 2075 */ 2076 static bool edid_vendor(const struct edid *edid, const char *vendor) 2077 { 2078 char edid_vendor[3]; 2079 2080 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2081 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2082 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2083 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2084 2085 return !strncmp(edid_vendor, vendor, 3); 2086 } 2087 2088 /** 2089 * edid_get_quirks - return quirk flags for a given EDID 2090 * @edid: EDID to process 2091 * 2092 * This tells subsequent routines what fixes they need to apply. 2093 */ 2094 static u32 edid_get_quirks(const struct edid *edid) 2095 { 2096 const struct edid_quirk *quirk; 2097 int i; 2098 2099 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2100 quirk = &edid_quirk_list[i]; 2101 2102 if (edid_vendor(edid, quirk->vendor) && 2103 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2104 return quirk->quirks; 2105 } 2106 2107 return 0; 2108 } 2109 2110 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2111 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2112 2113 /** 2114 * edid_fixup_preferred - set preferred modes based on quirk list 2115 * @connector: has mode list to fix up 2116 * @quirks: quirks list 2117 * 2118 * Walk the mode list for @connector, clearing the preferred status 2119 * on existing modes and setting it anew for the right mode ala @quirks. 2120 */ 2121 static void edid_fixup_preferred(struct drm_connector *connector, 2122 u32 quirks) 2123 { 2124 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2125 int target_refresh = 0; 2126 int cur_vrefresh, preferred_vrefresh; 2127 2128 if (list_empty(&connector->probed_modes)) 2129 return; 2130 2131 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2132 target_refresh = 60; 2133 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2134 target_refresh = 75; 2135 2136 preferred_mode = list_first_entry(&connector->probed_modes, 2137 struct drm_display_mode, head); 2138 2139 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2140 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2141 2142 if (cur_mode == preferred_mode) 2143 continue; 2144 2145 /* Largest mode is preferred */ 2146 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2147 preferred_mode = cur_mode; 2148 2149 cur_vrefresh = cur_mode->vrefresh ? 2150 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 2151 preferred_vrefresh = preferred_mode->vrefresh ? 2152 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 2153 /* At a given size, try to get closest to target refresh */ 2154 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2155 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2156 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2157 preferred_mode = cur_mode; 2158 } 2159 } 2160 2161 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2162 } 2163 2164 static bool 2165 mode_is_rb(const struct drm_display_mode *mode) 2166 { 2167 return (mode->htotal - mode->hdisplay == 160) && 2168 (mode->hsync_end - mode->hdisplay == 80) && 2169 (mode->hsync_end - mode->hsync_start == 32) && 2170 (mode->vsync_start - mode->vdisplay == 3); 2171 } 2172 2173 /* 2174 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2175 * @dev: Device to duplicate against 2176 * @hsize: Mode width 2177 * @vsize: Mode height 2178 * @fresh: Mode refresh rate 2179 * @rb: Mode reduced-blanking-ness 2180 * 2181 * Walk the DMT mode list looking for a match for the given parameters. 2182 * 2183 * Return: A newly allocated copy of the mode, or NULL if not found. 2184 */ 2185 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2186 int hsize, int vsize, int fresh, 2187 bool rb) 2188 { 2189 int i; 2190 2191 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2192 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2193 if (hsize != ptr->hdisplay) 2194 continue; 2195 if (vsize != ptr->vdisplay) 2196 continue; 2197 if (fresh != drm_mode_vrefresh(ptr)) 2198 continue; 2199 if (rb != mode_is_rb(ptr)) 2200 continue; 2201 2202 return drm_mode_duplicate(dev, ptr); 2203 } 2204 2205 return NULL; 2206 } 2207 EXPORT_SYMBOL(drm_mode_find_dmt); 2208 2209 static bool is_display_descriptor(const u8 d[18], u8 tag) 2210 { 2211 return d[0] == 0x00 && d[1] == 0x00 && 2212 d[2] == 0x00 && d[3] == tag; 2213 } 2214 2215 static bool is_detailed_timing_descriptor(const u8 d[18]) 2216 { 2217 return d[0] != 0x00 || d[1] != 0x00; 2218 } 2219 2220 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2221 2222 static void 2223 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2224 { 2225 int i, n; 2226 u8 d = ext[0x02]; 2227 u8 *det_base = ext + d; 2228 2229 if (d < 4 || d > 127) 2230 return; 2231 2232 n = (127 - d) / 18; 2233 for (i = 0; i < n; i++) 2234 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2235 } 2236 2237 static void 2238 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2239 { 2240 unsigned int i, n = min((int)ext[0x02], 6); 2241 u8 *det_base = ext + 5; 2242 2243 if (ext[0x01] != 1) 2244 return; /* unknown version */ 2245 2246 for (i = 0; i < n; i++) 2247 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2248 } 2249 2250 static void 2251 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2252 { 2253 int i; 2254 struct edid *edid = (struct edid *)raw_edid; 2255 2256 if (edid == NULL) 2257 return; 2258 2259 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2260 cb(&(edid->detailed_timings[i]), closure); 2261 2262 for (i = 1; i <= raw_edid[0x7e]; i++) { 2263 u8 *ext = raw_edid + (i * EDID_LENGTH); 2264 switch (*ext) { 2265 case CEA_EXT: 2266 cea_for_each_detailed_block(ext, cb, closure); 2267 break; 2268 case VTB_EXT: 2269 vtb_for_each_detailed_block(ext, cb, closure); 2270 break; 2271 default: 2272 break; 2273 } 2274 } 2275 } 2276 2277 static void 2278 is_rb(struct detailed_timing *t, void *data) 2279 { 2280 u8 *r = (u8 *)t; 2281 2282 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2283 return; 2284 2285 if (r[15] & 0x10) 2286 *(bool *)data = true; 2287 } 2288 2289 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2290 static bool 2291 drm_monitor_supports_rb(struct edid *edid) 2292 { 2293 if (edid->revision >= 4) { 2294 bool ret = false; 2295 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2296 return ret; 2297 } 2298 2299 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2300 } 2301 2302 static void 2303 find_gtf2(struct detailed_timing *t, void *data) 2304 { 2305 u8 *r = (u8 *)t; 2306 2307 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2308 return; 2309 2310 if (r[10] == 0x02) 2311 *(u8 **)data = r; 2312 } 2313 2314 /* Secondary GTF curve kicks in above some break frequency */ 2315 static int 2316 drm_gtf2_hbreak(struct edid *edid) 2317 { 2318 u8 *r = NULL; 2319 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2320 return r ? (r[12] * 2) : 0; 2321 } 2322 2323 static int 2324 drm_gtf2_2c(struct edid *edid) 2325 { 2326 u8 *r = NULL; 2327 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2328 return r ? r[13] : 0; 2329 } 2330 2331 static int 2332 drm_gtf2_m(struct edid *edid) 2333 { 2334 u8 *r = NULL; 2335 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2336 return r ? (r[15] << 8) + r[14] : 0; 2337 } 2338 2339 static int 2340 drm_gtf2_k(struct edid *edid) 2341 { 2342 u8 *r = NULL; 2343 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2344 return r ? r[16] : 0; 2345 } 2346 2347 static int 2348 drm_gtf2_2j(struct edid *edid) 2349 { 2350 u8 *r = NULL; 2351 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2352 return r ? r[17] : 0; 2353 } 2354 2355 /** 2356 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2357 * @edid: EDID block to scan 2358 */ 2359 static int standard_timing_level(struct edid *edid) 2360 { 2361 if (edid->revision >= 2) { 2362 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2363 return LEVEL_CVT; 2364 if (drm_gtf2_hbreak(edid)) 2365 return LEVEL_GTF2; 2366 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2367 return LEVEL_GTF; 2368 } 2369 return LEVEL_DMT; 2370 } 2371 2372 /* 2373 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2374 * monitors fill with ascii space (0x20) instead. 2375 */ 2376 static int 2377 bad_std_timing(u8 a, u8 b) 2378 { 2379 return (a == 0x00 && b == 0x00) || 2380 (a == 0x01 && b == 0x01) || 2381 (a == 0x20 && b == 0x20); 2382 } 2383 2384 static int drm_mode_hsync(const struct drm_display_mode *mode) 2385 { 2386 if (mode->htotal <= 0) 2387 return 0; 2388 2389 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2390 } 2391 2392 /** 2393 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2394 * @connector: connector of for the EDID block 2395 * @edid: EDID block to scan 2396 * @t: standard timing params 2397 * 2398 * Take the standard timing params (in this case width, aspect, and refresh) 2399 * and convert them into a real mode using CVT/GTF/DMT. 2400 */ 2401 static struct drm_display_mode * 2402 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2403 struct std_timing *t) 2404 { 2405 struct drm_device *dev = connector->dev; 2406 struct drm_display_mode *m, *mode = NULL; 2407 int hsize, vsize; 2408 int vrefresh_rate; 2409 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2410 >> EDID_TIMING_ASPECT_SHIFT; 2411 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2412 >> EDID_TIMING_VFREQ_SHIFT; 2413 int timing_level = standard_timing_level(edid); 2414 2415 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2416 return NULL; 2417 2418 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2419 hsize = t->hsize * 8 + 248; 2420 /* vrefresh_rate = vfreq + 60 */ 2421 vrefresh_rate = vfreq + 60; 2422 /* the vdisplay is calculated based on the aspect ratio */ 2423 if (aspect_ratio == 0) { 2424 if (edid->revision < 3) 2425 vsize = hsize; 2426 else 2427 vsize = (hsize * 10) / 16; 2428 } else if (aspect_ratio == 1) 2429 vsize = (hsize * 3) / 4; 2430 else if (aspect_ratio == 2) 2431 vsize = (hsize * 4) / 5; 2432 else 2433 vsize = (hsize * 9) / 16; 2434 2435 /* HDTV hack, part 1 */ 2436 if (vrefresh_rate == 60 && 2437 ((hsize == 1360 && vsize == 765) || 2438 (hsize == 1368 && vsize == 769))) { 2439 hsize = 1366; 2440 vsize = 768; 2441 } 2442 2443 /* 2444 * If this connector already has a mode for this size and refresh 2445 * rate (because it came from detailed or CVT info), use that 2446 * instead. This way we don't have to guess at interlace or 2447 * reduced blanking. 2448 */ 2449 list_for_each_entry(m, &connector->probed_modes, head) 2450 if (m->hdisplay == hsize && m->vdisplay == vsize && 2451 drm_mode_vrefresh(m) == vrefresh_rate) 2452 return NULL; 2453 2454 /* HDTV hack, part 2 */ 2455 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2456 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2457 false); 2458 if (!mode) 2459 return NULL; 2460 mode->hdisplay = 1366; 2461 mode->hsync_start = mode->hsync_start - 1; 2462 mode->hsync_end = mode->hsync_end - 1; 2463 return mode; 2464 } 2465 2466 /* check whether it can be found in default mode table */ 2467 if (drm_monitor_supports_rb(edid)) { 2468 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2469 true); 2470 if (mode) 2471 return mode; 2472 } 2473 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2474 if (mode) 2475 return mode; 2476 2477 /* okay, generate it */ 2478 switch (timing_level) { 2479 case LEVEL_DMT: 2480 break; 2481 case LEVEL_GTF: 2482 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2483 break; 2484 case LEVEL_GTF2: 2485 /* 2486 * This is potentially wrong if there's ever a monitor with 2487 * more than one ranges section, each claiming a different 2488 * secondary GTF curve. Please don't do that. 2489 */ 2490 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2491 if (!mode) 2492 return NULL; 2493 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2494 drm_mode_destroy(dev, mode); 2495 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2496 vrefresh_rate, 0, 0, 2497 drm_gtf2_m(edid), 2498 drm_gtf2_2c(edid), 2499 drm_gtf2_k(edid), 2500 drm_gtf2_2j(edid)); 2501 } 2502 break; 2503 case LEVEL_CVT: 2504 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2505 false); 2506 break; 2507 } 2508 return mode; 2509 } 2510 2511 /* 2512 * EDID is delightfully ambiguous about how interlaced modes are to be 2513 * encoded. Our internal representation is of frame height, but some 2514 * HDTV detailed timings are encoded as field height. 2515 * 2516 * The format list here is from CEA, in frame size. Technically we 2517 * should be checking refresh rate too. Whatever. 2518 */ 2519 static void 2520 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2521 struct detailed_pixel_timing *pt) 2522 { 2523 int i; 2524 static const struct { 2525 int w, h; 2526 } cea_interlaced[] = { 2527 { 1920, 1080 }, 2528 { 720, 480 }, 2529 { 1440, 480 }, 2530 { 2880, 480 }, 2531 { 720, 576 }, 2532 { 1440, 576 }, 2533 { 2880, 576 }, 2534 }; 2535 2536 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2537 return; 2538 2539 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2540 if ((mode->hdisplay == cea_interlaced[i].w) && 2541 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2542 mode->vdisplay *= 2; 2543 mode->vsync_start *= 2; 2544 mode->vsync_end *= 2; 2545 mode->vtotal *= 2; 2546 mode->vtotal |= 1; 2547 } 2548 } 2549 2550 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2551 } 2552 2553 /** 2554 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2555 * @dev: DRM device (needed to create new mode) 2556 * @edid: EDID block 2557 * @timing: EDID detailed timing info 2558 * @quirks: quirks to apply 2559 * 2560 * An EDID detailed timing block contains enough info for us to create and 2561 * return a new struct drm_display_mode. 2562 */ 2563 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2564 struct edid *edid, 2565 struct detailed_timing *timing, 2566 u32 quirks) 2567 { 2568 struct drm_display_mode *mode; 2569 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2570 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2571 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2572 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2573 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2574 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2575 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2576 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2577 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2578 2579 /* ignore tiny modes */ 2580 if (hactive < 64 || vactive < 64) 2581 return NULL; 2582 2583 if (pt->misc & DRM_EDID_PT_STEREO) { 2584 DRM_DEBUG_KMS("stereo mode not supported\n"); 2585 return NULL; 2586 } 2587 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2588 DRM_DEBUG_KMS("composite sync not supported\n"); 2589 } 2590 2591 /* it is incorrect if hsync/vsync width is zero */ 2592 if (!hsync_pulse_width || !vsync_pulse_width) { 2593 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2594 "Wrong Hsync/Vsync pulse width\n"); 2595 return NULL; 2596 } 2597 2598 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2599 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2600 if (!mode) 2601 return NULL; 2602 2603 goto set_size; 2604 } 2605 2606 mode = drm_mode_create(dev); 2607 if (!mode) 2608 return NULL; 2609 2610 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2611 timing->pixel_clock = cpu_to_le16(1088); 2612 2613 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2614 2615 mode->hdisplay = hactive; 2616 mode->hsync_start = mode->hdisplay + hsync_offset; 2617 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2618 mode->htotal = mode->hdisplay + hblank; 2619 2620 mode->vdisplay = vactive; 2621 mode->vsync_start = mode->vdisplay + vsync_offset; 2622 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2623 mode->vtotal = mode->vdisplay + vblank; 2624 2625 /* Some EDIDs have bogus h/vtotal values */ 2626 if (mode->hsync_end > mode->htotal) 2627 mode->htotal = mode->hsync_end + 1; 2628 if (mode->vsync_end > mode->vtotal) 2629 mode->vtotal = mode->vsync_end + 1; 2630 2631 drm_mode_do_interlace_quirk(mode, pt); 2632 2633 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2634 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2635 } 2636 2637 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2638 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2639 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2640 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2641 2642 set_size: 2643 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2644 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2645 2646 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2647 mode->width_mm *= 10; 2648 mode->height_mm *= 10; 2649 } 2650 2651 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2652 mode->width_mm = edid->width_cm * 10; 2653 mode->height_mm = edid->height_cm * 10; 2654 } 2655 2656 mode->type = DRM_MODE_TYPE_DRIVER; 2657 mode->vrefresh = drm_mode_vrefresh(mode); 2658 drm_mode_set_name(mode); 2659 2660 return mode; 2661 } 2662 2663 static bool 2664 mode_in_hsync_range(const struct drm_display_mode *mode, 2665 struct edid *edid, u8 *t) 2666 { 2667 int hsync, hmin, hmax; 2668 2669 hmin = t[7]; 2670 if (edid->revision >= 4) 2671 hmin += ((t[4] & 0x04) ? 255 : 0); 2672 hmax = t[8]; 2673 if (edid->revision >= 4) 2674 hmax += ((t[4] & 0x08) ? 255 : 0); 2675 hsync = drm_mode_hsync(mode); 2676 2677 return (hsync <= hmax && hsync >= hmin); 2678 } 2679 2680 static bool 2681 mode_in_vsync_range(const struct drm_display_mode *mode, 2682 struct edid *edid, u8 *t) 2683 { 2684 int vsync, vmin, vmax; 2685 2686 vmin = t[5]; 2687 if (edid->revision >= 4) 2688 vmin += ((t[4] & 0x01) ? 255 : 0); 2689 vmax = t[6]; 2690 if (edid->revision >= 4) 2691 vmax += ((t[4] & 0x02) ? 255 : 0); 2692 vsync = drm_mode_vrefresh(mode); 2693 2694 return (vsync <= vmax && vsync >= vmin); 2695 } 2696 2697 static u32 2698 range_pixel_clock(struct edid *edid, u8 *t) 2699 { 2700 /* unspecified */ 2701 if (t[9] == 0 || t[9] == 255) 2702 return 0; 2703 2704 /* 1.4 with CVT support gives us real precision, yay */ 2705 if (edid->revision >= 4 && t[10] == 0x04) 2706 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2707 2708 /* 1.3 is pathetic, so fuzz up a bit */ 2709 return t[9] * 10000 + 5001; 2710 } 2711 2712 static bool 2713 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2714 struct detailed_timing *timing) 2715 { 2716 u32 max_clock; 2717 u8 *t = (u8 *)timing; 2718 2719 if (!mode_in_hsync_range(mode, edid, t)) 2720 return false; 2721 2722 if (!mode_in_vsync_range(mode, edid, t)) 2723 return false; 2724 2725 if ((max_clock = range_pixel_clock(edid, t))) 2726 if (mode->clock > max_clock) 2727 return false; 2728 2729 /* 1.4 max horizontal check */ 2730 if (edid->revision >= 4 && t[10] == 0x04) 2731 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2732 return false; 2733 2734 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2735 return false; 2736 2737 return true; 2738 } 2739 2740 static bool valid_inferred_mode(const struct drm_connector *connector, 2741 const struct drm_display_mode *mode) 2742 { 2743 const struct drm_display_mode *m; 2744 bool ok = false; 2745 2746 list_for_each_entry(m, &connector->probed_modes, head) { 2747 if (mode->hdisplay == m->hdisplay && 2748 mode->vdisplay == m->vdisplay && 2749 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2750 return false; /* duplicated */ 2751 if (mode->hdisplay <= m->hdisplay && 2752 mode->vdisplay <= m->vdisplay) 2753 ok = true; 2754 } 2755 return ok; 2756 } 2757 2758 static int 2759 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2760 struct detailed_timing *timing) 2761 { 2762 int i, modes = 0; 2763 struct drm_display_mode *newmode; 2764 struct drm_device *dev = connector->dev; 2765 2766 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2767 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2768 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2769 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2770 if (newmode) { 2771 drm_mode_probed_add(connector, newmode); 2772 modes++; 2773 } 2774 } 2775 } 2776 2777 return modes; 2778 } 2779 2780 /* fix up 1366x768 mode from 1368x768; 2781 * GFT/CVT can't express 1366 width which isn't dividable by 8 2782 */ 2783 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2784 { 2785 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2786 mode->hdisplay = 1366; 2787 mode->hsync_start--; 2788 mode->hsync_end--; 2789 drm_mode_set_name(mode); 2790 } 2791 } 2792 2793 static int 2794 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2795 struct detailed_timing *timing) 2796 { 2797 int i, modes = 0; 2798 struct drm_display_mode *newmode; 2799 struct drm_device *dev = connector->dev; 2800 2801 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2802 const struct minimode *m = &extra_modes[i]; 2803 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2804 if (!newmode) 2805 return modes; 2806 2807 drm_mode_fixup_1366x768(newmode); 2808 if (!mode_in_range(newmode, edid, timing) || 2809 !valid_inferred_mode(connector, newmode)) { 2810 drm_mode_destroy(dev, newmode); 2811 continue; 2812 } 2813 2814 drm_mode_probed_add(connector, newmode); 2815 modes++; 2816 } 2817 2818 return modes; 2819 } 2820 2821 static int 2822 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2823 struct detailed_timing *timing) 2824 { 2825 int i, modes = 0; 2826 struct drm_display_mode *newmode; 2827 struct drm_device *dev = connector->dev; 2828 bool rb = drm_monitor_supports_rb(edid); 2829 2830 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2831 const struct minimode *m = &extra_modes[i]; 2832 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2833 if (!newmode) 2834 return modes; 2835 2836 drm_mode_fixup_1366x768(newmode); 2837 if (!mode_in_range(newmode, edid, timing) || 2838 !valid_inferred_mode(connector, newmode)) { 2839 drm_mode_destroy(dev, newmode); 2840 continue; 2841 } 2842 2843 drm_mode_probed_add(connector, newmode); 2844 modes++; 2845 } 2846 2847 return modes; 2848 } 2849 2850 static void 2851 do_inferred_modes(struct detailed_timing *timing, void *c) 2852 { 2853 struct detailed_mode_closure *closure = c; 2854 struct detailed_non_pixel *data = &timing->data.other_data; 2855 struct detailed_data_monitor_range *range = &data->data.range; 2856 2857 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2858 return; 2859 2860 closure->modes += drm_dmt_modes_for_range(closure->connector, 2861 closure->edid, 2862 timing); 2863 2864 if (!version_greater(closure->edid, 1, 1)) 2865 return; /* GTF not defined yet */ 2866 2867 switch (range->flags) { 2868 case 0x02: /* secondary gtf, XXX could do more */ 2869 case 0x00: /* default gtf */ 2870 closure->modes += drm_gtf_modes_for_range(closure->connector, 2871 closure->edid, 2872 timing); 2873 break; 2874 case 0x04: /* cvt, only in 1.4+ */ 2875 if (!version_greater(closure->edid, 1, 3)) 2876 break; 2877 2878 closure->modes += drm_cvt_modes_for_range(closure->connector, 2879 closure->edid, 2880 timing); 2881 break; 2882 case 0x01: /* just the ranges, no formula */ 2883 default: 2884 break; 2885 } 2886 } 2887 2888 static int 2889 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2890 { 2891 struct detailed_mode_closure closure = { 2892 .connector = connector, 2893 .edid = edid, 2894 }; 2895 2896 if (version_greater(edid, 1, 0)) 2897 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2898 &closure); 2899 2900 return closure.modes; 2901 } 2902 2903 static int 2904 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2905 { 2906 int i, j, m, modes = 0; 2907 struct drm_display_mode *mode; 2908 u8 *est = ((u8 *)timing) + 6; 2909 2910 for (i = 0; i < 6; i++) { 2911 for (j = 7; j >= 0; j--) { 2912 m = (i * 8) + (7 - j); 2913 if (m >= ARRAY_SIZE(est3_modes)) 2914 break; 2915 if (est[i] & (1 << j)) { 2916 mode = drm_mode_find_dmt(connector->dev, 2917 est3_modes[m].w, 2918 est3_modes[m].h, 2919 est3_modes[m].r, 2920 est3_modes[m].rb); 2921 if (mode) { 2922 drm_mode_probed_add(connector, mode); 2923 modes++; 2924 } 2925 } 2926 } 2927 } 2928 2929 return modes; 2930 } 2931 2932 static void 2933 do_established_modes(struct detailed_timing *timing, void *c) 2934 { 2935 struct detailed_mode_closure *closure = c; 2936 2937 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2938 return; 2939 2940 closure->modes += drm_est3_modes(closure->connector, timing); 2941 } 2942 2943 /** 2944 * add_established_modes - get est. modes from EDID and add them 2945 * @connector: connector to add mode(s) to 2946 * @edid: EDID block to scan 2947 * 2948 * Each EDID block contains a bitmap of the supported "established modes" list 2949 * (defined above). Tease them out and add them to the global modes list. 2950 */ 2951 static int 2952 add_established_modes(struct drm_connector *connector, struct edid *edid) 2953 { 2954 struct drm_device *dev = connector->dev; 2955 unsigned long est_bits = edid->established_timings.t1 | 2956 (edid->established_timings.t2 << 8) | 2957 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2958 int i, modes = 0; 2959 struct detailed_mode_closure closure = { 2960 .connector = connector, 2961 .edid = edid, 2962 }; 2963 2964 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2965 if (est_bits & (1<<i)) { 2966 struct drm_display_mode *newmode; 2967 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2968 if (newmode) { 2969 drm_mode_probed_add(connector, newmode); 2970 modes++; 2971 } 2972 } 2973 } 2974 2975 if (version_greater(edid, 1, 0)) 2976 drm_for_each_detailed_block((u8 *)edid, 2977 do_established_modes, &closure); 2978 2979 return modes + closure.modes; 2980 } 2981 2982 static void 2983 do_standard_modes(struct detailed_timing *timing, void *c) 2984 { 2985 struct detailed_mode_closure *closure = c; 2986 struct detailed_non_pixel *data = &timing->data.other_data; 2987 struct drm_connector *connector = closure->connector; 2988 struct edid *edid = closure->edid; 2989 int i; 2990 2991 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 2992 return; 2993 2994 for (i = 0; i < 6; i++) { 2995 struct std_timing *std = &data->data.timings[i]; 2996 struct drm_display_mode *newmode; 2997 2998 newmode = drm_mode_std(connector, edid, std); 2999 if (newmode) { 3000 drm_mode_probed_add(connector, newmode); 3001 closure->modes++; 3002 } 3003 } 3004 } 3005 3006 /** 3007 * add_standard_modes - get std. modes from EDID and add them 3008 * @connector: connector to add mode(s) to 3009 * @edid: EDID block to scan 3010 * 3011 * Standard modes can be calculated using the appropriate standard (DMT, 3012 * GTF or CVT. Grab them from @edid and add them to the list. 3013 */ 3014 static int 3015 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3016 { 3017 int i, modes = 0; 3018 struct detailed_mode_closure closure = { 3019 .connector = connector, 3020 .edid = edid, 3021 }; 3022 3023 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3024 struct drm_display_mode *newmode; 3025 3026 newmode = drm_mode_std(connector, edid, 3027 &edid->standard_timings[i]); 3028 if (newmode) { 3029 drm_mode_probed_add(connector, newmode); 3030 modes++; 3031 } 3032 } 3033 3034 if (version_greater(edid, 1, 0)) 3035 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3036 &closure); 3037 3038 /* XXX should also look for standard codes in VTB blocks */ 3039 3040 return modes + closure.modes; 3041 } 3042 3043 static int drm_cvt_modes(struct drm_connector *connector, 3044 struct detailed_timing *timing) 3045 { 3046 int i, j, modes = 0; 3047 struct drm_display_mode *newmode; 3048 struct drm_device *dev = connector->dev; 3049 struct cvt_timing *cvt; 3050 const int rates[] = { 60, 85, 75, 60, 50 }; 3051 const u8 empty[3] = { 0, 0, 0 }; 3052 3053 for (i = 0; i < 4; i++) { 3054 int uninitialized_var(width), height; 3055 cvt = &(timing->data.other_data.data.cvt[i]); 3056 3057 if (!memcmp(cvt->code, empty, 3)) 3058 continue; 3059 3060 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3061 switch (cvt->code[1] & 0x0c) { 3062 case 0x00: 3063 width = height * 4 / 3; 3064 break; 3065 case 0x04: 3066 width = height * 16 / 9; 3067 break; 3068 case 0x08: 3069 width = height * 16 / 10; 3070 break; 3071 case 0x0c: 3072 width = height * 15 / 9; 3073 break; 3074 } 3075 3076 for (j = 1; j < 5; j++) { 3077 if (cvt->code[2] & (1 << j)) { 3078 newmode = drm_cvt_mode(dev, width, height, 3079 rates[j], j == 0, 3080 false, false); 3081 if (newmode) { 3082 drm_mode_probed_add(connector, newmode); 3083 modes++; 3084 } 3085 } 3086 } 3087 } 3088 3089 return modes; 3090 } 3091 3092 static void 3093 do_cvt_mode(struct detailed_timing *timing, void *c) 3094 { 3095 struct detailed_mode_closure *closure = c; 3096 3097 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3098 return; 3099 3100 closure->modes += drm_cvt_modes(closure->connector, timing); 3101 } 3102 3103 static int 3104 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3105 { 3106 struct detailed_mode_closure closure = { 3107 .connector = connector, 3108 .edid = edid, 3109 }; 3110 3111 if (version_greater(edid, 1, 2)) 3112 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3113 3114 /* XXX should also look for CVT codes in VTB blocks */ 3115 3116 return closure.modes; 3117 } 3118 3119 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3120 3121 static void 3122 do_detailed_mode(struct detailed_timing *timing, void *c) 3123 { 3124 struct detailed_mode_closure *closure = c; 3125 struct drm_display_mode *newmode; 3126 3127 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3128 return; 3129 3130 newmode = drm_mode_detailed(closure->connector->dev, 3131 closure->edid, timing, 3132 closure->quirks); 3133 if (!newmode) 3134 return; 3135 3136 if (closure->preferred) 3137 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3138 3139 /* 3140 * Detailed modes are limited to 10kHz pixel clock resolution, 3141 * so fix up anything that looks like CEA/HDMI mode, but the clock 3142 * is just slightly off. 3143 */ 3144 fixup_detailed_cea_mode_clock(newmode); 3145 3146 drm_mode_probed_add(closure->connector, newmode); 3147 closure->modes++; 3148 closure->preferred = false; 3149 } 3150 3151 /* 3152 * add_detailed_modes - Add modes from detailed timings 3153 * @connector: attached connector 3154 * @edid: EDID block to scan 3155 * @quirks: quirks to apply 3156 */ 3157 static int 3158 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3159 u32 quirks) 3160 { 3161 struct detailed_mode_closure closure = { 3162 .connector = connector, 3163 .edid = edid, 3164 .preferred = true, 3165 .quirks = quirks, 3166 }; 3167 3168 if (closure.preferred && !version_greater(edid, 1, 3)) 3169 closure.preferred = 3170 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3171 3172 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3173 3174 return closure.modes; 3175 } 3176 3177 #define AUDIO_BLOCK 0x01 3178 #define VIDEO_BLOCK 0x02 3179 #define VENDOR_BLOCK 0x03 3180 #define SPEAKER_BLOCK 0x04 3181 #define HDR_STATIC_METADATA_BLOCK 0x6 3182 #define USE_EXTENDED_TAG 0x07 3183 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3184 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3185 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3186 #define EDID_BASIC_AUDIO (1 << 6) 3187 #define EDID_CEA_YCRCB444 (1 << 5) 3188 #define EDID_CEA_YCRCB422 (1 << 4) 3189 #define EDID_CEA_VCDB_QS (1 << 6) 3190 3191 /* 3192 * Search EDID for CEA extension block. 3193 */ 3194 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3195 { 3196 u8 *edid_ext = NULL; 3197 int i; 3198 3199 /* No EDID or EDID extensions */ 3200 if (edid == NULL || edid->extensions == 0) 3201 return NULL; 3202 3203 /* Find CEA extension */ 3204 for (i = 0; i < edid->extensions; i++) { 3205 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3206 if (edid_ext[0] == ext_id) 3207 break; 3208 } 3209 3210 if (i == edid->extensions) 3211 return NULL; 3212 3213 return edid_ext; 3214 } 3215 3216 3217 static u8 *drm_find_displayid_extension(const struct edid *edid, 3218 int *length, int *idx) 3219 { 3220 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT); 3221 struct displayid_hdr *base; 3222 int ret; 3223 3224 if (!displayid) 3225 return NULL; 3226 3227 /* EDID extensions block checksum isn't for us */ 3228 *length = EDID_LENGTH - 1; 3229 *idx = 1; 3230 3231 ret = validate_displayid(displayid, *length, *idx); 3232 if (ret) 3233 return NULL; 3234 3235 base = (struct displayid_hdr *)&displayid[*idx]; 3236 *length = *idx + sizeof(*base) + base->bytes; 3237 3238 return displayid; 3239 } 3240 3241 static u8 *drm_find_cea_extension(const struct edid *edid) 3242 { 3243 int length, idx; 3244 struct displayid_block *block; 3245 u8 *cea; 3246 u8 *displayid; 3247 3248 /* Look for a top level CEA extension block */ 3249 cea = drm_find_edid_extension(edid, CEA_EXT); 3250 if (cea) 3251 return cea; 3252 3253 /* CEA blocks can also be found embedded in a DisplayID block */ 3254 displayid = drm_find_displayid_extension(edid, &length, &idx); 3255 if (!displayid) 3256 return NULL; 3257 3258 idx += sizeof(struct displayid_hdr); 3259 for_each_displayid_db(displayid, block, idx, length) { 3260 if (block->tag == DATA_BLOCK_CTA) { 3261 cea = (u8 *)block; 3262 break; 3263 } 3264 } 3265 3266 return cea; 3267 } 3268 3269 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3270 { 3271 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3272 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3273 3274 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3275 return &edid_cea_modes_1[vic - 1]; 3276 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3277 return &edid_cea_modes_193[vic - 193]; 3278 return NULL; 3279 } 3280 3281 static u8 cea_num_vics(void) 3282 { 3283 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3284 } 3285 3286 static u8 cea_next_vic(u8 vic) 3287 { 3288 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3289 vic = 193; 3290 return vic; 3291 } 3292 3293 /* 3294 * Calculate the alternate clock for the CEA mode 3295 * (60Hz vs. 59.94Hz etc.) 3296 */ 3297 static unsigned int 3298 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3299 { 3300 unsigned int clock = cea_mode->clock; 3301 3302 if (cea_mode->vrefresh % 6 != 0) 3303 return clock; 3304 3305 /* 3306 * edid_cea_modes contains the 59.94Hz 3307 * variant for 240 and 480 line modes, 3308 * and the 60Hz variant otherwise. 3309 */ 3310 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3311 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3312 else 3313 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3314 3315 return clock; 3316 } 3317 3318 static bool 3319 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3320 { 3321 /* 3322 * For certain VICs the spec allows the vertical 3323 * front porch to vary by one or two lines. 3324 * 3325 * cea_modes[] stores the variant with the shortest 3326 * vertical front porch. We can adjust the mode to 3327 * get the other variants by simply increasing the 3328 * vertical front porch length. 3329 */ 3330 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3331 cea_mode_for_vic(9)->vtotal != 262 || 3332 cea_mode_for_vic(12)->vtotal != 262 || 3333 cea_mode_for_vic(13)->vtotal != 262 || 3334 cea_mode_for_vic(23)->vtotal != 312 || 3335 cea_mode_for_vic(24)->vtotal != 312 || 3336 cea_mode_for_vic(27)->vtotal != 312 || 3337 cea_mode_for_vic(28)->vtotal != 312); 3338 3339 if (((vic == 8 || vic == 9 || 3340 vic == 12 || vic == 13) && mode->vtotal < 263) || 3341 ((vic == 23 || vic == 24 || 3342 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3343 mode->vsync_start++; 3344 mode->vsync_end++; 3345 mode->vtotal++; 3346 3347 return true; 3348 } 3349 3350 return false; 3351 } 3352 3353 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3354 unsigned int clock_tolerance) 3355 { 3356 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3357 u8 vic; 3358 3359 if (!to_match->clock) 3360 return 0; 3361 3362 if (to_match->picture_aspect_ratio) 3363 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3364 3365 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3366 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3367 unsigned int clock1, clock2; 3368 3369 /* Check both 60Hz and 59.94Hz */ 3370 clock1 = cea_mode.clock; 3371 clock2 = cea_mode_alternate_clock(&cea_mode); 3372 3373 if (abs(to_match->clock - clock1) > clock_tolerance && 3374 abs(to_match->clock - clock2) > clock_tolerance) 3375 continue; 3376 3377 do { 3378 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3379 return vic; 3380 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3381 } 3382 3383 return 0; 3384 } 3385 3386 /** 3387 * drm_match_cea_mode - look for a CEA mode matching given mode 3388 * @to_match: display mode 3389 * 3390 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3391 * mode. 3392 */ 3393 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3394 { 3395 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3396 u8 vic; 3397 3398 if (!to_match->clock) 3399 return 0; 3400 3401 if (to_match->picture_aspect_ratio) 3402 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3403 3404 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3405 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3406 unsigned int clock1, clock2; 3407 3408 /* Check both 60Hz and 59.94Hz */ 3409 clock1 = cea_mode.clock; 3410 clock2 = cea_mode_alternate_clock(&cea_mode); 3411 3412 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3413 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3414 continue; 3415 3416 do { 3417 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3418 return vic; 3419 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3420 } 3421 3422 return 0; 3423 } 3424 EXPORT_SYMBOL(drm_match_cea_mode); 3425 3426 static bool drm_valid_cea_vic(u8 vic) 3427 { 3428 return cea_mode_for_vic(vic) != NULL; 3429 } 3430 3431 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3432 { 3433 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3434 3435 if (mode) 3436 return mode->picture_aspect_ratio; 3437 3438 return HDMI_PICTURE_ASPECT_NONE; 3439 } 3440 3441 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3442 { 3443 return edid_4k_modes[video_code].picture_aspect_ratio; 3444 } 3445 3446 /* 3447 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3448 * specific block). 3449 */ 3450 static unsigned int 3451 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3452 { 3453 return cea_mode_alternate_clock(hdmi_mode); 3454 } 3455 3456 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3457 unsigned int clock_tolerance) 3458 { 3459 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3460 u8 vic; 3461 3462 if (!to_match->clock) 3463 return 0; 3464 3465 if (to_match->picture_aspect_ratio) 3466 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3467 3468 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3469 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3470 unsigned int clock1, clock2; 3471 3472 /* Make sure to also match alternate clocks */ 3473 clock1 = hdmi_mode->clock; 3474 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3475 3476 if (abs(to_match->clock - clock1) > clock_tolerance && 3477 abs(to_match->clock - clock2) > clock_tolerance) 3478 continue; 3479 3480 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3481 return vic; 3482 } 3483 3484 return 0; 3485 } 3486 3487 /* 3488 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3489 * @to_match: display mode 3490 * 3491 * An HDMI mode is one defined in the HDMI vendor specific block. 3492 * 3493 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3494 */ 3495 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3496 { 3497 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3498 u8 vic; 3499 3500 if (!to_match->clock) 3501 return 0; 3502 3503 if (to_match->picture_aspect_ratio) 3504 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3505 3506 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3507 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3508 unsigned int clock1, clock2; 3509 3510 /* Make sure to also match alternate clocks */ 3511 clock1 = hdmi_mode->clock; 3512 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3513 3514 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3515 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3516 drm_mode_match(to_match, hdmi_mode, match_flags)) 3517 return vic; 3518 } 3519 return 0; 3520 } 3521 3522 static bool drm_valid_hdmi_vic(u8 vic) 3523 { 3524 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3525 } 3526 3527 static int 3528 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3529 { 3530 struct drm_device *dev = connector->dev; 3531 struct drm_display_mode *mode, *tmp; 3532 LIST_HEAD(list); 3533 int modes = 0; 3534 3535 /* Don't add CEA modes if the CEA extension block is missing */ 3536 if (!drm_find_cea_extension(edid)) 3537 return 0; 3538 3539 /* 3540 * Go through all probed modes and create a new mode 3541 * with the alternate clock for certain CEA modes. 3542 */ 3543 list_for_each_entry(mode, &connector->probed_modes, head) { 3544 const struct drm_display_mode *cea_mode = NULL; 3545 struct drm_display_mode *newmode; 3546 u8 vic = drm_match_cea_mode(mode); 3547 unsigned int clock1, clock2; 3548 3549 if (drm_valid_cea_vic(vic)) { 3550 cea_mode = cea_mode_for_vic(vic); 3551 clock2 = cea_mode_alternate_clock(cea_mode); 3552 } else { 3553 vic = drm_match_hdmi_mode(mode); 3554 if (drm_valid_hdmi_vic(vic)) { 3555 cea_mode = &edid_4k_modes[vic]; 3556 clock2 = hdmi_mode_alternate_clock(cea_mode); 3557 } 3558 } 3559 3560 if (!cea_mode) 3561 continue; 3562 3563 clock1 = cea_mode->clock; 3564 3565 if (clock1 == clock2) 3566 continue; 3567 3568 if (mode->clock != clock1 && mode->clock != clock2) 3569 continue; 3570 3571 newmode = drm_mode_duplicate(dev, cea_mode); 3572 if (!newmode) 3573 continue; 3574 3575 /* Carry over the stereo flags */ 3576 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3577 3578 /* 3579 * The current mode could be either variant. Make 3580 * sure to pick the "other" clock for the new mode. 3581 */ 3582 if (mode->clock != clock1) 3583 newmode->clock = clock1; 3584 else 3585 newmode->clock = clock2; 3586 3587 list_add_tail(&newmode->head, &list); 3588 } 3589 3590 list_for_each_entry_safe(mode, tmp, &list, head) { 3591 list_del(&mode->head); 3592 drm_mode_probed_add(connector, mode); 3593 modes++; 3594 } 3595 3596 return modes; 3597 } 3598 3599 static u8 svd_to_vic(u8 svd) 3600 { 3601 /* 0-6 bit vic, 7th bit native mode indicator */ 3602 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3603 return svd & 127; 3604 3605 return svd; 3606 } 3607 3608 static struct drm_display_mode * 3609 drm_display_mode_from_vic_index(struct drm_connector *connector, 3610 const u8 *video_db, u8 video_len, 3611 u8 video_index) 3612 { 3613 struct drm_device *dev = connector->dev; 3614 struct drm_display_mode *newmode; 3615 u8 vic; 3616 3617 if (video_db == NULL || video_index >= video_len) 3618 return NULL; 3619 3620 /* CEA modes are numbered 1..127 */ 3621 vic = svd_to_vic(video_db[video_index]); 3622 if (!drm_valid_cea_vic(vic)) 3623 return NULL; 3624 3625 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3626 if (!newmode) 3627 return NULL; 3628 3629 newmode->vrefresh = 0; 3630 3631 return newmode; 3632 } 3633 3634 /* 3635 * do_y420vdb_modes - Parse YCBCR 420 only modes 3636 * @connector: connector corresponding to the HDMI sink 3637 * @svds: start of the data block of CEA YCBCR 420 VDB 3638 * @len: length of the CEA YCBCR 420 VDB 3639 * 3640 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3641 * which contains modes which can be supported in YCBCR 420 3642 * output format only. 3643 */ 3644 static int do_y420vdb_modes(struct drm_connector *connector, 3645 const u8 *svds, u8 svds_len) 3646 { 3647 int modes = 0, i; 3648 struct drm_device *dev = connector->dev; 3649 struct drm_display_info *info = &connector->display_info; 3650 struct drm_hdmi_info *hdmi = &info->hdmi; 3651 3652 for (i = 0; i < svds_len; i++) { 3653 u8 vic = svd_to_vic(svds[i]); 3654 struct drm_display_mode *newmode; 3655 3656 if (!drm_valid_cea_vic(vic)) 3657 continue; 3658 3659 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3660 if (!newmode) 3661 break; 3662 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3663 drm_mode_probed_add(connector, newmode); 3664 modes++; 3665 } 3666 3667 if (modes > 0) 3668 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3669 return modes; 3670 } 3671 3672 /* 3673 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3674 * @connector: connector corresponding to the HDMI sink 3675 * @vic: CEA vic for the video mode to be added in the map 3676 * 3677 * Makes an entry for a videomode in the YCBCR 420 bitmap 3678 */ 3679 static void 3680 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3681 { 3682 u8 vic = svd_to_vic(svd); 3683 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3684 3685 if (!drm_valid_cea_vic(vic)) 3686 return; 3687 3688 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3689 } 3690 3691 static int 3692 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3693 { 3694 int i, modes = 0; 3695 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3696 3697 for (i = 0; i < len; i++) { 3698 struct drm_display_mode *mode; 3699 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3700 if (mode) { 3701 /* 3702 * YCBCR420 capability block contains a bitmap which 3703 * gives the index of CEA modes from CEA VDB, which 3704 * can support YCBCR 420 sampling output also (apart 3705 * from RGB/YCBCR444 etc). 3706 * For example, if the bit 0 in bitmap is set, 3707 * first mode in VDB can support YCBCR420 output too. 3708 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3709 */ 3710 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3711 drm_add_cmdb_modes(connector, db[i]); 3712 3713 drm_mode_probed_add(connector, mode); 3714 modes++; 3715 } 3716 } 3717 3718 return modes; 3719 } 3720 3721 struct stereo_mandatory_mode { 3722 int width, height, vrefresh; 3723 unsigned int flags; 3724 }; 3725 3726 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3727 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3728 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3729 { 1920, 1080, 50, 3730 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3731 { 1920, 1080, 60, 3732 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3733 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3734 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3735 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3736 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3737 }; 3738 3739 static bool 3740 stereo_match_mandatory(const struct drm_display_mode *mode, 3741 const struct stereo_mandatory_mode *stereo_mode) 3742 { 3743 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3744 3745 return mode->hdisplay == stereo_mode->width && 3746 mode->vdisplay == stereo_mode->height && 3747 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3748 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3749 } 3750 3751 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3752 { 3753 struct drm_device *dev = connector->dev; 3754 const struct drm_display_mode *mode; 3755 struct list_head stereo_modes; 3756 int modes = 0, i; 3757 3758 INIT_LIST_HEAD(&stereo_modes); 3759 3760 list_for_each_entry(mode, &connector->probed_modes, head) { 3761 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3762 const struct stereo_mandatory_mode *mandatory; 3763 struct drm_display_mode *new_mode; 3764 3765 if (!stereo_match_mandatory(mode, 3766 &stereo_mandatory_modes[i])) 3767 continue; 3768 3769 mandatory = &stereo_mandatory_modes[i]; 3770 new_mode = drm_mode_duplicate(dev, mode); 3771 if (!new_mode) 3772 continue; 3773 3774 new_mode->flags |= mandatory->flags; 3775 list_add_tail(&new_mode->head, &stereo_modes); 3776 modes++; 3777 } 3778 } 3779 3780 list_splice_tail(&stereo_modes, &connector->probed_modes); 3781 3782 return modes; 3783 } 3784 3785 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3786 { 3787 struct drm_device *dev = connector->dev; 3788 struct drm_display_mode *newmode; 3789 3790 if (!drm_valid_hdmi_vic(vic)) { 3791 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3792 return 0; 3793 } 3794 3795 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3796 if (!newmode) 3797 return 0; 3798 3799 drm_mode_probed_add(connector, newmode); 3800 3801 return 1; 3802 } 3803 3804 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3805 const u8 *video_db, u8 video_len, u8 video_index) 3806 { 3807 struct drm_display_mode *newmode; 3808 int modes = 0; 3809 3810 if (structure & (1 << 0)) { 3811 newmode = drm_display_mode_from_vic_index(connector, video_db, 3812 video_len, 3813 video_index); 3814 if (newmode) { 3815 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3816 drm_mode_probed_add(connector, newmode); 3817 modes++; 3818 } 3819 } 3820 if (structure & (1 << 6)) { 3821 newmode = drm_display_mode_from_vic_index(connector, video_db, 3822 video_len, 3823 video_index); 3824 if (newmode) { 3825 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3826 drm_mode_probed_add(connector, newmode); 3827 modes++; 3828 } 3829 } 3830 if (structure & (1 << 8)) { 3831 newmode = drm_display_mode_from_vic_index(connector, video_db, 3832 video_len, 3833 video_index); 3834 if (newmode) { 3835 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3836 drm_mode_probed_add(connector, newmode); 3837 modes++; 3838 } 3839 } 3840 3841 return modes; 3842 } 3843 3844 /* 3845 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3846 * @connector: connector corresponding to the HDMI sink 3847 * @db: start of the CEA vendor specific block 3848 * @len: length of the CEA block payload, ie. one can access up to db[len] 3849 * 3850 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3851 * also adds the stereo 3d modes when applicable. 3852 */ 3853 static int 3854 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3855 const u8 *video_db, u8 video_len) 3856 { 3857 struct drm_display_info *info = &connector->display_info; 3858 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3859 u8 vic_len, hdmi_3d_len = 0; 3860 u16 mask; 3861 u16 structure_all; 3862 3863 if (len < 8) 3864 goto out; 3865 3866 /* no HDMI_Video_Present */ 3867 if (!(db[8] & (1 << 5))) 3868 goto out; 3869 3870 /* Latency_Fields_Present */ 3871 if (db[8] & (1 << 7)) 3872 offset += 2; 3873 3874 /* I_Latency_Fields_Present */ 3875 if (db[8] & (1 << 6)) 3876 offset += 2; 3877 3878 /* the declared length is not long enough for the 2 first bytes 3879 * of additional video format capabilities */ 3880 if (len < (8 + offset + 2)) 3881 goto out; 3882 3883 /* 3D_Present */ 3884 offset++; 3885 if (db[8 + offset] & (1 << 7)) { 3886 modes += add_hdmi_mandatory_stereo_modes(connector); 3887 3888 /* 3D_Multi_present */ 3889 multi_present = (db[8 + offset] & 0x60) >> 5; 3890 } 3891 3892 offset++; 3893 vic_len = db[8 + offset] >> 5; 3894 hdmi_3d_len = db[8 + offset] & 0x1f; 3895 3896 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3897 u8 vic; 3898 3899 vic = db[9 + offset + i]; 3900 modes += add_hdmi_mode(connector, vic); 3901 } 3902 offset += 1 + vic_len; 3903 3904 if (multi_present == 1) 3905 multi_len = 2; 3906 else if (multi_present == 2) 3907 multi_len = 4; 3908 else 3909 multi_len = 0; 3910 3911 if (len < (8 + offset + hdmi_3d_len - 1)) 3912 goto out; 3913 3914 if (hdmi_3d_len < multi_len) 3915 goto out; 3916 3917 if (multi_present == 1 || multi_present == 2) { 3918 /* 3D_Structure_ALL */ 3919 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3920 3921 /* check if 3D_MASK is present */ 3922 if (multi_present == 2) 3923 mask = (db[10 + offset] << 8) | db[11 + offset]; 3924 else 3925 mask = 0xffff; 3926 3927 for (i = 0; i < 16; i++) { 3928 if (mask & (1 << i)) 3929 modes += add_3d_struct_modes(connector, 3930 structure_all, 3931 video_db, 3932 video_len, i); 3933 } 3934 } 3935 3936 offset += multi_len; 3937 3938 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3939 int vic_index; 3940 struct drm_display_mode *newmode = NULL; 3941 unsigned int newflag = 0; 3942 bool detail_present; 3943 3944 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3945 3946 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3947 break; 3948 3949 /* 2D_VIC_order_X */ 3950 vic_index = db[8 + offset + i] >> 4; 3951 3952 /* 3D_Structure_X */ 3953 switch (db[8 + offset + i] & 0x0f) { 3954 case 0: 3955 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3956 break; 3957 case 6: 3958 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3959 break; 3960 case 8: 3961 /* 3D_Detail_X */ 3962 if ((db[9 + offset + i] >> 4) == 1) 3963 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3964 break; 3965 } 3966 3967 if (newflag != 0) { 3968 newmode = drm_display_mode_from_vic_index(connector, 3969 video_db, 3970 video_len, 3971 vic_index); 3972 3973 if (newmode) { 3974 newmode->flags |= newflag; 3975 drm_mode_probed_add(connector, newmode); 3976 modes++; 3977 } 3978 } 3979 3980 if (detail_present) 3981 i++; 3982 } 3983 3984 out: 3985 if (modes > 0) 3986 info->has_hdmi_infoframe = true; 3987 return modes; 3988 } 3989 3990 static int 3991 cea_db_payload_len(const u8 *db) 3992 { 3993 return db[0] & 0x1f; 3994 } 3995 3996 static int 3997 cea_db_extended_tag(const u8 *db) 3998 { 3999 return db[1]; 4000 } 4001 4002 static int 4003 cea_db_tag(const u8 *db) 4004 { 4005 return db[0] >> 5; 4006 } 4007 4008 static int 4009 cea_revision(const u8 *cea) 4010 { 4011 /* 4012 * FIXME is this correct for the DispID variant? 4013 * The DispID spec doesn't really specify whether 4014 * this is the revision of the CEA extension or 4015 * the DispID CEA data block. And the only value 4016 * given as an example is 0. 4017 */ 4018 return cea[1]; 4019 } 4020 4021 static int 4022 cea_db_offsets(const u8 *cea, int *start, int *end) 4023 { 4024 /* DisplayID CTA extension blocks and top-level CEA EDID 4025 * block header definitions differ in the following bytes: 4026 * 1) Byte 2 of the header specifies length differently, 4027 * 2) Byte 3 is only present in the CEA top level block. 4028 * 4029 * The different definitions for byte 2 follow. 4030 * 4031 * DisplayID CTA extension block defines byte 2 as: 4032 * Number of payload bytes 4033 * 4034 * CEA EDID block defines byte 2 as: 4035 * Byte number (decimal) within this block where the 18-byte 4036 * DTDs begin. If no non-DTD data is present in this extension 4037 * block, the value should be set to 04h (the byte after next). 4038 * If set to 00h, there are no DTDs present in this block and 4039 * no non-DTD data. 4040 */ 4041 if (cea[0] == DATA_BLOCK_CTA) { 4042 /* 4043 * for_each_displayid_db() has already verified 4044 * that these stay within expected bounds. 4045 */ 4046 *start = 3; 4047 *end = *start + cea[2]; 4048 } else if (cea[0] == CEA_EXT) { 4049 /* Data block offset in CEA extension block */ 4050 *start = 4; 4051 *end = cea[2]; 4052 if (*end == 0) 4053 *end = 127; 4054 if (*end < 4 || *end > 127) 4055 return -ERANGE; 4056 } else { 4057 return -EOPNOTSUPP; 4058 } 4059 4060 return 0; 4061 } 4062 4063 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4064 { 4065 int hdmi_id; 4066 4067 if (cea_db_tag(db) != VENDOR_BLOCK) 4068 return false; 4069 4070 if (cea_db_payload_len(db) < 5) 4071 return false; 4072 4073 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4074 4075 return hdmi_id == HDMI_IEEE_OUI; 4076 } 4077 4078 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4079 { 4080 unsigned int oui; 4081 4082 if (cea_db_tag(db) != VENDOR_BLOCK) 4083 return false; 4084 4085 if (cea_db_payload_len(db) < 7) 4086 return false; 4087 4088 oui = db[3] << 16 | db[2] << 8 | db[1]; 4089 4090 return oui == HDMI_FORUM_IEEE_OUI; 4091 } 4092 4093 static bool cea_db_is_vcdb(const u8 *db) 4094 { 4095 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4096 return false; 4097 4098 if (cea_db_payload_len(db) != 2) 4099 return false; 4100 4101 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4102 return false; 4103 4104 return true; 4105 } 4106 4107 static bool cea_db_is_y420cmdb(const u8 *db) 4108 { 4109 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4110 return false; 4111 4112 if (!cea_db_payload_len(db)) 4113 return false; 4114 4115 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4116 return false; 4117 4118 return true; 4119 } 4120 4121 static bool cea_db_is_y420vdb(const u8 *db) 4122 { 4123 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4124 return false; 4125 4126 if (!cea_db_payload_len(db)) 4127 return false; 4128 4129 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4130 return false; 4131 4132 return true; 4133 } 4134 4135 #define for_each_cea_db(cea, i, start, end) \ 4136 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4137 4138 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4139 const u8 *db) 4140 { 4141 struct drm_display_info *info = &connector->display_info; 4142 struct drm_hdmi_info *hdmi = &info->hdmi; 4143 u8 map_len = cea_db_payload_len(db) - 1; 4144 u8 count; 4145 u64 map = 0; 4146 4147 if (map_len == 0) { 4148 /* All CEA modes support ycbcr420 sampling also.*/ 4149 hdmi->y420_cmdb_map = U64_MAX; 4150 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4151 return; 4152 } 4153 4154 /* 4155 * This map indicates which of the existing CEA block modes 4156 * from VDB can support YCBCR420 output too. So if bit=0 is 4157 * set, first mode from VDB can support YCBCR420 output too. 4158 * We will parse and keep this map, before parsing VDB itself 4159 * to avoid going through the same block again and again. 4160 * 4161 * Spec is not clear about max possible size of this block. 4162 * Clamping max bitmap block size at 8 bytes. Every byte can 4163 * address 8 CEA modes, in this way this map can address 4164 * 8*8 = first 64 SVDs. 4165 */ 4166 if (WARN_ON_ONCE(map_len > 8)) 4167 map_len = 8; 4168 4169 for (count = 0; count < map_len; count++) 4170 map |= (u64)db[2 + count] << (8 * count); 4171 4172 if (map) 4173 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4174 4175 hdmi->y420_cmdb_map = map; 4176 } 4177 4178 static int 4179 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4180 { 4181 const u8 *cea = drm_find_cea_extension(edid); 4182 const u8 *db, *hdmi = NULL, *video = NULL; 4183 u8 dbl, hdmi_len, video_len = 0; 4184 int modes = 0; 4185 4186 if (cea && cea_revision(cea) >= 3) { 4187 int i, start, end; 4188 4189 if (cea_db_offsets(cea, &start, &end)) 4190 return 0; 4191 4192 for_each_cea_db(cea, i, start, end) { 4193 db = &cea[i]; 4194 dbl = cea_db_payload_len(db); 4195 4196 if (cea_db_tag(db) == VIDEO_BLOCK) { 4197 video = db + 1; 4198 video_len = dbl; 4199 modes += do_cea_modes(connector, video, dbl); 4200 } else if (cea_db_is_hdmi_vsdb(db)) { 4201 hdmi = db; 4202 hdmi_len = dbl; 4203 } else if (cea_db_is_y420vdb(db)) { 4204 const u8 *vdb420 = &db[2]; 4205 4206 /* Add 4:2:0(only) modes present in EDID */ 4207 modes += do_y420vdb_modes(connector, 4208 vdb420, 4209 dbl - 1); 4210 } 4211 } 4212 } 4213 4214 /* 4215 * We parse the HDMI VSDB after having added the cea modes as we will 4216 * be patching their flags when the sink supports stereo 3D. 4217 */ 4218 if (hdmi) 4219 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4220 video_len); 4221 4222 return modes; 4223 } 4224 4225 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4226 { 4227 const struct drm_display_mode *cea_mode; 4228 int clock1, clock2, clock; 4229 u8 vic; 4230 const char *type; 4231 4232 /* 4233 * allow 5kHz clock difference either way to account for 4234 * the 10kHz clock resolution limit of detailed timings. 4235 */ 4236 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4237 if (drm_valid_cea_vic(vic)) { 4238 type = "CEA"; 4239 cea_mode = cea_mode_for_vic(vic); 4240 clock1 = cea_mode->clock; 4241 clock2 = cea_mode_alternate_clock(cea_mode); 4242 } else { 4243 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4244 if (drm_valid_hdmi_vic(vic)) { 4245 type = "HDMI"; 4246 cea_mode = &edid_4k_modes[vic]; 4247 clock1 = cea_mode->clock; 4248 clock2 = hdmi_mode_alternate_clock(cea_mode); 4249 } else { 4250 return; 4251 } 4252 } 4253 4254 /* pick whichever is closest */ 4255 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4256 clock = clock1; 4257 else 4258 clock = clock2; 4259 4260 if (mode->clock == clock) 4261 return; 4262 4263 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4264 type, vic, mode->clock, clock); 4265 mode->clock = clock; 4266 } 4267 4268 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4269 { 4270 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4271 return false; 4272 4273 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4274 return false; 4275 4276 if (cea_db_payload_len(db) < 3) 4277 return false; 4278 4279 return true; 4280 } 4281 4282 static uint8_t eotf_supported(const u8 *edid_ext) 4283 { 4284 return edid_ext[2] & 4285 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4286 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4287 BIT(HDMI_EOTF_SMPTE_ST2084) | 4288 BIT(HDMI_EOTF_BT_2100_HLG)); 4289 } 4290 4291 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4292 { 4293 return edid_ext[3] & 4294 BIT(HDMI_STATIC_METADATA_TYPE1); 4295 } 4296 4297 static void 4298 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4299 { 4300 u16 len; 4301 4302 len = cea_db_payload_len(db); 4303 4304 connector->hdr_sink_metadata.hdmi_type1.eotf = 4305 eotf_supported(db); 4306 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4307 hdr_metadata_type(db); 4308 4309 if (len >= 4) 4310 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4311 if (len >= 5) 4312 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4313 if (len >= 6) 4314 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4315 } 4316 4317 static void 4318 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4319 { 4320 u8 len = cea_db_payload_len(db); 4321 4322 if (len >= 6 && (db[6] & (1 << 7))) 4323 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4324 if (len >= 8) { 4325 connector->latency_present[0] = db[8] >> 7; 4326 connector->latency_present[1] = (db[8] >> 6) & 1; 4327 } 4328 if (len >= 9) 4329 connector->video_latency[0] = db[9]; 4330 if (len >= 10) 4331 connector->audio_latency[0] = db[10]; 4332 if (len >= 11) 4333 connector->video_latency[1] = db[11]; 4334 if (len >= 12) 4335 connector->audio_latency[1] = db[12]; 4336 4337 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4338 "video latency %d %d, " 4339 "audio latency %d %d\n", 4340 connector->latency_present[0], 4341 connector->latency_present[1], 4342 connector->video_latency[0], 4343 connector->video_latency[1], 4344 connector->audio_latency[0], 4345 connector->audio_latency[1]); 4346 } 4347 4348 static void 4349 monitor_name(struct detailed_timing *t, void *data) 4350 { 4351 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4352 return; 4353 4354 *(u8 **)data = t->data.other_data.data.str.str; 4355 } 4356 4357 static int get_monitor_name(struct edid *edid, char name[13]) 4358 { 4359 char *edid_name = NULL; 4360 int mnl; 4361 4362 if (!edid || !name) 4363 return 0; 4364 4365 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4366 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4367 if (edid_name[mnl] == 0x0a) 4368 break; 4369 4370 name[mnl] = edid_name[mnl]; 4371 } 4372 4373 return mnl; 4374 } 4375 4376 /** 4377 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4378 * @edid: monitor EDID information 4379 * @name: pointer to a character array to hold the name of the monitor 4380 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4381 * 4382 */ 4383 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4384 { 4385 int name_length; 4386 char buf[13]; 4387 4388 if (bufsize <= 0) 4389 return; 4390 4391 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4392 memcpy(name, buf, name_length); 4393 name[name_length] = '\0'; 4394 } 4395 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4396 4397 static void clear_eld(struct drm_connector *connector) 4398 { 4399 memset(connector->eld, 0, sizeof(connector->eld)); 4400 4401 connector->latency_present[0] = false; 4402 connector->latency_present[1] = false; 4403 connector->video_latency[0] = 0; 4404 connector->audio_latency[0] = 0; 4405 connector->video_latency[1] = 0; 4406 connector->audio_latency[1] = 0; 4407 } 4408 4409 /* 4410 * drm_edid_to_eld - build ELD from EDID 4411 * @connector: connector corresponding to the HDMI/DP sink 4412 * @edid: EDID to parse 4413 * 4414 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4415 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4416 */ 4417 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4418 { 4419 uint8_t *eld = connector->eld; 4420 u8 *cea; 4421 u8 *db; 4422 int total_sad_count = 0; 4423 int mnl; 4424 int dbl; 4425 4426 clear_eld(connector); 4427 4428 if (!edid) 4429 return; 4430 4431 cea = drm_find_cea_extension(edid); 4432 if (!cea) { 4433 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4434 return; 4435 } 4436 4437 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4438 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4439 4440 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4441 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4442 4443 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4444 4445 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4446 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4447 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4448 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4449 4450 if (cea_revision(cea) >= 3) { 4451 int i, start, end; 4452 int sad_count; 4453 4454 if (cea_db_offsets(cea, &start, &end)) { 4455 start = 0; 4456 end = 0; 4457 } 4458 4459 for_each_cea_db(cea, i, start, end) { 4460 db = &cea[i]; 4461 dbl = cea_db_payload_len(db); 4462 4463 switch (cea_db_tag(db)) { 4464 case AUDIO_BLOCK: 4465 /* Audio Data Block, contains SADs */ 4466 sad_count = min(dbl / 3, 15 - total_sad_count); 4467 if (sad_count >= 1) 4468 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4469 &db[1], sad_count * 3); 4470 total_sad_count += sad_count; 4471 break; 4472 case SPEAKER_BLOCK: 4473 /* Speaker Allocation Data Block */ 4474 if (dbl >= 1) 4475 eld[DRM_ELD_SPEAKER] = db[1]; 4476 break; 4477 case VENDOR_BLOCK: 4478 /* HDMI Vendor-Specific Data Block */ 4479 if (cea_db_is_hdmi_vsdb(db)) 4480 drm_parse_hdmi_vsdb_audio(connector, db); 4481 break; 4482 default: 4483 break; 4484 } 4485 } 4486 } 4487 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4488 4489 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4490 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4491 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4492 else 4493 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4494 4495 eld[DRM_ELD_BASELINE_ELD_LEN] = 4496 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4497 4498 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4499 drm_eld_size(eld), total_sad_count); 4500 } 4501 4502 /** 4503 * drm_edid_to_sad - extracts SADs from EDID 4504 * @edid: EDID to parse 4505 * @sads: pointer that will be set to the extracted SADs 4506 * 4507 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4508 * 4509 * Note: The returned pointer needs to be freed using kfree(). 4510 * 4511 * Return: The number of found SADs or negative number on error. 4512 */ 4513 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4514 { 4515 int count = 0; 4516 int i, start, end, dbl; 4517 u8 *cea; 4518 4519 cea = drm_find_cea_extension(edid); 4520 if (!cea) { 4521 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4522 return 0; 4523 } 4524 4525 if (cea_revision(cea) < 3) { 4526 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4527 return 0; 4528 } 4529 4530 if (cea_db_offsets(cea, &start, &end)) { 4531 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4532 return -EPROTO; 4533 } 4534 4535 for_each_cea_db(cea, i, start, end) { 4536 u8 *db = &cea[i]; 4537 4538 if (cea_db_tag(db) == AUDIO_BLOCK) { 4539 int j; 4540 dbl = cea_db_payload_len(db); 4541 4542 count = dbl / 3; /* SAD is 3B */ 4543 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4544 if (!*sads) 4545 return -ENOMEM; 4546 for (j = 0; j < count; j++) { 4547 u8 *sad = &db[1 + j * 3]; 4548 4549 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4550 (*sads)[j].channels = sad[0] & 0x7; 4551 (*sads)[j].freq = sad[1] & 0x7F; 4552 (*sads)[j].byte2 = sad[2]; 4553 } 4554 break; 4555 } 4556 } 4557 4558 return count; 4559 } 4560 EXPORT_SYMBOL(drm_edid_to_sad); 4561 4562 /** 4563 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4564 * @edid: EDID to parse 4565 * @sadb: pointer to the speaker block 4566 * 4567 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4568 * 4569 * Note: The returned pointer needs to be freed using kfree(). 4570 * 4571 * Return: The number of found Speaker Allocation Blocks or negative number on 4572 * error. 4573 */ 4574 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4575 { 4576 int count = 0; 4577 int i, start, end, dbl; 4578 const u8 *cea; 4579 4580 cea = drm_find_cea_extension(edid); 4581 if (!cea) { 4582 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4583 return 0; 4584 } 4585 4586 if (cea_revision(cea) < 3) { 4587 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4588 return 0; 4589 } 4590 4591 if (cea_db_offsets(cea, &start, &end)) { 4592 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4593 return -EPROTO; 4594 } 4595 4596 for_each_cea_db(cea, i, start, end) { 4597 const u8 *db = &cea[i]; 4598 4599 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4600 dbl = cea_db_payload_len(db); 4601 4602 /* Speaker Allocation Data Block */ 4603 if (dbl == 3) { 4604 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4605 if (!*sadb) 4606 return -ENOMEM; 4607 count = dbl; 4608 break; 4609 } 4610 } 4611 } 4612 4613 return count; 4614 } 4615 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4616 4617 /** 4618 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4619 * @connector: connector associated with the HDMI/DP sink 4620 * @mode: the display mode 4621 * 4622 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4623 * the sink doesn't support audio or video. 4624 */ 4625 int drm_av_sync_delay(struct drm_connector *connector, 4626 const struct drm_display_mode *mode) 4627 { 4628 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4629 int a, v; 4630 4631 if (!connector->latency_present[0]) 4632 return 0; 4633 if (!connector->latency_present[1]) 4634 i = 0; 4635 4636 a = connector->audio_latency[i]; 4637 v = connector->video_latency[i]; 4638 4639 /* 4640 * HDMI/DP sink doesn't support audio or video? 4641 */ 4642 if (a == 255 || v == 255) 4643 return 0; 4644 4645 /* 4646 * Convert raw EDID values to millisecond. 4647 * Treat unknown latency as 0ms. 4648 */ 4649 if (a) 4650 a = min(2 * (a - 1), 500); 4651 if (v) 4652 v = min(2 * (v - 1), 500); 4653 4654 return max(v - a, 0); 4655 } 4656 EXPORT_SYMBOL(drm_av_sync_delay); 4657 4658 /** 4659 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4660 * @edid: monitor EDID information 4661 * 4662 * Parse the CEA extension according to CEA-861-B. 4663 * 4664 * Drivers that have added the modes parsed from EDID to drm_display_info 4665 * should use &drm_display_info.is_hdmi instead of calling this function. 4666 * 4667 * Return: True if the monitor is HDMI, false if not or unknown. 4668 */ 4669 bool drm_detect_hdmi_monitor(struct edid *edid) 4670 { 4671 u8 *edid_ext; 4672 int i; 4673 int start_offset, end_offset; 4674 4675 edid_ext = drm_find_cea_extension(edid); 4676 if (!edid_ext) 4677 return false; 4678 4679 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4680 return false; 4681 4682 /* 4683 * Because HDMI identifier is in Vendor Specific Block, 4684 * search it from all data blocks of CEA extension. 4685 */ 4686 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4687 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4688 return true; 4689 } 4690 4691 return false; 4692 } 4693 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4694 4695 /** 4696 * drm_detect_monitor_audio - check monitor audio capability 4697 * @edid: EDID block to scan 4698 * 4699 * Monitor should have CEA extension block. 4700 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4701 * audio' only. If there is any audio extension block and supported 4702 * audio format, assume at least 'basic audio' support, even if 'basic 4703 * audio' is not defined in EDID. 4704 * 4705 * Return: True if the monitor supports audio, false otherwise. 4706 */ 4707 bool drm_detect_monitor_audio(struct edid *edid) 4708 { 4709 u8 *edid_ext; 4710 int i, j; 4711 bool has_audio = false; 4712 int start_offset, end_offset; 4713 4714 edid_ext = drm_find_cea_extension(edid); 4715 if (!edid_ext) 4716 goto end; 4717 4718 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4719 4720 if (has_audio) { 4721 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4722 goto end; 4723 } 4724 4725 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4726 goto end; 4727 4728 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4729 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4730 has_audio = true; 4731 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4732 DRM_DEBUG_KMS("CEA audio format %d\n", 4733 (edid_ext[i + j] >> 3) & 0xf); 4734 goto end; 4735 } 4736 } 4737 end: 4738 return has_audio; 4739 } 4740 EXPORT_SYMBOL(drm_detect_monitor_audio); 4741 4742 4743 /** 4744 * drm_default_rgb_quant_range - default RGB quantization range 4745 * @mode: display mode 4746 * 4747 * Determine the default RGB quantization range for the mode, 4748 * as specified in CEA-861. 4749 * 4750 * Return: The default RGB quantization range for the mode 4751 */ 4752 enum hdmi_quantization_range 4753 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4754 { 4755 /* All CEA modes other than VIC 1 use limited quantization range. */ 4756 return drm_match_cea_mode(mode) > 1 ? 4757 HDMI_QUANTIZATION_RANGE_LIMITED : 4758 HDMI_QUANTIZATION_RANGE_FULL; 4759 } 4760 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4761 4762 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4763 { 4764 struct drm_display_info *info = &connector->display_info; 4765 4766 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4767 4768 if (db[2] & EDID_CEA_VCDB_QS) 4769 info->rgb_quant_range_selectable = true; 4770 } 4771 4772 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4773 const u8 *db) 4774 { 4775 u8 dc_mask; 4776 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4777 4778 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4779 hdmi->y420_dc_modes = dc_mask; 4780 } 4781 4782 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4783 const u8 *hf_vsdb) 4784 { 4785 struct drm_display_info *display = &connector->display_info; 4786 struct drm_hdmi_info *hdmi = &display->hdmi; 4787 4788 display->has_hdmi_infoframe = true; 4789 4790 if (hf_vsdb[6] & 0x80) { 4791 hdmi->scdc.supported = true; 4792 if (hf_vsdb[6] & 0x40) 4793 hdmi->scdc.read_request = true; 4794 } 4795 4796 /* 4797 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4798 * And as per the spec, three factors confirm this: 4799 * * Availability of a HF-VSDB block in EDID (check) 4800 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4801 * * SCDC support available (let's check) 4802 * Lets check it out. 4803 */ 4804 4805 if (hf_vsdb[5]) { 4806 /* max clock is 5000 KHz times block value */ 4807 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4808 struct drm_scdc *scdc = &hdmi->scdc; 4809 4810 if (max_tmds_clock > 340000) { 4811 display->max_tmds_clock = max_tmds_clock; 4812 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4813 display->max_tmds_clock); 4814 } 4815 4816 if (scdc->supported) { 4817 scdc->scrambling.supported = true; 4818 4819 /* Few sinks support scrambling for clocks < 340M */ 4820 if ((hf_vsdb[6] & 0x8)) 4821 scdc->scrambling.low_rates = true; 4822 } 4823 } 4824 4825 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4826 } 4827 4828 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4829 const u8 *hdmi) 4830 { 4831 struct drm_display_info *info = &connector->display_info; 4832 unsigned int dc_bpc = 0; 4833 4834 /* HDMI supports at least 8 bpc */ 4835 info->bpc = 8; 4836 4837 if (cea_db_payload_len(hdmi) < 6) 4838 return; 4839 4840 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4841 dc_bpc = 10; 4842 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4843 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4844 connector->name); 4845 } 4846 4847 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4848 dc_bpc = 12; 4849 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4850 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4851 connector->name); 4852 } 4853 4854 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4855 dc_bpc = 16; 4856 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4857 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4858 connector->name); 4859 } 4860 4861 if (dc_bpc == 0) { 4862 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4863 connector->name); 4864 return; 4865 } 4866 4867 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4868 connector->name, dc_bpc); 4869 info->bpc = dc_bpc; 4870 4871 /* 4872 * Deep color support mandates RGB444 support for all video 4873 * modes and forbids YCRCB422 support for all video modes per 4874 * HDMI 1.3 spec. 4875 */ 4876 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4877 4878 /* YCRCB444 is optional according to spec. */ 4879 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4880 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4881 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4882 connector->name); 4883 } 4884 4885 /* 4886 * Spec says that if any deep color mode is supported at all, 4887 * then deep color 36 bit must be supported. 4888 */ 4889 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4890 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4891 connector->name); 4892 } 4893 } 4894 4895 static void 4896 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4897 { 4898 struct drm_display_info *info = &connector->display_info; 4899 u8 len = cea_db_payload_len(db); 4900 4901 info->is_hdmi = true; 4902 4903 if (len >= 6) 4904 info->dvi_dual = db[6] & 1; 4905 if (len >= 7) 4906 info->max_tmds_clock = db[7] * 5000; 4907 4908 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4909 "max TMDS clock %d kHz\n", 4910 info->dvi_dual, 4911 info->max_tmds_clock); 4912 4913 drm_parse_hdmi_deep_color_info(connector, db); 4914 } 4915 4916 static void drm_parse_cea_ext(struct drm_connector *connector, 4917 const struct edid *edid) 4918 { 4919 struct drm_display_info *info = &connector->display_info; 4920 const u8 *edid_ext; 4921 int i, start, end; 4922 4923 edid_ext = drm_find_cea_extension(edid); 4924 if (!edid_ext) 4925 return; 4926 4927 info->cea_rev = edid_ext[1]; 4928 4929 /* The existence of a CEA block should imply RGB support */ 4930 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4931 if (edid_ext[3] & EDID_CEA_YCRCB444) 4932 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4933 if (edid_ext[3] & EDID_CEA_YCRCB422) 4934 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4935 4936 if (cea_db_offsets(edid_ext, &start, &end)) 4937 return; 4938 4939 for_each_cea_db(edid_ext, i, start, end) { 4940 const u8 *db = &edid_ext[i]; 4941 4942 if (cea_db_is_hdmi_vsdb(db)) 4943 drm_parse_hdmi_vsdb_video(connector, db); 4944 if (cea_db_is_hdmi_forum_vsdb(db)) 4945 drm_parse_hdmi_forum_vsdb(connector, db); 4946 if (cea_db_is_y420cmdb(db)) 4947 drm_parse_y420cmdb_bitmap(connector, db); 4948 if (cea_db_is_vcdb(db)) 4949 drm_parse_vcdb(connector, db); 4950 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4951 drm_parse_hdr_metadata_block(connector, db); 4952 } 4953 } 4954 4955 static 4956 void get_monitor_range(struct detailed_timing *timing, 4957 void *info_monitor_range) 4958 { 4959 struct drm_monitor_range_info *monitor_range = info_monitor_range; 4960 const struct detailed_non_pixel *data = &timing->data.other_data; 4961 const struct detailed_data_monitor_range *range = &data->data.range; 4962 4963 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 4964 return; 4965 4966 /* 4967 * Check for flag range limits only. If flag == 1 then 4968 * no additional timing information provided. 4969 * Default GTF, GTF Secondary curve and CVT are not 4970 * supported 4971 */ 4972 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 4973 return; 4974 4975 monitor_range->min_vfreq = range->min_vfreq; 4976 monitor_range->max_vfreq = range->max_vfreq; 4977 } 4978 4979 static 4980 void drm_get_monitor_range(struct drm_connector *connector, 4981 const struct edid *edid) 4982 { 4983 struct drm_display_info *info = &connector->display_info; 4984 4985 if (!version_greater(edid, 1, 1)) 4986 return; 4987 4988 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 4989 &info->monitor_range); 4990 4991 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 4992 info->monitor_range.min_vfreq, 4993 info->monitor_range.max_vfreq); 4994 } 4995 4996 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4997 * all of the values which would have been set from EDID 4998 */ 4999 void 5000 drm_reset_display_info(struct drm_connector *connector) 5001 { 5002 struct drm_display_info *info = &connector->display_info; 5003 5004 info->width_mm = 0; 5005 info->height_mm = 0; 5006 5007 info->bpc = 0; 5008 info->color_formats = 0; 5009 info->cea_rev = 0; 5010 info->max_tmds_clock = 0; 5011 info->dvi_dual = false; 5012 info->is_hdmi = false; 5013 info->has_hdmi_infoframe = false; 5014 info->rgb_quant_range_selectable = false; 5015 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5016 5017 info->non_desktop = 0; 5018 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5019 } 5020 5021 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5022 { 5023 struct drm_display_info *info = &connector->display_info; 5024 5025 u32 quirks = edid_get_quirks(edid); 5026 5027 drm_reset_display_info(connector); 5028 5029 info->width_mm = edid->width_cm * 10; 5030 info->height_mm = edid->height_cm * 10; 5031 5032 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5033 5034 drm_get_monitor_range(connector, edid); 5035 5036 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5037 5038 if (edid->revision < 3) 5039 return quirks; 5040 5041 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5042 return quirks; 5043 5044 drm_parse_cea_ext(connector, edid); 5045 5046 /* 5047 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5048 * 5049 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5050 * tells us to assume 8 bpc color depth if the EDID doesn't have 5051 * extensions which tell otherwise. 5052 */ 5053 if (info->bpc == 0 && edid->revision == 3 && 5054 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5055 info->bpc = 8; 5056 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5057 connector->name, info->bpc); 5058 } 5059 5060 /* Only defined for 1.4 with digital displays */ 5061 if (edid->revision < 4) 5062 return quirks; 5063 5064 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5065 case DRM_EDID_DIGITAL_DEPTH_6: 5066 info->bpc = 6; 5067 break; 5068 case DRM_EDID_DIGITAL_DEPTH_8: 5069 info->bpc = 8; 5070 break; 5071 case DRM_EDID_DIGITAL_DEPTH_10: 5072 info->bpc = 10; 5073 break; 5074 case DRM_EDID_DIGITAL_DEPTH_12: 5075 info->bpc = 12; 5076 break; 5077 case DRM_EDID_DIGITAL_DEPTH_14: 5078 info->bpc = 14; 5079 break; 5080 case DRM_EDID_DIGITAL_DEPTH_16: 5081 info->bpc = 16; 5082 break; 5083 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5084 default: 5085 info->bpc = 0; 5086 break; 5087 } 5088 5089 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5090 connector->name, info->bpc); 5091 5092 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5093 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5094 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5095 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5096 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5097 return quirks; 5098 } 5099 5100 static int validate_displayid(u8 *displayid, int length, int idx) 5101 { 5102 int i, dispid_length; 5103 u8 csum = 0; 5104 struct displayid_hdr *base; 5105 5106 base = (struct displayid_hdr *)&displayid[idx]; 5107 5108 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5109 base->rev, base->bytes, base->prod_id, base->ext_count); 5110 5111 /* +1 for DispID checksum */ 5112 dispid_length = sizeof(*base) + base->bytes + 1; 5113 if (dispid_length > length - idx) 5114 return -EINVAL; 5115 5116 for (i = 0; i < dispid_length; i++) 5117 csum += displayid[idx + i]; 5118 if (csum) { 5119 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5120 return -EINVAL; 5121 } 5122 5123 return 0; 5124 } 5125 5126 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5127 struct displayid_detailed_timings_1 *timings) 5128 { 5129 struct drm_display_mode *mode; 5130 unsigned pixel_clock = (timings->pixel_clock[0] | 5131 (timings->pixel_clock[1] << 8) | 5132 (timings->pixel_clock[2] << 16)) + 1; 5133 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5134 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5135 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5136 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5137 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5138 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5139 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5140 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5141 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5142 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5143 mode = drm_mode_create(dev); 5144 if (!mode) 5145 return NULL; 5146 5147 mode->clock = pixel_clock * 10; 5148 mode->hdisplay = hactive; 5149 mode->hsync_start = mode->hdisplay + hsync; 5150 mode->hsync_end = mode->hsync_start + hsync_width; 5151 mode->htotal = mode->hdisplay + hblank; 5152 5153 mode->vdisplay = vactive; 5154 mode->vsync_start = mode->vdisplay + vsync; 5155 mode->vsync_end = mode->vsync_start + vsync_width; 5156 mode->vtotal = mode->vdisplay + vblank; 5157 5158 mode->flags = 0; 5159 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5160 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5161 mode->type = DRM_MODE_TYPE_DRIVER; 5162 5163 if (timings->flags & 0x80) 5164 mode->type |= DRM_MODE_TYPE_PREFERRED; 5165 mode->vrefresh = drm_mode_vrefresh(mode); 5166 drm_mode_set_name(mode); 5167 5168 return mode; 5169 } 5170 5171 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5172 struct displayid_block *block) 5173 { 5174 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5175 int i; 5176 int num_timings; 5177 struct drm_display_mode *newmode; 5178 int num_modes = 0; 5179 /* blocks must be multiple of 20 bytes length */ 5180 if (block->num_bytes % 20) 5181 return 0; 5182 5183 num_timings = block->num_bytes / 20; 5184 for (i = 0; i < num_timings; i++) { 5185 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5186 5187 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5188 if (!newmode) 5189 continue; 5190 5191 drm_mode_probed_add(connector, newmode); 5192 num_modes++; 5193 } 5194 return num_modes; 5195 } 5196 5197 static int add_displayid_detailed_modes(struct drm_connector *connector, 5198 struct edid *edid) 5199 { 5200 u8 *displayid; 5201 int length, idx; 5202 struct displayid_block *block; 5203 int num_modes = 0; 5204 5205 displayid = drm_find_displayid_extension(edid, &length, &idx); 5206 if (!displayid) 5207 return 0; 5208 5209 idx += sizeof(struct displayid_hdr); 5210 for_each_displayid_db(displayid, block, idx, length) { 5211 switch (block->tag) { 5212 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5213 num_modes += add_displayid_detailed_1_modes(connector, block); 5214 break; 5215 } 5216 } 5217 return num_modes; 5218 } 5219 5220 /** 5221 * drm_add_edid_modes - add modes from EDID data, if available 5222 * @connector: connector we're probing 5223 * @edid: EDID data 5224 * 5225 * Add the specified modes to the connector's mode list. Also fills out the 5226 * &drm_display_info structure and ELD in @connector with any information which 5227 * can be derived from the edid. 5228 * 5229 * Return: The number of modes added or 0 if we couldn't find any. 5230 */ 5231 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5232 { 5233 int num_modes = 0; 5234 u32 quirks; 5235 5236 if (edid == NULL) { 5237 clear_eld(connector); 5238 return 0; 5239 } 5240 if (!drm_edid_is_valid(edid)) { 5241 clear_eld(connector); 5242 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5243 connector->name); 5244 return 0; 5245 } 5246 5247 drm_edid_to_eld(connector, edid); 5248 5249 /* 5250 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5251 * To avoid multiple parsing of same block, lets parse that map 5252 * from sink info, before parsing CEA modes. 5253 */ 5254 quirks = drm_add_display_info(connector, edid); 5255 5256 /* 5257 * EDID spec says modes should be preferred in this order: 5258 * - preferred detailed mode 5259 * - other detailed modes from base block 5260 * - detailed modes from extension blocks 5261 * - CVT 3-byte code modes 5262 * - standard timing codes 5263 * - established timing codes 5264 * - modes inferred from GTF or CVT range information 5265 * 5266 * We get this pretty much right. 5267 * 5268 * XXX order for additional mode types in extension blocks? 5269 */ 5270 num_modes += add_detailed_modes(connector, edid, quirks); 5271 num_modes += add_cvt_modes(connector, edid); 5272 num_modes += add_standard_modes(connector, edid); 5273 num_modes += add_established_modes(connector, edid); 5274 num_modes += add_cea_modes(connector, edid); 5275 num_modes += add_alternate_cea_modes(connector, edid); 5276 num_modes += add_displayid_detailed_modes(connector, edid); 5277 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5278 num_modes += add_inferred_modes(connector, edid); 5279 5280 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5281 edid_fixup_preferred(connector, quirks); 5282 5283 if (quirks & EDID_QUIRK_FORCE_6BPC) 5284 connector->display_info.bpc = 6; 5285 5286 if (quirks & EDID_QUIRK_FORCE_8BPC) 5287 connector->display_info.bpc = 8; 5288 5289 if (quirks & EDID_QUIRK_FORCE_10BPC) 5290 connector->display_info.bpc = 10; 5291 5292 if (quirks & EDID_QUIRK_FORCE_12BPC) 5293 connector->display_info.bpc = 12; 5294 5295 return num_modes; 5296 } 5297 EXPORT_SYMBOL(drm_add_edid_modes); 5298 5299 /** 5300 * drm_add_modes_noedid - add modes for the connectors without EDID 5301 * @connector: connector we're probing 5302 * @hdisplay: the horizontal display limit 5303 * @vdisplay: the vertical display limit 5304 * 5305 * Add the specified modes to the connector's mode list. Only when the 5306 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5307 * 5308 * Return: The number of modes added or 0 if we couldn't find any. 5309 */ 5310 int drm_add_modes_noedid(struct drm_connector *connector, 5311 int hdisplay, int vdisplay) 5312 { 5313 int i, count, num_modes = 0; 5314 struct drm_display_mode *mode; 5315 struct drm_device *dev = connector->dev; 5316 5317 count = ARRAY_SIZE(drm_dmt_modes); 5318 if (hdisplay < 0) 5319 hdisplay = 0; 5320 if (vdisplay < 0) 5321 vdisplay = 0; 5322 5323 for (i = 0; i < count; i++) { 5324 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5325 if (hdisplay && vdisplay) { 5326 /* 5327 * Only when two are valid, they will be used to check 5328 * whether the mode should be added to the mode list of 5329 * the connector. 5330 */ 5331 if (ptr->hdisplay > hdisplay || 5332 ptr->vdisplay > vdisplay) 5333 continue; 5334 } 5335 if (drm_mode_vrefresh(ptr) > 61) 5336 continue; 5337 mode = drm_mode_duplicate(dev, ptr); 5338 if (mode) { 5339 drm_mode_probed_add(connector, mode); 5340 num_modes++; 5341 } 5342 } 5343 return num_modes; 5344 } 5345 EXPORT_SYMBOL(drm_add_modes_noedid); 5346 5347 /** 5348 * drm_set_preferred_mode - Sets the preferred mode of a connector 5349 * @connector: connector whose mode list should be processed 5350 * @hpref: horizontal resolution of preferred mode 5351 * @vpref: vertical resolution of preferred mode 5352 * 5353 * Marks a mode as preferred if it matches the resolution specified by @hpref 5354 * and @vpref. 5355 */ 5356 void drm_set_preferred_mode(struct drm_connector *connector, 5357 int hpref, int vpref) 5358 { 5359 struct drm_display_mode *mode; 5360 5361 list_for_each_entry(mode, &connector->probed_modes, head) { 5362 if (mode->hdisplay == hpref && 5363 mode->vdisplay == vpref) 5364 mode->type |= DRM_MODE_TYPE_PREFERRED; 5365 } 5366 } 5367 EXPORT_SYMBOL(drm_set_preferred_mode); 5368 5369 static bool is_hdmi2_sink(struct drm_connector *connector) 5370 { 5371 /* 5372 * FIXME: sil-sii8620 doesn't have a connector around when 5373 * we need one, so we have to be prepared for a NULL connector. 5374 */ 5375 if (!connector) 5376 return true; 5377 5378 return connector->display_info.hdmi.scdc.supported || 5379 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5380 } 5381 5382 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5383 { 5384 return sink_eotf & BIT(output_eotf); 5385 } 5386 5387 /** 5388 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5389 * HDR metadata from userspace 5390 * @frame: HDMI DRM infoframe 5391 * @conn_state: Connector state containing HDR metadata 5392 * 5393 * Return: 0 on success or a negative error code on failure. 5394 */ 5395 int 5396 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5397 const struct drm_connector_state *conn_state) 5398 { 5399 struct drm_connector *connector; 5400 struct hdr_output_metadata *hdr_metadata; 5401 int err; 5402 5403 if (!frame || !conn_state) 5404 return -EINVAL; 5405 5406 connector = conn_state->connector; 5407 5408 if (!conn_state->hdr_output_metadata) 5409 return -EINVAL; 5410 5411 hdr_metadata = conn_state->hdr_output_metadata->data; 5412 5413 if (!hdr_metadata || !connector) 5414 return -EINVAL; 5415 5416 /* Sink EOTF is Bit map while infoframe is absolute values */ 5417 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5418 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5419 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5420 return -EINVAL; 5421 } 5422 5423 err = hdmi_drm_infoframe_init(frame); 5424 if (err < 0) 5425 return err; 5426 5427 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5428 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5429 5430 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5431 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5432 BUILD_BUG_ON(sizeof(frame->white_point) != 5433 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5434 5435 memcpy(&frame->display_primaries, 5436 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5437 sizeof(frame->display_primaries)); 5438 5439 memcpy(&frame->white_point, 5440 &hdr_metadata->hdmi_metadata_type1.white_point, 5441 sizeof(frame->white_point)); 5442 5443 frame->max_display_mastering_luminance = 5444 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5445 frame->min_display_mastering_luminance = 5446 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5447 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5448 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5449 5450 return 0; 5451 } 5452 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5453 5454 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5455 const struct drm_display_mode *mode) 5456 { 5457 bool has_hdmi_infoframe = connector ? 5458 connector->display_info.has_hdmi_infoframe : false; 5459 5460 if (!has_hdmi_infoframe) 5461 return 0; 5462 5463 /* No HDMI VIC when signalling 3D video format */ 5464 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5465 return 0; 5466 5467 return drm_match_hdmi_mode(mode); 5468 } 5469 5470 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5471 const struct drm_display_mode *mode) 5472 { 5473 u8 vic; 5474 5475 /* 5476 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5477 * we should send its VIC in vendor infoframes, else send the 5478 * VIC in AVI infoframes. Lets check if this mode is present in 5479 * HDMI 1.4b 4K modes 5480 */ 5481 if (drm_mode_hdmi_vic(connector, mode)) 5482 return 0; 5483 5484 vic = drm_match_cea_mode(mode); 5485 5486 /* 5487 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5488 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5489 * have to make sure we dont break HDMI 1.4 sinks. 5490 */ 5491 if (!is_hdmi2_sink(connector) && vic > 64) 5492 return 0; 5493 5494 return vic; 5495 } 5496 5497 /** 5498 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5499 * data from a DRM display mode 5500 * @frame: HDMI AVI infoframe 5501 * @connector: the connector 5502 * @mode: DRM display mode 5503 * 5504 * Return: 0 on success or a negative error code on failure. 5505 */ 5506 int 5507 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5508 struct drm_connector *connector, 5509 const struct drm_display_mode *mode) 5510 { 5511 enum hdmi_picture_aspect picture_aspect; 5512 u8 vic, hdmi_vic; 5513 5514 if (!frame || !mode) 5515 return -EINVAL; 5516 5517 hdmi_avi_infoframe_init(frame); 5518 5519 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5520 frame->pixel_repeat = 1; 5521 5522 vic = drm_mode_cea_vic(connector, mode); 5523 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5524 5525 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5526 5527 /* 5528 * As some drivers don't support atomic, we can't use connector state. 5529 * So just initialize the frame with default values, just the same way 5530 * as it's done with other properties here. 5531 */ 5532 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5533 frame->itc = 0; 5534 5535 /* 5536 * Populate picture aspect ratio from either 5537 * user input (if specified) or from the CEA/HDMI mode lists. 5538 */ 5539 picture_aspect = mode->picture_aspect_ratio; 5540 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5541 if (vic) 5542 picture_aspect = drm_get_cea_aspect_ratio(vic); 5543 else if (hdmi_vic) 5544 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5545 } 5546 5547 /* 5548 * The infoframe can't convey anything but none, 4:3 5549 * and 16:9, so if the user has asked for anything else 5550 * we can only satisfy it by specifying the right VIC. 5551 */ 5552 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5553 if (vic) { 5554 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5555 return -EINVAL; 5556 } else if (hdmi_vic) { 5557 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5558 return -EINVAL; 5559 } else { 5560 return -EINVAL; 5561 } 5562 5563 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5564 } 5565 5566 frame->video_code = vic; 5567 frame->picture_aspect = picture_aspect; 5568 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5569 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5570 5571 return 0; 5572 } 5573 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5574 5575 /* HDMI Colorspace Spec Definitions */ 5576 #define FULL_COLORIMETRY_MASK 0x1FF 5577 #define NORMAL_COLORIMETRY_MASK 0x3 5578 #define EXTENDED_COLORIMETRY_MASK 0x7 5579 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5580 5581 #define C(x) ((x) << 0) 5582 #define EC(x) ((x) << 2) 5583 #define ACE(x) ((x) << 5) 5584 5585 #define HDMI_COLORIMETRY_NO_DATA 0x0 5586 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5587 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5588 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5589 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5590 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5591 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5592 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5593 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5594 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5595 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5596 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5597 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5598 5599 static const u32 hdmi_colorimetry_val[] = { 5600 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5601 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5602 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5603 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5604 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5605 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5606 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5607 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5608 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5609 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5610 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5611 }; 5612 5613 #undef C 5614 #undef EC 5615 #undef ACE 5616 5617 /** 5618 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5619 * colorspace information 5620 * @frame: HDMI AVI infoframe 5621 * @conn_state: connector state 5622 */ 5623 void 5624 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5625 const struct drm_connector_state *conn_state) 5626 { 5627 u32 colorimetry_val; 5628 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5629 5630 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5631 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5632 else 5633 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5634 5635 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5636 /* 5637 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5638 * structure and extend it in drivers/video/hdmi 5639 */ 5640 frame->extended_colorimetry = (colorimetry_val >> 2) & 5641 EXTENDED_COLORIMETRY_MASK; 5642 } 5643 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5644 5645 /** 5646 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5647 * quantization range information 5648 * @frame: HDMI AVI infoframe 5649 * @connector: the connector 5650 * @mode: DRM display mode 5651 * @rgb_quant_range: RGB quantization range (Q) 5652 */ 5653 void 5654 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5655 struct drm_connector *connector, 5656 const struct drm_display_mode *mode, 5657 enum hdmi_quantization_range rgb_quant_range) 5658 { 5659 const struct drm_display_info *info = &connector->display_info; 5660 5661 /* 5662 * CEA-861: 5663 * "A Source shall not send a non-zero Q value that does not correspond 5664 * to the default RGB Quantization Range for the transmitted Picture 5665 * unless the Sink indicates support for the Q bit in a Video 5666 * Capabilities Data Block." 5667 * 5668 * HDMI 2.0 recommends sending non-zero Q when it does match the 5669 * default RGB quantization range for the mode, even when QS=0. 5670 */ 5671 if (info->rgb_quant_range_selectable || 5672 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5673 frame->quantization_range = rgb_quant_range; 5674 else 5675 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5676 5677 /* 5678 * CEA-861-F: 5679 * "When transmitting any RGB colorimetry, the Source should set the 5680 * YQ-field to match the RGB Quantization Range being transmitted 5681 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5682 * set YQ=1) and the Sink shall ignore the YQ-field." 5683 * 5684 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5685 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5686 * good way to tell which version of CEA-861 the sink supports, so 5687 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5688 * on on CEA-861-F. 5689 */ 5690 if (!is_hdmi2_sink(connector) || 5691 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5692 frame->ycc_quantization_range = 5693 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5694 else 5695 frame->ycc_quantization_range = 5696 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5697 } 5698 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5699 5700 /** 5701 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5702 * bar information 5703 * @frame: HDMI AVI infoframe 5704 * @conn_state: connector state 5705 */ 5706 void 5707 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5708 const struct drm_connector_state *conn_state) 5709 { 5710 frame->right_bar = conn_state->tv.margins.right; 5711 frame->left_bar = conn_state->tv.margins.left; 5712 frame->top_bar = conn_state->tv.margins.top; 5713 frame->bottom_bar = conn_state->tv.margins.bottom; 5714 } 5715 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5716 5717 static enum hdmi_3d_structure 5718 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5719 { 5720 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5721 5722 switch (layout) { 5723 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5724 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5725 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5726 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5727 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5728 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5729 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5730 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5731 case DRM_MODE_FLAG_3D_L_DEPTH: 5732 return HDMI_3D_STRUCTURE_L_DEPTH; 5733 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5734 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5735 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5736 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5737 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5738 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5739 default: 5740 return HDMI_3D_STRUCTURE_INVALID; 5741 } 5742 } 5743 5744 /** 5745 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5746 * data from a DRM display mode 5747 * @frame: HDMI vendor infoframe 5748 * @connector: the connector 5749 * @mode: DRM display mode 5750 * 5751 * Note that there's is a need to send HDMI vendor infoframes only when using a 5752 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5753 * function will return -EINVAL, error that can be safely ignored. 5754 * 5755 * Return: 0 on success or a negative error code on failure. 5756 */ 5757 int 5758 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5759 struct drm_connector *connector, 5760 const struct drm_display_mode *mode) 5761 { 5762 /* 5763 * FIXME: sil-sii8620 doesn't have a connector around when 5764 * we need one, so we have to be prepared for a NULL connector. 5765 */ 5766 bool has_hdmi_infoframe = connector ? 5767 connector->display_info.has_hdmi_infoframe : false; 5768 int err; 5769 5770 if (!frame || !mode) 5771 return -EINVAL; 5772 5773 if (!has_hdmi_infoframe) 5774 return -EINVAL; 5775 5776 err = hdmi_vendor_infoframe_init(frame); 5777 if (err < 0) 5778 return err; 5779 5780 /* 5781 * Even if it's not absolutely necessary to send the infoframe 5782 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5783 * know that the sink can handle it. This is based on a 5784 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5785 * have trouble realizing that they shuld switch from 3D to 2D 5786 * mode if the source simply stops sending the infoframe when 5787 * it wants to switch from 3D to 2D. 5788 */ 5789 frame->vic = drm_mode_hdmi_vic(connector, mode); 5790 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5791 5792 return 0; 5793 } 5794 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5795 5796 static int drm_parse_tiled_block(struct drm_connector *connector, 5797 const struct displayid_block *block) 5798 { 5799 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5800 u16 w, h; 5801 u8 tile_v_loc, tile_h_loc; 5802 u8 num_v_tile, num_h_tile; 5803 struct drm_tile_group *tg; 5804 5805 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5806 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5807 5808 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5809 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5810 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5811 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5812 5813 connector->has_tile = true; 5814 if (tile->tile_cap & 0x80) 5815 connector->tile_is_single_monitor = true; 5816 5817 connector->num_h_tile = num_h_tile + 1; 5818 connector->num_v_tile = num_v_tile + 1; 5819 connector->tile_h_loc = tile_h_loc; 5820 connector->tile_v_loc = tile_v_loc; 5821 connector->tile_h_size = w + 1; 5822 connector->tile_v_size = h + 1; 5823 5824 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5825 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5826 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5827 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5828 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5829 5830 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5831 if (!tg) { 5832 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5833 } 5834 if (!tg) 5835 return -ENOMEM; 5836 5837 if (connector->tile_group != tg) { 5838 /* if we haven't got a pointer, 5839 take the reference, drop ref to old tile group */ 5840 if (connector->tile_group) { 5841 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5842 } 5843 connector->tile_group = tg; 5844 } else 5845 /* if same tile group, then release the ref we just took. */ 5846 drm_mode_put_tile_group(connector->dev, tg); 5847 return 0; 5848 } 5849 5850 static int drm_displayid_parse_tiled(struct drm_connector *connector, 5851 const u8 *displayid, int length, int idx) 5852 { 5853 const struct displayid_block *block; 5854 int ret; 5855 5856 idx += sizeof(struct displayid_hdr); 5857 for_each_displayid_db(displayid, block, idx, length) { 5858 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5859 block->tag, block->rev, block->num_bytes); 5860 5861 switch (block->tag) { 5862 case DATA_BLOCK_TILED_DISPLAY: 5863 ret = drm_parse_tiled_block(connector, block); 5864 if (ret) 5865 return ret; 5866 break; 5867 default: 5868 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5869 break; 5870 } 5871 } 5872 return 0; 5873 } 5874 5875 void drm_update_tile_info(struct drm_connector *connector, 5876 const struct edid *edid) 5877 { 5878 const void *displayid = NULL; 5879 int length, idx; 5880 int ret; 5881 5882 connector->has_tile = false; 5883 displayid = drm_find_displayid_extension(edid, &length, &idx); 5884 if (!displayid) { 5885 /* drop reference to any tile group we had */ 5886 goto out_drop_ref; 5887 } 5888 5889 ret = drm_displayid_parse_tiled(connector, displayid, length, idx); 5890 if (ret < 0) 5891 goto out_drop_ref; 5892 if (!connector->has_tile) 5893 goto out_drop_ref; 5894 return; 5895 out_drop_ref: 5896 if (connector->tile_group) { 5897 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5898 connector->tile_group = NULL; 5899 } 5900 return; 5901 } 5902