1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 u32 quirks; 100 int modes; 101 }; 102 103 #define LEVEL_DMT 0 104 #define LEVEL_GTF 1 105 #define LEVEL_GTF2 2 106 #define LEVEL_CVT 3 107 108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 109 { \ 110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 111 product_id), \ 112 .quirks = _quirks \ 113 } 114 115 static const struct edid_quirk { 116 u32 panel_id; 117 u32 quirks; 118 } edid_quirk_list[] = { 119 /* Acer AL1706 */ 120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 121 /* Acer F51 */ 122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 123 124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 126 127 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 128 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 129 130 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 131 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 132 133 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 134 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 135 136 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 137 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 138 139 /* Belinea 10 15 55 */ 140 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 141 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 142 143 /* Envision Peripherals, Inc. EN-7100e */ 144 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 145 /* Envision EN2028 */ 146 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 147 148 /* Funai Electronics PM36B */ 149 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 150 EDID_QUIRK_DETAILED_IN_CM), 151 152 /* LG 27GP950 */ 153 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 154 155 /* LG 27GN950 */ 156 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 157 158 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 159 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 160 161 /* LG Philips LCD LP154W01-A5 */ 162 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 163 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 164 165 /* Samsung SyncMaster 205BW. Note: irony */ 166 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 167 /* Samsung SyncMaster 22[5-6]BW */ 168 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 169 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 170 171 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 172 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 173 174 /* ViewSonic VA2026w */ 175 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 176 177 /* Medion MD 30217 PG */ 178 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 179 180 /* Lenovo G50 */ 181 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 182 183 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 184 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 185 186 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 187 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 188 189 /* Valve Index Headset */ 190 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 207 208 /* HTC Vive and Vive Pro VR Headsets */ 209 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 211 212 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 213 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 217 218 /* Windows Mixed Reality Headsets */ 219 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 221 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 224 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 225 226 /* Sony PlayStation VR Headset */ 227 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 228 229 /* Sensics VR Headsets */ 230 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 231 232 /* OSVR HDK and HDK2 VR Headsets */ 233 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 234 }; 235 236 /* 237 * Autogenerated from the DMT spec. 238 * This table is copied from xfree86/modes/xf86EdidModes.c. 239 */ 240 static const struct drm_display_mode drm_dmt_modes[] = { 241 /* 0x01 - 640x350@85Hz */ 242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 243 736, 832, 0, 350, 382, 385, 445, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x02 - 640x400@85Hz */ 246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 247 736, 832, 0, 400, 401, 404, 445, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x03 - 720x400@85Hz */ 250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 251 828, 936, 0, 400, 401, 404, 446, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x04 - 640x480@60Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 255 752, 800, 0, 480, 490, 492, 525, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x05 - 640x480@72Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 259 704, 832, 0, 480, 489, 492, 520, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x06 - 640x480@75Hz */ 262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 263 720, 840, 0, 480, 481, 484, 500, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x07 - 640x480@85Hz */ 266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 267 752, 832, 0, 480, 481, 484, 509, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 269 /* 0x08 - 800x600@56Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 271 896, 1024, 0, 600, 601, 603, 625, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x09 - 800x600@60Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 275 968, 1056, 0, 600, 601, 605, 628, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0a - 800x600@72Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 279 976, 1040, 0, 600, 637, 643, 666, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0b - 800x600@75Hz */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 283 896, 1056, 0, 600, 601, 604, 625, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x0c - 800x600@85Hz */ 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 287 896, 1048, 0, 600, 601, 604, 631, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x0d - 800x600@120Hz RB */ 290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 291 880, 960, 0, 600, 603, 607, 636, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x0e - 848x480@60Hz */ 294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 295 976, 1088, 0, 480, 486, 494, 517, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x0f - 1024x768@43Hz, interlace */ 298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 299 1208, 1264, 0, 768, 768, 776, 817, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 301 DRM_MODE_FLAG_INTERLACE) }, 302 /* 0x10 - 1024x768@60Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 304 1184, 1344, 0, 768, 771, 777, 806, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x11 - 1024x768@70Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 308 1184, 1328, 0, 768, 771, 777, 806, 0, 309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 310 /* 0x12 - 1024x768@75Hz */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 312 1136, 1312, 0, 768, 769, 772, 800, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x13 - 1024x768@85Hz */ 315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 316 1168, 1376, 0, 768, 769, 772, 808, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x14 - 1024x768@120Hz RB */ 319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 320 1104, 1184, 0, 768, 771, 775, 813, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x15 - 1152x864@75Hz */ 323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 324 1344, 1600, 0, 864, 865, 868, 900, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x55 - 1280x720@60Hz */ 327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 328 1430, 1650, 0, 720, 725, 730, 750, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x16 - 1280x768@60Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 790, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x17 - 1280x768@60Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 336 1472, 1664, 0, 768, 771, 778, 798, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x18 - 1280x768@75Hz */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 340 1488, 1696, 0, 768, 771, 778, 805, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x19 - 1280x768@85Hz */ 343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 344 1496, 1712, 0, 768, 771, 778, 809, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1a - 1280x768@120Hz RB */ 347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 348 1360, 1440, 0, 768, 771, 778, 813, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x1b - 1280x800@60Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 823, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x1c - 1280x800@60Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 356 1480, 1680, 0, 800, 803, 809, 831, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1d - 1280x800@75Hz */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 360 1488, 1696, 0, 800, 803, 809, 838, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x1e - 1280x800@85Hz */ 363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 364 1496, 1712, 0, 800, 803, 809, 843, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x1f - 1280x800@120Hz RB */ 367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 368 1360, 1440, 0, 800, 803, 809, 847, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x20 - 1280x960@60Hz */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 372 1488, 1800, 0, 960, 961, 964, 1000, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x21 - 1280x960@85Hz */ 375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 376 1504, 1728, 0, 960, 961, 964, 1011, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x22 - 1280x960@120Hz RB */ 379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 380 1360, 1440, 0, 960, 963, 967, 1017, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x23 - 1280x1024@60Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x24 - 1280x1024@75Hz */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x25 - 1280x1024@85Hz */ 391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x26 - 1280x1024@120Hz RB */ 395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x27 - 1360x768@60Hz */ 399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 400 1536, 1792, 0, 768, 771, 777, 795, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x28 - 1360x768@120Hz RB */ 403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 404 1440, 1520, 0, 768, 771, 776, 813, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 406 /* 0x51 - 1366x768@60Hz */ 407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 408 1579, 1792, 0, 768, 771, 774, 798, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x56 - 1366x768@60Hz */ 411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 412 1436, 1500, 0, 768, 769, 772, 800, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x29 - 1400x1050@60Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2a - 1400x1050@60Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2b - 1400x1050@75Hz */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x2c - 1400x1050@85Hz */ 427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x2d - 1400x1050@120Hz RB */ 431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x2e - 1440x900@60Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 926, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x2f - 1440x900@60Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 440 1672, 1904, 0, 900, 903, 909, 934, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x30 - 1440x900@75Hz */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 444 1688, 1936, 0, 900, 903, 909, 942, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x31 - 1440x900@85Hz */ 447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 448 1696, 1952, 0, 900, 903, 909, 948, 0, 449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x32 - 1440x900@120Hz RB */ 451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 452 1520, 1600, 0, 900, 903, 909, 953, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 454 /* 0x53 - 1600x900@60Hz */ 455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 456 1704, 1800, 0, 900, 901, 904, 1000, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x33 - 1600x1200@60Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x34 - 1600x1200@65Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x35 - 1600x1200@70Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x36 - 1600x1200@75Hz */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x37 - 1600x1200@85Hz */ 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x38 - 1600x1200@120Hz RB */ 479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x39 - 1680x1050@60Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3a - 1680x1050@60Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3b - 1680x1050@75Hz */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x3c - 1680x1050@85Hz */ 495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x3d - 1680x1050@120Hz RB */ 499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x3e - 1792x1344@60Hz */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x3f - 1792x1344@75Hz */ 507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x40 - 1792x1344@120Hz RB */ 511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x41 - 1856x1392@60Hz */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x42 - 1856x1392@75Hz */ 519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x43 - 1856x1392@120Hz RB */ 523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x52 - 1920x1080@60Hz */ 527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x44 - 1920x1200@60Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x45 - 1920x1200@60Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x46 - 1920x1200@75Hz */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x47 - 1920x1200@85Hz */ 543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 546 /* 0x48 - 1920x1200@120Hz RB */ 547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 550 /* 0x49 - 1920x1440@60Hz */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4a - 1920x1440@75Hz */ 555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4b - 1920x1440@120Hz RB */ 559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 562 /* 0x54 - 2048x1152@60Hz */ 563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x4c - 2560x1600@60Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x4d - 2560x1600@60Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x4e - 2560x1600@75Hz */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 578 /* 0x4f - 2560x1600@85Hz */ 579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 582 /* 0x50 - 2560x1600@120Hz RB */ 583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x57 - 4096x2160@60Hz RB */ 587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 590 /* 0x58 - 4096x2160@59.94Hz RB */ 591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 594 }; 595 596 /* 597 * These more or less come from the DMT spec. The 720x400 modes are 598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 601 * mode. 602 * 603 * The DMT modes have been fact-checked; the rest are mild guesses. 604 */ 605 static const struct drm_display_mode edid_est_modes[] = { 606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 607 968, 1056, 0, 600, 601, 605, 628, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 610 896, 1024, 0, 600, 601, 603, 625, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 613 720, 840, 0, 480, 481, 484, 500, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 616 704, 832, 0, 480, 489, 492, 520, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 619 768, 864, 0, 480, 483, 486, 525, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 622 752, 800, 0, 480, 490, 492, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 625 846, 900, 0, 400, 421, 423, 449, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 628 846, 900, 0, 400, 412, 414, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 634 1136, 1312, 0, 768, 769, 772, 800, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 637 1184, 1328, 0, 768, 771, 777, 806, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 640 1184, 1344, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 643 1208, 1264, 0, 768, 768, 776, 817, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 646 928, 1152, 0, 624, 625, 628, 667, 0, 647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 649 896, 1056, 0, 600, 601, 604, 625, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 652 976, 1040, 0, 600, 637, 643, 666, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 655 1344, 1600, 0, 864, 865, 868, 900, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 657 }; 658 659 struct minimode { 660 short w; 661 short h; 662 short r; 663 short rb; 664 }; 665 666 static const struct minimode est3_modes[] = { 667 /* byte 6 */ 668 { 640, 350, 85, 0 }, 669 { 640, 400, 85, 0 }, 670 { 720, 400, 85, 0 }, 671 { 640, 480, 85, 0 }, 672 { 848, 480, 60, 0 }, 673 { 800, 600, 85, 0 }, 674 { 1024, 768, 85, 0 }, 675 { 1152, 864, 75, 0 }, 676 /* byte 7 */ 677 { 1280, 768, 60, 1 }, 678 { 1280, 768, 60, 0 }, 679 { 1280, 768, 75, 0 }, 680 { 1280, 768, 85, 0 }, 681 { 1280, 960, 60, 0 }, 682 { 1280, 960, 85, 0 }, 683 { 1280, 1024, 60, 0 }, 684 { 1280, 1024, 85, 0 }, 685 /* byte 8 */ 686 { 1360, 768, 60, 0 }, 687 { 1440, 900, 60, 1 }, 688 { 1440, 900, 60, 0 }, 689 { 1440, 900, 75, 0 }, 690 { 1440, 900, 85, 0 }, 691 { 1400, 1050, 60, 1 }, 692 { 1400, 1050, 60, 0 }, 693 { 1400, 1050, 75, 0 }, 694 /* byte 9 */ 695 { 1400, 1050, 85, 0 }, 696 { 1680, 1050, 60, 1 }, 697 { 1680, 1050, 60, 0 }, 698 { 1680, 1050, 75, 0 }, 699 { 1680, 1050, 85, 0 }, 700 { 1600, 1200, 60, 0 }, 701 { 1600, 1200, 65, 0 }, 702 { 1600, 1200, 70, 0 }, 703 /* byte 10 */ 704 { 1600, 1200, 75, 0 }, 705 { 1600, 1200, 85, 0 }, 706 { 1792, 1344, 60, 0 }, 707 { 1792, 1344, 75, 0 }, 708 { 1856, 1392, 60, 0 }, 709 { 1856, 1392, 75, 0 }, 710 { 1920, 1200, 60, 1 }, 711 { 1920, 1200, 60, 0 }, 712 /* byte 11 */ 713 { 1920, 1200, 75, 0 }, 714 { 1920, 1200, 85, 0 }, 715 { 1920, 1440, 60, 0 }, 716 { 1920, 1440, 75, 0 }, 717 }; 718 719 static const struct minimode extra_modes[] = { 720 { 1024, 576, 60, 0 }, 721 { 1366, 768, 60, 0 }, 722 { 1600, 900, 60, 0 }, 723 { 1680, 945, 60, 0 }, 724 { 1920, 1080, 60, 0 }, 725 { 2048, 1152, 60, 0 }, 726 { 2048, 1536, 60, 0 }, 727 }; 728 729 /* 730 * From CEA/CTA-861 spec. 731 * 732 * Do not access directly, instead always use cea_mode_for_vic(). 733 */ 734 static const struct drm_display_mode edid_cea_modes_1[] = { 735 /* 1 - 640x480@60Hz 4:3 */ 736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 737 752, 800, 0, 480, 490, 492, 525, 0, 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 740 /* 2 - 720x480@60Hz 4:3 */ 741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 742 798, 858, 0, 480, 489, 495, 525, 0, 743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 745 /* 3 - 720x480@60Hz 16:9 */ 746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 747 798, 858, 0, 480, 489, 495, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 750 /* 4 - 1280x720@60Hz 16:9 */ 751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 752 1430, 1650, 0, 720, 725, 730, 750, 0, 753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 755 /* 5 - 1920x1080i@60Hz 16:9 */ 756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 759 DRM_MODE_FLAG_INTERLACE), 760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 761 /* 6 - 720(1440)x480i@60Hz 4:3 */ 762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 763 801, 858, 0, 480, 488, 494, 525, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 767 /* 7 - 720(1440)x480i@60Hz 16:9 */ 768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 769 801, 858, 0, 480, 488, 494, 525, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 8 - 720(1440)x240@60Hz 4:3 */ 774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 775 801, 858, 0, 240, 244, 247, 262, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 777 DRM_MODE_FLAG_DBLCLK), 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 779 /* 9 - 720(1440)x240@60Hz 16:9 */ 780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 781 801, 858, 0, 240, 244, 247, 262, 0, 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 783 DRM_MODE_FLAG_DBLCLK), 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 785 /* 10 - 2880x480i@60Hz 4:3 */ 786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 480, 488, 494, 525, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 789 DRM_MODE_FLAG_INTERLACE), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 791 /* 11 - 2880x480i@60Hz 16:9 */ 792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 793 3204, 3432, 0, 480, 488, 494, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_INTERLACE), 796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 12 - 2880x240@60Hz 4:3 */ 798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 799 3204, 3432, 0, 240, 244, 247, 262, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 13 - 2880x240@60Hz 16:9 */ 803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 804 3204, 3432, 0, 240, 244, 247, 262, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 14 - 1440x480@60Hz 4:3 */ 808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 809 1596, 1716, 0, 480, 489, 495, 525, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 15 - 1440x480@60Hz 16:9 */ 813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 814 1596, 1716, 0, 480, 489, 495, 525, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 16 - 1920x1080@60Hz 16:9 */ 818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 17 - 720x576@50Hz 4:3 */ 823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 824 796, 864, 0, 576, 581, 586, 625, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 827 /* 18 - 720x576@50Hz 16:9 */ 828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 829 796, 864, 0, 576, 581, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 19 - 1280x720@50Hz 16:9 */ 833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 834 1760, 1980, 0, 720, 725, 730, 750, 0, 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 837 /* 20 - 1920x1080i@50Hz 16:9 */ 838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 841 DRM_MODE_FLAG_INTERLACE), 842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 21 - 720(1440)x576i@50Hz 4:3 */ 844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 845 795, 864, 0, 576, 580, 586, 625, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 849 /* 22 - 720(1440)x576i@50Hz 16:9 */ 850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 851 795, 864, 0, 576, 580, 586, 625, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 23 - 720(1440)x288@50Hz 4:3 */ 856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 857 795, 864, 0, 288, 290, 293, 312, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 859 DRM_MODE_FLAG_DBLCLK), 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 861 /* 24 - 720(1440)x288@50Hz 16:9 */ 862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 863 795, 864, 0, 288, 290, 293, 312, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 865 DRM_MODE_FLAG_DBLCLK), 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 25 - 2880x576i@50Hz 4:3 */ 868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 576, 580, 586, 625, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 871 DRM_MODE_FLAG_INTERLACE), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 873 /* 26 - 2880x576i@50Hz 16:9 */ 874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 875 3180, 3456, 0, 576, 580, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 877 DRM_MODE_FLAG_INTERLACE), 878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 879 /* 27 - 2880x288@50Hz 4:3 */ 880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 881 3180, 3456, 0, 288, 290, 293, 312, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 884 /* 28 - 2880x288@50Hz 16:9 */ 885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 886 3180, 3456, 0, 288, 290, 293, 312, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 29 - 1440x576@50Hz 4:3 */ 890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 891 1592, 1728, 0, 576, 581, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 894 /* 30 - 1440x576@50Hz 16:9 */ 895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 896 1592, 1728, 0, 576, 581, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 31 - 1920x1080@50Hz 16:9 */ 900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 32 - 1920x1080@24Hz 16:9 */ 905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 33 - 1920x1080@25Hz 16:9 */ 910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 34 - 1920x1080@30Hz 16:9 */ 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 35 - 2880x480@60Hz 4:3 */ 920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 921 3192, 3432, 0, 480, 489, 495, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 36 - 2880x480@60Hz 16:9 */ 925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 926 3192, 3432, 0, 480, 489, 495, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 37 - 2880x576@50Hz 4:3 */ 930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 931 3184, 3456, 0, 576, 581, 586, 625, 0, 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 934 /* 38 - 2880x576@50Hz 16:9 */ 935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 936 3184, 3456, 0, 576, 581, 586, 625, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 39 - 1920x1080i@50Hz 16:9 */ 940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 943 DRM_MODE_FLAG_INTERLACE), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 40 - 1920x1080i@100Hz 16:9 */ 946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 949 DRM_MODE_FLAG_INTERLACE), 950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 41 - 1280x720@100Hz 16:9 */ 952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 953 1760, 1980, 0, 720, 725, 730, 750, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 42 - 720x576@100Hz 4:3 */ 957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 796, 864, 0, 576, 581, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 961 /* 43 - 720x576@100Hz 16:9 */ 962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 963 796, 864, 0, 576, 581, 586, 625, 0, 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 44 - 720(1440)x576i@100Hz 4:3 */ 967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 968 795, 864, 0, 576, 580, 586, 625, 0, 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 972 /* 45 - 720(1440)x576i@100Hz 16:9 */ 973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 974 795, 864, 0, 576, 580, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 978 /* 46 - 1920x1080i@120Hz 16:9 */ 979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 982 DRM_MODE_FLAG_INTERLACE), 983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 47 - 1280x720@120Hz 16:9 */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 986 1430, 1650, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 48 - 720x480@120Hz 4:3 */ 990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 991 798, 858, 0, 480, 489, 495, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 994 /* 49 - 720x480@120Hz 16:9 */ 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 996 798, 858, 0, 480, 489, 495, 525, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1001 801, 858, 0, 480, 488, 494, 525, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1005 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1007 801, 858, 0, 480, 488, 494, 525, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1011 /* 52 - 720x576@200Hz 4:3 */ 1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1013 796, 864, 0, 576, 581, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1016 /* 53 - 720x576@200Hz 16:9 */ 1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1018 796, 864, 0, 576, 581, 586, 625, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1021 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1023 795, 864, 0, 576, 580, 586, 625, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1027 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1029 795, 864, 0, 576, 580, 586, 625, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1033 /* 56 - 720x480@240Hz 4:3 */ 1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1035 798, 858, 0, 480, 489, 495, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1038 /* 57 - 720x480@240Hz 16:9 */ 1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1040 798, 858, 0, 480, 489, 495, 525, 0, 1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1045 801, 858, 0, 480, 488, 494, 525, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1049 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1051 801, 858, 0, 480, 488, 494, 525, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1055 /* 60 - 1280x720@24Hz 16:9 */ 1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1057 3080, 3300, 0, 720, 725, 730, 750, 0, 1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1060 /* 61 - 1280x720@25Hz 16:9 */ 1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1062 3740, 3960, 0, 720, 725, 730, 750, 0, 1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1065 /* 62 - 1280x720@30Hz 16:9 */ 1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1067 3080, 3300, 0, 720, 725, 730, 750, 0, 1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 63 - 1920x1080@120Hz 16:9 */ 1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1075 /* 64 - 1920x1080@100Hz 16:9 */ 1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1080 /* 65 - 1280x720@24Hz 64:27 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1085 /* 66 - 1280x720@25Hz 64:27 */ 1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1087 3740, 3960, 0, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1090 /* 67 - 1280x720@30Hz 64:27 */ 1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1092 3080, 3300, 0, 720, 725, 730, 750, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1095 /* 68 - 1280x720@50Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1097 1760, 1980, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 69 - 1280x720@60Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1102 1430, 1650, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 70 - 1280x720@100Hz 64:27 */ 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1107 1760, 1980, 0, 720, 725, 730, 750, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 71 - 1280x720@120Hz 64:27 */ 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1112 1430, 1650, 0, 720, 725, 730, 750, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 72 - 1920x1080@24Hz 64:27 */ 1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 73 - 1920x1080@25Hz 64:27 */ 1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 74 - 1920x1080@30Hz 64:27 */ 1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 75 - 1920x1080@50Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 76 - 1920x1080@60Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 77 - 1920x1080@100Hz 64:27 */ 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 78 - 1920x1080@120Hz 64:27 */ 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 79 - 1680x720@24Hz 64:27 */ 1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1152 3080, 3300, 0, 720, 725, 730, 750, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 80 - 1680x720@25Hz 64:27 */ 1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1157 2948, 3168, 0, 720, 725, 730, 750, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 81 - 1680x720@30Hz 64:27 */ 1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1162 2420, 2640, 0, 720, 725, 730, 750, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 82 - 1680x720@50Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1167 1980, 2200, 0, 720, 725, 730, 750, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 83 - 1680x720@60Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1172 1980, 2200, 0, 720, 725, 730, 750, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 84 - 1680x720@100Hz 64:27 */ 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1177 1780, 2000, 0, 720, 725, 730, 825, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 85 - 1680x720@120Hz 64:27 */ 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1182 1780, 2000, 0, 720, 725, 730, 825, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 86 - 2560x1080@24Hz 64:27 */ 1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 87 - 2560x1080@25Hz 64:27 */ 1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 88 - 2560x1080@30Hz 64:27 */ 1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 89 - 2560x1080@50Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 90 - 2560x1080@60Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 91 - 2560x1080@100Hz 64:27 */ 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1215 /* 92 - 2560x1080@120Hz 64:27 */ 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1220 /* 93 - 3840x2160@24Hz 16:9 */ 1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1225 /* 94 - 3840x2160@25Hz 16:9 */ 1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1230 /* 95 - 3840x2160@30Hz 16:9 */ 1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1235 /* 96 - 3840x2160@50Hz 16:9 */ 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1240 /* 97 - 3840x2160@60Hz 16:9 */ 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1245 /* 98 - 4096x2160@24Hz 256:135 */ 1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1250 /* 99 - 4096x2160@25Hz 256:135 */ 1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1255 /* 100 - 4096x2160@30Hz 256:135 */ 1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1260 /* 101 - 4096x2160@50Hz 256:135 */ 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1265 /* 102 - 4096x2160@60Hz 256:135 */ 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1270 /* 103 - 3840x2160@24Hz 64:27 */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1275 /* 104 - 3840x2160@25Hz 64:27 */ 1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1280 /* 105 - 3840x2160@30Hz 64:27 */ 1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1285 /* 106 - 3840x2160@50Hz 64:27 */ 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 107 - 3840x2160@60Hz 64:27 */ 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 108 - 1280x720@48Hz 16:9 */ 1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1297 2280, 2500, 0, 720, 725, 730, 750, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1300 /* 109 - 1280x720@48Hz 64:27 */ 1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1302 2280, 2500, 0, 720, 725, 730, 750, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 110 - 1680x720@48Hz 64:27 */ 1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1307 2530, 2750, 0, 720, 725, 730, 750, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 111 - 1920x1080@48Hz 16:9 */ 1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 112 - 1920x1080@48Hz 64:27 */ 1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1320 /* 113 - 2560x1080@48Hz 64:27 */ 1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 114 - 3840x2160@48Hz 16:9 */ 1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 115 - 4096x2160@48Hz 256:135 */ 1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1335 /* 116 - 3840x2160@48Hz 64:27 */ 1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 117 - 3840x2160@100Hz 16:9 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1345 /* 118 - 3840x2160@120Hz 16:9 */ 1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1350 /* 119 - 3840x2160@100Hz 64:27 */ 1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 120 - 3840x2160@120Hz 64:27 */ 1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1360 /* 121 - 5120x2160@24Hz 64:27 */ 1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1365 /* 122 - 5120x2160@25Hz 64:27 */ 1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 123 - 5120x2160@30Hz 64:27 */ 1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 124 - 5120x2160@48Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 /* 125 - 5120x2160@50Hz 64:27 */ 1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1385 /* 126 - 5120x2160@60Hz 64:27 */ 1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1390 /* 127 - 5120x2160@100Hz 64:27 */ 1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1395 }; 1396 1397 /* 1398 * From CEA/CTA-861 spec. 1399 * 1400 * Do not access directly, instead always use cea_mode_for_vic(). 1401 */ 1402 static const struct drm_display_mode edid_cea_modes_193[] = { 1403 /* 193 - 5120x2160@120Hz 64:27 */ 1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1408 /* 194 - 7680x4320@24Hz 16:9 */ 1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1413 /* 195 - 7680x4320@25Hz 16:9 */ 1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1418 /* 196 - 7680x4320@30Hz 16:9 */ 1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1423 /* 197 - 7680x4320@48Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 198 - 7680x4320@50Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 199 - 7680x4320@60Hz 16:9 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1438 /* 200 - 7680x4320@100Hz 16:9 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1443 /* 201 - 7680x4320@120Hz 16:9 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1448 /* 202 - 7680x4320@24Hz 64:27 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1453 /* 203 - 7680x4320@25Hz 64:27 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1458 /* 204 - 7680x4320@30Hz 64:27 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1463 /* 205 - 7680x4320@48Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 206 - 7680x4320@50Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 207 - 7680x4320@60Hz 64:27 */ 1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 208 - 7680x4320@100Hz 64:27 */ 1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 209 - 7680x4320@120Hz 64:27 */ 1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 210 - 10240x4320@24Hz 64:27 */ 1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 211 - 10240x4320@25Hz 64:27 */ 1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 212 - 10240x4320@30Hz 64:27 */ 1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 213 - 10240x4320@48Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 214 - 10240x4320@50Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 215 - 10240x4320@60Hz 64:27 */ 1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1518 /* 216 - 10240x4320@100Hz 64:27 */ 1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1523 /* 217 - 10240x4320@120Hz 64:27 */ 1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1528 /* 218 - 4096x2160@100Hz 256:135 */ 1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1533 /* 219 - 4096x2160@120Hz 256:135 */ 1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1538 }; 1539 1540 /* 1541 * HDMI 1.4 4k modes. Index using the VIC. 1542 */ 1543 static const struct drm_display_mode edid_4k_modes[] = { 1544 /* 0 - dummy, VICs start at 1 */ 1545 { }, 1546 /* 1 - 3840x2160@30Hz */ 1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1548 3840, 4016, 4104, 4400, 0, 1549 2160, 2168, 2178, 2250, 0, 1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1552 /* 2 - 3840x2160@25Hz */ 1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1554 3840, 4896, 4984, 5280, 0, 1555 2160, 2168, 2178, 2250, 0, 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1558 /* 3 - 3840x2160@24Hz */ 1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1560 3840, 5116, 5204, 5500, 0, 1561 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 4 - 4096x2160@24Hz (SMPTE) */ 1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1566 4096, 5116, 5204, 5500, 0, 1567 2160, 2168, 2178, 2250, 0, 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1570 }; 1571 1572 /*** DDC fetch and block validation ***/ 1573 1574 /* 1575 * The opaque EDID type, internal to drm_edid.c. 1576 */ 1577 struct drm_edid { 1578 /* Size allocated for edid */ 1579 size_t size; 1580 const struct edid *edid; 1581 }; 1582 1583 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1584 1585 static int edid_hfeeodb_block_count(const struct edid *edid) 1586 { 1587 int eeodb = edid_hfeeodb_extension_block_count(edid); 1588 1589 return eeodb ? eeodb + 1 : 0; 1590 } 1591 1592 static int edid_extension_block_count(const struct edid *edid) 1593 { 1594 return edid->extensions; 1595 } 1596 1597 static int edid_block_count(const struct edid *edid) 1598 { 1599 return edid_extension_block_count(edid) + 1; 1600 } 1601 1602 static int edid_size_by_blocks(int num_blocks) 1603 { 1604 return num_blocks * EDID_LENGTH; 1605 } 1606 1607 static int edid_size(const struct edid *edid) 1608 { 1609 return edid_size_by_blocks(edid_block_count(edid)); 1610 } 1611 1612 static const void *edid_block_data(const struct edid *edid, int index) 1613 { 1614 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1615 1616 return edid + index; 1617 } 1618 1619 static const void *edid_extension_block_data(const struct edid *edid, int index) 1620 { 1621 return edid_block_data(edid, index + 1); 1622 } 1623 1624 /* EDID block count indicated in EDID, may exceed allocated size */ 1625 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1626 { 1627 int num_blocks; 1628 1629 /* Starting point */ 1630 num_blocks = edid_block_count(drm_edid->edid); 1631 1632 /* HF-EEODB override */ 1633 if (drm_edid->size >= edid_size_by_blocks(2)) { 1634 int eeodb; 1635 1636 /* 1637 * Note: HF-EEODB may specify a smaller extension count than the 1638 * regular one. Unlike in buffer allocation, here we can use it. 1639 */ 1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1641 if (eeodb) 1642 num_blocks = eeodb; 1643 } 1644 1645 return num_blocks; 1646 } 1647 1648 /* EDID block count, limited by allocated size */ 1649 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1650 { 1651 /* Limit by allocated size */ 1652 return min(__drm_edid_block_count(drm_edid), 1653 (int)drm_edid->size / EDID_LENGTH); 1654 } 1655 1656 /* EDID extension block count, limited by allocated size */ 1657 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1658 { 1659 return drm_edid_block_count(drm_edid) - 1; 1660 } 1661 1662 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1663 { 1664 return edid_block_data(drm_edid->edid, index); 1665 } 1666 1667 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1668 int index) 1669 { 1670 return edid_extension_block_data(drm_edid->edid, index); 1671 } 1672 1673 /* 1674 * Initializer helper for legacy interfaces, where we have no choice but to 1675 * trust edid size. Not for general purpose use. 1676 */ 1677 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1678 const struct edid *edid) 1679 { 1680 if (!edid) 1681 return NULL; 1682 1683 memset(drm_edid, 0, sizeof(*drm_edid)); 1684 1685 drm_edid->edid = edid; 1686 drm_edid->size = edid_size(edid); 1687 1688 return drm_edid; 1689 } 1690 1691 /* 1692 * EDID base and extension block iterator. 1693 * 1694 * struct drm_edid_iter iter; 1695 * const u8 *block; 1696 * 1697 * drm_edid_iter_begin(drm_edid, &iter); 1698 * drm_edid_iter_for_each(block, &iter) { 1699 * // do stuff with block 1700 * } 1701 * drm_edid_iter_end(&iter); 1702 */ 1703 struct drm_edid_iter { 1704 const struct drm_edid *drm_edid; 1705 1706 /* Current block index. */ 1707 int index; 1708 }; 1709 1710 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1711 struct drm_edid_iter *iter) 1712 { 1713 memset(iter, 0, sizeof(*iter)); 1714 1715 iter->drm_edid = drm_edid; 1716 } 1717 1718 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1719 { 1720 const void *block = NULL; 1721 1722 if (!iter->drm_edid) 1723 return NULL; 1724 1725 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1726 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1727 1728 return block; 1729 } 1730 1731 #define drm_edid_iter_for_each(__block, __iter) \ 1732 while (((__block) = __drm_edid_iter_next(__iter))) 1733 1734 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1735 { 1736 memset(iter, 0, sizeof(*iter)); 1737 } 1738 1739 static const u8 edid_header[] = { 1740 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1741 }; 1742 1743 static void edid_header_fix(void *edid) 1744 { 1745 memcpy(edid, edid_header, sizeof(edid_header)); 1746 } 1747 1748 /** 1749 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1750 * @_edid: pointer to raw base EDID block 1751 * 1752 * Sanity check the header of the base EDID block. 1753 * 1754 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1755 */ 1756 int drm_edid_header_is_valid(const void *_edid) 1757 { 1758 const struct edid *edid = _edid; 1759 int i, score = 0; 1760 1761 for (i = 0; i < sizeof(edid_header); i++) { 1762 if (edid->header[i] == edid_header[i]) 1763 score++; 1764 } 1765 1766 return score; 1767 } 1768 EXPORT_SYMBOL(drm_edid_header_is_valid); 1769 1770 static int edid_fixup __read_mostly = 6; 1771 module_param_named(edid_fixup, edid_fixup, int, 0400); 1772 MODULE_PARM_DESC(edid_fixup, 1773 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1774 1775 static int edid_block_compute_checksum(const void *_block) 1776 { 1777 const u8 *block = _block; 1778 int i; 1779 u8 csum = 0, crc = 0; 1780 1781 for (i = 0; i < EDID_LENGTH - 1; i++) 1782 csum += block[i]; 1783 1784 crc = 0x100 - csum; 1785 1786 return crc; 1787 } 1788 1789 static int edid_block_get_checksum(const void *_block) 1790 { 1791 const struct edid *block = _block; 1792 1793 return block->checksum; 1794 } 1795 1796 static int edid_block_tag(const void *_block) 1797 { 1798 const u8 *block = _block; 1799 1800 return block[0]; 1801 } 1802 1803 static bool edid_block_is_zero(const void *edid) 1804 { 1805 return !memchr_inv(edid, 0, EDID_LENGTH); 1806 } 1807 1808 /** 1809 * drm_edid_are_equal - compare two edid blobs. 1810 * @edid1: pointer to first blob 1811 * @edid2: pointer to second blob 1812 * This helper can be used during probing to determine if 1813 * edid had changed. 1814 */ 1815 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1816 { 1817 int edid1_len, edid2_len; 1818 bool edid1_present = edid1 != NULL; 1819 bool edid2_present = edid2 != NULL; 1820 1821 if (edid1_present != edid2_present) 1822 return false; 1823 1824 if (edid1) { 1825 edid1_len = edid_size(edid1); 1826 edid2_len = edid_size(edid2); 1827 1828 if (edid1_len != edid2_len) 1829 return false; 1830 1831 if (memcmp(edid1, edid2, edid1_len)) 1832 return false; 1833 } 1834 1835 return true; 1836 } 1837 EXPORT_SYMBOL(drm_edid_are_equal); 1838 1839 enum edid_block_status { 1840 EDID_BLOCK_OK = 0, 1841 EDID_BLOCK_READ_FAIL, 1842 EDID_BLOCK_NULL, 1843 EDID_BLOCK_ZERO, 1844 EDID_BLOCK_HEADER_CORRUPT, 1845 EDID_BLOCK_HEADER_REPAIR, 1846 EDID_BLOCK_HEADER_FIXED, 1847 EDID_BLOCK_CHECKSUM, 1848 EDID_BLOCK_VERSION, 1849 }; 1850 1851 static enum edid_block_status edid_block_check(const void *_block, 1852 bool is_base_block) 1853 { 1854 const struct edid *block = _block; 1855 1856 if (!block) 1857 return EDID_BLOCK_NULL; 1858 1859 if (is_base_block) { 1860 int score = drm_edid_header_is_valid(block); 1861 1862 if (score < clamp(edid_fixup, 0, 8)) { 1863 if (edid_block_is_zero(block)) 1864 return EDID_BLOCK_ZERO; 1865 else 1866 return EDID_BLOCK_HEADER_CORRUPT; 1867 } 1868 1869 if (score < 8) 1870 return EDID_BLOCK_HEADER_REPAIR; 1871 } 1872 1873 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1874 if (edid_block_is_zero(block)) 1875 return EDID_BLOCK_ZERO; 1876 else 1877 return EDID_BLOCK_CHECKSUM; 1878 } 1879 1880 if (is_base_block) { 1881 if (block->version != 1) 1882 return EDID_BLOCK_VERSION; 1883 } 1884 1885 return EDID_BLOCK_OK; 1886 } 1887 1888 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1889 { 1890 return status == EDID_BLOCK_OK || 1891 status == EDID_BLOCK_HEADER_FIXED || 1892 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1893 } 1894 1895 static bool edid_block_valid(const void *block, bool base) 1896 { 1897 return edid_block_status_valid(edid_block_check(block, base), 1898 edid_block_tag(block)); 1899 } 1900 1901 static void edid_block_status_print(enum edid_block_status status, 1902 const struct edid *block, 1903 int block_num) 1904 { 1905 switch (status) { 1906 case EDID_BLOCK_OK: 1907 break; 1908 case EDID_BLOCK_READ_FAIL: 1909 pr_debug("EDID block %d read failed\n", block_num); 1910 break; 1911 case EDID_BLOCK_NULL: 1912 pr_debug("EDID block %d pointer is NULL\n", block_num); 1913 break; 1914 case EDID_BLOCK_ZERO: 1915 pr_notice("EDID block %d is all zeroes\n", block_num); 1916 break; 1917 case EDID_BLOCK_HEADER_CORRUPT: 1918 pr_notice("EDID has corrupt header\n"); 1919 break; 1920 case EDID_BLOCK_HEADER_REPAIR: 1921 pr_debug("EDID corrupt header needs repair\n"); 1922 break; 1923 case EDID_BLOCK_HEADER_FIXED: 1924 pr_debug("EDID corrupt header fixed\n"); 1925 break; 1926 case EDID_BLOCK_CHECKSUM: 1927 if (edid_block_status_valid(status, edid_block_tag(block))) { 1928 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1929 block_num, edid_block_tag(block), 1930 edid_block_compute_checksum(block)); 1931 } else { 1932 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1933 block_num, edid_block_tag(block), 1934 edid_block_compute_checksum(block)); 1935 } 1936 break; 1937 case EDID_BLOCK_VERSION: 1938 pr_notice("EDID has major version %d, instead of 1\n", 1939 block->version); 1940 break; 1941 default: 1942 WARN(1, "EDID block %d unknown edid block status code %d\n", 1943 block_num, status); 1944 break; 1945 } 1946 } 1947 1948 static void edid_block_dump(const char *level, const void *block, int block_num) 1949 { 1950 enum edid_block_status status; 1951 char prefix[20]; 1952 1953 status = edid_block_check(block, block_num == 0); 1954 if (status == EDID_BLOCK_ZERO) 1955 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1956 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1957 sprintf(prefix, "\t[%02x] BAD ", block_num); 1958 else 1959 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1960 1961 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1962 block, EDID_LENGTH, false); 1963 } 1964 1965 /** 1966 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1967 * @_block: pointer to raw EDID block 1968 * @block_num: type of block to validate (0 for base, extension otherwise) 1969 * @print_bad_edid: if true, dump bad EDID blocks to the console 1970 * @edid_corrupt: if true, the header or checksum is invalid 1971 * 1972 * Validate a base or extension EDID block and optionally dump bad blocks to 1973 * the console. 1974 * 1975 * Return: True if the block is valid, false otherwise. 1976 */ 1977 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1978 bool *edid_corrupt) 1979 { 1980 struct edid *block = (struct edid *)_block; 1981 enum edid_block_status status; 1982 bool is_base_block = block_num == 0; 1983 bool valid; 1984 1985 if (WARN_ON(!block)) 1986 return false; 1987 1988 status = edid_block_check(block, is_base_block); 1989 if (status == EDID_BLOCK_HEADER_REPAIR) { 1990 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1991 edid_header_fix(block); 1992 1993 /* Retry with fixed header, update status if that worked. */ 1994 status = edid_block_check(block, is_base_block); 1995 if (status == EDID_BLOCK_OK) 1996 status = EDID_BLOCK_HEADER_FIXED; 1997 } 1998 1999 if (edid_corrupt) { 2000 /* 2001 * Unknown major version isn't corrupt but we can't use it. Only 2002 * the base block can reset edid_corrupt to false. 2003 */ 2004 if (is_base_block && 2005 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2006 *edid_corrupt = false; 2007 else if (status != EDID_BLOCK_OK) 2008 *edid_corrupt = true; 2009 } 2010 2011 edid_block_status_print(status, block, block_num); 2012 2013 /* Determine whether we can use this block with this status. */ 2014 valid = edid_block_status_valid(status, edid_block_tag(block)); 2015 2016 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2017 pr_notice("Raw EDID:\n"); 2018 edid_block_dump(KERN_NOTICE, block, block_num); 2019 } 2020 2021 return valid; 2022 } 2023 EXPORT_SYMBOL(drm_edid_block_valid); 2024 2025 /** 2026 * drm_edid_is_valid - sanity check EDID data 2027 * @edid: EDID data 2028 * 2029 * Sanity-check an entire EDID record (including extensions) 2030 * 2031 * Return: True if the EDID data is valid, false otherwise. 2032 */ 2033 bool drm_edid_is_valid(struct edid *edid) 2034 { 2035 int i; 2036 2037 if (!edid) 2038 return false; 2039 2040 for (i = 0; i < edid_block_count(edid); i++) { 2041 void *block = (void *)edid_block_data(edid, i); 2042 2043 if (!drm_edid_block_valid(block, i, true, NULL)) 2044 return false; 2045 } 2046 2047 return true; 2048 } 2049 EXPORT_SYMBOL(drm_edid_is_valid); 2050 2051 /** 2052 * drm_edid_valid - sanity check EDID data 2053 * @drm_edid: EDID data 2054 * 2055 * Sanity check an EDID. Cross check block count against allocated size and 2056 * checksum the blocks. 2057 * 2058 * Return: True if the EDID data is valid, false otherwise. 2059 */ 2060 bool drm_edid_valid(const struct drm_edid *drm_edid) 2061 { 2062 int i; 2063 2064 if (!drm_edid) 2065 return false; 2066 2067 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2068 return false; 2069 2070 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2071 const void *block = drm_edid_block_data(drm_edid, i); 2072 2073 if (!edid_block_valid(block, i == 0)) 2074 return false; 2075 } 2076 2077 return true; 2078 } 2079 EXPORT_SYMBOL(drm_edid_valid); 2080 2081 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2082 size_t *alloc_size) 2083 { 2084 struct edid *new; 2085 int i, valid_blocks = 0; 2086 2087 /* 2088 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2089 * back to regular extension count here. We don't want to start 2090 * modifying the HF-EEODB extension too. 2091 */ 2092 for (i = 0; i < edid_block_count(edid); i++) { 2093 const void *src_block = edid_block_data(edid, i); 2094 2095 if (edid_block_valid(src_block, i == 0)) { 2096 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2097 2098 memmove(dst_block, src_block, EDID_LENGTH); 2099 valid_blocks++; 2100 } 2101 } 2102 2103 /* We already trusted the base block to be valid here... */ 2104 if (WARN_ON(!valid_blocks)) { 2105 kfree(edid); 2106 return NULL; 2107 } 2108 2109 edid->extensions = valid_blocks - 1; 2110 edid->checksum = edid_block_compute_checksum(edid); 2111 2112 *alloc_size = edid_size_by_blocks(valid_blocks); 2113 2114 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2115 if (!new) 2116 kfree(edid); 2117 2118 return new; 2119 } 2120 2121 #define DDC_SEGMENT_ADDR 0x30 2122 /** 2123 * drm_do_probe_ddc_edid() - get EDID information via I2C 2124 * @data: I2C device adapter 2125 * @buf: EDID data buffer to be filled 2126 * @block: 128 byte EDID block to start fetching from 2127 * @len: EDID data buffer length to fetch 2128 * 2129 * Try to fetch EDID information by calling I2C driver functions. 2130 * 2131 * Return: 0 on success or -1 on failure. 2132 */ 2133 static int 2134 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2135 { 2136 struct i2c_adapter *adapter = data; 2137 unsigned char start = block * EDID_LENGTH; 2138 unsigned char segment = block >> 1; 2139 unsigned char xfers = segment ? 3 : 2; 2140 int ret, retries = 5; 2141 2142 /* 2143 * The core I2C driver will automatically retry the transfer if the 2144 * adapter reports EAGAIN. However, we find that bit-banging transfers 2145 * are susceptible to errors under a heavily loaded machine and 2146 * generate spurious NAKs and timeouts. Retrying the transfer 2147 * of the individual block a few times seems to overcome this. 2148 */ 2149 do { 2150 struct i2c_msg msgs[] = { 2151 { 2152 .addr = DDC_SEGMENT_ADDR, 2153 .flags = 0, 2154 .len = 1, 2155 .buf = &segment, 2156 }, { 2157 .addr = DDC_ADDR, 2158 .flags = 0, 2159 .len = 1, 2160 .buf = &start, 2161 }, { 2162 .addr = DDC_ADDR, 2163 .flags = I2C_M_RD, 2164 .len = len, 2165 .buf = buf, 2166 } 2167 }; 2168 2169 /* 2170 * Avoid sending the segment addr to not upset non-compliant 2171 * DDC monitors. 2172 */ 2173 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2174 2175 if (ret == -ENXIO) { 2176 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2177 adapter->name); 2178 break; 2179 } 2180 } while (ret != xfers && --retries); 2181 2182 return ret == xfers ? 0 : -1; 2183 } 2184 2185 static void connector_bad_edid(struct drm_connector *connector, 2186 const struct edid *edid, int num_blocks) 2187 { 2188 int i; 2189 u8 last_block; 2190 2191 /* 2192 * 0x7e in the EDID is the number of extension blocks. The EDID 2193 * is 1 (base block) + num_ext_blocks big. That means we can think 2194 * of 0x7e in the EDID of the _index_ of the last block in the 2195 * combined chunk of memory. 2196 */ 2197 last_block = edid->extensions; 2198 2199 /* Calculate real checksum for the last edid extension block data */ 2200 if (last_block < num_blocks) 2201 connector->real_edid_checksum = 2202 edid_block_compute_checksum(edid + last_block); 2203 2204 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2205 return; 2206 2207 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2208 connector->base.id, connector->name); 2209 for (i = 0; i < num_blocks; i++) 2210 edid_block_dump(KERN_DEBUG, edid + i, i); 2211 } 2212 2213 /* Get override or firmware EDID */ 2214 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2215 { 2216 const struct drm_edid *override = NULL; 2217 2218 mutex_lock(&connector->edid_override_mutex); 2219 2220 if (connector->edid_override) 2221 override = drm_edid_dup(connector->edid_override); 2222 2223 mutex_unlock(&connector->edid_override_mutex); 2224 2225 if (!override) 2226 override = drm_edid_load_firmware(connector); 2227 2228 return IS_ERR(override) ? NULL : override; 2229 } 2230 2231 /* For debugfs edid_override implementation */ 2232 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2233 { 2234 const struct drm_edid *drm_edid; 2235 2236 mutex_lock(&connector->edid_override_mutex); 2237 2238 drm_edid = connector->edid_override; 2239 if (drm_edid) 2240 seq_write(m, drm_edid->edid, drm_edid->size); 2241 2242 mutex_unlock(&connector->edid_override_mutex); 2243 2244 return 0; 2245 } 2246 2247 /* For debugfs edid_override implementation */ 2248 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2249 size_t size) 2250 { 2251 const struct drm_edid *drm_edid; 2252 2253 drm_edid = drm_edid_alloc(edid, size); 2254 if (!drm_edid_valid(drm_edid)) { 2255 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2256 connector->base.id, connector->name); 2257 drm_edid_free(drm_edid); 2258 return -EINVAL; 2259 } 2260 2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2262 connector->base.id, connector->name); 2263 2264 mutex_lock(&connector->edid_override_mutex); 2265 2266 drm_edid_free(connector->edid_override); 2267 connector->edid_override = drm_edid; 2268 2269 mutex_unlock(&connector->edid_override_mutex); 2270 2271 return 0; 2272 } 2273 2274 /* For debugfs edid_override implementation */ 2275 int drm_edid_override_reset(struct drm_connector *connector) 2276 { 2277 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2278 connector->base.id, connector->name); 2279 2280 mutex_lock(&connector->edid_override_mutex); 2281 2282 drm_edid_free(connector->edid_override); 2283 connector->edid_override = NULL; 2284 2285 mutex_unlock(&connector->edid_override_mutex); 2286 2287 return 0; 2288 } 2289 2290 /** 2291 * drm_edid_override_connector_update - add modes from override/firmware EDID 2292 * @connector: connector we're probing 2293 * 2294 * Add modes from the override/firmware EDID, if available. Only to be used from 2295 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2296 * failed during drm_get_edid() and caused the override/firmware EDID to be 2297 * skipped. 2298 * 2299 * Return: The number of modes added or 0 if we couldn't find any. 2300 */ 2301 int drm_edid_override_connector_update(struct drm_connector *connector) 2302 { 2303 const struct drm_edid *override; 2304 int num_modes = 0; 2305 2306 override = drm_edid_override_get(connector); 2307 if (override) { 2308 num_modes = drm_edid_connector_update(connector, override); 2309 2310 drm_edid_free(override); 2311 2312 drm_dbg_kms(connector->dev, 2313 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2314 connector->base.id, connector->name, num_modes); 2315 } 2316 2317 return num_modes; 2318 } 2319 EXPORT_SYMBOL(drm_edid_override_connector_update); 2320 2321 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2322 2323 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2324 read_block_fn read_block, 2325 void *context) 2326 { 2327 enum edid_block_status status; 2328 bool is_base_block = block_num == 0; 2329 int try; 2330 2331 for (try = 0; try < 4; try++) { 2332 if (read_block(context, block, block_num, EDID_LENGTH)) 2333 return EDID_BLOCK_READ_FAIL; 2334 2335 status = edid_block_check(block, is_base_block); 2336 if (status == EDID_BLOCK_HEADER_REPAIR) { 2337 edid_header_fix(block); 2338 2339 /* Retry with fixed header, update status if that worked. */ 2340 status = edid_block_check(block, is_base_block); 2341 if (status == EDID_BLOCK_OK) 2342 status = EDID_BLOCK_HEADER_FIXED; 2343 } 2344 2345 if (edid_block_status_valid(status, edid_block_tag(block))) 2346 break; 2347 2348 /* Fail early for unrepairable base block all zeros. */ 2349 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2350 break; 2351 } 2352 2353 return status; 2354 } 2355 2356 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2357 read_block_fn read_block, void *context, 2358 size_t *size) 2359 { 2360 enum edid_block_status status; 2361 int i, num_blocks, invalid_blocks = 0; 2362 const struct drm_edid *override; 2363 struct edid *edid, *new; 2364 size_t alloc_size = EDID_LENGTH; 2365 2366 override = drm_edid_override_get(connector); 2367 if (override) { 2368 alloc_size = override->size; 2369 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2370 drm_edid_free(override); 2371 if (!edid) 2372 return NULL; 2373 goto ok; 2374 } 2375 2376 edid = kmalloc(alloc_size, GFP_KERNEL); 2377 if (!edid) 2378 return NULL; 2379 2380 status = edid_block_read(edid, 0, read_block, context); 2381 2382 edid_block_status_print(status, edid, 0); 2383 2384 if (status == EDID_BLOCK_READ_FAIL) 2385 goto fail; 2386 2387 /* FIXME: Clarify what a corrupt EDID actually means. */ 2388 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2389 connector->edid_corrupt = false; 2390 else 2391 connector->edid_corrupt = true; 2392 2393 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2394 if (status == EDID_BLOCK_ZERO) 2395 connector->null_edid_counter++; 2396 2397 connector_bad_edid(connector, edid, 1); 2398 goto fail; 2399 } 2400 2401 if (!edid_extension_block_count(edid)) 2402 goto ok; 2403 2404 alloc_size = edid_size(edid); 2405 new = krealloc(edid, alloc_size, GFP_KERNEL); 2406 if (!new) 2407 goto fail; 2408 edid = new; 2409 2410 num_blocks = edid_block_count(edid); 2411 for (i = 1; i < num_blocks; i++) { 2412 void *block = (void *)edid_block_data(edid, i); 2413 2414 status = edid_block_read(block, i, read_block, context); 2415 2416 edid_block_status_print(status, block, i); 2417 2418 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2419 if (status == EDID_BLOCK_READ_FAIL) 2420 goto fail; 2421 invalid_blocks++; 2422 } else if (i == 1) { 2423 /* 2424 * If the first EDID extension is a CTA extension, and 2425 * the first Data Block is HF-EEODB, override the 2426 * extension block count. 2427 * 2428 * Note: HF-EEODB could specify a smaller extension 2429 * count too, but we can't risk allocating a smaller 2430 * amount. 2431 */ 2432 int eeodb = edid_hfeeodb_block_count(edid); 2433 2434 if (eeodb > num_blocks) { 2435 num_blocks = eeodb; 2436 alloc_size = edid_size_by_blocks(num_blocks); 2437 new = krealloc(edid, alloc_size, GFP_KERNEL); 2438 if (!new) 2439 goto fail; 2440 edid = new; 2441 } 2442 } 2443 } 2444 2445 if (invalid_blocks) { 2446 connector_bad_edid(connector, edid, num_blocks); 2447 2448 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2449 } 2450 2451 ok: 2452 if (size) 2453 *size = alloc_size; 2454 2455 return edid; 2456 2457 fail: 2458 kfree(edid); 2459 return NULL; 2460 } 2461 2462 /** 2463 * drm_do_get_edid - get EDID data using a custom EDID block read function 2464 * @connector: connector we're probing 2465 * @read_block: EDID block read function 2466 * @context: private data passed to the block read function 2467 * 2468 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2469 * exposes a different interface to read EDID blocks this function can be used 2470 * to get EDID data using a custom block read function. 2471 * 2472 * As in the general case the DDC bus is accessible by the kernel at the I2C 2473 * level, drivers must make all reasonable efforts to expose it as an I2C 2474 * adapter and use drm_get_edid() instead of abusing this function. 2475 * 2476 * The EDID may be overridden using debugfs override_edid or firmware EDID 2477 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2478 * order. Having either of them bypasses actual EDID reads. 2479 * 2480 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2481 */ 2482 struct edid *drm_do_get_edid(struct drm_connector *connector, 2483 read_block_fn read_block, 2484 void *context) 2485 { 2486 return _drm_do_get_edid(connector, read_block, context, NULL); 2487 } 2488 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2489 2490 /** 2491 * drm_edid_raw - Get a pointer to the raw EDID data. 2492 * @drm_edid: drm_edid container 2493 * 2494 * Get a pointer to the raw EDID data. 2495 * 2496 * This is for transition only. Avoid using this like the plague. 2497 * 2498 * Return: Pointer to raw EDID data. 2499 */ 2500 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2501 { 2502 if (!drm_edid || !drm_edid->size) 2503 return NULL; 2504 2505 /* 2506 * Do not return pointers where relying on EDID extension count would 2507 * lead to buffer overflow. 2508 */ 2509 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2510 return NULL; 2511 2512 return drm_edid->edid; 2513 } 2514 EXPORT_SYMBOL(drm_edid_raw); 2515 2516 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2517 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2518 { 2519 struct drm_edid *drm_edid; 2520 2521 if (!edid || !size || size < EDID_LENGTH) 2522 return NULL; 2523 2524 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2525 if (drm_edid) { 2526 drm_edid->edid = edid; 2527 drm_edid->size = size; 2528 } 2529 2530 return drm_edid; 2531 } 2532 2533 /** 2534 * drm_edid_alloc - Allocate a new drm_edid container 2535 * @edid: Pointer to raw EDID data 2536 * @size: Size of memory allocated for EDID 2537 * 2538 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2539 * the actual size that has been allocated for the data. There is no validation 2540 * of the raw EDID data against the size, but at least the EDID base block must 2541 * fit in the buffer. 2542 * 2543 * The returned pointer must be freed using drm_edid_free(). 2544 * 2545 * Return: drm_edid container, or NULL on errors 2546 */ 2547 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2548 { 2549 const struct drm_edid *drm_edid; 2550 2551 if (!edid || !size || size < EDID_LENGTH) 2552 return NULL; 2553 2554 edid = kmemdup(edid, size, GFP_KERNEL); 2555 if (!edid) 2556 return NULL; 2557 2558 drm_edid = _drm_edid_alloc(edid, size); 2559 if (!drm_edid) 2560 kfree(edid); 2561 2562 return drm_edid; 2563 } 2564 EXPORT_SYMBOL(drm_edid_alloc); 2565 2566 /** 2567 * drm_edid_dup - Duplicate a drm_edid container 2568 * @drm_edid: EDID to duplicate 2569 * 2570 * The returned pointer must be freed using drm_edid_free(). 2571 * 2572 * Returns: drm_edid container copy, or NULL on errors 2573 */ 2574 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2575 { 2576 if (!drm_edid) 2577 return NULL; 2578 2579 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2580 } 2581 EXPORT_SYMBOL(drm_edid_dup); 2582 2583 /** 2584 * drm_edid_free - Free the drm_edid container 2585 * @drm_edid: EDID to free 2586 */ 2587 void drm_edid_free(const struct drm_edid *drm_edid) 2588 { 2589 if (!drm_edid) 2590 return; 2591 2592 kfree(drm_edid->edid); 2593 kfree(drm_edid); 2594 } 2595 EXPORT_SYMBOL(drm_edid_free); 2596 2597 /** 2598 * drm_probe_ddc() - probe DDC presence 2599 * @adapter: I2C adapter to probe 2600 * 2601 * Return: True on success, false on failure. 2602 */ 2603 bool 2604 drm_probe_ddc(struct i2c_adapter *adapter) 2605 { 2606 unsigned char out; 2607 2608 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2609 } 2610 EXPORT_SYMBOL(drm_probe_ddc); 2611 2612 /** 2613 * drm_get_edid - get EDID data, if available 2614 * @connector: connector we're probing 2615 * @adapter: I2C adapter to use for DDC 2616 * 2617 * Poke the given I2C channel to grab EDID data if possible. If found, 2618 * attach it to the connector. 2619 * 2620 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2621 */ 2622 struct edid *drm_get_edid(struct drm_connector *connector, 2623 struct i2c_adapter *adapter) 2624 { 2625 struct edid *edid; 2626 2627 if (connector->force == DRM_FORCE_OFF) 2628 return NULL; 2629 2630 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2631 return NULL; 2632 2633 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2634 drm_connector_update_edid_property(connector, edid); 2635 return edid; 2636 } 2637 EXPORT_SYMBOL(drm_get_edid); 2638 2639 /** 2640 * drm_edid_read_custom - Read EDID data using given EDID block read function 2641 * @connector: Connector to use 2642 * @read_block: EDID block read function 2643 * @context: Private data passed to the block read function 2644 * 2645 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2646 * exposes a different interface to read EDID blocks this function can be used 2647 * to get EDID data using a custom block read function. 2648 * 2649 * As in the general case the DDC bus is accessible by the kernel at the I2C 2650 * level, drivers must make all reasonable efforts to expose it as an I2C 2651 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2652 * this function. 2653 * 2654 * The EDID may be overridden using debugfs override_edid or firmware EDID 2655 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2656 * order. Having either of them bypasses actual EDID reads. 2657 * 2658 * The returned pointer must be freed using drm_edid_free(). 2659 * 2660 * Return: Pointer to EDID, or NULL if probe/read failed. 2661 */ 2662 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2663 read_block_fn read_block, 2664 void *context) 2665 { 2666 const struct drm_edid *drm_edid; 2667 struct edid *edid; 2668 size_t size = 0; 2669 2670 edid = _drm_do_get_edid(connector, read_block, context, &size); 2671 if (!edid) 2672 return NULL; 2673 2674 /* Sanity check for now */ 2675 drm_WARN_ON(connector->dev, !size); 2676 2677 drm_edid = _drm_edid_alloc(edid, size); 2678 if (!drm_edid) 2679 kfree(edid); 2680 2681 return drm_edid; 2682 } 2683 EXPORT_SYMBOL(drm_edid_read_custom); 2684 2685 /** 2686 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2687 * @connector: Connector to use 2688 * @adapter: I2C adapter to use for DDC 2689 * 2690 * Read EDID using the given I2C adapter. 2691 * 2692 * The EDID may be overridden using debugfs override_edid or firmware EDID 2693 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2694 * order. Having either of them bypasses actual EDID reads. 2695 * 2696 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2697 * using drm_edid_read() instead of this function. 2698 * 2699 * The returned pointer must be freed using drm_edid_free(). 2700 * 2701 * Return: Pointer to EDID, or NULL if probe/read failed. 2702 */ 2703 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2704 struct i2c_adapter *adapter) 2705 { 2706 const struct drm_edid *drm_edid; 2707 2708 if (connector->force == DRM_FORCE_OFF) 2709 return NULL; 2710 2711 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2712 return NULL; 2713 2714 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2715 2716 /* Note: Do *not* call connector updates here. */ 2717 2718 return drm_edid; 2719 } 2720 EXPORT_SYMBOL(drm_edid_read_ddc); 2721 2722 /** 2723 * drm_edid_read - Read EDID data using connector's I2C adapter 2724 * @connector: Connector to use 2725 * 2726 * Read EDID using the connector's I2C adapter. 2727 * 2728 * The EDID may be overridden using debugfs override_edid or firmware EDID 2729 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2730 * order. Having either of them bypasses actual EDID reads. 2731 * 2732 * The returned pointer must be freed using drm_edid_free(). 2733 * 2734 * Return: Pointer to EDID, or NULL if probe/read failed. 2735 */ 2736 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2737 { 2738 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2739 return NULL; 2740 2741 return drm_edid_read_ddc(connector, connector->ddc); 2742 } 2743 EXPORT_SYMBOL(drm_edid_read); 2744 2745 static u32 edid_extract_panel_id(const struct edid *edid) 2746 { 2747 /* 2748 * We represent the ID as a 32-bit number so it can easily be compared 2749 * with "==". 2750 * 2751 * NOTE that we deal with endianness differently for the top half 2752 * of this ID than for the bottom half. The bottom half (the product 2753 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2754 * that's how everyone seems to interpret it. The top half (the mfg_id) 2755 * gets stored as big endian because that makes 2756 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2757 * to write (it's easier to extract the ASCII). It doesn't really 2758 * matter, though, as long as the number here is unique. 2759 */ 2760 return (u32)edid->mfg_id[0] << 24 | 2761 (u32)edid->mfg_id[1] << 16 | 2762 (u32)EDID_PRODUCT_ID(edid); 2763 } 2764 2765 /** 2766 * drm_edid_get_panel_id - Get a panel's ID through DDC 2767 * @adapter: I2C adapter to use for DDC 2768 * 2769 * This function reads the first block of the EDID of a panel and (assuming 2770 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2771 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2772 * supposed to be different for each different modem of panel. 2773 * 2774 * This function is intended to be used during early probing on devices where 2775 * more than one panel might be present. Because of its intended use it must 2776 * assume that the EDID of the panel is correct, at least as far as the ID 2777 * is concerned (in other words, we don't process any overrides here). 2778 * 2779 * NOTE: it's expected that this function and drm_do_get_edid() will both 2780 * be read the EDID, but there is no caching between them. Since we're only 2781 * reading the first block, hopefully this extra overhead won't be too big. 2782 * 2783 * Return: A 32-bit ID that should be different for each make/model of panel. 2784 * See the functions drm_edid_encode_panel_id() and 2785 * drm_edid_decode_panel_id() for some details on the structure of this 2786 * ID. 2787 */ 2788 2789 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2790 { 2791 enum edid_block_status status; 2792 void *base_block; 2793 u32 panel_id = 0; 2794 2795 /* 2796 * There are no manufacturer IDs of 0, so if there is a problem reading 2797 * the EDID then we'll just return 0. 2798 */ 2799 2800 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); 2801 if (!base_block) 2802 return 0; 2803 2804 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2805 2806 edid_block_status_print(status, base_block, 0); 2807 2808 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2809 panel_id = edid_extract_panel_id(base_block); 2810 2811 kfree(base_block); 2812 2813 return panel_id; 2814 } 2815 EXPORT_SYMBOL(drm_edid_get_panel_id); 2816 2817 /** 2818 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2819 * @connector: connector we're probing 2820 * @adapter: I2C adapter to use for DDC 2821 * 2822 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2823 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2824 * switch DDC to the GPU which is retrieving EDID. 2825 * 2826 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2827 */ 2828 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2829 struct i2c_adapter *adapter) 2830 { 2831 struct drm_device *dev = connector->dev; 2832 struct pci_dev *pdev = to_pci_dev(dev->dev); 2833 struct edid *edid; 2834 2835 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2836 return NULL; 2837 2838 vga_switcheroo_lock_ddc(pdev); 2839 edid = drm_get_edid(connector, adapter); 2840 vga_switcheroo_unlock_ddc(pdev); 2841 2842 return edid; 2843 } 2844 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2845 2846 /** 2847 * drm_edid_duplicate - duplicate an EDID and the extensions 2848 * @edid: EDID to duplicate 2849 * 2850 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2851 */ 2852 struct edid *drm_edid_duplicate(const struct edid *edid) 2853 { 2854 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2855 } 2856 EXPORT_SYMBOL(drm_edid_duplicate); 2857 2858 /*** EDID parsing ***/ 2859 2860 /** 2861 * edid_get_quirks - return quirk flags for a given EDID 2862 * @drm_edid: EDID to process 2863 * 2864 * This tells subsequent routines what fixes they need to apply. 2865 */ 2866 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2867 { 2868 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2869 const struct edid_quirk *quirk; 2870 int i; 2871 2872 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2873 quirk = &edid_quirk_list[i]; 2874 if (quirk->panel_id == panel_id) 2875 return quirk->quirks; 2876 } 2877 2878 return 0; 2879 } 2880 2881 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2882 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2883 2884 /* 2885 * Walk the mode list for connector, clearing the preferred status on existing 2886 * modes and setting it anew for the right mode ala quirks. 2887 */ 2888 static void edid_fixup_preferred(struct drm_connector *connector, 2889 u32 quirks) 2890 { 2891 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2892 int target_refresh = 0; 2893 int cur_vrefresh, preferred_vrefresh; 2894 2895 if (list_empty(&connector->probed_modes)) 2896 return; 2897 2898 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2899 target_refresh = 60; 2900 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2901 target_refresh = 75; 2902 2903 preferred_mode = list_first_entry(&connector->probed_modes, 2904 struct drm_display_mode, head); 2905 2906 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2907 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2908 2909 if (cur_mode == preferred_mode) 2910 continue; 2911 2912 /* Largest mode is preferred */ 2913 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2914 preferred_mode = cur_mode; 2915 2916 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2917 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2918 /* At a given size, try to get closest to target refresh */ 2919 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2920 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2921 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2922 preferred_mode = cur_mode; 2923 } 2924 } 2925 2926 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2927 } 2928 2929 static bool 2930 mode_is_rb(const struct drm_display_mode *mode) 2931 { 2932 return (mode->htotal - mode->hdisplay == 160) && 2933 (mode->hsync_end - mode->hdisplay == 80) && 2934 (mode->hsync_end - mode->hsync_start == 32) && 2935 (mode->vsync_start - mode->vdisplay == 3); 2936 } 2937 2938 /* 2939 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2940 * @dev: Device to duplicate against 2941 * @hsize: Mode width 2942 * @vsize: Mode height 2943 * @fresh: Mode refresh rate 2944 * @rb: Mode reduced-blanking-ness 2945 * 2946 * Walk the DMT mode list looking for a match for the given parameters. 2947 * 2948 * Return: A newly allocated copy of the mode, or NULL if not found. 2949 */ 2950 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2951 int hsize, int vsize, int fresh, 2952 bool rb) 2953 { 2954 int i; 2955 2956 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2957 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2958 2959 if (hsize != ptr->hdisplay) 2960 continue; 2961 if (vsize != ptr->vdisplay) 2962 continue; 2963 if (fresh != drm_mode_vrefresh(ptr)) 2964 continue; 2965 if (rb != mode_is_rb(ptr)) 2966 continue; 2967 2968 return drm_mode_duplicate(dev, ptr); 2969 } 2970 2971 return NULL; 2972 } 2973 EXPORT_SYMBOL(drm_mode_find_dmt); 2974 2975 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2976 { 2977 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2978 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2979 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2980 2981 return descriptor->pixel_clock == 0 && 2982 descriptor->data.other_data.pad1 == 0 && 2983 descriptor->data.other_data.type == type; 2984 } 2985 2986 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2987 { 2988 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2989 2990 return descriptor->pixel_clock != 0; 2991 } 2992 2993 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2994 2995 static void 2996 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2997 { 2998 int i, n; 2999 u8 d = ext[0x02]; 3000 const u8 *det_base = ext + d; 3001 3002 if (d < 4 || d > 127) 3003 return; 3004 3005 n = (127 - d) / 18; 3006 for (i = 0; i < n; i++) 3007 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3008 } 3009 3010 static void 3011 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3012 { 3013 unsigned int i, n = min((int)ext[0x02], 6); 3014 const u8 *det_base = ext + 5; 3015 3016 if (ext[0x01] != 1) 3017 return; /* unknown version */ 3018 3019 for (i = 0; i < n; i++) 3020 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3021 } 3022 3023 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3024 detailed_cb *cb, void *closure) 3025 { 3026 struct drm_edid_iter edid_iter; 3027 const u8 *ext; 3028 int i; 3029 3030 if (!drm_edid) 3031 return; 3032 3033 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3034 cb(&drm_edid->edid->detailed_timings[i], closure); 3035 3036 drm_edid_iter_begin(drm_edid, &edid_iter); 3037 drm_edid_iter_for_each(ext, &edid_iter) { 3038 switch (*ext) { 3039 case CEA_EXT: 3040 cea_for_each_detailed_block(ext, cb, closure); 3041 break; 3042 case VTB_EXT: 3043 vtb_for_each_detailed_block(ext, cb, closure); 3044 break; 3045 default: 3046 break; 3047 } 3048 } 3049 drm_edid_iter_end(&edid_iter); 3050 } 3051 3052 static void 3053 is_rb(const struct detailed_timing *descriptor, void *data) 3054 { 3055 bool *res = data; 3056 3057 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3058 return; 3059 3060 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3062 3063 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3064 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3065 *res = true; 3066 } 3067 3068 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3069 static bool 3070 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3071 { 3072 if (drm_edid->edid->revision >= 4) { 3073 bool ret = false; 3074 3075 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3076 return ret; 3077 } 3078 3079 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3080 } 3081 3082 static void 3083 find_gtf2(const struct detailed_timing *descriptor, void *data) 3084 { 3085 const struct detailed_timing **res = data; 3086 3087 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3088 return; 3089 3090 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3091 3092 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3093 *res = descriptor; 3094 } 3095 3096 /* Secondary GTF curve kicks in above some break frequency */ 3097 static int 3098 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3099 { 3100 const struct detailed_timing *descriptor = NULL; 3101 3102 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3103 3104 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3105 3106 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3107 } 3108 3109 static int 3110 drm_gtf2_2c(const struct drm_edid *drm_edid) 3111 { 3112 const struct detailed_timing *descriptor = NULL; 3113 3114 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3115 3116 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3117 3118 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3119 } 3120 3121 static int 3122 drm_gtf2_m(const struct drm_edid *drm_edid) 3123 { 3124 const struct detailed_timing *descriptor = NULL; 3125 3126 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3127 3128 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3129 3130 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3131 } 3132 3133 static int 3134 drm_gtf2_k(const struct drm_edid *drm_edid) 3135 { 3136 const struct detailed_timing *descriptor = NULL; 3137 3138 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3139 3140 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3141 3142 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3143 } 3144 3145 static int 3146 drm_gtf2_2j(const struct drm_edid *drm_edid) 3147 { 3148 const struct detailed_timing *descriptor = NULL; 3149 3150 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3151 3152 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3153 3154 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3155 } 3156 3157 static void 3158 get_timing_level(const struct detailed_timing *descriptor, void *data) 3159 { 3160 int *res = data; 3161 3162 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3163 return; 3164 3165 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3166 3167 switch (descriptor->data.other_data.data.range.flags) { 3168 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3169 *res = LEVEL_GTF; 3170 break; 3171 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3172 *res = LEVEL_GTF2; 3173 break; 3174 case DRM_EDID_CVT_SUPPORT_FLAG: 3175 *res = LEVEL_CVT; 3176 break; 3177 default: 3178 break; 3179 } 3180 } 3181 3182 /* Get standard timing level (CVT/GTF/DMT). */ 3183 static int standard_timing_level(const struct drm_edid *drm_edid) 3184 { 3185 const struct edid *edid = drm_edid->edid; 3186 3187 if (edid->revision >= 4) { 3188 /* 3189 * If the range descriptor doesn't 3190 * indicate otherwise default to CVT 3191 */ 3192 int ret = LEVEL_CVT; 3193 3194 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3195 3196 return ret; 3197 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3198 return LEVEL_GTF2; 3199 } else if (edid->revision >= 2) { 3200 return LEVEL_GTF; 3201 } else { 3202 return LEVEL_DMT; 3203 } 3204 } 3205 3206 /* 3207 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3208 * monitors fill with ascii space (0x20) instead. 3209 */ 3210 static int 3211 bad_std_timing(u8 a, u8 b) 3212 { 3213 return (a == 0x00 && b == 0x00) || 3214 (a == 0x01 && b == 0x01) || 3215 (a == 0x20 && b == 0x20); 3216 } 3217 3218 static int drm_mode_hsync(const struct drm_display_mode *mode) 3219 { 3220 if (mode->htotal <= 0) 3221 return 0; 3222 3223 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3224 } 3225 3226 static struct drm_display_mode * 3227 drm_gtf2_mode(struct drm_device *dev, 3228 const struct drm_edid *drm_edid, 3229 int hsize, int vsize, int vrefresh_rate) 3230 { 3231 struct drm_display_mode *mode; 3232 3233 /* 3234 * This is potentially wrong if there's ever a monitor with 3235 * more than one ranges section, each claiming a different 3236 * secondary GTF curve. Please don't do that. 3237 */ 3238 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3239 if (!mode) 3240 return NULL; 3241 3242 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3243 drm_mode_destroy(dev, mode); 3244 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3245 vrefresh_rate, 0, 0, 3246 drm_gtf2_m(drm_edid), 3247 drm_gtf2_2c(drm_edid), 3248 drm_gtf2_k(drm_edid), 3249 drm_gtf2_2j(drm_edid)); 3250 } 3251 3252 return mode; 3253 } 3254 3255 /* 3256 * Take the standard timing params (in this case width, aspect, and refresh) 3257 * and convert them into a real mode using CVT/GTF/DMT. 3258 */ 3259 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3260 const struct drm_edid *drm_edid, 3261 const struct std_timing *t) 3262 { 3263 struct drm_device *dev = connector->dev; 3264 struct drm_display_mode *m, *mode = NULL; 3265 int hsize, vsize; 3266 int vrefresh_rate; 3267 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3268 >> EDID_TIMING_ASPECT_SHIFT; 3269 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3270 >> EDID_TIMING_VFREQ_SHIFT; 3271 int timing_level = standard_timing_level(drm_edid); 3272 3273 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3274 return NULL; 3275 3276 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3277 hsize = t->hsize * 8 + 248; 3278 /* vrefresh_rate = vfreq + 60 */ 3279 vrefresh_rate = vfreq + 60; 3280 /* the vdisplay is calculated based on the aspect ratio */ 3281 if (aspect_ratio == 0) { 3282 if (drm_edid->edid->revision < 3) 3283 vsize = hsize; 3284 else 3285 vsize = (hsize * 10) / 16; 3286 } else if (aspect_ratio == 1) 3287 vsize = (hsize * 3) / 4; 3288 else if (aspect_ratio == 2) 3289 vsize = (hsize * 4) / 5; 3290 else 3291 vsize = (hsize * 9) / 16; 3292 3293 /* HDTV hack, part 1 */ 3294 if (vrefresh_rate == 60 && 3295 ((hsize == 1360 && vsize == 765) || 3296 (hsize == 1368 && vsize == 769))) { 3297 hsize = 1366; 3298 vsize = 768; 3299 } 3300 3301 /* 3302 * If this connector already has a mode for this size and refresh 3303 * rate (because it came from detailed or CVT info), use that 3304 * instead. This way we don't have to guess at interlace or 3305 * reduced blanking. 3306 */ 3307 list_for_each_entry(m, &connector->probed_modes, head) 3308 if (m->hdisplay == hsize && m->vdisplay == vsize && 3309 drm_mode_vrefresh(m) == vrefresh_rate) 3310 return NULL; 3311 3312 /* HDTV hack, part 2 */ 3313 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3314 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3315 false); 3316 if (!mode) 3317 return NULL; 3318 mode->hdisplay = 1366; 3319 mode->hsync_start = mode->hsync_start - 1; 3320 mode->hsync_end = mode->hsync_end - 1; 3321 return mode; 3322 } 3323 3324 /* check whether it can be found in default mode table */ 3325 if (drm_monitor_supports_rb(drm_edid)) { 3326 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3327 true); 3328 if (mode) 3329 return mode; 3330 } 3331 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3332 if (mode) 3333 return mode; 3334 3335 /* okay, generate it */ 3336 switch (timing_level) { 3337 case LEVEL_DMT: 3338 break; 3339 case LEVEL_GTF: 3340 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3341 break; 3342 case LEVEL_GTF2: 3343 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3344 break; 3345 case LEVEL_CVT: 3346 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3347 false); 3348 break; 3349 } 3350 return mode; 3351 } 3352 3353 /* 3354 * EDID is delightfully ambiguous about how interlaced modes are to be 3355 * encoded. Our internal representation is of frame height, but some 3356 * HDTV detailed timings are encoded as field height. 3357 * 3358 * The format list here is from CEA, in frame size. Technically we 3359 * should be checking refresh rate too. Whatever. 3360 */ 3361 static void 3362 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3363 const struct detailed_pixel_timing *pt) 3364 { 3365 int i; 3366 static const struct { 3367 int w, h; 3368 } cea_interlaced[] = { 3369 { 1920, 1080 }, 3370 { 720, 480 }, 3371 { 1440, 480 }, 3372 { 2880, 480 }, 3373 { 720, 576 }, 3374 { 1440, 576 }, 3375 { 2880, 576 }, 3376 }; 3377 3378 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3379 return; 3380 3381 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3382 if ((mode->hdisplay == cea_interlaced[i].w) && 3383 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3384 mode->vdisplay *= 2; 3385 mode->vsync_start *= 2; 3386 mode->vsync_end *= 2; 3387 mode->vtotal *= 2; 3388 mode->vtotal |= 1; 3389 } 3390 } 3391 3392 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3393 } 3394 3395 /* 3396 * Create a new mode from an EDID detailed timing section. An EDID detailed 3397 * timing block contains enough info for us to create and return a new struct 3398 * drm_display_mode. 3399 */ 3400 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3401 const struct drm_edid *drm_edid, 3402 const struct detailed_timing *timing, 3403 u32 quirks) 3404 { 3405 struct drm_device *dev = connector->dev; 3406 struct drm_display_mode *mode; 3407 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3408 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3409 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3410 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3411 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3412 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3413 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3414 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3415 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3416 3417 /* ignore tiny modes */ 3418 if (hactive < 64 || vactive < 64) 3419 return NULL; 3420 3421 if (pt->misc & DRM_EDID_PT_STEREO) { 3422 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3423 connector->base.id, connector->name); 3424 return NULL; 3425 } 3426 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3427 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3428 connector->base.id, connector->name); 3429 } 3430 3431 /* it is incorrect if hsync/vsync width is zero */ 3432 if (!hsync_pulse_width || !vsync_pulse_width) { 3433 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3434 connector->base.id, connector->name); 3435 return NULL; 3436 } 3437 3438 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3439 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3440 if (!mode) 3441 return NULL; 3442 3443 goto set_size; 3444 } 3445 3446 mode = drm_mode_create(dev); 3447 if (!mode) 3448 return NULL; 3449 3450 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3451 mode->clock = 1088 * 10; 3452 else 3453 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3454 3455 mode->hdisplay = hactive; 3456 mode->hsync_start = mode->hdisplay + hsync_offset; 3457 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3458 mode->htotal = mode->hdisplay + hblank; 3459 3460 mode->vdisplay = vactive; 3461 mode->vsync_start = mode->vdisplay + vsync_offset; 3462 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3463 mode->vtotal = mode->vdisplay + vblank; 3464 3465 /* Some EDIDs have bogus h/vtotal values */ 3466 if (mode->hsync_end > mode->htotal) 3467 mode->htotal = mode->hsync_end + 1; 3468 if (mode->vsync_end > mode->vtotal) 3469 mode->vtotal = mode->vsync_end + 1; 3470 3471 drm_mode_do_interlace_quirk(mode, pt); 3472 3473 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3474 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3475 } else { 3476 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3477 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3478 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3479 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3480 } 3481 3482 set_size: 3483 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3484 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3485 3486 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 3487 mode->width_mm *= 10; 3488 mode->height_mm *= 10; 3489 } 3490 3491 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3492 mode->width_mm = drm_edid->edid->width_cm * 10; 3493 mode->height_mm = drm_edid->edid->height_cm * 10; 3494 } 3495 3496 mode->type = DRM_MODE_TYPE_DRIVER; 3497 drm_mode_set_name(mode); 3498 3499 return mode; 3500 } 3501 3502 static bool 3503 mode_in_hsync_range(const struct drm_display_mode *mode, 3504 const struct edid *edid, const u8 *t) 3505 { 3506 int hsync, hmin, hmax; 3507 3508 hmin = t[7]; 3509 if (edid->revision >= 4) 3510 hmin += ((t[4] & 0x04) ? 255 : 0); 3511 hmax = t[8]; 3512 if (edid->revision >= 4) 3513 hmax += ((t[4] & 0x08) ? 255 : 0); 3514 hsync = drm_mode_hsync(mode); 3515 3516 return (hsync <= hmax && hsync >= hmin); 3517 } 3518 3519 static bool 3520 mode_in_vsync_range(const struct drm_display_mode *mode, 3521 const struct edid *edid, const u8 *t) 3522 { 3523 int vsync, vmin, vmax; 3524 3525 vmin = t[5]; 3526 if (edid->revision >= 4) 3527 vmin += ((t[4] & 0x01) ? 255 : 0); 3528 vmax = t[6]; 3529 if (edid->revision >= 4) 3530 vmax += ((t[4] & 0x02) ? 255 : 0); 3531 vsync = drm_mode_vrefresh(mode); 3532 3533 return (vsync <= vmax && vsync >= vmin); 3534 } 3535 3536 static u32 3537 range_pixel_clock(const struct edid *edid, const u8 *t) 3538 { 3539 /* unspecified */ 3540 if (t[9] == 0 || t[9] == 255) 3541 return 0; 3542 3543 /* 1.4 with CVT support gives us real precision, yay */ 3544 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3545 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3546 3547 /* 1.3 is pathetic, so fuzz up a bit */ 3548 return t[9] * 10000 + 5001; 3549 } 3550 3551 static bool mode_in_range(const struct drm_display_mode *mode, 3552 const struct drm_edid *drm_edid, 3553 const struct detailed_timing *timing) 3554 { 3555 const struct edid *edid = drm_edid->edid; 3556 u32 max_clock; 3557 const u8 *t = (const u8 *)timing; 3558 3559 if (!mode_in_hsync_range(mode, edid, t)) 3560 return false; 3561 3562 if (!mode_in_vsync_range(mode, edid, t)) 3563 return false; 3564 3565 if ((max_clock = range_pixel_clock(edid, t))) 3566 if (mode->clock > max_clock) 3567 return false; 3568 3569 /* 1.4 max horizontal check */ 3570 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3571 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3572 return false; 3573 3574 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3575 return false; 3576 3577 return true; 3578 } 3579 3580 static bool valid_inferred_mode(const struct drm_connector *connector, 3581 const struct drm_display_mode *mode) 3582 { 3583 const struct drm_display_mode *m; 3584 bool ok = false; 3585 3586 list_for_each_entry(m, &connector->probed_modes, head) { 3587 if (mode->hdisplay == m->hdisplay && 3588 mode->vdisplay == m->vdisplay && 3589 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3590 return false; /* duplicated */ 3591 if (mode->hdisplay <= m->hdisplay && 3592 mode->vdisplay <= m->vdisplay) 3593 ok = true; 3594 } 3595 return ok; 3596 } 3597 3598 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3599 const struct drm_edid *drm_edid, 3600 const struct detailed_timing *timing) 3601 { 3602 int i, modes = 0; 3603 struct drm_display_mode *newmode; 3604 struct drm_device *dev = connector->dev; 3605 3606 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3607 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3608 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3609 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3610 if (newmode) { 3611 drm_mode_probed_add(connector, newmode); 3612 modes++; 3613 } 3614 } 3615 } 3616 3617 return modes; 3618 } 3619 3620 /* fix up 1366x768 mode from 1368x768; 3621 * GFT/CVT can't express 1366 width which isn't dividable by 8 3622 */ 3623 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3624 { 3625 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3626 mode->hdisplay = 1366; 3627 mode->hsync_start--; 3628 mode->hsync_end--; 3629 drm_mode_set_name(mode); 3630 } 3631 } 3632 3633 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3634 const struct drm_edid *drm_edid, 3635 const struct detailed_timing *timing) 3636 { 3637 int i, modes = 0; 3638 struct drm_display_mode *newmode; 3639 struct drm_device *dev = connector->dev; 3640 3641 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3642 const struct minimode *m = &extra_modes[i]; 3643 3644 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3645 if (!newmode) 3646 return modes; 3647 3648 drm_mode_fixup_1366x768(newmode); 3649 if (!mode_in_range(newmode, drm_edid, timing) || 3650 !valid_inferred_mode(connector, newmode)) { 3651 drm_mode_destroy(dev, newmode); 3652 continue; 3653 } 3654 3655 drm_mode_probed_add(connector, newmode); 3656 modes++; 3657 } 3658 3659 return modes; 3660 } 3661 3662 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3663 const struct drm_edid *drm_edid, 3664 const struct detailed_timing *timing) 3665 { 3666 int i, modes = 0; 3667 struct drm_display_mode *newmode; 3668 struct drm_device *dev = connector->dev; 3669 3670 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3671 const struct minimode *m = &extra_modes[i]; 3672 3673 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3674 if (!newmode) 3675 return modes; 3676 3677 drm_mode_fixup_1366x768(newmode); 3678 if (!mode_in_range(newmode, drm_edid, timing) || 3679 !valid_inferred_mode(connector, newmode)) { 3680 drm_mode_destroy(dev, newmode); 3681 continue; 3682 } 3683 3684 drm_mode_probed_add(connector, newmode); 3685 modes++; 3686 } 3687 3688 return modes; 3689 } 3690 3691 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3692 const struct drm_edid *drm_edid, 3693 const struct detailed_timing *timing) 3694 { 3695 int i, modes = 0; 3696 struct drm_display_mode *newmode; 3697 struct drm_device *dev = connector->dev; 3698 bool rb = drm_monitor_supports_rb(drm_edid); 3699 3700 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3701 const struct minimode *m = &extra_modes[i]; 3702 3703 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3704 if (!newmode) 3705 return modes; 3706 3707 drm_mode_fixup_1366x768(newmode); 3708 if (!mode_in_range(newmode, drm_edid, timing) || 3709 !valid_inferred_mode(connector, newmode)) { 3710 drm_mode_destroy(dev, newmode); 3711 continue; 3712 } 3713 3714 drm_mode_probed_add(connector, newmode); 3715 modes++; 3716 } 3717 3718 return modes; 3719 } 3720 3721 static void 3722 do_inferred_modes(const struct detailed_timing *timing, void *c) 3723 { 3724 struct detailed_mode_closure *closure = c; 3725 const struct detailed_non_pixel *data = &timing->data.other_data; 3726 const struct detailed_data_monitor_range *range = &data->data.range; 3727 3728 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3729 return; 3730 3731 closure->modes += drm_dmt_modes_for_range(closure->connector, 3732 closure->drm_edid, 3733 timing); 3734 3735 if (closure->drm_edid->edid->revision < 2) 3736 return; /* GTF not defined yet */ 3737 3738 switch (range->flags) { 3739 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3740 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3741 closure->drm_edid, 3742 timing); 3743 break; 3744 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3745 closure->modes += drm_gtf_modes_for_range(closure->connector, 3746 closure->drm_edid, 3747 timing); 3748 break; 3749 case DRM_EDID_CVT_SUPPORT_FLAG: 3750 if (closure->drm_edid->edid->revision < 4) 3751 break; 3752 3753 closure->modes += drm_cvt_modes_for_range(closure->connector, 3754 closure->drm_edid, 3755 timing); 3756 break; 3757 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3758 default: 3759 break; 3760 } 3761 } 3762 3763 static int add_inferred_modes(struct drm_connector *connector, 3764 const struct drm_edid *drm_edid) 3765 { 3766 struct detailed_mode_closure closure = { 3767 .connector = connector, 3768 .drm_edid = drm_edid, 3769 }; 3770 3771 if (drm_edid->edid->revision >= 1) 3772 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3773 3774 return closure.modes; 3775 } 3776 3777 static int 3778 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3779 { 3780 int i, j, m, modes = 0; 3781 struct drm_display_mode *mode; 3782 const u8 *est = ((const u8 *)timing) + 6; 3783 3784 for (i = 0; i < 6; i++) { 3785 for (j = 7; j >= 0; j--) { 3786 m = (i * 8) + (7 - j); 3787 if (m >= ARRAY_SIZE(est3_modes)) 3788 break; 3789 if (est[i] & (1 << j)) { 3790 mode = drm_mode_find_dmt(connector->dev, 3791 est3_modes[m].w, 3792 est3_modes[m].h, 3793 est3_modes[m].r, 3794 est3_modes[m].rb); 3795 if (mode) { 3796 drm_mode_probed_add(connector, mode); 3797 modes++; 3798 } 3799 } 3800 } 3801 } 3802 3803 return modes; 3804 } 3805 3806 static void 3807 do_established_modes(const struct detailed_timing *timing, void *c) 3808 { 3809 struct detailed_mode_closure *closure = c; 3810 3811 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3812 return; 3813 3814 closure->modes += drm_est3_modes(closure->connector, timing); 3815 } 3816 3817 /* 3818 * Get established modes from EDID and add them. Each EDID block contains a 3819 * bitmap of the supported "established modes" list (defined above). Tease them 3820 * out and add them to the global modes list. 3821 */ 3822 static int add_established_modes(struct drm_connector *connector, 3823 const struct drm_edid *drm_edid) 3824 { 3825 struct drm_device *dev = connector->dev; 3826 const struct edid *edid = drm_edid->edid; 3827 unsigned long est_bits = edid->established_timings.t1 | 3828 (edid->established_timings.t2 << 8) | 3829 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3830 int i, modes = 0; 3831 struct detailed_mode_closure closure = { 3832 .connector = connector, 3833 .drm_edid = drm_edid, 3834 }; 3835 3836 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3837 if (est_bits & (1<<i)) { 3838 struct drm_display_mode *newmode; 3839 3840 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3841 if (newmode) { 3842 drm_mode_probed_add(connector, newmode); 3843 modes++; 3844 } 3845 } 3846 } 3847 3848 if (edid->revision >= 1) 3849 drm_for_each_detailed_block(drm_edid, do_established_modes, 3850 &closure); 3851 3852 return modes + closure.modes; 3853 } 3854 3855 static void 3856 do_standard_modes(const struct detailed_timing *timing, void *c) 3857 { 3858 struct detailed_mode_closure *closure = c; 3859 const struct detailed_non_pixel *data = &timing->data.other_data; 3860 struct drm_connector *connector = closure->connector; 3861 int i; 3862 3863 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3864 return; 3865 3866 for (i = 0; i < 6; i++) { 3867 const struct std_timing *std = &data->data.timings[i]; 3868 struct drm_display_mode *newmode; 3869 3870 newmode = drm_mode_std(connector, closure->drm_edid, std); 3871 if (newmode) { 3872 drm_mode_probed_add(connector, newmode); 3873 closure->modes++; 3874 } 3875 } 3876 } 3877 3878 /* 3879 * Get standard modes from EDID and add them. Standard modes can be calculated 3880 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3881 * add them to the list. 3882 */ 3883 static int add_standard_modes(struct drm_connector *connector, 3884 const struct drm_edid *drm_edid) 3885 { 3886 int i, modes = 0; 3887 struct detailed_mode_closure closure = { 3888 .connector = connector, 3889 .drm_edid = drm_edid, 3890 }; 3891 3892 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3893 struct drm_display_mode *newmode; 3894 3895 newmode = drm_mode_std(connector, drm_edid, 3896 &drm_edid->edid->standard_timings[i]); 3897 if (newmode) { 3898 drm_mode_probed_add(connector, newmode); 3899 modes++; 3900 } 3901 } 3902 3903 if (drm_edid->edid->revision >= 1) 3904 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3905 &closure); 3906 3907 /* XXX should also look for standard codes in VTB blocks */ 3908 3909 return modes + closure.modes; 3910 } 3911 3912 static int drm_cvt_modes(struct drm_connector *connector, 3913 const struct detailed_timing *timing) 3914 { 3915 int i, j, modes = 0; 3916 struct drm_display_mode *newmode; 3917 struct drm_device *dev = connector->dev; 3918 const struct cvt_timing *cvt; 3919 const int rates[] = { 60, 85, 75, 60, 50 }; 3920 const u8 empty[3] = { 0, 0, 0 }; 3921 3922 for (i = 0; i < 4; i++) { 3923 int width, height; 3924 3925 cvt = &(timing->data.other_data.data.cvt[i]); 3926 3927 if (!memcmp(cvt->code, empty, 3)) 3928 continue; 3929 3930 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3931 switch (cvt->code[1] & 0x0c) { 3932 /* default - because compiler doesn't see that we've enumerated all cases */ 3933 default: 3934 case 0x00: 3935 width = height * 4 / 3; 3936 break; 3937 case 0x04: 3938 width = height * 16 / 9; 3939 break; 3940 case 0x08: 3941 width = height * 16 / 10; 3942 break; 3943 case 0x0c: 3944 width = height * 15 / 9; 3945 break; 3946 } 3947 3948 for (j = 1; j < 5; j++) { 3949 if (cvt->code[2] & (1 << j)) { 3950 newmode = drm_cvt_mode(dev, width, height, 3951 rates[j], j == 0, 3952 false, false); 3953 if (newmode) { 3954 drm_mode_probed_add(connector, newmode); 3955 modes++; 3956 } 3957 } 3958 } 3959 } 3960 3961 return modes; 3962 } 3963 3964 static void 3965 do_cvt_mode(const struct detailed_timing *timing, void *c) 3966 { 3967 struct detailed_mode_closure *closure = c; 3968 3969 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3970 return; 3971 3972 closure->modes += drm_cvt_modes(closure->connector, timing); 3973 } 3974 3975 static int 3976 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 3977 { 3978 struct detailed_mode_closure closure = { 3979 .connector = connector, 3980 .drm_edid = drm_edid, 3981 }; 3982 3983 if (drm_edid->edid->revision >= 3) 3984 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 3985 3986 /* XXX should also look for CVT codes in VTB blocks */ 3987 3988 return closure.modes; 3989 } 3990 3991 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 3992 struct drm_display_mode *mode); 3993 3994 static void 3995 do_detailed_mode(const struct detailed_timing *timing, void *c) 3996 { 3997 struct detailed_mode_closure *closure = c; 3998 struct drm_display_mode *newmode; 3999 4000 if (!is_detailed_timing_descriptor(timing)) 4001 return; 4002 4003 newmode = drm_mode_detailed(closure->connector, 4004 closure->drm_edid, timing, 4005 closure->quirks); 4006 if (!newmode) 4007 return; 4008 4009 if (closure->preferred) 4010 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4011 4012 /* 4013 * Detailed modes are limited to 10kHz pixel clock resolution, 4014 * so fix up anything that looks like CEA/HDMI mode, but the clock 4015 * is just slightly off. 4016 */ 4017 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4018 4019 drm_mode_probed_add(closure->connector, newmode); 4020 closure->modes++; 4021 closure->preferred = false; 4022 } 4023 4024 /* 4025 * add_detailed_modes - Add modes from detailed timings 4026 * @connector: attached connector 4027 * @drm_edid: EDID block to scan 4028 * @quirks: quirks to apply 4029 */ 4030 static int add_detailed_modes(struct drm_connector *connector, 4031 const struct drm_edid *drm_edid, u32 quirks) 4032 { 4033 struct detailed_mode_closure closure = { 4034 .connector = connector, 4035 .drm_edid = drm_edid, 4036 .quirks = quirks, 4037 }; 4038 4039 if (drm_edid->edid->revision >= 4) 4040 closure.preferred = true; /* first detailed timing is always preferred */ 4041 else 4042 closure.preferred = 4043 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4044 4045 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4046 4047 return closure.modes; 4048 } 4049 4050 /* CTA-861-H Table 60 - CTA Tag Codes */ 4051 #define CTA_DB_AUDIO 1 4052 #define CTA_DB_VIDEO 2 4053 #define CTA_DB_VENDOR 3 4054 #define CTA_DB_SPEAKER 4 4055 #define CTA_DB_EXTENDED_TAG 7 4056 4057 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4058 #define CTA_EXT_DB_VIDEO_CAP 0 4059 #define CTA_EXT_DB_VENDOR 1 4060 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4061 #define CTA_EXT_DB_420_VIDEO_DATA 14 4062 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4063 #define CTA_EXT_DB_HF_EEODB 0x78 4064 #define CTA_EXT_DB_HF_SCDB 0x79 4065 4066 #define EDID_BASIC_AUDIO (1 << 6) 4067 #define EDID_CEA_YCRCB444 (1 << 5) 4068 #define EDID_CEA_YCRCB422 (1 << 4) 4069 #define EDID_CEA_VCDB_QS (1 << 6) 4070 4071 /* 4072 * Search EDID for CEA extension block. 4073 * 4074 * FIXME: Prefer not returning pointers to raw EDID data. 4075 */ 4076 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4077 int ext_id, int *ext_index) 4078 { 4079 const u8 *edid_ext = NULL; 4080 int i; 4081 4082 /* No EDID or EDID extensions */ 4083 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4084 return NULL; 4085 4086 /* Find CEA extension */ 4087 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4088 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4089 if (edid_block_tag(edid_ext) == ext_id) 4090 break; 4091 } 4092 4093 if (i >= drm_edid_extension_block_count(drm_edid)) 4094 return NULL; 4095 4096 *ext_index = i + 1; 4097 4098 return edid_ext; 4099 } 4100 4101 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4102 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4103 { 4104 const struct displayid_block *block; 4105 struct displayid_iter iter; 4106 int ext_index = 0; 4107 bool found = false; 4108 4109 /* Look for a top level CEA extension block */ 4110 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4111 return true; 4112 4113 /* CEA blocks can also be found embedded in a DisplayID block */ 4114 displayid_iter_edid_begin(drm_edid, &iter); 4115 displayid_iter_for_each(block, &iter) { 4116 if (block->tag == DATA_BLOCK_CTA) { 4117 found = true; 4118 break; 4119 } 4120 } 4121 displayid_iter_end(&iter); 4122 4123 return found; 4124 } 4125 4126 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4127 { 4128 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4129 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4130 4131 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4132 return &edid_cea_modes_1[vic - 1]; 4133 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4134 return &edid_cea_modes_193[vic - 193]; 4135 return NULL; 4136 } 4137 4138 static u8 cea_num_vics(void) 4139 { 4140 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4141 } 4142 4143 static u8 cea_next_vic(u8 vic) 4144 { 4145 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4146 vic = 193; 4147 return vic; 4148 } 4149 4150 /* 4151 * Calculate the alternate clock for the CEA mode 4152 * (60Hz vs. 59.94Hz etc.) 4153 */ 4154 static unsigned int 4155 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4156 { 4157 unsigned int clock = cea_mode->clock; 4158 4159 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4160 return clock; 4161 4162 /* 4163 * edid_cea_modes contains the 59.94Hz 4164 * variant for 240 and 480 line modes, 4165 * and the 60Hz variant otherwise. 4166 */ 4167 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4168 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4169 else 4170 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4171 4172 return clock; 4173 } 4174 4175 static bool 4176 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4177 { 4178 /* 4179 * For certain VICs the spec allows the vertical 4180 * front porch to vary by one or two lines. 4181 * 4182 * cea_modes[] stores the variant with the shortest 4183 * vertical front porch. We can adjust the mode to 4184 * get the other variants by simply increasing the 4185 * vertical front porch length. 4186 */ 4187 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4188 cea_mode_for_vic(9)->vtotal != 262 || 4189 cea_mode_for_vic(12)->vtotal != 262 || 4190 cea_mode_for_vic(13)->vtotal != 262 || 4191 cea_mode_for_vic(23)->vtotal != 312 || 4192 cea_mode_for_vic(24)->vtotal != 312 || 4193 cea_mode_for_vic(27)->vtotal != 312 || 4194 cea_mode_for_vic(28)->vtotal != 312); 4195 4196 if (((vic == 8 || vic == 9 || 4197 vic == 12 || vic == 13) && mode->vtotal < 263) || 4198 ((vic == 23 || vic == 24 || 4199 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4200 mode->vsync_start++; 4201 mode->vsync_end++; 4202 mode->vtotal++; 4203 4204 return true; 4205 } 4206 4207 return false; 4208 } 4209 4210 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4211 unsigned int clock_tolerance) 4212 { 4213 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4214 u8 vic; 4215 4216 if (!to_match->clock) 4217 return 0; 4218 4219 if (to_match->picture_aspect_ratio) 4220 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4221 4222 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4223 struct drm_display_mode cea_mode; 4224 unsigned int clock1, clock2; 4225 4226 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4227 4228 /* Check both 60Hz and 59.94Hz */ 4229 clock1 = cea_mode.clock; 4230 clock2 = cea_mode_alternate_clock(&cea_mode); 4231 4232 if (abs(to_match->clock - clock1) > clock_tolerance && 4233 abs(to_match->clock - clock2) > clock_tolerance) 4234 continue; 4235 4236 do { 4237 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4238 return vic; 4239 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4240 } 4241 4242 return 0; 4243 } 4244 4245 /** 4246 * drm_match_cea_mode - look for a CEA mode matching given mode 4247 * @to_match: display mode 4248 * 4249 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4250 * mode. 4251 */ 4252 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4253 { 4254 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4255 u8 vic; 4256 4257 if (!to_match->clock) 4258 return 0; 4259 4260 if (to_match->picture_aspect_ratio) 4261 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4262 4263 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4264 struct drm_display_mode cea_mode; 4265 unsigned int clock1, clock2; 4266 4267 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4268 4269 /* Check both 60Hz and 59.94Hz */ 4270 clock1 = cea_mode.clock; 4271 clock2 = cea_mode_alternate_clock(&cea_mode); 4272 4273 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4274 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4275 continue; 4276 4277 do { 4278 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4279 return vic; 4280 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4281 } 4282 4283 return 0; 4284 } 4285 EXPORT_SYMBOL(drm_match_cea_mode); 4286 4287 static bool drm_valid_cea_vic(u8 vic) 4288 { 4289 return cea_mode_for_vic(vic) != NULL; 4290 } 4291 4292 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4293 { 4294 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4295 4296 if (mode) 4297 return mode->picture_aspect_ratio; 4298 4299 return HDMI_PICTURE_ASPECT_NONE; 4300 } 4301 4302 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4303 { 4304 return edid_4k_modes[video_code].picture_aspect_ratio; 4305 } 4306 4307 /* 4308 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4309 * specific block). 4310 */ 4311 static unsigned int 4312 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4313 { 4314 return cea_mode_alternate_clock(hdmi_mode); 4315 } 4316 4317 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4318 unsigned int clock_tolerance) 4319 { 4320 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4321 u8 vic; 4322 4323 if (!to_match->clock) 4324 return 0; 4325 4326 if (to_match->picture_aspect_ratio) 4327 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4328 4329 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4330 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4331 unsigned int clock1, clock2; 4332 4333 /* Make sure to also match alternate clocks */ 4334 clock1 = hdmi_mode->clock; 4335 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4336 4337 if (abs(to_match->clock - clock1) > clock_tolerance && 4338 abs(to_match->clock - clock2) > clock_tolerance) 4339 continue; 4340 4341 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4342 return vic; 4343 } 4344 4345 return 0; 4346 } 4347 4348 /* 4349 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4350 * @to_match: display mode 4351 * 4352 * An HDMI mode is one defined in the HDMI vendor specific block. 4353 * 4354 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4355 */ 4356 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4357 { 4358 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4359 u8 vic; 4360 4361 if (!to_match->clock) 4362 return 0; 4363 4364 if (to_match->picture_aspect_ratio) 4365 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4366 4367 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4368 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4369 unsigned int clock1, clock2; 4370 4371 /* Make sure to also match alternate clocks */ 4372 clock1 = hdmi_mode->clock; 4373 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4374 4375 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4376 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4377 drm_mode_match(to_match, hdmi_mode, match_flags)) 4378 return vic; 4379 } 4380 return 0; 4381 } 4382 4383 static bool drm_valid_hdmi_vic(u8 vic) 4384 { 4385 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4386 } 4387 4388 static int add_alternate_cea_modes(struct drm_connector *connector, 4389 const struct drm_edid *drm_edid) 4390 { 4391 struct drm_device *dev = connector->dev; 4392 struct drm_display_mode *mode, *tmp; 4393 LIST_HEAD(list); 4394 int modes = 0; 4395 4396 /* Don't add CTA modes if the CTA extension block is missing */ 4397 if (!drm_edid_has_cta_extension(drm_edid)) 4398 return 0; 4399 4400 /* 4401 * Go through all probed modes and create a new mode 4402 * with the alternate clock for certain CEA modes. 4403 */ 4404 list_for_each_entry(mode, &connector->probed_modes, head) { 4405 const struct drm_display_mode *cea_mode = NULL; 4406 struct drm_display_mode *newmode; 4407 u8 vic = drm_match_cea_mode(mode); 4408 unsigned int clock1, clock2; 4409 4410 if (drm_valid_cea_vic(vic)) { 4411 cea_mode = cea_mode_for_vic(vic); 4412 clock2 = cea_mode_alternate_clock(cea_mode); 4413 } else { 4414 vic = drm_match_hdmi_mode(mode); 4415 if (drm_valid_hdmi_vic(vic)) { 4416 cea_mode = &edid_4k_modes[vic]; 4417 clock2 = hdmi_mode_alternate_clock(cea_mode); 4418 } 4419 } 4420 4421 if (!cea_mode) 4422 continue; 4423 4424 clock1 = cea_mode->clock; 4425 4426 if (clock1 == clock2) 4427 continue; 4428 4429 if (mode->clock != clock1 && mode->clock != clock2) 4430 continue; 4431 4432 newmode = drm_mode_duplicate(dev, cea_mode); 4433 if (!newmode) 4434 continue; 4435 4436 /* Carry over the stereo flags */ 4437 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4438 4439 /* 4440 * The current mode could be either variant. Make 4441 * sure to pick the "other" clock for the new mode. 4442 */ 4443 if (mode->clock != clock1) 4444 newmode->clock = clock1; 4445 else 4446 newmode->clock = clock2; 4447 4448 list_add_tail(&newmode->head, &list); 4449 } 4450 4451 list_for_each_entry_safe(mode, tmp, &list, head) { 4452 list_del(&mode->head); 4453 drm_mode_probed_add(connector, mode); 4454 modes++; 4455 } 4456 4457 return modes; 4458 } 4459 4460 static u8 svd_to_vic(u8 svd) 4461 { 4462 /* 0-6 bit vic, 7th bit native mode indicator */ 4463 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4464 return svd & 127; 4465 4466 return svd; 4467 } 4468 4469 static struct drm_display_mode * 4470 drm_display_mode_from_vic_index(struct drm_connector *connector, 4471 const u8 *video_db, u8 video_len, 4472 u8 video_index) 4473 { 4474 struct drm_device *dev = connector->dev; 4475 struct drm_display_mode *newmode; 4476 u8 vic; 4477 4478 if (video_db == NULL || video_index >= video_len) 4479 return NULL; 4480 4481 /* CEA modes are numbered 1..127 */ 4482 vic = svd_to_vic(video_db[video_index]); 4483 if (!drm_valid_cea_vic(vic)) 4484 return NULL; 4485 4486 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4487 if (!newmode) 4488 return NULL; 4489 4490 return newmode; 4491 } 4492 4493 /* 4494 * do_y420vdb_modes - Parse YCBCR 420 only modes 4495 * @connector: connector corresponding to the HDMI sink 4496 * @svds: start of the data block of CEA YCBCR 420 VDB 4497 * @len: length of the CEA YCBCR 420 VDB 4498 * 4499 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4500 * which contains modes which can be supported in YCBCR 420 4501 * output format only. 4502 */ 4503 static int do_y420vdb_modes(struct drm_connector *connector, 4504 const u8 *svds, u8 svds_len) 4505 { 4506 int modes = 0, i; 4507 struct drm_device *dev = connector->dev; 4508 struct drm_display_info *info = &connector->display_info; 4509 struct drm_hdmi_info *hdmi = &info->hdmi; 4510 4511 for (i = 0; i < svds_len; i++) { 4512 u8 vic = svd_to_vic(svds[i]); 4513 struct drm_display_mode *newmode; 4514 4515 if (!drm_valid_cea_vic(vic)) 4516 continue; 4517 4518 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4519 if (!newmode) 4520 break; 4521 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 4522 drm_mode_probed_add(connector, newmode); 4523 modes++; 4524 } 4525 4526 if (modes > 0) 4527 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4528 return modes; 4529 } 4530 4531 /* 4532 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 4533 * @connector: connector corresponding to the HDMI sink 4534 * @vic: CEA vic for the video mode to be added in the map 4535 * 4536 * Makes an entry for a videomode in the YCBCR 420 bitmap 4537 */ 4538 static void 4539 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 4540 { 4541 u8 vic = svd_to_vic(svd); 4542 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4543 4544 if (!drm_valid_cea_vic(vic)) 4545 return; 4546 4547 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 4548 } 4549 4550 /** 4551 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4552 * @dev: DRM device 4553 * @video_code: CEA VIC of the mode 4554 * 4555 * Creates a new mode matching the specified CEA VIC. 4556 * 4557 * Returns: A new drm_display_mode on success or NULL on failure 4558 */ 4559 struct drm_display_mode * 4560 drm_display_mode_from_cea_vic(struct drm_device *dev, 4561 u8 video_code) 4562 { 4563 const struct drm_display_mode *cea_mode; 4564 struct drm_display_mode *newmode; 4565 4566 cea_mode = cea_mode_for_vic(video_code); 4567 if (!cea_mode) 4568 return NULL; 4569 4570 newmode = drm_mode_duplicate(dev, cea_mode); 4571 if (!newmode) 4572 return NULL; 4573 4574 return newmode; 4575 } 4576 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4577 4578 static int 4579 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 4580 { 4581 int i, modes = 0; 4582 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4583 4584 for (i = 0; i < len; i++) { 4585 struct drm_display_mode *mode; 4586 4587 mode = drm_display_mode_from_vic_index(connector, db, len, i); 4588 if (mode) { 4589 /* 4590 * YCBCR420 capability block contains a bitmap which 4591 * gives the index of CEA modes from CEA VDB, which 4592 * can support YCBCR 420 sampling output also (apart 4593 * from RGB/YCBCR444 etc). 4594 * For example, if the bit 0 in bitmap is set, 4595 * first mode in VDB can support YCBCR420 output too. 4596 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 4597 */ 4598 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 4599 drm_add_cmdb_modes(connector, db[i]); 4600 4601 drm_mode_probed_add(connector, mode); 4602 modes++; 4603 } 4604 } 4605 4606 return modes; 4607 } 4608 4609 struct stereo_mandatory_mode { 4610 int width, height, vrefresh; 4611 unsigned int flags; 4612 }; 4613 4614 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4615 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4616 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4617 { 1920, 1080, 50, 4618 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4619 { 1920, 1080, 60, 4620 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4621 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4622 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4623 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4624 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4625 }; 4626 4627 static bool 4628 stereo_match_mandatory(const struct drm_display_mode *mode, 4629 const struct stereo_mandatory_mode *stereo_mode) 4630 { 4631 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4632 4633 return mode->hdisplay == stereo_mode->width && 4634 mode->vdisplay == stereo_mode->height && 4635 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4636 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4637 } 4638 4639 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4640 { 4641 struct drm_device *dev = connector->dev; 4642 const struct drm_display_mode *mode; 4643 struct list_head stereo_modes; 4644 int modes = 0, i; 4645 4646 INIT_LIST_HEAD(&stereo_modes); 4647 4648 list_for_each_entry(mode, &connector->probed_modes, head) { 4649 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4650 const struct stereo_mandatory_mode *mandatory; 4651 struct drm_display_mode *new_mode; 4652 4653 if (!stereo_match_mandatory(mode, 4654 &stereo_mandatory_modes[i])) 4655 continue; 4656 4657 mandatory = &stereo_mandatory_modes[i]; 4658 new_mode = drm_mode_duplicate(dev, mode); 4659 if (!new_mode) 4660 continue; 4661 4662 new_mode->flags |= mandatory->flags; 4663 list_add_tail(&new_mode->head, &stereo_modes); 4664 modes++; 4665 } 4666 } 4667 4668 list_splice_tail(&stereo_modes, &connector->probed_modes); 4669 4670 return modes; 4671 } 4672 4673 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4674 { 4675 struct drm_device *dev = connector->dev; 4676 struct drm_display_mode *newmode; 4677 4678 if (!drm_valid_hdmi_vic(vic)) { 4679 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4680 connector->base.id, connector->name, vic); 4681 return 0; 4682 } 4683 4684 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4685 if (!newmode) 4686 return 0; 4687 4688 drm_mode_probed_add(connector, newmode); 4689 4690 return 1; 4691 } 4692 4693 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4694 const u8 *video_db, u8 video_len, u8 video_index) 4695 { 4696 struct drm_display_mode *newmode; 4697 int modes = 0; 4698 4699 if (structure & (1 << 0)) { 4700 newmode = drm_display_mode_from_vic_index(connector, video_db, 4701 video_len, 4702 video_index); 4703 if (newmode) { 4704 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4705 drm_mode_probed_add(connector, newmode); 4706 modes++; 4707 } 4708 } 4709 if (structure & (1 << 6)) { 4710 newmode = drm_display_mode_from_vic_index(connector, video_db, 4711 video_len, 4712 video_index); 4713 if (newmode) { 4714 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4715 drm_mode_probed_add(connector, newmode); 4716 modes++; 4717 } 4718 } 4719 if (structure & (1 << 8)) { 4720 newmode = drm_display_mode_from_vic_index(connector, video_db, 4721 video_len, 4722 video_index); 4723 if (newmode) { 4724 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4725 drm_mode_probed_add(connector, newmode); 4726 modes++; 4727 } 4728 } 4729 4730 return modes; 4731 } 4732 4733 /* 4734 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4735 * @connector: connector corresponding to the HDMI sink 4736 * @db: start of the CEA vendor specific block 4737 * @len: length of the CEA block payload, ie. one can access up to db[len] 4738 * 4739 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4740 * also adds the stereo 3d modes when applicable. 4741 */ 4742 static int 4743 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4744 const u8 *video_db, u8 video_len) 4745 { 4746 struct drm_display_info *info = &connector->display_info; 4747 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4748 u8 vic_len, hdmi_3d_len = 0; 4749 u16 mask; 4750 u16 structure_all; 4751 4752 if (len < 8) 4753 goto out; 4754 4755 /* no HDMI_Video_Present */ 4756 if (!(db[8] & (1 << 5))) 4757 goto out; 4758 4759 /* Latency_Fields_Present */ 4760 if (db[8] & (1 << 7)) 4761 offset += 2; 4762 4763 /* I_Latency_Fields_Present */ 4764 if (db[8] & (1 << 6)) 4765 offset += 2; 4766 4767 /* the declared length is not long enough for the 2 first bytes 4768 * of additional video format capabilities */ 4769 if (len < (8 + offset + 2)) 4770 goto out; 4771 4772 /* 3D_Present */ 4773 offset++; 4774 if (db[8 + offset] & (1 << 7)) { 4775 modes += add_hdmi_mandatory_stereo_modes(connector); 4776 4777 /* 3D_Multi_present */ 4778 multi_present = (db[8 + offset] & 0x60) >> 5; 4779 } 4780 4781 offset++; 4782 vic_len = db[8 + offset] >> 5; 4783 hdmi_3d_len = db[8 + offset] & 0x1f; 4784 4785 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4786 u8 vic; 4787 4788 vic = db[9 + offset + i]; 4789 modes += add_hdmi_mode(connector, vic); 4790 } 4791 offset += 1 + vic_len; 4792 4793 if (multi_present == 1) 4794 multi_len = 2; 4795 else if (multi_present == 2) 4796 multi_len = 4; 4797 else 4798 multi_len = 0; 4799 4800 if (len < (8 + offset + hdmi_3d_len - 1)) 4801 goto out; 4802 4803 if (hdmi_3d_len < multi_len) 4804 goto out; 4805 4806 if (multi_present == 1 || multi_present == 2) { 4807 /* 3D_Structure_ALL */ 4808 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4809 4810 /* check if 3D_MASK is present */ 4811 if (multi_present == 2) 4812 mask = (db[10 + offset] << 8) | db[11 + offset]; 4813 else 4814 mask = 0xffff; 4815 4816 for (i = 0; i < 16; i++) { 4817 if (mask & (1 << i)) 4818 modes += add_3d_struct_modes(connector, 4819 structure_all, 4820 video_db, 4821 video_len, i); 4822 } 4823 } 4824 4825 offset += multi_len; 4826 4827 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4828 int vic_index; 4829 struct drm_display_mode *newmode = NULL; 4830 unsigned int newflag = 0; 4831 bool detail_present; 4832 4833 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4834 4835 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4836 break; 4837 4838 /* 2D_VIC_order_X */ 4839 vic_index = db[8 + offset + i] >> 4; 4840 4841 /* 3D_Structure_X */ 4842 switch (db[8 + offset + i] & 0x0f) { 4843 case 0: 4844 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4845 break; 4846 case 6: 4847 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4848 break; 4849 case 8: 4850 /* 3D_Detail_X */ 4851 if ((db[9 + offset + i] >> 4) == 1) 4852 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4853 break; 4854 } 4855 4856 if (newflag != 0) { 4857 newmode = drm_display_mode_from_vic_index(connector, 4858 video_db, 4859 video_len, 4860 vic_index); 4861 4862 if (newmode) { 4863 newmode->flags |= newflag; 4864 drm_mode_probed_add(connector, newmode); 4865 modes++; 4866 } 4867 } 4868 4869 if (detail_present) 4870 i++; 4871 } 4872 4873 out: 4874 if (modes > 0) 4875 info->has_hdmi_infoframe = true; 4876 return modes; 4877 } 4878 4879 static int 4880 cea_revision(const u8 *cea) 4881 { 4882 /* 4883 * FIXME is this correct for the DispID variant? 4884 * The DispID spec doesn't really specify whether 4885 * this is the revision of the CEA extension or 4886 * the DispID CEA data block. And the only value 4887 * given as an example is 0. 4888 */ 4889 return cea[1]; 4890 } 4891 4892 /* 4893 * CTA Data Block iterator. 4894 * 4895 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4896 * CTA Data Blocks. 4897 * 4898 * struct cea_db *db: 4899 * struct cea_db_iter iter; 4900 * 4901 * cea_db_iter_edid_begin(edid, &iter); 4902 * cea_db_iter_for_each(db, &iter) { 4903 * // do stuff with db 4904 * } 4905 * cea_db_iter_end(&iter); 4906 */ 4907 struct cea_db_iter { 4908 struct drm_edid_iter edid_iter; 4909 struct displayid_iter displayid_iter; 4910 4911 /* Current Data Block Collection. */ 4912 const u8 *collection; 4913 4914 /* Current Data Block index in current collection. */ 4915 int index; 4916 4917 /* End index in current collection. */ 4918 int end; 4919 }; 4920 4921 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4922 struct cea_db { 4923 u8 tag_length; 4924 u8 data[]; 4925 } __packed; 4926 4927 static int cea_db_tag(const struct cea_db *db) 4928 { 4929 return db->tag_length >> 5; 4930 } 4931 4932 static int cea_db_payload_len(const void *_db) 4933 { 4934 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4935 const struct cea_db *db = _db; 4936 4937 return db->tag_length & 0x1f; 4938 } 4939 4940 static const void *cea_db_data(const struct cea_db *db) 4941 { 4942 return db->data; 4943 } 4944 4945 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4946 { 4947 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4948 cea_db_payload_len(db) >= 1 && 4949 db->data[0] == tag; 4950 } 4951 4952 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4953 { 4954 const u8 *data = cea_db_data(db); 4955 4956 return cea_db_tag(db) == CTA_DB_VENDOR && 4957 cea_db_payload_len(db) >= 3 && 4958 oui(data[2], data[1], data[0]) == vendor_oui; 4959 } 4960 4961 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4962 struct cea_db_iter *iter) 4963 { 4964 memset(iter, 0, sizeof(*iter)); 4965 4966 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4967 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4968 } 4969 4970 static const struct cea_db * 4971 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4972 { 4973 const struct cea_db *db; 4974 4975 if (!iter->collection) 4976 return NULL; 4977 4978 db = (const struct cea_db *)&iter->collection[iter->index]; 4979 4980 if (iter->index + sizeof(*db) <= iter->end && 4981 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4982 return db; 4983 4984 return NULL; 4985 } 4986 4987 /* 4988 * References: 4989 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4990 */ 4991 static int cea_db_collection_size(const u8 *cta) 4992 { 4993 u8 d = cta[2]; 4994 4995 if (d < 4 || d > 127) 4996 return 0; 4997 4998 return d - 4; 4999 } 5000 5001 /* 5002 * References: 5003 * - VESA E-EDID v1.4 5004 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5005 */ 5006 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5007 { 5008 const u8 *ext; 5009 5010 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5011 int size; 5012 5013 /* Only support CTA Extension revision 3+ */ 5014 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5015 continue; 5016 5017 size = cea_db_collection_size(ext); 5018 if (!size) 5019 continue; 5020 5021 iter->index = 4; 5022 iter->end = iter->index + size; 5023 5024 return ext; 5025 } 5026 5027 return NULL; 5028 } 5029 5030 /* 5031 * References: 5032 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5033 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5034 * 5035 * Note that the above do not specify any connection between DisplayID Data 5036 * Block revision and CTA Extension versions. 5037 */ 5038 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5039 { 5040 const struct displayid_block *block; 5041 5042 displayid_iter_for_each(block, &iter->displayid_iter) { 5043 if (block->tag != DATA_BLOCK_CTA) 5044 continue; 5045 5046 /* 5047 * The displayid iterator has already verified the block bounds 5048 * in displayid_iter_block(). 5049 */ 5050 iter->index = sizeof(*block); 5051 iter->end = iter->index + block->num_bytes; 5052 5053 return block; 5054 } 5055 5056 return NULL; 5057 } 5058 5059 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5060 { 5061 const struct cea_db *db; 5062 5063 if (iter->collection) { 5064 /* Current collection should always be valid. */ 5065 db = __cea_db_iter_current_block(iter); 5066 if (WARN_ON(!db)) { 5067 iter->collection = NULL; 5068 return NULL; 5069 } 5070 5071 /* Next block in CTA Data Block Collection */ 5072 iter->index += sizeof(*db) + cea_db_payload_len(db); 5073 5074 db = __cea_db_iter_current_block(iter); 5075 if (db) 5076 return db; 5077 } 5078 5079 for (;;) { 5080 /* 5081 * Find the next CTA Data Block Collection. First iterate all 5082 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5083 * 5084 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5085 * Extension, it's recommended that DisplayID extensions are 5086 * exposed after all of the CTA Extensions. 5087 */ 5088 iter->collection = __cea_db_iter_edid_next(iter); 5089 if (!iter->collection) 5090 iter->collection = __cea_db_iter_displayid_next(iter); 5091 5092 if (!iter->collection) 5093 return NULL; 5094 5095 db = __cea_db_iter_current_block(iter); 5096 if (db) 5097 return db; 5098 } 5099 } 5100 5101 #define cea_db_iter_for_each(__db, __iter) \ 5102 while (((__db) = __cea_db_iter_next(__iter))) 5103 5104 static void cea_db_iter_end(struct cea_db_iter *iter) 5105 { 5106 displayid_iter_end(&iter->displayid_iter); 5107 drm_edid_iter_end(&iter->edid_iter); 5108 5109 memset(iter, 0, sizeof(*iter)); 5110 } 5111 5112 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5113 { 5114 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5115 cea_db_payload_len(db) >= 5; 5116 } 5117 5118 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5119 { 5120 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5121 cea_db_payload_len(db) >= 7; 5122 } 5123 5124 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5125 { 5126 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5127 cea_db_payload_len(db) >= 2; 5128 } 5129 5130 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5131 { 5132 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5133 cea_db_payload_len(db) == 21; 5134 } 5135 5136 static bool cea_db_is_vcdb(const struct cea_db *db) 5137 { 5138 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5139 cea_db_payload_len(db) == 2; 5140 } 5141 5142 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5143 { 5144 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5145 cea_db_payload_len(db) >= 7; 5146 } 5147 5148 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5149 { 5150 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5151 } 5152 5153 static bool cea_db_is_y420vdb(const struct cea_db *db) 5154 { 5155 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5156 } 5157 5158 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5159 { 5160 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5161 cea_db_payload_len(db) >= 3; 5162 } 5163 5164 /* 5165 * Get the HF-EEODB override extension block count from EDID. 5166 * 5167 * The passed in EDID may be partially read, as long as it has at least two 5168 * blocks (base block and one extension block) if EDID extension count is > 0. 5169 * 5170 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5171 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5172 * iterators instead. 5173 * 5174 * References: 5175 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5176 */ 5177 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5178 { 5179 const u8 *cta; 5180 5181 /* No extensions according to base block, no HF-EEODB. */ 5182 if (!edid_extension_block_count(edid)) 5183 return 0; 5184 5185 /* HF-EEODB is always in the first EDID extension block only */ 5186 cta = edid_extension_block_data(edid, 0); 5187 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5188 return 0; 5189 5190 /* Need to have the data block collection, and at least 3 bytes. */ 5191 if (cea_db_collection_size(cta) < 3) 5192 return 0; 5193 5194 /* 5195 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5196 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5197 * through 6 of Block 1 of the E-EDID. 5198 */ 5199 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5200 return 0; 5201 5202 return cta[4 + 2]; 5203 } 5204 5205 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 5206 const u8 *db) 5207 { 5208 struct drm_display_info *info = &connector->display_info; 5209 struct drm_hdmi_info *hdmi = &info->hdmi; 5210 u8 map_len = cea_db_payload_len(db) - 1; 5211 u8 count; 5212 u64 map = 0; 5213 5214 if (map_len == 0) { 5215 /* All CEA modes support ycbcr420 sampling also.*/ 5216 hdmi->y420_cmdb_map = U64_MAX; 5217 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5218 return; 5219 } 5220 5221 /* 5222 * This map indicates which of the existing CEA block modes 5223 * from VDB can support YCBCR420 output too. So if bit=0 is 5224 * set, first mode from VDB can support YCBCR420 output too. 5225 * We will parse and keep this map, before parsing VDB itself 5226 * to avoid going through the same block again and again. 5227 * 5228 * Spec is not clear about max possible size of this block. 5229 * Clamping max bitmap block size at 8 bytes. Every byte can 5230 * address 8 CEA modes, in this way this map can address 5231 * 8*8 = first 64 SVDs. 5232 */ 5233 if (WARN_ON_ONCE(map_len > 8)) 5234 map_len = 8; 5235 5236 for (count = 0; count < map_len; count++) 5237 map |= (u64)db[2 + count] << (8 * count); 5238 5239 if (map) 5240 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5241 5242 hdmi->y420_cmdb_map = map; 5243 } 5244 5245 static int add_cea_modes(struct drm_connector *connector, 5246 const struct drm_edid *drm_edid) 5247 { 5248 const struct cea_db *db; 5249 struct cea_db_iter iter; 5250 int modes = 0; 5251 5252 cea_db_iter_edid_begin(drm_edid, &iter); 5253 cea_db_iter_for_each(db, &iter) { 5254 const u8 *hdmi = NULL, *video = NULL; 5255 u8 hdmi_len = 0, video_len = 0; 5256 5257 if (cea_db_tag(db) == CTA_DB_VIDEO) { 5258 video = cea_db_data(db); 5259 video_len = cea_db_payload_len(db); 5260 modes += do_cea_modes(connector, video, video_len); 5261 } else if (cea_db_is_hdmi_vsdb(db)) { 5262 /* FIXME: Switch to use cea_db_data() */ 5263 hdmi = (const u8 *)db; 5264 hdmi_len = cea_db_payload_len(db); 5265 } else if (cea_db_is_y420vdb(db)) { 5266 const u8 *vdb420 = cea_db_data(db) + 1; 5267 5268 /* Add 4:2:0(only) modes present in EDID */ 5269 modes += do_y420vdb_modes(connector, vdb420, 5270 cea_db_payload_len(db) - 1); 5271 } 5272 5273 /* 5274 * We parse the HDMI VSDB after having added the cea modes as we 5275 * will be patching their flags when the sink supports stereo 5276 * 3D. 5277 */ 5278 if (hdmi) 5279 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, 5280 video, video_len); 5281 } 5282 cea_db_iter_end(&iter); 5283 5284 return modes; 5285 } 5286 5287 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5288 struct drm_display_mode *mode) 5289 { 5290 const struct drm_display_mode *cea_mode; 5291 int clock1, clock2, clock; 5292 u8 vic; 5293 const char *type; 5294 5295 /* 5296 * allow 5kHz clock difference either way to account for 5297 * the 10kHz clock resolution limit of detailed timings. 5298 */ 5299 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5300 if (drm_valid_cea_vic(vic)) { 5301 type = "CEA"; 5302 cea_mode = cea_mode_for_vic(vic); 5303 clock1 = cea_mode->clock; 5304 clock2 = cea_mode_alternate_clock(cea_mode); 5305 } else { 5306 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5307 if (drm_valid_hdmi_vic(vic)) { 5308 type = "HDMI"; 5309 cea_mode = &edid_4k_modes[vic]; 5310 clock1 = cea_mode->clock; 5311 clock2 = hdmi_mode_alternate_clock(cea_mode); 5312 } else { 5313 return; 5314 } 5315 } 5316 5317 /* pick whichever is closest */ 5318 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5319 clock = clock1; 5320 else 5321 clock = clock2; 5322 5323 if (mode->clock == clock) 5324 return; 5325 5326 drm_dbg_kms(connector->dev, 5327 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5328 connector->base.id, connector->name, 5329 type, vic, mode->clock, clock); 5330 mode->clock = clock; 5331 } 5332 5333 static void drm_calculate_luminance_range(struct drm_connector *connector) 5334 { 5335 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5336 struct drm_luminance_range_info *luminance_range = 5337 &connector->display_info.luminance_range; 5338 static const u8 pre_computed_values[] = { 5339 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5340 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5341 }; 5342 u32 max_avg, min_cll, max, min, q, r; 5343 5344 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5345 return; 5346 5347 max_avg = hdr_metadata->max_fall; 5348 min_cll = hdr_metadata->min_cll; 5349 5350 /* 5351 * From the specification (CTA-861-G), for calculating the maximum 5352 * luminance we need to use: 5353 * Luminance = 50*2**(CV/32) 5354 * Where CV is a one-byte value. 5355 * For calculating this expression we may need float point precision; 5356 * to avoid this complexity level, we take advantage that CV is divided 5357 * by a constant. From the Euclids division algorithm, we know that CV 5358 * can be written as: CV = 32*q + r. Next, we replace CV in the 5359 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5360 * need to pre-compute the value of r/32. For pre-computing the values 5361 * We just used the following Ruby line: 5362 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5363 * The results of the above expressions can be verified at 5364 * pre_computed_values. 5365 */ 5366 q = max_avg >> 5; 5367 r = max_avg % 32; 5368 max = (1 << q) * pre_computed_values[r]; 5369 5370 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5371 q = DIV_ROUND_CLOSEST(min_cll, 255); 5372 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5373 5374 luminance_range->min_luminance = min; 5375 luminance_range->max_luminance = max; 5376 } 5377 5378 static uint8_t eotf_supported(const u8 *edid_ext) 5379 { 5380 return edid_ext[2] & 5381 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5382 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5383 BIT(HDMI_EOTF_SMPTE_ST2084) | 5384 BIT(HDMI_EOTF_BT_2100_HLG)); 5385 } 5386 5387 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5388 { 5389 return edid_ext[3] & 5390 BIT(HDMI_STATIC_METADATA_TYPE1); 5391 } 5392 5393 static void 5394 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5395 { 5396 u16 len; 5397 5398 len = cea_db_payload_len(db); 5399 5400 connector->hdr_sink_metadata.hdmi_type1.eotf = 5401 eotf_supported(db); 5402 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5403 hdr_metadata_type(db); 5404 5405 if (len >= 4) 5406 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5407 if (len >= 5) 5408 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5409 if (len >= 6) { 5410 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5411 5412 /* Calculate only when all values are available */ 5413 drm_calculate_luminance_range(connector); 5414 } 5415 } 5416 5417 static void 5418 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5419 { 5420 u8 len = cea_db_payload_len(db); 5421 5422 if (len >= 6 && (db[6] & (1 << 7))) 5423 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5424 if (len >= 8) { 5425 connector->latency_present[0] = db[8] >> 7; 5426 connector->latency_present[1] = (db[8] >> 6) & 1; 5427 } 5428 if (len >= 9) 5429 connector->video_latency[0] = db[9]; 5430 if (len >= 10) 5431 connector->audio_latency[0] = db[10]; 5432 if (len >= 11) 5433 connector->video_latency[1] = db[11]; 5434 if (len >= 12) 5435 connector->audio_latency[1] = db[12]; 5436 5437 drm_dbg_kms(connector->dev, 5438 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5439 connector->base.id, connector->name, 5440 connector->latency_present[0], connector->latency_present[1], 5441 connector->video_latency[0], connector->video_latency[1], 5442 connector->audio_latency[0], connector->audio_latency[1]); 5443 } 5444 5445 static void 5446 monitor_name(const struct detailed_timing *timing, void *data) 5447 { 5448 const char **res = data; 5449 5450 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5451 return; 5452 5453 *res = timing->data.other_data.data.str.str; 5454 } 5455 5456 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5457 { 5458 const char *edid_name = NULL; 5459 int mnl; 5460 5461 if (!drm_edid || !name) 5462 return 0; 5463 5464 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5465 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5466 if (edid_name[mnl] == 0x0a) 5467 break; 5468 5469 name[mnl] = edid_name[mnl]; 5470 } 5471 5472 return mnl; 5473 } 5474 5475 /** 5476 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5477 * @edid: monitor EDID information 5478 * @name: pointer to a character array to hold the name of the monitor 5479 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5480 * 5481 */ 5482 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5483 { 5484 int name_length = 0; 5485 5486 if (bufsize <= 0) 5487 return; 5488 5489 if (edid) { 5490 char buf[13]; 5491 struct drm_edid drm_edid = { 5492 .edid = edid, 5493 .size = edid_size(edid), 5494 }; 5495 5496 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5497 memcpy(name, buf, name_length); 5498 } 5499 5500 name[name_length] = '\0'; 5501 } 5502 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5503 5504 static void clear_eld(struct drm_connector *connector) 5505 { 5506 memset(connector->eld, 0, sizeof(connector->eld)); 5507 5508 connector->latency_present[0] = false; 5509 connector->latency_present[1] = false; 5510 connector->video_latency[0] = 0; 5511 connector->audio_latency[0] = 0; 5512 connector->video_latency[1] = 0; 5513 connector->audio_latency[1] = 0; 5514 } 5515 5516 /* 5517 * drm_edid_to_eld - build ELD from EDID 5518 * @connector: connector corresponding to the HDMI/DP sink 5519 * @drm_edid: EDID to parse 5520 * 5521 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5522 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5523 */ 5524 static void drm_edid_to_eld(struct drm_connector *connector, 5525 const struct drm_edid *drm_edid) 5526 { 5527 const struct drm_display_info *info = &connector->display_info; 5528 const struct cea_db *db; 5529 struct cea_db_iter iter; 5530 uint8_t *eld = connector->eld; 5531 int total_sad_count = 0; 5532 int mnl; 5533 5534 clear_eld(connector); 5535 5536 if (!drm_edid) 5537 return; 5538 5539 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5540 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5541 connector->base.id, connector->name, 5542 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5543 5544 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5545 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5546 5547 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5548 5549 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5550 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5551 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5552 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5553 5554 cea_db_iter_edid_begin(drm_edid, &iter); 5555 cea_db_iter_for_each(db, &iter) { 5556 const u8 *data = cea_db_data(db); 5557 int len = cea_db_payload_len(db); 5558 int sad_count; 5559 5560 switch (cea_db_tag(db)) { 5561 case CTA_DB_AUDIO: 5562 /* Audio Data Block, contains SADs */ 5563 sad_count = min(len / 3, 15 - total_sad_count); 5564 if (sad_count >= 1) 5565 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5566 data, sad_count * 3); 5567 total_sad_count += sad_count; 5568 break; 5569 case CTA_DB_SPEAKER: 5570 /* Speaker Allocation Data Block */ 5571 if (len >= 1) 5572 eld[DRM_ELD_SPEAKER] = data[0]; 5573 break; 5574 case CTA_DB_VENDOR: 5575 /* HDMI Vendor-Specific Data Block */ 5576 if (cea_db_is_hdmi_vsdb(db)) 5577 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5578 break; 5579 default: 5580 break; 5581 } 5582 } 5583 cea_db_iter_end(&iter); 5584 5585 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5586 5587 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5588 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5589 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5590 else 5591 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5592 5593 eld[DRM_ELD_BASELINE_ELD_LEN] = 5594 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5595 5596 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5597 connector->base.id, connector->name, 5598 drm_eld_size(eld), total_sad_count); 5599 } 5600 5601 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5602 struct cea_sad **sads) 5603 { 5604 const struct cea_db *db; 5605 struct cea_db_iter iter; 5606 int count = 0; 5607 5608 cea_db_iter_edid_begin(drm_edid, &iter); 5609 cea_db_iter_for_each(db, &iter) { 5610 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5611 int j; 5612 5613 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5614 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5615 if (!*sads) 5616 return -ENOMEM; 5617 for (j = 0; j < count; j++) { 5618 const u8 *sad = &db->data[j * 3]; 5619 5620 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5621 (*sads)[j].channels = sad[0] & 0x7; 5622 (*sads)[j].freq = sad[1] & 0x7F; 5623 (*sads)[j].byte2 = sad[2]; 5624 } 5625 break; 5626 } 5627 } 5628 cea_db_iter_end(&iter); 5629 5630 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5631 5632 return count; 5633 } 5634 5635 /** 5636 * drm_edid_to_sad - extracts SADs from EDID 5637 * @edid: EDID to parse 5638 * @sads: pointer that will be set to the extracted SADs 5639 * 5640 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5641 * 5642 * Note: The returned pointer needs to be freed using kfree(). 5643 * 5644 * Return: The number of found SADs or negative number on error. 5645 */ 5646 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5647 { 5648 struct drm_edid drm_edid; 5649 5650 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5651 } 5652 EXPORT_SYMBOL(drm_edid_to_sad); 5653 5654 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5655 u8 **sadb) 5656 { 5657 const struct cea_db *db; 5658 struct cea_db_iter iter; 5659 int count = 0; 5660 5661 cea_db_iter_edid_begin(drm_edid, &iter); 5662 cea_db_iter_for_each(db, &iter) { 5663 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5664 cea_db_payload_len(db) == 3) { 5665 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5666 GFP_KERNEL); 5667 if (!*sadb) 5668 return -ENOMEM; 5669 count = cea_db_payload_len(db); 5670 break; 5671 } 5672 } 5673 cea_db_iter_end(&iter); 5674 5675 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5676 5677 return count; 5678 } 5679 5680 /** 5681 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5682 * @edid: EDID to parse 5683 * @sadb: pointer to the speaker block 5684 * 5685 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5686 * 5687 * Note: The returned pointer needs to be freed using kfree(). 5688 * 5689 * Return: The number of found Speaker Allocation Blocks or negative number on 5690 * error. 5691 */ 5692 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5693 { 5694 struct drm_edid drm_edid; 5695 5696 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5697 sadb); 5698 } 5699 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5700 5701 /** 5702 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5703 * @connector: connector associated with the HDMI/DP sink 5704 * @mode: the display mode 5705 * 5706 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5707 * the sink doesn't support audio or video. 5708 */ 5709 int drm_av_sync_delay(struct drm_connector *connector, 5710 const struct drm_display_mode *mode) 5711 { 5712 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5713 int a, v; 5714 5715 if (!connector->latency_present[0]) 5716 return 0; 5717 if (!connector->latency_present[1]) 5718 i = 0; 5719 5720 a = connector->audio_latency[i]; 5721 v = connector->video_latency[i]; 5722 5723 /* 5724 * HDMI/DP sink doesn't support audio or video? 5725 */ 5726 if (a == 255 || v == 255) 5727 return 0; 5728 5729 /* 5730 * Convert raw EDID values to millisecond. 5731 * Treat unknown latency as 0ms. 5732 */ 5733 if (a) 5734 a = min(2 * (a - 1), 500); 5735 if (v) 5736 v = min(2 * (v - 1), 500); 5737 5738 return max(v - a, 0); 5739 } 5740 EXPORT_SYMBOL(drm_av_sync_delay); 5741 5742 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5743 { 5744 const struct cea_db *db; 5745 struct cea_db_iter iter; 5746 bool hdmi = false; 5747 5748 /* 5749 * Because HDMI identifier is in Vendor Specific Block, 5750 * search it from all data blocks of CEA extension. 5751 */ 5752 cea_db_iter_edid_begin(drm_edid, &iter); 5753 cea_db_iter_for_each(db, &iter) { 5754 if (cea_db_is_hdmi_vsdb(db)) { 5755 hdmi = true; 5756 break; 5757 } 5758 } 5759 cea_db_iter_end(&iter); 5760 5761 return hdmi; 5762 } 5763 5764 /** 5765 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5766 * @edid: monitor EDID information 5767 * 5768 * Parse the CEA extension according to CEA-861-B. 5769 * 5770 * Drivers that have added the modes parsed from EDID to drm_display_info 5771 * should use &drm_display_info.is_hdmi instead of calling this function. 5772 * 5773 * Return: True if the monitor is HDMI, false if not or unknown. 5774 */ 5775 bool drm_detect_hdmi_monitor(const struct edid *edid) 5776 { 5777 struct drm_edid drm_edid; 5778 5779 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5780 } 5781 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5782 5783 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5784 { 5785 struct drm_edid_iter edid_iter; 5786 const struct cea_db *db; 5787 struct cea_db_iter iter; 5788 const u8 *edid_ext; 5789 bool has_audio = false; 5790 5791 drm_edid_iter_begin(drm_edid, &edid_iter); 5792 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5793 if (edid_ext[0] == CEA_EXT) { 5794 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5795 if (has_audio) 5796 break; 5797 } 5798 } 5799 drm_edid_iter_end(&edid_iter); 5800 5801 if (has_audio) { 5802 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5803 goto end; 5804 } 5805 5806 cea_db_iter_edid_begin(drm_edid, &iter); 5807 cea_db_iter_for_each(db, &iter) { 5808 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5809 const u8 *data = cea_db_data(db); 5810 int i; 5811 5812 for (i = 0; i < cea_db_payload_len(db); i += 3) 5813 DRM_DEBUG_KMS("CEA audio format %d\n", 5814 (data[i] >> 3) & 0xf); 5815 has_audio = true; 5816 break; 5817 } 5818 } 5819 cea_db_iter_end(&iter); 5820 5821 end: 5822 return has_audio; 5823 } 5824 5825 /** 5826 * drm_detect_monitor_audio - check monitor audio capability 5827 * @edid: EDID block to scan 5828 * 5829 * Monitor should have CEA extension block. 5830 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5831 * audio' only. If there is any audio extension block and supported 5832 * audio format, assume at least 'basic audio' support, even if 'basic 5833 * audio' is not defined in EDID. 5834 * 5835 * Return: True if the monitor supports audio, false otherwise. 5836 */ 5837 bool drm_detect_monitor_audio(const struct edid *edid) 5838 { 5839 struct drm_edid drm_edid; 5840 5841 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5842 } 5843 EXPORT_SYMBOL(drm_detect_monitor_audio); 5844 5845 5846 /** 5847 * drm_default_rgb_quant_range - default RGB quantization range 5848 * @mode: display mode 5849 * 5850 * Determine the default RGB quantization range for the mode, 5851 * as specified in CEA-861. 5852 * 5853 * Return: The default RGB quantization range for the mode 5854 */ 5855 enum hdmi_quantization_range 5856 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5857 { 5858 /* All CEA modes other than VIC 1 use limited quantization range. */ 5859 return drm_match_cea_mode(mode) > 1 ? 5860 HDMI_QUANTIZATION_RANGE_LIMITED : 5861 HDMI_QUANTIZATION_RANGE_FULL; 5862 } 5863 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5864 5865 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5866 { 5867 struct drm_display_info *info = &connector->display_info; 5868 5869 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5870 connector->base.id, connector->name, db[2]); 5871 5872 if (db[2] & EDID_CEA_VCDB_QS) 5873 info->rgb_quant_range_selectable = true; 5874 } 5875 5876 static 5877 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5878 { 5879 switch (max_frl_rate) { 5880 case 1: 5881 *max_lanes = 3; 5882 *max_rate_per_lane = 3; 5883 break; 5884 case 2: 5885 *max_lanes = 3; 5886 *max_rate_per_lane = 6; 5887 break; 5888 case 3: 5889 *max_lanes = 4; 5890 *max_rate_per_lane = 6; 5891 break; 5892 case 4: 5893 *max_lanes = 4; 5894 *max_rate_per_lane = 8; 5895 break; 5896 case 5: 5897 *max_lanes = 4; 5898 *max_rate_per_lane = 10; 5899 break; 5900 case 6: 5901 *max_lanes = 4; 5902 *max_rate_per_lane = 12; 5903 break; 5904 case 0: 5905 default: 5906 *max_lanes = 0; 5907 *max_rate_per_lane = 0; 5908 } 5909 } 5910 5911 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5912 const u8 *db) 5913 { 5914 u8 dc_mask; 5915 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5916 5917 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5918 hdmi->y420_dc_modes = dc_mask; 5919 } 5920 5921 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 5922 const u8 *hf_scds) 5923 { 5924 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5925 5926 if (!hdmi_dsc->v_1p2) 5927 return; 5928 5929 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5930 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5931 5932 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 5933 hdmi_dsc->bpc_supported = 16; 5934 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 5935 hdmi_dsc->bpc_supported = 12; 5936 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 5937 hdmi_dsc->bpc_supported = 10; 5938 else 5939 /* Supports min 8 BPC if DSC 1.2 is supported*/ 5940 hdmi_dsc->bpc_supported = 8; 5941 5942 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 5943 u8 dsc_max_slices; 5944 u8 dsc_max_frl_rate; 5945 5946 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5947 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5948 &hdmi_dsc->max_frl_rate_per_lane); 5949 5950 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 5951 5952 switch (dsc_max_slices) { 5953 case 1: 5954 hdmi_dsc->max_slices = 1; 5955 hdmi_dsc->clk_per_slice = 340; 5956 break; 5957 case 2: 5958 hdmi_dsc->max_slices = 2; 5959 hdmi_dsc->clk_per_slice = 340; 5960 break; 5961 case 3: 5962 hdmi_dsc->max_slices = 4; 5963 hdmi_dsc->clk_per_slice = 340; 5964 break; 5965 case 4: 5966 hdmi_dsc->max_slices = 8; 5967 hdmi_dsc->clk_per_slice = 340; 5968 break; 5969 case 5: 5970 hdmi_dsc->max_slices = 8; 5971 hdmi_dsc->clk_per_slice = 400; 5972 break; 5973 case 6: 5974 hdmi_dsc->max_slices = 12; 5975 hdmi_dsc->clk_per_slice = 400; 5976 break; 5977 case 7: 5978 hdmi_dsc->max_slices = 16; 5979 hdmi_dsc->clk_per_slice = 400; 5980 break; 5981 case 0: 5982 default: 5983 hdmi_dsc->max_slices = 0; 5984 hdmi_dsc->clk_per_slice = 0; 5985 } 5986 } 5987 5988 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 5989 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5990 } 5991 5992 /* Sink Capability Data Structure */ 5993 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 5994 const u8 *hf_scds) 5995 { 5996 struct drm_display_info *display = &connector->display_info; 5997 struct drm_hdmi_info *hdmi = &display->hdmi; 5998 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5999 int max_tmds_clock = 0; 6000 u8 max_frl_rate = 0; 6001 bool dsc_support = false; 6002 6003 display->has_hdmi_infoframe = true; 6004 6005 if (hf_scds[6] & 0x80) { 6006 hdmi->scdc.supported = true; 6007 if (hf_scds[6] & 0x40) 6008 hdmi->scdc.read_request = true; 6009 } 6010 6011 /* 6012 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6013 * And as per the spec, three factors confirm this: 6014 * * Availability of a HF-VSDB block in EDID (check) 6015 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6016 * * SCDC support available (let's check) 6017 * Lets check it out. 6018 */ 6019 6020 if (hf_scds[5]) { 6021 struct drm_scdc *scdc = &hdmi->scdc; 6022 6023 /* max clock is 5000 KHz times block value */ 6024 max_tmds_clock = hf_scds[5] * 5000; 6025 6026 if (max_tmds_clock > 340000) { 6027 display->max_tmds_clock = max_tmds_clock; 6028 } 6029 6030 if (scdc->supported) { 6031 scdc->scrambling.supported = true; 6032 6033 /* Few sinks support scrambling for clocks < 340M */ 6034 if ((hf_scds[6] & 0x8)) 6035 scdc->scrambling.low_rates = true; 6036 } 6037 } 6038 6039 if (hf_scds[7]) { 6040 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6041 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6042 &hdmi->max_frl_rate_per_lane); 6043 } 6044 6045 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6046 6047 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6048 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6049 dsc_support = true; 6050 } 6051 6052 drm_dbg_kms(connector->dev, 6053 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6054 connector->base.id, connector->name, 6055 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6056 } 6057 6058 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6059 const u8 *hdmi) 6060 { 6061 struct drm_display_info *info = &connector->display_info; 6062 unsigned int dc_bpc = 0; 6063 6064 /* HDMI supports at least 8 bpc */ 6065 info->bpc = 8; 6066 6067 if (cea_db_payload_len(hdmi) < 6) 6068 return; 6069 6070 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6071 dc_bpc = 10; 6072 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6073 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6074 connector->base.id, connector->name); 6075 } 6076 6077 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6078 dc_bpc = 12; 6079 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6080 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6081 connector->base.id, connector->name); 6082 } 6083 6084 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6085 dc_bpc = 16; 6086 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6087 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6088 connector->base.id, connector->name); 6089 } 6090 6091 if (dc_bpc == 0) { 6092 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6093 connector->base.id, connector->name); 6094 return; 6095 } 6096 6097 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6098 connector->base.id, connector->name, dc_bpc); 6099 info->bpc = dc_bpc; 6100 6101 /* YCRCB444 is optional according to spec. */ 6102 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6103 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6104 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6105 connector->base.id, connector->name); 6106 } 6107 6108 /* 6109 * Spec says that if any deep color mode is supported at all, 6110 * then deep color 36 bit must be supported. 6111 */ 6112 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6113 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6114 connector->base.id, connector->name); 6115 } 6116 } 6117 6118 static void 6119 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6120 { 6121 struct drm_display_info *info = &connector->display_info; 6122 u8 len = cea_db_payload_len(db); 6123 6124 info->is_hdmi = true; 6125 6126 if (len >= 6) 6127 info->dvi_dual = db[6] & 1; 6128 if (len >= 7) 6129 info->max_tmds_clock = db[7] * 5000; 6130 6131 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6132 connector->base.id, connector->name, 6133 info->dvi_dual, info->max_tmds_clock); 6134 6135 drm_parse_hdmi_deep_color_info(connector, db); 6136 } 6137 6138 /* 6139 * See EDID extension for head-mounted and specialized monitors, specified at: 6140 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6141 */ 6142 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6143 const u8 *db) 6144 { 6145 struct drm_display_info *info = &connector->display_info; 6146 u8 version = db[4]; 6147 bool desktop_usage = db[5] & BIT(6); 6148 6149 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6150 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6151 info->non_desktop = true; 6152 6153 drm_dbg_kms(connector->dev, 6154 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6155 connector->base.id, connector->name, version, db[5]); 6156 } 6157 6158 static void drm_parse_cea_ext(struct drm_connector *connector, 6159 const struct drm_edid *drm_edid) 6160 { 6161 struct drm_display_info *info = &connector->display_info; 6162 struct drm_edid_iter edid_iter; 6163 const struct cea_db *db; 6164 struct cea_db_iter iter; 6165 const u8 *edid_ext; 6166 6167 drm_edid_iter_begin(drm_edid, &edid_iter); 6168 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6169 if (edid_ext[0] != CEA_EXT) 6170 continue; 6171 6172 if (!info->cea_rev) 6173 info->cea_rev = edid_ext[1]; 6174 6175 if (info->cea_rev != edid_ext[1]) 6176 drm_dbg_kms(connector->dev, 6177 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6178 connector->base.id, connector->name, 6179 info->cea_rev, edid_ext[1]); 6180 6181 /* The existence of a CTA extension should imply RGB support */ 6182 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6183 if (edid_ext[3] & EDID_CEA_YCRCB444) 6184 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6185 if (edid_ext[3] & EDID_CEA_YCRCB422) 6186 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6187 } 6188 drm_edid_iter_end(&edid_iter); 6189 6190 cea_db_iter_edid_begin(drm_edid, &iter); 6191 cea_db_iter_for_each(db, &iter) { 6192 /* FIXME: convert parsers to use struct cea_db */ 6193 const u8 *data = (const u8 *)db; 6194 6195 if (cea_db_is_hdmi_vsdb(db)) 6196 drm_parse_hdmi_vsdb_video(connector, data); 6197 else if (cea_db_is_hdmi_forum_vsdb(db) || 6198 cea_db_is_hdmi_forum_scdb(db)) 6199 drm_parse_hdmi_forum_scds(connector, data); 6200 else if (cea_db_is_microsoft_vsdb(db)) 6201 drm_parse_microsoft_vsdb(connector, data); 6202 else if (cea_db_is_y420cmdb(db)) 6203 drm_parse_y420cmdb_bitmap(connector, data); 6204 else if (cea_db_is_vcdb(db)) 6205 drm_parse_vcdb(connector, data); 6206 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6207 drm_parse_hdr_metadata_block(connector, data); 6208 } 6209 cea_db_iter_end(&iter); 6210 } 6211 6212 static 6213 void get_monitor_range(const struct detailed_timing *timing, void *c) 6214 { 6215 struct detailed_mode_closure *closure = c; 6216 struct drm_display_info *info = &closure->connector->display_info; 6217 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6218 const struct detailed_non_pixel *data = &timing->data.other_data; 6219 const struct detailed_data_monitor_range *range = &data->data.range; 6220 const struct edid *edid = closure->drm_edid->edid; 6221 6222 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6223 return; 6224 6225 /* 6226 * These limits are used to determine the VRR refresh 6227 * rate range. Only the "range limits only" variant 6228 * of the range descriptor seems to guarantee that 6229 * any and all timings are accepted by the sink, as 6230 * opposed to just timings conforming to the indicated 6231 * formula (GTF/GTF2/CVT). Thus other variants of the 6232 * range descriptor are not accepted here. 6233 */ 6234 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6235 return; 6236 6237 monitor_range->min_vfreq = range->min_vfreq; 6238 monitor_range->max_vfreq = range->max_vfreq; 6239 6240 if (edid->revision >= 4) { 6241 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6242 monitor_range->min_vfreq += 255; 6243 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6244 monitor_range->max_vfreq += 255; 6245 } 6246 } 6247 6248 static void drm_get_monitor_range(struct drm_connector *connector, 6249 const struct drm_edid *drm_edid) 6250 { 6251 const struct drm_display_info *info = &connector->display_info; 6252 struct detailed_mode_closure closure = { 6253 .connector = connector, 6254 .drm_edid = drm_edid, 6255 }; 6256 6257 if (drm_edid->edid->revision < 4) 6258 return; 6259 6260 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6261 return; 6262 6263 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6264 6265 drm_dbg_kms(connector->dev, 6266 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6267 connector->base.id, connector->name, 6268 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6269 } 6270 6271 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6272 const struct displayid_block *block) 6273 { 6274 struct displayid_vesa_vendor_specific_block *vesa = 6275 (struct displayid_vesa_vendor_specific_block *)block; 6276 struct drm_display_info *info = &connector->display_info; 6277 6278 if (block->num_bytes < 3) { 6279 drm_dbg_kms(connector->dev, 6280 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6281 connector->base.id, connector->name, block->num_bytes); 6282 return; 6283 } 6284 6285 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6286 return; 6287 6288 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6289 drm_dbg_kms(connector->dev, 6290 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6291 connector->base.id, connector->name); 6292 return; 6293 } 6294 6295 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6296 default: 6297 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6298 connector->base.id, connector->name); 6299 fallthrough; 6300 case 0: 6301 info->mso_stream_count = 0; 6302 break; 6303 case 1: 6304 info->mso_stream_count = 2; /* 2 or 4 links */ 6305 break; 6306 case 2: 6307 info->mso_stream_count = 4; /* 4 links */ 6308 break; 6309 } 6310 6311 if (!info->mso_stream_count) { 6312 info->mso_pixel_overlap = 0; 6313 return; 6314 } 6315 6316 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6317 if (info->mso_pixel_overlap > 8) { 6318 drm_dbg_kms(connector->dev, 6319 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6320 connector->base.id, connector->name, 6321 info->mso_pixel_overlap); 6322 info->mso_pixel_overlap = 8; 6323 } 6324 6325 drm_dbg_kms(connector->dev, 6326 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6327 connector->base.id, connector->name, 6328 info->mso_stream_count, info->mso_pixel_overlap); 6329 } 6330 6331 static void drm_update_mso(struct drm_connector *connector, 6332 const struct drm_edid *drm_edid) 6333 { 6334 const struct displayid_block *block; 6335 struct displayid_iter iter; 6336 6337 displayid_iter_edid_begin(drm_edid, &iter); 6338 displayid_iter_for_each(block, &iter) { 6339 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6340 drm_parse_vesa_mso_data(connector, block); 6341 } 6342 displayid_iter_end(&iter); 6343 } 6344 6345 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6346 * all of the values which would have been set from EDID 6347 */ 6348 static void drm_reset_display_info(struct drm_connector *connector) 6349 { 6350 struct drm_display_info *info = &connector->display_info; 6351 6352 info->width_mm = 0; 6353 info->height_mm = 0; 6354 6355 info->bpc = 0; 6356 info->color_formats = 0; 6357 info->cea_rev = 0; 6358 info->max_tmds_clock = 0; 6359 info->dvi_dual = false; 6360 info->is_hdmi = false; 6361 info->has_hdmi_infoframe = false; 6362 info->rgb_quant_range_selectable = false; 6363 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6364 6365 info->edid_hdmi_rgb444_dc_modes = 0; 6366 info->edid_hdmi_ycbcr444_dc_modes = 0; 6367 6368 info->non_desktop = 0; 6369 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6370 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6371 6372 info->mso_stream_count = 0; 6373 info->mso_pixel_overlap = 0; 6374 info->max_dsc_bpp = 0; 6375 } 6376 6377 static u32 update_display_info(struct drm_connector *connector, 6378 const struct drm_edid *drm_edid) 6379 { 6380 struct drm_display_info *info = &connector->display_info; 6381 const struct edid *edid = drm_edid->edid; 6382 6383 u32 quirks = edid_get_quirks(drm_edid); 6384 6385 drm_reset_display_info(connector); 6386 6387 info->width_mm = edid->width_cm * 10; 6388 info->height_mm = edid->height_cm * 10; 6389 6390 drm_get_monitor_range(connector, drm_edid); 6391 6392 if (edid->revision < 3) 6393 goto out; 6394 6395 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6396 goto out; 6397 6398 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6399 drm_parse_cea_ext(connector, drm_edid); 6400 6401 /* 6402 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6403 * 6404 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6405 * tells us to assume 8 bpc color depth if the EDID doesn't have 6406 * extensions which tell otherwise. 6407 */ 6408 if (info->bpc == 0 && edid->revision == 3 && 6409 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6410 info->bpc = 8; 6411 drm_dbg_kms(connector->dev, 6412 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6413 connector->base.id, connector->name, info->bpc); 6414 } 6415 6416 /* Only defined for 1.4 with digital displays */ 6417 if (edid->revision < 4) 6418 goto out; 6419 6420 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6421 case DRM_EDID_DIGITAL_DEPTH_6: 6422 info->bpc = 6; 6423 break; 6424 case DRM_EDID_DIGITAL_DEPTH_8: 6425 info->bpc = 8; 6426 break; 6427 case DRM_EDID_DIGITAL_DEPTH_10: 6428 info->bpc = 10; 6429 break; 6430 case DRM_EDID_DIGITAL_DEPTH_12: 6431 info->bpc = 12; 6432 break; 6433 case DRM_EDID_DIGITAL_DEPTH_14: 6434 info->bpc = 14; 6435 break; 6436 case DRM_EDID_DIGITAL_DEPTH_16: 6437 info->bpc = 16; 6438 break; 6439 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6440 default: 6441 info->bpc = 0; 6442 break; 6443 } 6444 6445 drm_dbg_kms(connector->dev, 6446 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6447 connector->base.id, connector->name, info->bpc); 6448 6449 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6450 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6451 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6452 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6453 6454 drm_update_mso(connector, drm_edid); 6455 6456 out: 6457 if (quirks & EDID_QUIRK_NON_DESKTOP) { 6458 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6459 connector->base.id, connector->name, 6460 info->non_desktop ? " (redundant quirk)" : ""); 6461 info->non_desktop = true; 6462 } 6463 6464 if (quirks & EDID_QUIRK_CAP_DSC_15BPP) 6465 info->max_dsc_bpp = 15; 6466 6467 return quirks; 6468 } 6469 6470 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6471 struct displayid_detailed_timings_1 *timings, 6472 bool type_7) 6473 { 6474 struct drm_display_mode *mode; 6475 unsigned pixel_clock = (timings->pixel_clock[0] | 6476 (timings->pixel_clock[1] << 8) | 6477 (timings->pixel_clock[2] << 16)) + 1; 6478 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6479 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6480 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6481 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6482 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6483 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6484 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6485 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6486 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6487 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6488 6489 mode = drm_mode_create(dev); 6490 if (!mode) 6491 return NULL; 6492 6493 /* resolution is kHz for type VII, and 10 kHz for type I */ 6494 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6495 mode->hdisplay = hactive; 6496 mode->hsync_start = mode->hdisplay + hsync; 6497 mode->hsync_end = mode->hsync_start + hsync_width; 6498 mode->htotal = mode->hdisplay + hblank; 6499 6500 mode->vdisplay = vactive; 6501 mode->vsync_start = mode->vdisplay + vsync; 6502 mode->vsync_end = mode->vsync_start + vsync_width; 6503 mode->vtotal = mode->vdisplay + vblank; 6504 6505 mode->flags = 0; 6506 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6507 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6508 mode->type = DRM_MODE_TYPE_DRIVER; 6509 6510 if (timings->flags & 0x80) 6511 mode->type |= DRM_MODE_TYPE_PREFERRED; 6512 drm_mode_set_name(mode); 6513 6514 return mode; 6515 } 6516 6517 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6518 const struct displayid_block *block) 6519 { 6520 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6521 int i; 6522 int num_timings; 6523 struct drm_display_mode *newmode; 6524 int num_modes = 0; 6525 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6526 /* blocks must be multiple of 20 bytes length */ 6527 if (block->num_bytes % 20) 6528 return 0; 6529 6530 num_timings = block->num_bytes / 20; 6531 for (i = 0; i < num_timings; i++) { 6532 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6533 6534 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6535 if (!newmode) 6536 continue; 6537 6538 drm_mode_probed_add(connector, newmode); 6539 num_modes++; 6540 } 6541 return num_modes; 6542 } 6543 6544 static int add_displayid_detailed_modes(struct drm_connector *connector, 6545 const struct drm_edid *drm_edid) 6546 { 6547 const struct displayid_block *block; 6548 struct displayid_iter iter; 6549 int num_modes = 0; 6550 6551 displayid_iter_edid_begin(drm_edid, &iter); 6552 displayid_iter_for_each(block, &iter) { 6553 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6554 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6555 num_modes += add_displayid_detailed_1_modes(connector, block); 6556 } 6557 displayid_iter_end(&iter); 6558 6559 return num_modes; 6560 } 6561 6562 static int _drm_edid_connector_update(struct drm_connector *connector, 6563 const struct drm_edid *drm_edid) 6564 { 6565 int num_modes = 0; 6566 u32 quirks; 6567 6568 if (!drm_edid) { 6569 drm_reset_display_info(connector); 6570 clear_eld(connector); 6571 return 0; 6572 } 6573 6574 /* 6575 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 6576 * To avoid multiple parsing of same block, lets parse that map 6577 * from sink info, before parsing CEA modes. 6578 */ 6579 quirks = update_display_info(connector, drm_edid); 6580 6581 /* Depends on info->cea_rev set by update_display_info() above */ 6582 drm_edid_to_eld(connector, drm_edid); 6583 6584 /* 6585 * EDID spec says modes should be preferred in this order: 6586 * - preferred detailed mode 6587 * - other detailed modes from base block 6588 * - detailed modes from extension blocks 6589 * - CVT 3-byte code modes 6590 * - standard timing codes 6591 * - established timing codes 6592 * - modes inferred from GTF or CVT range information 6593 * 6594 * We get this pretty much right. 6595 * 6596 * XXX order for additional mode types in extension blocks? 6597 */ 6598 num_modes += add_detailed_modes(connector, drm_edid, quirks); 6599 num_modes += add_cvt_modes(connector, drm_edid); 6600 num_modes += add_standard_modes(connector, drm_edid); 6601 num_modes += add_established_modes(connector, drm_edid); 6602 num_modes += add_cea_modes(connector, drm_edid); 6603 num_modes += add_alternate_cea_modes(connector, drm_edid); 6604 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6605 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6606 num_modes += add_inferred_modes(connector, drm_edid); 6607 6608 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6609 edid_fixup_preferred(connector, quirks); 6610 6611 if (quirks & EDID_QUIRK_FORCE_6BPC) 6612 connector->display_info.bpc = 6; 6613 6614 if (quirks & EDID_QUIRK_FORCE_8BPC) 6615 connector->display_info.bpc = 8; 6616 6617 if (quirks & EDID_QUIRK_FORCE_10BPC) 6618 connector->display_info.bpc = 10; 6619 6620 if (quirks & EDID_QUIRK_FORCE_12BPC) 6621 connector->display_info.bpc = 12; 6622 6623 return num_modes; 6624 } 6625 6626 static void _drm_update_tile_info(struct drm_connector *connector, 6627 const struct drm_edid *drm_edid); 6628 6629 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6630 const struct drm_edid *drm_edid) 6631 { 6632 struct drm_device *dev = connector->dev; 6633 int ret; 6634 6635 if (connector->edid_blob_ptr) { 6636 const struct edid *old_edid = connector->edid_blob_ptr->data; 6637 6638 if (old_edid) { 6639 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6640 connector->epoch_counter++; 6641 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6642 connector->base.id, connector->name, 6643 connector->epoch_counter); 6644 } 6645 } 6646 } 6647 6648 ret = drm_property_replace_global_blob(dev, 6649 &connector->edid_blob_ptr, 6650 drm_edid ? drm_edid->size : 0, 6651 drm_edid ? drm_edid->edid : NULL, 6652 &connector->base, 6653 dev->mode_config.edid_property); 6654 if (ret) { 6655 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6656 connector->base.id, connector->name, ret); 6657 goto out; 6658 } 6659 6660 ret = drm_object_property_set_value(&connector->base, 6661 dev->mode_config.non_desktop_property, 6662 connector->display_info.non_desktop); 6663 if (ret) { 6664 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6665 connector->base.id, connector->name, ret); 6666 goto out; 6667 } 6668 6669 ret = drm_connector_set_tile_property(connector); 6670 if (ret) { 6671 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6672 connector->base.id, connector->name, ret); 6673 goto out; 6674 } 6675 6676 out: 6677 return ret; 6678 } 6679 6680 /** 6681 * drm_edid_connector_update - Update connector information from EDID 6682 * @connector: Connector 6683 * @drm_edid: EDID 6684 * 6685 * Update the connector mode list, display info, ELD, HDR metadata, relevant 6686 * properties, etc. from the passed in EDID. 6687 * 6688 * If EDID is NULL, reset the information. 6689 * 6690 * Return: The number of modes added or 0 if we couldn't find any. 6691 */ 6692 int drm_edid_connector_update(struct drm_connector *connector, 6693 const struct drm_edid *drm_edid) 6694 { 6695 int count; 6696 6697 count = _drm_edid_connector_update(connector, drm_edid); 6698 6699 _drm_update_tile_info(connector, drm_edid); 6700 6701 /* Note: Ignore errors for now. */ 6702 _drm_edid_connector_property_update(connector, drm_edid); 6703 6704 return count; 6705 } 6706 EXPORT_SYMBOL(drm_edid_connector_update); 6707 6708 static int _drm_connector_update_edid_property(struct drm_connector *connector, 6709 const struct drm_edid *drm_edid) 6710 { 6711 /* 6712 * Set the display info, using edid if available, otherwise resetting 6713 * the values to defaults. This duplicates the work done in 6714 * drm_add_edid_modes, but that function is not consistently called 6715 * before this one in all drivers and the computation is cheap enough 6716 * that it seems better to duplicate it rather than attempt to ensure 6717 * some arbitrary ordering of calls. 6718 */ 6719 if (drm_edid) 6720 update_display_info(connector, drm_edid); 6721 else 6722 drm_reset_display_info(connector); 6723 6724 _drm_update_tile_info(connector, drm_edid); 6725 6726 return _drm_edid_connector_property_update(connector, drm_edid); 6727 } 6728 6729 /** 6730 * drm_connector_update_edid_property - update the edid property of a connector 6731 * @connector: drm connector 6732 * @edid: new value of the edid property 6733 * 6734 * This function creates a new blob modeset object and assigns its id to the 6735 * connector's edid property. 6736 * Since we also parse tile information from EDID's displayID block, we also 6737 * set the connector's tile property here. See drm_connector_set_tile_property() 6738 * for more details. 6739 * 6740 * This function is deprecated. Use drm_edid_connector_update() instead. 6741 * 6742 * Returns: 6743 * Zero on success, negative errno on failure. 6744 */ 6745 int drm_connector_update_edid_property(struct drm_connector *connector, 6746 const struct edid *edid) 6747 { 6748 struct drm_edid drm_edid; 6749 6750 return _drm_connector_update_edid_property(connector, 6751 drm_edid_legacy_init(&drm_edid, edid)); 6752 } 6753 EXPORT_SYMBOL(drm_connector_update_edid_property); 6754 6755 /** 6756 * drm_add_edid_modes - add modes from EDID data, if available 6757 * @connector: connector we're probing 6758 * @edid: EDID data 6759 * 6760 * Add the specified modes to the connector's mode list. Also fills out the 6761 * &drm_display_info structure and ELD in @connector with any information which 6762 * can be derived from the edid. 6763 * 6764 * This function is deprecated. Use drm_edid_connector_update() instead. 6765 * 6766 * Return: The number of modes added or 0 if we couldn't find any. 6767 */ 6768 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6769 { 6770 struct drm_edid drm_edid; 6771 6772 if (edid && !drm_edid_is_valid(edid)) { 6773 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6774 connector->base.id, connector->name); 6775 edid = NULL; 6776 } 6777 6778 return _drm_edid_connector_update(connector, 6779 drm_edid_legacy_init(&drm_edid, edid)); 6780 } 6781 EXPORT_SYMBOL(drm_add_edid_modes); 6782 6783 /** 6784 * drm_add_modes_noedid - add modes for the connectors without EDID 6785 * @connector: connector we're probing 6786 * @hdisplay: the horizontal display limit 6787 * @vdisplay: the vertical display limit 6788 * 6789 * Add the specified modes to the connector's mode list. Only when the 6790 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6791 * 6792 * Return: The number of modes added or 0 if we couldn't find any. 6793 */ 6794 int drm_add_modes_noedid(struct drm_connector *connector, 6795 int hdisplay, int vdisplay) 6796 { 6797 int i, count, num_modes = 0; 6798 struct drm_display_mode *mode; 6799 struct drm_device *dev = connector->dev; 6800 6801 count = ARRAY_SIZE(drm_dmt_modes); 6802 if (hdisplay < 0) 6803 hdisplay = 0; 6804 if (vdisplay < 0) 6805 vdisplay = 0; 6806 6807 for (i = 0; i < count; i++) { 6808 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6809 6810 if (hdisplay && vdisplay) { 6811 /* 6812 * Only when two are valid, they will be used to check 6813 * whether the mode should be added to the mode list of 6814 * the connector. 6815 */ 6816 if (ptr->hdisplay > hdisplay || 6817 ptr->vdisplay > vdisplay) 6818 continue; 6819 } 6820 if (drm_mode_vrefresh(ptr) > 61) 6821 continue; 6822 mode = drm_mode_duplicate(dev, ptr); 6823 if (mode) { 6824 drm_mode_probed_add(connector, mode); 6825 num_modes++; 6826 } 6827 } 6828 return num_modes; 6829 } 6830 EXPORT_SYMBOL(drm_add_modes_noedid); 6831 6832 /** 6833 * drm_set_preferred_mode - Sets the preferred mode of a connector 6834 * @connector: connector whose mode list should be processed 6835 * @hpref: horizontal resolution of preferred mode 6836 * @vpref: vertical resolution of preferred mode 6837 * 6838 * Marks a mode as preferred if it matches the resolution specified by @hpref 6839 * and @vpref. 6840 */ 6841 void drm_set_preferred_mode(struct drm_connector *connector, 6842 int hpref, int vpref) 6843 { 6844 struct drm_display_mode *mode; 6845 6846 list_for_each_entry(mode, &connector->probed_modes, head) { 6847 if (mode->hdisplay == hpref && 6848 mode->vdisplay == vpref) 6849 mode->type |= DRM_MODE_TYPE_PREFERRED; 6850 } 6851 } 6852 EXPORT_SYMBOL(drm_set_preferred_mode); 6853 6854 static bool is_hdmi2_sink(const struct drm_connector *connector) 6855 { 6856 /* 6857 * FIXME: sil-sii8620 doesn't have a connector around when 6858 * we need one, so we have to be prepared for a NULL connector. 6859 */ 6860 if (!connector) 6861 return true; 6862 6863 return connector->display_info.hdmi.scdc.supported || 6864 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 6865 } 6866 6867 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 6868 const struct drm_display_mode *mode) 6869 { 6870 bool has_hdmi_infoframe = connector ? 6871 connector->display_info.has_hdmi_infoframe : false; 6872 6873 if (!has_hdmi_infoframe) 6874 return 0; 6875 6876 /* No HDMI VIC when signalling 3D video format */ 6877 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 6878 return 0; 6879 6880 return drm_match_hdmi_mode(mode); 6881 } 6882 6883 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 6884 const struct drm_display_mode *mode) 6885 { 6886 u8 vic; 6887 6888 /* 6889 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 6890 * we should send its VIC in vendor infoframes, else send the 6891 * VIC in AVI infoframes. Lets check if this mode is present in 6892 * HDMI 1.4b 4K modes 6893 */ 6894 if (drm_mode_hdmi_vic(connector, mode)) 6895 return 0; 6896 6897 vic = drm_match_cea_mode(mode); 6898 6899 /* 6900 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 6901 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 6902 * have to make sure we dont break HDMI 1.4 sinks. 6903 */ 6904 if (!is_hdmi2_sink(connector) && vic > 64) 6905 return 0; 6906 6907 return vic; 6908 } 6909 6910 /** 6911 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 6912 * data from a DRM display mode 6913 * @frame: HDMI AVI infoframe 6914 * @connector: the connector 6915 * @mode: DRM display mode 6916 * 6917 * Return: 0 on success or a negative error code on failure. 6918 */ 6919 int 6920 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 6921 const struct drm_connector *connector, 6922 const struct drm_display_mode *mode) 6923 { 6924 enum hdmi_picture_aspect picture_aspect; 6925 u8 vic, hdmi_vic; 6926 6927 if (!frame || !mode) 6928 return -EINVAL; 6929 6930 hdmi_avi_infoframe_init(frame); 6931 6932 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 6933 frame->pixel_repeat = 1; 6934 6935 vic = drm_mode_cea_vic(connector, mode); 6936 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 6937 6938 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6939 6940 /* 6941 * As some drivers don't support atomic, we can't use connector state. 6942 * So just initialize the frame with default values, just the same way 6943 * as it's done with other properties here. 6944 */ 6945 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 6946 frame->itc = 0; 6947 6948 /* 6949 * Populate picture aspect ratio from either 6950 * user input (if specified) or from the CEA/HDMI mode lists. 6951 */ 6952 picture_aspect = mode->picture_aspect_ratio; 6953 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 6954 if (vic) 6955 picture_aspect = drm_get_cea_aspect_ratio(vic); 6956 else if (hdmi_vic) 6957 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 6958 } 6959 6960 /* 6961 * The infoframe can't convey anything but none, 4:3 6962 * and 16:9, so if the user has asked for anything else 6963 * we can only satisfy it by specifying the right VIC. 6964 */ 6965 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 6966 if (vic) { 6967 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 6968 return -EINVAL; 6969 } else if (hdmi_vic) { 6970 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 6971 return -EINVAL; 6972 } else { 6973 return -EINVAL; 6974 } 6975 6976 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6977 } 6978 6979 frame->video_code = vic; 6980 frame->picture_aspect = picture_aspect; 6981 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 6982 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 6983 6984 return 0; 6985 } 6986 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 6987 6988 /** 6989 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 6990 * quantization range information 6991 * @frame: HDMI AVI infoframe 6992 * @connector: the connector 6993 * @mode: DRM display mode 6994 * @rgb_quant_range: RGB quantization range (Q) 6995 */ 6996 void 6997 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6998 const struct drm_connector *connector, 6999 const struct drm_display_mode *mode, 7000 enum hdmi_quantization_range rgb_quant_range) 7001 { 7002 const struct drm_display_info *info = &connector->display_info; 7003 7004 /* 7005 * CEA-861: 7006 * "A Source shall not send a non-zero Q value that does not correspond 7007 * to the default RGB Quantization Range for the transmitted Picture 7008 * unless the Sink indicates support for the Q bit in a Video 7009 * Capabilities Data Block." 7010 * 7011 * HDMI 2.0 recommends sending non-zero Q when it does match the 7012 * default RGB quantization range for the mode, even when QS=0. 7013 */ 7014 if (info->rgb_quant_range_selectable || 7015 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7016 frame->quantization_range = rgb_quant_range; 7017 else 7018 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7019 7020 /* 7021 * CEA-861-F: 7022 * "When transmitting any RGB colorimetry, the Source should set the 7023 * YQ-field to match the RGB Quantization Range being transmitted 7024 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7025 * set YQ=1) and the Sink shall ignore the YQ-field." 7026 * 7027 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7028 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7029 * good way to tell which version of CEA-861 the sink supports, so 7030 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7031 * on CEA-861-F. 7032 */ 7033 if (!is_hdmi2_sink(connector) || 7034 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7035 frame->ycc_quantization_range = 7036 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7037 else 7038 frame->ycc_quantization_range = 7039 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7040 } 7041 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7042 7043 static enum hdmi_3d_structure 7044 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7045 { 7046 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7047 7048 switch (layout) { 7049 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7050 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7051 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7052 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7053 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7054 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7055 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7056 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7057 case DRM_MODE_FLAG_3D_L_DEPTH: 7058 return HDMI_3D_STRUCTURE_L_DEPTH; 7059 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7060 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7061 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7062 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7063 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7064 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7065 default: 7066 return HDMI_3D_STRUCTURE_INVALID; 7067 } 7068 } 7069 7070 /** 7071 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7072 * data from a DRM display mode 7073 * @frame: HDMI vendor infoframe 7074 * @connector: the connector 7075 * @mode: DRM display mode 7076 * 7077 * Note that there's is a need to send HDMI vendor infoframes only when using a 7078 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7079 * function will return -EINVAL, error that can be safely ignored. 7080 * 7081 * Return: 0 on success or a negative error code on failure. 7082 */ 7083 int 7084 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7085 const struct drm_connector *connector, 7086 const struct drm_display_mode *mode) 7087 { 7088 /* 7089 * FIXME: sil-sii8620 doesn't have a connector around when 7090 * we need one, so we have to be prepared for a NULL connector. 7091 */ 7092 bool has_hdmi_infoframe = connector ? 7093 connector->display_info.has_hdmi_infoframe : false; 7094 int err; 7095 7096 if (!frame || !mode) 7097 return -EINVAL; 7098 7099 if (!has_hdmi_infoframe) 7100 return -EINVAL; 7101 7102 err = hdmi_vendor_infoframe_init(frame); 7103 if (err < 0) 7104 return err; 7105 7106 /* 7107 * Even if it's not absolutely necessary to send the infoframe 7108 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7109 * know that the sink can handle it. This is based on a 7110 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7111 * have trouble realizing that they should switch from 3D to 2D 7112 * mode if the source simply stops sending the infoframe when 7113 * it wants to switch from 3D to 2D. 7114 */ 7115 frame->vic = drm_mode_hdmi_vic(connector, mode); 7116 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7117 7118 return 0; 7119 } 7120 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7121 7122 static void drm_parse_tiled_block(struct drm_connector *connector, 7123 const struct displayid_block *block) 7124 { 7125 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7126 u16 w, h; 7127 u8 tile_v_loc, tile_h_loc; 7128 u8 num_v_tile, num_h_tile; 7129 struct drm_tile_group *tg; 7130 7131 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7132 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7133 7134 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7135 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7136 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7137 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7138 7139 connector->has_tile = true; 7140 if (tile->tile_cap & 0x80) 7141 connector->tile_is_single_monitor = true; 7142 7143 connector->num_h_tile = num_h_tile + 1; 7144 connector->num_v_tile = num_v_tile + 1; 7145 connector->tile_h_loc = tile_h_loc; 7146 connector->tile_v_loc = tile_v_loc; 7147 connector->tile_h_size = w + 1; 7148 connector->tile_v_size = h + 1; 7149 7150 drm_dbg_kms(connector->dev, 7151 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7152 connector->base.id, connector->name, 7153 tile->tile_cap, 7154 connector->tile_h_size, connector->tile_v_size, 7155 connector->num_h_tile, connector->num_v_tile, 7156 connector->tile_h_loc, connector->tile_v_loc, 7157 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7158 7159 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7160 if (!tg) 7161 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7162 if (!tg) 7163 return; 7164 7165 if (connector->tile_group != tg) { 7166 /* if we haven't got a pointer, 7167 take the reference, drop ref to old tile group */ 7168 if (connector->tile_group) 7169 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7170 connector->tile_group = tg; 7171 } else { 7172 /* if same tile group, then release the ref we just took. */ 7173 drm_mode_put_tile_group(connector->dev, tg); 7174 } 7175 } 7176 7177 static void _drm_update_tile_info(struct drm_connector *connector, 7178 const struct drm_edid *drm_edid) 7179 { 7180 const struct displayid_block *block; 7181 struct displayid_iter iter; 7182 7183 connector->has_tile = false; 7184 7185 displayid_iter_edid_begin(drm_edid, &iter); 7186 displayid_iter_for_each(block, &iter) { 7187 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 7188 drm_parse_tiled_block(connector, block); 7189 } 7190 displayid_iter_end(&iter); 7191 7192 if (!connector->has_tile && connector->tile_group) { 7193 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7194 connector->tile_group = NULL; 7195 } 7196 } 7197