1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_displayid.h> 40 #include <drm/drm_scdc_helper.h> 41 42 #include "drm_crtc_internal.h" 43 44 #define version_greater(edid, maj, min) \ 45 (((edid)->version > (maj)) || \ 46 ((edid)->version == (maj) && (edid)->revision > (min))) 47 48 #define EDID_EST_TIMINGS 16 49 #define EDID_STD_TIMINGS 8 50 #define EDID_DETAILED_TIMINGS 4 51 52 /* 53 * EDID blocks out in the wild have a variety of bugs, try to collect 54 * them here (note that userspace may work around broken monitors first, 55 * but fixes should make their way here so that the kernel "just works" 56 * on as many displays as possible). 57 */ 58 59 /* First detailed mode wrong, use largest 60Hz mode */ 60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 61 /* Reported 135MHz pixel clock is too high, needs adjustment */ 62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 63 /* Prefer the largest mode at 75 Hz */ 64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 65 /* Detail timing is in cm not mm */ 66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 67 /* Detailed timing descriptors have bogus size values, so just take the 68 * maximum size and use that. 69 */ 70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 /* Force 6bpc */ 80 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 81 /* Force 10bpc */ 82 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 83 /* Non desktop display (i.e. HMD) */ 84 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 85 86 struct detailed_mode_closure { 87 struct drm_connector *connector; 88 struct edid *edid; 89 bool preferred; 90 u32 quirks; 91 int modes; 92 }; 93 94 #define LEVEL_DMT 0 95 #define LEVEL_GTF 1 96 #define LEVEL_GTF2 2 97 #define LEVEL_CVT 3 98 99 static const struct edid_quirk { 100 char vendor[4]; 101 int product_id; 102 u32 quirks; 103 } edid_quirk_list[] = { 104 /* Acer AL1706 */ 105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 106 /* Acer F51 */ 107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 108 109 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 110 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 111 112 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 113 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 114 115 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 116 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 117 118 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 119 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 120 121 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 122 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 123 124 /* Belinea 10 15 55 */ 125 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 126 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 127 128 /* Envision Peripherals, Inc. EN-7100e */ 129 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 130 /* Envision EN2028 */ 131 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 132 133 /* Funai Electronics PM36B */ 134 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 135 EDID_QUIRK_DETAILED_IN_CM }, 136 137 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 138 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 139 140 /* LG Philips LCD LP154W01-A5 */ 141 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 142 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 143 144 /* Samsung SyncMaster 205BW. Note: irony */ 145 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 146 /* Samsung SyncMaster 22[5-6]BW */ 147 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 148 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 149 150 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 151 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 152 153 /* ViewSonic VA2026w */ 154 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 155 156 /* Medion MD 30217 PG */ 157 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 158 159 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 160 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 161 162 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 163 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 164 165 /* HTC Vive and Vive Pro VR Headsets */ 166 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 167 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 168 169 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 170 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 171 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 172 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 173 174 /* Windows Mixed Reality Headsets */ 175 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 176 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 177 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 178 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 179 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 180 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 181 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 182 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 183 184 /* Sony PlayStation VR Headset */ 185 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 186 187 /* Sensics VR Headsets */ 188 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 189 190 /* OSVR HDK and HDK2 VR Headsets */ 191 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 192 }; 193 194 /* 195 * Autogenerated from the DMT spec. 196 * This table is copied from xfree86/modes/xf86EdidModes.c. 197 */ 198 static const struct drm_display_mode drm_dmt_modes[] = { 199 /* 0x01 - 640x350@85Hz */ 200 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 201 736, 832, 0, 350, 382, 385, 445, 0, 202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 203 /* 0x02 - 640x400@85Hz */ 204 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 205 736, 832, 0, 400, 401, 404, 445, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 207 /* 0x03 - 720x400@85Hz */ 208 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 209 828, 936, 0, 400, 401, 404, 446, 0, 210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x04 - 640x480@60Hz */ 212 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 213 752, 800, 0, 480, 490, 492, 525, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 215 /* 0x05 - 640x480@72Hz */ 216 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 217 704, 832, 0, 480, 489, 492, 520, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 0x06 - 640x480@75Hz */ 220 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 221 720, 840, 0, 480, 481, 484, 500, 0, 222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 223 /* 0x07 - 640x480@85Hz */ 224 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 225 752, 832, 0, 480, 481, 484, 509, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 227 /* 0x08 - 800x600@56Hz */ 228 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 229 896, 1024, 0, 600, 601, 603, 625, 0, 230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 231 /* 0x09 - 800x600@60Hz */ 232 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 233 968, 1056, 0, 600, 601, 605, 628, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 235 /* 0x0a - 800x600@72Hz */ 236 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 237 976, 1040, 0, 600, 637, 643, 666, 0, 238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 239 /* 0x0b - 800x600@75Hz */ 240 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 241 896, 1056, 0, 600, 601, 604, 625, 0, 242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 243 /* 0x0c - 800x600@85Hz */ 244 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 245 896, 1048, 0, 600, 601, 604, 631, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 247 /* 0x0d - 800x600@120Hz RB */ 248 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 249 880, 960, 0, 600, 603, 607, 636, 0, 250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 0x0e - 848x480@60Hz */ 252 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 253 976, 1088, 0, 480, 486, 494, 517, 0, 254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 255 /* 0x0f - 1024x768@43Hz, interlace */ 256 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 257 1208, 1264, 0, 768, 768, 776, 817, 0, 258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 259 DRM_MODE_FLAG_INTERLACE) }, 260 /* 0x10 - 1024x768@60Hz */ 261 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 262 1184, 1344, 0, 768, 771, 777, 806, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 264 /* 0x11 - 1024x768@70Hz */ 265 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 266 1184, 1328, 0, 768, 771, 777, 806, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x12 - 1024x768@75Hz */ 269 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 270 1136, 1312, 0, 768, 769, 772, 800, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x13 - 1024x768@85Hz */ 273 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 274 1168, 1376, 0, 768, 769, 772, 808, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x14 - 1024x768@120Hz RB */ 277 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 278 1104, 1184, 0, 768, 771, 775, 813, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 280 /* 0x15 - 1152x864@75Hz */ 281 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 282 1344, 1600, 0, 864, 865, 868, 900, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x55 - 1280x720@60Hz */ 285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 286 1430, 1650, 0, 720, 725, 730, 750, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x16 - 1280x768@60Hz RB */ 289 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 290 1360, 1440, 0, 768, 771, 778, 790, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 292 /* 0x17 - 1280x768@60Hz */ 293 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 294 1472, 1664, 0, 768, 771, 778, 798, 0, 295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 296 /* 0x18 - 1280x768@75Hz */ 297 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 298 1488, 1696, 0, 768, 771, 778, 805, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x19 - 1280x768@85Hz */ 301 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 302 1496, 1712, 0, 768, 771, 778, 809, 0, 303 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x1a - 1280x768@120Hz RB */ 305 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 306 1360, 1440, 0, 768, 771, 778, 813, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 308 /* 0x1b - 1280x800@60Hz RB */ 309 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 310 1360, 1440, 0, 800, 803, 809, 823, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 312 /* 0x1c - 1280x800@60Hz */ 313 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 314 1480, 1680, 0, 800, 803, 809, 831, 0, 315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x1d - 1280x800@75Hz */ 317 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 318 1488, 1696, 0, 800, 803, 809, 838, 0, 319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x1e - 1280x800@85Hz */ 321 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 322 1496, 1712, 0, 800, 803, 809, 843, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 0x1f - 1280x800@120Hz RB */ 325 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 326 1360, 1440, 0, 800, 803, 809, 847, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 328 /* 0x20 - 1280x960@60Hz */ 329 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 330 1488, 1800, 0, 960, 961, 964, 1000, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 332 /* 0x21 - 1280x960@85Hz */ 333 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 334 1504, 1728, 0, 960, 961, 964, 1011, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x22 - 1280x960@120Hz RB */ 337 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 338 1360, 1440, 0, 960, 963, 967, 1017, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 340 /* 0x23 - 1280x1024@60Hz */ 341 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 342 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 344 /* 0x24 - 1280x1024@75Hz */ 345 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 346 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x25 - 1280x1024@85Hz */ 349 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 350 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x26 - 1280x1024@120Hz RB */ 353 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 354 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 356 /* 0x27 - 1360x768@60Hz */ 357 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 358 1536, 1792, 0, 768, 771, 777, 795, 0, 359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 360 /* 0x28 - 1360x768@120Hz RB */ 361 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 362 1440, 1520, 0, 768, 771, 776, 813, 0, 363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 364 /* 0x51 - 1366x768@60Hz */ 365 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 366 1579, 1792, 0, 768, 771, 774, 798, 0, 367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x56 - 1366x768@60Hz */ 369 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 370 1436, 1500, 0, 768, 769, 772, 800, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x29 - 1400x1050@60Hz RB */ 373 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 374 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 376 /* 0x2a - 1400x1050@60Hz */ 377 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 378 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x2b - 1400x1050@75Hz */ 381 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 382 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x2c - 1400x1050@85Hz */ 385 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 386 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x2d - 1400x1050@120Hz RB */ 389 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 390 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 392 /* 0x2e - 1440x900@60Hz RB */ 393 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 394 1520, 1600, 0, 900, 903, 909, 926, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 396 /* 0x2f - 1440x900@60Hz */ 397 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 398 1672, 1904, 0, 900, 903, 909, 934, 0, 399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x30 - 1440x900@75Hz */ 401 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 402 1688, 1936, 0, 900, 903, 909, 942, 0, 403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x31 - 1440x900@85Hz */ 405 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 406 1696, 1952, 0, 900, 903, 909, 948, 0, 407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 408 /* 0x32 - 1440x900@120Hz RB */ 409 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 410 1520, 1600, 0, 900, 903, 909, 953, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 412 /* 0x53 - 1600x900@60Hz */ 413 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 414 1704, 1800, 0, 900, 901, 904, 1000, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x33 - 1600x1200@60Hz */ 417 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 418 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x34 - 1600x1200@65Hz */ 421 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 422 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 424 /* 0x35 - 1600x1200@70Hz */ 425 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 426 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 0x36 - 1600x1200@75Hz */ 429 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 430 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x37 - 1600x1200@85Hz */ 433 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 434 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x38 - 1600x1200@120Hz RB */ 437 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 438 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 0x39 - 1680x1050@60Hz RB */ 441 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 442 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x3a - 1680x1050@60Hz */ 445 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 446 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x3b - 1680x1050@75Hz */ 449 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 450 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x3c - 1680x1050@85Hz */ 453 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 454 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x3d - 1680x1050@120Hz RB */ 457 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 458 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 460 /* 0x3e - 1792x1344@60Hz */ 461 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 462 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 464 /* 0x3f - 1792x1344@75Hz */ 465 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 466 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x40 - 1792x1344@120Hz RB */ 469 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 470 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 472 /* 0x41 - 1856x1392@60Hz */ 473 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 474 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 476 /* 0x42 - 1856x1392@75Hz */ 477 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 478 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x43 - 1856x1392@120Hz RB */ 481 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 482 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 484 /* 0x52 - 1920x1080@60Hz */ 485 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 486 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 488 /* 0x44 - 1920x1200@60Hz RB */ 489 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 490 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 492 /* 0x45 - 1920x1200@60Hz */ 493 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 494 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x46 - 1920x1200@75Hz */ 497 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 498 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x47 - 1920x1200@85Hz */ 501 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 502 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x48 - 1920x1200@120Hz RB */ 505 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 506 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 508 /* 0x49 - 1920x1440@60Hz */ 509 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 510 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 512 /* 0x4a - 1920x1440@75Hz */ 513 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 514 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 516 /* 0x4b - 1920x1440@120Hz RB */ 517 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 518 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 /* 0x54 - 2048x1152@60Hz */ 521 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 522 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 524 /* 0x4c - 2560x1600@60Hz RB */ 525 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 526 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 528 /* 0x4d - 2560x1600@60Hz */ 529 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 530 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 532 /* 0x4e - 2560x1600@75Hz */ 533 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 534 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 536 /* 0x4f - 2560x1600@85Hz */ 537 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 538 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 540 /* 0x50 - 2560x1600@120Hz RB */ 541 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 542 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 544 /* 0x57 - 4096x2160@60Hz RB */ 545 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 546 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 548 /* 0x58 - 4096x2160@59.94Hz RB */ 549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 550 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 552 }; 553 554 /* 555 * These more or less come from the DMT spec. The 720x400 modes are 556 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 557 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 558 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 559 * mode. 560 * 561 * The DMT modes have been fact-checked; the rest are mild guesses. 562 */ 563 static const struct drm_display_mode edid_est_modes[] = { 564 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 565 968, 1056, 0, 600, 601, 605, 628, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 567 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 568 896, 1024, 0, 600, 601, 603, 625, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 570 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 571 720, 840, 0, 480, 481, 484, 500, 0, 572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 573 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 574 704, 832, 0, 480, 489, 492, 520, 0, 575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 576 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 577 768, 864, 0, 480, 483, 486, 525, 0, 578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 579 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 580 752, 800, 0, 480, 490, 492, 525, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 582 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 583 846, 900, 0, 400, 421, 423, 449, 0, 584 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 585 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 586 846, 900, 0, 400, 412, 414, 449, 0, 587 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 588 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 589 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 591 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 592 1136, 1312, 0, 768, 769, 772, 800, 0, 593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 594 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 595 1184, 1328, 0, 768, 771, 777, 806, 0, 596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 597 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 598 1184, 1344, 0, 768, 771, 777, 806, 0, 599 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 600 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 601 1208, 1264, 0, 768, 768, 776, 817, 0, 602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 603 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 604 928, 1152, 0, 624, 625, 628, 667, 0, 605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 607 896, 1056, 0, 600, 601, 604, 625, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 610 976, 1040, 0, 600, 637, 643, 666, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 612 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 613 1344, 1600, 0, 864, 865, 868, 900, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 615 }; 616 617 struct minimode { 618 short w; 619 short h; 620 short r; 621 short rb; 622 }; 623 624 static const struct minimode est3_modes[] = { 625 /* byte 6 */ 626 { 640, 350, 85, 0 }, 627 { 640, 400, 85, 0 }, 628 { 720, 400, 85, 0 }, 629 { 640, 480, 85, 0 }, 630 { 848, 480, 60, 0 }, 631 { 800, 600, 85, 0 }, 632 { 1024, 768, 85, 0 }, 633 { 1152, 864, 75, 0 }, 634 /* byte 7 */ 635 { 1280, 768, 60, 1 }, 636 { 1280, 768, 60, 0 }, 637 { 1280, 768, 75, 0 }, 638 { 1280, 768, 85, 0 }, 639 { 1280, 960, 60, 0 }, 640 { 1280, 960, 85, 0 }, 641 { 1280, 1024, 60, 0 }, 642 { 1280, 1024, 85, 0 }, 643 /* byte 8 */ 644 { 1360, 768, 60, 0 }, 645 { 1440, 900, 60, 1 }, 646 { 1440, 900, 60, 0 }, 647 { 1440, 900, 75, 0 }, 648 { 1440, 900, 85, 0 }, 649 { 1400, 1050, 60, 1 }, 650 { 1400, 1050, 60, 0 }, 651 { 1400, 1050, 75, 0 }, 652 /* byte 9 */ 653 { 1400, 1050, 85, 0 }, 654 { 1680, 1050, 60, 1 }, 655 { 1680, 1050, 60, 0 }, 656 { 1680, 1050, 75, 0 }, 657 { 1680, 1050, 85, 0 }, 658 { 1600, 1200, 60, 0 }, 659 { 1600, 1200, 65, 0 }, 660 { 1600, 1200, 70, 0 }, 661 /* byte 10 */ 662 { 1600, 1200, 75, 0 }, 663 { 1600, 1200, 85, 0 }, 664 { 1792, 1344, 60, 0 }, 665 { 1792, 1344, 75, 0 }, 666 { 1856, 1392, 60, 0 }, 667 { 1856, 1392, 75, 0 }, 668 { 1920, 1200, 60, 1 }, 669 { 1920, 1200, 60, 0 }, 670 /* byte 11 */ 671 { 1920, 1200, 75, 0 }, 672 { 1920, 1200, 85, 0 }, 673 { 1920, 1440, 60, 0 }, 674 { 1920, 1440, 75, 0 }, 675 }; 676 677 static const struct minimode extra_modes[] = { 678 { 1024, 576, 60, 0 }, 679 { 1366, 768, 60, 0 }, 680 { 1600, 900, 60, 0 }, 681 { 1680, 945, 60, 0 }, 682 { 1920, 1080, 60, 0 }, 683 { 2048, 1152, 60, 0 }, 684 { 2048, 1536, 60, 0 }, 685 }; 686 687 /* 688 * Probably taken from CEA-861 spec. 689 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 690 * 691 * Index using the VIC. 692 */ 693 static const struct drm_display_mode edid_cea_modes[] = { 694 /* 0 - dummy, VICs start at 1 */ 695 { }, 696 /* 1 - 640x480@60Hz 4:3 */ 697 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 698 752, 800, 0, 480, 490, 492, 525, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 701 /* 2 - 720x480@60Hz 4:3 */ 702 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 703 798, 858, 0, 480, 489, 495, 525, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 705 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 706 /* 3 - 720x480@60Hz 16:9 */ 707 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 708 798, 858, 0, 480, 489, 495, 525, 0, 709 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 711 /* 4 - 1280x720@60Hz 16:9 */ 712 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 713 1430, 1650, 0, 720, 725, 730, 750, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 716 /* 5 - 1920x1080i@60Hz 16:9 */ 717 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 718 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 720 DRM_MODE_FLAG_INTERLACE), 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 722 /* 6 - 720(1440)x480i@60Hz 4:3 */ 723 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 724 801, 858, 0, 480, 488, 494, 525, 0, 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 726 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 7 - 720(1440)x480i@60Hz 16:9 */ 729 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 730 801, 858, 0, 480, 488, 494, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 732 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 8 - 720(1440)x240@60Hz 4:3 */ 735 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 736 801, 858, 0, 240, 244, 247, 262, 0, 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 738 DRM_MODE_FLAG_DBLCLK), 739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 740 /* 9 - 720(1440)x240@60Hz 16:9 */ 741 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 742 801, 858, 0, 240, 244, 247, 262, 0, 743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 744 DRM_MODE_FLAG_DBLCLK), 745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 10 - 2880x480i@60Hz 4:3 */ 747 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 748 3204, 3432, 0, 480, 488, 494, 525, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 750 DRM_MODE_FLAG_INTERLACE), 751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 752 /* 11 - 2880x480i@60Hz 16:9 */ 753 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 754 3204, 3432, 0, 480, 488, 494, 525, 0, 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 756 DRM_MODE_FLAG_INTERLACE), 757 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 12 - 2880x240@60Hz 4:3 */ 759 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 760 3204, 3432, 0, 240, 244, 247, 262, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 762 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 13 - 2880x240@60Hz 16:9 */ 764 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 765 3204, 3432, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 768 /* 14 - 1440x480@60Hz 4:3 */ 769 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 770 1596, 1716, 0, 480, 489, 495, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 772 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 773 /* 15 - 1440x480@60Hz 16:9 */ 774 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 775 1596, 1716, 0, 480, 489, 495, 525, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 777 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 16 - 1920x1080@60Hz 16:9 */ 779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 780 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 782 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 783 /* 17 - 720x576@50Hz 4:3 */ 784 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 785 796, 864, 0, 576, 581, 586, 625, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 787 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 788 /* 18 - 720x576@50Hz 16:9 */ 789 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 790 796, 864, 0, 576, 581, 586, 625, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 19 - 1280x720@50Hz 16:9 */ 794 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 795 1760, 1980, 0, 720, 725, 730, 750, 0, 796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 798 /* 20 - 1920x1080i@50Hz 16:9 */ 799 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 800 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 802 DRM_MODE_FLAG_INTERLACE), 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 804 /* 21 - 720(1440)x576i@50Hz 4:3 */ 805 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 806 795, 864, 0, 576, 580, 586, 625, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 808 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 22 - 720(1440)x576i@50Hz 16:9 */ 811 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 812 795, 864, 0, 576, 580, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 814 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 23 - 720(1440)x288@50Hz 4:3 */ 817 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 818 795, 864, 0, 288, 290, 293, 312, 0, 819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 820 DRM_MODE_FLAG_DBLCLK), 821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 822 /* 24 - 720(1440)x288@50Hz 16:9 */ 823 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 824 795, 864, 0, 288, 290, 293, 312, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 826 DRM_MODE_FLAG_DBLCLK), 827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 25 - 2880x576i@50Hz 4:3 */ 829 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 830 3180, 3456, 0, 576, 580, 586, 625, 0, 831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 832 DRM_MODE_FLAG_INTERLACE), 833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 834 /* 26 - 2880x576i@50Hz 16:9 */ 835 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 836 3180, 3456, 0, 576, 580, 586, 625, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 838 DRM_MODE_FLAG_INTERLACE), 839 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 27 - 2880x288@50Hz 4:3 */ 841 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 842 3180, 3456, 0, 288, 290, 293, 312, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 28 - 2880x288@50Hz 16:9 */ 846 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 847 3180, 3456, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 850 /* 29 - 1440x576@50Hz 4:3 */ 851 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 852 1592, 1728, 0, 576, 581, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 854 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 855 /* 30 - 1440x576@50Hz 16:9 */ 856 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 857 1592, 1728, 0, 576, 581, 586, 625, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 859 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 860 /* 31 - 1920x1080@50Hz 16:9 */ 861 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 862 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 32 - 1920x1080@24Hz 16:9 */ 866 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 867 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 869 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 33 - 1920x1080@25Hz 16:9 */ 871 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 872 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 874 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 34 - 1920x1080@30Hz 16:9 */ 876 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 877 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 879 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 880 /* 35 - 2880x480@60Hz 4:3 */ 881 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 882 3192, 3432, 0, 480, 489, 495, 525, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 885 /* 36 - 2880x480@60Hz 16:9 */ 886 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 887 3192, 3432, 0, 480, 489, 495, 525, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 890 /* 37 - 2880x576@50Hz 4:3 */ 891 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 892 3184, 3456, 0, 576, 581, 586, 625, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 895 /* 38 - 2880x576@50Hz 16:9 */ 896 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 897 3184, 3456, 0, 576, 581, 586, 625, 0, 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 899 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 39 - 1920x1080i@50Hz 16:9 */ 901 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 902 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 904 DRM_MODE_FLAG_INTERLACE), 905 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 40 - 1920x1080i@100Hz 16:9 */ 907 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 908 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 910 DRM_MODE_FLAG_INTERLACE), 911 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 41 - 1280x720@100Hz 16:9 */ 913 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 914 1760, 1980, 0, 720, 725, 730, 750, 0, 915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 916 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 917 /* 42 - 720x576@100Hz 4:3 */ 918 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 919 796, 864, 0, 576, 581, 586, 625, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 922 /* 43 - 720x576@100Hz 16:9 */ 923 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 924 796, 864, 0, 576, 581, 586, 625, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 926 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 927 /* 44 - 720(1440)x576i@100Hz 4:3 */ 928 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 929 795, 864, 0, 576, 580, 586, 625, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 931 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 932 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 933 /* 45 - 720(1440)x576i@100Hz 16:9 */ 934 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 935 795, 864, 0, 576, 580, 586, 625, 0, 936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 937 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 46 - 1920x1080i@120Hz 16:9 */ 940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 941 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 943 DRM_MODE_FLAG_INTERLACE), 944 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 945 /* 47 - 1280x720@120Hz 16:9 */ 946 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 947 1430, 1650, 0, 720, 725, 730, 750, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 949 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 48 - 720x480@120Hz 4:3 */ 951 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 952 798, 858, 0, 480, 489, 495, 525, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 954 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 955 /* 49 - 720x480@120Hz 16:9 */ 956 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 957 798, 858, 0, 480, 489, 495, 525, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 959 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 960 /* 50 - 720(1440)x480i@120Hz 4:3 */ 961 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 962 801, 858, 0, 480, 488, 494, 525, 0, 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 964 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 965 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 966 /* 51 - 720(1440)x480i@120Hz 16:9 */ 967 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 968 801, 858, 0, 480, 488, 494, 525, 0, 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 52 - 720x576@200Hz 4:3 */ 973 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 974 796, 864, 0, 576, 581, 586, 625, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 977 /* 53 - 720x576@200Hz 16:9 */ 978 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 979 796, 864, 0, 576, 581, 586, 625, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 981 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 54 - 720(1440)x576i@200Hz 4:3 */ 983 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 984 795, 864, 0, 576, 580, 586, 625, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 987 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 988 /* 55 - 720(1440)x576i@200Hz 16:9 */ 989 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 990 795, 864, 0, 576, 580, 586, 625, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 993 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 56 - 720x480@240Hz 4:3 */ 995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 996 798, 858, 0, 480, 489, 495, 525, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 999 /* 57 - 720x480@240Hz 16:9 */ 1000 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1001 798, 858, 0, 480, 489, 495, 525, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1003 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1005 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1006 801, 858, 0, 480, 488, 494, 525, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1009 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1010 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1011 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1012 801, 858, 0, 480, 488, 494, 525, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1015 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1016 /* 60 - 1280x720@24Hz 16:9 */ 1017 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1018 3080, 3300, 0, 720, 725, 730, 750, 0, 1019 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1020 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1021 /* 61 - 1280x720@25Hz 16:9 */ 1022 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1023 3740, 3960, 0, 720, 725, 730, 750, 0, 1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1025 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 62 - 1280x720@30Hz 16:9 */ 1027 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1028 3080, 3300, 0, 720, 725, 730, 750, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1030 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1031 /* 63 - 1920x1080@120Hz 16:9 */ 1032 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1033 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1034 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1035 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 64 - 1920x1080@100Hz 16:9 */ 1037 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1038 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1040 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1041 /* 65 - 1280x720@24Hz 64:27 */ 1042 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1043 3080, 3300, 0, 720, 725, 730, 750, 0, 1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1045 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1046 /* 66 - 1280x720@25Hz 64:27 */ 1047 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1048 3740, 3960, 0, 720, 725, 730, 750, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1050 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1051 /* 67 - 1280x720@30Hz 64:27 */ 1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1053 3080, 3300, 0, 720, 725, 730, 750, 0, 1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1055 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1056 /* 68 - 1280x720@50Hz 64:27 */ 1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1058 1760, 1980, 0, 720, 725, 730, 750, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1060 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1061 /* 69 - 1280x720@60Hz 64:27 */ 1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1063 1430, 1650, 0, 720, 725, 730, 750, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1066 /* 70 - 1280x720@100Hz 64:27 */ 1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1068 1760, 1980, 0, 720, 725, 730, 750, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1071 /* 71 - 1280x720@120Hz 64:27 */ 1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1073 1430, 1650, 0, 720, 725, 730, 750, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1076 /* 72 - 1920x1080@24Hz 64:27 */ 1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1078 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1081 /* 73 - 1920x1080@25Hz 64:27 */ 1082 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1083 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1086 /* 74 - 1920x1080@30Hz 64:27 */ 1087 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1088 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 75 - 1920x1080@50Hz 64:27 */ 1092 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1093 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 76 - 1920x1080@60Hz 64:27 */ 1097 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1098 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 77 - 1920x1080@100Hz 64:27 */ 1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1103 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 78 - 1920x1080@120Hz 64:27 */ 1107 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1108 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 79 - 1680x720@24Hz 64:27 */ 1112 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1113 3080, 3300, 0, 720, 725, 730, 750, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 80 - 1680x720@25Hz 64:27 */ 1117 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1118 2948, 3168, 0, 720, 725, 730, 750, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 81 - 1680x720@30Hz 64:27 */ 1122 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1123 2420, 2640, 0, 720, 725, 730, 750, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 82 - 1680x720@50Hz 64:27 */ 1127 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1128 1980, 2200, 0, 720, 725, 730, 750, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 83 - 1680x720@60Hz 64:27 */ 1132 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1133 1980, 2200, 0, 720, 725, 730, 750, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 84 - 1680x720@100Hz 64:27 */ 1137 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1138 1780, 2000, 0, 720, 725, 730, 825, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 85 - 1680x720@120Hz 64:27 */ 1142 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1143 1780, 2000, 0, 720, 725, 730, 825, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 86 - 2560x1080@24Hz 64:27 */ 1147 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1148 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 87 - 2560x1080@25Hz 64:27 */ 1152 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1153 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 88 - 2560x1080@30Hz 64:27 */ 1157 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1158 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 89 - 2560x1080@50Hz 64:27 */ 1162 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1163 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 90 - 2560x1080@60Hz 64:27 */ 1167 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1168 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 91 - 2560x1080@100Hz 64:27 */ 1172 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1173 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 92 - 2560x1080@120Hz 64:27 */ 1177 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1178 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 93 - 3840x2160@24Hz 16:9 */ 1182 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1183 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1186 /* 94 - 3840x2160@25Hz 16:9 */ 1187 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1188 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1191 /* 95 - 3840x2160@30Hz 16:9 */ 1192 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1193 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1196 /* 96 - 3840x2160@50Hz 16:9 */ 1197 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1198 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1201 /* 97 - 3840x2160@60Hz 16:9 */ 1202 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1203 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1206 /* 98 - 4096x2160@24Hz 256:135 */ 1207 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1208 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1211 /* 99 - 4096x2160@25Hz 256:135 */ 1212 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1213 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1216 /* 100 - 4096x2160@30Hz 256:135 */ 1217 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1218 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1221 /* 101 - 4096x2160@50Hz 256:135 */ 1222 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1223 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1226 /* 102 - 4096x2160@60Hz 256:135 */ 1227 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1228 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1231 /* 103 - 3840x2160@24Hz 64:27 */ 1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1233 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1236 /* 104 - 3840x2160@25Hz 64:27 */ 1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1238 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1241 /* 105 - 3840x2160@30Hz 64:27 */ 1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1243 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1246 /* 106 - 3840x2160@50Hz 64:27 */ 1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1248 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1251 /* 107 - 3840x2160@60Hz 64:27 */ 1252 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1253 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1256 }; 1257 1258 /* 1259 * HDMI 1.4 4k modes. Index using the VIC. 1260 */ 1261 static const struct drm_display_mode edid_4k_modes[] = { 1262 /* 0 - dummy, VICs start at 1 */ 1263 { }, 1264 /* 1 - 3840x2160@30Hz */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1266 3840, 4016, 4104, 4400, 0, 1267 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .vrefresh = 30, }, 1270 /* 2 - 3840x2160@25Hz */ 1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1272 3840, 4896, 4984, 5280, 0, 1273 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .vrefresh = 25, }, 1276 /* 3 - 3840x2160@24Hz */ 1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1278 3840, 5116, 5204, 5500, 0, 1279 2160, 2168, 2178, 2250, 0, 1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1281 .vrefresh = 24, }, 1282 /* 4 - 4096x2160@24Hz (SMPTE) */ 1283 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1284 4096, 5116, 5204, 5500, 0, 1285 2160, 2168, 2178, 2250, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .vrefresh = 24, }, 1288 }; 1289 1290 /*** DDC fetch and block validation ***/ 1291 1292 static const u8 edid_header[] = { 1293 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1294 }; 1295 1296 /** 1297 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1298 * @raw_edid: pointer to raw base EDID block 1299 * 1300 * Sanity check the header of the base EDID block. 1301 * 1302 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1303 */ 1304 int drm_edid_header_is_valid(const u8 *raw_edid) 1305 { 1306 int i, score = 0; 1307 1308 for (i = 0; i < sizeof(edid_header); i++) 1309 if (raw_edid[i] == edid_header[i]) 1310 score++; 1311 1312 return score; 1313 } 1314 EXPORT_SYMBOL(drm_edid_header_is_valid); 1315 1316 static int edid_fixup __read_mostly = 6; 1317 module_param_named(edid_fixup, edid_fixup, int, 0400); 1318 MODULE_PARM_DESC(edid_fixup, 1319 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1320 1321 static void drm_get_displayid(struct drm_connector *connector, 1322 struct edid *edid); 1323 1324 static int drm_edid_block_checksum(const u8 *raw_edid) 1325 { 1326 int i; 1327 u8 csum = 0; 1328 for (i = 0; i < EDID_LENGTH; i++) 1329 csum += raw_edid[i]; 1330 1331 return csum; 1332 } 1333 1334 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1335 { 1336 if (memchr_inv(in_edid, 0, length)) 1337 return false; 1338 1339 return true; 1340 } 1341 1342 /** 1343 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1344 * @raw_edid: pointer to raw EDID block 1345 * @block: type of block to validate (0 for base, extension otherwise) 1346 * @print_bad_edid: if true, dump bad EDID blocks to the console 1347 * @edid_corrupt: if true, the header or checksum is invalid 1348 * 1349 * Validate a base or extension EDID block and optionally dump bad blocks to 1350 * the console. 1351 * 1352 * Return: True if the block is valid, false otherwise. 1353 */ 1354 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1355 bool *edid_corrupt) 1356 { 1357 u8 csum; 1358 struct edid *edid = (struct edid *)raw_edid; 1359 1360 if (WARN_ON(!raw_edid)) 1361 return false; 1362 1363 if (edid_fixup > 8 || edid_fixup < 0) 1364 edid_fixup = 6; 1365 1366 if (block == 0) { 1367 int score = drm_edid_header_is_valid(raw_edid); 1368 if (score == 8) { 1369 if (edid_corrupt) 1370 *edid_corrupt = false; 1371 } else if (score >= edid_fixup) { 1372 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1373 * The corrupt flag needs to be set here otherwise, the 1374 * fix-up code here will correct the problem, the 1375 * checksum is correct and the test fails 1376 */ 1377 if (edid_corrupt) 1378 *edid_corrupt = true; 1379 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1380 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1381 } else { 1382 if (edid_corrupt) 1383 *edid_corrupt = true; 1384 goto bad; 1385 } 1386 } 1387 1388 csum = drm_edid_block_checksum(raw_edid); 1389 if (csum) { 1390 if (edid_corrupt) 1391 *edid_corrupt = true; 1392 1393 /* allow CEA to slide through, switches mangle this */ 1394 if (raw_edid[0] == CEA_EXT) { 1395 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1396 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1397 } else { 1398 if (print_bad_edid) 1399 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1400 1401 goto bad; 1402 } 1403 } 1404 1405 /* per-block-type checks */ 1406 switch (raw_edid[0]) { 1407 case 0: /* base */ 1408 if (edid->version != 1) { 1409 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1410 goto bad; 1411 } 1412 1413 if (edid->revision > 4) 1414 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1415 break; 1416 1417 default: 1418 break; 1419 } 1420 1421 return true; 1422 1423 bad: 1424 if (print_bad_edid) { 1425 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1426 pr_notice("EDID block is all zeroes\n"); 1427 } else { 1428 pr_notice("Raw EDID:\n"); 1429 print_hex_dump(KERN_NOTICE, 1430 " \t", DUMP_PREFIX_NONE, 16, 1, 1431 raw_edid, EDID_LENGTH, false); 1432 } 1433 } 1434 return false; 1435 } 1436 EXPORT_SYMBOL(drm_edid_block_valid); 1437 1438 /** 1439 * drm_edid_is_valid - sanity check EDID data 1440 * @edid: EDID data 1441 * 1442 * Sanity-check an entire EDID record (including extensions) 1443 * 1444 * Return: True if the EDID data is valid, false otherwise. 1445 */ 1446 bool drm_edid_is_valid(struct edid *edid) 1447 { 1448 int i; 1449 u8 *raw = (u8 *)edid; 1450 1451 if (!edid) 1452 return false; 1453 1454 for (i = 0; i <= edid->extensions; i++) 1455 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1456 return false; 1457 1458 return true; 1459 } 1460 EXPORT_SYMBOL(drm_edid_is_valid); 1461 1462 #define DDC_SEGMENT_ADDR 0x30 1463 /** 1464 * drm_do_probe_ddc_edid() - get EDID information via I2C 1465 * @data: I2C device adapter 1466 * @buf: EDID data buffer to be filled 1467 * @block: 128 byte EDID block to start fetching from 1468 * @len: EDID data buffer length to fetch 1469 * 1470 * Try to fetch EDID information by calling I2C driver functions. 1471 * 1472 * Return: 0 on success or -1 on failure. 1473 */ 1474 static int 1475 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1476 { 1477 struct i2c_adapter *adapter = data; 1478 unsigned char start = block * EDID_LENGTH; 1479 unsigned char segment = block >> 1; 1480 unsigned char xfers = segment ? 3 : 2; 1481 int ret, retries = 5; 1482 1483 /* 1484 * The core I2C driver will automatically retry the transfer if the 1485 * adapter reports EAGAIN. However, we find that bit-banging transfers 1486 * are susceptible to errors under a heavily loaded machine and 1487 * generate spurious NAKs and timeouts. Retrying the transfer 1488 * of the individual block a few times seems to overcome this. 1489 */ 1490 do { 1491 struct i2c_msg msgs[] = { 1492 { 1493 .addr = DDC_SEGMENT_ADDR, 1494 .flags = 0, 1495 .len = 1, 1496 .buf = &segment, 1497 }, { 1498 .addr = DDC_ADDR, 1499 .flags = 0, 1500 .len = 1, 1501 .buf = &start, 1502 }, { 1503 .addr = DDC_ADDR, 1504 .flags = I2C_M_RD, 1505 .len = len, 1506 .buf = buf, 1507 } 1508 }; 1509 1510 /* 1511 * Avoid sending the segment addr to not upset non-compliant 1512 * DDC monitors. 1513 */ 1514 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1515 1516 if (ret == -ENXIO) { 1517 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1518 adapter->name); 1519 break; 1520 } 1521 } while (ret != xfers && --retries); 1522 1523 return ret == xfers ? 0 : -1; 1524 } 1525 1526 static void connector_bad_edid(struct drm_connector *connector, 1527 u8 *edid, int num_blocks) 1528 { 1529 int i; 1530 1531 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1532 return; 1533 1534 dev_warn(connector->dev->dev, 1535 "%s: EDID is invalid:\n", 1536 connector->name); 1537 for (i = 0; i < num_blocks; i++) { 1538 u8 *block = edid + i * EDID_LENGTH; 1539 char prefix[20]; 1540 1541 if (drm_edid_is_zero(block, EDID_LENGTH)) 1542 sprintf(prefix, "\t[%02x] ZERO ", i); 1543 else if (!drm_edid_block_valid(block, i, false, NULL)) 1544 sprintf(prefix, "\t[%02x] BAD ", i); 1545 else 1546 sprintf(prefix, "\t[%02x] GOOD ", i); 1547 1548 print_hex_dump(KERN_WARNING, 1549 prefix, DUMP_PREFIX_NONE, 16, 1, 1550 block, EDID_LENGTH, false); 1551 } 1552 } 1553 1554 /** 1555 * drm_do_get_edid - get EDID data using a custom EDID block read function 1556 * @connector: connector we're probing 1557 * @get_edid_block: EDID block read function 1558 * @data: private data passed to the block read function 1559 * 1560 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1561 * exposes a different interface to read EDID blocks this function can be used 1562 * to get EDID data using a custom block read function. 1563 * 1564 * As in the general case the DDC bus is accessible by the kernel at the I2C 1565 * level, drivers must make all reasonable efforts to expose it as an I2C 1566 * adapter and use drm_get_edid() instead of abusing this function. 1567 * 1568 * The EDID may be overridden using debugfs override_edid or firmare EDID 1569 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1570 * order. Having either of them bypasses actual EDID reads. 1571 * 1572 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1573 */ 1574 struct edid *drm_do_get_edid(struct drm_connector *connector, 1575 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1576 size_t len), 1577 void *data) 1578 { 1579 int i, j = 0, valid_extensions = 0; 1580 u8 *edid, *new; 1581 struct edid *override = NULL; 1582 1583 if (connector->override_edid) 1584 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1585 1586 if (!override) 1587 override = drm_load_edid_firmware(connector); 1588 1589 if (!IS_ERR_OR_NULL(override)) 1590 return override; 1591 1592 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1593 return NULL; 1594 1595 /* base block fetch */ 1596 for (i = 0; i < 4; i++) { 1597 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1598 goto out; 1599 if (drm_edid_block_valid(edid, 0, false, 1600 &connector->edid_corrupt)) 1601 break; 1602 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1603 connector->null_edid_counter++; 1604 goto carp; 1605 } 1606 } 1607 if (i == 4) 1608 goto carp; 1609 1610 /* if there's no extensions, we're done */ 1611 valid_extensions = edid[0x7e]; 1612 if (valid_extensions == 0) 1613 return (struct edid *)edid; 1614 1615 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1616 if (!new) 1617 goto out; 1618 edid = new; 1619 1620 for (j = 1; j <= edid[0x7e]; j++) { 1621 u8 *block = edid + j * EDID_LENGTH; 1622 1623 for (i = 0; i < 4; i++) { 1624 if (get_edid_block(data, block, j, EDID_LENGTH)) 1625 goto out; 1626 if (drm_edid_block_valid(block, j, false, NULL)) 1627 break; 1628 } 1629 1630 if (i == 4) 1631 valid_extensions--; 1632 } 1633 1634 if (valid_extensions != edid[0x7e]) { 1635 u8 *base; 1636 1637 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1638 1639 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1640 edid[0x7e] = valid_extensions; 1641 1642 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1643 GFP_KERNEL); 1644 if (!new) 1645 goto out; 1646 1647 base = new; 1648 for (i = 0; i <= edid[0x7e]; i++) { 1649 u8 *block = edid + i * EDID_LENGTH; 1650 1651 if (!drm_edid_block_valid(block, i, false, NULL)) 1652 continue; 1653 1654 memcpy(base, block, EDID_LENGTH); 1655 base += EDID_LENGTH; 1656 } 1657 1658 kfree(edid); 1659 edid = new; 1660 } 1661 1662 return (struct edid *)edid; 1663 1664 carp: 1665 connector_bad_edid(connector, edid, 1); 1666 out: 1667 kfree(edid); 1668 return NULL; 1669 } 1670 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1671 1672 /** 1673 * drm_probe_ddc() - probe DDC presence 1674 * @adapter: I2C adapter to probe 1675 * 1676 * Return: True on success, false on failure. 1677 */ 1678 bool 1679 drm_probe_ddc(struct i2c_adapter *adapter) 1680 { 1681 unsigned char out; 1682 1683 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1684 } 1685 EXPORT_SYMBOL(drm_probe_ddc); 1686 1687 /** 1688 * drm_get_edid - get EDID data, if available 1689 * @connector: connector we're probing 1690 * @adapter: I2C adapter to use for DDC 1691 * 1692 * Poke the given I2C channel to grab EDID data if possible. If found, 1693 * attach it to the connector. 1694 * 1695 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1696 */ 1697 struct edid *drm_get_edid(struct drm_connector *connector, 1698 struct i2c_adapter *adapter) 1699 { 1700 struct edid *edid; 1701 1702 if (connector->force == DRM_FORCE_OFF) 1703 return NULL; 1704 1705 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1706 return NULL; 1707 1708 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1709 if (edid) 1710 drm_get_displayid(connector, edid); 1711 return edid; 1712 } 1713 EXPORT_SYMBOL(drm_get_edid); 1714 1715 /** 1716 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1717 * @connector: connector we're probing 1718 * @adapter: I2C adapter to use for DDC 1719 * 1720 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1721 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1722 * switch DDC to the GPU which is retrieving EDID. 1723 * 1724 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1725 */ 1726 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1727 struct i2c_adapter *adapter) 1728 { 1729 struct pci_dev *pdev = connector->dev->pdev; 1730 struct edid *edid; 1731 1732 vga_switcheroo_lock_ddc(pdev); 1733 edid = drm_get_edid(connector, adapter); 1734 vga_switcheroo_unlock_ddc(pdev); 1735 1736 return edid; 1737 } 1738 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1739 1740 /** 1741 * drm_edid_duplicate - duplicate an EDID and the extensions 1742 * @edid: EDID to duplicate 1743 * 1744 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1745 */ 1746 struct edid *drm_edid_duplicate(const struct edid *edid) 1747 { 1748 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1749 } 1750 EXPORT_SYMBOL(drm_edid_duplicate); 1751 1752 /*** EDID parsing ***/ 1753 1754 /** 1755 * edid_vendor - match a string against EDID's obfuscated vendor field 1756 * @edid: EDID to match 1757 * @vendor: vendor string 1758 * 1759 * Returns true if @vendor is in @edid, false otherwise 1760 */ 1761 static bool edid_vendor(const struct edid *edid, const char *vendor) 1762 { 1763 char edid_vendor[3]; 1764 1765 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1766 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1767 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1768 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1769 1770 return !strncmp(edid_vendor, vendor, 3); 1771 } 1772 1773 /** 1774 * edid_get_quirks - return quirk flags for a given EDID 1775 * @edid: EDID to process 1776 * 1777 * This tells subsequent routines what fixes they need to apply. 1778 */ 1779 static u32 edid_get_quirks(const struct edid *edid) 1780 { 1781 const struct edid_quirk *quirk; 1782 int i; 1783 1784 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1785 quirk = &edid_quirk_list[i]; 1786 1787 if (edid_vendor(edid, quirk->vendor) && 1788 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1789 return quirk->quirks; 1790 } 1791 1792 return 0; 1793 } 1794 1795 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1796 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1797 1798 /** 1799 * edid_fixup_preferred - set preferred modes based on quirk list 1800 * @connector: has mode list to fix up 1801 * @quirks: quirks list 1802 * 1803 * Walk the mode list for @connector, clearing the preferred status 1804 * on existing modes and setting it anew for the right mode ala @quirks. 1805 */ 1806 static void edid_fixup_preferred(struct drm_connector *connector, 1807 u32 quirks) 1808 { 1809 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1810 int target_refresh = 0; 1811 int cur_vrefresh, preferred_vrefresh; 1812 1813 if (list_empty(&connector->probed_modes)) 1814 return; 1815 1816 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1817 target_refresh = 60; 1818 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1819 target_refresh = 75; 1820 1821 preferred_mode = list_first_entry(&connector->probed_modes, 1822 struct drm_display_mode, head); 1823 1824 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1825 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1826 1827 if (cur_mode == preferred_mode) 1828 continue; 1829 1830 /* Largest mode is preferred */ 1831 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1832 preferred_mode = cur_mode; 1833 1834 cur_vrefresh = cur_mode->vrefresh ? 1835 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1836 preferred_vrefresh = preferred_mode->vrefresh ? 1837 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1838 /* At a given size, try to get closest to target refresh */ 1839 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1840 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1841 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1842 preferred_mode = cur_mode; 1843 } 1844 } 1845 1846 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1847 } 1848 1849 static bool 1850 mode_is_rb(const struct drm_display_mode *mode) 1851 { 1852 return (mode->htotal - mode->hdisplay == 160) && 1853 (mode->hsync_end - mode->hdisplay == 80) && 1854 (mode->hsync_end - mode->hsync_start == 32) && 1855 (mode->vsync_start - mode->vdisplay == 3); 1856 } 1857 1858 /* 1859 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1860 * @dev: Device to duplicate against 1861 * @hsize: Mode width 1862 * @vsize: Mode height 1863 * @fresh: Mode refresh rate 1864 * @rb: Mode reduced-blanking-ness 1865 * 1866 * Walk the DMT mode list looking for a match for the given parameters. 1867 * 1868 * Return: A newly allocated copy of the mode, or NULL if not found. 1869 */ 1870 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1871 int hsize, int vsize, int fresh, 1872 bool rb) 1873 { 1874 int i; 1875 1876 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1877 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1878 if (hsize != ptr->hdisplay) 1879 continue; 1880 if (vsize != ptr->vdisplay) 1881 continue; 1882 if (fresh != drm_mode_vrefresh(ptr)) 1883 continue; 1884 if (rb != mode_is_rb(ptr)) 1885 continue; 1886 1887 return drm_mode_duplicate(dev, ptr); 1888 } 1889 1890 return NULL; 1891 } 1892 EXPORT_SYMBOL(drm_mode_find_dmt); 1893 1894 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1895 1896 static void 1897 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1898 { 1899 int i, n = 0; 1900 u8 d = ext[0x02]; 1901 u8 *det_base = ext + d; 1902 1903 n = (127 - d) / 18; 1904 for (i = 0; i < n; i++) 1905 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1906 } 1907 1908 static void 1909 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1910 { 1911 unsigned int i, n = min((int)ext[0x02], 6); 1912 u8 *det_base = ext + 5; 1913 1914 if (ext[0x01] != 1) 1915 return; /* unknown version */ 1916 1917 for (i = 0; i < n; i++) 1918 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1919 } 1920 1921 static void 1922 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1923 { 1924 int i; 1925 struct edid *edid = (struct edid *)raw_edid; 1926 1927 if (edid == NULL) 1928 return; 1929 1930 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1931 cb(&(edid->detailed_timings[i]), closure); 1932 1933 for (i = 1; i <= raw_edid[0x7e]; i++) { 1934 u8 *ext = raw_edid + (i * EDID_LENGTH); 1935 switch (*ext) { 1936 case CEA_EXT: 1937 cea_for_each_detailed_block(ext, cb, closure); 1938 break; 1939 case VTB_EXT: 1940 vtb_for_each_detailed_block(ext, cb, closure); 1941 break; 1942 default: 1943 break; 1944 } 1945 } 1946 } 1947 1948 static void 1949 is_rb(struct detailed_timing *t, void *data) 1950 { 1951 u8 *r = (u8 *)t; 1952 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1953 if (r[15] & 0x10) 1954 *(bool *)data = true; 1955 } 1956 1957 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1958 static bool 1959 drm_monitor_supports_rb(struct edid *edid) 1960 { 1961 if (edid->revision >= 4) { 1962 bool ret = false; 1963 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1964 return ret; 1965 } 1966 1967 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1968 } 1969 1970 static void 1971 find_gtf2(struct detailed_timing *t, void *data) 1972 { 1973 u8 *r = (u8 *)t; 1974 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1975 *(u8 **)data = r; 1976 } 1977 1978 /* Secondary GTF curve kicks in above some break frequency */ 1979 static int 1980 drm_gtf2_hbreak(struct edid *edid) 1981 { 1982 u8 *r = NULL; 1983 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1984 return r ? (r[12] * 2) : 0; 1985 } 1986 1987 static int 1988 drm_gtf2_2c(struct edid *edid) 1989 { 1990 u8 *r = NULL; 1991 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1992 return r ? r[13] : 0; 1993 } 1994 1995 static int 1996 drm_gtf2_m(struct edid *edid) 1997 { 1998 u8 *r = NULL; 1999 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2000 return r ? (r[15] << 8) + r[14] : 0; 2001 } 2002 2003 static int 2004 drm_gtf2_k(struct edid *edid) 2005 { 2006 u8 *r = NULL; 2007 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2008 return r ? r[16] : 0; 2009 } 2010 2011 static int 2012 drm_gtf2_2j(struct edid *edid) 2013 { 2014 u8 *r = NULL; 2015 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2016 return r ? r[17] : 0; 2017 } 2018 2019 /** 2020 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2021 * @edid: EDID block to scan 2022 */ 2023 static int standard_timing_level(struct edid *edid) 2024 { 2025 if (edid->revision >= 2) { 2026 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2027 return LEVEL_CVT; 2028 if (drm_gtf2_hbreak(edid)) 2029 return LEVEL_GTF2; 2030 return LEVEL_GTF; 2031 } 2032 return LEVEL_DMT; 2033 } 2034 2035 /* 2036 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2037 * monitors fill with ascii space (0x20) instead. 2038 */ 2039 static int 2040 bad_std_timing(u8 a, u8 b) 2041 { 2042 return (a == 0x00 && b == 0x00) || 2043 (a == 0x01 && b == 0x01) || 2044 (a == 0x20 && b == 0x20); 2045 } 2046 2047 /** 2048 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2049 * @connector: connector of for the EDID block 2050 * @edid: EDID block to scan 2051 * @t: standard timing params 2052 * 2053 * Take the standard timing params (in this case width, aspect, and refresh) 2054 * and convert them into a real mode using CVT/GTF/DMT. 2055 */ 2056 static struct drm_display_mode * 2057 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2058 struct std_timing *t) 2059 { 2060 struct drm_device *dev = connector->dev; 2061 struct drm_display_mode *m, *mode = NULL; 2062 int hsize, vsize; 2063 int vrefresh_rate; 2064 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2065 >> EDID_TIMING_ASPECT_SHIFT; 2066 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2067 >> EDID_TIMING_VFREQ_SHIFT; 2068 int timing_level = standard_timing_level(edid); 2069 2070 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2071 return NULL; 2072 2073 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2074 hsize = t->hsize * 8 + 248; 2075 /* vrefresh_rate = vfreq + 60 */ 2076 vrefresh_rate = vfreq + 60; 2077 /* the vdisplay is calculated based on the aspect ratio */ 2078 if (aspect_ratio == 0) { 2079 if (edid->revision < 3) 2080 vsize = hsize; 2081 else 2082 vsize = (hsize * 10) / 16; 2083 } else if (aspect_ratio == 1) 2084 vsize = (hsize * 3) / 4; 2085 else if (aspect_ratio == 2) 2086 vsize = (hsize * 4) / 5; 2087 else 2088 vsize = (hsize * 9) / 16; 2089 2090 /* HDTV hack, part 1 */ 2091 if (vrefresh_rate == 60 && 2092 ((hsize == 1360 && vsize == 765) || 2093 (hsize == 1368 && vsize == 769))) { 2094 hsize = 1366; 2095 vsize = 768; 2096 } 2097 2098 /* 2099 * If this connector already has a mode for this size and refresh 2100 * rate (because it came from detailed or CVT info), use that 2101 * instead. This way we don't have to guess at interlace or 2102 * reduced blanking. 2103 */ 2104 list_for_each_entry(m, &connector->probed_modes, head) 2105 if (m->hdisplay == hsize && m->vdisplay == vsize && 2106 drm_mode_vrefresh(m) == vrefresh_rate) 2107 return NULL; 2108 2109 /* HDTV hack, part 2 */ 2110 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2111 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2112 false); 2113 if (!mode) 2114 return NULL; 2115 mode->hdisplay = 1366; 2116 mode->hsync_start = mode->hsync_start - 1; 2117 mode->hsync_end = mode->hsync_end - 1; 2118 return mode; 2119 } 2120 2121 /* check whether it can be found in default mode table */ 2122 if (drm_monitor_supports_rb(edid)) { 2123 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2124 true); 2125 if (mode) 2126 return mode; 2127 } 2128 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2129 if (mode) 2130 return mode; 2131 2132 /* okay, generate it */ 2133 switch (timing_level) { 2134 case LEVEL_DMT: 2135 break; 2136 case LEVEL_GTF: 2137 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2138 break; 2139 case LEVEL_GTF2: 2140 /* 2141 * This is potentially wrong if there's ever a monitor with 2142 * more than one ranges section, each claiming a different 2143 * secondary GTF curve. Please don't do that. 2144 */ 2145 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2146 if (!mode) 2147 return NULL; 2148 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2149 drm_mode_destroy(dev, mode); 2150 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2151 vrefresh_rate, 0, 0, 2152 drm_gtf2_m(edid), 2153 drm_gtf2_2c(edid), 2154 drm_gtf2_k(edid), 2155 drm_gtf2_2j(edid)); 2156 } 2157 break; 2158 case LEVEL_CVT: 2159 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2160 false); 2161 break; 2162 } 2163 return mode; 2164 } 2165 2166 /* 2167 * EDID is delightfully ambiguous about how interlaced modes are to be 2168 * encoded. Our internal representation is of frame height, but some 2169 * HDTV detailed timings are encoded as field height. 2170 * 2171 * The format list here is from CEA, in frame size. Technically we 2172 * should be checking refresh rate too. Whatever. 2173 */ 2174 static void 2175 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2176 struct detailed_pixel_timing *pt) 2177 { 2178 int i; 2179 static const struct { 2180 int w, h; 2181 } cea_interlaced[] = { 2182 { 1920, 1080 }, 2183 { 720, 480 }, 2184 { 1440, 480 }, 2185 { 2880, 480 }, 2186 { 720, 576 }, 2187 { 1440, 576 }, 2188 { 2880, 576 }, 2189 }; 2190 2191 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2192 return; 2193 2194 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2195 if ((mode->hdisplay == cea_interlaced[i].w) && 2196 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2197 mode->vdisplay *= 2; 2198 mode->vsync_start *= 2; 2199 mode->vsync_end *= 2; 2200 mode->vtotal *= 2; 2201 mode->vtotal |= 1; 2202 } 2203 } 2204 2205 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2206 } 2207 2208 /** 2209 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2210 * @dev: DRM device (needed to create new mode) 2211 * @edid: EDID block 2212 * @timing: EDID detailed timing info 2213 * @quirks: quirks to apply 2214 * 2215 * An EDID detailed timing block contains enough info for us to create and 2216 * return a new struct drm_display_mode. 2217 */ 2218 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2219 struct edid *edid, 2220 struct detailed_timing *timing, 2221 u32 quirks) 2222 { 2223 struct drm_display_mode *mode; 2224 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2225 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2226 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2227 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2228 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2229 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2230 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2231 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2232 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2233 2234 /* ignore tiny modes */ 2235 if (hactive < 64 || vactive < 64) 2236 return NULL; 2237 2238 if (pt->misc & DRM_EDID_PT_STEREO) { 2239 DRM_DEBUG_KMS("stereo mode not supported\n"); 2240 return NULL; 2241 } 2242 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2243 DRM_DEBUG_KMS("composite sync not supported\n"); 2244 } 2245 2246 /* it is incorrect if hsync/vsync width is zero */ 2247 if (!hsync_pulse_width || !vsync_pulse_width) { 2248 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2249 "Wrong Hsync/Vsync pulse width\n"); 2250 return NULL; 2251 } 2252 2253 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2254 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2255 if (!mode) 2256 return NULL; 2257 2258 goto set_size; 2259 } 2260 2261 mode = drm_mode_create(dev); 2262 if (!mode) 2263 return NULL; 2264 2265 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2266 timing->pixel_clock = cpu_to_le16(1088); 2267 2268 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2269 2270 mode->hdisplay = hactive; 2271 mode->hsync_start = mode->hdisplay + hsync_offset; 2272 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2273 mode->htotal = mode->hdisplay + hblank; 2274 2275 mode->vdisplay = vactive; 2276 mode->vsync_start = mode->vdisplay + vsync_offset; 2277 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2278 mode->vtotal = mode->vdisplay + vblank; 2279 2280 /* Some EDIDs have bogus h/vtotal values */ 2281 if (mode->hsync_end > mode->htotal) 2282 mode->htotal = mode->hsync_end + 1; 2283 if (mode->vsync_end > mode->vtotal) 2284 mode->vtotal = mode->vsync_end + 1; 2285 2286 drm_mode_do_interlace_quirk(mode, pt); 2287 2288 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2289 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2290 } 2291 2292 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2293 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2294 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2295 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2296 2297 set_size: 2298 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2299 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2300 2301 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2302 mode->width_mm *= 10; 2303 mode->height_mm *= 10; 2304 } 2305 2306 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2307 mode->width_mm = edid->width_cm * 10; 2308 mode->height_mm = edid->height_cm * 10; 2309 } 2310 2311 mode->type = DRM_MODE_TYPE_DRIVER; 2312 mode->vrefresh = drm_mode_vrefresh(mode); 2313 drm_mode_set_name(mode); 2314 2315 return mode; 2316 } 2317 2318 static bool 2319 mode_in_hsync_range(const struct drm_display_mode *mode, 2320 struct edid *edid, u8 *t) 2321 { 2322 int hsync, hmin, hmax; 2323 2324 hmin = t[7]; 2325 if (edid->revision >= 4) 2326 hmin += ((t[4] & 0x04) ? 255 : 0); 2327 hmax = t[8]; 2328 if (edid->revision >= 4) 2329 hmax += ((t[4] & 0x08) ? 255 : 0); 2330 hsync = drm_mode_hsync(mode); 2331 2332 return (hsync <= hmax && hsync >= hmin); 2333 } 2334 2335 static bool 2336 mode_in_vsync_range(const struct drm_display_mode *mode, 2337 struct edid *edid, u8 *t) 2338 { 2339 int vsync, vmin, vmax; 2340 2341 vmin = t[5]; 2342 if (edid->revision >= 4) 2343 vmin += ((t[4] & 0x01) ? 255 : 0); 2344 vmax = t[6]; 2345 if (edid->revision >= 4) 2346 vmax += ((t[4] & 0x02) ? 255 : 0); 2347 vsync = drm_mode_vrefresh(mode); 2348 2349 return (vsync <= vmax && vsync >= vmin); 2350 } 2351 2352 static u32 2353 range_pixel_clock(struct edid *edid, u8 *t) 2354 { 2355 /* unspecified */ 2356 if (t[9] == 0 || t[9] == 255) 2357 return 0; 2358 2359 /* 1.4 with CVT support gives us real precision, yay */ 2360 if (edid->revision >= 4 && t[10] == 0x04) 2361 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2362 2363 /* 1.3 is pathetic, so fuzz up a bit */ 2364 return t[9] * 10000 + 5001; 2365 } 2366 2367 static bool 2368 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2369 struct detailed_timing *timing) 2370 { 2371 u32 max_clock; 2372 u8 *t = (u8 *)timing; 2373 2374 if (!mode_in_hsync_range(mode, edid, t)) 2375 return false; 2376 2377 if (!mode_in_vsync_range(mode, edid, t)) 2378 return false; 2379 2380 if ((max_clock = range_pixel_clock(edid, t))) 2381 if (mode->clock > max_clock) 2382 return false; 2383 2384 /* 1.4 max horizontal check */ 2385 if (edid->revision >= 4 && t[10] == 0x04) 2386 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2387 return false; 2388 2389 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2390 return false; 2391 2392 return true; 2393 } 2394 2395 static bool valid_inferred_mode(const struct drm_connector *connector, 2396 const struct drm_display_mode *mode) 2397 { 2398 const struct drm_display_mode *m; 2399 bool ok = false; 2400 2401 list_for_each_entry(m, &connector->probed_modes, head) { 2402 if (mode->hdisplay == m->hdisplay && 2403 mode->vdisplay == m->vdisplay && 2404 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2405 return false; /* duplicated */ 2406 if (mode->hdisplay <= m->hdisplay && 2407 mode->vdisplay <= m->vdisplay) 2408 ok = true; 2409 } 2410 return ok; 2411 } 2412 2413 static int 2414 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2415 struct detailed_timing *timing) 2416 { 2417 int i, modes = 0; 2418 struct drm_display_mode *newmode; 2419 struct drm_device *dev = connector->dev; 2420 2421 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2422 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2423 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2424 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2425 if (newmode) { 2426 drm_mode_probed_add(connector, newmode); 2427 modes++; 2428 } 2429 } 2430 } 2431 2432 return modes; 2433 } 2434 2435 /* fix up 1366x768 mode from 1368x768; 2436 * GFT/CVT can't express 1366 width which isn't dividable by 8 2437 */ 2438 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2439 { 2440 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2441 mode->hdisplay = 1366; 2442 mode->hsync_start--; 2443 mode->hsync_end--; 2444 drm_mode_set_name(mode); 2445 } 2446 } 2447 2448 static int 2449 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2450 struct detailed_timing *timing) 2451 { 2452 int i, modes = 0; 2453 struct drm_display_mode *newmode; 2454 struct drm_device *dev = connector->dev; 2455 2456 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2457 const struct minimode *m = &extra_modes[i]; 2458 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2459 if (!newmode) 2460 return modes; 2461 2462 drm_mode_fixup_1366x768(newmode); 2463 if (!mode_in_range(newmode, edid, timing) || 2464 !valid_inferred_mode(connector, newmode)) { 2465 drm_mode_destroy(dev, newmode); 2466 continue; 2467 } 2468 2469 drm_mode_probed_add(connector, newmode); 2470 modes++; 2471 } 2472 2473 return modes; 2474 } 2475 2476 static int 2477 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2478 struct detailed_timing *timing) 2479 { 2480 int i, modes = 0; 2481 struct drm_display_mode *newmode; 2482 struct drm_device *dev = connector->dev; 2483 bool rb = drm_monitor_supports_rb(edid); 2484 2485 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2486 const struct minimode *m = &extra_modes[i]; 2487 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2488 if (!newmode) 2489 return modes; 2490 2491 drm_mode_fixup_1366x768(newmode); 2492 if (!mode_in_range(newmode, edid, timing) || 2493 !valid_inferred_mode(connector, newmode)) { 2494 drm_mode_destroy(dev, newmode); 2495 continue; 2496 } 2497 2498 drm_mode_probed_add(connector, newmode); 2499 modes++; 2500 } 2501 2502 return modes; 2503 } 2504 2505 static void 2506 do_inferred_modes(struct detailed_timing *timing, void *c) 2507 { 2508 struct detailed_mode_closure *closure = c; 2509 struct detailed_non_pixel *data = &timing->data.other_data; 2510 struct detailed_data_monitor_range *range = &data->data.range; 2511 2512 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2513 return; 2514 2515 closure->modes += drm_dmt_modes_for_range(closure->connector, 2516 closure->edid, 2517 timing); 2518 2519 if (!version_greater(closure->edid, 1, 1)) 2520 return; /* GTF not defined yet */ 2521 2522 switch (range->flags) { 2523 case 0x02: /* secondary gtf, XXX could do more */ 2524 case 0x00: /* default gtf */ 2525 closure->modes += drm_gtf_modes_for_range(closure->connector, 2526 closure->edid, 2527 timing); 2528 break; 2529 case 0x04: /* cvt, only in 1.4+ */ 2530 if (!version_greater(closure->edid, 1, 3)) 2531 break; 2532 2533 closure->modes += drm_cvt_modes_for_range(closure->connector, 2534 closure->edid, 2535 timing); 2536 break; 2537 case 0x01: /* just the ranges, no formula */ 2538 default: 2539 break; 2540 } 2541 } 2542 2543 static int 2544 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2545 { 2546 struct detailed_mode_closure closure = { 2547 .connector = connector, 2548 .edid = edid, 2549 }; 2550 2551 if (version_greater(edid, 1, 0)) 2552 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2553 &closure); 2554 2555 return closure.modes; 2556 } 2557 2558 static int 2559 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2560 { 2561 int i, j, m, modes = 0; 2562 struct drm_display_mode *mode; 2563 u8 *est = ((u8 *)timing) + 6; 2564 2565 for (i = 0; i < 6; i++) { 2566 for (j = 7; j >= 0; j--) { 2567 m = (i * 8) + (7 - j); 2568 if (m >= ARRAY_SIZE(est3_modes)) 2569 break; 2570 if (est[i] & (1 << j)) { 2571 mode = drm_mode_find_dmt(connector->dev, 2572 est3_modes[m].w, 2573 est3_modes[m].h, 2574 est3_modes[m].r, 2575 est3_modes[m].rb); 2576 if (mode) { 2577 drm_mode_probed_add(connector, mode); 2578 modes++; 2579 } 2580 } 2581 } 2582 } 2583 2584 return modes; 2585 } 2586 2587 static void 2588 do_established_modes(struct detailed_timing *timing, void *c) 2589 { 2590 struct detailed_mode_closure *closure = c; 2591 struct detailed_non_pixel *data = &timing->data.other_data; 2592 2593 if (data->type == EDID_DETAIL_EST_TIMINGS) 2594 closure->modes += drm_est3_modes(closure->connector, timing); 2595 } 2596 2597 /** 2598 * add_established_modes - get est. modes from EDID and add them 2599 * @connector: connector to add mode(s) to 2600 * @edid: EDID block to scan 2601 * 2602 * Each EDID block contains a bitmap of the supported "established modes" list 2603 * (defined above). Tease them out and add them to the global modes list. 2604 */ 2605 static int 2606 add_established_modes(struct drm_connector *connector, struct edid *edid) 2607 { 2608 struct drm_device *dev = connector->dev; 2609 unsigned long est_bits = edid->established_timings.t1 | 2610 (edid->established_timings.t2 << 8) | 2611 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2612 int i, modes = 0; 2613 struct detailed_mode_closure closure = { 2614 .connector = connector, 2615 .edid = edid, 2616 }; 2617 2618 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2619 if (est_bits & (1<<i)) { 2620 struct drm_display_mode *newmode; 2621 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2622 if (newmode) { 2623 drm_mode_probed_add(connector, newmode); 2624 modes++; 2625 } 2626 } 2627 } 2628 2629 if (version_greater(edid, 1, 0)) 2630 drm_for_each_detailed_block((u8 *)edid, 2631 do_established_modes, &closure); 2632 2633 return modes + closure.modes; 2634 } 2635 2636 static void 2637 do_standard_modes(struct detailed_timing *timing, void *c) 2638 { 2639 struct detailed_mode_closure *closure = c; 2640 struct detailed_non_pixel *data = &timing->data.other_data; 2641 struct drm_connector *connector = closure->connector; 2642 struct edid *edid = closure->edid; 2643 2644 if (data->type == EDID_DETAIL_STD_MODES) { 2645 int i; 2646 for (i = 0; i < 6; i++) { 2647 struct std_timing *std; 2648 struct drm_display_mode *newmode; 2649 2650 std = &data->data.timings[i]; 2651 newmode = drm_mode_std(connector, edid, std); 2652 if (newmode) { 2653 drm_mode_probed_add(connector, newmode); 2654 closure->modes++; 2655 } 2656 } 2657 } 2658 } 2659 2660 /** 2661 * add_standard_modes - get std. modes from EDID and add them 2662 * @connector: connector to add mode(s) to 2663 * @edid: EDID block to scan 2664 * 2665 * Standard modes can be calculated using the appropriate standard (DMT, 2666 * GTF or CVT. Grab them from @edid and add them to the list. 2667 */ 2668 static int 2669 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2670 { 2671 int i, modes = 0; 2672 struct detailed_mode_closure closure = { 2673 .connector = connector, 2674 .edid = edid, 2675 }; 2676 2677 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2678 struct drm_display_mode *newmode; 2679 2680 newmode = drm_mode_std(connector, edid, 2681 &edid->standard_timings[i]); 2682 if (newmode) { 2683 drm_mode_probed_add(connector, newmode); 2684 modes++; 2685 } 2686 } 2687 2688 if (version_greater(edid, 1, 0)) 2689 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2690 &closure); 2691 2692 /* XXX should also look for standard codes in VTB blocks */ 2693 2694 return modes + closure.modes; 2695 } 2696 2697 static int drm_cvt_modes(struct drm_connector *connector, 2698 struct detailed_timing *timing) 2699 { 2700 int i, j, modes = 0; 2701 struct drm_display_mode *newmode; 2702 struct drm_device *dev = connector->dev; 2703 struct cvt_timing *cvt; 2704 const int rates[] = { 60, 85, 75, 60, 50 }; 2705 const u8 empty[3] = { 0, 0, 0 }; 2706 2707 for (i = 0; i < 4; i++) { 2708 int uninitialized_var(width), height; 2709 cvt = &(timing->data.other_data.data.cvt[i]); 2710 2711 if (!memcmp(cvt->code, empty, 3)) 2712 continue; 2713 2714 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2715 switch (cvt->code[1] & 0x0c) { 2716 case 0x00: 2717 width = height * 4 / 3; 2718 break; 2719 case 0x04: 2720 width = height * 16 / 9; 2721 break; 2722 case 0x08: 2723 width = height * 16 / 10; 2724 break; 2725 case 0x0c: 2726 width = height * 15 / 9; 2727 break; 2728 } 2729 2730 for (j = 1; j < 5; j++) { 2731 if (cvt->code[2] & (1 << j)) { 2732 newmode = drm_cvt_mode(dev, width, height, 2733 rates[j], j == 0, 2734 false, false); 2735 if (newmode) { 2736 drm_mode_probed_add(connector, newmode); 2737 modes++; 2738 } 2739 } 2740 } 2741 } 2742 2743 return modes; 2744 } 2745 2746 static void 2747 do_cvt_mode(struct detailed_timing *timing, void *c) 2748 { 2749 struct detailed_mode_closure *closure = c; 2750 struct detailed_non_pixel *data = &timing->data.other_data; 2751 2752 if (data->type == EDID_DETAIL_CVT_3BYTE) 2753 closure->modes += drm_cvt_modes(closure->connector, timing); 2754 } 2755 2756 static int 2757 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2758 { 2759 struct detailed_mode_closure closure = { 2760 .connector = connector, 2761 .edid = edid, 2762 }; 2763 2764 if (version_greater(edid, 1, 2)) 2765 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2766 2767 /* XXX should also look for CVT codes in VTB blocks */ 2768 2769 return closure.modes; 2770 } 2771 2772 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2773 2774 static void 2775 do_detailed_mode(struct detailed_timing *timing, void *c) 2776 { 2777 struct detailed_mode_closure *closure = c; 2778 struct drm_display_mode *newmode; 2779 2780 if (timing->pixel_clock) { 2781 newmode = drm_mode_detailed(closure->connector->dev, 2782 closure->edid, timing, 2783 closure->quirks); 2784 if (!newmode) 2785 return; 2786 2787 if (closure->preferred) 2788 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2789 2790 /* 2791 * Detailed modes are limited to 10kHz pixel clock resolution, 2792 * so fix up anything that looks like CEA/HDMI mode, but the clock 2793 * is just slightly off. 2794 */ 2795 fixup_detailed_cea_mode_clock(newmode); 2796 2797 drm_mode_probed_add(closure->connector, newmode); 2798 closure->modes++; 2799 closure->preferred = false; 2800 } 2801 } 2802 2803 /* 2804 * add_detailed_modes - Add modes from detailed timings 2805 * @connector: attached connector 2806 * @edid: EDID block to scan 2807 * @quirks: quirks to apply 2808 */ 2809 static int 2810 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2811 u32 quirks) 2812 { 2813 struct detailed_mode_closure closure = { 2814 .connector = connector, 2815 .edid = edid, 2816 .preferred = true, 2817 .quirks = quirks, 2818 }; 2819 2820 if (closure.preferred && !version_greater(edid, 1, 3)) 2821 closure.preferred = 2822 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2823 2824 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2825 2826 return closure.modes; 2827 } 2828 2829 #define AUDIO_BLOCK 0x01 2830 #define VIDEO_BLOCK 0x02 2831 #define VENDOR_BLOCK 0x03 2832 #define SPEAKER_BLOCK 0x04 2833 #define USE_EXTENDED_TAG 0x07 2834 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 2835 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 2836 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 2837 #define EDID_BASIC_AUDIO (1 << 6) 2838 #define EDID_CEA_YCRCB444 (1 << 5) 2839 #define EDID_CEA_YCRCB422 (1 << 4) 2840 #define EDID_CEA_VCDB_QS (1 << 6) 2841 2842 /* 2843 * Search EDID for CEA extension block. 2844 */ 2845 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 2846 { 2847 u8 *edid_ext = NULL; 2848 int i; 2849 2850 /* No EDID or EDID extensions */ 2851 if (edid == NULL || edid->extensions == 0) 2852 return NULL; 2853 2854 /* Find CEA extension */ 2855 for (i = 0; i < edid->extensions; i++) { 2856 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2857 if (edid_ext[0] == ext_id) 2858 break; 2859 } 2860 2861 if (i == edid->extensions) 2862 return NULL; 2863 2864 return edid_ext; 2865 } 2866 2867 static u8 *drm_find_cea_extension(const struct edid *edid) 2868 { 2869 return drm_find_edid_extension(edid, CEA_EXT); 2870 } 2871 2872 static u8 *drm_find_displayid_extension(const struct edid *edid) 2873 { 2874 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2875 } 2876 2877 /* 2878 * Calculate the alternate clock for the CEA mode 2879 * (60Hz vs. 59.94Hz etc.) 2880 */ 2881 static unsigned int 2882 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2883 { 2884 unsigned int clock = cea_mode->clock; 2885 2886 if (cea_mode->vrefresh % 6 != 0) 2887 return clock; 2888 2889 /* 2890 * edid_cea_modes contains the 59.94Hz 2891 * variant for 240 and 480 line modes, 2892 * and the 60Hz variant otherwise. 2893 */ 2894 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2895 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2896 else 2897 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2898 2899 return clock; 2900 } 2901 2902 static bool 2903 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2904 { 2905 /* 2906 * For certain VICs the spec allows the vertical 2907 * front porch to vary by one or two lines. 2908 * 2909 * cea_modes[] stores the variant with the shortest 2910 * vertical front porch. We can adjust the mode to 2911 * get the other variants by simply increasing the 2912 * vertical front porch length. 2913 */ 2914 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2915 edid_cea_modes[9].vtotal != 262 || 2916 edid_cea_modes[12].vtotal != 262 || 2917 edid_cea_modes[13].vtotal != 262 || 2918 edid_cea_modes[23].vtotal != 312 || 2919 edid_cea_modes[24].vtotal != 312 || 2920 edid_cea_modes[27].vtotal != 312 || 2921 edid_cea_modes[28].vtotal != 312); 2922 2923 if (((vic == 8 || vic == 9 || 2924 vic == 12 || vic == 13) && mode->vtotal < 263) || 2925 ((vic == 23 || vic == 24 || 2926 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2927 mode->vsync_start++; 2928 mode->vsync_end++; 2929 mode->vtotal++; 2930 2931 return true; 2932 } 2933 2934 return false; 2935 } 2936 2937 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2938 unsigned int clock_tolerance) 2939 { 2940 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2941 u8 vic; 2942 2943 if (!to_match->clock) 2944 return 0; 2945 2946 if (to_match->picture_aspect_ratio) 2947 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2948 2949 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2950 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2951 unsigned int clock1, clock2; 2952 2953 /* Check both 60Hz and 59.94Hz */ 2954 clock1 = cea_mode.clock; 2955 clock2 = cea_mode_alternate_clock(&cea_mode); 2956 2957 if (abs(to_match->clock - clock1) > clock_tolerance && 2958 abs(to_match->clock - clock2) > clock_tolerance) 2959 continue; 2960 2961 do { 2962 if (drm_mode_match(to_match, &cea_mode, match_flags)) 2963 return vic; 2964 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2965 } 2966 2967 return 0; 2968 } 2969 2970 /** 2971 * drm_match_cea_mode - look for a CEA mode matching given mode 2972 * @to_match: display mode 2973 * 2974 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2975 * mode. 2976 */ 2977 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2978 { 2979 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 2980 u8 vic; 2981 2982 if (!to_match->clock) 2983 return 0; 2984 2985 if (to_match->picture_aspect_ratio) 2986 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 2987 2988 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2989 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2990 unsigned int clock1, clock2; 2991 2992 /* Check both 60Hz and 59.94Hz */ 2993 clock1 = cea_mode.clock; 2994 clock2 = cea_mode_alternate_clock(&cea_mode); 2995 2996 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 2997 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 2998 continue; 2999 3000 do { 3001 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3002 return vic; 3003 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3004 } 3005 3006 return 0; 3007 } 3008 EXPORT_SYMBOL(drm_match_cea_mode); 3009 3010 static bool drm_valid_cea_vic(u8 vic) 3011 { 3012 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 3013 } 3014 3015 /** 3016 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 3017 * the input VIC from the CEA mode list 3018 * @video_code: ID given to each of the CEA modes 3019 * 3020 * Returns picture aspect ratio 3021 */ 3022 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3023 { 3024 return edid_cea_modes[video_code].picture_aspect_ratio; 3025 } 3026 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 3027 3028 /* 3029 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3030 * specific block). 3031 * 3032 * It's almost like cea_mode_alternate_clock(), we just need to add an 3033 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 3034 * one. 3035 */ 3036 static unsigned int 3037 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3038 { 3039 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3040 return hdmi_mode->clock; 3041 3042 return cea_mode_alternate_clock(hdmi_mode); 3043 } 3044 3045 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3046 unsigned int clock_tolerance) 3047 { 3048 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3049 u8 vic; 3050 3051 if (!to_match->clock) 3052 return 0; 3053 3054 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3055 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3056 unsigned int clock1, clock2; 3057 3058 /* Make sure to also match alternate clocks */ 3059 clock1 = hdmi_mode->clock; 3060 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3061 3062 if (abs(to_match->clock - clock1) > clock_tolerance && 3063 abs(to_match->clock - clock2) > clock_tolerance) 3064 continue; 3065 3066 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3067 return vic; 3068 } 3069 3070 return 0; 3071 } 3072 3073 /* 3074 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3075 * @to_match: display mode 3076 * 3077 * An HDMI mode is one defined in the HDMI vendor specific block. 3078 * 3079 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3080 */ 3081 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3082 { 3083 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3084 u8 vic; 3085 3086 if (!to_match->clock) 3087 return 0; 3088 3089 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3090 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3091 unsigned int clock1, clock2; 3092 3093 /* Make sure to also match alternate clocks */ 3094 clock1 = hdmi_mode->clock; 3095 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3096 3097 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3098 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3099 drm_mode_match(to_match, hdmi_mode, match_flags)) 3100 return vic; 3101 } 3102 return 0; 3103 } 3104 3105 static bool drm_valid_hdmi_vic(u8 vic) 3106 { 3107 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3108 } 3109 3110 static int 3111 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3112 { 3113 struct drm_device *dev = connector->dev; 3114 struct drm_display_mode *mode, *tmp; 3115 LIST_HEAD(list); 3116 int modes = 0; 3117 3118 /* Don't add CEA modes if the CEA extension block is missing */ 3119 if (!drm_find_cea_extension(edid)) 3120 return 0; 3121 3122 /* 3123 * Go through all probed modes and create a new mode 3124 * with the alternate clock for certain CEA modes. 3125 */ 3126 list_for_each_entry(mode, &connector->probed_modes, head) { 3127 const struct drm_display_mode *cea_mode = NULL; 3128 struct drm_display_mode *newmode; 3129 u8 vic = drm_match_cea_mode(mode); 3130 unsigned int clock1, clock2; 3131 3132 if (drm_valid_cea_vic(vic)) { 3133 cea_mode = &edid_cea_modes[vic]; 3134 clock2 = cea_mode_alternate_clock(cea_mode); 3135 } else { 3136 vic = drm_match_hdmi_mode(mode); 3137 if (drm_valid_hdmi_vic(vic)) { 3138 cea_mode = &edid_4k_modes[vic]; 3139 clock2 = hdmi_mode_alternate_clock(cea_mode); 3140 } 3141 } 3142 3143 if (!cea_mode) 3144 continue; 3145 3146 clock1 = cea_mode->clock; 3147 3148 if (clock1 == clock2) 3149 continue; 3150 3151 if (mode->clock != clock1 && mode->clock != clock2) 3152 continue; 3153 3154 newmode = drm_mode_duplicate(dev, cea_mode); 3155 if (!newmode) 3156 continue; 3157 3158 /* Carry over the stereo flags */ 3159 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3160 3161 /* 3162 * The current mode could be either variant. Make 3163 * sure to pick the "other" clock for the new mode. 3164 */ 3165 if (mode->clock != clock1) 3166 newmode->clock = clock1; 3167 else 3168 newmode->clock = clock2; 3169 3170 list_add_tail(&newmode->head, &list); 3171 } 3172 3173 list_for_each_entry_safe(mode, tmp, &list, head) { 3174 list_del(&mode->head); 3175 drm_mode_probed_add(connector, mode); 3176 modes++; 3177 } 3178 3179 return modes; 3180 } 3181 3182 static u8 svd_to_vic(u8 svd) 3183 { 3184 /* 0-6 bit vic, 7th bit native mode indicator */ 3185 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3186 return svd & 127; 3187 3188 return svd; 3189 } 3190 3191 static struct drm_display_mode * 3192 drm_display_mode_from_vic_index(struct drm_connector *connector, 3193 const u8 *video_db, u8 video_len, 3194 u8 video_index) 3195 { 3196 struct drm_device *dev = connector->dev; 3197 struct drm_display_mode *newmode; 3198 u8 vic; 3199 3200 if (video_db == NULL || video_index >= video_len) 3201 return NULL; 3202 3203 /* CEA modes are numbered 1..127 */ 3204 vic = svd_to_vic(video_db[video_index]); 3205 if (!drm_valid_cea_vic(vic)) 3206 return NULL; 3207 3208 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3209 if (!newmode) 3210 return NULL; 3211 3212 newmode->vrefresh = 0; 3213 3214 return newmode; 3215 } 3216 3217 /* 3218 * do_y420vdb_modes - Parse YCBCR 420 only modes 3219 * @connector: connector corresponding to the HDMI sink 3220 * @svds: start of the data block of CEA YCBCR 420 VDB 3221 * @len: length of the CEA YCBCR 420 VDB 3222 * 3223 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3224 * which contains modes which can be supported in YCBCR 420 3225 * output format only. 3226 */ 3227 static int do_y420vdb_modes(struct drm_connector *connector, 3228 const u8 *svds, u8 svds_len) 3229 { 3230 int modes = 0, i; 3231 struct drm_device *dev = connector->dev; 3232 struct drm_display_info *info = &connector->display_info; 3233 struct drm_hdmi_info *hdmi = &info->hdmi; 3234 3235 for (i = 0; i < svds_len; i++) { 3236 u8 vic = svd_to_vic(svds[i]); 3237 struct drm_display_mode *newmode; 3238 3239 if (!drm_valid_cea_vic(vic)) 3240 continue; 3241 3242 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 3243 if (!newmode) 3244 break; 3245 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3246 drm_mode_probed_add(connector, newmode); 3247 modes++; 3248 } 3249 3250 if (modes > 0) 3251 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3252 return modes; 3253 } 3254 3255 /* 3256 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3257 * @connector: connector corresponding to the HDMI sink 3258 * @vic: CEA vic for the video mode to be added in the map 3259 * 3260 * Makes an entry for a videomode in the YCBCR 420 bitmap 3261 */ 3262 static void 3263 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3264 { 3265 u8 vic = svd_to_vic(svd); 3266 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3267 3268 if (!drm_valid_cea_vic(vic)) 3269 return; 3270 3271 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3272 } 3273 3274 static int 3275 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3276 { 3277 int i, modes = 0; 3278 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3279 3280 for (i = 0; i < len; i++) { 3281 struct drm_display_mode *mode; 3282 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3283 if (mode) { 3284 /* 3285 * YCBCR420 capability block contains a bitmap which 3286 * gives the index of CEA modes from CEA VDB, which 3287 * can support YCBCR 420 sampling output also (apart 3288 * from RGB/YCBCR444 etc). 3289 * For example, if the bit 0 in bitmap is set, 3290 * first mode in VDB can support YCBCR420 output too. 3291 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3292 */ 3293 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3294 drm_add_cmdb_modes(connector, db[i]); 3295 3296 drm_mode_probed_add(connector, mode); 3297 modes++; 3298 } 3299 } 3300 3301 return modes; 3302 } 3303 3304 struct stereo_mandatory_mode { 3305 int width, height, vrefresh; 3306 unsigned int flags; 3307 }; 3308 3309 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3310 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3311 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3312 { 1920, 1080, 50, 3313 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3314 { 1920, 1080, 60, 3315 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3316 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3317 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3318 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3319 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3320 }; 3321 3322 static bool 3323 stereo_match_mandatory(const struct drm_display_mode *mode, 3324 const struct stereo_mandatory_mode *stereo_mode) 3325 { 3326 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3327 3328 return mode->hdisplay == stereo_mode->width && 3329 mode->vdisplay == stereo_mode->height && 3330 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3331 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3332 } 3333 3334 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3335 { 3336 struct drm_device *dev = connector->dev; 3337 const struct drm_display_mode *mode; 3338 struct list_head stereo_modes; 3339 int modes = 0, i; 3340 3341 INIT_LIST_HEAD(&stereo_modes); 3342 3343 list_for_each_entry(mode, &connector->probed_modes, head) { 3344 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3345 const struct stereo_mandatory_mode *mandatory; 3346 struct drm_display_mode *new_mode; 3347 3348 if (!stereo_match_mandatory(mode, 3349 &stereo_mandatory_modes[i])) 3350 continue; 3351 3352 mandatory = &stereo_mandatory_modes[i]; 3353 new_mode = drm_mode_duplicate(dev, mode); 3354 if (!new_mode) 3355 continue; 3356 3357 new_mode->flags |= mandatory->flags; 3358 list_add_tail(&new_mode->head, &stereo_modes); 3359 modes++; 3360 } 3361 } 3362 3363 list_splice_tail(&stereo_modes, &connector->probed_modes); 3364 3365 return modes; 3366 } 3367 3368 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3369 { 3370 struct drm_device *dev = connector->dev; 3371 struct drm_display_mode *newmode; 3372 3373 if (!drm_valid_hdmi_vic(vic)) { 3374 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3375 return 0; 3376 } 3377 3378 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3379 if (!newmode) 3380 return 0; 3381 3382 drm_mode_probed_add(connector, newmode); 3383 3384 return 1; 3385 } 3386 3387 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3388 const u8 *video_db, u8 video_len, u8 video_index) 3389 { 3390 struct drm_display_mode *newmode; 3391 int modes = 0; 3392 3393 if (structure & (1 << 0)) { 3394 newmode = drm_display_mode_from_vic_index(connector, video_db, 3395 video_len, 3396 video_index); 3397 if (newmode) { 3398 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3399 drm_mode_probed_add(connector, newmode); 3400 modes++; 3401 } 3402 } 3403 if (structure & (1 << 6)) { 3404 newmode = drm_display_mode_from_vic_index(connector, video_db, 3405 video_len, 3406 video_index); 3407 if (newmode) { 3408 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3409 drm_mode_probed_add(connector, newmode); 3410 modes++; 3411 } 3412 } 3413 if (structure & (1 << 8)) { 3414 newmode = drm_display_mode_from_vic_index(connector, video_db, 3415 video_len, 3416 video_index); 3417 if (newmode) { 3418 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3419 drm_mode_probed_add(connector, newmode); 3420 modes++; 3421 } 3422 } 3423 3424 return modes; 3425 } 3426 3427 /* 3428 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3429 * @connector: connector corresponding to the HDMI sink 3430 * @db: start of the CEA vendor specific block 3431 * @len: length of the CEA block payload, ie. one can access up to db[len] 3432 * 3433 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3434 * also adds the stereo 3d modes when applicable. 3435 */ 3436 static int 3437 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3438 const u8 *video_db, u8 video_len) 3439 { 3440 struct drm_display_info *info = &connector->display_info; 3441 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3442 u8 vic_len, hdmi_3d_len = 0; 3443 u16 mask; 3444 u16 structure_all; 3445 3446 if (len < 8) 3447 goto out; 3448 3449 /* no HDMI_Video_Present */ 3450 if (!(db[8] & (1 << 5))) 3451 goto out; 3452 3453 /* Latency_Fields_Present */ 3454 if (db[8] & (1 << 7)) 3455 offset += 2; 3456 3457 /* I_Latency_Fields_Present */ 3458 if (db[8] & (1 << 6)) 3459 offset += 2; 3460 3461 /* the declared length is not long enough for the 2 first bytes 3462 * of additional video format capabilities */ 3463 if (len < (8 + offset + 2)) 3464 goto out; 3465 3466 /* 3D_Present */ 3467 offset++; 3468 if (db[8 + offset] & (1 << 7)) { 3469 modes += add_hdmi_mandatory_stereo_modes(connector); 3470 3471 /* 3D_Multi_present */ 3472 multi_present = (db[8 + offset] & 0x60) >> 5; 3473 } 3474 3475 offset++; 3476 vic_len = db[8 + offset] >> 5; 3477 hdmi_3d_len = db[8 + offset] & 0x1f; 3478 3479 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3480 u8 vic; 3481 3482 vic = db[9 + offset + i]; 3483 modes += add_hdmi_mode(connector, vic); 3484 } 3485 offset += 1 + vic_len; 3486 3487 if (multi_present == 1) 3488 multi_len = 2; 3489 else if (multi_present == 2) 3490 multi_len = 4; 3491 else 3492 multi_len = 0; 3493 3494 if (len < (8 + offset + hdmi_3d_len - 1)) 3495 goto out; 3496 3497 if (hdmi_3d_len < multi_len) 3498 goto out; 3499 3500 if (multi_present == 1 || multi_present == 2) { 3501 /* 3D_Structure_ALL */ 3502 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3503 3504 /* check if 3D_MASK is present */ 3505 if (multi_present == 2) 3506 mask = (db[10 + offset] << 8) | db[11 + offset]; 3507 else 3508 mask = 0xffff; 3509 3510 for (i = 0; i < 16; i++) { 3511 if (mask & (1 << i)) 3512 modes += add_3d_struct_modes(connector, 3513 structure_all, 3514 video_db, 3515 video_len, i); 3516 } 3517 } 3518 3519 offset += multi_len; 3520 3521 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3522 int vic_index; 3523 struct drm_display_mode *newmode = NULL; 3524 unsigned int newflag = 0; 3525 bool detail_present; 3526 3527 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3528 3529 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3530 break; 3531 3532 /* 2D_VIC_order_X */ 3533 vic_index = db[8 + offset + i] >> 4; 3534 3535 /* 3D_Structure_X */ 3536 switch (db[8 + offset + i] & 0x0f) { 3537 case 0: 3538 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3539 break; 3540 case 6: 3541 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3542 break; 3543 case 8: 3544 /* 3D_Detail_X */ 3545 if ((db[9 + offset + i] >> 4) == 1) 3546 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3547 break; 3548 } 3549 3550 if (newflag != 0) { 3551 newmode = drm_display_mode_from_vic_index(connector, 3552 video_db, 3553 video_len, 3554 vic_index); 3555 3556 if (newmode) { 3557 newmode->flags |= newflag; 3558 drm_mode_probed_add(connector, newmode); 3559 modes++; 3560 } 3561 } 3562 3563 if (detail_present) 3564 i++; 3565 } 3566 3567 out: 3568 if (modes > 0) 3569 info->has_hdmi_infoframe = true; 3570 return modes; 3571 } 3572 3573 static int 3574 cea_db_payload_len(const u8 *db) 3575 { 3576 return db[0] & 0x1f; 3577 } 3578 3579 static int 3580 cea_db_extended_tag(const u8 *db) 3581 { 3582 return db[1]; 3583 } 3584 3585 static int 3586 cea_db_tag(const u8 *db) 3587 { 3588 return db[0] >> 5; 3589 } 3590 3591 static int 3592 cea_revision(const u8 *cea) 3593 { 3594 return cea[1]; 3595 } 3596 3597 static int 3598 cea_db_offsets(const u8 *cea, int *start, int *end) 3599 { 3600 /* Data block offset in CEA extension block */ 3601 *start = 4; 3602 *end = cea[2]; 3603 if (*end == 0) 3604 *end = 127; 3605 if (*end < 4 || *end > 127) 3606 return -ERANGE; 3607 return 0; 3608 } 3609 3610 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3611 { 3612 int hdmi_id; 3613 3614 if (cea_db_tag(db) != VENDOR_BLOCK) 3615 return false; 3616 3617 if (cea_db_payload_len(db) < 5) 3618 return false; 3619 3620 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3621 3622 return hdmi_id == HDMI_IEEE_OUI; 3623 } 3624 3625 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3626 { 3627 unsigned int oui; 3628 3629 if (cea_db_tag(db) != VENDOR_BLOCK) 3630 return false; 3631 3632 if (cea_db_payload_len(db) < 7) 3633 return false; 3634 3635 oui = db[3] << 16 | db[2] << 8 | db[1]; 3636 3637 return oui == HDMI_FORUM_IEEE_OUI; 3638 } 3639 3640 static bool cea_db_is_vcdb(const u8 *db) 3641 { 3642 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3643 return false; 3644 3645 if (cea_db_payload_len(db) != 2) 3646 return false; 3647 3648 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 3649 return false; 3650 3651 return true; 3652 } 3653 3654 static bool cea_db_is_y420cmdb(const u8 *db) 3655 { 3656 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3657 return false; 3658 3659 if (!cea_db_payload_len(db)) 3660 return false; 3661 3662 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 3663 return false; 3664 3665 return true; 3666 } 3667 3668 static bool cea_db_is_y420vdb(const u8 *db) 3669 { 3670 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3671 return false; 3672 3673 if (!cea_db_payload_len(db)) 3674 return false; 3675 3676 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 3677 return false; 3678 3679 return true; 3680 } 3681 3682 #define for_each_cea_db(cea, i, start, end) \ 3683 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3684 3685 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 3686 const u8 *db) 3687 { 3688 struct drm_display_info *info = &connector->display_info; 3689 struct drm_hdmi_info *hdmi = &info->hdmi; 3690 u8 map_len = cea_db_payload_len(db) - 1; 3691 u8 count; 3692 u64 map = 0; 3693 3694 if (map_len == 0) { 3695 /* All CEA modes support ycbcr420 sampling also.*/ 3696 hdmi->y420_cmdb_map = U64_MAX; 3697 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3698 return; 3699 } 3700 3701 /* 3702 * This map indicates which of the existing CEA block modes 3703 * from VDB can support YCBCR420 output too. So if bit=0 is 3704 * set, first mode from VDB can support YCBCR420 output too. 3705 * We will parse and keep this map, before parsing VDB itself 3706 * to avoid going through the same block again and again. 3707 * 3708 * Spec is not clear about max possible size of this block. 3709 * Clamping max bitmap block size at 8 bytes. Every byte can 3710 * address 8 CEA modes, in this way this map can address 3711 * 8*8 = first 64 SVDs. 3712 */ 3713 if (WARN_ON_ONCE(map_len > 8)) 3714 map_len = 8; 3715 3716 for (count = 0; count < map_len; count++) 3717 map |= (u64)db[2 + count] << (8 * count); 3718 3719 if (map) 3720 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3721 3722 hdmi->y420_cmdb_map = map; 3723 } 3724 3725 static int 3726 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3727 { 3728 const u8 *cea = drm_find_cea_extension(edid); 3729 const u8 *db, *hdmi = NULL, *video = NULL; 3730 u8 dbl, hdmi_len, video_len = 0; 3731 int modes = 0; 3732 3733 if (cea && cea_revision(cea) >= 3) { 3734 int i, start, end; 3735 3736 if (cea_db_offsets(cea, &start, &end)) 3737 return 0; 3738 3739 for_each_cea_db(cea, i, start, end) { 3740 db = &cea[i]; 3741 dbl = cea_db_payload_len(db); 3742 3743 if (cea_db_tag(db) == VIDEO_BLOCK) { 3744 video = db + 1; 3745 video_len = dbl; 3746 modes += do_cea_modes(connector, video, dbl); 3747 } else if (cea_db_is_hdmi_vsdb(db)) { 3748 hdmi = db; 3749 hdmi_len = dbl; 3750 } else if (cea_db_is_y420vdb(db)) { 3751 const u8 *vdb420 = &db[2]; 3752 3753 /* Add 4:2:0(only) modes present in EDID */ 3754 modes += do_y420vdb_modes(connector, 3755 vdb420, 3756 dbl - 1); 3757 } 3758 } 3759 } 3760 3761 /* 3762 * We parse the HDMI VSDB after having added the cea modes as we will 3763 * be patching their flags when the sink supports stereo 3D. 3764 */ 3765 if (hdmi) 3766 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3767 video_len); 3768 3769 return modes; 3770 } 3771 3772 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3773 { 3774 const struct drm_display_mode *cea_mode; 3775 int clock1, clock2, clock; 3776 u8 vic; 3777 const char *type; 3778 3779 /* 3780 * allow 5kHz clock difference either way to account for 3781 * the 10kHz clock resolution limit of detailed timings. 3782 */ 3783 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3784 if (drm_valid_cea_vic(vic)) { 3785 type = "CEA"; 3786 cea_mode = &edid_cea_modes[vic]; 3787 clock1 = cea_mode->clock; 3788 clock2 = cea_mode_alternate_clock(cea_mode); 3789 } else { 3790 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3791 if (drm_valid_hdmi_vic(vic)) { 3792 type = "HDMI"; 3793 cea_mode = &edid_4k_modes[vic]; 3794 clock1 = cea_mode->clock; 3795 clock2 = hdmi_mode_alternate_clock(cea_mode); 3796 } else { 3797 return; 3798 } 3799 } 3800 3801 /* pick whichever is closest */ 3802 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3803 clock = clock1; 3804 else 3805 clock = clock2; 3806 3807 if (mode->clock == clock) 3808 return; 3809 3810 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3811 type, vic, mode->clock, clock); 3812 mode->clock = clock; 3813 } 3814 3815 static void 3816 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3817 { 3818 u8 len = cea_db_payload_len(db); 3819 3820 if (len >= 6 && (db[6] & (1 << 7))) 3821 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 3822 if (len >= 8) { 3823 connector->latency_present[0] = db[8] >> 7; 3824 connector->latency_present[1] = (db[8] >> 6) & 1; 3825 } 3826 if (len >= 9) 3827 connector->video_latency[0] = db[9]; 3828 if (len >= 10) 3829 connector->audio_latency[0] = db[10]; 3830 if (len >= 11) 3831 connector->video_latency[1] = db[11]; 3832 if (len >= 12) 3833 connector->audio_latency[1] = db[12]; 3834 3835 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3836 "video latency %d %d, " 3837 "audio latency %d %d\n", 3838 connector->latency_present[0], 3839 connector->latency_present[1], 3840 connector->video_latency[0], 3841 connector->video_latency[1], 3842 connector->audio_latency[0], 3843 connector->audio_latency[1]); 3844 } 3845 3846 static void 3847 monitor_name(struct detailed_timing *t, void *data) 3848 { 3849 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3850 *(u8 **)data = t->data.other_data.data.str.str; 3851 } 3852 3853 static int get_monitor_name(struct edid *edid, char name[13]) 3854 { 3855 char *edid_name = NULL; 3856 int mnl; 3857 3858 if (!edid || !name) 3859 return 0; 3860 3861 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3862 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3863 if (edid_name[mnl] == 0x0a) 3864 break; 3865 3866 name[mnl] = edid_name[mnl]; 3867 } 3868 3869 return mnl; 3870 } 3871 3872 /** 3873 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3874 * @edid: monitor EDID information 3875 * @name: pointer to a character array to hold the name of the monitor 3876 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3877 * 3878 */ 3879 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3880 { 3881 int name_length; 3882 char buf[13]; 3883 3884 if (bufsize <= 0) 3885 return; 3886 3887 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3888 memcpy(name, buf, name_length); 3889 name[name_length] = '\0'; 3890 } 3891 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3892 3893 static void clear_eld(struct drm_connector *connector) 3894 { 3895 memset(connector->eld, 0, sizeof(connector->eld)); 3896 3897 connector->latency_present[0] = false; 3898 connector->latency_present[1] = false; 3899 connector->video_latency[0] = 0; 3900 connector->audio_latency[0] = 0; 3901 connector->video_latency[1] = 0; 3902 connector->audio_latency[1] = 0; 3903 } 3904 3905 /* 3906 * drm_edid_to_eld - build ELD from EDID 3907 * @connector: connector corresponding to the HDMI/DP sink 3908 * @edid: EDID to parse 3909 * 3910 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3911 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3912 */ 3913 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3914 { 3915 uint8_t *eld = connector->eld; 3916 u8 *cea; 3917 u8 *db; 3918 int total_sad_count = 0; 3919 int mnl; 3920 int dbl; 3921 3922 clear_eld(connector); 3923 3924 if (!edid) 3925 return; 3926 3927 cea = drm_find_cea_extension(edid); 3928 if (!cea) { 3929 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3930 return; 3931 } 3932 3933 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 3934 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 3935 3936 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 3937 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 3938 3939 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 3940 3941 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 3942 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 3943 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 3944 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 3945 3946 if (cea_revision(cea) >= 3) { 3947 int i, start, end; 3948 3949 if (cea_db_offsets(cea, &start, &end)) { 3950 start = 0; 3951 end = 0; 3952 } 3953 3954 for_each_cea_db(cea, i, start, end) { 3955 db = &cea[i]; 3956 dbl = cea_db_payload_len(db); 3957 3958 switch (cea_db_tag(db)) { 3959 int sad_count; 3960 3961 case AUDIO_BLOCK: 3962 /* Audio Data Block, contains SADs */ 3963 sad_count = min(dbl / 3, 15 - total_sad_count); 3964 if (sad_count >= 1) 3965 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 3966 &db[1], sad_count * 3); 3967 total_sad_count += sad_count; 3968 break; 3969 case SPEAKER_BLOCK: 3970 /* Speaker Allocation Data Block */ 3971 if (dbl >= 1) 3972 eld[DRM_ELD_SPEAKER] = db[1]; 3973 break; 3974 case VENDOR_BLOCK: 3975 /* HDMI Vendor-Specific Data Block */ 3976 if (cea_db_is_hdmi_vsdb(db)) 3977 drm_parse_hdmi_vsdb_audio(connector, db); 3978 break; 3979 default: 3980 break; 3981 } 3982 } 3983 } 3984 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 3985 3986 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3987 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3988 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 3989 else 3990 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 3991 3992 eld[DRM_ELD_BASELINE_ELD_LEN] = 3993 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3994 3995 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3996 drm_eld_size(eld), total_sad_count); 3997 } 3998 3999 /** 4000 * drm_edid_to_sad - extracts SADs from EDID 4001 * @edid: EDID to parse 4002 * @sads: pointer that will be set to the extracted SADs 4003 * 4004 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4005 * 4006 * Note: The returned pointer needs to be freed using kfree(). 4007 * 4008 * Return: The number of found SADs or negative number on error. 4009 */ 4010 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4011 { 4012 int count = 0; 4013 int i, start, end, dbl; 4014 u8 *cea; 4015 4016 cea = drm_find_cea_extension(edid); 4017 if (!cea) { 4018 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4019 return -ENOENT; 4020 } 4021 4022 if (cea_revision(cea) < 3) { 4023 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4024 return -ENOTSUPP; 4025 } 4026 4027 if (cea_db_offsets(cea, &start, &end)) { 4028 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4029 return -EPROTO; 4030 } 4031 4032 for_each_cea_db(cea, i, start, end) { 4033 u8 *db = &cea[i]; 4034 4035 if (cea_db_tag(db) == AUDIO_BLOCK) { 4036 int j; 4037 dbl = cea_db_payload_len(db); 4038 4039 count = dbl / 3; /* SAD is 3B */ 4040 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4041 if (!*sads) 4042 return -ENOMEM; 4043 for (j = 0; j < count; j++) { 4044 u8 *sad = &db[1 + j * 3]; 4045 4046 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4047 (*sads)[j].channels = sad[0] & 0x7; 4048 (*sads)[j].freq = sad[1] & 0x7F; 4049 (*sads)[j].byte2 = sad[2]; 4050 } 4051 break; 4052 } 4053 } 4054 4055 return count; 4056 } 4057 EXPORT_SYMBOL(drm_edid_to_sad); 4058 4059 /** 4060 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4061 * @edid: EDID to parse 4062 * @sadb: pointer to the speaker block 4063 * 4064 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4065 * 4066 * Note: The returned pointer needs to be freed using kfree(). 4067 * 4068 * Return: The number of found Speaker Allocation Blocks or negative number on 4069 * error. 4070 */ 4071 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4072 { 4073 int count = 0; 4074 int i, start, end, dbl; 4075 const u8 *cea; 4076 4077 cea = drm_find_cea_extension(edid); 4078 if (!cea) { 4079 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4080 return -ENOENT; 4081 } 4082 4083 if (cea_revision(cea) < 3) { 4084 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4085 return -ENOTSUPP; 4086 } 4087 4088 if (cea_db_offsets(cea, &start, &end)) { 4089 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4090 return -EPROTO; 4091 } 4092 4093 for_each_cea_db(cea, i, start, end) { 4094 const u8 *db = &cea[i]; 4095 4096 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4097 dbl = cea_db_payload_len(db); 4098 4099 /* Speaker Allocation Data Block */ 4100 if (dbl == 3) { 4101 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4102 if (!*sadb) 4103 return -ENOMEM; 4104 count = dbl; 4105 break; 4106 } 4107 } 4108 } 4109 4110 return count; 4111 } 4112 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4113 4114 /** 4115 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4116 * @connector: connector associated with the HDMI/DP sink 4117 * @mode: the display mode 4118 * 4119 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4120 * the sink doesn't support audio or video. 4121 */ 4122 int drm_av_sync_delay(struct drm_connector *connector, 4123 const struct drm_display_mode *mode) 4124 { 4125 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4126 int a, v; 4127 4128 if (!connector->latency_present[0]) 4129 return 0; 4130 if (!connector->latency_present[1]) 4131 i = 0; 4132 4133 a = connector->audio_latency[i]; 4134 v = connector->video_latency[i]; 4135 4136 /* 4137 * HDMI/DP sink doesn't support audio or video? 4138 */ 4139 if (a == 255 || v == 255) 4140 return 0; 4141 4142 /* 4143 * Convert raw EDID values to millisecond. 4144 * Treat unknown latency as 0ms. 4145 */ 4146 if (a) 4147 a = min(2 * (a - 1), 500); 4148 if (v) 4149 v = min(2 * (v - 1), 500); 4150 4151 return max(v - a, 0); 4152 } 4153 EXPORT_SYMBOL(drm_av_sync_delay); 4154 4155 /** 4156 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4157 * @edid: monitor EDID information 4158 * 4159 * Parse the CEA extension according to CEA-861-B. 4160 * 4161 * Return: True if the monitor is HDMI, false if not or unknown. 4162 */ 4163 bool drm_detect_hdmi_monitor(struct edid *edid) 4164 { 4165 u8 *edid_ext; 4166 int i; 4167 int start_offset, end_offset; 4168 4169 edid_ext = drm_find_cea_extension(edid); 4170 if (!edid_ext) 4171 return false; 4172 4173 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4174 return false; 4175 4176 /* 4177 * Because HDMI identifier is in Vendor Specific Block, 4178 * search it from all data blocks of CEA extension. 4179 */ 4180 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4181 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4182 return true; 4183 } 4184 4185 return false; 4186 } 4187 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4188 4189 /** 4190 * drm_detect_monitor_audio - check monitor audio capability 4191 * @edid: EDID block to scan 4192 * 4193 * Monitor should have CEA extension block. 4194 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4195 * audio' only. If there is any audio extension block and supported 4196 * audio format, assume at least 'basic audio' support, even if 'basic 4197 * audio' is not defined in EDID. 4198 * 4199 * Return: True if the monitor supports audio, false otherwise. 4200 */ 4201 bool drm_detect_monitor_audio(struct edid *edid) 4202 { 4203 u8 *edid_ext; 4204 int i, j; 4205 bool has_audio = false; 4206 int start_offset, end_offset; 4207 4208 edid_ext = drm_find_cea_extension(edid); 4209 if (!edid_ext) 4210 goto end; 4211 4212 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4213 4214 if (has_audio) { 4215 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4216 goto end; 4217 } 4218 4219 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4220 goto end; 4221 4222 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4223 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4224 has_audio = true; 4225 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4226 DRM_DEBUG_KMS("CEA audio format %d\n", 4227 (edid_ext[i + j] >> 3) & 0xf); 4228 goto end; 4229 } 4230 } 4231 end: 4232 return has_audio; 4233 } 4234 EXPORT_SYMBOL(drm_detect_monitor_audio); 4235 4236 4237 /** 4238 * drm_default_rgb_quant_range - default RGB quantization range 4239 * @mode: display mode 4240 * 4241 * Determine the default RGB quantization range for the mode, 4242 * as specified in CEA-861. 4243 * 4244 * Return: The default RGB quantization range for the mode 4245 */ 4246 enum hdmi_quantization_range 4247 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4248 { 4249 /* All CEA modes other than VIC 1 use limited quantization range. */ 4250 return drm_match_cea_mode(mode) > 1 ? 4251 HDMI_QUANTIZATION_RANGE_LIMITED : 4252 HDMI_QUANTIZATION_RANGE_FULL; 4253 } 4254 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4255 4256 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4257 { 4258 struct drm_display_info *info = &connector->display_info; 4259 4260 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4261 4262 if (db[2] & EDID_CEA_VCDB_QS) 4263 info->rgb_quant_range_selectable = true; 4264 } 4265 4266 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4267 const u8 *db) 4268 { 4269 u8 dc_mask; 4270 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4271 4272 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4273 hdmi->y420_dc_modes = dc_mask; 4274 } 4275 4276 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4277 const u8 *hf_vsdb) 4278 { 4279 struct drm_display_info *display = &connector->display_info; 4280 struct drm_hdmi_info *hdmi = &display->hdmi; 4281 4282 display->has_hdmi_infoframe = true; 4283 4284 if (hf_vsdb[6] & 0x80) { 4285 hdmi->scdc.supported = true; 4286 if (hf_vsdb[6] & 0x40) 4287 hdmi->scdc.read_request = true; 4288 } 4289 4290 /* 4291 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4292 * And as per the spec, three factors confirm this: 4293 * * Availability of a HF-VSDB block in EDID (check) 4294 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4295 * * SCDC support available (let's check) 4296 * Lets check it out. 4297 */ 4298 4299 if (hf_vsdb[5]) { 4300 /* max clock is 5000 KHz times block value */ 4301 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4302 struct drm_scdc *scdc = &hdmi->scdc; 4303 4304 if (max_tmds_clock > 340000) { 4305 display->max_tmds_clock = max_tmds_clock; 4306 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4307 display->max_tmds_clock); 4308 } 4309 4310 if (scdc->supported) { 4311 scdc->scrambling.supported = true; 4312 4313 /* Few sinks support scrambling for cloks < 340M */ 4314 if ((hf_vsdb[6] & 0x8)) 4315 scdc->scrambling.low_rates = true; 4316 } 4317 } 4318 4319 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4320 } 4321 4322 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4323 const u8 *hdmi) 4324 { 4325 struct drm_display_info *info = &connector->display_info; 4326 unsigned int dc_bpc = 0; 4327 4328 /* HDMI supports at least 8 bpc */ 4329 info->bpc = 8; 4330 4331 if (cea_db_payload_len(hdmi) < 6) 4332 return; 4333 4334 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4335 dc_bpc = 10; 4336 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4337 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4338 connector->name); 4339 } 4340 4341 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4342 dc_bpc = 12; 4343 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4344 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4345 connector->name); 4346 } 4347 4348 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4349 dc_bpc = 16; 4350 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4351 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4352 connector->name); 4353 } 4354 4355 if (dc_bpc == 0) { 4356 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4357 connector->name); 4358 return; 4359 } 4360 4361 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4362 connector->name, dc_bpc); 4363 info->bpc = dc_bpc; 4364 4365 /* 4366 * Deep color support mandates RGB444 support for all video 4367 * modes and forbids YCRCB422 support for all video modes per 4368 * HDMI 1.3 spec. 4369 */ 4370 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4371 4372 /* YCRCB444 is optional according to spec. */ 4373 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4374 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4375 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4376 connector->name); 4377 } 4378 4379 /* 4380 * Spec says that if any deep color mode is supported at all, 4381 * then deep color 36 bit must be supported. 4382 */ 4383 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4384 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4385 connector->name); 4386 } 4387 } 4388 4389 static void 4390 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4391 { 4392 struct drm_display_info *info = &connector->display_info; 4393 u8 len = cea_db_payload_len(db); 4394 4395 if (len >= 6) 4396 info->dvi_dual = db[6] & 1; 4397 if (len >= 7) 4398 info->max_tmds_clock = db[7] * 5000; 4399 4400 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4401 "max TMDS clock %d kHz\n", 4402 info->dvi_dual, 4403 info->max_tmds_clock); 4404 4405 drm_parse_hdmi_deep_color_info(connector, db); 4406 } 4407 4408 static void drm_parse_cea_ext(struct drm_connector *connector, 4409 const struct edid *edid) 4410 { 4411 struct drm_display_info *info = &connector->display_info; 4412 const u8 *edid_ext; 4413 int i, start, end; 4414 4415 edid_ext = drm_find_cea_extension(edid); 4416 if (!edid_ext) 4417 return; 4418 4419 info->cea_rev = edid_ext[1]; 4420 4421 /* The existence of a CEA block should imply RGB support */ 4422 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4423 if (edid_ext[3] & EDID_CEA_YCRCB444) 4424 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4425 if (edid_ext[3] & EDID_CEA_YCRCB422) 4426 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4427 4428 if (cea_db_offsets(edid_ext, &start, &end)) 4429 return; 4430 4431 for_each_cea_db(edid_ext, i, start, end) { 4432 const u8 *db = &edid_ext[i]; 4433 4434 if (cea_db_is_hdmi_vsdb(db)) 4435 drm_parse_hdmi_vsdb_video(connector, db); 4436 if (cea_db_is_hdmi_forum_vsdb(db)) 4437 drm_parse_hdmi_forum_vsdb(connector, db); 4438 if (cea_db_is_y420cmdb(db)) 4439 drm_parse_y420cmdb_bitmap(connector, db); 4440 if (cea_db_is_vcdb(db)) 4441 drm_parse_vcdb(connector, db); 4442 } 4443 } 4444 4445 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4446 * all of the values which would have been set from EDID 4447 */ 4448 void 4449 drm_reset_display_info(struct drm_connector *connector) 4450 { 4451 struct drm_display_info *info = &connector->display_info; 4452 4453 info->width_mm = 0; 4454 info->height_mm = 0; 4455 4456 info->bpc = 0; 4457 info->color_formats = 0; 4458 info->cea_rev = 0; 4459 info->max_tmds_clock = 0; 4460 info->dvi_dual = false; 4461 info->has_hdmi_infoframe = false; 4462 info->rgb_quant_range_selectable = false; 4463 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4464 4465 info->non_desktop = 0; 4466 } 4467 4468 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4469 { 4470 struct drm_display_info *info = &connector->display_info; 4471 4472 u32 quirks = edid_get_quirks(edid); 4473 4474 drm_reset_display_info(connector); 4475 4476 info->width_mm = edid->width_cm * 10; 4477 info->height_mm = edid->height_cm * 10; 4478 4479 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4480 4481 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4482 4483 if (edid->revision < 3) 4484 return quirks; 4485 4486 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4487 return quirks; 4488 4489 drm_parse_cea_ext(connector, edid); 4490 4491 /* 4492 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4493 * 4494 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4495 * tells us to assume 8 bpc color depth if the EDID doesn't have 4496 * extensions which tell otherwise. 4497 */ 4498 if ((info->bpc == 0) && (edid->revision < 4) && 4499 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4500 info->bpc = 8; 4501 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4502 connector->name, info->bpc); 4503 } 4504 4505 /* Only defined for 1.4 with digital displays */ 4506 if (edid->revision < 4) 4507 return quirks; 4508 4509 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4510 case DRM_EDID_DIGITAL_DEPTH_6: 4511 info->bpc = 6; 4512 break; 4513 case DRM_EDID_DIGITAL_DEPTH_8: 4514 info->bpc = 8; 4515 break; 4516 case DRM_EDID_DIGITAL_DEPTH_10: 4517 info->bpc = 10; 4518 break; 4519 case DRM_EDID_DIGITAL_DEPTH_12: 4520 info->bpc = 12; 4521 break; 4522 case DRM_EDID_DIGITAL_DEPTH_14: 4523 info->bpc = 14; 4524 break; 4525 case DRM_EDID_DIGITAL_DEPTH_16: 4526 info->bpc = 16; 4527 break; 4528 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4529 default: 4530 info->bpc = 0; 4531 break; 4532 } 4533 4534 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4535 connector->name, info->bpc); 4536 4537 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4538 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4539 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4540 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4541 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4542 return quirks; 4543 } 4544 4545 static int validate_displayid(u8 *displayid, int length, int idx) 4546 { 4547 int i; 4548 u8 csum = 0; 4549 struct displayid_hdr *base; 4550 4551 base = (struct displayid_hdr *)&displayid[idx]; 4552 4553 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4554 base->rev, base->bytes, base->prod_id, base->ext_count); 4555 4556 if (base->bytes + 5 > length - idx) 4557 return -EINVAL; 4558 for (i = idx; i <= base->bytes + 5; i++) { 4559 csum += displayid[i]; 4560 } 4561 if (csum) { 4562 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4563 return -EINVAL; 4564 } 4565 return 0; 4566 } 4567 4568 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4569 struct displayid_detailed_timings_1 *timings) 4570 { 4571 struct drm_display_mode *mode; 4572 unsigned pixel_clock = (timings->pixel_clock[0] | 4573 (timings->pixel_clock[1] << 8) | 4574 (timings->pixel_clock[2] << 16)); 4575 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4576 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4577 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4578 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4579 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4580 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4581 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4582 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4583 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4584 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4585 mode = drm_mode_create(dev); 4586 if (!mode) 4587 return NULL; 4588 4589 mode->clock = pixel_clock * 10; 4590 mode->hdisplay = hactive; 4591 mode->hsync_start = mode->hdisplay + hsync; 4592 mode->hsync_end = mode->hsync_start + hsync_width; 4593 mode->htotal = mode->hdisplay + hblank; 4594 4595 mode->vdisplay = vactive; 4596 mode->vsync_start = mode->vdisplay + vsync; 4597 mode->vsync_end = mode->vsync_start + vsync_width; 4598 mode->vtotal = mode->vdisplay + vblank; 4599 4600 mode->flags = 0; 4601 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4602 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4603 mode->type = DRM_MODE_TYPE_DRIVER; 4604 4605 if (timings->flags & 0x80) 4606 mode->type |= DRM_MODE_TYPE_PREFERRED; 4607 mode->vrefresh = drm_mode_vrefresh(mode); 4608 drm_mode_set_name(mode); 4609 4610 return mode; 4611 } 4612 4613 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4614 struct displayid_block *block) 4615 { 4616 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4617 int i; 4618 int num_timings; 4619 struct drm_display_mode *newmode; 4620 int num_modes = 0; 4621 /* blocks must be multiple of 20 bytes length */ 4622 if (block->num_bytes % 20) 4623 return 0; 4624 4625 num_timings = block->num_bytes / 20; 4626 for (i = 0; i < num_timings; i++) { 4627 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4628 4629 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4630 if (!newmode) 4631 continue; 4632 4633 drm_mode_probed_add(connector, newmode); 4634 num_modes++; 4635 } 4636 return num_modes; 4637 } 4638 4639 static int add_displayid_detailed_modes(struct drm_connector *connector, 4640 struct edid *edid) 4641 { 4642 u8 *displayid; 4643 int ret; 4644 int idx = 1; 4645 int length = EDID_LENGTH; 4646 struct displayid_block *block; 4647 int num_modes = 0; 4648 4649 displayid = drm_find_displayid_extension(edid); 4650 if (!displayid) 4651 return 0; 4652 4653 ret = validate_displayid(displayid, length, idx); 4654 if (ret) 4655 return 0; 4656 4657 idx += sizeof(struct displayid_hdr); 4658 while (block = (struct displayid_block *)&displayid[idx], 4659 idx + sizeof(struct displayid_block) <= length && 4660 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4661 block->num_bytes > 0) { 4662 idx += block->num_bytes + sizeof(struct displayid_block); 4663 switch (block->tag) { 4664 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4665 num_modes += add_displayid_detailed_1_modes(connector, block); 4666 break; 4667 } 4668 } 4669 return num_modes; 4670 } 4671 4672 /** 4673 * drm_add_edid_modes - add modes from EDID data, if available 4674 * @connector: connector we're probing 4675 * @edid: EDID data 4676 * 4677 * Add the specified modes to the connector's mode list. Also fills out the 4678 * &drm_display_info structure and ELD in @connector with any information which 4679 * can be derived from the edid. 4680 * 4681 * Return: The number of modes added or 0 if we couldn't find any. 4682 */ 4683 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4684 { 4685 int num_modes = 0; 4686 u32 quirks; 4687 4688 if (edid == NULL) { 4689 clear_eld(connector); 4690 return 0; 4691 } 4692 if (!drm_edid_is_valid(edid)) { 4693 clear_eld(connector); 4694 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4695 connector->name); 4696 return 0; 4697 } 4698 4699 drm_edid_to_eld(connector, edid); 4700 4701 /* 4702 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4703 * To avoid multiple parsing of same block, lets parse that map 4704 * from sink info, before parsing CEA modes. 4705 */ 4706 quirks = drm_add_display_info(connector, edid); 4707 4708 /* 4709 * EDID spec says modes should be preferred in this order: 4710 * - preferred detailed mode 4711 * - other detailed modes from base block 4712 * - detailed modes from extension blocks 4713 * - CVT 3-byte code modes 4714 * - standard timing codes 4715 * - established timing codes 4716 * - modes inferred from GTF or CVT range information 4717 * 4718 * We get this pretty much right. 4719 * 4720 * XXX order for additional mode types in extension blocks? 4721 */ 4722 num_modes += add_detailed_modes(connector, edid, quirks); 4723 num_modes += add_cvt_modes(connector, edid); 4724 num_modes += add_standard_modes(connector, edid); 4725 num_modes += add_established_modes(connector, edid); 4726 num_modes += add_cea_modes(connector, edid); 4727 num_modes += add_alternate_cea_modes(connector, edid); 4728 num_modes += add_displayid_detailed_modes(connector, edid); 4729 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4730 num_modes += add_inferred_modes(connector, edid); 4731 4732 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4733 edid_fixup_preferred(connector, quirks); 4734 4735 if (quirks & EDID_QUIRK_FORCE_6BPC) 4736 connector->display_info.bpc = 6; 4737 4738 if (quirks & EDID_QUIRK_FORCE_8BPC) 4739 connector->display_info.bpc = 8; 4740 4741 if (quirks & EDID_QUIRK_FORCE_10BPC) 4742 connector->display_info.bpc = 10; 4743 4744 if (quirks & EDID_QUIRK_FORCE_12BPC) 4745 connector->display_info.bpc = 12; 4746 4747 return num_modes; 4748 } 4749 EXPORT_SYMBOL(drm_add_edid_modes); 4750 4751 /** 4752 * drm_add_modes_noedid - add modes for the connectors without EDID 4753 * @connector: connector we're probing 4754 * @hdisplay: the horizontal display limit 4755 * @vdisplay: the vertical display limit 4756 * 4757 * Add the specified modes to the connector's mode list. Only when the 4758 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4759 * 4760 * Return: The number of modes added or 0 if we couldn't find any. 4761 */ 4762 int drm_add_modes_noedid(struct drm_connector *connector, 4763 int hdisplay, int vdisplay) 4764 { 4765 int i, count, num_modes = 0; 4766 struct drm_display_mode *mode; 4767 struct drm_device *dev = connector->dev; 4768 4769 count = ARRAY_SIZE(drm_dmt_modes); 4770 if (hdisplay < 0) 4771 hdisplay = 0; 4772 if (vdisplay < 0) 4773 vdisplay = 0; 4774 4775 for (i = 0; i < count; i++) { 4776 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4777 if (hdisplay && vdisplay) { 4778 /* 4779 * Only when two are valid, they will be used to check 4780 * whether the mode should be added to the mode list of 4781 * the connector. 4782 */ 4783 if (ptr->hdisplay > hdisplay || 4784 ptr->vdisplay > vdisplay) 4785 continue; 4786 } 4787 if (drm_mode_vrefresh(ptr) > 61) 4788 continue; 4789 mode = drm_mode_duplicate(dev, ptr); 4790 if (mode) { 4791 drm_mode_probed_add(connector, mode); 4792 num_modes++; 4793 } 4794 } 4795 return num_modes; 4796 } 4797 EXPORT_SYMBOL(drm_add_modes_noedid); 4798 4799 /** 4800 * drm_set_preferred_mode - Sets the preferred mode of a connector 4801 * @connector: connector whose mode list should be processed 4802 * @hpref: horizontal resolution of preferred mode 4803 * @vpref: vertical resolution of preferred mode 4804 * 4805 * Marks a mode as preferred if it matches the resolution specified by @hpref 4806 * and @vpref. 4807 */ 4808 void drm_set_preferred_mode(struct drm_connector *connector, 4809 int hpref, int vpref) 4810 { 4811 struct drm_display_mode *mode; 4812 4813 list_for_each_entry(mode, &connector->probed_modes, head) { 4814 if (mode->hdisplay == hpref && 4815 mode->vdisplay == vpref) 4816 mode->type |= DRM_MODE_TYPE_PREFERRED; 4817 } 4818 } 4819 EXPORT_SYMBOL(drm_set_preferred_mode); 4820 4821 static bool is_hdmi2_sink(struct drm_connector *connector) 4822 { 4823 /* 4824 * FIXME: sil-sii8620 doesn't have a connector around when 4825 * we need one, so we have to be prepared for a NULL connector. 4826 */ 4827 if (!connector) 4828 return true; 4829 4830 return connector->display_info.hdmi.scdc.supported || 4831 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 4832 } 4833 4834 /** 4835 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4836 * data from a DRM display mode 4837 * @frame: HDMI AVI infoframe 4838 * @connector: the connector 4839 * @mode: DRM display mode 4840 * 4841 * Return: 0 on success or a negative error code on failure. 4842 */ 4843 int 4844 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4845 struct drm_connector *connector, 4846 const struct drm_display_mode *mode) 4847 { 4848 enum hdmi_picture_aspect picture_aspect; 4849 int err; 4850 4851 if (!frame || !mode) 4852 return -EINVAL; 4853 4854 err = hdmi_avi_infoframe_init(frame); 4855 if (err < 0) 4856 return err; 4857 4858 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4859 frame->pixel_repeat = 1; 4860 4861 frame->video_code = drm_match_cea_mode(mode); 4862 4863 /* 4864 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 4865 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 4866 * have to make sure we dont break HDMI 1.4 sinks. 4867 */ 4868 if (!is_hdmi2_sink(connector) && frame->video_code > 64) 4869 frame->video_code = 0; 4870 4871 /* 4872 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 4873 * we should send its VIC in vendor infoframes, else send the 4874 * VIC in AVI infoframes. Lets check if this mode is present in 4875 * HDMI 1.4b 4K modes 4876 */ 4877 if (frame->video_code) { 4878 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 4879 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 4880 4881 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 4882 frame->video_code = 0; 4883 } 4884 4885 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4886 4887 /* 4888 * As some drivers don't support atomic, we can't use connector state. 4889 * So just initialize the frame with default values, just the same way 4890 * as it's done with other properties here. 4891 */ 4892 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 4893 frame->itc = 0; 4894 4895 /* 4896 * Populate picture aspect ratio from either 4897 * user input (if specified) or from the CEA mode list. 4898 */ 4899 picture_aspect = mode->picture_aspect_ratio; 4900 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) 4901 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code); 4902 4903 /* 4904 * The infoframe can't convey anything but none, 4:3 4905 * and 16:9, so if the user has asked for anything else 4906 * we can only satisfy it by specifying the right VIC. 4907 */ 4908 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 4909 if (picture_aspect != 4910 drm_get_cea_aspect_ratio(frame->video_code)) 4911 return -EINVAL; 4912 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4913 } 4914 4915 frame->picture_aspect = picture_aspect; 4916 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4917 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4918 4919 return 0; 4920 } 4921 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4922 4923 /* HDMI Colorspace Spec Definitions */ 4924 #define FULL_COLORIMETRY_MASK 0x1FF 4925 #define NORMAL_COLORIMETRY_MASK 0x3 4926 #define EXTENDED_COLORIMETRY_MASK 0x7 4927 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 4928 4929 #define C(x) ((x) << 0) 4930 #define EC(x) ((x) << 2) 4931 #define ACE(x) ((x) << 5) 4932 4933 #define HDMI_COLORIMETRY_NO_DATA 0x0 4934 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 4935 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 4936 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 4937 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 4938 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 4939 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 4940 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 4941 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 4942 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 4943 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 4944 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 4945 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 4946 4947 static const u32 hdmi_colorimetry_val[] = { 4948 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 4949 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 4950 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 4951 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 4952 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 4953 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 4954 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 4955 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 4956 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 4957 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 4958 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 4959 }; 4960 4961 #undef C 4962 #undef EC 4963 #undef ACE 4964 4965 /** 4966 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 4967 * colorspace information 4968 * @frame: HDMI AVI infoframe 4969 * @conn_state: connector state 4970 */ 4971 void 4972 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 4973 const struct drm_connector_state *conn_state) 4974 { 4975 u32 colorimetry_val; 4976 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 4977 4978 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 4979 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 4980 else 4981 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 4982 4983 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 4984 /* 4985 * ToDo: Extend it for ACE formats as well. Modify the infoframe 4986 * structure and extend it in drivers/video/hdmi 4987 */ 4988 frame->extended_colorimetry = (colorimetry_val >> 2) & 4989 EXTENDED_COLORIMETRY_MASK; 4990 } 4991 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 4992 4993 /** 4994 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4995 * quantization range information 4996 * @frame: HDMI AVI infoframe 4997 * @connector: the connector 4998 * @mode: DRM display mode 4999 * @rgb_quant_range: RGB quantization range (Q) 5000 */ 5001 void 5002 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5003 struct drm_connector *connector, 5004 const struct drm_display_mode *mode, 5005 enum hdmi_quantization_range rgb_quant_range) 5006 { 5007 const struct drm_display_info *info = &connector->display_info; 5008 5009 /* 5010 * CEA-861: 5011 * "A Source shall not send a non-zero Q value that does not correspond 5012 * to the default RGB Quantization Range for the transmitted Picture 5013 * unless the Sink indicates support for the Q bit in a Video 5014 * Capabilities Data Block." 5015 * 5016 * HDMI 2.0 recommends sending non-zero Q when it does match the 5017 * default RGB quantization range for the mode, even when QS=0. 5018 */ 5019 if (info->rgb_quant_range_selectable || 5020 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5021 frame->quantization_range = rgb_quant_range; 5022 else 5023 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5024 5025 /* 5026 * CEA-861-F: 5027 * "When transmitting any RGB colorimetry, the Source should set the 5028 * YQ-field to match the RGB Quantization Range being transmitted 5029 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5030 * set YQ=1) and the Sink shall ignore the YQ-field." 5031 * 5032 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5033 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5034 * good way to tell which version of CEA-861 the sink supports, so 5035 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5036 * on on CEA-861-F. 5037 */ 5038 if (!is_hdmi2_sink(connector) || 5039 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5040 frame->ycc_quantization_range = 5041 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5042 else 5043 frame->ycc_quantization_range = 5044 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5045 } 5046 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5047 5048 static enum hdmi_3d_structure 5049 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5050 { 5051 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5052 5053 switch (layout) { 5054 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5055 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5056 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5057 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5058 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5059 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5060 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5061 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5062 case DRM_MODE_FLAG_3D_L_DEPTH: 5063 return HDMI_3D_STRUCTURE_L_DEPTH; 5064 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5065 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5066 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5067 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5068 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5069 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5070 default: 5071 return HDMI_3D_STRUCTURE_INVALID; 5072 } 5073 } 5074 5075 /** 5076 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5077 * data from a DRM display mode 5078 * @frame: HDMI vendor infoframe 5079 * @connector: the connector 5080 * @mode: DRM display mode 5081 * 5082 * Note that there's is a need to send HDMI vendor infoframes only when using a 5083 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5084 * function will return -EINVAL, error that can be safely ignored. 5085 * 5086 * Return: 0 on success or a negative error code on failure. 5087 */ 5088 int 5089 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5090 struct drm_connector *connector, 5091 const struct drm_display_mode *mode) 5092 { 5093 /* 5094 * FIXME: sil-sii8620 doesn't have a connector around when 5095 * we need one, so we have to be prepared for a NULL connector. 5096 */ 5097 bool has_hdmi_infoframe = connector ? 5098 connector->display_info.has_hdmi_infoframe : false; 5099 int err; 5100 u32 s3d_flags; 5101 u8 vic; 5102 5103 if (!frame || !mode) 5104 return -EINVAL; 5105 5106 if (!has_hdmi_infoframe) 5107 return -EINVAL; 5108 5109 vic = drm_match_hdmi_mode(mode); 5110 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5111 5112 /* 5113 * Even if it's not absolutely necessary to send the infoframe 5114 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5115 * know that the sink can handle it. This is based on a 5116 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5117 * have trouble realizing that they shuld switch from 3D to 2D 5118 * mode if the source simply stops sending the infoframe when 5119 * it wants to switch from 3D to 2D. 5120 */ 5121 5122 if (vic && s3d_flags) 5123 return -EINVAL; 5124 5125 err = hdmi_vendor_infoframe_init(frame); 5126 if (err < 0) 5127 return err; 5128 5129 frame->vic = vic; 5130 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5131 5132 return 0; 5133 } 5134 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5135 5136 static int drm_parse_tiled_block(struct drm_connector *connector, 5137 struct displayid_block *block) 5138 { 5139 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5140 u16 w, h; 5141 u8 tile_v_loc, tile_h_loc; 5142 u8 num_v_tile, num_h_tile; 5143 struct drm_tile_group *tg; 5144 5145 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5146 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5147 5148 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5149 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5150 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5151 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5152 5153 connector->has_tile = true; 5154 if (tile->tile_cap & 0x80) 5155 connector->tile_is_single_monitor = true; 5156 5157 connector->num_h_tile = num_h_tile + 1; 5158 connector->num_v_tile = num_v_tile + 1; 5159 connector->tile_h_loc = tile_h_loc; 5160 connector->tile_v_loc = tile_v_loc; 5161 connector->tile_h_size = w + 1; 5162 connector->tile_v_size = h + 1; 5163 5164 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5165 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5166 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5167 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5168 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5169 5170 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5171 if (!tg) { 5172 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5173 } 5174 if (!tg) 5175 return -ENOMEM; 5176 5177 if (connector->tile_group != tg) { 5178 /* if we haven't got a pointer, 5179 take the reference, drop ref to old tile group */ 5180 if (connector->tile_group) { 5181 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5182 } 5183 connector->tile_group = tg; 5184 } else 5185 /* if same tile group, then release the ref we just took. */ 5186 drm_mode_put_tile_group(connector->dev, tg); 5187 return 0; 5188 } 5189 5190 static int drm_parse_display_id(struct drm_connector *connector, 5191 u8 *displayid, int length, 5192 bool is_edid_extension) 5193 { 5194 /* if this is an EDID extension the first byte will be 0x70 */ 5195 int idx = 0; 5196 struct displayid_block *block; 5197 int ret; 5198 5199 if (is_edid_extension) 5200 idx = 1; 5201 5202 ret = validate_displayid(displayid, length, idx); 5203 if (ret) 5204 return ret; 5205 5206 idx += sizeof(struct displayid_hdr); 5207 while (block = (struct displayid_block *)&displayid[idx], 5208 idx + sizeof(struct displayid_block) <= length && 5209 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 5210 block->num_bytes > 0) { 5211 idx += block->num_bytes + sizeof(struct displayid_block); 5212 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5213 block->tag, block->rev, block->num_bytes); 5214 5215 switch (block->tag) { 5216 case DATA_BLOCK_TILED_DISPLAY: 5217 ret = drm_parse_tiled_block(connector, block); 5218 if (ret) 5219 return ret; 5220 break; 5221 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5222 /* handled in mode gathering code. */ 5223 break; 5224 default: 5225 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5226 break; 5227 } 5228 } 5229 return 0; 5230 } 5231 5232 static void drm_get_displayid(struct drm_connector *connector, 5233 struct edid *edid) 5234 { 5235 void *displayid = NULL; 5236 int ret; 5237 connector->has_tile = false; 5238 displayid = drm_find_displayid_extension(edid); 5239 if (!displayid) { 5240 /* drop reference to any tile group we had */ 5241 goto out_drop_ref; 5242 } 5243 5244 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5245 if (ret < 0) 5246 goto out_drop_ref; 5247 if (!connector->has_tile) 5248 goto out_drop_ref; 5249 return; 5250 out_drop_ref: 5251 if (connector->tile_group) { 5252 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5253 connector->tile_group = NULL; 5254 } 5255 return; 5256 } 5257