1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_displayid.h> 39 40 #define version_greater(edid, maj, min) \ 41 (((edid)->version > (maj)) || \ 42 ((edid)->version == (maj) && (edid)->revision > (min))) 43 44 #define EDID_EST_TIMINGS 16 45 #define EDID_STD_TIMINGS 8 46 #define EDID_DETAILED_TIMINGS 4 47 48 /* 49 * EDID blocks out in the wild have a variety of bugs, try to collect 50 * them here (note that userspace may work around broken monitors first, 51 * but fixes should make their way here so that the kernel "just works" 52 * on as many displays as possible). 53 */ 54 55 /* First detailed mode wrong, use largest 60Hz mode */ 56 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 57 /* Reported 135MHz pixel clock is too high, needs adjustment */ 58 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 59 /* Prefer the largest mode at 75 Hz */ 60 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 61 /* Detail timing is in cm not mm */ 62 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 63 /* Detailed timing descriptors have bogus size values, so just take the 64 * maximum size and use that. 65 */ 66 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 67 /* Monitor forgot to set the first detailed is preferred bit. */ 68 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 69 /* use +hsync +vsync for detailed mode */ 70 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 71 /* Force reduced-blanking timings for detailed modes */ 72 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 73 /* Force 8bpc */ 74 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 75 /* Force 12bpc */ 76 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 77 /* Force 6bpc */ 78 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 79 80 struct detailed_mode_closure { 81 struct drm_connector *connector; 82 struct edid *edid; 83 bool preferred; 84 u32 quirks; 85 int modes; 86 }; 87 88 #define LEVEL_DMT 0 89 #define LEVEL_GTF 1 90 #define LEVEL_GTF2 2 91 #define LEVEL_CVT 3 92 93 static struct edid_quirk { 94 char vendor[4]; 95 int product_id; 96 u32 quirks; 97 } edid_quirk_list[] = { 98 /* Acer AL1706 */ 99 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 100 /* Acer F51 */ 101 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Unknown Acer */ 103 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 104 105 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 106 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 107 108 /* Belinea 10 15 55 */ 109 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 110 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* Envision Peripherals, Inc. EN-7100e */ 113 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 114 /* Envision EN2028 */ 115 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 116 117 /* Funai Electronics PM36B */ 118 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 119 EDID_QUIRK_DETAILED_IN_CM }, 120 121 /* LG Philips LCD LP154W01-A5 */ 122 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 123 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 124 125 /* Philips 107p5 CRT */ 126 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Proview AY765C */ 129 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 130 131 /* Samsung SyncMaster 205BW. Note: irony */ 132 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 133 /* Samsung SyncMaster 22[5-6]BW */ 134 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 135 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 136 137 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 138 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 139 140 /* ViewSonic VA2026w */ 141 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 142 143 /* Medion MD 30217 PG */ 144 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 145 146 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 147 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Autogenerated from the DMT spec. 152 * This table is copied from xfree86/modes/xf86EdidModes.c. 153 */ 154 static const struct drm_display_mode drm_dmt_modes[] = { 155 /* 0x01 - 640x350@85Hz */ 156 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 157 736, 832, 0, 350, 382, 385, 445, 0, 158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 159 /* 0x02 - 640x400@85Hz */ 160 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 161 736, 832, 0, 400, 401, 404, 445, 0, 162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 163 /* 0x03 - 720x400@85Hz */ 164 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 165 828, 936, 0, 400, 401, 404, 446, 0, 166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 167 /* 0x04 - 640x480@60Hz */ 168 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 169 752, 800, 0, 480, 490, 492, 525, 0, 170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 171 /* 0x05 - 640x480@72Hz */ 172 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 173 704, 832, 0, 480, 489, 492, 520, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 175 /* 0x06 - 640x480@75Hz */ 176 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 177 720, 840, 0, 480, 481, 484, 500, 0, 178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 179 /* 0x07 - 640x480@85Hz */ 180 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 181 752, 832, 0, 480, 481, 484, 509, 0, 182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 183 /* 0x08 - 800x600@56Hz */ 184 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 185 896, 1024, 0, 600, 601, 603, 625, 0, 186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 187 /* 0x09 - 800x600@60Hz */ 188 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 189 968, 1056, 0, 600, 601, 605, 628, 0, 190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 191 /* 0x0a - 800x600@72Hz */ 192 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 193 976, 1040, 0, 600, 637, 643, 666, 0, 194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 195 /* 0x0b - 800x600@75Hz */ 196 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 197 896, 1056, 0, 600, 601, 604, 625, 0, 198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 199 /* 0x0c - 800x600@85Hz */ 200 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 201 896, 1048, 0, 600, 601, 604, 631, 0, 202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 203 /* 0x0d - 800x600@120Hz RB */ 204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 205 880, 960, 0, 600, 603, 607, 636, 0, 206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 207 /* 0x0e - 848x480@60Hz */ 208 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 209 976, 1088, 0, 480, 486, 494, 517, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x0f - 1024x768@43Hz, interlace */ 212 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 213 1208, 1264, 0, 768, 768, 776, 817, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 215 DRM_MODE_FLAG_INTERLACE) }, 216 /* 0x10 - 1024x768@60Hz */ 217 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 218 1184, 1344, 0, 768, 771, 777, 806, 0, 219 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 220 /* 0x11 - 1024x768@70Hz */ 221 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 222 1184, 1328, 0, 768, 771, 777, 806, 0, 223 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 224 /* 0x12 - 1024x768@75Hz */ 225 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 226 1136, 1312, 0, 768, 769, 772, 800, 0, 227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 228 /* 0x13 - 1024x768@85Hz */ 229 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 230 1168, 1376, 0, 768, 769, 772, 808, 0, 231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 232 /* 0x14 - 1024x768@120Hz RB */ 233 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 234 1104, 1184, 0, 768, 771, 775, 813, 0, 235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 236 /* 0x15 - 1152x864@75Hz */ 237 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 238 1344, 1600, 0, 864, 865, 868, 900, 0, 239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 240 /* 0x55 - 1280x720@60Hz */ 241 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 242 1430, 1650, 0, 720, 725, 730, 750, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 244 /* 0x16 - 1280x768@60Hz RB */ 245 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 246 1360, 1440, 0, 768, 771, 778, 790, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x17 - 1280x768@60Hz */ 249 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 250 1472, 1664, 0, 768, 771, 778, 798, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x18 - 1280x768@75Hz */ 253 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 254 1488, 1696, 0, 768, 771, 778, 805, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x19 - 1280x768@85Hz */ 257 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 258 1496, 1712, 0, 768, 771, 778, 809, 0, 259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x1a - 1280x768@120Hz RB */ 261 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 262 1360, 1440, 0, 768, 771, 778, 813, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 264 /* 0x1b - 1280x800@60Hz RB */ 265 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 266 1360, 1440, 0, 800, 803, 809, 823, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x1c - 1280x800@60Hz */ 269 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 270 1480, 1680, 0, 800, 803, 809, 831, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x1d - 1280x800@75Hz */ 273 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 274 1488, 1696, 0, 800, 803, 809, 838, 0, 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x1e - 1280x800@85Hz */ 277 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 278 1496, 1712, 0, 800, 803, 809, 843, 0, 279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x1f - 1280x800@120Hz RB */ 281 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 282 1360, 1440, 0, 800, 803, 809, 847, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 284 /* 0x20 - 1280x960@60Hz */ 285 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 286 1488, 1800, 0, 960, 961, 964, 1000, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x21 - 1280x960@85Hz */ 289 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 290 1504, 1728, 0, 960, 961, 964, 1011, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x22 - 1280x960@120Hz RB */ 293 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 294 1360, 1440, 0, 960, 963, 967, 1017, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x23 - 1280x1024@60Hz */ 297 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 298 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x24 - 1280x1024@75Hz */ 301 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 302 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x25 - 1280x1024@85Hz */ 305 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 306 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 308 /* 0x26 - 1280x1024@120Hz RB */ 309 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 310 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 312 /* 0x27 - 1360x768@60Hz */ 313 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 314 1536, 1792, 0, 768, 771, 777, 795, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x28 - 1360x768@120Hz RB */ 317 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 318 1440, 1520, 0, 768, 771, 776, 813, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 320 /* 0x51 - 1366x768@60Hz */ 321 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 322 1579, 1792, 0, 768, 771, 774, 798, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 0x56 - 1366x768@60Hz */ 325 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 326 1436, 1500, 0, 768, 769, 772, 800, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x29 - 1400x1050@60Hz RB */ 329 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 330 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 332 /* 0x2a - 1400x1050@60Hz */ 333 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 334 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x2b - 1400x1050@75Hz */ 337 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 338 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 339 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 0x2c - 1400x1050@85Hz */ 341 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 342 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 344 /* 0x2d - 1400x1050@120Hz RB */ 345 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 346 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 348 /* 0x2e - 1440x900@60Hz RB */ 349 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 350 1520, 1600, 0, 900, 903, 909, 926, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 352 /* 0x2f - 1440x900@60Hz */ 353 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 354 1672, 1904, 0, 900, 903, 909, 934, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x30 - 1440x900@75Hz */ 357 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 358 1688, 1936, 0, 900, 903, 909, 942, 0, 359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 360 /* 0x31 - 1440x900@85Hz */ 361 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 362 1696, 1952, 0, 900, 903, 909, 948, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x32 - 1440x900@120Hz RB */ 365 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 366 1520, 1600, 0, 900, 903, 909, 953, 0, 367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 368 /* 0x53 - 1600x900@60Hz */ 369 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 370 1704, 1800, 0, 900, 901, 904, 1000, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 372 /* 0x33 - 1600x1200@60Hz */ 373 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 374 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x34 - 1600x1200@65Hz */ 377 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 378 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x35 - 1600x1200@70Hz */ 381 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 382 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x36 - 1600x1200@75Hz */ 385 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 386 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x37 - 1600x1200@85Hz */ 389 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 390 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x38 - 1600x1200@120Hz RB */ 393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 394 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 396 /* 0x39 - 1680x1050@60Hz RB */ 397 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 398 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 400 /* 0x3a - 1680x1050@60Hz */ 401 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 402 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x3b - 1680x1050@75Hz */ 405 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 406 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 408 /* 0x3c - 1680x1050@85Hz */ 409 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 410 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x3d - 1680x1050@120Hz RB */ 413 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 414 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 416 /* 0x3e - 1792x1344@60Hz */ 417 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 418 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 420 /* 0x3f - 1792x1344@75Hz */ 421 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 422 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 424 /* 0x40 - 1792x1344@120Hz RB */ 425 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 426 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 428 /* 0x41 - 1856x1392@60Hz */ 429 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 430 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x42 - 1856x1392@75Hz */ 433 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 434 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x43 - 1856x1392@120Hz RB */ 437 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 438 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 0x52 - 1920x1080@60Hz */ 441 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 442 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 444 /* 0x44 - 1920x1200@60Hz RB */ 445 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 446 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 448 /* 0x45 - 1920x1200@60Hz */ 449 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 450 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x46 - 1920x1200@75Hz */ 453 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 454 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x47 - 1920x1200@85Hz */ 457 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 458 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 460 /* 0x48 - 1920x1200@120Hz RB */ 461 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 462 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 464 /* 0x49 - 1920x1440@60Hz */ 465 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 466 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 468 /* 0x4a - 1920x1440@75Hz */ 469 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 470 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x4b - 1920x1440@120Hz RB */ 473 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 474 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 476 /* 0x54 - 2048x1152@60Hz */ 477 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 478 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x4c - 2560x1600@60Hz RB */ 481 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 482 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 484 /* 0x4d - 2560x1600@60Hz */ 485 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 486 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 488 /* 0x4e - 2560x1600@75Hz */ 489 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 490 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 492 /* 0x4f - 2560x1600@85Hz */ 493 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 494 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x50 - 2560x1600@120Hz RB */ 497 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 498 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 500 /* 0x57 - 4096x2160@60Hz RB */ 501 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 502 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 504 /* 0x58 - 4096x2160@59.94Hz RB */ 505 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 506 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 508 }; 509 510 /* 511 * These more or less come from the DMT spec. The 720x400 modes are 512 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 513 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 514 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 515 * mode. 516 * 517 * The DMT modes have been fact-checked; the rest are mild guesses. 518 */ 519 static const struct drm_display_mode edid_est_modes[] = { 520 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 521 968, 1056, 0, 600, 601, 605, 628, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 523 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 524 896, 1024, 0, 600, 601, 603, 625, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 526 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 527 720, 840, 0, 480, 481, 484, 500, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 530 704, 832, 0, 480, 489, 492, 520, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 533 768, 864, 0, 480, 483, 486, 525, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 535 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 536 752, 800, 0, 480, 490, 492, 525, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 538 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 539 846, 900, 0, 400, 421, 423, 449, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 541 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 542 846, 900, 0, 400, 412, 414, 449, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 544 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 545 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 547 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 548 1136, 1312, 0, 768, 769, 772, 800, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 551 1184, 1328, 0, 768, 771, 777, 806, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 553 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 554 1184, 1344, 0, 768, 771, 777, 806, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 556 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 557 1208, 1264, 0, 768, 768, 776, 817, 0, 558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 559 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 560 928, 1152, 0, 624, 625, 628, 667, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 563 896, 1056, 0, 600, 601, 604, 625, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 565 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 566 976, 1040, 0, 600, 637, 643, 666, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 568 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 569 1344, 1600, 0, 864, 865, 868, 900, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 571 }; 572 573 struct minimode { 574 short w; 575 short h; 576 short r; 577 short rb; 578 }; 579 580 static const struct minimode est3_modes[] = { 581 /* byte 6 */ 582 { 640, 350, 85, 0 }, 583 { 640, 400, 85, 0 }, 584 { 720, 400, 85, 0 }, 585 { 640, 480, 85, 0 }, 586 { 848, 480, 60, 0 }, 587 { 800, 600, 85, 0 }, 588 { 1024, 768, 85, 0 }, 589 { 1152, 864, 75, 0 }, 590 /* byte 7 */ 591 { 1280, 768, 60, 1 }, 592 { 1280, 768, 60, 0 }, 593 { 1280, 768, 75, 0 }, 594 { 1280, 768, 85, 0 }, 595 { 1280, 960, 60, 0 }, 596 { 1280, 960, 85, 0 }, 597 { 1280, 1024, 60, 0 }, 598 { 1280, 1024, 85, 0 }, 599 /* byte 8 */ 600 { 1360, 768, 60, 0 }, 601 { 1440, 900, 60, 1 }, 602 { 1440, 900, 60, 0 }, 603 { 1440, 900, 75, 0 }, 604 { 1440, 900, 85, 0 }, 605 { 1400, 1050, 60, 1 }, 606 { 1400, 1050, 60, 0 }, 607 { 1400, 1050, 75, 0 }, 608 /* byte 9 */ 609 { 1400, 1050, 85, 0 }, 610 { 1680, 1050, 60, 1 }, 611 { 1680, 1050, 60, 0 }, 612 { 1680, 1050, 75, 0 }, 613 { 1680, 1050, 85, 0 }, 614 { 1600, 1200, 60, 0 }, 615 { 1600, 1200, 65, 0 }, 616 { 1600, 1200, 70, 0 }, 617 /* byte 10 */ 618 { 1600, 1200, 75, 0 }, 619 { 1600, 1200, 85, 0 }, 620 { 1792, 1344, 60, 0 }, 621 { 1792, 1344, 75, 0 }, 622 { 1856, 1392, 60, 0 }, 623 { 1856, 1392, 75, 0 }, 624 { 1920, 1200, 60, 1 }, 625 { 1920, 1200, 60, 0 }, 626 /* byte 11 */ 627 { 1920, 1200, 75, 0 }, 628 { 1920, 1200, 85, 0 }, 629 { 1920, 1440, 60, 0 }, 630 { 1920, 1440, 75, 0 }, 631 }; 632 633 static const struct minimode extra_modes[] = { 634 { 1024, 576, 60, 0 }, 635 { 1366, 768, 60, 0 }, 636 { 1600, 900, 60, 0 }, 637 { 1680, 945, 60, 0 }, 638 { 1920, 1080, 60, 0 }, 639 { 2048, 1152, 60, 0 }, 640 { 2048, 1536, 60, 0 }, 641 }; 642 643 /* 644 * Probably taken from CEA-861 spec. 645 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 646 * 647 * Index using the VIC. 648 */ 649 static const struct drm_display_mode edid_cea_modes[] = { 650 /* 0 - dummy, VICs start at 1 */ 651 { }, 652 /* 1 - 640x480@60Hz */ 653 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 654 752, 800, 0, 480, 490, 492, 525, 0, 655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 656 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 657 /* 2 - 720x480@60Hz */ 658 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 659 798, 858, 0, 480, 489, 495, 525, 0, 660 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 661 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 662 /* 3 - 720x480@60Hz */ 663 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 664 798, 858, 0, 480, 489, 495, 525, 0, 665 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 666 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 667 /* 4 - 1280x720@60Hz */ 668 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 669 1430, 1650, 0, 720, 725, 730, 750, 0, 670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 671 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 672 /* 5 - 1920x1080i@60Hz */ 673 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 674 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 675 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 676 DRM_MODE_FLAG_INTERLACE), 677 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 678 /* 6 - 720(1440)x480i@60Hz */ 679 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 680 801, 858, 0, 480, 488, 494, 525, 0, 681 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 682 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 684 /* 7 - 720(1440)x480i@60Hz */ 685 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 686 801, 858, 0, 480, 488, 494, 525, 0, 687 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 688 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 690 /* 8 - 720(1440)x240@60Hz */ 691 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 692 801, 858, 0, 240, 244, 247, 262, 0, 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 694 DRM_MODE_FLAG_DBLCLK), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 696 /* 9 - 720(1440)x240@60Hz */ 697 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 698 801, 858, 0, 240, 244, 247, 262, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 700 DRM_MODE_FLAG_DBLCLK), 701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 702 /* 10 - 2880x480i@60Hz */ 703 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 704 3204, 3432, 0, 480, 488, 494, 525, 0, 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 706 DRM_MODE_FLAG_INTERLACE), 707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 708 /* 11 - 2880x480i@60Hz */ 709 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 710 3204, 3432, 0, 480, 488, 494, 525, 0, 711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 712 DRM_MODE_FLAG_INTERLACE), 713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 714 /* 12 - 2880x240@60Hz */ 715 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 716 3204, 3432, 0, 240, 244, 247, 262, 0, 717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 719 /* 13 - 2880x240@60Hz */ 720 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 721 3204, 3432, 0, 240, 244, 247, 262, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 724 /* 14 - 1440x480@60Hz */ 725 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 726 1596, 1716, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 15 - 1440x480@60Hz */ 730 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 731 1596, 1716, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 16 - 1920x1080@60Hz */ 735 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 736 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 17 - 720x576@50Hz */ 740 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 741 796, 864, 0, 576, 581, 586, 625, 0, 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 743 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 744 /* 18 - 720x576@50Hz */ 745 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 746 796, 864, 0, 576, 581, 586, 625, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 748 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 749 /* 19 - 1280x720@50Hz */ 750 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 751 1760, 1980, 0, 720, 725, 730, 750, 0, 752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 753 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 20 - 1920x1080i@50Hz */ 755 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 756 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 758 DRM_MODE_FLAG_INTERLACE), 759 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 760 /* 21 - 720(1440)x576i@50Hz */ 761 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 762 795, 864, 0, 576, 580, 586, 625, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 764 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 766 /* 22 - 720(1440)x576i@50Hz */ 767 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 768 795, 864, 0, 576, 580, 586, 625, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 770 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 772 /* 23 - 720(1440)x288@50Hz */ 773 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 774 795, 864, 0, 288, 290, 293, 312, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 776 DRM_MODE_FLAG_DBLCLK), 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 778 /* 24 - 720(1440)x288@50Hz */ 779 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 780 795, 864, 0, 288, 290, 293, 312, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_DBLCLK), 783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 784 /* 25 - 2880x576i@50Hz */ 785 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 786 3180, 3456, 0, 576, 580, 586, 625, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_INTERLACE), 789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 790 /* 26 - 2880x576i@50Hz */ 791 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 792 3180, 3456, 0, 576, 580, 586, 625, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 794 DRM_MODE_FLAG_INTERLACE), 795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 796 /* 27 - 2880x288@50Hz */ 797 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 798 3180, 3456, 0, 288, 290, 293, 312, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 801 /* 28 - 2880x288@50Hz */ 802 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 803 3180, 3456, 0, 288, 290, 293, 312, 0, 804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 805 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 29 - 1440x576@50Hz */ 807 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 808 1592, 1728, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 30 - 1440x576@50Hz */ 812 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 813 1592, 1728, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 31 - 1920x1080@50Hz */ 817 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 818 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 32 - 1920x1080@24Hz */ 822 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 823 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 825 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 33 - 1920x1080@25Hz */ 827 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 828 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 830 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 831 /* 34 - 1920x1080@30Hz */ 832 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 833 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 835 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 35 - 2880x480@60Hz */ 837 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 838 3192, 3432, 0, 480, 489, 495, 525, 0, 839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 840 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 841 /* 36 - 2880x480@60Hz */ 842 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 843 3192, 3432, 0, 480, 489, 495, 525, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 845 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 37 - 2880x576@50Hz */ 847 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 848 3184, 3456, 0, 576, 581, 586, 625, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 851 /* 38 - 2880x576@50Hz */ 852 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 853 3184, 3456, 0, 576, 581, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 856 /* 39 - 1920x1080i@50Hz */ 857 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 858 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 40 - 1920x1080i@100Hz */ 863 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 864 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 866 DRM_MODE_FLAG_INTERLACE), 867 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 868 /* 41 - 1280x720@100Hz */ 869 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 870 1760, 1980, 0, 720, 725, 730, 750, 0, 871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 872 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 42 - 720x576@100Hz */ 874 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 875 796, 864, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 43 - 720x576@100Hz */ 879 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 880 796, 864, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 44 - 720(1440)x576i@100Hz */ 884 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 885 795, 864, 0, 576, 580, 586, 625, 0, 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 887 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 888 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 889 /* 45 - 720(1440)x576i@100Hz */ 890 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 891 795, 864, 0, 576, 580, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 893 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 46 - 1920x1080i@120Hz */ 896 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 897 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 899 DRM_MODE_FLAG_INTERLACE), 900 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 47 - 1280x720@120Hz */ 902 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 903 1430, 1650, 0, 720, 725, 730, 750, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 905 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 48 - 720x480@120Hz */ 907 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 908 798, 858, 0, 480, 489, 495, 525, 0, 909 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 910 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 911 /* 49 - 720x480@120Hz */ 912 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 913 798, 858, 0, 480, 489, 495, 525, 0, 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 915 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 916 /* 50 - 720(1440)x480i@120Hz */ 917 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 918 801, 858, 0, 480, 488, 494, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 920 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 921 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 922 /* 51 - 720(1440)x480i@120Hz */ 923 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 924 801, 858, 0, 480, 488, 494, 525, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 926 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 52 - 720x576@200Hz */ 929 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 930 796, 864, 0, 576, 581, 586, 625, 0, 931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 932 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 933 /* 53 - 720x576@200Hz */ 934 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 935 796, 864, 0, 576, 581, 586, 625, 0, 936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 937 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 938 /* 54 - 720(1440)x576i@200Hz */ 939 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 940 795, 864, 0, 576, 580, 586, 625, 0, 941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 942 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 943 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 944 /* 55 - 720(1440)x576i@200Hz */ 945 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 946 795, 864, 0, 576, 580, 586, 625, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 948 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 56 - 720x480@240Hz */ 951 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 952 798, 858, 0, 480, 489, 495, 525, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 954 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 955 /* 57 - 720x480@240Hz */ 956 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 957 798, 858, 0, 480, 489, 495, 525, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 959 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 960 /* 58 - 720(1440)x480i@240 */ 961 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 962 801, 858, 0, 480, 488, 494, 525, 0, 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 964 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 965 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 966 /* 59 - 720(1440)x480i@240 */ 967 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 968 801, 858, 0, 480, 488, 494, 525, 0, 969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 60 - 1280x720@24Hz */ 973 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 974 3080, 3300, 0, 720, 725, 730, 750, 0, 975 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 976 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 977 /* 61 - 1280x720@25Hz */ 978 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 979 3740, 3960, 0, 720, 725, 730, 750, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 981 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 62 - 1280x720@30Hz */ 983 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 984 3080, 3300, 0, 720, 725, 730, 750, 0, 985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 986 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 987 /* 63 - 1920x1080@120Hz */ 988 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 989 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 991 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 64 - 1920x1080@100Hz */ 993 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 994 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 995 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 996 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 }; 998 999 /* 1000 * HDMI 1.4 4k modes. Index using the VIC. 1001 */ 1002 static const struct drm_display_mode edid_4k_modes[] = { 1003 /* 0 - dummy, VICs start at 1 */ 1004 { }, 1005 /* 1 - 3840x2160@30Hz */ 1006 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1007 3840, 4016, 4104, 4400, 0, 1008 2160, 2168, 2178, 2250, 0, 1009 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1010 .vrefresh = 30, }, 1011 /* 2 - 3840x2160@25Hz */ 1012 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1013 3840, 4896, 4984, 5280, 0, 1014 2160, 2168, 2178, 2250, 0, 1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1016 .vrefresh = 25, }, 1017 /* 3 - 3840x2160@24Hz */ 1018 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1019 3840, 5116, 5204, 5500, 0, 1020 2160, 2168, 2178, 2250, 0, 1021 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1022 .vrefresh = 24, }, 1023 /* 4 - 4096x2160@24Hz (SMPTE) */ 1024 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1025 4096, 5116, 5204, 5500, 0, 1026 2160, 2168, 2178, 2250, 0, 1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1028 .vrefresh = 24, }, 1029 }; 1030 1031 /*** DDC fetch and block validation ***/ 1032 1033 static const u8 edid_header[] = { 1034 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1035 }; 1036 1037 /** 1038 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1039 * @raw_edid: pointer to raw base EDID block 1040 * 1041 * Sanity check the header of the base EDID block. 1042 * 1043 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1044 */ 1045 int drm_edid_header_is_valid(const u8 *raw_edid) 1046 { 1047 int i, score = 0; 1048 1049 for (i = 0; i < sizeof(edid_header); i++) 1050 if (raw_edid[i] == edid_header[i]) 1051 score++; 1052 1053 return score; 1054 } 1055 EXPORT_SYMBOL(drm_edid_header_is_valid); 1056 1057 static int edid_fixup __read_mostly = 6; 1058 module_param_named(edid_fixup, edid_fixup, int, 0400); 1059 MODULE_PARM_DESC(edid_fixup, 1060 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1061 1062 static void drm_get_displayid(struct drm_connector *connector, 1063 struct edid *edid); 1064 1065 static int drm_edid_block_checksum(const u8 *raw_edid) 1066 { 1067 int i; 1068 u8 csum = 0; 1069 for (i = 0; i < EDID_LENGTH; i++) 1070 csum += raw_edid[i]; 1071 1072 return csum; 1073 } 1074 1075 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1076 { 1077 if (memchr_inv(in_edid, 0, length)) 1078 return false; 1079 1080 return true; 1081 } 1082 1083 /** 1084 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1085 * @raw_edid: pointer to raw EDID block 1086 * @block: type of block to validate (0 for base, extension otherwise) 1087 * @print_bad_edid: if true, dump bad EDID blocks to the console 1088 * @edid_corrupt: if true, the header or checksum is invalid 1089 * 1090 * Validate a base or extension EDID block and optionally dump bad blocks to 1091 * the console. 1092 * 1093 * Return: True if the block is valid, false otherwise. 1094 */ 1095 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1096 bool *edid_corrupt) 1097 { 1098 u8 csum; 1099 struct edid *edid = (struct edid *)raw_edid; 1100 1101 if (WARN_ON(!raw_edid)) 1102 return false; 1103 1104 if (edid_fixup > 8 || edid_fixup < 0) 1105 edid_fixup = 6; 1106 1107 if (block == 0) { 1108 int score = drm_edid_header_is_valid(raw_edid); 1109 if (score == 8) { 1110 if (edid_corrupt) 1111 *edid_corrupt = false; 1112 } else if (score >= edid_fixup) { 1113 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1114 * The corrupt flag needs to be set here otherwise, the 1115 * fix-up code here will correct the problem, the 1116 * checksum is correct and the test fails 1117 */ 1118 if (edid_corrupt) 1119 *edid_corrupt = true; 1120 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1121 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1122 } else { 1123 if (edid_corrupt) 1124 *edid_corrupt = true; 1125 goto bad; 1126 } 1127 } 1128 1129 csum = drm_edid_block_checksum(raw_edid); 1130 if (csum) { 1131 if (print_bad_edid) { 1132 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1133 } 1134 1135 if (edid_corrupt) 1136 *edid_corrupt = true; 1137 1138 /* allow CEA to slide through, switches mangle this */ 1139 if (raw_edid[0] != 0x02) 1140 goto bad; 1141 } 1142 1143 /* per-block-type checks */ 1144 switch (raw_edid[0]) { 1145 case 0: /* base */ 1146 if (edid->version != 1) { 1147 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1148 goto bad; 1149 } 1150 1151 if (edid->revision > 4) 1152 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1153 break; 1154 1155 default: 1156 break; 1157 } 1158 1159 return true; 1160 1161 bad: 1162 if (print_bad_edid) { 1163 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1164 printk(KERN_ERR "EDID block is all zeroes\n"); 1165 } else { 1166 printk(KERN_ERR "Raw EDID:\n"); 1167 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1168 raw_edid, EDID_LENGTH, false); 1169 } 1170 } 1171 return false; 1172 } 1173 EXPORT_SYMBOL(drm_edid_block_valid); 1174 1175 /** 1176 * drm_edid_is_valid - sanity check EDID data 1177 * @edid: EDID data 1178 * 1179 * Sanity-check an entire EDID record (including extensions) 1180 * 1181 * Return: True if the EDID data is valid, false otherwise. 1182 */ 1183 bool drm_edid_is_valid(struct edid *edid) 1184 { 1185 int i; 1186 u8 *raw = (u8 *)edid; 1187 1188 if (!edid) 1189 return false; 1190 1191 for (i = 0; i <= edid->extensions; i++) 1192 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1193 return false; 1194 1195 return true; 1196 } 1197 EXPORT_SYMBOL(drm_edid_is_valid); 1198 1199 #define DDC_SEGMENT_ADDR 0x30 1200 /** 1201 * drm_do_probe_ddc_edid() - get EDID information via I2C 1202 * @data: I2C device adapter 1203 * @buf: EDID data buffer to be filled 1204 * @block: 128 byte EDID block to start fetching from 1205 * @len: EDID data buffer length to fetch 1206 * 1207 * Try to fetch EDID information by calling I2C driver functions. 1208 * 1209 * Return: 0 on success or -1 on failure. 1210 */ 1211 static int 1212 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1213 { 1214 struct i2c_adapter *adapter = data; 1215 unsigned char start = block * EDID_LENGTH; 1216 unsigned char segment = block >> 1; 1217 unsigned char xfers = segment ? 3 : 2; 1218 int ret, retries = 5; 1219 1220 /* 1221 * The core I2C driver will automatically retry the transfer if the 1222 * adapter reports EAGAIN. However, we find that bit-banging transfers 1223 * are susceptible to errors under a heavily loaded machine and 1224 * generate spurious NAKs and timeouts. Retrying the transfer 1225 * of the individual block a few times seems to overcome this. 1226 */ 1227 do { 1228 struct i2c_msg msgs[] = { 1229 { 1230 .addr = DDC_SEGMENT_ADDR, 1231 .flags = 0, 1232 .len = 1, 1233 .buf = &segment, 1234 }, { 1235 .addr = DDC_ADDR, 1236 .flags = 0, 1237 .len = 1, 1238 .buf = &start, 1239 }, { 1240 .addr = DDC_ADDR, 1241 .flags = I2C_M_RD, 1242 .len = len, 1243 .buf = buf, 1244 } 1245 }; 1246 1247 /* 1248 * Avoid sending the segment addr to not upset non-compliant 1249 * DDC monitors. 1250 */ 1251 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1252 1253 if (ret == -ENXIO) { 1254 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1255 adapter->name); 1256 break; 1257 } 1258 } while (ret != xfers && --retries); 1259 1260 return ret == xfers ? 0 : -1; 1261 } 1262 1263 /** 1264 * drm_do_get_edid - get EDID data using a custom EDID block read function 1265 * @connector: connector we're probing 1266 * @get_edid_block: EDID block read function 1267 * @data: private data passed to the block read function 1268 * 1269 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1270 * exposes a different interface to read EDID blocks this function can be used 1271 * to get EDID data using a custom block read function. 1272 * 1273 * As in the general case the DDC bus is accessible by the kernel at the I2C 1274 * level, drivers must make all reasonable efforts to expose it as an I2C 1275 * adapter and use drm_get_edid() instead of abusing this function. 1276 * 1277 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1278 */ 1279 struct edid *drm_do_get_edid(struct drm_connector *connector, 1280 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1281 size_t len), 1282 void *data) 1283 { 1284 int i, j = 0, valid_extensions = 0; 1285 u8 *block, *new; 1286 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1287 1288 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1289 return NULL; 1290 1291 /* base block fetch */ 1292 for (i = 0; i < 4; i++) { 1293 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1294 goto out; 1295 if (drm_edid_block_valid(block, 0, print_bad_edid, 1296 &connector->edid_corrupt)) 1297 break; 1298 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1299 connector->null_edid_counter++; 1300 goto carp; 1301 } 1302 } 1303 if (i == 4) 1304 goto carp; 1305 1306 /* if there's no extensions, we're done */ 1307 if (block[0x7e] == 0) 1308 return (struct edid *)block; 1309 1310 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1311 if (!new) 1312 goto out; 1313 block = new; 1314 1315 for (j = 1; j <= block[0x7e]; j++) { 1316 for (i = 0; i < 4; i++) { 1317 if (get_edid_block(data, 1318 block + (valid_extensions + 1) * EDID_LENGTH, 1319 j, EDID_LENGTH)) 1320 goto out; 1321 if (drm_edid_block_valid(block + (valid_extensions + 1) 1322 * EDID_LENGTH, j, 1323 print_bad_edid, 1324 NULL)) { 1325 valid_extensions++; 1326 break; 1327 } 1328 } 1329 1330 if (i == 4 && print_bad_edid) { 1331 dev_warn(connector->dev->dev, 1332 "%s: Ignoring invalid EDID block %d.\n", 1333 connector->name, j); 1334 1335 connector->bad_edid_counter++; 1336 } 1337 } 1338 1339 if (valid_extensions != block[0x7e]) { 1340 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1341 block[0x7e] = valid_extensions; 1342 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1343 if (!new) 1344 goto out; 1345 block = new; 1346 } 1347 1348 return (struct edid *)block; 1349 1350 carp: 1351 if (print_bad_edid) { 1352 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1353 connector->name, j); 1354 } 1355 connector->bad_edid_counter++; 1356 1357 out: 1358 kfree(block); 1359 return NULL; 1360 } 1361 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1362 1363 /** 1364 * drm_probe_ddc() - probe DDC presence 1365 * @adapter: I2C adapter to probe 1366 * 1367 * Return: True on success, false on failure. 1368 */ 1369 bool 1370 drm_probe_ddc(struct i2c_adapter *adapter) 1371 { 1372 unsigned char out; 1373 1374 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1375 } 1376 EXPORT_SYMBOL(drm_probe_ddc); 1377 1378 /** 1379 * drm_get_edid - get EDID data, if available 1380 * @connector: connector we're probing 1381 * @adapter: I2C adapter to use for DDC 1382 * 1383 * Poke the given I2C channel to grab EDID data if possible. If found, 1384 * attach it to the connector. 1385 * 1386 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1387 */ 1388 struct edid *drm_get_edid(struct drm_connector *connector, 1389 struct i2c_adapter *adapter) 1390 { 1391 struct edid *edid; 1392 1393 if (!drm_probe_ddc(adapter)) 1394 return NULL; 1395 1396 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1397 if (edid) 1398 drm_get_displayid(connector, edid); 1399 return edid; 1400 } 1401 EXPORT_SYMBOL(drm_get_edid); 1402 1403 /** 1404 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1405 * @connector: connector we're probing 1406 * @adapter: I2C adapter to use for DDC 1407 * 1408 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1409 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1410 * switch DDC to the GPU which is retrieving EDID. 1411 * 1412 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1413 */ 1414 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1415 struct i2c_adapter *adapter) 1416 { 1417 struct pci_dev *pdev = connector->dev->pdev; 1418 struct edid *edid; 1419 1420 vga_switcheroo_lock_ddc(pdev); 1421 edid = drm_get_edid(connector, adapter); 1422 vga_switcheroo_unlock_ddc(pdev); 1423 1424 return edid; 1425 } 1426 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1427 1428 /** 1429 * drm_edid_duplicate - duplicate an EDID and the extensions 1430 * @edid: EDID to duplicate 1431 * 1432 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1433 */ 1434 struct edid *drm_edid_duplicate(const struct edid *edid) 1435 { 1436 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1437 } 1438 EXPORT_SYMBOL(drm_edid_duplicate); 1439 1440 /*** EDID parsing ***/ 1441 1442 /** 1443 * edid_vendor - match a string against EDID's obfuscated vendor field 1444 * @edid: EDID to match 1445 * @vendor: vendor string 1446 * 1447 * Returns true if @vendor is in @edid, false otherwise 1448 */ 1449 static bool edid_vendor(struct edid *edid, char *vendor) 1450 { 1451 char edid_vendor[3]; 1452 1453 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1454 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1455 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1456 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1457 1458 return !strncmp(edid_vendor, vendor, 3); 1459 } 1460 1461 /** 1462 * edid_get_quirks - return quirk flags for a given EDID 1463 * @edid: EDID to process 1464 * 1465 * This tells subsequent routines what fixes they need to apply. 1466 */ 1467 static u32 edid_get_quirks(struct edid *edid) 1468 { 1469 struct edid_quirk *quirk; 1470 int i; 1471 1472 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1473 quirk = &edid_quirk_list[i]; 1474 1475 if (edid_vendor(edid, quirk->vendor) && 1476 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1477 return quirk->quirks; 1478 } 1479 1480 return 0; 1481 } 1482 1483 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1484 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1485 1486 /** 1487 * edid_fixup_preferred - set preferred modes based on quirk list 1488 * @connector: has mode list to fix up 1489 * @quirks: quirks list 1490 * 1491 * Walk the mode list for @connector, clearing the preferred status 1492 * on existing modes and setting it anew for the right mode ala @quirks. 1493 */ 1494 static void edid_fixup_preferred(struct drm_connector *connector, 1495 u32 quirks) 1496 { 1497 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1498 int target_refresh = 0; 1499 int cur_vrefresh, preferred_vrefresh; 1500 1501 if (list_empty(&connector->probed_modes)) 1502 return; 1503 1504 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1505 target_refresh = 60; 1506 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1507 target_refresh = 75; 1508 1509 preferred_mode = list_first_entry(&connector->probed_modes, 1510 struct drm_display_mode, head); 1511 1512 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1513 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1514 1515 if (cur_mode == preferred_mode) 1516 continue; 1517 1518 /* Largest mode is preferred */ 1519 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1520 preferred_mode = cur_mode; 1521 1522 cur_vrefresh = cur_mode->vrefresh ? 1523 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1524 preferred_vrefresh = preferred_mode->vrefresh ? 1525 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1526 /* At a given size, try to get closest to target refresh */ 1527 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1528 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1529 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1530 preferred_mode = cur_mode; 1531 } 1532 } 1533 1534 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1535 } 1536 1537 static bool 1538 mode_is_rb(const struct drm_display_mode *mode) 1539 { 1540 return (mode->htotal - mode->hdisplay == 160) && 1541 (mode->hsync_end - mode->hdisplay == 80) && 1542 (mode->hsync_end - mode->hsync_start == 32) && 1543 (mode->vsync_start - mode->vdisplay == 3); 1544 } 1545 1546 /* 1547 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1548 * @dev: Device to duplicate against 1549 * @hsize: Mode width 1550 * @vsize: Mode height 1551 * @fresh: Mode refresh rate 1552 * @rb: Mode reduced-blanking-ness 1553 * 1554 * Walk the DMT mode list looking for a match for the given parameters. 1555 * 1556 * Return: A newly allocated copy of the mode, or NULL if not found. 1557 */ 1558 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1559 int hsize, int vsize, int fresh, 1560 bool rb) 1561 { 1562 int i; 1563 1564 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1565 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1566 if (hsize != ptr->hdisplay) 1567 continue; 1568 if (vsize != ptr->vdisplay) 1569 continue; 1570 if (fresh != drm_mode_vrefresh(ptr)) 1571 continue; 1572 if (rb != mode_is_rb(ptr)) 1573 continue; 1574 1575 return drm_mode_duplicate(dev, ptr); 1576 } 1577 1578 return NULL; 1579 } 1580 EXPORT_SYMBOL(drm_mode_find_dmt); 1581 1582 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1583 1584 static void 1585 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1586 { 1587 int i, n = 0; 1588 u8 d = ext[0x02]; 1589 u8 *det_base = ext + d; 1590 1591 n = (127 - d) / 18; 1592 for (i = 0; i < n; i++) 1593 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1594 } 1595 1596 static void 1597 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1598 { 1599 unsigned int i, n = min((int)ext[0x02], 6); 1600 u8 *det_base = ext + 5; 1601 1602 if (ext[0x01] != 1) 1603 return; /* unknown version */ 1604 1605 for (i = 0; i < n; i++) 1606 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1607 } 1608 1609 static void 1610 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1611 { 1612 int i; 1613 struct edid *edid = (struct edid *)raw_edid; 1614 1615 if (edid == NULL) 1616 return; 1617 1618 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1619 cb(&(edid->detailed_timings[i]), closure); 1620 1621 for (i = 1; i <= raw_edid[0x7e]; i++) { 1622 u8 *ext = raw_edid + (i * EDID_LENGTH); 1623 switch (*ext) { 1624 case CEA_EXT: 1625 cea_for_each_detailed_block(ext, cb, closure); 1626 break; 1627 case VTB_EXT: 1628 vtb_for_each_detailed_block(ext, cb, closure); 1629 break; 1630 default: 1631 break; 1632 } 1633 } 1634 } 1635 1636 static void 1637 is_rb(struct detailed_timing *t, void *data) 1638 { 1639 u8 *r = (u8 *)t; 1640 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1641 if (r[15] & 0x10) 1642 *(bool *)data = true; 1643 } 1644 1645 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1646 static bool 1647 drm_monitor_supports_rb(struct edid *edid) 1648 { 1649 if (edid->revision >= 4) { 1650 bool ret = false; 1651 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1652 return ret; 1653 } 1654 1655 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1656 } 1657 1658 static void 1659 find_gtf2(struct detailed_timing *t, void *data) 1660 { 1661 u8 *r = (u8 *)t; 1662 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1663 *(u8 **)data = r; 1664 } 1665 1666 /* Secondary GTF curve kicks in above some break frequency */ 1667 static int 1668 drm_gtf2_hbreak(struct edid *edid) 1669 { 1670 u8 *r = NULL; 1671 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1672 return r ? (r[12] * 2) : 0; 1673 } 1674 1675 static int 1676 drm_gtf2_2c(struct edid *edid) 1677 { 1678 u8 *r = NULL; 1679 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1680 return r ? r[13] : 0; 1681 } 1682 1683 static int 1684 drm_gtf2_m(struct edid *edid) 1685 { 1686 u8 *r = NULL; 1687 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1688 return r ? (r[15] << 8) + r[14] : 0; 1689 } 1690 1691 static int 1692 drm_gtf2_k(struct edid *edid) 1693 { 1694 u8 *r = NULL; 1695 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1696 return r ? r[16] : 0; 1697 } 1698 1699 static int 1700 drm_gtf2_2j(struct edid *edid) 1701 { 1702 u8 *r = NULL; 1703 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1704 return r ? r[17] : 0; 1705 } 1706 1707 /** 1708 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1709 * @edid: EDID block to scan 1710 */ 1711 static int standard_timing_level(struct edid *edid) 1712 { 1713 if (edid->revision >= 2) { 1714 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1715 return LEVEL_CVT; 1716 if (drm_gtf2_hbreak(edid)) 1717 return LEVEL_GTF2; 1718 return LEVEL_GTF; 1719 } 1720 return LEVEL_DMT; 1721 } 1722 1723 /* 1724 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1725 * monitors fill with ascii space (0x20) instead. 1726 */ 1727 static int 1728 bad_std_timing(u8 a, u8 b) 1729 { 1730 return (a == 0x00 && b == 0x00) || 1731 (a == 0x01 && b == 0x01) || 1732 (a == 0x20 && b == 0x20); 1733 } 1734 1735 /** 1736 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1737 * @connector: connector of for the EDID block 1738 * @edid: EDID block to scan 1739 * @t: standard timing params 1740 * 1741 * Take the standard timing params (in this case width, aspect, and refresh) 1742 * and convert them into a real mode using CVT/GTF/DMT. 1743 */ 1744 static struct drm_display_mode * 1745 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1746 struct std_timing *t) 1747 { 1748 struct drm_device *dev = connector->dev; 1749 struct drm_display_mode *m, *mode = NULL; 1750 int hsize, vsize; 1751 int vrefresh_rate; 1752 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1753 >> EDID_TIMING_ASPECT_SHIFT; 1754 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1755 >> EDID_TIMING_VFREQ_SHIFT; 1756 int timing_level = standard_timing_level(edid); 1757 1758 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1759 return NULL; 1760 1761 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1762 hsize = t->hsize * 8 + 248; 1763 /* vrefresh_rate = vfreq + 60 */ 1764 vrefresh_rate = vfreq + 60; 1765 /* the vdisplay is calculated based on the aspect ratio */ 1766 if (aspect_ratio == 0) { 1767 if (edid->revision < 3) 1768 vsize = hsize; 1769 else 1770 vsize = (hsize * 10) / 16; 1771 } else if (aspect_ratio == 1) 1772 vsize = (hsize * 3) / 4; 1773 else if (aspect_ratio == 2) 1774 vsize = (hsize * 4) / 5; 1775 else 1776 vsize = (hsize * 9) / 16; 1777 1778 /* HDTV hack, part 1 */ 1779 if (vrefresh_rate == 60 && 1780 ((hsize == 1360 && vsize == 765) || 1781 (hsize == 1368 && vsize == 769))) { 1782 hsize = 1366; 1783 vsize = 768; 1784 } 1785 1786 /* 1787 * If this connector already has a mode for this size and refresh 1788 * rate (because it came from detailed or CVT info), use that 1789 * instead. This way we don't have to guess at interlace or 1790 * reduced blanking. 1791 */ 1792 list_for_each_entry(m, &connector->probed_modes, head) 1793 if (m->hdisplay == hsize && m->vdisplay == vsize && 1794 drm_mode_vrefresh(m) == vrefresh_rate) 1795 return NULL; 1796 1797 /* HDTV hack, part 2 */ 1798 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1799 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1800 false); 1801 mode->hdisplay = 1366; 1802 mode->hsync_start = mode->hsync_start - 1; 1803 mode->hsync_end = mode->hsync_end - 1; 1804 return mode; 1805 } 1806 1807 /* check whether it can be found in default mode table */ 1808 if (drm_monitor_supports_rb(edid)) { 1809 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1810 true); 1811 if (mode) 1812 return mode; 1813 } 1814 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1815 if (mode) 1816 return mode; 1817 1818 /* okay, generate it */ 1819 switch (timing_level) { 1820 case LEVEL_DMT: 1821 break; 1822 case LEVEL_GTF: 1823 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1824 break; 1825 case LEVEL_GTF2: 1826 /* 1827 * This is potentially wrong if there's ever a monitor with 1828 * more than one ranges section, each claiming a different 1829 * secondary GTF curve. Please don't do that. 1830 */ 1831 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1832 if (!mode) 1833 return NULL; 1834 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1835 drm_mode_destroy(dev, mode); 1836 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1837 vrefresh_rate, 0, 0, 1838 drm_gtf2_m(edid), 1839 drm_gtf2_2c(edid), 1840 drm_gtf2_k(edid), 1841 drm_gtf2_2j(edid)); 1842 } 1843 break; 1844 case LEVEL_CVT: 1845 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1846 false); 1847 break; 1848 } 1849 return mode; 1850 } 1851 1852 /* 1853 * EDID is delightfully ambiguous about how interlaced modes are to be 1854 * encoded. Our internal representation is of frame height, but some 1855 * HDTV detailed timings are encoded as field height. 1856 * 1857 * The format list here is from CEA, in frame size. Technically we 1858 * should be checking refresh rate too. Whatever. 1859 */ 1860 static void 1861 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1862 struct detailed_pixel_timing *pt) 1863 { 1864 int i; 1865 static const struct { 1866 int w, h; 1867 } cea_interlaced[] = { 1868 { 1920, 1080 }, 1869 { 720, 480 }, 1870 { 1440, 480 }, 1871 { 2880, 480 }, 1872 { 720, 576 }, 1873 { 1440, 576 }, 1874 { 2880, 576 }, 1875 }; 1876 1877 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1878 return; 1879 1880 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1881 if ((mode->hdisplay == cea_interlaced[i].w) && 1882 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1883 mode->vdisplay *= 2; 1884 mode->vsync_start *= 2; 1885 mode->vsync_end *= 2; 1886 mode->vtotal *= 2; 1887 mode->vtotal |= 1; 1888 } 1889 } 1890 1891 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1892 } 1893 1894 /** 1895 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1896 * @dev: DRM device (needed to create new mode) 1897 * @edid: EDID block 1898 * @timing: EDID detailed timing info 1899 * @quirks: quirks to apply 1900 * 1901 * An EDID detailed timing block contains enough info for us to create and 1902 * return a new struct drm_display_mode. 1903 */ 1904 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1905 struct edid *edid, 1906 struct detailed_timing *timing, 1907 u32 quirks) 1908 { 1909 struct drm_display_mode *mode; 1910 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1911 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1912 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1913 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1914 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1915 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1916 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1917 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1918 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1919 1920 /* ignore tiny modes */ 1921 if (hactive < 64 || vactive < 64) 1922 return NULL; 1923 1924 if (pt->misc & DRM_EDID_PT_STEREO) { 1925 DRM_DEBUG_KMS("stereo mode not supported\n"); 1926 return NULL; 1927 } 1928 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1929 DRM_DEBUG_KMS("composite sync not supported\n"); 1930 } 1931 1932 /* it is incorrect if hsync/vsync width is zero */ 1933 if (!hsync_pulse_width || !vsync_pulse_width) { 1934 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1935 "Wrong Hsync/Vsync pulse width\n"); 1936 return NULL; 1937 } 1938 1939 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1940 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1941 if (!mode) 1942 return NULL; 1943 1944 goto set_size; 1945 } 1946 1947 mode = drm_mode_create(dev); 1948 if (!mode) 1949 return NULL; 1950 1951 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1952 timing->pixel_clock = cpu_to_le16(1088); 1953 1954 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1955 1956 mode->hdisplay = hactive; 1957 mode->hsync_start = mode->hdisplay + hsync_offset; 1958 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1959 mode->htotal = mode->hdisplay + hblank; 1960 1961 mode->vdisplay = vactive; 1962 mode->vsync_start = mode->vdisplay + vsync_offset; 1963 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1964 mode->vtotal = mode->vdisplay + vblank; 1965 1966 /* Some EDIDs have bogus h/vtotal values */ 1967 if (mode->hsync_end > mode->htotal) 1968 mode->htotal = mode->hsync_end + 1; 1969 if (mode->vsync_end > mode->vtotal) 1970 mode->vtotal = mode->vsync_end + 1; 1971 1972 drm_mode_do_interlace_quirk(mode, pt); 1973 1974 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1975 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1976 } 1977 1978 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1979 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1980 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1981 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1982 1983 set_size: 1984 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1985 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1986 1987 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1988 mode->width_mm *= 10; 1989 mode->height_mm *= 10; 1990 } 1991 1992 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1993 mode->width_mm = edid->width_cm * 10; 1994 mode->height_mm = edid->height_cm * 10; 1995 } 1996 1997 mode->type = DRM_MODE_TYPE_DRIVER; 1998 mode->vrefresh = drm_mode_vrefresh(mode); 1999 drm_mode_set_name(mode); 2000 2001 return mode; 2002 } 2003 2004 static bool 2005 mode_in_hsync_range(const struct drm_display_mode *mode, 2006 struct edid *edid, u8 *t) 2007 { 2008 int hsync, hmin, hmax; 2009 2010 hmin = t[7]; 2011 if (edid->revision >= 4) 2012 hmin += ((t[4] & 0x04) ? 255 : 0); 2013 hmax = t[8]; 2014 if (edid->revision >= 4) 2015 hmax += ((t[4] & 0x08) ? 255 : 0); 2016 hsync = drm_mode_hsync(mode); 2017 2018 return (hsync <= hmax && hsync >= hmin); 2019 } 2020 2021 static bool 2022 mode_in_vsync_range(const struct drm_display_mode *mode, 2023 struct edid *edid, u8 *t) 2024 { 2025 int vsync, vmin, vmax; 2026 2027 vmin = t[5]; 2028 if (edid->revision >= 4) 2029 vmin += ((t[4] & 0x01) ? 255 : 0); 2030 vmax = t[6]; 2031 if (edid->revision >= 4) 2032 vmax += ((t[4] & 0x02) ? 255 : 0); 2033 vsync = drm_mode_vrefresh(mode); 2034 2035 return (vsync <= vmax && vsync >= vmin); 2036 } 2037 2038 static u32 2039 range_pixel_clock(struct edid *edid, u8 *t) 2040 { 2041 /* unspecified */ 2042 if (t[9] == 0 || t[9] == 255) 2043 return 0; 2044 2045 /* 1.4 with CVT support gives us real precision, yay */ 2046 if (edid->revision >= 4 && t[10] == 0x04) 2047 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2048 2049 /* 1.3 is pathetic, so fuzz up a bit */ 2050 return t[9] * 10000 + 5001; 2051 } 2052 2053 static bool 2054 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2055 struct detailed_timing *timing) 2056 { 2057 u32 max_clock; 2058 u8 *t = (u8 *)timing; 2059 2060 if (!mode_in_hsync_range(mode, edid, t)) 2061 return false; 2062 2063 if (!mode_in_vsync_range(mode, edid, t)) 2064 return false; 2065 2066 if ((max_clock = range_pixel_clock(edid, t))) 2067 if (mode->clock > max_clock) 2068 return false; 2069 2070 /* 1.4 max horizontal check */ 2071 if (edid->revision >= 4 && t[10] == 0x04) 2072 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2073 return false; 2074 2075 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2076 return false; 2077 2078 return true; 2079 } 2080 2081 static bool valid_inferred_mode(const struct drm_connector *connector, 2082 const struct drm_display_mode *mode) 2083 { 2084 const struct drm_display_mode *m; 2085 bool ok = false; 2086 2087 list_for_each_entry(m, &connector->probed_modes, head) { 2088 if (mode->hdisplay == m->hdisplay && 2089 mode->vdisplay == m->vdisplay && 2090 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2091 return false; /* duplicated */ 2092 if (mode->hdisplay <= m->hdisplay && 2093 mode->vdisplay <= m->vdisplay) 2094 ok = true; 2095 } 2096 return ok; 2097 } 2098 2099 static int 2100 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2101 struct detailed_timing *timing) 2102 { 2103 int i, modes = 0; 2104 struct drm_display_mode *newmode; 2105 struct drm_device *dev = connector->dev; 2106 2107 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2108 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2109 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2110 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2111 if (newmode) { 2112 drm_mode_probed_add(connector, newmode); 2113 modes++; 2114 } 2115 } 2116 } 2117 2118 return modes; 2119 } 2120 2121 /* fix up 1366x768 mode from 1368x768; 2122 * GFT/CVT can't express 1366 width which isn't dividable by 8 2123 */ 2124 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2125 { 2126 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2127 mode->hdisplay = 1366; 2128 mode->hsync_start--; 2129 mode->hsync_end--; 2130 drm_mode_set_name(mode); 2131 } 2132 } 2133 2134 static int 2135 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2136 struct detailed_timing *timing) 2137 { 2138 int i, modes = 0; 2139 struct drm_display_mode *newmode; 2140 struct drm_device *dev = connector->dev; 2141 2142 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2143 const struct minimode *m = &extra_modes[i]; 2144 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2145 if (!newmode) 2146 return modes; 2147 2148 fixup_mode_1366x768(newmode); 2149 if (!mode_in_range(newmode, edid, timing) || 2150 !valid_inferred_mode(connector, newmode)) { 2151 drm_mode_destroy(dev, newmode); 2152 continue; 2153 } 2154 2155 drm_mode_probed_add(connector, newmode); 2156 modes++; 2157 } 2158 2159 return modes; 2160 } 2161 2162 static int 2163 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2164 struct detailed_timing *timing) 2165 { 2166 int i, modes = 0; 2167 struct drm_display_mode *newmode; 2168 struct drm_device *dev = connector->dev; 2169 bool rb = drm_monitor_supports_rb(edid); 2170 2171 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2172 const struct minimode *m = &extra_modes[i]; 2173 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2174 if (!newmode) 2175 return modes; 2176 2177 fixup_mode_1366x768(newmode); 2178 if (!mode_in_range(newmode, edid, timing) || 2179 !valid_inferred_mode(connector, newmode)) { 2180 drm_mode_destroy(dev, newmode); 2181 continue; 2182 } 2183 2184 drm_mode_probed_add(connector, newmode); 2185 modes++; 2186 } 2187 2188 return modes; 2189 } 2190 2191 static void 2192 do_inferred_modes(struct detailed_timing *timing, void *c) 2193 { 2194 struct detailed_mode_closure *closure = c; 2195 struct detailed_non_pixel *data = &timing->data.other_data; 2196 struct detailed_data_monitor_range *range = &data->data.range; 2197 2198 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2199 return; 2200 2201 closure->modes += drm_dmt_modes_for_range(closure->connector, 2202 closure->edid, 2203 timing); 2204 2205 if (!version_greater(closure->edid, 1, 1)) 2206 return; /* GTF not defined yet */ 2207 2208 switch (range->flags) { 2209 case 0x02: /* secondary gtf, XXX could do more */ 2210 case 0x00: /* default gtf */ 2211 closure->modes += drm_gtf_modes_for_range(closure->connector, 2212 closure->edid, 2213 timing); 2214 break; 2215 case 0x04: /* cvt, only in 1.4+ */ 2216 if (!version_greater(closure->edid, 1, 3)) 2217 break; 2218 2219 closure->modes += drm_cvt_modes_for_range(closure->connector, 2220 closure->edid, 2221 timing); 2222 break; 2223 case 0x01: /* just the ranges, no formula */ 2224 default: 2225 break; 2226 } 2227 } 2228 2229 static int 2230 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2231 { 2232 struct detailed_mode_closure closure = { 2233 .connector = connector, 2234 .edid = edid, 2235 }; 2236 2237 if (version_greater(edid, 1, 0)) 2238 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2239 &closure); 2240 2241 return closure.modes; 2242 } 2243 2244 static int 2245 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2246 { 2247 int i, j, m, modes = 0; 2248 struct drm_display_mode *mode; 2249 u8 *est = ((u8 *)timing) + 6; 2250 2251 for (i = 0; i < 6; i++) { 2252 for (j = 7; j >= 0; j--) { 2253 m = (i * 8) + (7 - j); 2254 if (m >= ARRAY_SIZE(est3_modes)) 2255 break; 2256 if (est[i] & (1 << j)) { 2257 mode = drm_mode_find_dmt(connector->dev, 2258 est3_modes[m].w, 2259 est3_modes[m].h, 2260 est3_modes[m].r, 2261 est3_modes[m].rb); 2262 if (mode) { 2263 drm_mode_probed_add(connector, mode); 2264 modes++; 2265 } 2266 } 2267 } 2268 } 2269 2270 return modes; 2271 } 2272 2273 static void 2274 do_established_modes(struct detailed_timing *timing, void *c) 2275 { 2276 struct detailed_mode_closure *closure = c; 2277 struct detailed_non_pixel *data = &timing->data.other_data; 2278 2279 if (data->type == EDID_DETAIL_EST_TIMINGS) 2280 closure->modes += drm_est3_modes(closure->connector, timing); 2281 } 2282 2283 /** 2284 * add_established_modes - get est. modes from EDID and add them 2285 * @connector: connector to add mode(s) to 2286 * @edid: EDID block to scan 2287 * 2288 * Each EDID block contains a bitmap of the supported "established modes" list 2289 * (defined above). Tease them out and add them to the global modes list. 2290 */ 2291 static int 2292 add_established_modes(struct drm_connector *connector, struct edid *edid) 2293 { 2294 struct drm_device *dev = connector->dev; 2295 unsigned long est_bits = edid->established_timings.t1 | 2296 (edid->established_timings.t2 << 8) | 2297 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2298 int i, modes = 0; 2299 struct detailed_mode_closure closure = { 2300 .connector = connector, 2301 .edid = edid, 2302 }; 2303 2304 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2305 if (est_bits & (1<<i)) { 2306 struct drm_display_mode *newmode; 2307 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2308 if (newmode) { 2309 drm_mode_probed_add(connector, newmode); 2310 modes++; 2311 } 2312 } 2313 } 2314 2315 if (version_greater(edid, 1, 0)) 2316 drm_for_each_detailed_block((u8 *)edid, 2317 do_established_modes, &closure); 2318 2319 return modes + closure.modes; 2320 } 2321 2322 static void 2323 do_standard_modes(struct detailed_timing *timing, void *c) 2324 { 2325 struct detailed_mode_closure *closure = c; 2326 struct detailed_non_pixel *data = &timing->data.other_data; 2327 struct drm_connector *connector = closure->connector; 2328 struct edid *edid = closure->edid; 2329 2330 if (data->type == EDID_DETAIL_STD_MODES) { 2331 int i; 2332 for (i = 0; i < 6; i++) { 2333 struct std_timing *std; 2334 struct drm_display_mode *newmode; 2335 2336 std = &data->data.timings[i]; 2337 newmode = drm_mode_std(connector, edid, std); 2338 if (newmode) { 2339 drm_mode_probed_add(connector, newmode); 2340 closure->modes++; 2341 } 2342 } 2343 } 2344 } 2345 2346 /** 2347 * add_standard_modes - get std. modes from EDID and add them 2348 * @connector: connector to add mode(s) to 2349 * @edid: EDID block to scan 2350 * 2351 * Standard modes can be calculated using the appropriate standard (DMT, 2352 * GTF or CVT. Grab them from @edid and add them to the list. 2353 */ 2354 static int 2355 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2356 { 2357 int i, modes = 0; 2358 struct detailed_mode_closure closure = { 2359 .connector = connector, 2360 .edid = edid, 2361 }; 2362 2363 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2364 struct drm_display_mode *newmode; 2365 2366 newmode = drm_mode_std(connector, edid, 2367 &edid->standard_timings[i]); 2368 if (newmode) { 2369 drm_mode_probed_add(connector, newmode); 2370 modes++; 2371 } 2372 } 2373 2374 if (version_greater(edid, 1, 0)) 2375 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2376 &closure); 2377 2378 /* XXX should also look for standard codes in VTB blocks */ 2379 2380 return modes + closure.modes; 2381 } 2382 2383 static int drm_cvt_modes(struct drm_connector *connector, 2384 struct detailed_timing *timing) 2385 { 2386 int i, j, modes = 0; 2387 struct drm_display_mode *newmode; 2388 struct drm_device *dev = connector->dev; 2389 struct cvt_timing *cvt; 2390 const int rates[] = { 60, 85, 75, 60, 50 }; 2391 const u8 empty[3] = { 0, 0, 0 }; 2392 2393 for (i = 0; i < 4; i++) { 2394 int uninitialized_var(width), height; 2395 cvt = &(timing->data.other_data.data.cvt[i]); 2396 2397 if (!memcmp(cvt->code, empty, 3)) 2398 continue; 2399 2400 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2401 switch (cvt->code[1] & 0x0c) { 2402 case 0x00: 2403 width = height * 4 / 3; 2404 break; 2405 case 0x04: 2406 width = height * 16 / 9; 2407 break; 2408 case 0x08: 2409 width = height * 16 / 10; 2410 break; 2411 case 0x0c: 2412 width = height * 15 / 9; 2413 break; 2414 } 2415 2416 for (j = 1; j < 5; j++) { 2417 if (cvt->code[2] & (1 << j)) { 2418 newmode = drm_cvt_mode(dev, width, height, 2419 rates[j], j == 0, 2420 false, false); 2421 if (newmode) { 2422 drm_mode_probed_add(connector, newmode); 2423 modes++; 2424 } 2425 } 2426 } 2427 } 2428 2429 return modes; 2430 } 2431 2432 static void 2433 do_cvt_mode(struct detailed_timing *timing, void *c) 2434 { 2435 struct detailed_mode_closure *closure = c; 2436 struct detailed_non_pixel *data = &timing->data.other_data; 2437 2438 if (data->type == EDID_DETAIL_CVT_3BYTE) 2439 closure->modes += drm_cvt_modes(closure->connector, timing); 2440 } 2441 2442 static int 2443 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2444 { 2445 struct detailed_mode_closure closure = { 2446 .connector = connector, 2447 .edid = edid, 2448 }; 2449 2450 if (version_greater(edid, 1, 2)) 2451 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2452 2453 /* XXX should also look for CVT codes in VTB blocks */ 2454 2455 return closure.modes; 2456 } 2457 2458 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2459 2460 static void 2461 do_detailed_mode(struct detailed_timing *timing, void *c) 2462 { 2463 struct detailed_mode_closure *closure = c; 2464 struct drm_display_mode *newmode; 2465 2466 if (timing->pixel_clock) { 2467 newmode = drm_mode_detailed(closure->connector->dev, 2468 closure->edid, timing, 2469 closure->quirks); 2470 if (!newmode) 2471 return; 2472 2473 if (closure->preferred) 2474 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2475 2476 /* 2477 * Detailed modes are limited to 10kHz pixel clock resolution, 2478 * so fix up anything that looks like CEA/HDMI mode, but the clock 2479 * is just slightly off. 2480 */ 2481 fixup_detailed_cea_mode_clock(newmode); 2482 2483 drm_mode_probed_add(closure->connector, newmode); 2484 closure->modes++; 2485 closure->preferred = 0; 2486 } 2487 } 2488 2489 /* 2490 * add_detailed_modes - Add modes from detailed timings 2491 * @connector: attached connector 2492 * @edid: EDID block to scan 2493 * @quirks: quirks to apply 2494 */ 2495 static int 2496 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2497 u32 quirks) 2498 { 2499 struct detailed_mode_closure closure = { 2500 .connector = connector, 2501 .edid = edid, 2502 .preferred = 1, 2503 .quirks = quirks, 2504 }; 2505 2506 if (closure.preferred && !version_greater(edid, 1, 3)) 2507 closure.preferred = 2508 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2509 2510 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2511 2512 return closure.modes; 2513 } 2514 2515 #define AUDIO_BLOCK 0x01 2516 #define VIDEO_BLOCK 0x02 2517 #define VENDOR_BLOCK 0x03 2518 #define SPEAKER_BLOCK 0x04 2519 #define VIDEO_CAPABILITY_BLOCK 0x07 2520 #define EDID_BASIC_AUDIO (1 << 6) 2521 #define EDID_CEA_YCRCB444 (1 << 5) 2522 #define EDID_CEA_YCRCB422 (1 << 4) 2523 #define EDID_CEA_VCDB_QS (1 << 6) 2524 2525 /* 2526 * Search EDID for CEA extension block. 2527 */ 2528 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2529 { 2530 u8 *edid_ext = NULL; 2531 int i; 2532 2533 /* No EDID or EDID extensions */ 2534 if (edid == NULL || edid->extensions == 0) 2535 return NULL; 2536 2537 /* Find CEA extension */ 2538 for (i = 0; i < edid->extensions; i++) { 2539 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2540 if (edid_ext[0] == ext_id) 2541 break; 2542 } 2543 2544 if (i == edid->extensions) 2545 return NULL; 2546 2547 return edid_ext; 2548 } 2549 2550 static u8 *drm_find_cea_extension(struct edid *edid) 2551 { 2552 return drm_find_edid_extension(edid, CEA_EXT); 2553 } 2554 2555 static u8 *drm_find_displayid_extension(struct edid *edid) 2556 { 2557 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2558 } 2559 2560 /* 2561 * Calculate the alternate clock for the CEA mode 2562 * (60Hz vs. 59.94Hz etc.) 2563 */ 2564 static unsigned int 2565 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2566 { 2567 unsigned int clock = cea_mode->clock; 2568 2569 if (cea_mode->vrefresh % 6 != 0) 2570 return clock; 2571 2572 /* 2573 * edid_cea_modes contains the 59.94Hz 2574 * variant for 240 and 480 line modes, 2575 * and the 60Hz variant otherwise. 2576 */ 2577 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2578 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2579 else 2580 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2581 2582 return clock; 2583 } 2584 2585 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2586 unsigned int clock_tolerance) 2587 { 2588 u8 vic; 2589 2590 if (!to_match->clock) 2591 return 0; 2592 2593 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2594 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2595 unsigned int clock1, clock2; 2596 2597 /* Check both 60Hz and 59.94Hz */ 2598 clock1 = cea_mode->clock; 2599 clock2 = cea_mode_alternate_clock(cea_mode); 2600 2601 if (abs(to_match->clock - clock1) > clock_tolerance && 2602 abs(to_match->clock - clock2) > clock_tolerance) 2603 continue; 2604 2605 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2606 return vic; 2607 } 2608 2609 return 0; 2610 } 2611 2612 /** 2613 * drm_match_cea_mode - look for a CEA mode matching given mode 2614 * @to_match: display mode 2615 * 2616 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2617 * mode. 2618 */ 2619 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2620 { 2621 u8 vic; 2622 2623 if (!to_match->clock) 2624 return 0; 2625 2626 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2627 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2628 unsigned int clock1, clock2; 2629 2630 /* Check both 60Hz and 59.94Hz */ 2631 clock1 = cea_mode->clock; 2632 clock2 = cea_mode_alternate_clock(cea_mode); 2633 2634 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2635 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2636 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2637 return vic; 2638 } 2639 return 0; 2640 } 2641 EXPORT_SYMBOL(drm_match_cea_mode); 2642 2643 static bool drm_valid_cea_vic(u8 vic) 2644 { 2645 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2646 } 2647 2648 /** 2649 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2650 * the input VIC from the CEA mode list 2651 * @video_code: ID given to each of the CEA modes 2652 * 2653 * Returns picture aspect ratio 2654 */ 2655 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2656 { 2657 return edid_cea_modes[video_code].picture_aspect_ratio; 2658 } 2659 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2660 2661 /* 2662 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2663 * specific block). 2664 * 2665 * It's almost like cea_mode_alternate_clock(), we just need to add an 2666 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2667 * one. 2668 */ 2669 static unsigned int 2670 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2671 { 2672 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2673 return hdmi_mode->clock; 2674 2675 return cea_mode_alternate_clock(hdmi_mode); 2676 } 2677 2678 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2679 unsigned int clock_tolerance) 2680 { 2681 u8 vic; 2682 2683 if (!to_match->clock) 2684 return 0; 2685 2686 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2687 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2688 unsigned int clock1, clock2; 2689 2690 /* Make sure to also match alternate clocks */ 2691 clock1 = hdmi_mode->clock; 2692 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2693 2694 if (abs(to_match->clock - clock1) > clock_tolerance && 2695 abs(to_match->clock - clock2) > clock_tolerance) 2696 continue; 2697 2698 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2699 return vic; 2700 } 2701 2702 return 0; 2703 } 2704 2705 /* 2706 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2707 * @to_match: display mode 2708 * 2709 * An HDMI mode is one defined in the HDMI vendor specific block. 2710 * 2711 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2712 */ 2713 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2714 { 2715 u8 vic; 2716 2717 if (!to_match->clock) 2718 return 0; 2719 2720 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2721 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2722 unsigned int clock1, clock2; 2723 2724 /* Make sure to also match alternate clocks */ 2725 clock1 = hdmi_mode->clock; 2726 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2727 2728 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2729 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2730 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2731 return vic; 2732 } 2733 return 0; 2734 } 2735 2736 static bool drm_valid_hdmi_vic(u8 vic) 2737 { 2738 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2739 } 2740 2741 static int 2742 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2743 { 2744 struct drm_device *dev = connector->dev; 2745 struct drm_display_mode *mode, *tmp; 2746 LIST_HEAD(list); 2747 int modes = 0; 2748 2749 /* Don't add CEA modes if the CEA extension block is missing */ 2750 if (!drm_find_cea_extension(edid)) 2751 return 0; 2752 2753 /* 2754 * Go through all probed modes and create a new mode 2755 * with the alternate clock for certain CEA modes. 2756 */ 2757 list_for_each_entry(mode, &connector->probed_modes, head) { 2758 const struct drm_display_mode *cea_mode = NULL; 2759 struct drm_display_mode *newmode; 2760 u8 vic = drm_match_cea_mode(mode); 2761 unsigned int clock1, clock2; 2762 2763 if (drm_valid_cea_vic(vic)) { 2764 cea_mode = &edid_cea_modes[vic]; 2765 clock2 = cea_mode_alternate_clock(cea_mode); 2766 } else { 2767 vic = drm_match_hdmi_mode(mode); 2768 if (drm_valid_hdmi_vic(vic)) { 2769 cea_mode = &edid_4k_modes[vic]; 2770 clock2 = hdmi_mode_alternate_clock(cea_mode); 2771 } 2772 } 2773 2774 if (!cea_mode) 2775 continue; 2776 2777 clock1 = cea_mode->clock; 2778 2779 if (clock1 == clock2) 2780 continue; 2781 2782 if (mode->clock != clock1 && mode->clock != clock2) 2783 continue; 2784 2785 newmode = drm_mode_duplicate(dev, cea_mode); 2786 if (!newmode) 2787 continue; 2788 2789 /* Carry over the stereo flags */ 2790 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2791 2792 /* 2793 * The current mode could be either variant. Make 2794 * sure to pick the "other" clock for the new mode. 2795 */ 2796 if (mode->clock != clock1) 2797 newmode->clock = clock1; 2798 else 2799 newmode->clock = clock2; 2800 2801 list_add_tail(&newmode->head, &list); 2802 } 2803 2804 list_for_each_entry_safe(mode, tmp, &list, head) { 2805 list_del(&mode->head); 2806 drm_mode_probed_add(connector, mode); 2807 modes++; 2808 } 2809 2810 return modes; 2811 } 2812 2813 static struct drm_display_mode * 2814 drm_display_mode_from_vic_index(struct drm_connector *connector, 2815 const u8 *video_db, u8 video_len, 2816 u8 video_index) 2817 { 2818 struct drm_device *dev = connector->dev; 2819 struct drm_display_mode *newmode; 2820 u8 vic; 2821 2822 if (video_db == NULL || video_index >= video_len) 2823 return NULL; 2824 2825 /* CEA modes are numbered 1..127 */ 2826 vic = (video_db[video_index] & 127); 2827 if (!drm_valid_cea_vic(vic)) 2828 return NULL; 2829 2830 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2831 if (!newmode) 2832 return NULL; 2833 2834 newmode->vrefresh = 0; 2835 2836 return newmode; 2837 } 2838 2839 static int 2840 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2841 { 2842 int i, modes = 0; 2843 2844 for (i = 0; i < len; i++) { 2845 struct drm_display_mode *mode; 2846 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2847 if (mode) { 2848 drm_mode_probed_add(connector, mode); 2849 modes++; 2850 } 2851 } 2852 2853 return modes; 2854 } 2855 2856 struct stereo_mandatory_mode { 2857 int width, height, vrefresh; 2858 unsigned int flags; 2859 }; 2860 2861 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2862 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2863 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2864 { 1920, 1080, 50, 2865 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2866 { 1920, 1080, 60, 2867 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2868 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2869 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2870 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2871 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2872 }; 2873 2874 static bool 2875 stereo_match_mandatory(const struct drm_display_mode *mode, 2876 const struct stereo_mandatory_mode *stereo_mode) 2877 { 2878 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2879 2880 return mode->hdisplay == stereo_mode->width && 2881 mode->vdisplay == stereo_mode->height && 2882 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2883 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2884 } 2885 2886 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2887 { 2888 struct drm_device *dev = connector->dev; 2889 const struct drm_display_mode *mode; 2890 struct list_head stereo_modes; 2891 int modes = 0, i; 2892 2893 INIT_LIST_HEAD(&stereo_modes); 2894 2895 list_for_each_entry(mode, &connector->probed_modes, head) { 2896 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2897 const struct stereo_mandatory_mode *mandatory; 2898 struct drm_display_mode *new_mode; 2899 2900 if (!stereo_match_mandatory(mode, 2901 &stereo_mandatory_modes[i])) 2902 continue; 2903 2904 mandatory = &stereo_mandatory_modes[i]; 2905 new_mode = drm_mode_duplicate(dev, mode); 2906 if (!new_mode) 2907 continue; 2908 2909 new_mode->flags |= mandatory->flags; 2910 list_add_tail(&new_mode->head, &stereo_modes); 2911 modes++; 2912 } 2913 } 2914 2915 list_splice_tail(&stereo_modes, &connector->probed_modes); 2916 2917 return modes; 2918 } 2919 2920 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2921 { 2922 struct drm_device *dev = connector->dev; 2923 struct drm_display_mode *newmode; 2924 2925 if (!drm_valid_hdmi_vic(vic)) { 2926 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2927 return 0; 2928 } 2929 2930 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2931 if (!newmode) 2932 return 0; 2933 2934 drm_mode_probed_add(connector, newmode); 2935 2936 return 1; 2937 } 2938 2939 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2940 const u8 *video_db, u8 video_len, u8 video_index) 2941 { 2942 struct drm_display_mode *newmode; 2943 int modes = 0; 2944 2945 if (structure & (1 << 0)) { 2946 newmode = drm_display_mode_from_vic_index(connector, video_db, 2947 video_len, 2948 video_index); 2949 if (newmode) { 2950 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2951 drm_mode_probed_add(connector, newmode); 2952 modes++; 2953 } 2954 } 2955 if (structure & (1 << 6)) { 2956 newmode = drm_display_mode_from_vic_index(connector, video_db, 2957 video_len, 2958 video_index); 2959 if (newmode) { 2960 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2961 drm_mode_probed_add(connector, newmode); 2962 modes++; 2963 } 2964 } 2965 if (structure & (1 << 8)) { 2966 newmode = drm_display_mode_from_vic_index(connector, video_db, 2967 video_len, 2968 video_index); 2969 if (newmode) { 2970 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2971 drm_mode_probed_add(connector, newmode); 2972 modes++; 2973 } 2974 } 2975 2976 return modes; 2977 } 2978 2979 /* 2980 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2981 * @connector: connector corresponding to the HDMI sink 2982 * @db: start of the CEA vendor specific block 2983 * @len: length of the CEA block payload, ie. one can access up to db[len] 2984 * 2985 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2986 * also adds the stereo 3d modes when applicable. 2987 */ 2988 static int 2989 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2990 const u8 *video_db, u8 video_len) 2991 { 2992 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2993 u8 vic_len, hdmi_3d_len = 0; 2994 u16 mask; 2995 u16 structure_all; 2996 2997 if (len < 8) 2998 goto out; 2999 3000 /* no HDMI_Video_Present */ 3001 if (!(db[8] & (1 << 5))) 3002 goto out; 3003 3004 /* Latency_Fields_Present */ 3005 if (db[8] & (1 << 7)) 3006 offset += 2; 3007 3008 /* I_Latency_Fields_Present */ 3009 if (db[8] & (1 << 6)) 3010 offset += 2; 3011 3012 /* the declared length is not long enough for the 2 first bytes 3013 * of additional video format capabilities */ 3014 if (len < (8 + offset + 2)) 3015 goto out; 3016 3017 /* 3D_Present */ 3018 offset++; 3019 if (db[8 + offset] & (1 << 7)) { 3020 modes += add_hdmi_mandatory_stereo_modes(connector); 3021 3022 /* 3D_Multi_present */ 3023 multi_present = (db[8 + offset] & 0x60) >> 5; 3024 } 3025 3026 offset++; 3027 vic_len = db[8 + offset] >> 5; 3028 hdmi_3d_len = db[8 + offset] & 0x1f; 3029 3030 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3031 u8 vic; 3032 3033 vic = db[9 + offset + i]; 3034 modes += add_hdmi_mode(connector, vic); 3035 } 3036 offset += 1 + vic_len; 3037 3038 if (multi_present == 1) 3039 multi_len = 2; 3040 else if (multi_present == 2) 3041 multi_len = 4; 3042 else 3043 multi_len = 0; 3044 3045 if (len < (8 + offset + hdmi_3d_len - 1)) 3046 goto out; 3047 3048 if (hdmi_3d_len < multi_len) 3049 goto out; 3050 3051 if (multi_present == 1 || multi_present == 2) { 3052 /* 3D_Structure_ALL */ 3053 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3054 3055 /* check if 3D_MASK is present */ 3056 if (multi_present == 2) 3057 mask = (db[10 + offset] << 8) | db[11 + offset]; 3058 else 3059 mask = 0xffff; 3060 3061 for (i = 0; i < 16; i++) { 3062 if (mask & (1 << i)) 3063 modes += add_3d_struct_modes(connector, 3064 structure_all, 3065 video_db, 3066 video_len, i); 3067 } 3068 } 3069 3070 offset += multi_len; 3071 3072 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3073 int vic_index; 3074 struct drm_display_mode *newmode = NULL; 3075 unsigned int newflag = 0; 3076 bool detail_present; 3077 3078 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3079 3080 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3081 break; 3082 3083 /* 2D_VIC_order_X */ 3084 vic_index = db[8 + offset + i] >> 4; 3085 3086 /* 3D_Structure_X */ 3087 switch (db[8 + offset + i] & 0x0f) { 3088 case 0: 3089 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3090 break; 3091 case 6: 3092 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3093 break; 3094 case 8: 3095 /* 3D_Detail_X */ 3096 if ((db[9 + offset + i] >> 4) == 1) 3097 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3098 break; 3099 } 3100 3101 if (newflag != 0) { 3102 newmode = drm_display_mode_from_vic_index(connector, 3103 video_db, 3104 video_len, 3105 vic_index); 3106 3107 if (newmode) { 3108 newmode->flags |= newflag; 3109 drm_mode_probed_add(connector, newmode); 3110 modes++; 3111 } 3112 } 3113 3114 if (detail_present) 3115 i++; 3116 } 3117 3118 out: 3119 return modes; 3120 } 3121 3122 static int 3123 cea_db_payload_len(const u8 *db) 3124 { 3125 return db[0] & 0x1f; 3126 } 3127 3128 static int 3129 cea_db_tag(const u8 *db) 3130 { 3131 return db[0] >> 5; 3132 } 3133 3134 static int 3135 cea_revision(const u8 *cea) 3136 { 3137 return cea[1]; 3138 } 3139 3140 static int 3141 cea_db_offsets(const u8 *cea, int *start, int *end) 3142 { 3143 /* Data block offset in CEA extension block */ 3144 *start = 4; 3145 *end = cea[2]; 3146 if (*end == 0) 3147 *end = 127; 3148 if (*end < 4 || *end > 127) 3149 return -ERANGE; 3150 return 0; 3151 } 3152 3153 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3154 { 3155 int hdmi_id; 3156 3157 if (cea_db_tag(db) != VENDOR_BLOCK) 3158 return false; 3159 3160 if (cea_db_payload_len(db) < 5) 3161 return false; 3162 3163 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3164 3165 return hdmi_id == HDMI_IEEE_OUI; 3166 } 3167 3168 #define for_each_cea_db(cea, i, start, end) \ 3169 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3170 3171 static int 3172 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3173 { 3174 const u8 *cea = drm_find_cea_extension(edid); 3175 const u8 *db, *hdmi = NULL, *video = NULL; 3176 u8 dbl, hdmi_len, video_len = 0; 3177 int modes = 0; 3178 3179 if (cea && cea_revision(cea) >= 3) { 3180 int i, start, end; 3181 3182 if (cea_db_offsets(cea, &start, &end)) 3183 return 0; 3184 3185 for_each_cea_db(cea, i, start, end) { 3186 db = &cea[i]; 3187 dbl = cea_db_payload_len(db); 3188 3189 if (cea_db_tag(db) == VIDEO_BLOCK) { 3190 video = db + 1; 3191 video_len = dbl; 3192 modes += do_cea_modes(connector, video, dbl); 3193 } 3194 else if (cea_db_is_hdmi_vsdb(db)) { 3195 hdmi = db; 3196 hdmi_len = dbl; 3197 } 3198 } 3199 } 3200 3201 /* 3202 * We parse the HDMI VSDB after having added the cea modes as we will 3203 * be patching their flags when the sink supports stereo 3D. 3204 */ 3205 if (hdmi) 3206 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3207 video_len); 3208 3209 return modes; 3210 } 3211 3212 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3213 { 3214 const struct drm_display_mode *cea_mode; 3215 int clock1, clock2, clock; 3216 u8 vic; 3217 const char *type; 3218 3219 /* 3220 * allow 5kHz clock difference either way to account for 3221 * the 10kHz clock resolution limit of detailed timings. 3222 */ 3223 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3224 if (drm_valid_cea_vic(vic)) { 3225 type = "CEA"; 3226 cea_mode = &edid_cea_modes[vic]; 3227 clock1 = cea_mode->clock; 3228 clock2 = cea_mode_alternate_clock(cea_mode); 3229 } else { 3230 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3231 if (drm_valid_hdmi_vic(vic)) { 3232 type = "HDMI"; 3233 cea_mode = &edid_4k_modes[vic]; 3234 clock1 = cea_mode->clock; 3235 clock2 = hdmi_mode_alternate_clock(cea_mode); 3236 } else { 3237 return; 3238 } 3239 } 3240 3241 /* pick whichever is closest */ 3242 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3243 clock = clock1; 3244 else 3245 clock = clock2; 3246 3247 if (mode->clock == clock) 3248 return; 3249 3250 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3251 type, vic, mode->clock, clock); 3252 mode->clock = clock; 3253 } 3254 3255 static void 3256 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3257 { 3258 u8 len = cea_db_payload_len(db); 3259 3260 if (len >= 6) { 3261 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3262 connector->dvi_dual = db[6] & 1; 3263 } 3264 if (len >= 7) 3265 connector->max_tmds_clock = db[7] * 5; 3266 if (len >= 8) { 3267 connector->latency_present[0] = db[8] >> 7; 3268 connector->latency_present[1] = (db[8] >> 6) & 1; 3269 } 3270 if (len >= 9) 3271 connector->video_latency[0] = db[9]; 3272 if (len >= 10) 3273 connector->audio_latency[0] = db[10]; 3274 if (len >= 11) 3275 connector->video_latency[1] = db[11]; 3276 if (len >= 12) 3277 connector->audio_latency[1] = db[12]; 3278 3279 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3280 "max TMDS clock %d, " 3281 "latency present %d %d, " 3282 "video latency %d %d, " 3283 "audio latency %d %d\n", 3284 connector->dvi_dual, 3285 connector->max_tmds_clock, 3286 (int) connector->latency_present[0], 3287 (int) connector->latency_present[1], 3288 connector->video_latency[0], 3289 connector->video_latency[1], 3290 connector->audio_latency[0], 3291 connector->audio_latency[1]); 3292 } 3293 3294 static void 3295 monitor_name(struct detailed_timing *t, void *data) 3296 { 3297 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3298 *(u8 **)data = t->data.other_data.data.str.str; 3299 } 3300 3301 static int get_monitor_name(struct edid *edid, char name[13]) 3302 { 3303 char *edid_name = NULL; 3304 int mnl; 3305 3306 if (!edid || !name) 3307 return 0; 3308 3309 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3310 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3311 if (edid_name[mnl] == 0x0a) 3312 break; 3313 3314 name[mnl] = edid_name[mnl]; 3315 } 3316 3317 return mnl; 3318 } 3319 3320 /** 3321 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3322 * @edid: monitor EDID information 3323 * @name: pointer to a character array to hold the name of the monitor 3324 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3325 * 3326 */ 3327 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3328 { 3329 int name_length; 3330 char buf[13]; 3331 3332 if (bufsize <= 0) 3333 return; 3334 3335 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3336 memcpy(name, buf, name_length); 3337 name[name_length] = '\0'; 3338 } 3339 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3340 3341 /** 3342 * drm_edid_to_eld - build ELD from EDID 3343 * @connector: connector corresponding to the HDMI/DP sink 3344 * @edid: EDID to parse 3345 * 3346 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3347 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3348 * fill in. 3349 */ 3350 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3351 { 3352 uint8_t *eld = connector->eld; 3353 u8 *cea; 3354 u8 *db; 3355 int total_sad_count = 0; 3356 int mnl; 3357 int dbl; 3358 3359 memset(eld, 0, sizeof(connector->eld)); 3360 3361 cea = drm_find_cea_extension(edid); 3362 if (!cea) { 3363 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3364 return; 3365 } 3366 3367 mnl = get_monitor_name(edid, eld + 20); 3368 3369 eld[4] = (cea[1] << 5) | mnl; 3370 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3371 3372 eld[0] = 2 << 3; /* ELD version: 2 */ 3373 3374 eld[16] = edid->mfg_id[0]; 3375 eld[17] = edid->mfg_id[1]; 3376 eld[18] = edid->prod_code[0]; 3377 eld[19] = edid->prod_code[1]; 3378 3379 if (cea_revision(cea) >= 3) { 3380 int i, start, end; 3381 3382 if (cea_db_offsets(cea, &start, &end)) { 3383 start = 0; 3384 end = 0; 3385 } 3386 3387 for_each_cea_db(cea, i, start, end) { 3388 db = &cea[i]; 3389 dbl = cea_db_payload_len(db); 3390 3391 switch (cea_db_tag(db)) { 3392 int sad_count; 3393 3394 case AUDIO_BLOCK: 3395 /* Audio Data Block, contains SADs */ 3396 sad_count = min(dbl / 3, 15 - total_sad_count); 3397 if (sad_count >= 1) 3398 memcpy(eld + 20 + mnl + total_sad_count * 3, 3399 &db[1], sad_count * 3); 3400 total_sad_count += sad_count; 3401 break; 3402 case SPEAKER_BLOCK: 3403 /* Speaker Allocation Data Block */ 3404 if (dbl >= 1) 3405 eld[7] = db[1]; 3406 break; 3407 case VENDOR_BLOCK: 3408 /* HDMI Vendor-Specific Data Block */ 3409 if (cea_db_is_hdmi_vsdb(db)) 3410 parse_hdmi_vsdb(connector, db); 3411 break; 3412 default: 3413 break; 3414 } 3415 } 3416 } 3417 eld[5] |= total_sad_count << 4; 3418 3419 eld[DRM_ELD_BASELINE_ELD_LEN] = 3420 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3421 3422 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3423 drm_eld_size(eld), total_sad_count); 3424 } 3425 EXPORT_SYMBOL(drm_edid_to_eld); 3426 3427 /** 3428 * drm_edid_to_sad - extracts SADs from EDID 3429 * @edid: EDID to parse 3430 * @sads: pointer that will be set to the extracted SADs 3431 * 3432 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3433 * 3434 * Note: The returned pointer needs to be freed using kfree(). 3435 * 3436 * Return: The number of found SADs or negative number on error. 3437 */ 3438 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3439 { 3440 int count = 0; 3441 int i, start, end, dbl; 3442 u8 *cea; 3443 3444 cea = drm_find_cea_extension(edid); 3445 if (!cea) { 3446 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3447 return -ENOENT; 3448 } 3449 3450 if (cea_revision(cea) < 3) { 3451 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3452 return -ENOTSUPP; 3453 } 3454 3455 if (cea_db_offsets(cea, &start, &end)) { 3456 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3457 return -EPROTO; 3458 } 3459 3460 for_each_cea_db(cea, i, start, end) { 3461 u8 *db = &cea[i]; 3462 3463 if (cea_db_tag(db) == AUDIO_BLOCK) { 3464 int j; 3465 dbl = cea_db_payload_len(db); 3466 3467 count = dbl / 3; /* SAD is 3B */ 3468 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3469 if (!*sads) 3470 return -ENOMEM; 3471 for (j = 0; j < count; j++) { 3472 u8 *sad = &db[1 + j * 3]; 3473 3474 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3475 (*sads)[j].channels = sad[0] & 0x7; 3476 (*sads)[j].freq = sad[1] & 0x7F; 3477 (*sads)[j].byte2 = sad[2]; 3478 } 3479 break; 3480 } 3481 } 3482 3483 return count; 3484 } 3485 EXPORT_SYMBOL(drm_edid_to_sad); 3486 3487 /** 3488 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3489 * @edid: EDID to parse 3490 * @sadb: pointer to the speaker block 3491 * 3492 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3493 * 3494 * Note: The returned pointer needs to be freed using kfree(). 3495 * 3496 * Return: The number of found Speaker Allocation Blocks or negative number on 3497 * error. 3498 */ 3499 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3500 { 3501 int count = 0; 3502 int i, start, end, dbl; 3503 const u8 *cea; 3504 3505 cea = drm_find_cea_extension(edid); 3506 if (!cea) { 3507 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3508 return -ENOENT; 3509 } 3510 3511 if (cea_revision(cea) < 3) { 3512 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3513 return -ENOTSUPP; 3514 } 3515 3516 if (cea_db_offsets(cea, &start, &end)) { 3517 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3518 return -EPROTO; 3519 } 3520 3521 for_each_cea_db(cea, i, start, end) { 3522 const u8 *db = &cea[i]; 3523 3524 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3525 dbl = cea_db_payload_len(db); 3526 3527 /* Speaker Allocation Data Block */ 3528 if (dbl == 3) { 3529 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3530 if (!*sadb) 3531 return -ENOMEM; 3532 count = dbl; 3533 break; 3534 } 3535 } 3536 } 3537 3538 return count; 3539 } 3540 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3541 3542 /** 3543 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3544 * @connector: connector associated with the HDMI/DP sink 3545 * @mode: the display mode 3546 * 3547 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3548 * the sink doesn't support audio or video. 3549 */ 3550 int drm_av_sync_delay(struct drm_connector *connector, 3551 const struct drm_display_mode *mode) 3552 { 3553 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3554 int a, v; 3555 3556 if (!connector->latency_present[0]) 3557 return 0; 3558 if (!connector->latency_present[1]) 3559 i = 0; 3560 3561 a = connector->audio_latency[i]; 3562 v = connector->video_latency[i]; 3563 3564 /* 3565 * HDMI/DP sink doesn't support audio or video? 3566 */ 3567 if (a == 255 || v == 255) 3568 return 0; 3569 3570 /* 3571 * Convert raw EDID values to millisecond. 3572 * Treat unknown latency as 0ms. 3573 */ 3574 if (a) 3575 a = min(2 * (a - 1), 500); 3576 if (v) 3577 v = min(2 * (v - 1), 500); 3578 3579 return max(v - a, 0); 3580 } 3581 EXPORT_SYMBOL(drm_av_sync_delay); 3582 3583 /** 3584 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3585 * @encoder: the encoder just changed display mode 3586 * 3587 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3588 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3589 * 3590 * Return: The connector associated with the first HDMI/DP sink that has ELD 3591 * attached to it. 3592 */ 3593 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3594 { 3595 struct drm_connector *connector; 3596 struct drm_device *dev = encoder->dev; 3597 3598 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3599 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3600 3601 drm_for_each_connector(connector, dev) 3602 if (connector->encoder == encoder && connector->eld[0]) 3603 return connector; 3604 3605 return NULL; 3606 } 3607 EXPORT_SYMBOL(drm_select_eld); 3608 3609 /** 3610 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3611 * @edid: monitor EDID information 3612 * 3613 * Parse the CEA extension according to CEA-861-B. 3614 * 3615 * Return: True if the monitor is HDMI, false if not or unknown. 3616 */ 3617 bool drm_detect_hdmi_monitor(struct edid *edid) 3618 { 3619 u8 *edid_ext; 3620 int i; 3621 int start_offset, end_offset; 3622 3623 edid_ext = drm_find_cea_extension(edid); 3624 if (!edid_ext) 3625 return false; 3626 3627 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3628 return false; 3629 3630 /* 3631 * Because HDMI identifier is in Vendor Specific Block, 3632 * search it from all data blocks of CEA extension. 3633 */ 3634 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3635 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3636 return true; 3637 } 3638 3639 return false; 3640 } 3641 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3642 3643 /** 3644 * drm_detect_monitor_audio - check monitor audio capability 3645 * @edid: EDID block to scan 3646 * 3647 * Monitor should have CEA extension block. 3648 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3649 * audio' only. If there is any audio extension block and supported 3650 * audio format, assume at least 'basic audio' support, even if 'basic 3651 * audio' is not defined in EDID. 3652 * 3653 * Return: True if the monitor supports audio, false otherwise. 3654 */ 3655 bool drm_detect_monitor_audio(struct edid *edid) 3656 { 3657 u8 *edid_ext; 3658 int i, j; 3659 bool has_audio = false; 3660 int start_offset, end_offset; 3661 3662 edid_ext = drm_find_cea_extension(edid); 3663 if (!edid_ext) 3664 goto end; 3665 3666 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3667 3668 if (has_audio) { 3669 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3670 goto end; 3671 } 3672 3673 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3674 goto end; 3675 3676 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3677 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3678 has_audio = true; 3679 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3680 DRM_DEBUG_KMS("CEA audio format %d\n", 3681 (edid_ext[i + j] >> 3) & 0xf); 3682 goto end; 3683 } 3684 } 3685 end: 3686 return has_audio; 3687 } 3688 EXPORT_SYMBOL(drm_detect_monitor_audio); 3689 3690 /** 3691 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3692 * @edid: EDID block to scan 3693 * 3694 * Check whether the monitor reports the RGB quantization range selection 3695 * as supported. The AVI infoframe can then be used to inform the monitor 3696 * which quantization range (full or limited) is used. 3697 * 3698 * Return: True if the RGB quantization range is selectable, false otherwise. 3699 */ 3700 bool drm_rgb_quant_range_selectable(struct edid *edid) 3701 { 3702 u8 *edid_ext; 3703 int i, start, end; 3704 3705 edid_ext = drm_find_cea_extension(edid); 3706 if (!edid_ext) 3707 return false; 3708 3709 if (cea_db_offsets(edid_ext, &start, &end)) 3710 return false; 3711 3712 for_each_cea_db(edid_ext, i, start, end) { 3713 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3714 cea_db_payload_len(&edid_ext[i]) == 2) { 3715 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3716 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3717 } 3718 } 3719 3720 return false; 3721 } 3722 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3723 3724 /** 3725 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3726 * hdmi deep color modes and update drm_display_info if so. 3727 * @edid: monitor EDID information 3728 * @info: Updated with maximum supported deep color bpc and color format 3729 * if deep color supported. 3730 * @connector: DRM connector, used only for debug output 3731 * 3732 * Parse the CEA extension according to CEA-861-B. 3733 * Return true if HDMI deep color supported, false if not or unknown. 3734 */ 3735 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3736 struct drm_display_info *info, 3737 struct drm_connector *connector) 3738 { 3739 u8 *edid_ext, *hdmi; 3740 int i; 3741 int start_offset, end_offset; 3742 unsigned int dc_bpc = 0; 3743 3744 edid_ext = drm_find_cea_extension(edid); 3745 if (!edid_ext) 3746 return false; 3747 3748 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3749 return false; 3750 3751 /* 3752 * Because HDMI identifier is in Vendor Specific Block, 3753 * search it from all data blocks of CEA extension. 3754 */ 3755 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3756 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3757 /* HDMI supports at least 8 bpc */ 3758 info->bpc = 8; 3759 3760 hdmi = &edid_ext[i]; 3761 if (cea_db_payload_len(hdmi) < 6) 3762 return false; 3763 3764 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3765 dc_bpc = 10; 3766 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3767 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3768 connector->name); 3769 } 3770 3771 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3772 dc_bpc = 12; 3773 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3774 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3775 connector->name); 3776 } 3777 3778 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3779 dc_bpc = 16; 3780 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3781 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3782 connector->name); 3783 } 3784 3785 if (dc_bpc > 0) { 3786 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3787 connector->name, dc_bpc); 3788 info->bpc = dc_bpc; 3789 3790 /* 3791 * Deep color support mandates RGB444 support for all video 3792 * modes and forbids YCRCB422 support for all video modes per 3793 * HDMI 1.3 spec. 3794 */ 3795 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3796 3797 /* YCRCB444 is optional according to spec. */ 3798 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3799 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3800 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3801 connector->name); 3802 } 3803 3804 /* 3805 * Spec says that if any deep color mode is supported at all, 3806 * then deep color 36 bit must be supported. 3807 */ 3808 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3809 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3810 connector->name); 3811 } 3812 3813 return true; 3814 } 3815 else { 3816 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3817 connector->name); 3818 } 3819 } 3820 } 3821 3822 return false; 3823 } 3824 3825 /** 3826 * drm_add_display_info - pull display info out if present 3827 * @edid: EDID data 3828 * @info: display info (attached to connector) 3829 * @connector: connector whose edid is used to build display info 3830 * 3831 * Grab any available display info and stuff it into the drm_display_info 3832 * structure that's part of the connector. Useful for tracking bpp and 3833 * color spaces. 3834 */ 3835 static void drm_add_display_info(struct edid *edid, 3836 struct drm_display_info *info, 3837 struct drm_connector *connector) 3838 { 3839 u8 *edid_ext; 3840 3841 info->width_mm = edid->width_cm * 10; 3842 info->height_mm = edid->height_cm * 10; 3843 3844 /* driver figures it out in this case */ 3845 info->bpc = 0; 3846 info->color_formats = 0; 3847 3848 if (edid->revision < 3) 3849 return; 3850 3851 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3852 return; 3853 3854 /* Get data from CEA blocks if present */ 3855 edid_ext = drm_find_cea_extension(edid); 3856 if (edid_ext) { 3857 info->cea_rev = edid_ext[1]; 3858 3859 /* The existence of a CEA block should imply RGB support */ 3860 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3861 if (edid_ext[3] & EDID_CEA_YCRCB444) 3862 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3863 if (edid_ext[3] & EDID_CEA_YCRCB422) 3864 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3865 } 3866 3867 /* HDMI deep color modes supported? Assign to info, if so */ 3868 drm_assign_hdmi_deep_color_info(edid, info, connector); 3869 3870 /* 3871 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3872 * 3873 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3874 * tells us to assume 8 bpc color depth if the EDID doesn't have 3875 * extensions which tell otherwise. 3876 */ 3877 if ((info->bpc == 0) && (edid->revision < 4) && 3878 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3879 info->bpc = 8; 3880 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 3881 connector->name, info->bpc); 3882 } 3883 3884 /* Only defined for 1.4 with digital displays */ 3885 if (edid->revision < 4) 3886 return; 3887 3888 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3889 case DRM_EDID_DIGITAL_DEPTH_6: 3890 info->bpc = 6; 3891 break; 3892 case DRM_EDID_DIGITAL_DEPTH_8: 3893 info->bpc = 8; 3894 break; 3895 case DRM_EDID_DIGITAL_DEPTH_10: 3896 info->bpc = 10; 3897 break; 3898 case DRM_EDID_DIGITAL_DEPTH_12: 3899 info->bpc = 12; 3900 break; 3901 case DRM_EDID_DIGITAL_DEPTH_14: 3902 info->bpc = 14; 3903 break; 3904 case DRM_EDID_DIGITAL_DEPTH_16: 3905 info->bpc = 16; 3906 break; 3907 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3908 default: 3909 info->bpc = 0; 3910 break; 3911 } 3912 3913 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3914 connector->name, info->bpc); 3915 3916 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3917 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3918 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3919 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3920 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3921 } 3922 3923 static int validate_displayid(u8 *displayid, int length, int idx) 3924 { 3925 int i; 3926 u8 csum = 0; 3927 struct displayid_hdr *base; 3928 3929 base = (struct displayid_hdr *)&displayid[idx]; 3930 3931 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 3932 base->rev, base->bytes, base->prod_id, base->ext_count); 3933 3934 if (base->bytes + 5 > length - idx) 3935 return -EINVAL; 3936 for (i = idx; i <= base->bytes + 5; i++) { 3937 csum += displayid[i]; 3938 } 3939 if (csum) { 3940 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 3941 return -EINVAL; 3942 } 3943 return 0; 3944 } 3945 3946 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 3947 struct displayid_detailed_timings_1 *timings) 3948 { 3949 struct drm_display_mode *mode; 3950 unsigned pixel_clock = (timings->pixel_clock[0] | 3951 (timings->pixel_clock[1] << 8) | 3952 (timings->pixel_clock[2] << 16)); 3953 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 3954 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 3955 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 3956 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 3957 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 3958 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 3959 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 3960 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 3961 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 3962 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 3963 mode = drm_mode_create(dev); 3964 if (!mode) 3965 return NULL; 3966 3967 mode->clock = pixel_clock * 10; 3968 mode->hdisplay = hactive; 3969 mode->hsync_start = mode->hdisplay + hsync; 3970 mode->hsync_end = mode->hsync_start + hsync_width; 3971 mode->htotal = mode->hdisplay + hblank; 3972 3973 mode->vdisplay = vactive; 3974 mode->vsync_start = mode->vdisplay + vsync; 3975 mode->vsync_end = mode->vsync_start + vsync_width; 3976 mode->vtotal = mode->vdisplay + vblank; 3977 3978 mode->flags = 0; 3979 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3980 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3981 mode->type = DRM_MODE_TYPE_DRIVER; 3982 3983 if (timings->flags & 0x80) 3984 mode->type |= DRM_MODE_TYPE_PREFERRED; 3985 mode->vrefresh = drm_mode_vrefresh(mode); 3986 drm_mode_set_name(mode); 3987 3988 return mode; 3989 } 3990 3991 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 3992 struct displayid_block *block) 3993 { 3994 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 3995 int i; 3996 int num_timings; 3997 struct drm_display_mode *newmode; 3998 int num_modes = 0; 3999 /* blocks must be multiple of 20 bytes length */ 4000 if (block->num_bytes % 20) 4001 return 0; 4002 4003 num_timings = block->num_bytes / 20; 4004 for (i = 0; i < num_timings; i++) { 4005 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4006 4007 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4008 if (!newmode) 4009 continue; 4010 4011 drm_mode_probed_add(connector, newmode); 4012 num_modes++; 4013 } 4014 return num_modes; 4015 } 4016 4017 static int add_displayid_detailed_modes(struct drm_connector *connector, 4018 struct edid *edid) 4019 { 4020 u8 *displayid; 4021 int ret; 4022 int idx = 1; 4023 int length = EDID_LENGTH; 4024 struct displayid_block *block; 4025 int num_modes = 0; 4026 4027 displayid = drm_find_displayid_extension(edid); 4028 if (!displayid) 4029 return 0; 4030 4031 ret = validate_displayid(displayid, length, idx); 4032 if (ret) 4033 return 0; 4034 4035 idx += sizeof(struct displayid_hdr); 4036 while (block = (struct displayid_block *)&displayid[idx], 4037 idx + sizeof(struct displayid_block) <= length && 4038 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4039 block->num_bytes > 0) { 4040 idx += block->num_bytes + sizeof(struct displayid_block); 4041 switch (block->tag) { 4042 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4043 num_modes += add_displayid_detailed_1_modes(connector, block); 4044 break; 4045 } 4046 } 4047 return num_modes; 4048 } 4049 4050 /** 4051 * drm_add_edid_modes - add modes from EDID data, if available 4052 * @connector: connector we're probing 4053 * @edid: EDID data 4054 * 4055 * Add the specified modes to the connector's mode list. 4056 * 4057 * Return: The number of modes added or 0 if we couldn't find any. 4058 */ 4059 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4060 { 4061 int num_modes = 0; 4062 u32 quirks; 4063 4064 if (edid == NULL) { 4065 return 0; 4066 } 4067 if (!drm_edid_is_valid(edid)) { 4068 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4069 connector->name); 4070 return 0; 4071 } 4072 4073 quirks = edid_get_quirks(edid); 4074 4075 /* 4076 * EDID spec says modes should be preferred in this order: 4077 * - preferred detailed mode 4078 * - other detailed modes from base block 4079 * - detailed modes from extension blocks 4080 * - CVT 3-byte code modes 4081 * - standard timing codes 4082 * - established timing codes 4083 * - modes inferred from GTF or CVT range information 4084 * 4085 * We get this pretty much right. 4086 * 4087 * XXX order for additional mode types in extension blocks? 4088 */ 4089 num_modes += add_detailed_modes(connector, edid, quirks); 4090 num_modes += add_cvt_modes(connector, edid); 4091 num_modes += add_standard_modes(connector, edid); 4092 num_modes += add_established_modes(connector, edid); 4093 num_modes += add_cea_modes(connector, edid); 4094 num_modes += add_alternate_cea_modes(connector, edid); 4095 num_modes += add_displayid_detailed_modes(connector, edid); 4096 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4097 num_modes += add_inferred_modes(connector, edid); 4098 4099 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4100 edid_fixup_preferred(connector, quirks); 4101 4102 drm_add_display_info(edid, &connector->display_info, connector); 4103 4104 if (quirks & EDID_QUIRK_FORCE_6BPC) 4105 connector->display_info.bpc = 6; 4106 4107 if (quirks & EDID_QUIRK_FORCE_8BPC) 4108 connector->display_info.bpc = 8; 4109 4110 if (quirks & EDID_QUIRK_FORCE_12BPC) 4111 connector->display_info.bpc = 12; 4112 4113 return num_modes; 4114 } 4115 EXPORT_SYMBOL(drm_add_edid_modes); 4116 4117 /** 4118 * drm_add_modes_noedid - add modes for the connectors without EDID 4119 * @connector: connector we're probing 4120 * @hdisplay: the horizontal display limit 4121 * @vdisplay: the vertical display limit 4122 * 4123 * Add the specified modes to the connector's mode list. Only when the 4124 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4125 * 4126 * Return: The number of modes added or 0 if we couldn't find any. 4127 */ 4128 int drm_add_modes_noedid(struct drm_connector *connector, 4129 int hdisplay, int vdisplay) 4130 { 4131 int i, count, num_modes = 0; 4132 struct drm_display_mode *mode; 4133 struct drm_device *dev = connector->dev; 4134 4135 count = ARRAY_SIZE(drm_dmt_modes); 4136 if (hdisplay < 0) 4137 hdisplay = 0; 4138 if (vdisplay < 0) 4139 vdisplay = 0; 4140 4141 for (i = 0; i < count; i++) { 4142 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4143 if (hdisplay && vdisplay) { 4144 /* 4145 * Only when two are valid, they will be used to check 4146 * whether the mode should be added to the mode list of 4147 * the connector. 4148 */ 4149 if (ptr->hdisplay > hdisplay || 4150 ptr->vdisplay > vdisplay) 4151 continue; 4152 } 4153 if (drm_mode_vrefresh(ptr) > 61) 4154 continue; 4155 mode = drm_mode_duplicate(dev, ptr); 4156 if (mode) { 4157 drm_mode_probed_add(connector, mode); 4158 num_modes++; 4159 } 4160 } 4161 return num_modes; 4162 } 4163 EXPORT_SYMBOL(drm_add_modes_noedid); 4164 4165 /** 4166 * drm_set_preferred_mode - Sets the preferred mode of a connector 4167 * @connector: connector whose mode list should be processed 4168 * @hpref: horizontal resolution of preferred mode 4169 * @vpref: vertical resolution of preferred mode 4170 * 4171 * Marks a mode as preferred if it matches the resolution specified by @hpref 4172 * and @vpref. 4173 */ 4174 void drm_set_preferred_mode(struct drm_connector *connector, 4175 int hpref, int vpref) 4176 { 4177 struct drm_display_mode *mode; 4178 4179 list_for_each_entry(mode, &connector->probed_modes, head) { 4180 if (mode->hdisplay == hpref && 4181 mode->vdisplay == vpref) 4182 mode->type |= DRM_MODE_TYPE_PREFERRED; 4183 } 4184 } 4185 EXPORT_SYMBOL(drm_set_preferred_mode); 4186 4187 /** 4188 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4189 * data from a DRM display mode 4190 * @frame: HDMI AVI infoframe 4191 * @mode: DRM display mode 4192 * 4193 * Return: 0 on success or a negative error code on failure. 4194 */ 4195 int 4196 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4197 const struct drm_display_mode *mode) 4198 { 4199 int err; 4200 4201 if (!frame || !mode) 4202 return -EINVAL; 4203 4204 err = hdmi_avi_infoframe_init(frame); 4205 if (err < 0) 4206 return err; 4207 4208 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4209 frame->pixel_repeat = 1; 4210 4211 frame->video_code = drm_match_cea_mode(mode); 4212 4213 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4214 4215 /* 4216 * Populate picture aspect ratio from either 4217 * user input (if specified) or from the CEA mode list. 4218 */ 4219 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4220 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4221 frame->picture_aspect = mode->picture_aspect_ratio; 4222 else if (frame->video_code > 0) 4223 frame->picture_aspect = drm_get_cea_aspect_ratio( 4224 frame->video_code); 4225 4226 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4227 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4228 4229 return 0; 4230 } 4231 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4232 4233 static enum hdmi_3d_structure 4234 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4235 { 4236 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4237 4238 switch (layout) { 4239 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4240 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4241 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4242 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4243 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4244 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4245 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4246 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4247 case DRM_MODE_FLAG_3D_L_DEPTH: 4248 return HDMI_3D_STRUCTURE_L_DEPTH; 4249 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4250 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4251 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4252 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4253 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4254 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4255 default: 4256 return HDMI_3D_STRUCTURE_INVALID; 4257 } 4258 } 4259 4260 /** 4261 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4262 * data from a DRM display mode 4263 * @frame: HDMI vendor infoframe 4264 * @mode: DRM display mode 4265 * 4266 * Note that there's is a need to send HDMI vendor infoframes only when using a 4267 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4268 * function will return -EINVAL, error that can be safely ignored. 4269 * 4270 * Return: 0 on success or a negative error code on failure. 4271 */ 4272 int 4273 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4274 const struct drm_display_mode *mode) 4275 { 4276 int err; 4277 u32 s3d_flags; 4278 u8 vic; 4279 4280 if (!frame || !mode) 4281 return -EINVAL; 4282 4283 vic = drm_match_hdmi_mode(mode); 4284 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4285 4286 if (!vic && !s3d_flags) 4287 return -EINVAL; 4288 4289 if (vic && s3d_flags) 4290 return -EINVAL; 4291 4292 err = hdmi_vendor_infoframe_init(frame); 4293 if (err < 0) 4294 return err; 4295 4296 if (vic) 4297 frame->vic = vic; 4298 else 4299 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4300 4301 return 0; 4302 } 4303 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4304 4305 static int drm_parse_tiled_block(struct drm_connector *connector, 4306 struct displayid_block *block) 4307 { 4308 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4309 u16 w, h; 4310 u8 tile_v_loc, tile_h_loc; 4311 u8 num_v_tile, num_h_tile; 4312 struct drm_tile_group *tg; 4313 4314 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4315 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4316 4317 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4318 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4319 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4320 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4321 4322 connector->has_tile = true; 4323 if (tile->tile_cap & 0x80) 4324 connector->tile_is_single_monitor = true; 4325 4326 connector->num_h_tile = num_h_tile + 1; 4327 connector->num_v_tile = num_v_tile + 1; 4328 connector->tile_h_loc = tile_h_loc; 4329 connector->tile_v_loc = tile_v_loc; 4330 connector->tile_h_size = w + 1; 4331 connector->tile_v_size = h + 1; 4332 4333 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4334 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4335 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4336 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4337 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4338 4339 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4340 if (!tg) { 4341 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4342 } 4343 if (!tg) 4344 return -ENOMEM; 4345 4346 if (connector->tile_group != tg) { 4347 /* if we haven't got a pointer, 4348 take the reference, drop ref to old tile group */ 4349 if (connector->tile_group) { 4350 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4351 } 4352 connector->tile_group = tg; 4353 } else 4354 /* if same tile group, then release the ref we just took. */ 4355 drm_mode_put_tile_group(connector->dev, tg); 4356 return 0; 4357 } 4358 4359 static int drm_parse_display_id(struct drm_connector *connector, 4360 u8 *displayid, int length, 4361 bool is_edid_extension) 4362 { 4363 /* if this is an EDID extension the first byte will be 0x70 */ 4364 int idx = 0; 4365 struct displayid_block *block; 4366 int ret; 4367 4368 if (is_edid_extension) 4369 idx = 1; 4370 4371 ret = validate_displayid(displayid, length, idx); 4372 if (ret) 4373 return ret; 4374 4375 idx += sizeof(struct displayid_hdr); 4376 while (block = (struct displayid_block *)&displayid[idx], 4377 idx + sizeof(struct displayid_block) <= length && 4378 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4379 block->num_bytes > 0) { 4380 idx += block->num_bytes + sizeof(struct displayid_block); 4381 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4382 block->tag, block->rev, block->num_bytes); 4383 4384 switch (block->tag) { 4385 case DATA_BLOCK_TILED_DISPLAY: 4386 ret = drm_parse_tiled_block(connector, block); 4387 if (ret) 4388 return ret; 4389 break; 4390 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4391 /* handled in mode gathering code. */ 4392 break; 4393 default: 4394 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 4395 break; 4396 } 4397 } 4398 return 0; 4399 } 4400 4401 static void drm_get_displayid(struct drm_connector *connector, 4402 struct edid *edid) 4403 { 4404 void *displayid = NULL; 4405 int ret; 4406 connector->has_tile = false; 4407 displayid = drm_find_displayid_extension(edid); 4408 if (!displayid) { 4409 /* drop reference to any tile group we had */ 4410 goto out_drop_ref; 4411 } 4412 4413 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4414 if (ret < 0) 4415 goto out_drop_ref; 4416 if (!connector->has_tile) 4417 goto out_drop_ref; 4418 return; 4419 out_drop_ref: 4420 if (connector->tile_group) { 4421 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4422 connector->tile_group = NULL; 4423 } 4424 return; 4425 } 4426