1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static int validate_displayid(u8 *displayid, int length, int idx); 1588 1589 static int drm_edid_block_checksum(const u8 *raw_edid) 1590 { 1591 int i; 1592 u8 csum = 0, crc = 0; 1593 1594 for (i = 0; i < EDID_LENGTH - 1; i++) 1595 csum += raw_edid[i]; 1596 1597 crc = 0x100 - csum; 1598 1599 return crc; 1600 } 1601 1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1603 { 1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1605 return true; 1606 else 1607 return false; 1608 } 1609 1610 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1611 { 1612 if (memchr_inv(in_edid, 0, length)) 1613 return false; 1614 1615 return true; 1616 } 1617 1618 /** 1619 * drm_edid_are_equal - compare two edid blobs. 1620 * @edid1: pointer to first blob 1621 * @edid2: pointer to second blob 1622 * This helper can be used during probing to determine if 1623 * edid had changed. 1624 */ 1625 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1626 { 1627 int edid1_len, edid2_len; 1628 bool edid1_present = edid1 != NULL; 1629 bool edid2_present = edid2 != NULL; 1630 1631 if (edid1_present != edid2_present) 1632 return false; 1633 1634 if (edid1) { 1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions); 1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions); 1637 1638 if (edid1_len != edid2_len) 1639 return false; 1640 1641 if (memcmp(edid1, edid2, edid1_len)) 1642 return false; 1643 } 1644 1645 return true; 1646 } 1647 EXPORT_SYMBOL(drm_edid_are_equal); 1648 1649 /** 1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1651 * @raw_edid: pointer to raw EDID block 1652 * @block: type of block to validate (0 for base, extension otherwise) 1653 * @print_bad_edid: if true, dump bad EDID blocks to the console 1654 * @edid_corrupt: if true, the header or checksum is invalid 1655 * 1656 * Validate a base or extension EDID block and optionally dump bad blocks to 1657 * the console. 1658 * 1659 * Return: True if the block is valid, false otherwise. 1660 */ 1661 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1662 bool *edid_corrupt) 1663 { 1664 u8 csum; 1665 struct edid *edid = (struct edid *)raw_edid; 1666 1667 if (WARN_ON(!raw_edid)) 1668 return false; 1669 1670 if (edid_fixup > 8 || edid_fixup < 0) 1671 edid_fixup = 6; 1672 1673 if (block == 0) { 1674 int score = drm_edid_header_is_valid(raw_edid); 1675 1676 if (score == 8) { 1677 if (edid_corrupt) 1678 *edid_corrupt = false; 1679 } else if (score >= edid_fixup) { 1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1681 * The corrupt flag needs to be set here otherwise, the 1682 * fix-up code here will correct the problem, the 1683 * checksum is correct and the test fails 1684 */ 1685 if (edid_corrupt) 1686 *edid_corrupt = true; 1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1688 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1689 } else { 1690 if (edid_corrupt) 1691 *edid_corrupt = true; 1692 goto bad; 1693 } 1694 } 1695 1696 csum = drm_edid_block_checksum(raw_edid); 1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1698 if (edid_corrupt) 1699 *edid_corrupt = true; 1700 1701 /* allow CEA to slide through, switches mangle this */ 1702 if (raw_edid[0] == CEA_EXT) { 1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1705 } else { 1706 if (print_bad_edid) 1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1708 1709 goto bad; 1710 } 1711 } 1712 1713 /* per-block-type checks */ 1714 switch (raw_edid[0]) { 1715 case 0: /* base */ 1716 if (edid->version != 1) { 1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1718 goto bad; 1719 } 1720 1721 if (edid->revision > 4) 1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1723 break; 1724 1725 default: 1726 break; 1727 } 1728 1729 return true; 1730 1731 bad: 1732 if (print_bad_edid) { 1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1734 pr_notice("EDID block is all zeroes\n"); 1735 } else { 1736 pr_notice("Raw EDID:\n"); 1737 print_hex_dump(KERN_NOTICE, 1738 " \t", DUMP_PREFIX_NONE, 16, 1, 1739 raw_edid, EDID_LENGTH, false); 1740 } 1741 } 1742 return false; 1743 } 1744 EXPORT_SYMBOL(drm_edid_block_valid); 1745 1746 /** 1747 * drm_edid_is_valid - sanity check EDID data 1748 * @edid: EDID data 1749 * 1750 * Sanity-check an entire EDID record (including extensions) 1751 * 1752 * Return: True if the EDID data is valid, false otherwise. 1753 */ 1754 bool drm_edid_is_valid(struct edid *edid) 1755 { 1756 int i; 1757 u8 *raw = (u8 *)edid; 1758 1759 if (!edid) 1760 return false; 1761 1762 for (i = 0; i <= edid->extensions; i++) 1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1764 return false; 1765 1766 return true; 1767 } 1768 EXPORT_SYMBOL(drm_edid_is_valid); 1769 1770 #define DDC_SEGMENT_ADDR 0x30 1771 /** 1772 * drm_do_probe_ddc_edid() - get EDID information via I2C 1773 * @data: I2C device adapter 1774 * @buf: EDID data buffer to be filled 1775 * @block: 128 byte EDID block to start fetching from 1776 * @len: EDID data buffer length to fetch 1777 * 1778 * Try to fetch EDID information by calling I2C driver functions. 1779 * 1780 * Return: 0 on success or -1 on failure. 1781 */ 1782 static int 1783 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1784 { 1785 struct i2c_adapter *adapter = data; 1786 unsigned char start = block * EDID_LENGTH; 1787 unsigned char segment = block >> 1; 1788 unsigned char xfers = segment ? 3 : 2; 1789 int ret, retries = 5; 1790 1791 /* 1792 * The core I2C driver will automatically retry the transfer if the 1793 * adapter reports EAGAIN. However, we find that bit-banging transfers 1794 * are susceptible to errors under a heavily loaded machine and 1795 * generate spurious NAKs and timeouts. Retrying the transfer 1796 * of the individual block a few times seems to overcome this. 1797 */ 1798 do { 1799 struct i2c_msg msgs[] = { 1800 { 1801 .addr = DDC_SEGMENT_ADDR, 1802 .flags = 0, 1803 .len = 1, 1804 .buf = &segment, 1805 }, { 1806 .addr = DDC_ADDR, 1807 .flags = 0, 1808 .len = 1, 1809 .buf = &start, 1810 }, { 1811 .addr = DDC_ADDR, 1812 .flags = I2C_M_RD, 1813 .len = len, 1814 .buf = buf, 1815 } 1816 }; 1817 1818 /* 1819 * Avoid sending the segment addr to not upset non-compliant 1820 * DDC monitors. 1821 */ 1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1823 1824 if (ret == -ENXIO) { 1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1826 adapter->name); 1827 break; 1828 } 1829 } while (ret != xfers && --retries); 1830 1831 return ret == xfers ? 0 : -1; 1832 } 1833 1834 static void connector_bad_edid(struct drm_connector *connector, 1835 u8 *edid, int num_blocks) 1836 { 1837 int i; 1838 u8 num_of_ext = edid[0x7e]; 1839 1840 /* Calculate real checksum for the last edid extension block data */ 1841 connector->real_edid_checksum = 1842 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1843 1844 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1845 return; 1846 1847 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 1848 for (i = 0; i < num_blocks; i++) { 1849 u8 *block = edid + i * EDID_LENGTH; 1850 char prefix[20]; 1851 1852 if (drm_edid_is_zero(block, EDID_LENGTH)) 1853 sprintf(prefix, "\t[%02x] ZERO ", i); 1854 else if (!drm_edid_block_valid(block, i, false, NULL)) 1855 sprintf(prefix, "\t[%02x] BAD ", i); 1856 else 1857 sprintf(prefix, "\t[%02x] GOOD ", i); 1858 1859 print_hex_dump(KERN_DEBUG, 1860 prefix, DUMP_PREFIX_NONE, 16, 1, 1861 block, EDID_LENGTH, false); 1862 } 1863 } 1864 1865 /* Get override or firmware EDID */ 1866 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1867 { 1868 struct edid *override = NULL; 1869 1870 if (connector->override_edid) 1871 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1872 1873 if (!override) 1874 override = drm_load_edid_firmware(connector); 1875 1876 return IS_ERR(override) ? NULL : override; 1877 } 1878 1879 /** 1880 * drm_add_override_edid_modes - add modes from override/firmware EDID 1881 * @connector: connector we're probing 1882 * 1883 * Add modes from the override/firmware EDID, if available. Only to be used from 1884 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1885 * failed during drm_get_edid() and caused the override/firmware EDID to be 1886 * skipped. 1887 * 1888 * Return: The number of modes added or 0 if we couldn't find any. 1889 */ 1890 int drm_add_override_edid_modes(struct drm_connector *connector) 1891 { 1892 struct edid *override; 1893 int num_modes = 0; 1894 1895 override = drm_get_override_edid(connector); 1896 if (override) { 1897 drm_connector_update_edid_property(connector, override); 1898 num_modes = drm_add_edid_modes(connector, override); 1899 kfree(override); 1900 1901 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1902 connector->base.id, connector->name, num_modes); 1903 } 1904 1905 return num_modes; 1906 } 1907 EXPORT_SYMBOL(drm_add_override_edid_modes); 1908 1909 /** 1910 * drm_do_get_edid - get EDID data using a custom EDID block read function 1911 * @connector: connector we're probing 1912 * @get_edid_block: EDID block read function 1913 * @data: private data passed to the block read function 1914 * 1915 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1916 * exposes a different interface to read EDID blocks this function can be used 1917 * to get EDID data using a custom block read function. 1918 * 1919 * As in the general case the DDC bus is accessible by the kernel at the I2C 1920 * level, drivers must make all reasonable efforts to expose it as an I2C 1921 * adapter and use drm_get_edid() instead of abusing this function. 1922 * 1923 * The EDID may be overridden using debugfs override_edid or firmare EDID 1924 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1925 * order. Having either of them bypasses actual EDID reads. 1926 * 1927 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1928 */ 1929 struct edid *drm_do_get_edid(struct drm_connector *connector, 1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1931 size_t len), 1932 void *data) 1933 { 1934 int i, j = 0, valid_extensions = 0; 1935 u8 *edid, *new; 1936 struct edid *override; 1937 1938 override = drm_get_override_edid(connector); 1939 if (override) 1940 return override; 1941 1942 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1943 return NULL; 1944 1945 /* base block fetch */ 1946 for (i = 0; i < 4; i++) { 1947 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1948 goto out; 1949 if (drm_edid_block_valid(edid, 0, false, 1950 &connector->edid_corrupt)) 1951 break; 1952 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1953 connector->null_edid_counter++; 1954 goto carp; 1955 } 1956 } 1957 if (i == 4) 1958 goto carp; 1959 1960 /* if there's no extensions, we're done */ 1961 valid_extensions = edid[0x7e]; 1962 if (valid_extensions == 0) 1963 return (struct edid *)edid; 1964 1965 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1966 if (!new) 1967 goto out; 1968 edid = new; 1969 1970 for (j = 1; j <= edid[0x7e]; j++) { 1971 u8 *block = edid + j * EDID_LENGTH; 1972 1973 for (i = 0; i < 4; i++) { 1974 if (get_edid_block(data, block, j, EDID_LENGTH)) 1975 goto out; 1976 if (drm_edid_block_valid(block, j, false, NULL)) 1977 break; 1978 } 1979 1980 if (i == 4) 1981 valid_extensions--; 1982 } 1983 1984 if (valid_extensions != edid[0x7e]) { 1985 u8 *base; 1986 1987 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1988 1989 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1990 edid[0x7e] = valid_extensions; 1991 1992 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1993 GFP_KERNEL); 1994 if (!new) 1995 goto out; 1996 1997 base = new; 1998 for (i = 0; i <= edid[0x7e]; i++) { 1999 u8 *block = edid + i * EDID_LENGTH; 2000 2001 if (!drm_edid_block_valid(block, i, false, NULL)) 2002 continue; 2003 2004 memcpy(base, block, EDID_LENGTH); 2005 base += EDID_LENGTH; 2006 } 2007 2008 kfree(edid); 2009 edid = new; 2010 } 2011 2012 return (struct edid *)edid; 2013 2014 carp: 2015 connector_bad_edid(connector, edid, 1); 2016 out: 2017 kfree(edid); 2018 return NULL; 2019 } 2020 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2021 2022 /** 2023 * drm_probe_ddc() - probe DDC presence 2024 * @adapter: I2C adapter to probe 2025 * 2026 * Return: True on success, false on failure. 2027 */ 2028 bool 2029 drm_probe_ddc(struct i2c_adapter *adapter) 2030 { 2031 unsigned char out; 2032 2033 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2034 } 2035 EXPORT_SYMBOL(drm_probe_ddc); 2036 2037 /** 2038 * drm_get_edid - get EDID data, if available 2039 * @connector: connector we're probing 2040 * @adapter: I2C adapter to use for DDC 2041 * 2042 * Poke the given I2C channel to grab EDID data if possible. If found, 2043 * attach it to the connector. 2044 * 2045 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2046 */ 2047 struct edid *drm_get_edid(struct drm_connector *connector, 2048 struct i2c_adapter *adapter) 2049 { 2050 struct edid *edid; 2051 2052 if (connector->force == DRM_FORCE_OFF) 2053 return NULL; 2054 2055 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2056 return NULL; 2057 2058 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2059 drm_connector_update_edid_property(connector, edid); 2060 return edid; 2061 } 2062 EXPORT_SYMBOL(drm_get_edid); 2063 2064 /** 2065 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2066 * @connector: connector we're probing 2067 * @adapter: I2C adapter to use for DDC 2068 * 2069 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2070 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2071 * switch DDC to the GPU which is retrieving EDID. 2072 * 2073 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2074 */ 2075 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2076 struct i2c_adapter *adapter) 2077 { 2078 struct pci_dev *pdev = connector->dev->pdev; 2079 struct edid *edid; 2080 2081 vga_switcheroo_lock_ddc(pdev); 2082 edid = drm_get_edid(connector, adapter); 2083 vga_switcheroo_unlock_ddc(pdev); 2084 2085 return edid; 2086 } 2087 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2088 2089 /** 2090 * drm_edid_duplicate - duplicate an EDID and the extensions 2091 * @edid: EDID to duplicate 2092 * 2093 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2094 */ 2095 struct edid *drm_edid_duplicate(const struct edid *edid) 2096 { 2097 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2098 } 2099 EXPORT_SYMBOL(drm_edid_duplicate); 2100 2101 /*** EDID parsing ***/ 2102 2103 /** 2104 * edid_vendor - match a string against EDID's obfuscated vendor field 2105 * @edid: EDID to match 2106 * @vendor: vendor string 2107 * 2108 * Returns true if @vendor is in @edid, false otherwise 2109 */ 2110 static bool edid_vendor(const struct edid *edid, const char *vendor) 2111 { 2112 char edid_vendor[3]; 2113 2114 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2115 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2116 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2117 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2118 2119 return !strncmp(edid_vendor, vendor, 3); 2120 } 2121 2122 /** 2123 * edid_get_quirks - return quirk flags for a given EDID 2124 * @edid: EDID to process 2125 * 2126 * This tells subsequent routines what fixes they need to apply. 2127 */ 2128 static u32 edid_get_quirks(const struct edid *edid) 2129 { 2130 const struct edid_quirk *quirk; 2131 int i; 2132 2133 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2134 quirk = &edid_quirk_list[i]; 2135 2136 if (edid_vendor(edid, quirk->vendor) && 2137 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2138 return quirk->quirks; 2139 } 2140 2141 return 0; 2142 } 2143 2144 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2145 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2146 2147 /** 2148 * edid_fixup_preferred - set preferred modes based on quirk list 2149 * @connector: has mode list to fix up 2150 * @quirks: quirks list 2151 * 2152 * Walk the mode list for @connector, clearing the preferred status 2153 * on existing modes and setting it anew for the right mode ala @quirks. 2154 */ 2155 static void edid_fixup_preferred(struct drm_connector *connector, 2156 u32 quirks) 2157 { 2158 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2159 int target_refresh = 0; 2160 int cur_vrefresh, preferred_vrefresh; 2161 2162 if (list_empty(&connector->probed_modes)) 2163 return; 2164 2165 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2166 target_refresh = 60; 2167 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2168 target_refresh = 75; 2169 2170 preferred_mode = list_first_entry(&connector->probed_modes, 2171 struct drm_display_mode, head); 2172 2173 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2174 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2175 2176 if (cur_mode == preferred_mode) 2177 continue; 2178 2179 /* Largest mode is preferred */ 2180 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2181 preferred_mode = cur_mode; 2182 2183 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2184 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2185 /* At a given size, try to get closest to target refresh */ 2186 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2187 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2188 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2189 preferred_mode = cur_mode; 2190 } 2191 } 2192 2193 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2194 } 2195 2196 static bool 2197 mode_is_rb(const struct drm_display_mode *mode) 2198 { 2199 return (mode->htotal - mode->hdisplay == 160) && 2200 (mode->hsync_end - mode->hdisplay == 80) && 2201 (mode->hsync_end - mode->hsync_start == 32) && 2202 (mode->vsync_start - mode->vdisplay == 3); 2203 } 2204 2205 /* 2206 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2207 * @dev: Device to duplicate against 2208 * @hsize: Mode width 2209 * @vsize: Mode height 2210 * @fresh: Mode refresh rate 2211 * @rb: Mode reduced-blanking-ness 2212 * 2213 * Walk the DMT mode list looking for a match for the given parameters. 2214 * 2215 * Return: A newly allocated copy of the mode, or NULL if not found. 2216 */ 2217 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2218 int hsize, int vsize, int fresh, 2219 bool rb) 2220 { 2221 int i; 2222 2223 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2224 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2225 2226 if (hsize != ptr->hdisplay) 2227 continue; 2228 if (vsize != ptr->vdisplay) 2229 continue; 2230 if (fresh != drm_mode_vrefresh(ptr)) 2231 continue; 2232 if (rb != mode_is_rb(ptr)) 2233 continue; 2234 2235 return drm_mode_duplicate(dev, ptr); 2236 } 2237 2238 return NULL; 2239 } 2240 EXPORT_SYMBOL(drm_mode_find_dmt); 2241 2242 static bool is_display_descriptor(const u8 d[18], u8 tag) 2243 { 2244 return d[0] == 0x00 && d[1] == 0x00 && 2245 d[2] == 0x00 && d[3] == tag; 2246 } 2247 2248 static bool is_detailed_timing_descriptor(const u8 d[18]) 2249 { 2250 return d[0] != 0x00 || d[1] != 0x00; 2251 } 2252 2253 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2254 2255 static void 2256 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2257 { 2258 int i, n; 2259 u8 d = ext[0x02]; 2260 u8 *det_base = ext + d; 2261 2262 if (d < 4 || d > 127) 2263 return; 2264 2265 n = (127 - d) / 18; 2266 for (i = 0; i < n; i++) 2267 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2268 } 2269 2270 static void 2271 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2272 { 2273 unsigned int i, n = min((int)ext[0x02], 6); 2274 u8 *det_base = ext + 5; 2275 2276 if (ext[0x01] != 1) 2277 return; /* unknown version */ 2278 2279 for (i = 0; i < n; i++) 2280 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2281 } 2282 2283 static void 2284 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2285 { 2286 int i; 2287 struct edid *edid = (struct edid *)raw_edid; 2288 2289 if (edid == NULL) 2290 return; 2291 2292 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2293 cb(&(edid->detailed_timings[i]), closure); 2294 2295 for (i = 1; i <= raw_edid[0x7e]; i++) { 2296 u8 *ext = raw_edid + (i * EDID_LENGTH); 2297 2298 switch (*ext) { 2299 case CEA_EXT: 2300 cea_for_each_detailed_block(ext, cb, closure); 2301 break; 2302 case VTB_EXT: 2303 vtb_for_each_detailed_block(ext, cb, closure); 2304 break; 2305 default: 2306 break; 2307 } 2308 } 2309 } 2310 2311 static void 2312 is_rb(struct detailed_timing *t, void *data) 2313 { 2314 u8 *r = (u8 *)t; 2315 2316 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2317 return; 2318 2319 if (r[15] & 0x10) 2320 *(bool *)data = true; 2321 } 2322 2323 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2324 static bool 2325 drm_monitor_supports_rb(struct edid *edid) 2326 { 2327 if (edid->revision >= 4) { 2328 bool ret = false; 2329 2330 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2331 return ret; 2332 } 2333 2334 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2335 } 2336 2337 static void 2338 find_gtf2(struct detailed_timing *t, void *data) 2339 { 2340 u8 *r = (u8 *)t; 2341 2342 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2343 return; 2344 2345 if (r[10] == 0x02) 2346 *(u8 **)data = r; 2347 } 2348 2349 /* Secondary GTF curve kicks in above some break frequency */ 2350 static int 2351 drm_gtf2_hbreak(struct edid *edid) 2352 { 2353 u8 *r = NULL; 2354 2355 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2356 return r ? (r[12] * 2) : 0; 2357 } 2358 2359 static int 2360 drm_gtf2_2c(struct edid *edid) 2361 { 2362 u8 *r = NULL; 2363 2364 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2365 return r ? r[13] : 0; 2366 } 2367 2368 static int 2369 drm_gtf2_m(struct edid *edid) 2370 { 2371 u8 *r = NULL; 2372 2373 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2374 return r ? (r[15] << 8) + r[14] : 0; 2375 } 2376 2377 static int 2378 drm_gtf2_k(struct edid *edid) 2379 { 2380 u8 *r = NULL; 2381 2382 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2383 return r ? r[16] : 0; 2384 } 2385 2386 static int 2387 drm_gtf2_2j(struct edid *edid) 2388 { 2389 u8 *r = NULL; 2390 2391 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2392 return r ? r[17] : 0; 2393 } 2394 2395 /** 2396 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2397 * @edid: EDID block to scan 2398 */ 2399 static int standard_timing_level(struct edid *edid) 2400 { 2401 if (edid->revision >= 2) { 2402 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2403 return LEVEL_CVT; 2404 if (drm_gtf2_hbreak(edid)) 2405 return LEVEL_GTF2; 2406 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2407 return LEVEL_GTF; 2408 } 2409 return LEVEL_DMT; 2410 } 2411 2412 /* 2413 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2414 * monitors fill with ascii space (0x20) instead. 2415 */ 2416 static int 2417 bad_std_timing(u8 a, u8 b) 2418 { 2419 return (a == 0x00 && b == 0x00) || 2420 (a == 0x01 && b == 0x01) || 2421 (a == 0x20 && b == 0x20); 2422 } 2423 2424 static int drm_mode_hsync(const struct drm_display_mode *mode) 2425 { 2426 if (mode->htotal <= 0) 2427 return 0; 2428 2429 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2430 } 2431 2432 /** 2433 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2434 * @connector: connector of for the EDID block 2435 * @edid: EDID block to scan 2436 * @t: standard timing params 2437 * 2438 * Take the standard timing params (in this case width, aspect, and refresh) 2439 * and convert them into a real mode using CVT/GTF/DMT. 2440 */ 2441 static struct drm_display_mode * 2442 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2443 struct std_timing *t) 2444 { 2445 struct drm_device *dev = connector->dev; 2446 struct drm_display_mode *m, *mode = NULL; 2447 int hsize, vsize; 2448 int vrefresh_rate; 2449 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2450 >> EDID_TIMING_ASPECT_SHIFT; 2451 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2452 >> EDID_TIMING_VFREQ_SHIFT; 2453 int timing_level = standard_timing_level(edid); 2454 2455 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2456 return NULL; 2457 2458 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2459 hsize = t->hsize * 8 + 248; 2460 /* vrefresh_rate = vfreq + 60 */ 2461 vrefresh_rate = vfreq + 60; 2462 /* the vdisplay is calculated based on the aspect ratio */ 2463 if (aspect_ratio == 0) { 2464 if (edid->revision < 3) 2465 vsize = hsize; 2466 else 2467 vsize = (hsize * 10) / 16; 2468 } else if (aspect_ratio == 1) 2469 vsize = (hsize * 3) / 4; 2470 else if (aspect_ratio == 2) 2471 vsize = (hsize * 4) / 5; 2472 else 2473 vsize = (hsize * 9) / 16; 2474 2475 /* HDTV hack, part 1 */ 2476 if (vrefresh_rate == 60 && 2477 ((hsize == 1360 && vsize == 765) || 2478 (hsize == 1368 && vsize == 769))) { 2479 hsize = 1366; 2480 vsize = 768; 2481 } 2482 2483 /* 2484 * If this connector already has a mode for this size and refresh 2485 * rate (because it came from detailed or CVT info), use that 2486 * instead. This way we don't have to guess at interlace or 2487 * reduced blanking. 2488 */ 2489 list_for_each_entry(m, &connector->probed_modes, head) 2490 if (m->hdisplay == hsize && m->vdisplay == vsize && 2491 drm_mode_vrefresh(m) == vrefresh_rate) 2492 return NULL; 2493 2494 /* HDTV hack, part 2 */ 2495 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2496 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2497 false); 2498 if (!mode) 2499 return NULL; 2500 mode->hdisplay = 1366; 2501 mode->hsync_start = mode->hsync_start - 1; 2502 mode->hsync_end = mode->hsync_end - 1; 2503 return mode; 2504 } 2505 2506 /* check whether it can be found in default mode table */ 2507 if (drm_monitor_supports_rb(edid)) { 2508 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2509 true); 2510 if (mode) 2511 return mode; 2512 } 2513 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2514 if (mode) 2515 return mode; 2516 2517 /* okay, generate it */ 2518 switch (timing_level) { 2519 case LEVEL_DMT: 2520 break; 2521 case LEVEL_GTF: 2522 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2523 break; 2524 case LEVEL_GTF2: 2525 /* 2526 * This is potentially wrong if there's ever a monitor with 2527 * more than one ranges section, each claiming a different 2528 * secondary GTF curve. Please don't do that. 2529 */ 2530 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2531 if (!mode) 2532 return NULL; 2533 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2534 drm_mode_destroy(dev, mode); 2535 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2536 vrefresh_rate, 0, 0, 2537 drm_gtf2_m(edid), 2538 drm_gtf2_2c(edid), 2539 drm_gtf2_k(edid), 2540 drm_gtf2_2j(edid)); 2541 } 2542 break; 2543 case LEVEL_CVT: 2544 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2545 false); 2546 break; 2547 } 2548 return mode; 2549 } 2550 2551 /* 2552 * EDID is delightfully ambiguous about how interlaced modes are to be 2553 * encoded. Our internal representation is of frame height, but some 2554 * HDTV detailed timings are encoded as field height. 2555 * 2556 * The format list here is from CEA, in frame size. Technically we 2557 * should be checking refresh rate too. Whatever. 2558 */ 2559 static void 2560 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2561 struct detailed_pixel_timing *pt) 2562 { 2563 int i; 2564 static const struct { 2565 int w, h; 2566 } cea_interlaced[] = { 2567 { 1920, 1080 }, 2568 { 720, 480 }, 2569 { 1440, 480 }, 2570 { 2880, 480 }, 2571 { 720, 576 }, 2572 { 1440, 576 }, 2573 { 2880, 576 }, 2574 }; 2575 2576 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2577 return; 2578 2579 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2580 if ((mode->hdisplay == cea_interlaced[i].w) && 2581 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2582 mode->vdisplay *= 2; 2583 mode->vsync_start *= 2; 2584 mode->vsync_end *= 2; 2585 mode->vtotal *= 2; 2586 mode->vtotal |= 1; 2587 } 2588 } 2589 2590 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2591 } 2592 2593 /** 2594 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2595 * @dev: DRM device (needed to create new mode) 2596 * @edid: EDID block 2597 * @timing: EDID detailed timing info 2598 * @quirks: quirks to apply 2599 * 2600 * An EDID detailed timing block contains enough info for us to create and 2601 * return a new struct drm_display_mode. 2602 */ 2603 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2604 struct edid *edid, 2605 struct detailed_timing *timing, 2606 u32 quirks) 2607 { 2608 struct drm_display_mode *mode; 2609 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2610 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2611 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2612 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2613 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2614 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2615 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2616 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2617 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2618 2619 /* ignore tiny modes */ 2620 if (hactive < 64 || vactive < 64) 2621 return NULL; 2622 2623 if (pt->misc & DRM_EDID_PT_STEREO) { 2624 DRM_DEBUG_KMS("stereo mode not supported\n"); 2625 return NULL; 2626 } 2627 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2628 DRM_DEBUG_KMS("composite sync not supported\n"); 2629 } 2630 2631 /* it is incorrect if hsync/vsync width is zero */ 2632 if (!hsync_pulse_width || !vsync_pulse_width) { 2633 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2634 "Wrong Hsync/Vsync pulse width\n"); 2635 return NULL; 2636 } 2637 2638 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2639 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2640 if (!mode) 2641 return NULL; 2642 2643 goto set_size; 2644 } 2645 2646 mode = drm_mode_create(dev); 2647 if (!mode) 2648 return NULL; 2649 2650 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2651 timing->pixel_clock = cpu_to_le16(1088); 2652 2653 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2654 2655 mode->hdisplay = hactive; 2656 mode->hsync_start = mode->hdisplay + hsync_offset; 2657 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2658 mode->htotal = mode->hdisplay + hblank; 2659 2660 mode->vdisplay = vactive; 2661 mode->vsync_start = mode->vdisplay + vsync_offset; 2662 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2663 mode->vtotal = mode->vdisplay + vblank; 2664 2665 /* Some EDIDs have bogus h/vtotal values */ 2666 if (mode->hsync_end > mode->htotal) 2667 mode->htotal = mode->hsync_end + 1; 2668 if (mode->vsync_end > mode->vtotal) 2669 mode->vtotal = mode->vsync_end + 1; 2670 2671 drm_mode_do_interlace_quirk(mode, pt); 2672 2673 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2674 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2675 } 2676 2677 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2678 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2679 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2680 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2681 2682 set_size: 2683 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2684 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2685 2686 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2687 mode->width_mm *= 10; 2688 mode->height_mm *= 10; 2689 } 2690 2691 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2692 mode->width_mm = edid->width_cm * 10; 2693 mode->height_mm = edid->height_cm * 10; 2694 } 2695 2696 mode->type = DRM_MODE_TYPE_DRIVER; 2697 drm_mode_set_name(mode); 2698 2699 return mode; 2700 } 2701 2702 static bool 2703 mode_in_hsync_range(const struct drm_display_mode *mode, 2704 struct edid *edid, u8 *t) 2705 { 2706 int hsync, hmin, hmax; 2707 2708 hmin = t[7]; 2709 if (edid->revision >= 4) 2710 hmin += ((t[4] & 0x04) ? 255 : 0); 2711 hmax = t[8]; 2712 if (edid->revision >= 4) 2713 hmax += ((t[4] & 0x08) ? 255 : 0); 2714 hsync = drm_mode_hsync(mode); 2715 2716 return (hsync <= hmax && hsync >= hmin); 2717 } 2718 2719 static bool 2720 mode_in_vsync_range(const struct drm_display_mode *mode, 2721 struct edid *edid, u8 *t) 2722 { 2723 int vsync, vmin, vmax; 2724 2725 vmin = t[5]; 2726 if (edid->revision >= 4) 2727 vmin += ((t[4] & 0x01) ? 255 : 0); 2728 vmax = t[6]; 2729 if (edid->revision >= 4) 2730 vmax += ((t[4] & 0x02) ? 255 : 0); 2731 vsync = drm_mode_vrefresh(mode); 2732 2733 return (vsync <= vmax && vsync >= vmin); 2734 } 2735 2736 static u32 2737 range_pixel_clock(struct edid *edid, u8 *t) 2738 { 2739 /* unspecified */ 2740 if (t[9] == 0 || t[9] == 255) 2741 return 0; 2742 2743 /* 1.4 with CVT support gives us real precision, yay */ 2744 if (edid->revision >= 4 && t[10] == 0x04) 2745 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2746 2747 /* 1.3 is pathetic, so fuzz up a bit */ 2748 return t[9] * 10000 + 5001; 2749 } 2750 2751 static bool 2752 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2753 struct detailed_timing *timing) 2754 { 2755 u32 max_clock; 2756 u8 *t = (u8 *)timing; 2757 2758 if (!mode_in_hsync_range(mode, edid, t)) 2759 return false; 2760 2761 if (!mode_in_vsync_range(mode, edid, t)) 2762 return false; 2763 2764 if ((max_clock = range_pixel_clock(edid, t))) 2765 if (mode->clock > max_clock) 2766 return false; 2767 2768 /* 1.4 max horizontal check */ 2769 if (edid->revision >= 4 && t[10] == 0x04) 2770 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2771 return false; 2772 2773 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2774 return false; 2775 2776 return true; 2777 } 2778 2779 static bool valid_inferred_mode(const struct drm_connector *connector, 2780 const struct drm_display_mode *mode) 2781 { 2782 const struct drm_display_mode *m; 2783 bool ok = false; 2784 2785 list_for_each_entry(m, &connector->probed_modes, head) { 2786 if (mode->hdisplay == m->hdisplay && 2787 mode->vdisplay == m->vdisplay && 2788 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2789 return false; /* duplicated */ 2790 if (mode->hdisplay <= m->hdisplay && 2791 mode->vdisplay <= m->vdisplay) 2792 ok = true; 2793 } 2794 return ok; 2795 } 2796 2797 static int 2798 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2799 struct detailed_timing *timing) 2800 { 2801 int i, modes = 0; 2802 struct drm_display_mode *newmode; 2803 struct drm_device *dev = connector->dev; 2804 2805 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2806 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2807 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2808 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2809 if (newmode) { 2810 drm_mode_probed_add(connector, newmode); 2811 modes++; 2812 } 2813 } 2814 } 2815 2816 return modes; 2817 } 2818 2819 /* fix up 1366x768 mode from 1368x768; 2820 * GFT/CVT can't express 1366 width which isn't dividable by 8 2821 */ 2822 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2823 { 2824 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2825 mode->hdisplay = 1366; 2826 mode->hsync_start--; 2827 mode->hsync_end--; 2828 drm_mode_set_name(mode); 2829 } 2830 } 2831 2832 static int 2833 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2834 struct detailed_timing *timing) 2835 { 2836 int i, modes = 0; 2837 struct drm_display_mode *newmode; 2838 struct drm_device *dev = connector->dev; 2839 2840 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2841 const struct minimode *m = &extra_modes[i]; 2842 2843 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2844 if (!newmode) 2845 return modes; 2846 2847 drm_mode_fixup_1366x768(newmode); 2848 if (!mode_in_range(newmode, edid, timing) || 2849 !valid_inferred_mode(connector, newmode)) { 2850 drm_mode_destroy(dev, newmode); 2851 continue; 2852 } 2853 2854 drm_mode_probed_add(connector, newmode); 2855 modes++; 2856 } 2857 2858 return modes; 2859 } 2860 2861 static int 2862 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2863 struct detailed_timing *timing) 2864 { 2865 int i, modes = 0; 2866 struct drm_display_mode *newmode; 2867 struct drm_device *dev = connector->dev; 2868 bool rb = drm_monitor_supports_rb(edid); 2869 2870 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2871 const struct minimode *m = &extra_modes[i]; 2872 2873 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2874 if (!newmode) 2875 return modes; 2876 2877 drm_mode_fixup_1366x768(newmode); 2878 if (!mode_in_range(newmode, edid, timing) || 2879 !valid_inferred_mode(connector, newmode)) { 2880 drm_mode_destroy(dev, newmode); 2881 continue; 2882 } 2883 2884 drm_mode_probed_add(connector, newmode); 2885 modes++; 2886 } 2887 2888 return modes; 2889 } 2890 2891 static void 2892 do_inferred_modes(struct detailed_timing *timing, void *c) 2893 { 2894 struct detailed_mode_closure *closure = c; 2895 struct detailed_non_pixel *data = &timing->data.other_data; 2896 struct detailed_data_monitor_range *range = &data->data.range; 2897 2898 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2899 return; 2900 2901 closure->modes += drm_dmt_modes_for_range(closure->connector, 2902 closure->edid, 2903 timing); 2904 2905 if (!version_greater(closure->edid, 1, 1)) 2906 return; /* GTF not defined yet */ 2907 2908 switch (range->flags) { 2909 case 0x02: /* secondary gtf, XXX could do more */ 2910 case 0x00: /* default gtf */ 2911 closure->modes += drm_gtf_modes_for_range(closure->connector, 2912 closure->edid, 2913 timing); 2914 break; 2915 case 0x04: /* cvt, only in 1.4+ */ 2916 if (!version_greater(closure->edid, 1, 3)) 2917 break; 2918 2919 closure->modes += drm_cvt_modes_for_range(closure->connector, 2920 closure->edid, 2921 timing); 2922 break; 2923 case 0x01: /* just the ranges, no formula */ 2924 default: 2925 break; 2926 } 2927 } 2928 2929 static int 2930 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2931 { 2932 struct detailed_mode_closure closure = { 2933 .connector = connector, 2934 .edid = edid, 2935 }; 2936 2937 if (version_greater(edid, 1, 0)) 2938 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2939 &closure); 2940 2941 return closure.modes; 2942 } 2943 2944 static int 2945 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2946 { 2947 int i, j, m, modes = 0; 2948 struct drm_display_mode *mode; 2949 u8 *est = ((u8 *)timing) + 6; 2950 2951 for (i = 0; i < 6; i++) { 2952 for (j = 7; j >= 0; j--) { 2953 m = (i * 8) + (7 - j); 2954 if (m >= ARRAY_SIZE(est3_modes)) 2955 break; 2956 if (est[i] & (1 << j)) { 2957 mode = drm_mode_find_dmt(connector->dev, 2958 est3_modes[m].w, 2959 est3_modes[m].h, 2960 est3_modes[m].r, 2961 est3_modes[m].rb); 2962 if (mode) { 2963 drm_mode_probed_add(connector, mode); 2964 modes++; 2965 } 2966 } 2967 } 2968 } 2969 2970 return modes; 2971 } 2972 2973 static void 2974 do_established_modes(struct detailed_timing *timing, void *c) 2975 { 2976 struct detailed_mode_closure *closure = c; 2977 2978 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2979 return; 2980 2981 closure->modes += drm_est3_modes(closure->connector, timing); 2982 } 2983 2984 /** 2985 * add_established_modes - get est. modes from EDID and add them 2986 * @connector: connector to add mode(s) to 2987 * @edid: EDID block to scan 2988 * 2989 * Each EDID block contains a bitmap of the supported "established modes" list 2990 * (defined above). Tease them out and add them to the global modes list. 2991 */ 2992 static int 2993 add_established_modes(struct drm_connector *connector, struct edid *edid) 2994 { 2995 struct drm_device *dev = connector->dev; 2996 unsigned long est_bits = edid->established_timings.t1 | 2997 (edid->established_timings.t2 << 8) | 2998 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2999 int i, modes = 0; 3000 struct detailed_mode_closure closure = { 3001 .connector = connector, 3002 .edid = edid, 3003 }; 3004 3005 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3006 if (est_bits & (1<<i)) { 3007 struct drm_display_mode *newmode; 3008 3009 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3010 if (newmode) { 3011 drm_mode_probed_add(connector, newmode); 3012 modes++; 3013 } 3014 } 3015 } 3016 3017 if (version_greater(edid, 1, 0)) 3018 drm_for_each_detailed_block((u8 *)edid, 3019 do_established_modes, &closure); 3020 3021 return modes + closure.modes; 3022 } 3023 3024 static void 3025 do_standard_modes(struct detailed_timing *timing, void *c) 3026 { 3027 struct detailed_mode_closure *closure = c; 3028 struct detailed_non_pixel *data = &timing->data.other_data; 3029 struct drm_connector *connector = closure->connector; 3030 struct edid *edid = closure->edid; 3031 int i; 3032 3033 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3034 return; 3035 3036 for (i = 0; i < 6; i++) { 3037 struct std_timing *std = &data->data.timings[i]; 3038 struct drm_display_mode *newmode; 3039 3040 newmode = drm_mode_std(connector, edid, std); 3041 if (newmode) { 3042 drm_mode_probed_add(connector, newmode); 3043 closure->modes++; 3044 } 3045 } 3046 } 3047 3048 /** 3049 * add_standard_modes - get std. modes from EDID and add them 3050 * @connector: connector to add mode(s) to 3051 * @edid: EDID block to scan 3052 * 3053 * Standard modes can be calculated using the appropriate standard (DMT, 3054 * GTF or CVT. Grab them from @edid and add them to the list. 3055 */ 3056 static int 3057 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3058 { 3059 int i, modes = 0; 3060 struct detailed_mode_closure closure = { 3061 .connector = connector, 3062 .edid = edid, 3063 }; 3064 3065 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3066 struct drm_display_mode *newmode; 3067 3068 newmode = drm_mode_std(connector, edid, 3069 &edid->standard_timings[i]); 3070 if (newmode) { 3071 drm_mode_probed_add(connector, newmode); 3072 modes++; 3073 } 3074 } 3075 3076 if (version_greater(edid, 1, 0)) 3077 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3078 &closure); 3079 3080 /* XXX should also look for standard codes in VTB blocks */ 3081 3082 return modes + closure.modes; 3083 } 3084 3085 static int drm_cvt_modes(struct drm_connector *connector, 3086 struct detailed_timing *timing) 3087 { 3088 int i, j, modes = 0; 3089 struct drm_display_mode *newmode; 3090 struct drm_device *dev = connector->dev; 3091 struct cvt_timing *cvt; 3092 const int rates[] = { 60, 85, 75, 60, 50 }; 3093 const u8 empty[3] = { 0, 0, 0 }; 3094 3095 for (i = 0; i < 4; i++) { 3096 int width, height; 3097 3098 cvt = &(timing->data.other_data.data.cvt[i]); 3099 3100 if (!memcmp(cvt->code, empty, 3)) 3101 continue; 3102 3103 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3104 switch (cvt->code[1] & 0x0c) { 3105 /* default - because compiler doesn't see that we've enumerated all cases */ 3106 default: 3107 case 0x00: 3108 width = height * 4 / 3; 3109 break; 3110 case 0x04: 3111 width = height * 16 / 9; 3112 break; 3113 case 0x08: 3114 width = height * 16 / 10; 3115 break; 3116 case 0x0c: 3117 width = height * 15 / 9; 3118 break; 3119 } 3120 3121 for (j = 1; j < 5; j++) { 3122 if (cvt->code[2] & (1 << j)) { 3123 newmode = drm_cvt_mode(dev, width, height, 3124 rates[j], j == 0, 3125 false, false); 3126 if (newmode) { 3127 drm_mode_probed_add(connector, newmode); 3128 modes++; 3129 } 3130 } 3131 } 3132 } 3133 3134 return modes; 3135 } 3136 3137 static void 3138 do_cvt_mode(struct detailed_timing *timing, void *c) 3139 { 3140 struct detailed_mode_closure *closure = c; 3141 3142 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3143 return; 3144 3145 closure->modes += drm_cvt_modes(closure->connector, timing); 3146 } 3147 3148 static int 3149 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3150 { 3151 struct detailed_mode_closure closure = { 3152 .connector = connector, 3153 .edid = edid, 3154 }; 3155 3156 if (version_greater(edid, 1, 2)) 3157 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3158 3159 /* XXX should also look for CVT codes in VTB blocks */ 3160 3161 return closure.modes; 3162 } 3163 3164 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3165 3166 static void 3167 do_detailed_mode(struct detailed_timing *timing, void *c) 3168 { 3169 struct detailed_mode_closure *closure = c; 3170 struct drm_display_mode *newmode; 3171 3172 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3173 return; 3174 3175 newmode = drm_mode_detailed(closure->connector->dev, 3176 closure->edid, timing, 3177 closure->quirks); 3178 if (!newmode) 3179 return; 3180 3181 if (closure->preferred) 3182 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3183 3184 /* 3185 * Detailed modes are limited to 10kHz pixel clock resolution, 3186 * so fix up anything that looks like CEA/HDMI mode, but the clock 3187 * is just slightly off. 3188 */ 3189 fixup_detailed_cea_mode_clock(newmode); 3190 3191 drm_mode_probed_add(closure->connector, newmode); 3192 closure->modes++; 3193 closure->preferred = false; 3194 } 3195 3196 /* 3197 * add_detailed_modes - Add modes from detailed timings 3198 * @connector: attached connector 3199 * @edid: EDID block to scan 3200 * @quirks: quirks to apply 3201 */ 3202 static int 3203 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3204 u32 quirks) 3205 { 3206 struct detailed_mode_closure closure = { 3207 .connector = connector, 3208 .edid = edid, 3209 .preferred = true, 3210 .quirks = quirks, 3211 }; 3212 3213 if (closure.preferred && !version_greater(edid, 1, 3)) 3214 closure.preferred = 3215 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3216 3217 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3218 3219 return closure.modes; 3220 } 3221 3222 #define AUDIO_BLOCK 0x01 3223 #define VIDEO_BLOCK 0x02 3224 #define VENDOR_BLOCK 0x03 3225 #define SPEAKER_BLOCK 0x04 3226 #define HDR_STATIC_METADATA_BLOCK 0x6 3227 #define USE_EXTENDED_TAG 0x07 3228 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3229 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3230 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3231 #define EDID_BASIC_AUDIO (1 << 6) 3232 #define EDID_CEA_YCRCB444 (1 << 5) 3233 #define EDID_CEA_YCRCB422 (1 << 4) 3234 #define EDID_CEA_VCDB_QS (1 << 6) 3235 3236 /* 3237 * Search EDID for CEA extension block. 3238 */ 3239 static u8 *drm_find_edid_extension(const struct edid *edid, 3240 int ext_id, int *ext_index) 3241 { 3242 u8 *edid_ext = NULL; 3243 int i; 3244 3245 /* No EDID or EDID extensions */ 3246 if (edid == NULL || edid->extensions == 0) 3247 return NULL; 3248 3249 /* Find CEA extension */ 3250 for (i = *ext_index; i < edid->extensions; i++) { 3251 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3252 if (edid_ext[0] == ext_id) 3253 break; 3254 } 3255 3256 if (i >= edid->extensions) 3257 return NULL; 3258 3259 *ext_index = i + 1; 3260 3261 return edid_ext; 3262 } 3263 3264 3265 static u8 *drm_find_displayid_extension(const struct edid *edid, 3266 int *length, int *idx, 3267 int *ext_index) 3268 { 3269 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index); 3270 struct displayid_hdr *base; 3271 int ret; 3272 3273 if (!displayid) 3274 return NULL; 3275 3276 /* EDID extensions block checksum isn't for us */ 3277 *length = EDID_LENGTH - 1; 3278 *idx = 1; 3279 3280 ret = validate_displayid(displayid, *length, *idx); 3281 if (ret) 3282 return NULL; 3283 3284 base = (struct displayid_hdr *)&displayid[*idx]; 3285 *length = *idx + sizeof(*base) + base->bytes; 3286 3287 return displayid; 3288 } 3289 3290 static u8 *drm_find_cea_extension(const struct edid *edid) 3291 { 3292 int length, idx; 3293 struct displayid_block *block; 3294 u8 *cea; 3295 u8 *displayid; 3296 int ext_index; 3297 3298 /* Look for a top level CEA extension block */ 3299 /* FIXME: make callers iterate through multiple CEA ext blocks? */ 3300 ext_index = 0; 3301 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); 3302 if (cea) 3303 return cea; 3304 3305 /* CEA blocks can also be found embedded in a DisplayID block */ 3306 ext_index = 0; 3307 for (;;) { 3308 displayid = drm_find_displayid_extension(edid, &length, &idx, 3309 &ext_index); 3310 if (!displayid) 3311 return NULL; 3312 3313 idx += sizeof(struct displayid_hdr); 3314 for_each_displayid_db(displayid, block, idx, length) { 3315 if (block->tag == DATA_BLOCK_CTA) 3316 return (u8 *)block; 3317 } 3318 } 3319 3320 return NULL; 3321 } 3322 3323 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3324 { 3325 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3326 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3327 3328 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3329 return &edid_cea_modes_1[vic - 1]; 3330 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3331 return &edid_cea_modes_193[vic - 193]; 3332 return NULL; 3333 } 3334 3335 static u8 cea_num_vics(void) 3336 { 3337 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3338 } 3339 3340 static u8 cea_next_vic(u8 vic) 3341 { 3342 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3343 vic = 193; 3344 return vic; 3345 } 3346 3347 /* 3348 * Calculate the alternate clock for the CEA mode 3349 * (60Hz vs. 59.94Hz etc.) 3350 */ 3351 static unsigned int 3352 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3353 { 3354 unsigned int clock = cea_mode->clock; 3355 3356 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3357 return clock; 3358 3359 /* 3360 * edid_cea_modes contains the 59.94Hz 3361 * variant for 240 and 480 line modes, 3362 * and the 60Hz variant otherwise. 3363 */ 3364 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3365 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3366 else 3367 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3368 3369 return clock; 3370 } 3371 3372 static bool 3373 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3374 { 3375 /* 3376 * For certain VICs the spec allows the vertical 3377 * front porch to vary by one or two lines. 3378 * 3379 * cea_modes[] stores the variant with the shortest 3380 * vertical front porch. We can adjust the mode to 3381 * get the other variants by simply increasing the 3382 * vertical front porch length. 3383 */ 3384 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3385 cea_mode_for_vic(9)->vtotal != 262 || 3386 cea_mode_for_vic(12)->vtotal != 262 || 3387 cea_mode_for_vic(13)->vtotal != 262 || 3388 cea_mode_for_vic(23)->vtotal != 312 || 3389 cea_mode_for_vic(24)->vtotal != 312 || 3390 cea_mode_for_vic(27)->vtotal != 312 || 3391 cea_mode_for_vic(28)->vtotal != 312); 3392 3393 if (((vic == 8 || vic == 9 || 3394 vic == 12 || vic == 13) && mode->vtotal < 263) || 3395 ((vic == 23 || vic == 24 || 3396 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3397 mode->vsync_start++; 3398 mode->vsync_end++; 3399 mode->vtotal++; 3400 3401 return true; 3402 } 3403 3404 return false; 3405 } 3406 3407 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3408 unsigned int clock_tolerance) 3409 { 3410 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3411 u8 vic; 3412 3413 if (!to_match->clock) 3414 return 0; 3415 3416 if (to_match->picture_aspect_ratio) 3417 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3418 3419 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3420 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3421 unsigned int clock1, clock2; 3422 3423 /* Check both 60Hz and 59.94Hz */ 3424 clock1 = cea_mode.clock; 3425 clock2 = cea_mode_alternate_clock(&cea_mode); 3426 3427 if (abs(to_match->clock - clock1) > clock_tolerance && 3428 abs(to_match->clock - clock2) > clock_tolerance) 3429 continue; 3430 3431 do { 3432 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3433 return vic; 3434 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3435 } 3436 3437 return 0; 3438 } 3439 3440 /** 3441 * drm_match_cea_mode - look for a CEA mode matching given mode 3442 * @to_match: display mode 3443 * 3444 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3445 * mode. 3446 */ 3447 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3448 { 3449 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3450 u8 vic; 3451 3452 if (!to_match->clock) 3453 return 0; 3454 3455 if (to_match->picture_aspect_ratio) 3456 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3457 3458 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3459 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3460 unsigned int clock1, clock2; 3461 3462 /* Check both 60Hz and 59.94Hz */ 3463 clock1 = cea_mode.clock; 3464 clock2 = cea_mode_alternate_clock(&cea_mode); 3465 3466 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3467 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3468 continue; 3469 3470 do { 3471 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3472 return vic; 3473 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3474 } 3475 3476 return 0; 3477 } 3478 EXPORT_SYMBOL(drm_match_cea_mode); 3479 3480 static bool drm_valid_cea_vic(u8 vic) 3481 { 3482 return cea_mode_for_vic(vic) != NULL; 3483 } 3484 3485 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3486 { 3487 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3488 3489 if (mode) 3490 return mode->picture_aspect_ratio; 3491 3492 return HDMI_PICTURE_ASPECT_NONE; 3493 } 3494 3495 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3496 { 3497 return edid_4k_modes[video_code].picture_aspect_ratio; 3498 } 3499 3500 /* 3501 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3502 * specific block). 3503 */ 3504 static unsigned int 3505 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3506 { 3507 return cea_mode_alternate_clock(hdmi_mode); 3508 } 3509 3510 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3511 unsigned int clock_tolerance) 3512 { 3513 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3514 u8 vic; 3515 3516 if (!to_match->clock) 3517 return 0; 3518 3519 if (to_match->picture_aspect_ratio) 3520 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3521 3522 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3523 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3524 unsigned int clock1, clock2; 3525 3526 /* Make sure to also match alternate clocks */ 3527 clock1 = hdmi_mode->clock; 3528 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3529 3530 if (abs(to_match->clock - clock1) > clock_tolerance && 3531 abs(to_match->clock - clock2) > clock_tolerance) 3532 continue; 3533 3534 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3535 return vic; 3536 } 3537 3538 return 0; 3539 } 3540 3541 /* 3542 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3543 * @to_match: display mode 3544 * 3545 * An HDMI mode is one defined in the HDMI vendor specific block. 3546 * 3547 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3548 */ 3549 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3550 { 3551 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3552 u8 vic; 3553 3554 if (!to_match->clock) 3555 return 0; 3556 3557 if (to_match->picture_aspect_ratio) 3558 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3559 3560 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3561 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3562 unsigned int clock1, clock2; 3563 3564 /* Make sure to also match alternate clocks */ 3565 clock1 = hdmi_mode->clock; 3566 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3567 3568 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3569 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3570 drm_mode_match(to_match, hdmi_mode, match_flags)) 3571 return vic; 3572 } 3573 return 0; 3574 } 3575 3576 static bool drm_valid_hdmi_vic(u8 vic) 3577 { 3578 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3579 } 3580 3581 static int 3582 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3583 { 3584 struct drm_device *dev = connector->dev; 3585 struct drm_display_mode *mode, *tmp; 3586 LIST_HEAD(list); 3587 int modes = 0; 3588 3589 /* Don't add CEA modes if the CEA extension block is missing */ 3590 if (!drm_find_cea_extension(edid)) 3591 return 0; 3592 3593 /* 3594 * Go through all probed modes and create a new mode 3595 * with the alternate clock for certain CEA modes. 3596 */ 3597 list_for_each_entry(mode, &connector->probed_modes, head) { 3598 const struct drm_display_mode *cea_mode = NULL; 3599 struct drm_display_mode *newmode; 3600 u8 vic = drm_match_cea_mode(mode); 3601 unsigned int clock1, clock2; 3602 3603 if (drm_valid_cea_vic(vic)) { 3604 cea_mode = cea_mode_for_vic(vic); 3605 clock2 = cea_mode_alternate_clock(cea_mode); 3606 } else { 3607 vic = drm_match_hdmi_mode(mode); 3608 if (drm_valid_hdmi_vic(vic)) { 3609 cea_mode = &edid_4k_modes[vic]; 3610 clock2 = hdmi_mode_alternate_clock(cea_mode); 3611 } 3612 } 3613 3614 if (!cea_mode) 3615 continue; 3616 3617 clock1 = cea_mode->clock; 3618 3619 if (clock1 == clock2) 3620 continue; 3621 3622 if (mode->clock != clock1 && mode->clock != clock2) 3623 continue; 3624 3625 newmode = drm_mode_duplicate(dev, cea_mode); 3626 if (!newmode) 3627 continue; 3628 3629 /* Carry over the stereo flags */ 3630 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3631 3632 /* 3633 * The current mode could be either variant. Make 3634 * sure to pick the "other" clock for the new mode. 3635 */ 3636 if (mode->clock != clock1) 3637 newmode->clock = clock1; 3638 else 3639 newmode->clock = clock2; 3640 3641 list_add_tail(&newmode->head, &list); 3642 } 3643 3644 list_for_each_entry_safe(mode, tmp, &list, head) { 3645 list_del(&mode->head); 3646 drm_mode_probed_add(connector, mode); 3647 modes++; 3648 } 3649 3650 return modes; 3651 } 3652 3653 static u8 svd_to_vic(u8 svd) 3654 { 3655 /* 0-6 bit vic, 7th bit native mode indicator */ 3656 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3657 return svd & 127; 3658 3659 return svd; 3660 } 3661 3662 static struct drm_display_mode * 3663 drm_display_mode_from_vic_index(struct drm_connector *connector, 3664 const u8 *video_db, u8 video_len, 3665 u8 video_index) 3666 { 3667 struct drm_device *dev = connector->dev; 3668 struct drm_display_mode *newmode; 3669 u8 vic; 3670 3671 if (video_db == NULL || video_index >= video_len) 3672 return NULL; 3673 3674 /* CEA modes are numbered 1..127 */ 3675 vic = svd_to_vic(video_db[video_index]); 3676 if (!drm_valid_cea_vic(vic)) 3677 return NULL; 3678 3679 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3680 if (!newmode) 3681 return NULL; 3682 3683 return newmode; 3684 } 3685 3686 /* 3687 * do_y420vdb_modes - Parse YCBCR 420 only modes 3688 * @connector: connector corresponding to the HDMI sink 3689 * @svds: start of the data block of CEA YCBCR 420 VDB 3690 * @len: length of the CEA YCBCR 420 VDB 3691 * 3692 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3693 * which contains modes which can be supported in YCBCR 420 3694 * output format only. 3695 */ 3696 static int do_y420vdb_modes(struct drm_connector *connector, 3697 const u8 *svds, u8 svds_len) 3698 { 3699 int modes = 0, i; 3700 struct drm_device *dev = connector->dev; 3701 struct drm_display_info *info = &connector->display_info; 3702 struct drm_hdmi_info *hdmi = &info->hdmi; 3703 3704 for (i = 0; i < svds_len; i++) { 3705 u8 vic = svd_to_vic(svds[i]); 3706 struct drm_display_mode *newmode; 3707 3708 if (!drm_valid_cea_vic(vic)) 3709 continue; 3710 3711 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3712 if (!newmode) 3713 break; 3714 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3715 drm_mode_probed_add(connector, newmode); 3716 modes++; 3717 } 3718 3719 if (modes > 0) 3720 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3721 return modes; 3722 } 3723 3724 /* 3725 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3726 * @connector: connector corresponding to the HDMI sink 3727 * @vic: CEA vic for the video mode to be added in the map 3728 * 3729 * Makes an entry for a videomode in the YCBCR 420 bitmap 3730 */ 3731 static void 3732 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3733 { 3734 u8 vic = svd_to_vic(svd); 3735 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3736 3737 if (!drm_valid_cea_vic(vic)) 3738 return; 3739 3740 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3741 } 3742 3743 /** 3744 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 3745 * @dev: DRM device 3746 * @video_code: CEA VIC of the mode 3747 * 3748 * Creates a new mode matching the specified CEA VIC. 3749 * 3750 * Returns: A new drm_display_mode on success or NULL on failure 3751 */ 3752 struct drm_display_mode * 3753 drm_display_mode_from_cea_vic(struct drm_device *dev, 3754 u8 video_code) 3755 { 3756 const struct drm_display_mode *cea_mode; 3757 struct drm_display_mode *newmode; 3758 3759 cea_mode = cea_mode_for_vic(video_code); 3760 if (!cea_mode) 3761 return NULL; 3762 3763 newmode = drm_mode_duplicate(dev, cea_mode); 3764 if (!newmode) 3765 return NULL; 3766 3767 return newmode; 3768 } 3769 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 3770 3771 static int 3772 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3773 { 3774 int i, modes = 0; 3775 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3776 3777 for (i = 0; i < len; i++) { 3778 struct drm_display_mode *mode; 3779 3780 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3781 if (mode) { 3782 /* 3783 * YCBCR420 capability block contains a bitmap which 3784 * gives the index of CEA modes from CEA VDB, which 3785 * can support YCBCR 420 sampling output also (apart 3786 * from RGB/YCBCR444 etc). 3787 * For example, if the bit 0 in bitmap is set, 3788 * first mode in VDB can support YCBCR420 output too. 3789 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3790 */ 3791 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3792 drm_add_cmdb_modes(connector, db[i]); 3793 3794 drm_mode_probed_add(connector, mode); 3795 modes++; 3796 } 3797 } 3798 3799 return modes; 3800 } 3801 3802 struct stereo_mandatory_mode { 3803 int width, height, vrefresh; 3804 unsigned int flags; 3805 }; 3806 3807 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3808 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3809 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3810 { 1920, 1080, 50, 3811 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3812 { 1920, 1080, 60, 3813 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3814 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3815 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3816 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3817 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3818 }; 3819 3820 static bool 3821 stereo_match_mandatory(const struct drm_display_mode *mode, 3822 const struct stereo_mandatory_mode *stereo_mode) 3823 { 3824 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3825 3826 return mode->hdisplay == stereo_mode->width && 3827 mode->vdisplay == stereo_mode->height && 3828 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3829 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3830 } 3831 3832 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3833 { 3834 struct drm_device *dev = connector->dev; 3835 const struct drm_display_mode *mode; 3836 struct list_head stereo_modes; 3837 int modes = 0, i; 3838 3839 INIT_LIST_HEAD(&stereo_modes); 3840 3841 list_for_each_entry(mode, &connector->probed_modes, head) { 3842 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3843 const struct stereo_mandatory_mode *mandatory; 3844 struct drm_display_mode *new_mode; 3845 3846 if (!stereo_match_mandatory(mode, 3847 &stereo_mandatory_modes[i])) 3848 continue; 3849 3850 mandatory = &stereo_mandatory_modes[i]; 3851 new_mode = drm_mode_duplicate(dev, mode); 3852 if (!new_mode) 3853 continue; 3854 3855 new_mode->flags |= mandatory->flags; 3856 list_add_tail(&new_mode->head, &stereo_modes); 3857 modes++; 3858 } 3859 } 3860 3861 list_splice_tail(&stereo_modes, &connector->probed_modes); 3862 3863 return modes; 3864 } 3865 3866 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3867 { 3868 struct drm_device *dev = connector->dev; 3869 struct drm_display_mode *newmode; 3870 3871 if (!drm_valid_hdmi_vic(vic)) { 3872 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3873 return 0; 3874 } 3875 3876 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3877 if (!newmode) 3878 return 0; 3879 3880 drm_mode_probed_add(connector, newmode); 3881 3882 return 1; 3883 } 3884 3885 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3886 const u8 *video_db, u8 video_len, u8 video_index) 3887 { 3888 struct drm_display_mode *newmode; 3889 int modes = 0; 3890 3891 if (structure & (1 << 0)) { 3892 newmode = drm_display_mode_from_vic_index(connector, video_db, 3893 video_len, 3894 video_index); 3895 if (newmode) { 3896 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3897 drm_mode_probed_add(connector, newmode); 3898 modes++; 3899 } 3900 } 3901 if (structure & (1 << 6)) { 3902 newmode = drm_display_mode_from_vic_index(connector, video_db, 3903 video_len, 3904 video_index); 3905 if (newmode) { 3906 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3907 drm_mode_probed_add(connector, newmode); 3908 modes++; 3909 } 3910 } 3911 if (structure & (1 << 8)) { 3912 newmode = drm_display_mode_from_vic_index(connector, video_db, 3913 video_len, 3914 video_index); 3915 if (newmode) { 3916 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3917 drm_mode_probed_add(connector, newmode); 3918 modes++; 3919 } 3920 } 3921 3922 return modes; 3923 } 3924 3925 /* 3926 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3927 * @connector: connector corresponding to the HDMI sink 3928 * @db: start of the CEA vendor specific block 3929 * @len: length of the CEA block payload, ie. one can access up to db[len] 3930 * 3931 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3932 * also adds the stereo 3d modes when applicable. 3933 */ 3934 static int 3935 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3936 const u8 *video_db, u8 video_len) 3937 { 3938 struct drm_display_info *info = &connector->display_info; 3939 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3940 u8 vic_len, hdmi_3d_len = 0; 3941 u16 mask; 3942 u16 structure_all; 3943 3944 if (len < 8) 3945 goto out; 3946 3947 /* no HDMI_Video_Present */ 3948 if (!(db[8] & (1 << 5))) 3949 goto out; 3950 3951 /* Latency_Fields_Present */ 3952 if (db[8] & (1 << 7)) 3953 offset += 2; 3954 3955 /* I_Latency_Fields_Present */ 3956 if (db[8] & (1 << 6)) 3957 offset += 2; 3958 3959 /* the declared length is not long enough for the 2 first bytes 3960 * of additional video format capabilities */ 3961 if (len < (8 + offset + 2)) 3962 goto out; 3963 3964 /* 3D_Present */ 3965 offset++; 3966 if (db[8 + offset] & (1 << 7)) { 3967 modes += add_hdmi_mandatory_stereo_modes(connector); 3968 3969 /* 3D_Multi_present */ 3970 multi_present = (db[8 + offset] & 0x60) >> 5; 3971 } 3972 3973 offset++; 3974 vic_len = db[8 + offset] >> 5; 3975 hdmi_3d_len = db[8 + offset] & 0x1f; 3976 3977 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3978 u8 vic; 3979 3980 vic = db[9 + offset + i]; 3981 modes += add_hdmi_mode(connector, vic); 3982 } 3983 offset += 1 + vic_len; 3984 3985 if (multi_present == 1) 3986 multi_len = 2; 3987 else if (multi_present == 2) 3988 multi_len = 4; 3989 else 3990 multi_len = 0; 3991 3992 if (len < (8 + offset + hdmi_3d_len - 1)) 3993 goto out; 3994 3995 if (hdmi_3d_len < multi_len) 3996 goto out; 3997 3998 if (multi_present == 1 || multi_present == 2) { 3999 /* 3D_Structure_ALL */ 4000 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4001 4002 /* check if 3D_MASK is present */ 4003 if (multi_present == 2) 4004 mask = (db[10 + offset] << 8) | db[11 + offset]; 4005 else 4006 mask = 0xffff; 4007 4008 for (i = 0; i < 16; i++) { 4009 if (mask & (1 << i)) 4010 modes += add_3d_struct_modes(connector, 4011 structure_all, 4012 video_db, 4013 video_len, i); 4014 } 4015 } 4016 4017 offset += multi_len; 4018 4019 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4020 int vic_index; 4021 struct drm_display_mode *newmode = NULL; 4022 unsigned int newflag = 0; 4023 bool detail_present; 4024 4025 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4026 4027 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4028 break; 4029 4030 /* 2D_VIC_order_X */ 4031 vic_index = db[8 + offset + i] >> 4; 4032 4033 /* 3D_Structure_X */ 4034 switch (db[8 + offset + i] & 0x0f) { 4035 case 0: 4036 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4037 break; 4038 case 6: 4039 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4040 break; 4041 case 8: 4042 /* 3D_Detail_X */ 4043 if ((db[9 + offset + i] >> 4) == 1) 4044 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4045 break; 4046 } 4047 4048 if (newflag != 0) { 4049 newmode = drm_display_mode_from_vic_index(connector, 4050 video_db, 4051 video_len, 4052 vic_index); 4053 4054 if (newmode) { 4055 newmode->flags |= newflag; 4056 drm_mode_probed_add(connector, newmode); 4057 modes++; 4058 } 4059 } 4060 4061 if (detail_present) 4062 i++; 4063 } 4064 4065 out: 4066 if (modes > 0) 4067 info->has_hdmi_infoframe = true; 4068 return modes; 4069 } 4070 4071 static int 4072 cea_db_payload_len(const u8 *db) 4073 { 4074 return db[0] & 0x1f; 4075 } 4076 4077 static int 4078 cea_db_extended_tag(const u8 *db) 4079 { 4080 return db[1]; 4081 } 4082 4083 static int 4084 cea_db_tag(const u8 *db) 4085 { 4086 return db[0] >> 5; 4087 } 4088 4089 static int 4090 cea_revision(const u8 *cea) 4091 { 4092 /* 4093 * FIXME is this correct for the DispID variant? 4094 * The DispID spec doesn't really specify whether 4095 * this is the revision of the CEA extension or 4096 * the DispID CEA data block. And the only value 4097 * given as an example is 0. 4098 */ 4099 return cea[1]; 4100 } 4101 4102 static int 4103 cea_db_offsets(const u8 *cea, int *start, int *end) 4104 { 4105 /* DisplayID CTA extension blocks and top-level CEA EDID 4106 * block header definitions differ in the following bytes: 4107 * 1) Byte 2 of the header specifies length differently, 4108 * 2) Byte 3 is only present in the CEA top level block. 4109 * 4110 * The different definitions for byte 2 follow. 4111 * 4112 * DisplayID CTA extension block defines byte 2 as: 4113 * Number of payload bytes 4114 * 4115 * CEA EDID block defines byte 2 as: 4116 * Byte number (decimal) within this block where the 18-byte 4117 * DTDs begin. If no non-DTD data is present in this extension 4118 * block, the value should be set to 04h (the byte after next). 4119 * If set to 00h, there are no DTDs present in this block and 4120 * no non-DTD data. 4121 */ 4122 if (cea[0] == DATA_BLOCK_CTA) { 4123 /* 4124 * for_each_displayid_db() has already verified 4125 * that these stay within expected bounds. 4126 */ 4127 *start = 3; 4128 *end = *start + cea[2]; 4129 } else if (cea[0] == CEA_EXT) { 4130 /* Data block offset in CEA extension block */ 4131 *start = 4; 4132 *end = cea[2]; 4133 if (*end == 0) 4134 *end = 127; 4135 if (*end < 4 || *end > 127) 4136 return -ERANGE; 4137 } else { 4138 return -EOPNOTSUPP; 4139 } 4140 4141 return 0; 4142 } 4143 4144 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4145 { 4146 int hdmi_id; 4147 4148 if (cea_db_tag(db) != VENDOR_BLOCK) 4149 return false; 4150 4151 if (cea_db_payload_len(db) < 5) 4152 return false; 4153 4154 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4155 4156 return hdmi_id == HDMI_IEEE_OUI; 4157 } 4158 4159 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4160 { 4161 unsigned int oui; 4162 4163 if (cea_db_tag(db) != VENDOR_BLOCK) 4164 return false; 4165 4166 if (cea_db_payload_len(db) < 7) 4167 return false; 4168 4169 oui = db[3] << 16 | db[2] << 8 | db[1]; 4170 4171 return oui == HDMI_FORUM_IEEE_OUI; 4172 } 4173 4174 static bool cea_db_is_vcdb(const u8 *db) 4175 { 4176 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4177 return false; 4178 4179 if (cea_db_payload_len(db) != 2) 4180 return false; 4181 4182 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4183 return false; 4184 4185 return true; 4186 } 4187 4188 static bool cea_db_is_y420cmdb(const u8 *db) 4189 { 4190 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4191 return false; 4192 4193 if (!cea_db_payload_len(db)) 4194 return false; 4195 4196 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4197 return false; 4198 4199 return true; 4200 } 4201 4202 static bool cea_db_is_y420vdb(const u8 *db) 4203 { 4204 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4205 return false; 4206 4207 if (!cea_db_payload_len(db)) 4208 return false; 4209 4210 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4211 return false; 4212 4213 return true; 4214 } 4215 4216 #define for_each_cea_db(cea, i, start, end) \ 4217 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4218 4219 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4220 const u8 *db) 4221 { 4222 struct drm_display_info *info = &connector->display_info; 4223 struct drm_hdmi_info *hdmi = &info->hdmi; 4224 u8 map_len = cea_db_payload_len(db) - 1; 4225 u8 count; 4226 u64 map = 0; 4227 4228 if (map_len == 0) { 4229 /* All CEA modes support ycbcr420 sampling also.*/ 4230 hdmi->y420_cmdb_map = U64_MAX; 4231 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4232 return; 4233 } 4234 4235 /* 4236 * This map indicates which of the existing CEA block modes 4237 * from VDB can support YCBCR420 output too. So if bit=0 is 4238 * set, first mode from VDB can support YCBCR420 output too. 4239 * We will parse and keep this map, before parsing VDB itself 4240 * to avoid going through the same block again and again. 4241 * 4242 * Spec is not clear about max possible size of this block. 4243 * Clamping max bitmap block size at 8 bytes. Every byte can 4244 * address 8 CEA modes, in this way this map can address 4245 * 8*8 = first 64 SVDs. 4246 */ 4247 if (WARN_ON_ONCE(map_len > 8)) 4248 map_len = 8; 4249 4250 for (count = 0; count < map_len; count++) 4251 map |= (u64)db[2 + count] << (8 * count); 4252 4253 if (map) 4254 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4255 4256 hdmi->y420_cmdb_map = map; 4257 } 4258 4259 static int 4260 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4261 { 4262 const u8 *cea = drm_find_cea_extension(edid); 4263 const u8 *db, *hdmi = NULL, *video = NULL; 4264 u8 dbl, hdmi_len, video_len = 0; 4265 int modes = 0; 4266 4267 if (cea && cea_revision(cea) >= 3) { 4268 int i, start, end; 4269 4270 if (cea_db_offsets(cea, &start, &end)) 4271 return 0; 4272 4273 for_each_cea_db(cea, i, start, end) { 4274 db = &cea[i]; 4275 dbl = cea_db_payload_len(db); 4276 4277 if (cea_db_tag(db) == VIDEO_BLOCK) { 4278 video = db + 1; 4279 video_len = dbl; 4280 modes += do_cea_modes(connector, video, dbl); 4281 } else if (cea_db_is_hdmi_vsdb(db)) { 4282 hdmi = db; 4283 hdmi_len = dbl; 4284 } else if (cea_db_is_y420vdb(db)) { 4285 const u8 *vdb420 = &db[2]; 4286 4287 /* Add 4:2:0(only) modes present in EDID */ 4288 modes += do_y420vdb_modes(connector, 4289 vdb420, 4290 dbl - 1); 4291 } 4292 } 4293 } 4294 4295 /* 4296 * We parse the HDMI VSDB after having added the cea modes as we will 4297 * be patching their flags when the sink supports stereo 3D. 4298 */ 4299 if (hdmi) 4300 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4301 video_len); 4302 4303 return modes; 4304 } 4305 4306 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4307 { 4308 const struct drm_display_mode *cea_mode; 4309 int clock1, clock2, clock; 4310 u8 vic; 4311 const char *type; 4312 4313 /* 4314 * allow 5kHz clock difference either way to account for 4315 * the 10kHz clock resolution limit of detailed timings. 4316 */ 4317 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4318 if (drm_valid_cea_vic(vic)) { 4319 type = "CEA"; 4320 cea_mode = cea_mode_for_vic(vic); 4321 clock1 = cea_mode->clock; 4322 clock2 = cea_mode_alternate_clock(cea_mode); 4323 } else { 4324 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4325 if (drm_valid_hdmi_vic(vic)) { 4326 type = "HDMI"; 4327 cea_mode = &edid_4k_modes[vic]; 4328 clock1 = cea_mode->clock; 4329 clock2 = hdmi_mode_alternate_clock(cea_mode); 4330 } else { 4331 return; 4332 } 4333 } 4334 4335 /* pick whichever is closest */ 4336 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4337 clock = clock1; 4338 else 4339 clock = clock2; 4340 4341 if (mode->clock == clock) 4342 return; 4343 4344 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4345 type, vic, mode->clock, clock); 4346 mode->clock = clock; 4347 } 4348 4349 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4350 { 4351 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4352 return false; 4353 4354 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4355 return false; 4356 4357 if (cea_db_payload_len(db) < 3) 4358 return false; 4359 4360 return true; 4361 } 4362 4363 static uint8_t eotf_supported(const u8 *edid_ext) 4364 { 4365 return edid_ext[2] & 4366 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4367 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4368 BIT(HDMI_EOTF_SMPTE_ST2084) | 4369 BIT(HDMI_EOTF_BT_2100_HLG)); 4370 } 4371 4372 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4373 { 4374 return edid_ext[3] & 4375 BIT(HDMI_STATIC_METADATA_TYPE1); 4376 } 4377 4378 static void 4379 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4380 { 4381 u16 len; 4382 4383 len = cea_db_payload_len(db); 4384 4385 connector->hdr_sink_metadata.hdmi_type1.eotf = 4386 eotf_supported(db); 4387 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4388 hdr_metadata_type(db); 4389 4390 if (len >= 4) 4391 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4392 if (len >= 5) 4393 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4394 if (len >= 6) 4395 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4396 } 4397 4398 static void 4399 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4400 { 4401 u8 len = cea_db_payload_len(db); 4402 4403 if (len >= 6 && (db[6] & (1 << 7))) 4404 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4405 if (len >= 8) { 4406 connector->latency_present[0] = db[8] >> 7; 4407 connector->latency_present[1] = (db[8] >> 6) & 1; 4408 } 4409 if (len >= 9) 4410 connector->video_latency[0] = db[9]; 4411 if (len >= 10) 4412 connector->audio_latency[0] = db[10]; 4413 if (len >= 11) 4414 connector->video_latency[1] = db[11]; 4415 if (len >= 12) 4416 connector->audio_latency[1] = db[12]; 4417 4418 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4419 "video latency %d %d, " 4420 "audio latency %d %d\n", 4421 connector->latency_present[0], 4422 connector->latency_present[1], 4423 connector->video_latency[0], 4424 connector->video_latency[1], 4425 connector->audio_latency[0], 4426 connector->audio_latency[1]); 4427 } 4428 4429 static void 4430 monitor_name(struct detailed_timing *t, void *data) 4431 { 4432 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4433 return; 4434 4435 *(u8 **)data = t->data.other_data.data.str.str; 4436 } 4437 4438 static int get_monitor_name(struct edid *edid, char name[13]) 4439 { 4440 char *edid_name = NULL; 4441 int mnl; 4442 4443 if (!edid || !name) 4444 return 0; 4445 4446 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4447 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4448 if (edid_name[mnl] == 0x0a) 4449 break; 4450 4451 name[mnl] = edid_name[mnl]; 4452 } 4453 4454 return mnl; 4455 } 4456 4457 /** 4458 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4459 * @edid: monitor EDID information 4460 * @name: pointer to a character array to hold the name of the monitor 4461 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4462 * 4463 */ 4464 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4465 { 4466 int name_length; 4467 char buf[13]; 4468 4469 if (bufsize <= 0) 4470 return; 4471 4472 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4473 memcpy(name, buf, name_length); 4474 name[name_length] = '\0'; 4475 } 4476 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4477 4478 static void clear_eld(struct drm_connector *connector) 4479 { 4480 memset(connector->eld, 0, sizeof(connector->eld)); 4481 4482 connector->latency_present[0] = false; 4483 connector->latency_present[1] = false; 4484 connector->video_latency[0] = 0; 4485 connector->audio_latency[0] = 0; 4486 connector->video_latency[1] = 0; 4487 connector->audio_latency[1] = 0; 4488 } 4489 4490 /* 4491 * drm_edid_to_eld - build ELD from EDID 4492 * @connector: connector corresponding to the HDMI/DP sink 4493 * @edid: EDID to parse 4494 * 4495 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4496 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4497 */ 4498 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4499 { 4500 uint8_t *eld = connector->eld; 4501 u8 *cea; 4502 u8 *db; 4503 int total_sad_count = 0; 4504 int mnl; 4505 int dbl; 4506 4507 clear_eld(connector); 4508 4509 if (!edid) 4510 return; 4511 4512 cea = drm_find_cea_extension(edid); 4513 if (!cea) { 4514 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4515 return; 4516 } 4517 4518 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4519 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4520 4521 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4522 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4523 4524 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4525 4526 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4527 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4528 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4529 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4530 4531 if (cea_revision(cea) >= 3) { 4532 int i, start, end; 4533 int sad_count; 4534 4535 if (cea_db_offsets(cea, &start, &end)) { 4536 start = 0; 4537 end = 0; 4538 } 4539 4540 for_each_cea_db(cea, i, start, end) { 4541 db = &cea[i]; 4542 dbl = cea_db_payload_len(db); 4543 4544 switch (cea_db_tag(db)) { 4545 case AUDIO_BLOCK: 4546 /* Audio Data Block, contains SADs */ 4547 sad_count = min(dbl / 3, 15 - total_sad_count); 4548 if (sad_count >= 1) 4549 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4550 &db[1], sad_count * 3); 4551 total_sad_count += sad_count; 4552 break; 4553 case SPEAKER_BLOCK: 4554 /* Speaker Allocation Data Block */ 4555 if (dbl >= 1) 4556 eld[DRM_ELD_SPEAKER] = db[1]; 4557 break; 4558 case VENDOR_BLOCK: 4559 /* HDMI Vendor-Specific Data Block */ 4560 if (cea_db_is_hdmi_vsdb(db)) 4561 drm_parse_hdmi_vsdb_audio(connector, db); 4562 break; 4563 default: 4564 break; 4565 } 4566 } 4567 } 4568 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4569 4570 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4571 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4572 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4573 else 4574 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4575 4576 eld[DRM_ELD_BASELINE_ELD_LEN] = 4577 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4578 4579 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4580 drm_eld_size(eld), total_sad_count); 4581 } 4582 4583 /** 4584 * drm_edid_to_sad - extracts SADs from EDID 4585 * @edid: EDID to parse 4586 * @sads: pointer that will be set to the extracted SADs 4587 * 4588 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4589 * 4590 * Note: The returned pointer needs to be freed using kfree(). 4591 * 4592 * Return: The number of found SADs or negative number on error. 4593 */ 4594 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4595 { 4596 int count = 0; 4597 int i, start, end, dbl; 4598 u8 *cea; 4599 4600 cea = drm_find_cea_extension(edid); 4601 if (!cea) { 4602 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4603 return 0; 4604 } 4605 4606 if (cea_revision(cea) < 3) { 4607 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4608 return 0; 4609 } 4610 4611 if (cea_db_offsets(cea, &start, &end)) { 4612 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4613 return -EPROTO; 4614 } 4615 4616 for_each_cea_db(cea, i, start, end) { 4617 u8 *db = &cea[i]; 4618 4619 if (cea_db_tag(db) == AUDIO_BLOCK) { 4620 int j; 4621 4622 dbl = cea_db_payload_len(db); 4623 4624 count = dbl / 3; /* SAD is 3B */ 4625 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4626 if (!*sads) 4627 return -ENOMEM; 4628 for (j = 0; j < count; j++) { 4629 u8 *sad = &db[1 + j * 3]; 4630 4631 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4632 (*sads)[j].channels = sad[0] & 0x7; 4633 (*sads)[j].freq = sad[1] & 0x7F; 4634 (*sads)[j].byte2 = sad[2]; 4635 } 4636 break; 4637 } 4638 } 4639 4640 return count; 4641 } 4642 EXPORT_SYMBOL(drm_edid_to_sad); 4643 4644 /** 4645 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4646 * @edid: EDID to parse 4647 * @sadb: pointer to the speaker block 4648 * 4649 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4650 * 4651 * Note: The returned pointer needs to be freed using kfree(). 4652 * 4653 * Return: The number of found Speaker Allocation Blocks or negative number on 4654 * error. 4655 */ 4656 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4657 { 4658 int count = 0; 4659 int i, start, end, dbl; 4660 const u8 *cea; 4661 4662 cea = drm_find_cea_extension(edid); 4663 if (!cea) { 4664 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4665 return 0; 4666 } 4667 4668 if (cea_revision(cea) < 3) { 4669 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4670 return 0; 4671 } 4672 4673 if (cea_db_offsets(cea, &start, &end)) { 4674 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4675 return -EPROTO; 4676 } 4677 4678 for_each_cea_db(cea, i, start, end) { 4679 const u8 *db = &cea[i]; 4680 4681 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4682 dbl = cea_db_payload_len(db); 4683 4684 /* Speaker Allocation Data Block */ 4685 if (dbl == 3) { 4686 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4687 if (!*sadb) 4688 return -ENOMEM; 4689 count = dbl; 4690 break; 4691 } 4692 } 4693 } 4694 4695 return count; 4696 } 4697 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4698 4699 /** 4700 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4701 * @connector: connector associated with the HDMI/DP sink 4702 * @mode: the display mode 4703 * 4704 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4705 * the sink doesn't support audio or video. 4706 */ 4707 int drm_av_sync_delay(struct drm_connector *connector, 4708 const struct drm_display_mode *mode) 4709 { 4710 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4711 int a, v; 4712 4713 if (!connector->latency_present[0]) 4714 return 0; 4715 if (!connector->latency_present[1]) 4716 i = 0; 4717 4718 a = connector->audio_latency[i]; 4719 v = connector->video_latency[i]; 4720 4721 /* 4722 * HDMI/DP sink doesn't support audio or video? 4723 */ 4724 if (a == 255 || v == 255) 4725 return 0; 4726 4727 /* 4728 * Convert raw EDID values to millisecond. 4729 * Treat unknown latency as 0ms. 4730 */ 4731 if (a) 4732 a = min(2 * (a - 1), 500); 4733 if (v) 4734 v = min(2 * (v - 1), 500); 4735 4736 return max(v - a, 0); 4737 } 4738 EXPORT_SYMBOL(drm_av_sync_delay); 4739 4740 /** 4741 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4742 * @edid: monitor EDID information 4743 * 4744 * Parse the CEA extension according to CEA-861-B. 4745 * 4746 * Drivers that have added the modes parsed from EDID to drm_display_info 4747 * should use &drm_display_info.is_hdmi instead of calling this function. 4748 * 4749 * Return: True if the monitor is HDMI, false if not or unknown. 4750 */ 4751 bool drm_detect_hdmi_monitor(struct edid *edid) 4752 { 4753 u8 *edid_ext; 4754 int i; 4755 int start_offset, end_offset; 4756 4757 edid_ext = drm_find_cea_extension(edid); 4758 if (!edid_ext) 4759 return false; 4760 4761 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4762 return false; 4763 4764 /* 4765 * Because HDMI identifier is in Vendor Specific Block, 4766 * search it from all data blocks of CEA extension. 4767 */ 4768 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4769 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4770 return true; 4771 } 4772 4773 return false; 4774 } 4775 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4776 4777 /** 4778 * drm_detect_monitor_audio - check monitor audio capability 4779 * @edid: EDID block to scan 4780 * 4781 * Monitor should have CEA extension block. 4782 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4783 * audio' only. If there is any audio extension block and supported 4784 * audio format, assume at least 'basic audio' support, even if 'basic 4785 * audio' is not defined in EDID. 4786 * 4787 * Return: True if the monitor supports audio, false otherwise. 4788 */ 4789 bool drm_detect_monitor_audio(struct edid *edid) 4790 { 4791 u8 *edid_ext; 4792 int i, j; 4793 bool has_audio = false; 4794 int start_offset, end_offset; 4795 4796 edid_ext = drm_find_cea_extension(edid); 4797 if (!edid_ext) 4798 goto end; 4799 4800 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4801 4802 if (has_audio) { 4803 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4804 goto end; 4805 } 4806 4807 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4808 goto end; 4809 4810 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4811 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4812 has_audio = true; 4813 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4814 DRM_DEBUG_KMS("CEA audio format %d\n", 4815 (edid_ext[i + j] >> 3) & 0xf); 4816 goto end; 4817 } 4818 } 4819 end: 4820 return has_audio; 4821 } 4822 EXPORT_SYMBOL(drm_detect_monitor_audio); 4823 4824 4825 /** 4826 * drm_default_rgb_quant_range - default RGB quantization range 4827 * @mode: display mode 4828 * 4829 * Determine the default RGB quantization range for the mode, 4830 * as specified in CEA-861. 4831 * 4832 * Return: The default RGB quantization range for the mode 4833 */ 4834 enum hdmi_quantization_range 4835 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4836 { 4837 /* All CEA modes other than VIC 1 use limited quantization range. */ 4838 return drm_match_cea_mode(mode) > 1 ? 4839 HDMI_QUANTIZATION_RANGE_LIMITED : 4840 HDMI_QUANTIZATION_RANGE_FULL; 4841 } 4842 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4843 4844 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4845 { 4846 struct drm_display_info *info = &connector->display_info; 4847 4848 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4849 4850 if (db[2] & EDID_CEA_VCDB_QS) 4851 info->rgb_quant_range_selectable = true; 4852 } 4853 4854 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4855 const u8 *db) 4856 { 4857 u8 dc_mask; 4858 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4859 4860 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4861 hdmi->y420_dc_modes = dc_mask; 4862 } 4863 4864 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4865 const u8 *hf_vsdb) 4866 { 4867 struct drm_display_info *display = &connector->display_info; 4868 struct drm_hdmi_info *hdmi = &display->hdmi; 4869 4870 display->has_hdmi_infoframe = true; 4871 4872 if (hf_vsdb[6] & 0x80) { 4873 hdmi->scdc.supported = true; 4874 if (hf_vsdb[6] & 0x40) 4875 hdmi->scdc.read_request = true; 4876 } 4877 4878 /* 4879 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4880 * And as per the spec, three factors confirm this: 4881 * * Availability of a HF-VSDB block in EDID (check) 4882 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4883 * * SCDC support available (let's check) 4884 * Lets check it out. 4885 */ 4886 4887 if (hf_vsdb[5]) { 4888 /* max clock is 5000 KHz times block value */ 4889 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4890 struct drm_scdc *scdc = &hdmi->scdc; 4891 4892 if (max_tmds_clock > 340000) { 4893 display->max_tmds_clock = max_tmds_clock; 4894 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4895 display->max_tmds_clock); 4896 } 4897 4898 if (scdc->supported) { 4899 scdc->scrambling.supported = true; 4900 4901 /* Few sinks support scrambling for clocks < 340M */ 4902 if ((hf_vsdb[6] & 0x8)) 4903 scdc->scrambling.low_rates = true; 4904 } 4905 } 4906 4907 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4908 } 4909 4910 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4911 const u8 *hdmi) 4912 { 4913 struct drm_display_info *info = &connector->display_info; 4914 unsigned int dc_bpc = 0; 4915 4916 /* HDMI supports at least 8 bpc */ 4917 info->bpc = 8; 4918 4919 if (cea_db_payload_len(hdmi) < 6) 4920 return; 4921 4922 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4923 dc_bpc = 10; 4924 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4925 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4926 connector->name); 4927 } 4928 4929 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4930 dc_bpc = 12; 4931 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4932 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4933 connector->name); 4934 } 4935 4936 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4937 dc_bpc = 16; 4938 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4939 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4940 connector->name); 4941 } 4942 4943 if (dc_bpc == 0) { 4944 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4945 connector->name); 4946 return; 4947 } 4948 4949 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4950 connector->name, dc_bpc); 4951 info->bpc = dc_bpc; 4952 4953 /* 4954 * Deep color support mandates RGB444 support for all video 4955 * modes and forbids YCRCB422 support for all video modes per 4956 * HDMI 1.3 spec. 4957 */ 4958 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4959 4960 /* YCRCB444 is optional according to spec. */ 4961 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4962 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4963 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4964 connector->name); 4965 } 4966 4967 /* 4968 * Spec says that if any deep color mode is supported at all, 4969 * then deep color 36 bit must be supported. 4970 */ 4971 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4972 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4973 connector->name); 4974 } 4975 } 4976 4977 static void 4978 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4979 { 4980 struct drm_display_info *info = &connector->display_info; 4981 u8 len = cea_db_payload_len(db); 4982 4983 info->is_hdmi = true; 4984 4985 if (len >= 6) 4986 info->dvi_dual = db[6] & 1; 4987 if (len >= 7) 4988 info->max_tmds_clock = db[7] * 5000; 4989 4990 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4991 "max TMDS clock %d kHz\n", 4992 info->dvi_dual, 4993 info->max_tmds_clock); 4994 4995 drm_parse_hdmi_deep_color_info(connector, db); 4996 } 4997 4998 static void drm_parse_cea_ext(struct drm_connector *connector, 4999 const struct edid *edid) 5000 { 5001 struct drm_display_info *info = &connector->display_info; 5002 const u8 *edid_ext; 5003 int i, start, end; 5004 5005 edid_ext = drm_find_cea_extension(edid); 5006 if (!edid_ext) 5007 return; 5008 5009 info->cea_rev = edid_ext[1]; 5010 5011 /* The existence of a CEA block should imply RGB support */ 5012 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5013 if (edid_ext[3] & EDID_CEA_YCRCB444) 5014 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5015 if (edid_ext[3] & EDID_CEA_YCRCB422) 5016 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5017 5018 if (cea_db_offsets(edid_ext, &start, &end)) 5019 return; 5020 5021 for_each_cea_db(edid_ext, i, start, end) { 5022 const u8 *db = &edid_ext[i]; 5023 5024 if (cea_db_is_hdmi_vsdb(db)) 5025 drm_parse_hdmi_vsdb_video(connector, db); 5026 if (cea_db_is_hdmi_forum_vsdb(db)) 5027 drm_parse_hdmi_forum_vsdb(connector, db); 5028 if (cea_db_is_y420cmdb(db)) 5029 drm_parse_y420cmdb_bitmap(connector, db); 5030 if (cea_db_is_vcdb(db)) 5031 drm_parse_vcdb(connector, db); 5032 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5033 drm_parse_hdr_metadata_block(connector, db); 5034 } 5035 } 5036 5037 static 5038 void get_monitor_range(struct detailed_timing *timing, 5039 void *info_monitor_range) 5040 { 5041 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5042 const struct detailed_non_pixel *data = &timing->data.other_data; 5043 const struct detailed_data_monitor_range *range = &data->data.range; 5044 5045 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 5046 return; 5047 5048 /* 5049 * Check for flag range limits only. If flag == 1 then 5050 * no additional timing information provided. 5051 * Default GTF, GTF Secondary curve and CVT are not 5052 * supported 5053 */ 5054 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5055 return; 5056 5057 monitor_range->min_vfreq = range->min_vfreq; 5058 monitor_range->max_vfreq = range->max_vfreq; 5059 } 5060 5061 static 5062 void drm_get_monitor_range(struct drm_connector *connector, 5063 const struct edid *edid) 5064 { 5065 struct drm_display_info *info = &connector->display_info; 5066 5067 if (!version_greater(edid, 1, 1)) 5068 return; 5069 5070 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 5071 &info->monitor_range); 5072 5073 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5074 info->monitor_range.min_vfreq, 5075 info->monitor_range.max_vfreq); 5076 } 5077 5078 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5079 * all of the values which would have been set from EDID 5080 */ 5081 void 5082 drm_reset_display_info(struct drm_connector *connector) 5083 { 5084 struct drm_display_info *info = &connector->display_info; 5085 5086 info->width_mm = 0; 5087 info->height_mm = 0; 5088 5089 info->bpc = 0; 5090 info->color_formats = 0; 5091 info->cea_rev = 0; 5092 info->max_tmds_clock = 0; 5093 info->dvi_dual = false; 5094 info->is_hdmi = false; 5095 info->has_hdmi_infoframe = false; 5096 info->rgb_quant_range_selectable = false; 5097 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5098 5099 info->non_desktop = 0; 5100 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5101 } 5102 5103 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5104 { 5105 struct drm_display_info *info = &connector->display_info; 5106 5107 u32 quirks = edid_get_quirks(edid); 5108 5109 drm_reset_display_info(connector); 5110 5111 info->width_mm = edid->width_cm * 10; 5112 info->height_mm = edid->height_cm * 10; 5113 5114 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5115 5116 drm_get_monitor_range(connector, edid); 5117 5118 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5119 5120 if (edid->revision < 3) 5121 return quirks; 5122 5123 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5124 return quirks; 5125 5126 drm_parse_cea_ext(connector, edid); 5127 5128 /* 5129 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5130 * 5131 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5132 * tells us to assume 8 bpc color depth if the EDID doesn't have 5133 * extensions which tell otherwise. 5134 */ 5135 if (info->bpc == 0 && edid->revision == 3 && 5136 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5137 info->bpc = 8; 5138 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5139 connector->name, info->bpc); 5140 } 5141 5142 /* Only defined for 1.4 with digital displays */ 5143 if (edid->revision < 4) 5144 return quirks; 5145 5146 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5147 case DRM_EDID_DIGITAL_DEPTH_6: 5148 info->bpc = 6; 5149 break; 5150 case DRM_EDID_DIGITAL_DEPTH_8: 5151 info->bpc = 8; 5152 break; 5153 case DRM_EDID_DIGITAL_DEPTH_10: 5154 info->bpc = 10; 5155 break; 5156 case DRM_EDID_DIGITAL_DEPTH_12: 5157 info->bpc = 12; 5158 break; 5159 case DRM_EDID_DIGITAL_DEPTH_14: 5160 info->bpc = 14; 5161 break; 5162 case DRM_EDID_DIGITAL_DEPTH_16: 5163 info->bpc = 16; 5164 break; 5165 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5166 default: 5167 info->bpc = 0; 5168 break; 5169 } 5170 5171 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5172 connector->name, info->bpc); 5173 5174 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5175 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5176 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5177 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5178 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5179 return quirks; 5180 } 5181 5182 static int validate_displayid(u8 *displayid, int length, int idx) 5183 { 5184 int i, dispid_length; 5185 u8 csum = 0; 5186 struct displayid_hdr *base; 5187 5188 base = (struct displayid_hdr *)&displayid[idx]; 5189 5190 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5191 base->rev, base->bytes, base->prod_id, base->ext_count); 5192 5193 /* +1 for DispID checksum */ 5194 dispid_length = sizeof(*base) + base->bytes + 1; 5195 if (dispid_length > length - idx) 5196 return -EINVAL; 5197 5198 for (i = 0; i < dispid_length; i++) 5199 csum += displayid[idx + i]; 5200 if (csum) { 5201 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5202 return -EINVAL; 5203 } 5204 5205 return 0; 5206 } 5207 5208 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5209 struct displayid_detailed_timings_1 *timings) 5210 { 5211 struct drm_display_mode *mode; 5212 unsigned pixel_clock = (timings->pixel_clock[0] | 5213 (timings->pixel_clock[1] << 8) | 5214 (timings->pixel_clock[2] << 16)) + 1; 5215 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5216 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5217 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5218 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5219 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5220 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5221 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5222 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5223 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5224 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5225 5226 mode = drm_mode_create(dev); 5227 if (!mode) 5228 return NULL; 5229 5230 mode->clock = pixel_clock * 10; 5231 mode->hdisplay = hactive; 5232 mode->hsync_start = mode->hdisplay + hsync; 5233 mode->hsync_end = mode->hsync_start + hsync_width; 5234 mode->htotal = mode->hdisplay + hblank; 5235 5236 mode->vdisplay = vactive; 5237 mode->vsync_start = mode->vdisplay + vsync; 5238 mode->vsync_end = mode->vsync_start + vsync_width; 5239 mode->vtotal = mode->vdisplay + vblank; 5240 5241 mode->flags = 0; 5242 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5243 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5244 mode->type = DRM_MODE_TYPE_DRIVER; 5245 5246 if (timings->flags & 0x80) 5247 mode->type |= DRM_MODE_TYPE_PREFERRED; 5248 drm_mode_set_name(mode); 5249 5250 return mode; 5251 } 5252 5253 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5254 struct displayid_block *block) 5255 { 5256 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5257 int i; 5258 int num_timings; 5259 struct drm_display_mode *newmode; 5260 int num_modes = 0; 5261 /* blocks must be multiple of 20 bytes length */ 5262 if (block->num_bytes % 20) 5263 return 0; 5264 5265 num_timings = block->num_bytes / 20; 5266 for (i = 0; i < num_timings; i++) { 5267 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5268 5269 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5270 if (!newmode) 5271 continue; 5272 5273 drm_mode_probed_add(connector, newmode); 5274 num_modes++; 5275 } 5276 return num_modes; 5277 } 5278 5279 static int add_displayid_detailed_modes(struct drm_connector *connector, 5280 struct edid *edid) 5281 { 5282 u8 *displayid; 5283 int length, idx; 5284 struct displayid_block *block; 5285 int num_modes = 0; 5286 int ext_index = 0; 5287 5288 for (;;) { 5289 displayid = drm_find_displayid_extension(edid, &length, &idx, 5290 &ext_index); 5291 if (!displayid) 5292 break; 5293 5294 idx += sizeof(struct displayid_hdr); 5295 for_each_displayid_db(displayid, block, idx, length) { 5296 switch (block->tag) { 5297 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5298 num_modes += add_displayid_detailed_1_modes(connector, block); 5299 break; 5300 } 5301 } 5302 } 5303 5304 return num_modes; 5305 } 5306 5307 /** 5308 * drm_add_edid_modes - add modes from EDID data, if available 5309 * @connector: connector we're probing 5310 * @edid: EDID data 5311 * 5312 * Add the specified modes to the connector's mode list. Also fills out the 5313 * &drm_display_info structure and ELD in @connector with any information which 5314 * can be derived from the edid. 5315 * 5316 * Return: The number of modes added or 0 if we couldn't find any. 5317 */ 5318 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5319 { 5320 int num_modes = 0; 5321 u32 quirks; 5322 5323 if (edid == NULL) { 5324 clear_eld(connector); 5325 return 0; 5326 } 5327 if (!drm_edid_is_valid(edid)) { 5328 clear_eld(connector); 5329 drm_warn(connector->dev, "%s: EDID invalid.\n", 5330 connector->name); 5331 return 0; 5332 } 5333 5334 drm_edid_to_eld(connector, edid); 5335 5336 /* 5337 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5338 * To avoid multiple parsing of same block, lets parse that map 5339 * from sink info, before parsing CEA modes. 5340 */ 5341 quirks = drm_add_display_info(connector, edid); 5342 5343 /* 5344 * EDID spec says modes should be preferred in this order: 5345 * - preferred detailed mode 5346 * - other detailed modes from base block 5347 * - detailed modes from extension blocks 5348 * - CVT 3-byte code modes 5349 * - standard timing codes 5350 * - established timing codes 5351 * - modes inferred from GTF or CVT range information 5352 * 5353 * We get this pretty much right. 5354 * 5355 * XXX order for additional mode types in extension blocks? 5356 */ 5357 num_modes += add_detailed_modes(connector, edid, quirks); 5358 num_modes += add_cvt_modes(connector, edid); 5359 num_modes += add_standard_modes(connector, edid); 5360 num_modes += add_established_modes(connector, edid); 5361 num_modes += add_cea_modes(connector, edid); 5362 num_modes += add_alternate_cea_modes(connector, edid); 5363 num_modes += add_displayid_detailed_modes(connector, edid); 5364 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5365 num_modes += add_inferred_modes(connector, edid); 5366 5367 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5368 edid_fixup_preferred(connector, quirks); 5369 5370 if (quirks & EDID_QUIRK_FORCE_6BPC) 5371 connector->display_info.bpc = 6; 5372 5373 if (quirks & EDID_QUIRK_FORCE_8BPC) 5374 connector->display_info.bpc = 8; 5375 5376 if (quirks & EDID_QUIRK_FORCE_10BPC) 5377 connector->display_info.bpc = 10; 5378 5379 if (quirks & EDID_QUIRK_FORCE_12BPC) 5380 connector->display_info.bpc = 12; 5381 5382 return num_modes; 5383 } 5384 EXPORT_SYMBOL(drm_add_edid_modes); 5385 5386 /** 5387 * drm_add_modes_noedid - add modes for the connectors without EDID 5388 * @connector: connector we're probing 5389 * @hdisplay: the horizontal display limit 5390 * @vdisplay: the vertical display limit 5391 * 5392 * Add the specified modes to the connector's mode list. Only when the 5393 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5394 * 5395 * Return: The number of modes added or 0 if we couldn't find any. 5396 */ 5397 int drm_add_modes_noedid(struct drm_connector *connector, 5398 int hdisplay, int vdisplay) 5399 { 5400 int i, count, num_modes = 0; 5401 struct drm_display_mode *mode; 5402 struct drm_device *dev = connector->dev; 5403 5404 count = ARRAY_SIZE(drm_dmt_modes); 5405 if (hdisplay < 0) 5406 hdisplay = 0; 5407 if (vdisplay < 0) 5408 vdisplay = 0; 5409 5410 for (i = 0; i < count; i++) { 5411 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5412 5413 if (hdisplay && vdisplay) { 5414 /* 5415 * Only when two are valid, they will be used to check 5416 * whether the mode should be added to the mode list of 5417 * the connector. 5418 */ 5419 if (ptr->hdisplay > hdisplay || 5420 ptr->vdisplay > vdisplay) 5421 continue; 5422 } 5423 if (drm_mode_vrefresh(ptr) > 61) 5424 continue; 5425 mode = drm_mode_duplicate(dev, ptr); 5426 if (mode) { 5427 drm_mode_probed_add(connector, mode); 5428 num_modes++; 5429 } 5430 } 5431 return num_modes; 5432 } 5433 EXPORT_SYMBOL(drm_add_modes_noedid); 5434 5435 /** 5436 * drm_set_preferred_mode - Sets the preferred mode of a connector 5437 * @connector: connector whose mode list should be processed 5438 * @hpref: horizontal resolution of preferred mode 5439 * @vpref: vertical resolution of preferred mode 5440 * 5441 * Marks a mode as preferred if it matches the resolution specified by @hpref 5442 * and @vpref. 5443 */ 5444 void drm_set_preferred_mode(struct drm_connector *connector, 5445 int hpref, int vpref) 5446 { 5447 struct drm_display_mode *mode; 5448 5449 list_for_each_entry(mode, &connector->probed_modes, head) { 5450 if (mode->hdisplay == hpref && 5451 mode->vdisplay == vpref) 5452 mode->type |= DRM_MODE_TYPE_PREFERRED; 5453 } 5454 } 5455 EXPORT_SYMBOL(drm_set_preferred_mode); 5456 5457 static bool is_hdmi2_sink(const struct drm_connector *connector) 5458 { 5459 /* 5460 * FIXME: sil-sii8620 doesn't have a connector around when 5461 * we need one, so we have to be prepared for a NULL connector. 5462 */ 5463 if (!connector) 5464 return true; 5465 5466 return connector->display_info.hdmi.scdc.supported || 5467 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5468 } 5469 5470 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5471 { 5472 return sink_eotf & BIT(output_eotf); 5473 } 5474 5475 /** 5476 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5477 * HDR metadata from userspace 5478 * @frame: HDMI DRM infoframe 5479 * @conn_state: Connector state containing HDR metadata 5480 * 5481 * Return: 0 on success or a negative error code on failure. 5482 */ 5483 int 5484 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5485 const struct drm_connector_state *conn_state) 5486 { 5487 struct drm_connector *connector; 5488 struct hdr_output_metadata *hdr_metadata; 5489 int err; 5490 5491 if (!frame || !conn_state) 5492 return -EINVAL; 5493 5494 connector = conn_state->connector; 5495 5496 if (!conn_state->hdr_output_metadata) 5497 return -EINVAL; 5498 5499 hdr_metadata = conn_state->hdr_output_metadata->data; 5500 5501 if (!hdr_metadata || !connector) 5502 return -EINVAL; 5503 5504 /* Sink EOTF is Bit map while infoframe is absolute values */ 5505 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5506 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5507 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5508 return -EINVAL; 5509 } 5510 5511 err = hdmi_drm_infoframe_init(frame); 5512 if (err < 0) 5513 return err; 5514 5515 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5516 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5517 5518 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5519 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5520 BUILD_BUG_ON(sizeof(frame->white_point) != 5521 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5522 5523 memcpy(&frame->display_primaries, 5524 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5525 sizeof(frame->display_primaries)); 5526 5527 memcpy(&frame->white_point, 5528 &hdr_metadata->hdmi_metadata_type1.white_point, 5529 sizeof(frame->white_point)); 5530 5531 frame->max_display_mastering_luminance = 5532 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5533 frame->min_display_mastering_luminance = 5534 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5535 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5536 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5537 5538 return 0; 5539 } 5540 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5541 5542 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5543 const struct drm_display_mode *mode) 5544 { 5545 bool has_hdmi_infoframe = connector ? 5546 connector->display_info.has_hdmi_infoframe : false; 5547 5548 if (!has_hdmi_infoframe) 5549 return 0; 5550 5551 /* No HDMI VIC when signalling 3D video format */ 5552 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5553 return 0; 5554 5555 return drm_match_hdmi_mode(mode); 5556 } 5557 5558 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5559 const struct drm_display_mode *mode) 5560 { 5561 u8 vic; 5562 5563 /* 5564 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5565 * we should send its VIC in vendor infoframes, else send the 5566 * VIC in AVI infoframes. Lets check if this mode is present in 5567 * HDMI 1.4b 4K modes 5568 */ 5569 if (drm_mode_hdmi_vic(connector, mode)) 5570 return 0; 5571 5572 vic = drm_match_cea_mode(mode); 5573 5574 /* 5575 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5576 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5577 * have to make sure we dont break HDMI 1.4 sinks. 5578 */ 5579 if (!is_hdmi2_sink(connector) && vic > 64) 5580 return 0; 5581 5582 return vic; 5583 } 5584 5585 /** 5586 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5587 * data from a DRM display mode 5588 * @frame: HDMI AVI infoframe 5589 * @connector: the connector 5590 * @mode: DRM display mode 5591 * 5592 * Return: 0 on success or a negative error code on failure. 5593 */ 5594 int 5595 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5596 const struct drm_connector *connector, 5597 const struct drm_display_mode *mode) 5598 { 5599 enum hdmi_picture_aspect picture_aspect; 5600 u8 vic, hdmi_vic; 5601 5602 if (!frame || !mode) 5603 return -EINVAL; 5604 5605 hdmi_avi_infoframe_init(frame); 5606 5607 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5608 frame->pixel_repeat = 1; 5609 5610 vic = drm_mode_cea_vic(connector, mode); 5611 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5612 5613 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5614 5615 /* 5616 * As some drivers don't support atomic, we can't use connector state. 5617 * So just initialize the frame with default values, just the same way 5618 * as it's done with other properties here. 5619 */ 5620 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5621 frame->itc = 0; 5622 5623 /* 5624 * Populate picture aspect ratio from either 5625 * user input (if specified) or from the CEA/HDMI mode lists. 5626 */ 5627 picture_aspect = mode->picture_aspect_ratio; 5628 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5629 if (vic) 5630 picture_aspect = drm_get_cea_aspect_ratio(vic); 5631 else if (hdmi_vic) 5632 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5633 } 5634 5635 /* 5636 * The infoframe can't convey anything but none, 4:3 5637 * and 16:9, so if the user has asked for anything else 5638 * we can only satisfy it by specifying the right VIC. 5639 */ 5640 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5641 if (vic) { 5642 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5643 return -EINVAL; 5644 } else if (hdmi_vic) { 5645 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5646 return -EINVAL; 5647 } else { 5648 return -EINVAL; 5649 } 5650 5651 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5652 } 5653 5654 frame->video_code = vic; 5655 frame->picture_aspect = picture_aspect; 5656 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5657 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5658 5659 return 0; 5660 } 5661 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5662 5663 /* HDMI Colorspace Spec Definitions */ 5664 #define FULL_COLORIMETRY_MASK 0x1FF 5665 #define NORMAL_COLORIMETRY_MASK 0x3 5666 #define EXTENDED_COLORIMETRY_MASK 0x7 5667 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5668 5669 #define C(x) ((x) << 0) 5670 #define EC(x) ((x) << 2) 5671 #define ACE(x) ((x) << 5) 5672 5673 #define HDMI_COLORIMETRY_NO_DATA 0x0 5674 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5675 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5676 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5677 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5678 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5679 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5680 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5681 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5682 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5683 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5684 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5685 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5686 5687 static const u32 hdmi_colorimetry_val[] = { 5688 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5689 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5690 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5691 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5692 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5693 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5694 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5695 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5696 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5697 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5698 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5699 }; 5700 5701 #undef C 5702 #undef EC 5703 #undef ACE 5704 5705 /** 5706 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5707 * colorspace information 5708 * @frame: HDMI AVI infoframe 5709 * @conn_state: connector state 5710 */ 5711 void 5712 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5713 const struct drm_connector_state *conn_state) 5714 { 5715 u32 colorimetry_val; 5716 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5717 5718 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5719 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5720 else 5721 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5722 5723 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5724 /* 5725 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5726 * structure and extend it in drivers/video/hdmi 5727 */ 5728 frame->extended_colorimetry = (colorimetry_val >> 2) & 5729 EXTENDED_COLORIMETRY_MASK; 5730 } 5731 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5732 5733 /** 5734 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5735 * quantization range information 5736 * @frame: HDMI AVI infoframe 5737 * @connector: the connector 5738 * @mode: DRM display mode 5739 * @rgb_quant_range: RGB quantization range (Q) 5740 */ 5741 void 5742 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5743 const struct drm_connector *connector, 5744 const struct drm_display_mode *mode, 5745 enum hdmi_quantization_range rgb_quant_range) 5746 { 5747 const struct drm_display_info *info = &connector->display_info; 5748 5749 /* 5750 * CEA-861: 5751 * "A Source shall not send a non-zero Q value that does not correspond 5752 * to the default RGB Quantization Range for the transmitted Picture 5753 * unless the Sink indicates support for the Q bit in a Video 5754 * Capabilities Data Block." 5755 * 5756 * HDMI 2.0 recommends sending non-zero Q when it does match the 5757 * default RGB quantization range for the mode, even when QS=0. 5758 */ 5759 if (info->rgb_quant_range_selectable || 5760 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5761 frame->quantization_range = rgb_quant_range; 5762 else 5763 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5764 5765 /* 5766 * CEA-861-F: 5767 * "When transmitting any RGB colorimetry, the Source should set the 5768 * YQ-field to match the RGB Quantization Range being transmitted 5769 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5770 * set YQ=1) and the Sink shall ignore the YQ-field." 5771 * 5772 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5773 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5774 * good way to tell which version of CEA-861 the sink supports, so 5775 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5776 * on on CEA-861-F. 5777 */ 5778 if (!is_hdmi2_sink(connector) || 5779 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5780 frame->ycc_quantization_range = 5781 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5782 else 5783 frame->ycc_quantization_range = 5784 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5785 } 5786 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5787 5788 /** 5789 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5790 * bar information 5791 * @frame: HDMI AVI infoframe 5792 * @conn_state: connector state 5793 */ 5794 void 5795 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5796 const struct drm_connector_state *conn_state) 5797 { 5798 frame->right_bar = conn_state->tv.margins.right; 5799 frame->left_bar = conn_state->tv.margins.left; 5800 frame->top_bar = conn_state->tv.margins.top; 5801 frame->bottom_bar = conn_state->tv.margins.bottom; 5802 } 5803 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5804 5805 static enum hdmi_3d_structure 5806 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5807 { 5808 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5809 5810 switch (layout) { 5811 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5812 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5813 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5814 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5815 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5816 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5817 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5818 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5819 case DRM_MODE_FLAG_3D_L_DEPTH: 5820 return HDMI_3D_STRUCTURE_L_DEPTH; 5821 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5822 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5823 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5824 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5825 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5826 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5827 default: 5828 return HDMI_3D_STRUCTURE_INVALID; 5829 } 5830 } 5831 5832 /** 5833 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5834 * data from a DRM display mode 5835 * @frame: HDMI vendor infoframe 5836 * @connector: the connector 5837 * @mode: DRM display mode 5838 * 5839 * Note that there's is a need to send HDMI vendor infoframes only when using a 5840 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5841 * function will return -EINVAL, error that can be safely ignored. 5842 * 5843 * Return: 0 on success or a negative error code on failure. 5844 */ 5845 int 5846 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5847 const struct drm_connector *connector, 5848 const struct drm_display_mode *mode) 5849 { 5850 /* 5851 * FIXME: sil-sii8620 doesn't have a connector around when 5852 * we need one, so we have to be prepared for a NULL connector. 5853 */ 5854 bool has_hdmi_infoframe = connector ? 5855 connector->display_info.has_hdmi_infoframe : false; 5856 int err; 5857 5858 if (!frame || !mode) 5859 return -EINVAL; 5860 5861 if (!has_hdmi_infoframe) 5862 return -EINVAL; 5863 5864 err = hdmi_vendor_infoframe_init(frame); 5865 if (err < 0) 5866 return err; 5867 5868 /* 5869 * Even if it's not absolutely necessary to send the infoframe 5870 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5871 * know that the sink can handle it. This is based on a 5872 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5873 * have trouble realizing that they shuld switch from 3D to 2D 5874 * mode if the source simply stops sending the infoframe when 5875 * it wants to switch from 3D to 2D. 5876 */ 5877 frame->vic = drm_mode_hdmi_vic(connector, mode); 5878 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5879 5880 return 0; 5881 } 5882 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5883 5884 static void drm_parse_tiled_block(struct drm_connector *connector, 5885 const struct displayid_block *block) 5886 { 5887 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5888 u16 w, h; 5889 u8 tile_v_loc, tile_h_loc; 5890 u8 num_v_tile, num_h_tile; 5891 struct drm_tile_group *tg; 5892 5893 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5894 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5895 5896 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5897 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5898 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5899 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5900 5901 connector->has_tile = true; 5902 if (tile->tile_cap & 0x80) 5903 connector->tile_is_single_monitor = true; 5904 5905 connector->num_h_tile = num_h_tile + 1; 5906 connector->num_v_tile = num_v_tile + 1; 5907 connector->tile_h_loc = tile_h_loc; 5908 connector->tile_v_loc = tile_v_loc; 5909 connector->tile_h_size = w + 1; 5910 connector->tile_v_size = h + 1; 5911 5912 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5913 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5914 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5915 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5916 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5917 5918 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5919 if (!tg) 5920 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5921 if (!tg) 5922 return; 5923 5924 if (connector->tile_group != tg) { 5925 /* if we haven't got a pointer, 5926 take the reference, drop ref to old tile group */ 5927 if (connector->tile_group) 5928 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5929 connector->tile_group = tg; 5930 } else { 5931 /* if same tile group, then release the ref we just took. */ 5932 drm_mode_put_tile_group(connector->dev, tg); 5933 } 5934 } 5935 5936 static void drm_displayid_parse_tiled(struct drm_connector *connector, 5937 const u8 *displayid, int length, int idx) 5938 { 5939 const struct displayid_block *block; 5940 5941 idx += sizeof(struct displayid_hdr); 5942 for_each_displayid_db(displayid, block, idx, length) { 5943 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5944 block->tag, block->rev, block->num_bytes); 5945 5946 switch (block->tag) { 5947 case DATA_BLOCK_TILED_DISPLAY: 5948 drm_parse_tiled_block(connector, block); 5949 break; 5950 default: 5951 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5952 break; 5953 } 5954 } 5955 } 5956 5957 void drm_update_tile_info(struct drm_connector *connector, 5958 const struct edid *edid) 5959 { 5960 const void *displayid = NULL; 5961 int ext_index = 0; 5962 int length, idx; 5963 5964 connector->has_tile = false; 5965 for (;;) { 5966 displayid = drm_find_displayid_extension(edid, &length, &idx, 5967 &ext_index); 5968 if (!displayid) 5969 break; 5970 5971 drm_displayid_parse_tiled(connector, displayid, length, idx); 5972 } 5973 5974 if (!connector->has_tile && connector->tile_group) { 5975 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5976 connector->tile_group = NULL; 5977 } 5978 } 5979