1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 199 /* Windows Mixed Reality Headsets */ 200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 208 209 /* Sony PlayStation VR Headset */ 210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 211 212 /* Sensics VR Headsets */ 213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 214 215 /* OSVR HDK and HDK2 VR Headsets */ 216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 217 }; 218 219 /* 220 * Autogenerated from the DMT spec. 221 * This table is copied from xfree86/modes/xf86EdidModes.c. 222 */ 223 static const struct drm_display_mode drm_dmt_modes[] = { 224 /* 0x01 - 640x350@85Hz */ 225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 226 736, 832, 0, 350, 382, 385, 445, 0, 227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 228 /* 0x02 - 640x400@85Hz */ 229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 230 736, 832, 0, 400, 401, 404, 445, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 232 /* 0x03 - 720x400@85Hz */ 233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 234 828, 936, 0, 400, 401, 404, 446, 0, 235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 236 /* 0x04 - 640x480@60Hz */ 237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 238 752, 800, 0, 480, 490, 492, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 240 /* 0x05 - 640x480@72Hz */ 241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 242 704, 832, 0, 480, 489, 492, 520, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x06 - 640x480@75Hz */ 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 246 720, 840, 0, 480, 481, 484, 500, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x07 - 640x480@85Hz */ 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 250 752, 832, 0, 480, 481, 484, 509, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 252 /* 0x08 - 800x600@56Hz */ 253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 254 896, 1024, 0, 600, 601, 603, 625, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x09 - 800x600@60Hz */ 257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 258 968, 1056, 0, 600, 601, 605, 628, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x0a - 800x600@72Hz */ 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 262 976, 1040, 0, 600, 637, 643, 666, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x0b - 800x600@75Hz */ 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 266 896, 1056, 0, 600, 601, 604, 625, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x0c - 800x600@85Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 270 896, 1048, 0, 600, 601, 604, 631, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x0d - 800x600@120Hz RB */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 274 880, 960, 0, 600, 603, 607, 636, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x0e - 848x480@60Hz */ 277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 278 976, 1088, 0, 480, 486, 494, 517, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0f - 1024x768@43Hz, interlace */ 281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 282 1208, 1264, 0, 768, 768, 776, 817, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 284 DRM_MODE_FLAG_INTERLACE) }, 285 /* 0x10 - 1024x768@60Hz */ 286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 287 1184, 1344, 0, 768, 771, 777, 806, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 0x11 - 1024x768@70Hz */ 290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 291 1184, 1328, 0, 768, 771, 777, 806, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x12 - 1024x768@75Hz */ 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 295 1136, 1312, 0, 768, 769, 772, 800, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x13 - 1024x768@85Hz */ 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 299 1168, 1376, 0, 768, 769, 772, 808, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x14 - 1024x768@120Hz RB */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 303 1104, 1184, 0, 768, 771, 775, 813, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 305 /* 0x15 - 1152x864@75Hz */ 306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 307 1344, 1600, 0, 864, 865, 868, 900, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x55 - 1280x720@60Hz */ 310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 311 1430, 1650, 0, 720, 725, 730, 750, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x16 - 1280x768@60Hz RB */ 314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 315 1360, 1440, 0, 768, 771, 778, 790, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x17 - 1280x768@60Hz */ 318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 319 1472, 1664, 0, 768, 771, 778, 798, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x18 - 1280x768@75Hz */ 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 323 1488, 1696, 0, 768, 771, 778, 805, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x19 - 1280x768@85Hz */ 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 327 1496, 1712, 0, 768, 771, 778, 809, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x1a - 1280x768@120Hz RB */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 331 1360, 1440, 0, 768, 771, 778, 813, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 0x1b - 1280x800@60Hz RB */ 334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 335 1360, 1440, 0, 800, 803, 809, 823, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x1c - 1280x800@60Hz */ 338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 339 1480, 1680, 0, 800, 803, 809, 831, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x1d - 1280x800@75Hz */ 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 343 1488, 1696, 0, 800, 803, 809, 838, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x1e - 1280x800@85Hz */ 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 347 1496, 1712, 0, 800, 803, 809, 843, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1f - 1280x800@120Hz RB */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 351 1360, 1440, 0, 800, 803, 809, 847, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x20 - 1280x960@60Hz */ 354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 355 1488, 1800, 0, 960, 961, 964, 1000, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x21 - 1280x960@85Hz */ 358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 359 1504, 1728, 0, 960, 961, 964, 1011, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x22 - 1280x960@120Hz RB */ 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 363 1360, 1440, 0, 960, 963, 967, 1017, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x23 - 1280x1024@60Hz */ 366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x24 - 1280x1024@75Hz */ 370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x25 - 1280x1024@85Hz */ 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x26 - 1280x1024@120Hz RB */ 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 381 /* 0x27 - 1360x768@60Hz */ 382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 383 1536, 1792, 0, 768, 771, 777, 795, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x28 - 1360x768@120Hz RB */ 386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 387 1440, 1520, 0, 768, 771, 776, 813, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 389 /* 0x51 - 1366x768@60Hz */ 390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 391 1579, 1792, 0, 768, 771, 774, 798, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x56 - 1366x768@60Hz */ 394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 395 1436, 1500, 0, 768, 769, 772, 800, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x29 - 1400x1050@60Hz RB */ 398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x2a - 1400x1050@60Hz */ 402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x2b - 1400x1050@75Hz */ 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x2c - 1400x1050@85Hz */ 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x2d - 1400x1050@120Hz RB */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 0x2e - 1440x900@60Hz RB */ 418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 419 1520, 1600, 0, 900, 903, 909, 926, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2f - 1440x900@60Hz */ 422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 423 1672, 1904, 0, 900, 903, 909, 934, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x30 - 1440x900@75Hz */ 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 427 1688, 1936, 0, 900, 903, 909, 942, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x31 - 1440x900@85Hz */ 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 431 1696, 1952, 0, 900, 903, 909, 948, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x32 - 1440x900@120Hz RB */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 435 1520, 1600, 0, 900, 903, 909, 953, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x53 - 1600x900@60Hz */ 438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 439 1704, 1800, 0, 900, 901, 904, 1000, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x33 - 1600x1200@60Hz */ 442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x34 - 1600x1200@65Hz */ 446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x35 - 1600x1200@70Hz */ 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x36 - 1600x1200@75Hz */ 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x37 - 1600x1200@85Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x38 - 1600x1200@120Hz RB */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 465 /* 0x39 - 1680x1050@60Hz RB */ 466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x3a - 1680x1050@60Hz */ 470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x3b - 1680x1050@75Hz */ 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x3c - 1680x1050@85Hz */ 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x3d - 1680x1050@120Hz RB */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x3e - 1792x1344@60Hz */ 486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x3f - 1792x1344@75Hz */ 490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x40 - 1792x1344@120Hz RB */ 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x41 - 1856x1392@60Hz */ 498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x42 - 1856x1392@75Hz */ 502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x43 - 1856x1392@120Hz RB */ 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 509 /* 0x52 - 1920x1080@60Hz */ 510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 /* 0x44 - 1920x1200@60Hz RB */ 514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x45 - 1920x1200@60Hz */ 518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x46 - 1920x1200@75Hz */ 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x47 - 1920x1200@85Hz */ 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 529 /* 0x48 - 1920x1200@120Hz RB */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x49 - 1920x1440@60Hz */ 534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x4a - 1920x1440@75Hz */ 538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x4b - 1920x1440@120Hz RB */ 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 545 /* 0x54 - 2048x1152@60Hz */ 546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x4c - 2560x1600@60Hz RB */ 550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x4d - 2560x1600@60Hz */ 554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4e - 2560x1600@75Hz */ 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4f - 2560x1600@85Hz */ 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x50 - 2560x1600@120Hz RB */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 569 /* 0x57 - 4096x2160@60Hz RB */ 570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x58 - 4096x2160@59.94Hz RB */ 574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 }; 578 579 /* 580 * These more or less come from the DMT spec. The 720x400 modes are 581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 584 * mode. 585 * 586 * The DMT modes have been fact-checked; the rest are mild guesses. 587 */ 588 static const struct drm_display_mode edid_est_modes[] = { 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 590 968, 1056, 0, 600, 601, 605, 628, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 593 896, 1024, 0, 600, 601, 603, 625, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 596 720, 840, 0, 480, 481, 484, 500, 0, 597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 599 704, 832, 0, 480, 489, 492, 520, 0, 600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 602 768, 864, 0, 480, 483, 486, 525, 0, 603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 605 752, 800, 0, 480, 490, 492, 525, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 608 846, 900, 0, 400, 421, 423, 449, 0, 609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 611 846, 900, 0, 400, 412, 414, 449, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 617 1136, 1312, 0, 768, 769, 772, 800, 0, 618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 620 1184, 1328, 0, 768, 771, 777, 806, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 623 1184, 1344, 0, 768, 771, 777, 806, 0, 624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 626 1208, 1264, 0, 768, 768, 776, 817, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 629 928, 1152, 0, 624, 625, 628, 667, 0, 630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 632 896, 1056, 0, 600, 601, 604, 625, 0, 633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 635 976, 1040, 0, 600, 637, 643, 666, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 638 1344, 1600, 0, 864, 865, 868, 900, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 640 }; 641 642 struct minimode { 643 short w; 644 short h; 645 short r; 646 short rb; 647 }; 648 649 static const struct minimode est3_modes[] = { 650 /* byte 6 */ 651 { 640, 350, 85, 0 }, 652 { 640, 400, 85, 0 }, 653 { 720, 400, 85, 0 }, 654 { 640, 480, 85, 0 }, 655 { 848, 480, 60, 0 }, 656 { 800, 600, 85, 0 }, 657 { 1024, 768, 85, 0 }, 658 { 1152, 864, 75, 0 }, 659 /* byte 7 */ 660 { 1280, 768, 60, 1 }, 661 { 1280, 768, 60, 0 }, 662 { 1280, 768, 75, 0 }, 663 { 1280, 768, 85, 0 }, 664 { 1280, 960, 60, 0 }, 665 { 1280, 960, 85, 0 }, 666 { 1280, 1024, 60, 0 }, 667 { 1280, 1024, 85, 0 }, 668 /* byte 8 */ 669 { 1360, 768, 60, 0 }, 670 { 1440, 900, 60, 1 }, 671 { 1440, 900, 60, 0 }, 672 { 1440, 900, 75, 0 }, 673 { 1440, 900, 85, 0 }, 674 { 1400, 1050, 60, 1 }, 675 { 1400, 1050, 60, 0 }, 676 { 1400, 1050, 75, 0 }, 677 /* byte 9 */ 678 { 1400, 1050, 85, 0 }, 679 { 1680, 1050, 60, 1 }, 680 { 1680, 1050, 60, 0 }, 681 { 1680, 1050, 75, 0 }, 682 { 1680, 1050, 85, 0 }, 683 { 1600, 1200, 60, 0 }, 684 { 1600, 1200, 65, 0 }, 685 { 1600, 1200, 70, 0 }, 686 /* byte 10 */ 687 { 1600, 1200, 75, 0 }, 688 { 1600, 1200, 85, 0 }, 689 { 1792, 1344, 60, 0 }, 690 { 1792, 1344, 75, 0 }, 691 { 1856, 1392, 60, 0 }, 692 { 1856, 1392, 75, 0 }, 693 { 1920, 1200, 60, 1 }, 694 { 1920, 1200, 60, 0 }, 695 /* byte 11 */ 696 { 1920, 1200, 75, 0 }, 697 { 1920, 1200, 85, 0 }, 698 { 1920, 1440, 60, 0 }, 699 { 1920, 1440, 75, 0 }, 700 }; 701 702 static const struct minimode extra_modes[] = { 703 { 1024, 576, 60, 0 }, 704 { 1366, 768, 60, 0 }, 705 { 1600, 900, 60, 0 }, 706 { 1680, 945, 60, 0 }, 707 { 1920, 1080, 60, 0 }, 708 { 2048, 1152, 60, 0 }, 709 { 2048, 1536, 60, 0 }, 710 }; 711 712 /* 713 * From CEA/CTA-861 spec. 714 * 715 * Do not access directly, instead always use cea_mode_for_vic(). 716 */ 717 static const struct drm_display_mode edid_cea_modes_1[] = { 718 /* 1 - 640x480@60Hz 4:3 */ 719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 720 752, 800, 0, 480, 490, 492, 525, 0, 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 722 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 723 /* 2 - 720x480@60Hz 4:3 */ 724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 725 798, 858, 0, 480, 489, 495, 525, 0, 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 727 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 3 - 720x480@60Hz 16:9 */ 729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 730 798, 858, 0, 480, 489, 495, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 732 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 733 /* 4 - 1280x720@60Hz 16:9 */ 734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 735 1430, 1650, 0, 720, 725, 730, 750, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 738 /* 5 - 1920x1080i@60Hz 16:9 */ 739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 742 DRM_MODE_FLAG_INTERLACE), 743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 6 - 720(1440)x480i@60Hz 4:3 */ 745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 746 801, 858, 0, 480, 488, 494, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 750 /* 7 - 720(1440)x480i@60Hz 16:9 */ 751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 752 801, 858, 0, 480, 488, 494, 525, 0, 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 8 - 720(1440)x240@60Hz 4:3 */ 757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 758 801, 858, 0, 240, 244, 247, 262, 0, 759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 760 DRM_MODE_FLAG_DBLCLK), 761 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 762 /* 9 - 720(1440)x240@60Hz 16:9 */ 763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 764 801, 858, 0, 240, 244, 247, 262, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 766 DRM_MODE_FLAG_DBLCLK), 767 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 768 /* 10 - 2880x480i@60Hz 4:3 */ 769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 770 3204, 3432, 0, 480, 488, 494, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 772 DRM_MODE_FLAG_INTERLACE), 773 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 774 /* 11 - 2880x480i@60Hz 16:9 */ 775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 776 3204, 3432, 0, 480, 488, 494, 525, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 778 DRM_MODE_FLAG_INTERLACE), 779 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 12 - 2880x240@60Hz 4:3 */ 781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 782 3204, 3432, 0, 240, 244, 247, 262, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 785 /* 13 - 2880x240@60Hz 16:9 */ 786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 787 3204, 3432, 0, 240, 244, 247, 262, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 789 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 14 - 1440x480@60Hz 4:3 */ 791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 792 1596, 1716, 0, 480, 489, 495, 525, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 794 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 15 - 1440x480@60Hz 16:9 */ 796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 797 1596, 1716, 0, 480, 489, 495, 525, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 16 - 1920x1080@60Hz 16:9 */ 801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 805 /* 17 - 720x576@50Hz 4:3 */ 806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 807 796, 864, 0, 576, 581, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 18 - 720x576@50Hz 16:9 */ 811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 812 796, 864, 0, 576, 581, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 19 - 1280x720@50Hz 16:9 */ 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 817 1760, 1980, 0, 720, 725, 730, 750, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 20 - 1920x1080i@50Hz 16:9 */ 821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 824 DRM_MODE_FLAG_INTERLACE), 825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 21 - 720(1440)x576i@50Hz 4:3 */ 827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 828 795, 864, 0, 576, 580, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 832 /* 22 - 720(1440)x576i@50Hz 16:9 */ 833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 834 795, 864, 0, 576, 580, 586, 625, 0, 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 23 - 720(1440)x288@50Hz 4:3 */ 839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 840 795, 864, 0, 288, 290, 293, 312, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 842 DRM_MODE_FLAG_DBLCLK), 843 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 24 - 720(1440)x288@50Hz 16:9 */ 845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 846 795, 864, 0, 288, 290, 293, 312, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 848 DRM_MODE_FLAG_DBLCLK), 849 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 850 /* 25 - 2880x576i@50Hz 4:3 */ 851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 852 3180, 3456, 0, 576, 580, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 854 DRM_MODE_FLAG_INTERLACE), 855 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 856 /* 26 - 2880x576i@50Hz 16:9 */ 857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 858 3180, 3456, 0, 576, 580, 586, 625, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 27 - 2880x288@50Hz 4:3 */ 863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 864 3180, 3456, 0, 288, 290, 293, 312, 0, 865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 867 /* 28 - 2880x288@50Hz 16:9 */ 868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 869 3180, 3456, 0, 288, 290, 293, 312, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 871 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 872 /* 29 - 1440x576@50Hz 4:3 */ 873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 874 1592, 1728, 0, 576, 581, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 877 /* 30 - 1440x576@50Hz 16:9 */ 878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 879 1592, 1728, 0, 576, 581, 586, 625, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 31 - 1920x1080@50Hz 16:9 */ 883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 887 /* 32 - 1920x1080@24Hz 16:9 */ 888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 33 - 1920x1080@25Hz 16:9 */ 893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 34 - 1920x1080@30Hz 16:9 */ 898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 35 - 2880x480@60Hz 4:3 */ 903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 904 3192, 3432, 0, 480, 489, 495, 525, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 907 /* 36 - 2880x480@60Hz 16:9 */ 908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 909 3192, 3432, 0, 480, 489, 495, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 37 - 2880x576@50Hz 4:3 */ 913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 914 3184, 3456, 0, 576, 581, 586, 625, 0, 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 917 /* 38 - 2880x576@50Hz 16:9 */ 918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 919 3184, 3456, 0, 576, 581, 586, 625, 0, 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 39 - 1920x1080i@50Hz 16:9 */ 923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 926 DRM_MODE_FLAG_INTERLACE), 927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 40 - 1920x1080i@100Hz 16:9 */ 929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 932 DRM_MODE_FLAG_INTERLACE), 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 41 - 1280x720@100Hz 16:9 */ 935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 936 1760, 1980, 0, 720, 725, 730, 750, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 939 /* 42 - 720x576@100Hz 4:3 */ 940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 941 796, 864, 0, 576, 581, 586, 625, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 944 /* 43 - 720x576@100Hz 16:9 */ 945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 946 796, 864, 0, 576, 581, 586, 625, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 949 /* 44 - 720(1440)x576i@100Hz 4:3 */ 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 951 795, 864, 0, 576, 580, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 955 /* 45 - 720(1440)x576i@100Hz 16:9 */ 956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 957 795, 864, 0, 576, 580, 586, 625, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 961 /* 46 - 1920x1080i@120Hz 16:9 */ 962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 965 DRM_MODE_FLAG_INTERLACE), 966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 967 /* 47 - 1280x720@120Hz 16:9 */ 968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 969 1430, 1650, 0, 720, 725, 730, 750, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 972 /* 48 - 720x480@120Hz 4:3 */ 973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 974 798, 858, 0, 480, 489, 495, 525, 0, 975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 977 /* 49 - 720x480@120Hz 16:9 */ 978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 979 798, 858, 0, 480, 489, 495, 525, 0, 980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 981 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 50 - 720(1440)x480i@120Hz 4:3 */ 983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 984 801, 858, 0, 480, 488, 494, 525, 0, 985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 988 /* 51 - 720(1440)x480i@120Hz 16:9 */ 989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 990 801, 858, 0, 480, 488, 494, 525, 0, 991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 52 - 720x576@200Hz 4:3 */ 995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 996 796, 864, 0, 576, 581, 586, 625, 0, 997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 999 /* 53 - 720x576@200Hz 16:9 */ 1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1001 796, 864, 0, 576, 581, 586, 625, 0, 1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1006 795, 864, 0, 576, 580, 586, 625, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1010 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1012 795, 864, 0, 576, 580, 586, 625, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1016 /* 56 - 720x480@240Hz 4:3 */ 1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1018 798, 858, 0, 480, 489, 495, 525, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1021 /* 57 - 720x480@240Hz 16:9 */ 1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1023 798, 858, 0, 480, 489, 495, 525, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1028 801, 858, 0, 480, 488, 494, 525, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1031 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1032 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1034 801, 858, 0, 480, 488, 494, 525, 0, 1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1038 /* 60 - 1280x720@24Hz 16:9 */ 1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1040 3080, 3300, 0, 720, 725, 730, 750, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1043 /* 61 - 1280x720@25Hz 16:9 */ 1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1045 3740, 3960, 0, 720, 725, 730, 750, 0, 1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1048 /* 62 - 1280x720@30Hz 16:9 */ 1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1050 3080, 3300, 0, 720, 725, 730, 750, 0, 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1053 /* 63 - 1920x1080@120Hz 16:9 */ 1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 64 - 1920x1080@100Hz 16:9 */ 1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 65 - 1280x720@24Hz 64:27 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1065 3080, 3300, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1068 /* 66 - 1280x720@25Hz 64:27 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1070 3740, 3960, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1073 /* 67 - 1280x720@30Hz 64:27 */ 1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1075 3080, 3300, 0, 720, 725, 730, 750, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1078 /* 68 - 1280x720@50Hz 64:27 */ 1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1080 1760, 1980, 0, 720, 725, 730, 750, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1083 /* 69 - 1280x720@60Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 70 - 1280x720@100Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1090 1760, 1980, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 71 - 1280x720@120Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1095 1430, 1650, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 72 - 1920x1080@24Hz 64:27 */ 1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 73 - 1920x1080@25Hz 64:27 */ 1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 74 - 1920x1080@30Hz 64:27 */ 1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 75 - 1920x1080@50Hz 64:27 */ 1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 76 - 1920x1080@60Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 77 - 1920x1080@100Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 78 - 1920x1080@120Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 79 - 1680x720@24Hz 64:27 */ 1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1135 3080, 3300, 0, 720, 725, 730, 750, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 80 - 1680x720@25Hz 64:27 */ 1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1140 2948, 3168, 0, 720, 725, 730, 750, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 81 - 1680x720@30Hz 64:27 */ 1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1145 2420, 2640, 0, 720, 725, 730, 750, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 82 - 1680x720@50Hz 64:27 */ 1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1150 1980, 2200, 0, 720, 725, 730, 750, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 83 - 1680x720@60Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1155 1980, 2200, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 84 - 1680x720@100Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1160 1780, 2000, 0, 720, 725, 730, 825, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 85 - 1680x720@120Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1165 1780, 2000, 0, 720, 725, 730, 825, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 86 - 2560x1080@24Hz 64:27 */ 1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 87 - 2560x1080@25Hz 64:27 */ 1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 88 - 2560x1080@30Hz 64:27 */ 1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 89 - 2560x1080@50Hz 64:27 */ 1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 90 - 2560x1080@60Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 91 - 2560x1080@100Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 92 - 2560x1080@120Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 93 - 3840x2160@24Hz 16:9 */ 1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1208 /* 94 - 3840x2160@25Hz 16:9 */ 1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1213 /* 95 - 3840x2160@30Hz 16:9 */ 1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1218 /* 96 - 3840x2160@50Hz 16:9 */ 1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1223 /* 97 - 3840x2160@60Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 98 - 4096x2160@24Hz 256:135 */ 1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1233 /* 99 - 4096x2160@25Hz 256:135 */ 1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1238 /* 100 - 4096x2160@30Hz 256:135 */ 1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1243 /* 101 - 4096x2160@50Hz 256:135 */ 1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1248 /* 102 - 4096x2160@60Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 103 - 3840x2160@24Hz 64:27 */ 1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1258 /* 104 - 3840x2160@25Hz 64:27 */ 1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1263 /* 105 - 3840x2160@30Hz 64:27 */ 1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1268 /* 106 - 3840x2160@50Hz 64:27 */ 1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1273 /* 107 - 3840x2160@60Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 /* 108 - 1280x720@48Hz 16:9 */ 1279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1280 2280, 2500, 0, 720, 725, 730, 750, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1283 /* 109 - 1280x720@48Hz 64:27 */ 1284 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1285 2280, 2500, 0, 720, 725, 730, 750, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1288 /* 110 - 1680x720@48Hz 64:27 */ 1289 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1290 2530, 2750, 0, 720, 725, 730, 750, 0, 1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1293 /* 111 - 1920x1080@48Hz 16:9 */ 1294 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1295 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1298 /* 112 - 1920x1080@48Hz 64:27 */ 1299 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1300 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1303 /* 113 - 2560x1080@48Hz 64:27 */ 1304 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1305 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1308 /* 114 - 3840x2160@48Hz 16:9 */ 1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1310 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1313 /* 115 - 4096x2160@48Hz 256:135 */ 1314 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1315 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1318 /* 116 - 3840x2160@48Hz 64:27 */ 1319 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1320 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1323 /* 117 - 3840x2160@100Hz 16:9 */ 1324 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1325 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1328 /* 118 - 3840x2160@120Hz 16:9 */ 1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1330 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1333 /* 119 - 3840x2160@100Hz 64:27 */ 1334 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1335 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1338 /* 120 - 3840x2160@120Hz 64:27 */ 1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1340 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1343 /* 121 - 5120x2160@24Hz 64:27 */ 1344 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1345 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1348 /* 122 - 5120x2160@25Hz 64:27 */ 1349 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1350 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1353 /* 123 - 5120x2160@30Hz 64:27 */ 1354 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1355 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1358 /* 124 - 5120x2160@48Hz 64:27 */ 1359 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1360 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1363 /* 125 - 5120x2160@50Hz 64:27 */ 1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1365 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1368 /* 126 - 5120x2160@60Hz 64:27 */ 1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1370 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1373 /* 127 - 5120x2160@100Hz 64:27 */ 1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1375 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1378 }; 1379 1380 /* 1381 * From CEA/CTA-861 spec. 1382 * 1383 * Do not access directly, instead always use cea_mode_for_vic(). 1384 */ 1385 static const struct drm_display_mode edid_cea_modes_193[] = { 1386 /* 193 - 5120x2160@120Hz 64:27 */ 1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1391 /* 194 - 7680x4320@24Hz 16:9 */ 1392 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1393 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1396 /* 195 - 7680x4320@25Hz 16:9 */ 1397 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1398 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1401 /* 196 - 7680x4320@30Hz 16:9 */ 1402 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1403 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1405 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1406 /* 197 - 7680x4320@48Hz 16:9 */ 1407 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1408 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1411 /* 198 - 7680x4320@50Hz 16:9 */ 1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1413 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1416 /* 199 - 7680x4320@60Hz 16:9 */ 1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1418 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1421 /* 200 - 7680x4320@100Hz 16:9 */ 1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1423 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1426 /* 201 - 7680x4320@120Hz 16:9 */ 1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1428 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1431 /* 202 - 7680x4320@24Hz 64:27 */ 1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1433 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1436 /* 203 - 7680x4320@25Hz 64:27 */ 1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1438 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1441 /* 204 - 7680x4320@30Hz 64:27 */ 1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1443 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1446 /* 205 - 7680x4320@48Hz 64:27 */ 1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1448 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1451 /* 206 - 7680x4320@50Hz 64:27 */ 1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1453 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1456 /* 207 - 7680x4320@60Hz 64:27 */ 1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1458 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1461 /* 208 - 7680x4320@100Hz 64:27 */ 1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1463 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1466 /* 209 - 7680x4320@120Hz 64:27 */ 1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1468 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1471 /* 210 - 10240x4320@24Hz 64:27 */ 1472 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1473 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1476 /* 211 - 10240x4320@25Hz 64:27 */ 1477 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1478 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1481 /* 212 - 10240x4320@30Hz 64:27 */ 1482 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1483 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1486 /* 213 - 10240x4320@48Hz 64:27 */ 1487 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1488 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1491 /* 214 - 10240x4320@50Hz 64:27 */ 1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1493 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1496 /* 215 - 10240x4320@60Hz 64:27 */ 1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1498 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1501 /* 216 - 10240x4320@100Hz 64:27 */ 1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1503 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1506 /* 217 - 10240x4320@120Hz 64:27 */ 1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1508 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1511 /* 218 - 4096x2160@100Hz 256:135 */ 1512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1513 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1516 /* 219 - 4096x2160@120Hz 256:135 */ 1517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1518 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1521 }; 1522 1523 /* 1524 * HDMI 1.4 4k modes. Index using the VIC. 1525 */ 1526 static const struct drm_display_mode edid_4k_modes[] = { 1527 /* 0 - dummy, VICs start at 1 */ 1528 { }, 1529 /* 1 - 3840x2160@30Hz */ 1530 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1531 3840, 4016, 4104, 4400, 0, 1532 2160, 2168, 2178, 2250, 0, 1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1535 /* 2 - 3840x2160@25Hz */ 1536 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1537 3840, 4896, 4984, 5280, 0, 1538 2160, 2168, 2178, 2250, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1541 /* 3 - 3840x2160@24Hz */ 1542 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1543 3840, 5116, 5204, 5500, 0, 1544 2160, 2168, 2178, 2250, 0, 1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1546 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1547 /* 4 - 4096x2160@24Hz (SMPTE) */ 1548 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1549 4096, 5116, 5204, 5500, 0, 1550 2160, 2168, 2178, 2250, 0, 1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1553 }; 1554 1555 /*** DDC fetch and block validation ***/ 1556 1557 static const u8 edid_header[] = { 1558 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1559 }; 1560 1561 /** 1562 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1563 * @raw_edid: pointer to raw base EDID block 1564 * 1565 * Sanity check the header of the base EDID block. 1566 * 1567 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1568 */ 1569 int drm_edid_header_is_valid(const u8 *raw_edid) 1570 { 1571 int i, score = 0; 1572 1573 for (i = 0; i < sizeof(edid_header); i++) 1574 if (raw_edid[i] == edid_header[i]) 1575 score++; 1576 1577 return score; 1578 } 1579 EXPORT_SYMBOL(drm_edid_header_is_valid); 1580 1581 static int edid_fixup __read_mostly = 6; 1582 module_param_named(edid_fixup, edid_fixup, int, 0400); 1583 MODULE_PARM_DESC(edid_fixup, 1584 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1585 1586 static int validate_displayid(u8 *displayid, int length, int idx); 1587 1588 static int drm_edid_block_checksum(const u8 *raw_edid) 1589 { 1590 int i; 1591 u8 csum = 0, crc = 0; 1592 1593 for (i = 0; i < EDID_LENGTH - 1; i++) 1594 csum += raw_edid[i]; 1595 1596 crc = 0x100 - csum; 1597 1598 return crc; 1599 } 1600 1601 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1602 { 1603 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1604 return true; 1605 else 1606 return false; 1607 } 1608 1609 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1610 { 1611 if (memchr_inv(in_edid, 0, length)) 1612 return false; 1613 1614 return true; 1615 } 1616 1617 /** 1618 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1619 * @raw_edid: pointer to raw EDID block 1620 * @block: type of block to validate (0 for base, extension otherwise) 1621 * @print_bad_edid: if true, dump bad EDID blocks to the console 1622 * @edid_corrupt: if true, the header or checksum is invalid 1623 * 1624 * Validate a base or extension EDID block and optionally dump bad blocks to 1625 * the console. 1626 * 1627 * Return: True if the block is valid, false otherwise. 1628 */ 1629 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1630 bool *edid_corrupt) 1631 { 1632 u8 csum; 1633 struct edid *edid = (struct edid *)raw_edid; 1634 1635 if (WARN_ON(!raw_edid)) 1636 return false; 1637 1638 if (edid_fixup > 8 || edid_fixup < 0) 1639 edid_fixup = 6; 1640 1641 if (block == 0) { 1642 int score = drm_edid_header_is_valid(raw_edid); 1643 if (score == 8) { 1644 if (edid_corrupt) 1645 *edid_corrupt = false; 1646 } else if (score >= edid_fixup) { 1647 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1648 * The corrupt flag needs to be set here otherwise, the 1649 * fix-up code here will correct the problem, the 1650 * checksum is correct and the test fails 1651 */ 1652 if (edid_corrupt) 1653 *edid_corrupt = true; 1654 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1655 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1656 } else { 1657 if (edid_corrupt) 1658 *edid_corrupt = true; 1659 goto bad; 1660 } 1661 } 1662 1663 csum = drm_edid_block_checksum(raw_edid); 1664 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1665 if (edid_corrupt) 1666 *edid_corrupt = true; 1667 1668 /* allow CEA to slide through, switches mangle this */ 1669 if (raw_edid[0] == CEA_EXT) { 1670 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1671 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1672 } else { 1673 if (print_bad_edid) 1674 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1675 1676 goto bad; 1677 } 1678 } 1679 1680 /* per-block-type checks */ 1681 switch (raw_edid[0]) { 1682 case 0: /* base */ 1683 if (edid->version != 1) { 1684 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1685 goto bad; 1686 } 1687 1688 if (edid->revision > 4) 1689 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1690 break; 1691 1692 default: 1693 break; 1694 } 1695 1696 return true; 1697 1698 bad: 1699 if (print_bad_edid) { 1700 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1701 pr_notice("EDID block is all zeroes\n"); 1702 } else { 1703 pr_notice("Raw EDID:\n"); 1704 print_hex_dump(KERN_NOTICE, 1705 " \t", DUMP_PREFIX_NONE, 16, 1, 1706 raw_edid, EDID_LENGTH, false); 1707 } 1708 } 1709 return false; 1710 } 1711 EXPORT_SYMBOL(drm_edid_block_valid); 1712 1713 /** 1714 * drm_edid_is_valid - sanity check EDID data 1715 * @edid: EDID data 1716 * 1717 * Sanity-check an entire EDID record (including extensions) 1718 * 1719 * Return: True if the EDID data is valid, false otherwise. 1720 */ 1721 bool drm_edid_is_valid(struct edid *edid) 1722 { 1723 int i; 1724 u8 *raw = (u8 *)edid; 1725 1726 if (!edid) 1727 return false; 1728 1729 for (i = 0; i <= edid->extensions; i++) 1730 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1731 return false; 1732 1733 return true; 1734 } 1735 EXPORT_SYMBOL(drm_edid_is_valid); 1736 1737 #define DDC_SEGMENT_ADDR 0x30 1738 /** 1739 * drm_do_probe_ddc_edid() - get EDID information via I2C 1740 * @data: I2C device adapter 1741 * @buf: EDID data buffer to be filled 1742 * @block: 128 byte EDID block to start fetching from 1743 * @len: EDID data buffer length to fetch 1744 * 1745 * Try to fetch EDID information by calling I2C driver functions. 1746 * 1747 * Return: 0 on success or -1 on failure. 1748 */ 1749 static int 1750 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1751 { 1752 struct i2c_adapter *adapter = data; 1753 unsigned char start = block * EDID_LENGTH; 1754 unsigned char segment = block >> 1; 1755 unsigned char xfers = segment ? 3 : 2; 1756 int ret, retries = 5; 1757 1758 /* 1759 * The core I2C driver will automatically retry the transfer if the 1760 * adapter reports EAGAIN. However, we find that bit-banging transfers 1761 * are susceptible to errors under a heavily loaded machine and 1762 * generate spurious NAKs and timeouts. Retrying the transfer 1763 * of the individual block a few times seems to overcome this. 1764 */ 1765 do { 1766 struct i2c_msg msgs[] = { 1767 { 1768 .addr = DDC_SEGMENT_ADDR, 1769 .flags = 0, 1770 .len = 1, 1771 .buf = &segment, 1772 }, { 1773 .addr = DDC_ADDR, 1774 .flags = 0, 1775 .len = 1, 1776 .buf = &start, 1777 }, { 1778 .addr = DDC_ADDR, 1779 .flags = I2C_M_RD, 1780 .len = len, 1781 .buf = buf, 1782 } 1783 }; 1784 1785 /* 1786 * Avoid sending the segment addr to not upset non-compliant 1787 * DDC monitors. 1788 */ 1789 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1790 1791 if (ret == -ENXIO) { 1792 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1793 adapter->name); 1794 break; 1795 } 1796 } while (ret != xfers && --retries); 1797 1798 return ret == xfers ? 0 : -1; 1799 } 1800 1801 static void connector_bad_edid(struct drm_connector *connector, 1802 u8 *edid, int num_blocks) 1803 { 1804 int i; 1805 u8 num_of_ext = edid[0x7e]; 1806 1807 /* Calculate real checksum for the last edid extension block data */ 1808 connector->real_edid_checksum = 1809 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1810 1811 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1812 return; 1813 1814 dev_warn(connector->dev->dev, 1815 "%s: EDID is invalid:\n", 1816 connector->name); 1817 for (i = 0; i < num_blocks; i++) { 1818 u8 *block = edid + i * EDID_LENGTH; 1819 char prefix[20]; 1820 1821 if (drm_edid_is_zero(block, EDID_LENGTH)) 1822 sprintf(prefix, "\t[%02x] ZERO ", i); 1823 else if (!drm_edid_block_valid(block, i, false, NULL)) 1824 sprintf(prefix, "\t[%02x] BAD ", i); 1825 else 1826 sprintf(prefix, "\t[%02x] GOOD ", i); 1827 1828 print_hex_dump(KERN_WARNING, 1829 prefix, DUMP_PREFIX_NONE, 16, 1, 1830 block, EDID_LENGTH, false); 1831 } 1832 } 1833 1834 /* Get override or firmware EDID */ 1835 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1836 { 1837 struct edid *override = NULL; 1838 1839 if (connector->override_edid) 1840 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1841 1842 if (!override) 1843 override = drm_load_edid_firmware(connector); 1844 1845 return IS_ERR(override) ? NULL : override; 1846 } 1847 1848 /** 1849 * drm_add_override_edid_modes - add modes from override/firmware EDID 1850 * @connector: connector we're probing 1851 * 1852 * Add modes from the override/firmware EDID, if available. Only to be used from 1853 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1854 * failed during drm_get_edid() and caused the override/firmware EDID to be 1855 * skipped. 1856 * 1857 * Return: The number of modes added or 0 if we couldn't find any. 1858 */ 1859 int drm_add_override_edid_modes(struct drm_connector *connector) 1860 { 1861 struct edid *override; 1862 int num_modes = 0; 1863 1864 override = drm_get_override_edid(connector); 1865 if (override) { 1866 drm_connector_update_edid_property(connector, override); 1867 num_modes = drm_add_edid_modes(connector, override); 1868 kfree(override); 1869 1870 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1871 connector->base.id, connector->name, num_modes); 1872 } 1873 1874 return num_modes; 1875 } 1876 EXPORT_SYMBOL(drm_add_override_edid_modes); 1877 1878 /** 1879 * drm_do_get_edid - get EDID data using a custom EDID block read function 1880 * @connector: connector we're probing 1881 * @get_edid_block: EDID block read function 1882 * @data: private data passed to the block read function 1883 * 1884 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1885 * exposes a different interface to read EDID blocks this function can be used 1886 * to get EDID data using a custom block read function. 1887 * 1888 * As in the general case the DDC bus is accessible by the kernel at the I2C 1889 * level, drivers must make all reasonable efforts to expose it as an I2C 1890 * adapter and use drm_get_edid() instead of abusing this function. 1891 * 1892 * The EDID may be overridden using debugfs override_edid or firmare EDID 1893 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1894 * order. Having either of them bypasses actual EDID reads. 1895 * 1896 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1897 */ 1898 struct edid *drm_do_get_edid(struct drm_connector *connector, 1899 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1900 size_t len), 1901 void *data) 1902 { 1903 int i, j = 0, valid_extensions = 0; 1904 u8 *edid, *new; 1905 struct edid *override; 1906 1907 override = drm_get_override_edid(connector); 1908 if (override) 1909 return override; 1910 1911 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1912 return NULL; 1913 1914 /* base block fetch */ 1915 for (i = 0; i < 4; i++) { 1916 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1917 goto out; 1918 if (drm_edid_block_valid(edid, 0, false, 1919 &connector->edid_corrupt)) 1920 break; 1921 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1922 connector->null_edid_counter++; 1923 goto carp; 1924 } 1925 } 1926 if (i == 4) 1927 goto carp; 1928 1929 /* if there's no extensions, we're done */ 1930 valid_extensions = edid[0x7e]; 1931 if (valid_extensions == 0) 1932 return (struct edid *)edid; 1933 1934 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1935 if (!new) 1936 goto out; 1937 edid = new; 1938 1939 for (j = 1; j <= edid[0x7e]; j++) { 1940 u8 *block = edid + j * EDID_LENGTH; 1941 1942 for (i = 0; i < 4; i++) { 1943 if (get_edid_block(data, block, j, EDID_LENGTH)) 1944 goto out; 1945 if (drm_edid_block_valid(block, j, false, NULL)) 1946 break; 1947 } 1948 1949 if (i == 4) 1950 valid_extensions--; 1951 } 1952 1953 if (valid_extensions != edid[0x7e]) { 1954 u8 *base; 1955 1956 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1957 1958 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1959 edid[0x7e] = valid_extensions; 1960 1961 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1962 GFP_KERNEL); 1963 if (!new) 1964 goto out; 1965 1966 base = new; 1967 for (i = 0; i <= edid[0x7e]; i++) { 1968 u8 *block = edid + i * EDID_LENGTH; 1969 1970 if (!drm_edid_block_valid(block, i, false, NULL)) 1971 continue; 1972 1973 memcpy(base, block, EDID_LENGTH); 1974 base += EDID_LENGTH; 1975 } 1976 1977 kfree(edid); 1978 edid = new; 1979 } 1980 1981 return (struct edid *)edid; 1982 1983 carp: 1984 connector_bad_edid(connector, edid, 1); 1985 out: 1986 kfree(edid); 1987 return NULL; 1988 } 1989 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1990 1991 /** 1992 * drm_probe_ddc() - probe DDC presence 1993 * @adapter: I2C adapter to probe 1994 * 1995 * Return: True on success, false on failure. 1996 */ 1997 bool 1998 drm_probe_ddc(struct i2c_adapter *adapter) 1999 { 2000 unsigned char out; 2001 2002 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2003 } 2004 EXPORT_SYMBOL(drm_probe_ddc); 2005 2006 /** 2007 * drm_get_edid - get EDID data, if available 2008 * @connector: connector we're probing 2009 * @adapter: I2C adapter to use for DDC 2010 * 2011 * Poke the given I2C channel to grab EDID data if possible. If found, 2012 * attach it to the connector. 2013 * 2014 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2015 */ 2016 struct edid *drm_get_edid(struct drm_connector *connector, 2017 struct i2c_adapter *adapter) 2018 { 2019 if (connector->force == DRM_FORCE_OFF) 2020 return NULL; 2021 2022 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2023 return NULL; 2024 2025 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2026 } 2027 EXPORT_SYMBOL(drm_get_edid); 2028 2029 /** 2030 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2031 * @connector: connector we're probing 2032 * @adapter: I2C adapter to use for DDC 2033 * 2034 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2035 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2036 * switch DDC to the GPU which is retrieving EDID. 2037 * 2038 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2039 */ 2040 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2041 struct i2c_adapter *adapter) 2042 { 2043 struct pci_dev *pdev = connector->dev->pdev; 2044 struct edid *edid; 2045 2046 vga_switcheroo_lock_ddc(pdev); 2047 edid = drm_get_edid(connector, adapter); 2048 vga_switcheroo_unlock_ddc(pdev); 2049 2050 return edid; 2051 } 2052 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2053 2054 /** 2055 * drm_edid_duplicate - duplicate an EDID and the extensions 2056 * @edid: EDID to duplicate 2057 * 2058 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2059 */ 2060 struct edid *drm_edid_duplicate(const struct edid *edid) 2061 { 2062 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2063 } 2064 EXPORT_SYMBOL(drm_edid_duplicate); 2065 2066 /*** EDID parsing ***/ 2067 2068 /** 2069 * edid_vendor - match a string against EDID's obfuscated vendor field 2070 * @edid: EDID to match 2071 * @vendor: vendor string 2072 * 2073 * Returns true if @vendor is in @edid, false otherwise 2074 */ 2075 static bool edid_vendor(const struct edid *edid, const char *vendor) 2076 { 2077 char edid_vendor[3]; 2078 2079 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2080 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2081 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2082 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2083 2084 return !strncmp(edid_vendor, vendor, 3); 2085 } 2086 2087 /** 2088 * edid_get_quirks - return quirk flags for a given EDID 2089 * @edid: EDID to process 2090 * 2091 * This tells subsequent routines what fixes they need to apply. 2092 */ 2093 static u32 edid_get_quirks(const struct edid *edid) 2094 { 2095 const struct edid_quirk *quirk; 2096 int i; 2097 2098 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2099 quirk = &edid_quirk_list[i]; 2100 2101 if (edid_vendor(edid, quirk->vendor) && 2102 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2103 return quirk->quirks; 2104 } 2105 2106 return 0; 2107 } 2108 2109 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2110 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2111 2112 /** 2113 * edid_fixup_preferred - set preferred modes based on quirk list 2114 * @connector: has mode list to fix up 2115 * @quirks: quirks list 2116 * 2117 * Walk the mode list for @connector, clearing the preferred status 2118 * on existing modes and setting it anew for the right mode ala @quirks. 2119 */ 2120 static void edid_fixup_preferred(struct drm_connector *connector, 2121 u32 quirks) 2122 { 2123 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2124 int target_refresh = 0; 2125 int cur_vrefresh, preferred_vrefresh; 2126 2127 if (list_empty(&connector->probed_modes)) 2128 return; 2129 2130 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2131 target_refresh = 60; 2132 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2133 target_refresh = 75; 2134 2135 preferred_mode = list_first_entry(&connector->probed_modes, 2136 struct drm_display_mode, head); 2137 2138 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2139 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2140 2141 if (cur_mode == preferred_mode) 2142 continue; 2143 2144 /* Largest mode is preferred */ 2145 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2146 preferred_mode = cur_mode; 2147 2148 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2149 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2150 /* At a given size, try to get closest to target refresh */ 2151 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2152 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2153 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2154 preferred_mode = cur_mode; 2155 } 2156 } 2157 2158 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2159 } 2160 2161 static bool 2162 mode_is_rb(const struct drm_display_mode *mode) 2163 { 2164 return (mode->htotal - mode->hdisplay == 160) && 2165 (mode->hsync_end - mode->hdisplay == 80) && 2166 (mode->hsync_end - mode->hsync_start == 32) && 2167 (mode->vsync_start - mode->vdisplay == 3); 2168 } 2169 2170 /* 2171 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2172 * @dev: Device to duplicate against 2173 * @hsize: Mode width 2174 * @vsize: Mode height 2175 * @fresh: Mode refresh rate 2176 * @rb: Mode reduced-blanking-ness 2177 * 2178 * Walk the DMT mode list looking for a match for the given parameters. 2179 * 2180 * Return: A newly allocated copy of the mode, or NULL if not found. 2181 */ 2182 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2183 int hsize, int vsize, int fresh, 2184 bool rb) 2185 { 2186 int i; 2187 2188 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2189 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2190 if (hsize != ptr->hdisplay) 2191 continue; 2192 if (vsize != ptr->vdisplay) 2193 continue; 2194 if (fresh != drm_mode_vrefresh(ptr)) 2195 continue; 2196 if (rb != mode_is_rb(ptr)) 2197 continue; 2198 2199 return drm_mode_duplicate(dev, ptr); 2200 } 2201 2202 return NULL; 2203 } 2204 EXPORT_SYMBOL(drm_mode_find_dmt); 2205 2206 static bool is_display_descriptor(const u8 d[18], u8 tag) 2207 { 2208 return d[0] == 0x00 && d[1] == 0x00 && 2209 d[2] == 0x00 && d[3] == tag; 2210 } 2211 2212 static bool is_detailed_timing_descriptor(const u8 d[18]) 2213 { 2214 return d[0] != 0x00 || d[1] != 0x00; 2215 } 2216 2217 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2218 2219 static void 2220 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2221 { 2222 int i, n; 2223 u8 d = ext[0x02]; 2224 u8 *det_base = ext + d; 2225 2226 if (d < 4 || d > 127) 2227 return; 2228 2229 n = (127 - d) / 18; 2230 for (i = 0; i < n; i++) 2231 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2232 } 2233 2234 static void 2235 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2236 { 2237 unsigned int i, n = min((int)ext[0x02], 6); 2238 u8 *det_base = ext + 5; 2239 2240 if (ext[0x01] != 1) 2241 return; /* unknown version */ 2242 2243 for (i = 0; i < n; i++) 2244 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2245 } 2246 2247 static void 2248 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2249 { 2250 int i; 2251 struct edid *edid = (struct edid *)raw_edid; 2252 2253 if (edid == NULL) 2254 return; 2255 2256 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2257 cb(&(edid->detailed_timings[i]), closure); 2258 2259 for (i = 1; i <= raw_edid[0x7e]; i++) { 2260 u8 *ext = raw_edid + (i * EDID_LENGTH); 2261 switch (*ext) { 2262 case CEA_EXT: 2263 cea_for_each_detailed_block(ext, cb, closure); 2264 break; 2265 case VTB_EXT: 2266 vtb_for_each_detailed_block(ext, cb, closure); 2267 break; 2268 default: 2269 break; 2270 } 2271 } 2272 } 2273 2274 static void 2275 is_rb(struct detailed_timing *t, void *data) 2276 { 2277 u8 *r = (u8 *)t; 2278 2279 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2280 return; 2281 2282 if (r[15] & 0x10) 2283 *(bool *)data = true; 2284 } 2285 2286 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2287 static bool 2288 drm_monitor_supports_rb(struct edid *edid) 2289 { 2290 if (edid->revision >= 4) { 2291 bool ret = false; 2292 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2293 return ret; 2294 } 2295 2296 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2297 } 2298 2299 static void 2300 find_gtf2(struct detailed_timing *t, void *data) 2301 { 2302 u8 *r = (u8 *)t; 2303 2304 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2305 return; 2306 2307 if (r[10] == 0x02) 2308 *(u8 **)data = r; 2309 } 2310 2311 /* Secondary GTF curve kicks in above some break frequency */ 2312 static int 2313 drm_gtf2_hbreak(struct edid *edid) 2314 { 2315 u8 *r = NULL; 2316 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2317 return r ? (r[12] * 2) : 0; 2318 } 2319 2320 static int 2321 drm_gtf2_2c(struct edid *edid) 2322 { 2323 u8 *r = NULL; 2324 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2325 return r ? r[13] : 0; 2326 } 2327 2328 static int 2329 drm_gtf2_m(struct edid *edid) 2330 { 2331 u8 *r = NULL; 2332 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2333 return r ? (r[15] << 8) + r[14] : 0; 2334 } 2335 2336 static int 2337 drm_gtf2_k(struct edid *edid) 2338 { 2339 u8 *r = NULL; 2340 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2341 return r ? r[16] : 0; 2342 } 2343 2344 static int 2345 drm_gtf2_2j(struct edid *edid) 2346 { 2347 u8 *r = NULL; 2348 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2349 return r ? r[17] : 0; 2350 } 2351 2352 /** 2353 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2354 * @edid: EDID block to scan 2355 */ 2356 static int standard_timing_level(struct edid *edid) 2357 { 2358 if (edid->revision >= 2) { 2359 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2360 return LEVEL_CVT; 2361 if (drm_gtf2_hbreak(edid)) 2362 return LEVEL_GTF2; 2363 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2364 return LEVEL_GTF; 2365 } 2366 return LEVEL_DMT; 2367 } 2368 2369 /* 2370 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2371 * monitors fill with ascii space (0x20) instead. 2372 */ 2373 static int 2374 bad_std_timing(u8 a, u8 b) 2375 { 2376 return (a == 0x00 && b == 0x00) || 2377 (a == 0x01 && b == 0x01) || 2378 (a == 0x20 && b == 0x20); 2379 } 2380 2381 static int drm_mode_hsync(const struct drm_display_mode *mode) 2382 { 2383 if (mode->htotal <= 0) 2384 return 0; 2385 2386 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2387 } 2388 2389 /** 2390 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2391 * @connector: connector of for the EDID block 2392 * @edid: EDID block to scan 2393 * @t: standard timing params 2394 * 2395 * Take the standard timing params (in this case width, aspect, and refresh) 2396 * and convert them into a real mode using CVT/GTF/DMT. 2397 */ 2398 static struct drm_display_mode * 2399 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2400 struct std_timing *t) 2401 { 2402 struct drm_device *dev = connector->dev; 2403 struct drm_display_mode *m, *mode = NULL; 2404 int hsize, vsize; 2405 int vrefresh_rate; 2406 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2407 >> EDID_TIMING_ASPECT_SHIFT; 2408 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2409 >> EDID_TIMING_VFREQ_SHIFT; 2410 int timing_level = standard_timing_level(edid); 2411 2412 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2413 return NULL; 2414 2415 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2416 hsize = t->hsize * 8 + 248; 2417 /* vrefresh_rate = vfreq + 60 */ 2418 vrefresh_rate = vfreq + 60; 2419 /* the vdisplay is calculated based on the aspect ratio */ 2420 if (aspect_ratio == 0) { 2421 if (edid->revision < 3) 2422 vsize = hsize; 2423 else 2424 vsize = (hsize * 10) / 16; 2425 } else if (aspect_ratio == 1) 2426 vsize = (hsize * 3) / 4; 2427 else if (aspect_ratio == 2) 2428 vsize = (hsize * 4) / 5; 2429 else 2430 vsize = (hsize * 9) / 16; 2431 2432 /* HDTV hack, part 1 */ 2433 if (vrefresh_rate == 60 && 2434 ((hsize == 1360 && vsize == 765) || 2435 (hsize == 1368 && vsize == 769))) { 2436 hsize = 1366; 2437 vsize = 768; 2438 } 2439 2440 /* 2441 * If this connector already has a mode for this size and refresh 2442 * rate (because it came from detailed or CVT info), use that 2443 * instead. This way we don't have to guess at interlace or 2444 * reduced blanking. 2445 */ 2446 list_for_each_entry(m, &connector->probed_modes, head) 2447 if (m->hdisplay == hsize && m->vdisplay == vsize && 2448 drm_mode_vrefresh(m) == vrefresh_rate) 2449 return NULL; 2450 2451 /* HDTV hack, part 2 */ 2452 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2453 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2454 false); 2455 if (!mode) 2456 return NULL; 2457 mode->hdisplay = 1366; 2458 mode->hsync_start = mode->hsync_start - 1; 2459 mode->hsync_end = mode->hsync_end - 1; 2460 return mode; 2461 } 2462 2463 /* check whether it can be found in default mode table */ 2464 if (drm_monitor_supports_rb(edid)) { 2465 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2466 true); 2467 if (mode) 2468 return mode; 2469 } 2470 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2471 if (mode) 2472 return mode; 2473 2474 /* okay, generate it */ 2475 switch (timing_level) { 2476 case LEVEL_DMT: 2477 break; 2478 case LEVEL_GTF: 2479 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2480 break; 2481 case LEVEL_GTF2: 2482 /* 2483 * This is potentially wrong if there's ever a monitor with 2484 * more than one ranges section, each claiming a different 2485 * secondary GTF curve. Please don't do that. 2486 */ 2487 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2488 if (!mode) 2489 return NULL; 2490 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2491 drm_mode_destroy(dev, mode); 2492 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2493 vrefresh_rate, 0, 0, 2494 drm_gtf2_m(edid), 2495 drm_gtf2_2c(edid), 2496 drm_gtf2_k(edid), 2497 drm_gtf2_2j(edid)); 2498 } 2499 break; 2500 case LEVEL_CVT: 2501 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2502 false); 2503 break; 2504 } 2505 return mode; 2506 } 2507 2508 /* 2509 * EDID is delightfully ambiguous about how interlaced modes are to be 2510 * encoded. Our internal representation is of frame height, but some 2511 * HDTV detailed timings are encoded as field height. 2512 * 2513 * The format list here is from CEA, in frame size. Technically we 2514 * should be checking refresh rate too. Whatever. 2515 */ 2516 static void 2517 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2518 struct detailed_pixel_timing *pt) 2519 { 2520 int i; 2521 static const struct { 2522 int w, h; 2523 } cea_interlaced[] = { 2524 { 1920, 1080 }, 2525 { 720, 480 }, 2526 { 1440, 480 }, 2527 { 2880, 480 }, 2528 { 720, 576 }, 2529 { 1440, 576 }, 2530 { 2880, 576 }, 2531 }; 2532 2533 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2534 return; 2535 2536 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2537 if ((mode->hdisplay == cea_interlaced[i].w) && 2538 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2539 mode->vdisplay *= 2; 2540 mode->vsync_start *= 2; 2541 mode->vsync_end *= 2; 2542 mode->vtotal *= 2; 2543 mode->vtotal |= 1; 2544 } 2545 } 2546 2547 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2548 } 2549 2550 /** 2551 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2552 * @dev: DRM device (needed to create new mode) 2553 * @edid: EDID block 2554 * @timing: EDID detailed timing info 2555 * @quirks: quirks to apply 2556 * 2557 * An EDID detailed timing block contains enough info for us to create and 2558 * return a new struct drm_display_mode. 2559 */ 2560 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2561 struct edid *edid, 2562 struct detailed_timing *timing, 2563 u32 quirks) 2564 { 2565 struct drm_display_mode *mode; 2566 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2567 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2568 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2569 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2570 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2571 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2572 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2573 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2574 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2575 2576 /* ignore tiny modes */ 2577 if (hactive < 64 || vactive < 64) 2578 return NULL; 2579 2580 if (pt->misc & DRM_EDID_PT_STEREO) { 2581 DRM_DEBUG_KMS("stereo mode not supported\n"); 2582 return NULL; 2583 } 2584 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2585 DRM_DEBUG_KMS("composite sync not supported\n"); 2586 } 2587 2588 /* it is incorrect if hsync/vsync width is zero */ 2589 if (!hsync_pulse_width || !vsync_pulse_width) { 2590 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2591 "Wrong Hsync/Vsync pulse width\n"); 2592 return NULL; 2593 } 2594 2595 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2596 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2597 if (!mode) 2598 return NULL; 2599 2600 goto set_size; 2601 } 2602 2603 mode = drm_mode_create(dev); 2604 if (!mode) 2605 return NULL; 2606 2607 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2608 timing->pixel_clock = cpu_to_le16(1088); 2609 2610 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2611 2612 mode->hdisplay = hactive; 2613 mode->hsync_start = mode->hdisplay + hsync_offset; 2614 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2615 mode->htotal = mode->hdisplay + hblank; 2616 2617 mode->vdisplay = vactive; 2618 mode->vsync_start = mode->vdisplay + vsync_offset; 2619 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2620 mode->vtotal = mode->vdisplay + vblank; 2621 2622 /* Some EDIDs have bogus h/vtotal values */ 2623 if (mode->hsync_end > mode->htotal) 2624 mode->htotal = mode->hsync_end + 1; 2625 if (mode->vsync_end > mode->vtotal) 2626 mode->vtotal = mode->vsync_end + 1; 2627 2628 drm_mode_do_interlace_quirk(mode, pt); 2629 2630 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2631 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2632 } 2633 2634 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2635 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2636 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2637 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2638 2639 set_size: 2640 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2641 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2642 2643 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2644 mode->width_mm *= 10; 2645 mode->height_mm *= 10; 2646 } 2647 2648 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2649 mode->width_mm = edid->width_cm * 10; 2650 mode->height_mm = edid->height_cm * 10; 2651 } 2652 2653 mode->type = DRM_MODE_TYPE_DRIVER; 2654 drm_mode_set_name(mode); 2655 2656 return mode; 2657 } 2658 2659 static bool 2660 mode_in_hsync_range(const struct drm_display_mode *mode, 2661 struct edid *edid, u8 *t) 2662 { 2663 int hsync, hmin, hmax; 2664 2665 hmin = t[7]; 2666 if (edid->revision >= 4) 2667 hmin += ((t[4] & 0x04) ? 255 : 0); 2668 hmax = t[8]; 2669 if (edid->revision >= 4) 2670 hmax += ((t[4] & 0x08) ? 255 : 0); 2671 hsync = drm_mode_hsync(mode); 2672 2673 return (hsync <= hmax && hsync >= hmin); 2674 } 2675 2676 static bool 2677 mode_in_vsync_range(const struct drm_display_mode *mode, 2678 struct edid *edid, u8 *t) 2679 { 2680 int vsync, vmin, vmax; 2681 2682 vmin = t[5]; 2683 if (edid->revision >= 4) 2684 vmin += ((t[4] & 0x01) ? 255 : 0); 2685 vmax = t[6]; 2686 if (edid->revision >= 4) 2687 vmax += ((t[4] & 0x02) ? 255 : 0); 2688 vsync = drm_mode_vrefresh(mode); 2689 2690 return (vsync <= vmax && vsync >= vmin); 2691 } 2692 2693 static u32 2694 range_pixel_clock(struct edid *edid, u8 *t) 2695 { 2696 /* unspecified */ 2697 if (t[9] == 0 || t[9] == 255) 2698 return 0; 2699 2700 /* 1.4 with CVT support gives us real precision, yay */ 2701 if (edid->revision >= 4 && t[10] == 0x04) 2702 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2703 2704 /* 1.3 is pathetic, so fuzz up a bit */ 2705 return t[9] * 10000 + 5001; 2706 } 2707 2708 static bool 2709 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2710 struct detailed_timing *timing) 2711 { 2712 u32 max_clock; 2713 u8 *t = (u8 *)timing; 2714 2715 if (!mode_in_hsync_range(mode, edid, t)) 2716 return false; 2717 2718 if (!mode_in_vsync_range(mode, edid, t)) 2719 return false; 2720 2721 if ((max_clock = range_pixel_clock(edid, t))) 2722 if (mode->clock > max_clock) 2723 return false; 2724 2725 /* 1.4 max horizontal check */ 2726 if (edid->revision >= 4 && t[10] == 0x04) 2727 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2728 return false; 2729 2730 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2731 return false; 2732 2733 return true; 2734 } 2735 2736 static bool valid_inferred_mode(const struct drm_connector *connector, 2737 const struct drm_display_mode *mode) 2738 { 2739 const struct drm_display_mode *m; 2740 bool ok = false; 2741 2742 list_for_each_entry(m, &connector->probed_modes, head) { 2743 if (mode->hdisplay == m->hdisplay && 2744 mode->vdisplay == m->vdisplay && 2745 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2746 return false; /* duplicated */ 2747 if (mode->hdisplay <= m->hdisplay && 2748 mode->vdisplay <= m->vdisplay) 2749 ok = true; 2750 } 2751 return ok; 2752 } 2753 2754 static int 2755 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2756 struct detailed_timing *timing) 2757 { 2758 int i, modes = 0; 2759 struct drm_display_mode *newmode; 2760 struct drm_device *dev = connector->dev; 2761 2762 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2763 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2764 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2765 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2766 if (newmode) { 2767 drm_mode_probed_add(connector, newmode); 2768 modes++; 2769 } 2770 } 2771 } 2772 2773 return modes; 2774 } 2775 2776 /* fix up 1366x768 mode from 1368x768; 2777 * GFT/CVT can't express 1366 width which isn't dividable by 8 2778 */ 2779 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2780 { 2781 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2782 mode->hdisplay = 1366; 2783 mode->hsync_start--; 2784 mode->hsync_end--; 2785 drm_mode_set_name(mode); 2786 } 2787 } 2788 2789 static int 2790 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2791 struct detailed_timing *timing) 2792 { 2793 int i, modes = 0; 2794 struct drm_display_mode *newmode; 2795 struct drm_device *dev = connector->dev; 2796 2797 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2798 const struct minimode *m = &extra_modes[i]; 2799 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2800 if (!newmode) 2801 return modes; 2802 2803 drm_mode_fixup_1366x768(newmode); 2804 if (!mode_in_range(newmode, edid, timing) || 2805 !valid_inferred_mode(connector, newmode)) { 2806 drm_mode_destroy(dev, newmode); 2807 continue; 2808 } 2809 2810 drm_mode_probed_add(connector, newmode); 2811 modes++; 2812 } 2813 2814 return modes; 2815 } 2816 2817 static int 2818 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2819 struct detailed_timing *timing) 2820 { 2821 int i, modes = 0; 2822 struct drm_display_mode *newmode; 2823 struct drm_device *dev = connector->dev; 2824 bool rb = drm_monitor_supports_rb(edid); 2825 2826 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2827 const struct minimode *m = &extra_modes[i]; 2828 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2829 if (!newmode) 2830 return modes; 2831 2832 drm_mode_fixup_1366x768(newmode); 2833 if (!mode_in_range(newmode, edid, timing) || 2834 !valid_inferred_mode(connector, newmode)) { 2835 drm_mode_destroy(dev, newmode); 2836 continue; 2837 } 2838 2839 drm_mode_probed_add(connector, newmode); 2840 modes++; 2841 } 2842 2843 return modes; 2844 } 2845 2846 static void 2847 do_inferred_modes(struct detailed_timing *timing, void *c) 2848 { 2849 struct detailed_mode_closure *closure = c; 2850 struct detailed_non_pixel *data = &timing->data.other_data; 2851 struct detailed_data_monitor_range *range = &data->data.range; 2852 2853 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2854 return; 2855 2856 closure->modes += drm_dmt_modes_for_range(closure->connector, 2857 closure->edid, 2858 timing); 2859 2860 if (!version_greater(closure->edid, 1, 1)) 2861 return; /* GTF not defined yet */ 2862 2863 switch (range->flags) { 2864 case 0x02: /* secondary gtf, XXX could do more */ 2865 case 0x00: /* default gtf */ 2866 closure->modes += drm_gtf_modes_for_range(closure->connector, 2867 closure->edid, 2868 timing); 2869 break; 2870 case 0x04: /* cvt, only in 1.4+ */ 2871 if (!version_greater(closure->edid, 1, 3)) 2872 break; 2873 2874 closure->modes += drm_cvt_modes_for_range(closure->connector, 2875 closure->edid, 2876 timing); 2877 break; 2878 case 0x01: /* just the ranges, no formula */ 2879 default: 2880 break; 2881 } 2882 } 2883 2884 static int 2885 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2886 { 2887 struct detailed_mode_closure closure = { 2888 .connector = connector, 2889 .edid = edid, 2890 }; 2891 2892 if (version_greater(edid, 1, 0)) 2893 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2894 &closure); 2895 2896 return closure.modes; 2897 } 2898 2899 static int 2900 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2901 { 2902 int i, j, m, modes = 0; 2903 struct drm_display_mode *mode; 2904 u8 *est = ((u8 *)timing) + 6; 2905 2906 for (i = 0; i < 6; i++) { 2907 for (j = 7; j >= 0; j--) { 2908 m = (i * 8) + (7 - j); 2909 if (m >= ARRAY_SIZE(est3_modes)) 2910 break; 2911 if (est[i] & (1 << j)) { 2912 mode = drm_mode_find_dmt(connector->dev, 2913 est3_modes[m].w, 2914 est3_modes[m].h, 2915 est3_modes[m].r, 2916 est3_modes[m].rb); 2917 if (mode) { 2918 drm_mode_probed_add(connector, mode); 2919 modes++; 2920 } 2921 } 2922 } 2923 } 2924 2925 return modes; 2926 } 2927 2928 static void 2929 do_established_modes(struct detailed_timing *timing, void *c) 2930 { 2931 struct detailed_mode_closure *closure = c; 2932 2933 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2934 return; 2935 2936 closure->modes += drm_est3_modes(closure->connector, timing); 2937 } 2938 2939 /** 2940 * add_established_modes - get est. modes from EDID and add them 2941 * @connector: connector to add mode(s) to 2942 * @edid: EDID block to scan 2943 * 2944 * Each EDID block contains a bitmap of the supported "established modes" list 2945 * (defined above). Tease them out and add them to the global modes list. 2946 */ 2947 static int 2948 add_established_modes(struct drm_connector *connector, struct edid *edid) 2949 { 2950 struct drm_device *dev = connector->dev; 2951 unsigned long est_bits = edid->established_timings.t1 | 2952 (edid->established_timings.t2 << 8) | 2953 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2954 int i, modes = 0; 2955 struct detailed_mode_closure closure = { 2956 .connector = connector, 2957 .edid = edid, 2958 }; 2959 2960 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2961 if (est_bits & (1<<i)) { 2962 struct drm_display_mode *newmode; 2963 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2964 if (newmode) { 2965 drm_mode_probed_add(connector, newmode); 2966 modes++; 2967 } 2968 } 2969 } 2970 2971 if (version_greater(edid, 1, 0)) 2972 drm_for_each_detailed_block((u8 *)edid, 2973 do_established_modes, &closure); 2974 2975 return modes + closure.modes; 2976 } 2977 2978 static void 2979 do_standard_modes(struct detailed_timing *timing, void *c) 2980 { 2981 struct detailed_mode_closure *closure = c; 2982 struct detailed_non_pixel *data = &timing->data.other_data; 2983 struct drm_connector *connector = closure->connector; 2984 struct edid *edid = closure->edid; 2985 int i; 2986 2987 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 2988 return; 2989 2990 for (i = 0; i < 6; i++) { 2991 struct std_timing *std = &data->data.timings[i]; 2992 struct drm_display_mode *newmode; 2993 2994 newmode = drm_mode_std(connector, edid, std); 2995 if (newmode) { 2996 drm_mode_probed_add(connector, newmode); 2997 closure->modes++; 2998 } 2999 } 3000 } 3001 3002 /** 3003 * add_standard_modes - get std. modes from EDID and add them 3004 * @connector: connector to add mode(s) to 3005 * @edid: EDID block to scan 3006 * 3007 * Standard modes can be calculated using the appropriate standard (DMT, 3008 * GTF or CVT. Grab them from @edid and add them to the list. 3009 */ 3010 static int 3011 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3012 { 3013 int i, modes = 0; 3014 struct detailed_mode_closure closure = { 3015 .connector = connector, 3016 .edid = edid, 3017 }; 3018 3019 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3020 struct drm_display_mode *newmode; 3021 3022 newmode = drm_mode_std(connector, edid, 3023 &edid->standard_timings[i]); 3024 if (newmode) { 3025 drm_mode_probed_add(connector, newmode); 3026 modes++; 3027 } 3028 } 3029 3030 if (version_greater(edid, 1, 0)) 3031 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3032 &closure); 3033 3034 /* XXX should also look for standard codes in VTB blocks */ 3035 3036 return modes + closure.modes; 3037 } 3038 3039 static int drm_cvt_modes(struct drm_connector *connector, 3040 struct detailed_timing *timing) 3041 { 3042 int i, j, modes = 0; 3043 struct drm_display_mode *newmode; 3044 struct drm_device *dev = connector->dev; 3045 struct cvt_timing *cvt; 3046 const int rates[] = { 60, 85, 75, 60, 50 }; 3047 const u8 empty[3] = { 0, 0, 0 }; 3048 3049 for (i = 0; i < 4; i++) { 3050 int uninitialized_var(width), height; 3051 cvt = &(timing->data.other_data.data.cvt[i]); 3052 3053 if (!memcmp(cvt->code, empty, 3)) 3054 continue; 3055 3056 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3057 switch (cvt->code[1] & 0x0c) { 3058 case 0x00: 3059 width = height * 4 / 3; 3060 break; 3061 case 0x04: 3062 width = height * 16 / 9; 3063 break; 3064 case 0x08: 3065 width = height * 16 / 10; 3066 break; 3067 case 0x0c: 3068 width = height * 15 / 9; 3069 break; 3070 } 3071 3072 for (j = 1; j < 5; j++) { 3073 if (cvt->code[2] & (1 << j)) { 3074 newmode = drm_cvt_mode(dev, width, height, 3075 rates[j], j == 0, 3076 false, false); 3077 if (newmode) { 3078 drm_mode_probed_add(connector, newmode); 3079 modes++; 3080 } 3081 } 3082 } 3083 } 3084 3085 return modes; 3086 } 3087 3088 static void 3089 do_cvt_mode(struct detailed_timing *timing, void *c) 3090 { 3091 struct detailed_mode_closure *closure = c; 3092 3093 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3094 return; 3095 3096 closure->modes += drm_cvt_modes(closure->connector, timing); 3097 } 3098 3099 static int 3100 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3101 { 3102 struct detailed_mode_closure closure = { 3103 .connector = connector, 3104 .edid = edid, 3105 }; 3106 3107 if (version_greater(edid, 1, 2)) 3108 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3109 3110 /* XXX should also look for CVT codes in VTB blocks */ 3111 3112 return closure.modes; 3113 } 3114 3115 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3116 3117 static void 3118 do_detailed_mode(struct detailed_timing *timing, void *c) 3119 { 3120 struct detailed_mode_closure *closure = c; 3121 struct drm_display_mode *newmode; 3122 3123 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3124 return; 3125 3126 newmode = drm_mode_detailed(closure->connector->dev, 3127 closure->edid, timing, 3128 closure->quirks); 3129 if (!newmode) 3130 return; 3131 3132 if (closure->preferred) 3133 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3134 3135 /* 3136 * Detailed modes are limited to 10kHz pixel clock resolution, 3137 * so fix up anything that looks like CEA/HDMI mode, but the clock 3138 * is just slightly off. 3139 */ 3140 fixup_detailed_cea_mode_clock(newmode); 3141 3142 drm_mode_probed_add(closure->connector, newmode); 3143 closure->modes++; 3144 closure->preferred = false; 3145 } 3146 3147 /* 3148 * add_detailed_modes - Add modes from detailed timings 3149 * @connector: attached connector 3150 * @edid: EDID block to scan 3151 * @quirks: quirks to apply 3152 */ 3153 static int 3154 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3155 u32 quirks) 3156 { 3157 struct detailed_mode_closure closure = { 3158 .connector = connector, 3159 .edid = edid, 3160 .preferred = true, 3161 .quirks = quirks, 3162 }; 3163 3164 if (closure.preferred && !version_greater(edid, 1, 3)) 3165 closure.preferred = 3166 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3167 3168 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3169 3170 return closure.modes; 3171 } 3172 3173 #define AUDIO_BLOCK 0x01 3174 #define VIDEO_BLOCK 0x02 3175 #define VENDOR_BLOCK 0x03 3176 #define SPEAKER_BLOCK 0x04 3177 #define HDR_STATIC_METADATA_BLOCK 0x6 3178 #define USE_EXTENDED_TAG 0x07 3179 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3180 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3181 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3182 #define EDID_BASIC_AUDIO (1 << 6) 3183 #define EDID_CEA_YCRCB444 (1 << 5) 3184 #define EDID_CEA_YCRCB422 (1 << 4) 3185 #define EDID_CEA_VCDB_QS (1 << 6) 3186 3187 /* 3188 * Search EDID for CEA extension block. 3189 */ 3190 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3191 { 3192 u8 *edid_ext = NULL; 3193 int i; 3194 3195 /* No EDID or EDID extensions */ 3196 if (edid == NULL || edid->extensions == 0) 3197 return NULL; 3198 3199 /* Find CEA extension */ 3200 for (i = 0; i < edid->extensions; i++) { 3201 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3202 if (edid_ext[0] == ext_id) 3203 break; 3204 } 3205 3206 if (i == edid->extensions) 3207 return NULL; 3208 3209 return edid_ext; 3210 } 3211 3212 3213 static u8 *drm_find_displayid_extension(const struct edid *edid, 3214 int *length, int *idx) 3215 { 3216 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT); 3217 struct displayid_hdr *base; 3218 int ret; 3219 3220 if (!displayid) 3221 return NULL; 3222 3223 /* EDID extensions block checksum isn't for us */ 3224 *length = EDID_LENGTH - 1; 3225 *idx = 1; 3226 3227 ret = validate_displayid(displayid, *length, *idx); 3228 if (ret) 3229 return NULL; 3230 3231 base = (struct displayid_hdr *)&displayid[*idx]; 3232 *length = *idx + sizeof(*base) + base->bytes; 3233 3234 return displayid; 3235 } 3236 3237 static u8 *drm_find_cea_extension(const struct edid *edid) 3238 { 3239 int length, idx; 3240 struct displayid_block *block; 3241 u8 *cea; 3242 u8 *displayid; 3243 3244 /* Look for a top level CEA extension block */ 3245 cea = drm_find_edid_extension(edid, CEA_EXT); 3246 if (cea) 3247 return cea; 3248 3249 /* CEA blocks can also be found embedded in a DisplayID block */ 3250 displayid = drm_find_displayid_extension(edid, &length, &idx); 3251 if (!displayid) 3252 return NULL; 3253 3254 idx += sizeof(struct displayid_hdr); 3255 for_each_displayid_db(displayid, block, idx, length) { 3256 if (block->tag == DATA_BLOCK_CTA) { 3257 cea = (u8 *)block; 3258 break; 3259 } 3260 } 3261 3262 return cea; 3263 } 3264 3265 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3266 { 3267 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3268 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3269 3270 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3271 return &edid_cea_modes_1[vic - 1]; 3272 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3273 return &edid_cea_modes_193[vic - 193]; 3274 return NULL; 3275 } 3276 3277 static u8 cea_num_vics(void) 3278 { 3279 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3280 } 3281 3282 static u8 cea_next_vic(u8 vic) 3283 { 3284 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3285 vic = 193; 3286 return vic; 3287 } 3288 3289 /* 3290 * Calculate the alternate clock for the CEA mode 3291 * (60Hz vs. 59.94Hz etc.) 3292 */ 3293 static unsigned int 3294 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3295 { 3296 unsigned int clock = cea_mode->clock; 3297 3298 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3299 return clock; 3300 3301 /* 3302 * edid_cea_modes contains the 59.94Hz 3303 * variant for 240 and 480 line modes, 3304 * and the 60Hz variant otherwise. 3305 */ 3306 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3307 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3308 else 3309 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3310 3311 return clock; 3312 } 3313 3314 static bool 3315 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3316 { 3317 /* 3318 * For certain VICs the spec allows the vertical 3319 * front porch to vary by one or two lines. 3320 * 3321 * cea_modes[] stores the variant with the shortest 3322 * vertical front porch. We can adjust the mode to 3323 * get the other variants by simply increasing the 3324 * vertical front porch length. 3325 */ 3326 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3327 cea_mode_for_vic(9)->vtotal != 262 || 3328 cea_mode_for_vic(12)->vtotal != 262 || 3329 cea_mode_for_vic(13)->vtotal != 262 || 3330 cea_mode_for_vic(23)->vtotal != 312 || 3331 cea_mode_for_vic(24)->vtotal != 312 || 3332 cea_mode_for_vic(27)->vtotal != 312 || 3333 cea_mode_for_vic(28)->vtotal != 312); 3334 3335 if (((vic == 8 || vic == 9 || 3336 vic == 12 || vic == 13) && mode->vtotal < 263) || 3337 ((vic == 23 || vic == 24 || 3338 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3339 mode->vsync_start++; 3340 mode->vsync_end++; 3341 mode->vtotal++; 3342 3343 return true; 3344 } 3345 3346 return false; 3347 } 3348 3349 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3350 unsigned int clock_tolerance) 3351 { 3352 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3353 u8 vic; 3354 3355 if (!to_match->clock) 3356 return 0; 3357 3358 if (to_match->picture_aspect_ratio) 3359 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3360 3361 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3362 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3363 unsigned int clock1, clock2; 3364 3365 /* Check both 60Hz and 59.94Hz */ 3366 clock1 = cea_mode.clock; 3367 clock2 = cea_mode_alternate_clock(&cea_mode); 3368 3369 if (abs(to_match->clock - clock1) > clock_tolerance && 3370 abs(to_match->clock - clock2) > clock_tolerance) 3371 continue; 3372 3373 do { 3374 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3375 return vic; 3376 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3377 } 3378 3379 return 0; 3380 } 3381 3382 /** 3383 * drm_match_cea_mode - look for a CEA mode matching given mode 3384 * @to_match: display mode 3385 * 3386 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3387 * mode. 3388 */ 3389 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3390 { 3391 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3392 u8 vic; 3393 3394 if (!to_match->clock) 3395 return 0; 3396 3397 if (to_match->picture_aspect_ratio) 3398 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3399 3400 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3401 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3402 unsigned int clock1, clock2; 3403 3404 /* Check both 60Hz and 59.94Hz */ 3405 clock1 = cea_mode.clock; 3406 clock2 = cea_mode_alternate_clock(&cea_mode); 3407 3408 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3409 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3410 continue; 3411 3412 do { 3413 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3414 return vic; 3415 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3416 } 3417 3418 return 0; 3419 } 3420 EXPORT_SYMBOL(drm_match_cea_mode); 3421 3422 static bool drm_valid_cea_vic(u8 vic) 3423 { 3424 return cea_mode_for_vic(vic) != NULL; 3425 } 3426 3427 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3428 { 3429 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3430 3431 if (mode) 3432 return mode->picture_aspect_ratio; 3433 3434 return HDMI_PICTURE_ASPECT_NONE; 3435 } 3436 3437 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3438 { 3439 return edid_4k_modes[video_code].picture_aspect_ratio; 3440 } 3441 3442 /* 3443 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3444 * specific block). 3445 */ 3446 static unsigned int 3447 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3448 { 3449 return cea_mode_alternate_clock(hdmi_mode); 3450 } 3451 3452 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3453 unsigned int clock_tolerance) 3454 { 3455 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3456 u8 vic; 3457 3458 if (!to_match->clock) 3459 return 0; 3460 3461 if (to_match->picture_aspect_ratio) 3462 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3463 3464 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3465 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3466 unsigned int clock1, clock2; 3467 3468 /* Make sure to also match alternate clocks */ 3469 clock1 = hdmi_mode->clock; 3470 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3471 3472 if (abs(to_match->clock - clock1) > clock_tolerance && 3473 abs(to_match->clock - clock2) > clock_tolerance) 3474 continue; 3475 3476 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3477 return vic; 3478 } 3479 3480 return 0; 3481 } 3482 3483 /* 3484 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3485 * @to_match: display mode 3486 * 3487 * An HDMI mode is one defined in the HDMI vendor specific block. 3488 * 3489 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3490 */ 3491 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3492 { 3493 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3494 u8 vic; 3495 3496 if (!to_match->clock) 3497 return 0; 3498 3499 if (to_match->picture_aspect_ratio) 3500 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3501 3502 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3503 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3504 unsigned int clock1, clock2; 3505 3506 /* Make sure to also match alternate clocks */ 3507 clock1 = hdmi_mode->clock; 3508 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3509 3510 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3511 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3512 drm_mode_match(to_match, hdmi_mode, match_flags)) 3513 return vic; 3514 } 3515 return 0; 3516 } 3517 3518 static bool drm_valid_hdmi_vic(u8 vic) 3519 { 3520 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3521 } 3522 3523 static int 3524 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3525 { 3526 struct drm_device *dev = connector->dev; 3527 struct drm_display_mode *mode, *tmp; 3528 LIST_HEAD(list); 3529 int modes = 0; 3530 3531 /* Don't add CEA modes if the CEA extension block is missing */ 3532 if (!drm_find_cea_extension(edid)) 3533 return 0; 3534 3535 /* 3536 * Go through all probed modes and create a new mode 3537 * with the alternate clock for certain CEA modes. 3538 */ 3539 list_for_each_entry(mode, &connector->probed_modes, head) { 3540 const struct drm_display_mode *cea_mode = NULL; 3541 struct drm_display_mode *newmode; 3542 u8 vic = drm_match_cea_mode(mode); 3543 unsigned int clock1, clock2; 3544 3545 if (drm_valid_cea_vic(vic)) { 3546 cea_mode = cea_mode_for_vic(vic); 3547 clock2 = cea_mode_alternate_clock(cea_mode); 3548 } else { 3549 vic = drm_match_hdmi_mode(mode); 3550 if (drm_valid_hdmi_vic(vic)) { 3551 cea_mode = &edid_4k_modes[vic]; 3552 clock2 = hdmi_mode_alternate_clock(cea_mode); 3553 } 3554 } 3555 3556 if (!cea_mode) 3557 continue; 3558 3559 clock1 = cea_mode->clock; 3560 3561 if (clock1 == clock2) 3562 continue; 3563 3564 if (mode->clock != clock1 && mode->clock != clock2) 3565 continue; 3566 3567 newmode = drm_mode_duplicate(dev, cea_mode); 3568 if (!newmode) 3569 continue; 3570 3571 /* Carry over the stereo flags */ 3572 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3573 3574 /* 3575 * The current mode could be either variant. Make 3576 * sure to pick the "other" clock for the new mode. 3577 */ 3578 if (mode->clock != clock1) 3579 newmode->clock = clock1; 3580 else 3581 newmode->clock = clock2; 3582 3583 list_add_tail(&newmode->head, &list); 3584 } 3585 3586 list_for_each_entry_safe(mode, tmp, &list, head) { 3587 list_del(&mode->head); 3588 drm_mode_probed_add(connector, mode); 3589 modes++; 3590 } 3591 3592 return modes; 3593 } 3594 3595 static u8 svd_to_vic(u8 svd) 3596 { 3597 /* 0-6 bit vic, 7th bit native mode indicator */ 3598 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3599 return svd & 127; 3600 3601 return svd; 3602 } 3603 3604 static struct drm_display_mode * 3605 drm_display_mode_from_vic_index(struct drm_connector *connector, 3606 const u8 *video_db, u8 video_len, 3607 u8 video_index) 3608 { 3609 struct drm_device *dev = connector->dev; 3610 struct drm_display_mode *newmode; 3611 u8 vic; 3612 3613 if (video_db == NULL || video_index >= video_len) 3614 return NULL; 3615 3616 /* CEA modes are numbered 1..127 */ 3617 vic = svd_to_vic(video_db[video_index]); 3618 if (!drm_valid_cea_vic(vic)) 3619 return NULL; 3620 3621 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3622 if (!newmode) 3623 return NULL; 3624 3625 return newmode; 3626 } 3627 3628 /* 3629 * do_y420vdb_modes - Parse YCBCR 420 only modes 3630 * @connector: connector corresponding to the HDMI sink 3631 * @svds: start of the data block of CEA YCBCR 420 VDB 3632 * @len: length of the CEA YCBCR 420 VDB 3633 * 3634 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3635 * which contains modes which can be supported in YCBCR 420 3636 * output format only. 3637 */ 3638 static int do_y420vdb_modes(struct drm_connector *connector, 3639 const u8 *svds, u8 svds_len) 3640 { 3641 int modes = 0, i; 3642 struct drm_device *dev = connector->dev; 3643 struct drm_display_info *info = &connector->display_info; 3644 struct drm_hdmi_info *hdmi = &info->hdmi; 3645 3646 for (i = 0; i < svds_len; i++) { 3647 u8 vic = svd_to_vic(svds[i]); 3648 struct drm_display_mode *newmode; 3649 3650 if (!drm_valid_cea_vic(vic)) 3651 continue; 3652 3653 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3654 if (!newmode) 3655 break; 3656 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3657 drm_mode_probed_add(connector, newmode); 3658 modes++; 3659 } 3660 3661 if (modes > 0) 3662 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3663 return modes; 3664 } 3665 3666 /* 3667 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3668 * @connector: connector corresponding to the HDMI sink 3669 * @vic: CEA vic for the video mode to be added in the map 3670 * 3671 * Makes an entry for a videomode in the YCBCR 420 bitmap 3672 */ 3673 static void 3674 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3675 { 3676 u8 vic = svd_to_vic(svd); 3677 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3678 3679 if (!drm_valid_cea_vic(vic)) 3680 return; 3681 3682 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3683 } 3684 3685 static int 3686 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3687 { 3688 int i, modes = 0; 3689 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3690 3691 for (i = 0; i < len; i++) { 3692 struct drm_display_mode *mode; 3693 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3694 if (mode) { 3695 /* 3696 * YCBCR420 capability block contains a bitmap which 3697 * gives the index of CEA modes from CEA VDB, which 3698 * can support YCBCR 420 sampling output also (apart 3699 * from RGB/YCBCR444 etc). 3700 * For example, if the bit 0 in bitmap is set, 3701 * first mode in VDB can support YCBCR420 output too. 3702 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3703 */ 3704 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3705 drm_add_cmdb_modes(connector, db[i]); 3706 3707 drm_mode_probed_add(connector, mode); 3708 modes++; 3709 } 3710 } 3711 3712 return modes; 3713 } 3714 3715 struct stereo_mandatory_mode { 3716 int width, height, vrefresh; 3717 unsigned int flags; 3718 }; 3719 3720 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3721 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3722 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3723 { 1920, 1080, 50, 3724 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3725 { 1920, 1080, 60, 3726 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3727 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3728 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3729 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3730 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3731 }; 3732 3733 static bool 3734 stereo_match_mandatory(const struct drm_display_mode *mode, 3735 const struct stereo_mandatory_mode *stereo_mode) 3736 { 3737 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3738 3739 return mode->hdisplay == stereo_mode->width && 3740 mode->vdisplay == stereo_mode->height && 3741 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3742 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3743 } 3744 3745 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3746 { 3747 struct drm_device *dev = connector->dev; 3748 const struct drm_display_mode *mode; 3749 struct list_head stereo_modes; 3750 int modes = 0, i; 3751 3752 INIT_LIST_HEAD(&stereo_modes); 3753 3754 list_for_each_entry(mode, &connector->probed_modes, head) { 3755 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3756 const struct stereo_mandatory_mode *mandatory; 3757 struct drm_display_mode *new_mode; 3758 3759 if (!stereo_match_mandatory(mode, 3760 &stereo_mandatory_modes[i])) 3761 continue; 3762 3763 mandatory = &stereo_mandatory_modes[i]; 3764 new_mode = drm_mode_duplicate(dev, mode); 3765 if (!new_mode) 3766 continue; 3767 3768 new_mode->flags |= mandatory->flags; 3769 list_add_tail(&new_mode->head, &stereo_modes); 3770 modes++; 3771 } 3772 } 3773 3774 list_splice_tail(&stereo_modes, &connector->probed_modes); 3775 3776 return modes; 3777 } 3778 3779 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3780 { 3781 struct drm_device *dev = connector->dev; 3782 struct drm_display_mode *newmode; 3783 3784 if (!drm_valid_hdmi_vic(vic)) { 3785 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3786 return 0; 3787 } 3788 3789 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3790 if (!newmode) 3791 return 0; 3792 3793 drm_mode_probed_add(connector, newmode); 3794 3795 return 1; 3796 } 3797 3798 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3799 const u8 *video_db, u8 video_len, u8 video_index) 3800 { 3801 struct drm_display_mode *newmode; 3802 int modes = 0; 3803 3804 if (structure & (1 << 0)) { 3805 newmode = drm_display_mode_from_vic_index(connector, video_db, 3806 video_len, 3807 video_index); 3808 if (newmode) { 3809 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3810 drm_mode_probed_add(connector, newmode); 3811 modes++; 3812 } 3813 } 3814 if (structure & (1 << 6)) { 3815 newmode = drm_display_mode_from_vic_index(connector, video_db, 3816 video_len, 3817 video_index); 3818 if (newmode) { 3819 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3820 drm_mode_probed_add(connector, newmode); 3821 modes++; 3822 } 3823 } 3824 if (structure & (1 << 8)) { 3825 newmode = drm_display_mode_from_vic_index(connector, video_db, 3826 video_len, 3827 video_index); 3828 if (newmode) { 3829 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3830 drm_mode_probed_add(connector, newmode); 3831 modes++; 3832 } 3833 } 3834 3835 return modes; 3836 } 3837 3838 /* 3839 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3840 * @connector: connector corresponding to the HDMI sink 3841 * @db: start of the CEA vendor specific block 3842 * @len: length of the CEA block payload, ie. one can access up to db[len] 3843 * 3844 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3845 * also adds the stereo 3d modes when applicable. 3846 */ 3847 static int 3848 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3849 const u8 *video_db, u8 video_len) 3850 { 3851 struct drm_display_info *info = &connector->display_info; 3852 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3853 u8 vic_len, hdmi_3d_len = 0; 3854 u16 mask; 3855 u16 structure_all; 3856 3857 if (len < 8) 3858 goto out; 3859 3860 /* no HDMI_Video_Present */ 3861 if (!(db[8] & (1 << 5))) 3862 goto out; 3863 3864 /* Latency_Fields_Present */ 3865 if (db[8] & (1 << 7)) 3866 offset += 2; 3867 3868 /* I_Latency_Fields_Present */ 3869 if (db[8] & (1 << 6)) 3870 offset += 2; 3871 3872 /* the declared length is not long enough for the 2 first bytes 3873 * of additional video format capabilities */ 3874 if (len < (8 + offset + 2)) 3875 goto out; 3876 3877 /* 3D_Present */ 3878 offset++; 3879 if (db[8 + offset] & (1 << 7)) { 3880 modes += add_hdmi_mandatory_stereo_modes(connector); 3881 3882 /* 3D_Multi_present */ 3883 multi_present = (db[8 + offset] & 0x60) >> 5; 3884 } 3885 3886 offset++; 3887 vic_len = db[8 + offset] >> 5; 3888 hdmi_3d_len = db[8 + offset] & 0x1f; 3889 3890 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3891 u8 vic; 3892 3893 vic = db[9 + offset + i]; 3894 modes += add_hdmi_mode(connector, vic); 3895 } 3896 offset += 1 + vic_len; 3897 3898 if (multi_present == 1) 3899 multi_len = 2; 3900 else if (multi_present == 2) 3901 multi_len = 4; 3902 else 3903 multi_len = 0; 3904 3905 if (len < (8 + offset + hdmi_3d_len - 1)) 3906 goto out; 3907 3908 if (hdmi_3d_len < multi_len) 3909 goto out; 3910 3911 if (multi_present == 1 || multi_present == 2) { 3912 /* 3D_Structure_ALL */ 3913 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3914 3915 /* check if 3D_MASK is present */ 3916 if (multi_present == 2) 3917 mask = (db[10 + offset] << 8) | db[11 + offset]; 3918 else 3919 mask = 0xffff; 3920 3921 for (i = 0; i < 16; i++) { 3922 if (mask & (1 << i)) 3923 modes += add_3d_struct_modes(connector, 3924 structure_all, 3925 video_db, 3926 video_len, i); 3927 } 3928 } 3929 3930 offset += multi_len; 3931 3932 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3933 int vic_index; 3934 struct drm_display_mode *newmode = NULL; 3935 unsigned int newflag = 0; 3936 bool detail_present; 3937 3938 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3939 3940 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3941 break; 3942 3943 /* 2D_VIC_order_X */ 3944 vic_index = db[8 + offset + i] >> 4; 3945 3946 /* 3D_Structure_X */ 3947 switch (db[8 + offset + i] & 0x0f) { 3948 case 0: 3949 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3950 break; 3951 case 6: 3952 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3953 break; 3954 case 8: 3955 /* 3D_Detail_X */ 3956 if ((db[9 + offset + i] >> 4) == 1) 3957 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3958 break; 3959 } 3960 3961 if (newflag != 0) { 3962 newmode = drm_display_mode_from_vic_index(connector, 3963 video_db, 3964 video_len, 3965 vic_index); 3966 3967 if (newmode) { 3968 newmode->flags |= newflag; 3969 drm_mode_probed_add(connector, newmode); 3970 modes++; 3971 } 3972 } 3973 3974 if (detail_present) 3975 i++; 3976 } 3977 3978 out: 3979 if (modes > 0) 3980 info->has_hdmi_infoframe = true; 3981 return modes; 3982 } 3983 3984 static int 3985 cea_db_payload_len(const u8 *db) 3986 { 3987 return db[0] & 0x1f; 3988 } 3989 3990 static int 3991 cea_db_extended_tag(const u8 *db) 3992 { 3993 return db[1]; 3994 } 3995 3996 static int 3997 cea_db_tag(const u8 *db) 3998 { 3999 return db[0] >> 5; 4000 } 4001 4002 static int 4003 cea_revision(const u8 *cea) 4004 { 4005 /* 4006 * FIXME is this correct for the DispID variant? 4007 * The DispID spec doesn't really specify whether 4008 * this is the revision of the CEA extension or 4009 * the DispID CEA data block. And the only value 4010 * given as an example is 0. 4011 */ 4012 return cea[1]; 4013 } 4014 4015 static int 4016 cea_db_offsets(const u8 *cea, int *start, int *end) 4017 { 4018 /* DisplayID CTA extension blocks and top-level CEA EDID 4019 * block header definitions differ in the following bytes: 4020 * 1) Byte 2 of the header specifies length differently, 4021 * 2) Byte 3 is only present in the CEA top level block. 4022 * 4023 * The different definitions for byte 2 follow. 4024 * 4025 * DisplayID CTA extension block defines byte 2 as: 4026 * Number of payload bytes 4027 * 4028 * CEA EDID block defines byte 2 as: 4029 * Byte number (decimal) within this block where the 18-byte 4030 * DTDs begin. If no non-DTD data is present in this extension 4031 * block, the value should be set to 04h (the byte after next). 4032 * If set to 00h, there are no DTDs present in this block and 4033 * no non-DTD data. 4034 */ 4035 if (cea[0] == DATA_BLOCK_CTA) { 4036 /* 4037 * for_each_displayid_db() has already verified 4038 * that these stay within expected bounds. 4039 */ 4040 *start = 3; 4041 *end = *start + cea[2]; 4042 } else if (cea[0] == CEA_EXT) { 4043 /* Data block offset in CEA extension block */ 4044 *start = 4; 4045 *end = cea[2]; 4046 if (*end == 0) 4047 *end = 127; 4048 if (*end < 4 || *end > 127) 4049 return -ERANGE; 4050 } else { 4051 return -EOPNOTSUPP; 4052 } 4053 4054 return 0; 4055 } 4056 4057 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4058 { 4059 int hdmi_id; 4060 4061 if (cea_db_tag(db) != VENDOR_BLOCK) 4062 return false; 4063 4064 if (cea_db_payload_len(db) < 5) 4065 return false; 4066 4067 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4068 4069 return hdmi_id == HDMI_IEEE_OUI; 4070 } 4071 4072 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4073 { 4074 unsigned int oui; 4075 4076 if (cea_db_tag(db) != VENDOR_BLOCK) 4077 return false; 4078 4079 if (cea_db_payload_len(db) < 7) 4080 return false; 4081 4082 oui = db[3] << 16 | db[2] << 8 | db[1]; 4083 4084 return oui == HDMI_FORUM_IEEE_OUI; 4085 } 4086 4087 static bool cea_db_is_vcdb(const u8 *db) 4088 { 4089 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4090 return false; 4091 4092 if (cea_db_payload_len(db) != 2) 4093 return false; 4094 4095 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4096 return false; 4097 4098 return true; 4099 } 4100 4101 static bool cea_db_is_y420cmdb(const u8 *db) 4102 { 4103 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4104 return false; 4105 4106 if (!cea_db_payload_len(db)) 4107 return false; 4108 4109 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4110 return false; 4111 4112 return true; 4113 } 4114 4115 static bool cea_db_is_y420vdb(const u8 *db) 4116 { 4117 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4118 return false; 4119 4120 if (!cea_db_payload_len(db)) 4121 return false; 4122 4123 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4124 return false; 4125 4126 return true; 4127 } 4128 4129 #define for_each_cea_db(cea, i, start, end) \ 4130 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4131 4132 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4133 const u8 *db) 4134 { 4135 struct drm_display_info *info = &connector->display_info; 4136 struct drm_hdmi_info *hdmi = &info->hdmi; 4137 u8 map_len = cea_db_payload_len(db) - 1; 4138 u8 count; 4139 u64 map = 0; 4140 4141 if (map_len == 0) { 4142 /* All CEA modes support ycbcr420 sampling also.*/ 4143 hdmi->y420_cmdb_map = U64_MAX; 4144 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4145 return; 4146 } 4147 4148 /* 4149 * This map indicates which of the existing CEA block modes 4150 * from VDB can support YCBCR420 output too. So if bit=0 is 4151 * set, first mode from VDB can support YCBCR420 output too. 4152 * We will parse and keep this map, before parsing VDB itself 4153 * to avoid going through the same block again and again. 4154 * 4155 * Spec is not clear about max possible size of this block. 4156 * Clamping max bitmap block size at 8 bytes. Every byte can 4157 * address 8 CEA modes, in this way this map can address 4158 * 8*8 = first 64 SVDs. 4159 */ 4160 if (WARN_ON_ONCE(map_len > 8)) 4161 map_len = 8; 4162 4163 for (count = 0; count < map_len; count++) 4164 map |= (u64)db[2 + count] << (8 * count); 4165 4166 if (map) 4167 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4168 4169 hdmi->y420_cmdb_map = map; 4170 } 4171 4172 static int 4173 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4174 { 4175 const u8 *cea = drm_find_cea_extension(edid); 4176 const u8 *db, *hdmi = NULL, *video = NULL; 4177 u8 dbl, hdmi_len, video_len = 0; 4178 int modes = 0; 4179 4180 if (cea && cea_revision(cea) >= 3) { 4181 int i, start, end; 4182 4183 if (cea_db_offsets(cea, &start, &end)) 4184 return 0; 4185 4186 for_each_cea_db(cea, i, start, end) { 4187 db = &cea[i]; 4188 dbl = cea_db_payload_len(db); 4189 4190 if (cea_db_tag(db) == VIDEO_BLOCK) { 4191 video = db + 1; 4192 video_len = dbl; 4193 modes += do_cea_modes(connector, video, dbl); 4194 } else if (cea_db_is_hdmi_vsdb(db)) { 4195 hdmi = db; 4196 hdmi_len = dbl; 4197 } else if (cea_db_is_y420vdb(db)) { 4198 const u8 *vdb420 = &db[2]; 4199 4200 /* Add 4:2:0(only) modes present in EDID */ 4201 modes += do_y420vdb_modes(connector, 4202 vdb420, 4203 dbl - 1); 4204 } 4205 } 4206 } 4207 4208 /* 4209 * We parse the HDMI VSDB after having added the cea modes as we will 4210 * be patching their flags when the sink supports stereo 3D. 4211 */ 4212 if (hdmi) 4213 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4214 video_len); 4215 4216 return modes; 4217 } 4218 4219 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4220 { 4221 const struct drm_display_mode *cea_mode; 4222 int clock1, clock2, clock; 4223 u8 vic; 4224 const char *type; 4225 4226 /* 4227 * allow 5kHz clock difference either way to account for 4228 * the 10kHz clock resolution limit of detailed timings. 4229 */ 4230 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4231 if (drm_valid_cea_vic(vic)) { 4232 type = "CEA"; 4233 cea_mode = cea_mode_for_vic(vic); 4234 clock1 = cea_mode->clock; 4235 clock2 = cea_mode_alternate_clock(cea_mode); 4236 } else { 4237 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4238 if (drm_valid_hdmi_vic(vic)) { 4239 type = "HDMI"; 4240 cea_mode = &edid_4k_modes[vic]; 4241 clock1 = cea_mode->clock; 4242 clock2 = hdmi_mode_alternate_clock(cea_mode); 4243 } else { 4244 return; 4245 } 4246 } 4247 4248 /* pick whichever is closest */ 4249 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4250 clock = clock1; 4251 else 4252 clock = clock2; 4253 4254 if (mode->clock == clock) 4255 return; 4256 4257 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4258 type, vic, mode->clock, clock); 4259 mode->clock = clock; 4260 } 4261 4262 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4263 { 4264 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4265 return false; 4266 4267 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4268 return false; 4269 4270 if (cea_db_payload_len(db) < 3) 4271 return false; 4272 4273 return true; 4274 } 4275 4276 static uint8_t eotf_supported(const u8 *edid_ext) 4277 { 4278 return edid_ext[2] & 4279 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4280 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4281 BIT(HDMI_EOTF_SMPTE_ST2084) | 4282 BIT(HDMI_EOTF_BT_2100_HLG)); 4283 } 4284 4285 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4286 { 4287 return edid_ext[3] & 4288 BIT(HDMI_STATIC_METADATA_TYPE1); 4289 } 4290 4291 static void 4292 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4293 { 4294 u16 len; 4295 4296 len = cea_db_payload_len(db); 4297 4298 connector->hdr_sink_metadata.hdmi_type1.eotf = 4299 eotf_supported(db); 4300 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4301 hdr_metadata_type(db); 4302 4303 if (len >= 4) 4304 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4305 if (len >= 5) 4306 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4307 if (len >= 6) 4308 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4309 } 4310 4311 static void 4312 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4313 { 4314 u8 len = cea_db_payload_len(db); 4315 4316 if (len >= 6 && (db[6] & (1 << 7))) 4317 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4318 if (len >= 8) { 4319 connector->latency_present[0] = db[8] >> 7; 4320 connector->latency_present[1] = (db[8] >> 6) & 1; 4321 } 4322 if (len >= 9) 4323 connector->video_latency[0] = db[9]; 4324 if (len >= 10) 4325 connector->audio_latency[0] = db[10]; 4326 if (len >= 11) 4327 connector->video_latency[1] = db[11]; 4328 if (len >= 12) 4329 connector->audio_latency[1] = db[12]; 4330 4331 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4332 "video latency %d %d, " 4333 "audio latency %d %d\n", 4334 connector->latency_present[0], 4335 connector->latency_present[1], 4336 connector->video_latency[0], 4337 connector->video_latency[1], 4338 connector->audio_latency[0], 4339 connector->audio_latency[1]); 4340 } 4341 4342 static void 4343 monitor_name(struct detailed_timing *t, void *data) 4344 { 4345 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4346 return; 4347 4348 *(u8 **)data = t->data.other_data.data.str.str; 4349 } 4350 4351 static int get_monitor_name(struct edid *edid, char name[13]) 4352 { 4353 char *edid_name = NULL; 4354 int mnl; 4355 4356 if (!edid || !name) 4357 return 0; 4358 4359 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4360 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4361 if (edid_name[mnl] == 0x0a) 4362 break; 4363 4364 name[mnl] = edid_name[mnl]; 4365 } 4366 4367 return mnl; 4368 } 4369 4370 /** 4371 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4372 * @edid: monitor EDID information 4373 * @name: pointer to a character array to hold the name of the monitor 4374 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4375 * 4376 */ 4377 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4378 { 4379 int name_length; 4380 char buf[13]; 4381 4382 if (bufsize <= 0) 4383 return; 4384 4385 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4386 memcpy(name, buf, name_length); 4387 name[name_length] = '\0'; 4388 } 4389 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4390 4391 static void clear_eld(struct drm_connector *connector) 4392 { 4393 memset(connector->eld, 0, sizeof(connector->eld)); 4394 4395 connector->latency_present[0] = false; 4396 connector->latency_present[1] = false; 4397 connector->video_latency[0] = 0; 4398 connector->audio_latency[0] = 0; 4399 connector->video_latency[1] = 0; 4400 connector->audio_latency[1] = 0; 4401 } 4402 4403 /* 4404 * drm_edid_to_eld - build ELD from EDID 4405 * @connector: connector corresponding to the HDMI/DP sink 4406 * @edid: EDID to parse 4407 * 4408 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4409 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4410 */ 4411 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4412 { 4413 uint8_t *eld = connector->eld; 4414 u8 *cea; 4415 u8 *db; 4416 int total_sad_count = 0; 4417 int mnl; 4418 int dbl; 4419 4420 clear_eld(connector); 4421 4422 if (!edid) 4423 return; 4424 4425 cea = drm_find_cea_extension(edid); 4426 if (!cea) { 4427 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4428 return; 4429 } 4430 4431 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4432 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4433 4434 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4435 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4436 4437 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4438 4439 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4440 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4441 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4442 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4443 4444 if (cea_revision(cea) >= 3) { 4445 int i, start, end; 4446 int sad_count; 4447 4448 if (cea_db_offsets(cea, &start, &end)) { 4449 start = 0; 4450 end = 0; 4451 } 4452 4453 for_each_cea_db(cea, i, start, end) { 4454 db = &cea[i]; 4455 dbl = cea_db_payload_len(db); 4456 4457 switch (cea_db_tag(db)) { 4458 case AUDIO_BLOCK: 4459 /* Audio Data Block, contains SADs */ 4460 sad_count = min(dbl / 3, 15 - total_sad_count); 4461 if (sad_count >= 1) 4462 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4463 &db[1], sad_count * 3); 4464 total_sad_count += sad_count; 4465 break; 4466 case SPEAKER_BLOCK: 4467 /* Speaker Allocation Data Block */ 4468 if (dbl >= 1) 4469 eld[DRM_ELD_SPEAKER] = db[1]; 4470 break; 4471 case VENDOR_BLOCK: 4472 /* HDMI Vendor-Specific Data Block */ 4473 if (cea_db_is_hdmi_vsdb(db)) 4474 drm_parse_hdmi_vsdb_audio(connector, db); 4475 break; 4476 default: 4477 break; 4478 } 4479 } 4480 } 4481 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4482 4483 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4484 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4485 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4486 else 4487 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4488 4489 eld[DRM_ELD_BASELINE_ELD_LEN] = 4490 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4491 4492 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4493 drm_eld_size(eld), total_sad_count); 4494 } 4495 4496 /** 4497 * drm_edid_to_sad - extracts SADs from EDID 4498 * @edid: EDID to parse 4499 * @sads: pointer that will be set to the extracted SADs 4500 * 4501 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4502 * 4503 * Note: The returned pointer needs to be freed using kfree(). 4504 * 4505 * Return: The number of found SADs or negative number on error. 4506 */ 4507 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4508 { 4509 int count = 0; 4510 int i, start, end, dbl; 4511 u8 *cea; 4512 4513 cea = drm_find_cea_extension(edid); 4514 if (!cea) { 4515 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4516 return 0; 4517 } 4518 4519 if (cea_revision(cea) < 3) { 4520 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4521 return 0; 4522 } 4523 4524 if (cea_db_offsets(cea, &start, &end)) { 4525 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4526 return -EPROTO; 4527 } 4528 4529 for_each_cea_db(cea, i, start, end) { 4530 u8 *db = &cea[i]; 4531 4532 if (cea_db_tag(db) == AUDIO_BLOCK) { 4533 int j; 4534 dbl = cea_db_payload_len(db); 4535 4536 count = dbl / 3; /* SAD is 3B */ 4537 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4538 if (!*sads) 4539 return -ENOMEM; 4540 for (j = 0; j < count; j++) { 4541 u8 *sad = &db[1 + j * 3]; 4542 4543 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4544 (*sads)[j].channels = sad[0] & 0x7; 4545 (*sads)[j].freq = sad[1] & 0x7F; 4546 (*sads)[j].byte2 = sad[2]; 4547 } 4548 break; 4549 } 4550 } 4551 4552 return count; 4553 } 4554 EXPORT_SYMBOL(drm_edid_to_sad); 4555 4556 /** 4557 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4558 * @edid: EDID to parse 4559 * @sadb: pointer to the speaker block 4560 * 4561 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4562 * 4563 * Note: The returned pointer needs to be freed using kfree(). 4564 * 4565 * Return: The number of found Speaker Allocation Blocks or negative number on 4566 * error. 4567 */ 4568 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4569 { 4570 int count = 0; 4571 int i, start, end, dbl; 4572 const u8 *cea; 4573 4574 cea = drm_find_cea_extension(edid); 4575 if (!cea) { 4576 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4577 return 0; 4578 } 4579 4580 if (cea_revision(cea) < 3) { 4581 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4582 return 0; 4583 } 4584 4585 if (cea_db_offsets(cea, &start, &end)) { 4586 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4587 return -EPROTO; 4588 } 4589 4590 for_each_cea_db(cea, i, start, end) { 4591 const u8 *db = &cea[i]; 4592 4593 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4594 dbl = cea_db_payload_len(db); 4595 4596 /* Speaker Allocation Data Block */ 4597 if (dbl == 3) { 4598 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4599 if (!*sadb) 4600 return -ENOMEM; 4601 count = dbl; 4602 break; 4603 } 4604 } 4605 } 4606 4607 return count; 4608 } 4609 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4610 4611 /** 4612 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4613 * @connector: connector associated with the HDMI/DP sink 4614 * @mode: the display mode 4615 * 4616 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4617 * the sink doesn't support audio or video. 4618 */ 4619 int drm_av_sync_delay(struct drm_connector *connector, 4620 const struct drm_display_mode *mode) 4621 { 4622 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4623 int a, v; 4624 4625 if (!connector->latency_present[0]) 4626 return 0; 4627 if (!connector->latency_present[1]) 4628 i = 0; 4629 4630 a = connector->audio_latency[i]; 4631 v = connector->video_latency[i]; 4632 4633 /* 4634 * HDMI/DP sink doesn't support audio or video? 4635 */ 4636 if (a == 255 || v == 255) 4637 return 0; 4638 4639 /* 4640 * Convert raw EDID values to millisecond. 4641 * Treat unknown latency as 0ms. 4642 */ 4643 if (a) 4644 a = min(2 * (a - 1), 500); 4645 if (v) 4646 v = min(2 * (v - 1), 500); 4647 4648 return max(v - a, 0); 4649 } 4650 EXPORT_SYMBOL(drm_av_sync_delay); 4651 4652 /** 4653 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4654 * @edid: monitor EDID information 4655 * 4656 * Parse the CEA extension according to CEA-861-B. 4657 * 4658 * Drivers that have added the modes parsed from EDID to drm_display_info 4659 * should use &drm_display_info.is_hdmi instead of calling this function. 4660 * 4661 * Return: True if the monitor is HDMI, false if not or unknown. 4662 */ 4663 bool drm_detect_hdmi_monitor(struct edid *edid) 4664 { 4665 u8 *edid_ext; 4666 int i; 4667 int start_offset, end_offset; 4668 4669 edid_ext = drm_find_cea_extension(edid); 4670 if (!edid_ext) 4671 return false; 4672 4673 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4674 return false; 4675 4676 /* 4677 * Because HDMI identifier is in Vendor Specific Block, 4678 * search it from all data blocks of CEA extension. 4679 */ 4680 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4681 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4682 return true; 4683 } 4684 4685 return false; 4686 } 4687 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4688 4689 /** 4690 * drm_detect_monitor_audio - check monitor audio capability 4691 * @edid: EDID block to scan 4692 * 4693 * Monitor should have CEA extension block. 4694 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4695 * audio' only. If there is any audio extension block and supported 4696 * audio format, assume at least 'basic audio' support, even if 'basic 4697 * audio' is not defined in EDID. 4698 * 4699 * Return: True if the monitor supports audio, false otherwise. 4700 */ 4701 bool drm_detect_monitor_audio(struct edid *edid) 4702 { 4703 u8 *edid_ext; 4704 int i, j; 4705 bool has_audio = false; 4706 int start_offset, end_offset; 4707 4708 edid_ext = drm_find_cea_extension(edid); 4709 if (!edid_ext) 4710 goto end; 4711 4712 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4713 4714 if (has_audio) { 4715 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4716 goto end; 4717 } 4718 4719 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4720 goto end; 4721 4722 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4723 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4724 has_audio = true; 4725 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4726 DRM_DEBUG_KMS("CEA audio format %d\n", 4727 (edid_ext[i + j] >> 3) & 0xf); 4728 goto end; 4729 } 4730 } 4731 end: 4732 return has_audio; 4733 } 4734 EXPORT_SYMBOL(drm_detect_monitor_audio); 4735 4736 4737 /** 4738 * drm_default_rgb_quant_range - default RGB quantization range 4739 * @mode: display mode 4740 * 4741 * Determine the default RGB quantization range for the mode, 4742 * as specified in CEA-861. 4743 * 4744 * Return: The default RGB quantization range for the mode 4745 */ 4746 enum hdmi_quantization_range 4747 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4748 { 4749 /* All CEA modes other than VIC 1 use limited quantization range. */ 4750 return drm_match_cea_mode(mode) > 1 ? 4751 HDMI_QUANTIZATION_RANGE_LIMITED : 4752 HDMI_QUANTIZATION_RANGE_FULL; 4753 } 4754 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4755 4756 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4757 { 4758 struct drm_display_info *info = &connector->display_info; 4759 4760 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4761 4762 if (db[2] & EDID_CEA_VCDB_QS) 4763 info->rgb_quant_range_selectable = true; 4764 } 4765 4766 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4767 const u8 *db) 4768 { 4769 u8 dc_mask; 4770 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4771 4772 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4773 hdmi->y420_dc_modes = dc_mask; 4774 } 4775 4776 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4777 const u8 *hf_vsdb) 4778 { 4779 struct drm_display_info *display = &connector->display_info; 4780 struct drm_hdmi_info *hdmi = &display->hdmi; 4781 4782 display->has_hdmi_infoframe = true; 4783 4784 if (hf_vsdb[6] & 0x80) { 4785 hdmi->scdc.supported = true; 4786 if (hf_vsdb[6] & 0x40) 4787 hdmi->scdc.read_request = true; 4788 } 4789 4790 /* 4791 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4792 * And as per the spec, three factors confirm this: 4793 * * Availability of a HF-VSDB block in EDID (check) 4794 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4795 * * SCDC support available (let's check) 4796 * Lets check it out. 4797 */ 4798 4799 if (hf_vsdb[5]) { 4800 /* max clock is 5000 KHz times block value */ 4801 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4802 struct drm_scdc *scdc = &hdmi->scdc; 4803 4804 if (max_tmds_clock > 340000) { 4805 display->max_tmds_clock = max_tmds_clock; 4806 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4807 display->max_tmds_clock); 4808 } 4809 4810 if (scdc->supported) { 4811 scdc->scrambling.supported = true; 4812 4813 /* Few sinks support scrambling for clocks < 340M */ 4814 if ((hf_vsdb[6] & 0x8)) 4815 scdc->scrambling.low_rates = true; 4816 } 4817 } 4818 4819 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4820 } 4821 4822 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4823 const u8 *hdmi) 4824 { 4825 struct drm_display_info *info = &connector->display_info; 4826 unsigned int dc_bpc = 0; 4827 4828 /* HDMI supports at least 8 bpc */ 4829 info->bpc = 8; 4830 4831 if (cea_db_payload_len(hdmi) < 6) 4832 return; 4833 4834 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4835 dc_bpc = 10; 4836 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4837 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4838 connector->name); 4839 } 4840 4841 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4842 dc_bpc = 12; 4843 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4844 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4845 connector->name); 4846 } 4847 4848 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4849 dc_bpc = 16; 4850 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4851 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4852 connector->name); 4853 } 4854 4855 if (dc_bpc == 0) { 4856 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4857 connector->name); 4858 return; 4859 } 4860 4861 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4862 connector->name, dc_bpc); 4863 info->bpc = dc_bpc; 4864 4865 /* 4866 * Deep color support mandates RGB444 support for all video 4867 * modes and forbids YCRCB422 support for all video modes per 4868 * HDMI 1.3 spec. 4869 */ 4870 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4871 4872 /* YCRCB444 is optional according to spec. */ 4873 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4874 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4875 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4876 connector->name); 4877 } 4878 4879 /* 4880 * Spec says that if any deep color mode is supported at all, 4881 * then deep color 36 bit must be supported. 4882 */ 4883 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4884 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4885 connector->name); 4886 } 4887 } 4888 4889 static void 4890 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4891 { 4892 struct drm_display_info *info = &connector->display_info; 4893 u8 len = cea_db_payload_len(db); 4894 4895 info->is_hdmi = true; 4896 4897 if (len >= 6) 4898 info->dvi_dual = db[6] & 1; 4899 if (len >= 7) 4900 info->max_tmds_clock = db[7] * 5000; 4901 4902 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4903 "max TMDS clock %d kHz\n", 4904 info->dvi_dual, 4905 info->max_tmds_clock); 4906 4907 drm_parse_hdmi_deep_color_info(connector, db); 4908 } 4909 4910 static void drm_parse_cea_ext(struct drm_connector *connector, 4911 const struct edid *edid) 4912 { 4913 struct drm_display_info *info = &connector->display_info; 4914 const u8 *edid_ext; 4915 int i, start, end; 4916 4917 edid_ext = drm_find_cea_extension(edid); 4918 if (!edid_ext) 4919 return; 4920 4921 info->cea_rev = edid_ext[1]; 4922 4923 /* The existence of a CEA block should imply RGB support */ 4924 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4925 if (edid_ext[3] & EDID_CEA_YCRCB444) 4926 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4927 if (edid_ext[3] & EDID_CEA_YCRCB422) 4928 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4929 4930 if (cea_db_offsets(edid_ext, &start, &end)) 4931 return; 4932 4933 for_each_cea_db(edid_ext, i, start, end) { 4934 const u8 *db = &edid_ext[i]; 4935 4936 if (cea_db_is_hdmi_vsdb(db)) 4937 drm_parse_hdmi_vsdb_video(connector, db); 4938 if (cea_db_is_hdmi_forum_vsdb(db)) 4939 drm_parse_hdmi_forum_vsdb(connector, db); 4940 if (cea_db_is_y420cmdb(db)) 4941 drm_parse_y420cmdb_bitmap(connector, db); 4942 if (cea_db_is_vcdb(db)) 4943 drm_parse_vcdb(connector, db); 4944 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4945 drm_parse_hdr_metadata_block(connector, db); 4946 } 4947 } 4948 4949 static 4950 void get_monitor_range(struct detailed_timing *timing, 4951 void *info_monitor_range) 4952 { 4953 struct drm_monitor_range_info *monitor_range = info_monitor_range; 4954 const struct detailed_non_pixel *data = &timing->data.other_data; 4955 const struct detailed_data_monitor_range *range = &data->data.range; 4956 4957 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 4958 return; 4959 4960 /* 4961 * Check for flag range limits only. If flag == 1 then 4962 * no additional timing information provided. 4963 * Default GTF, GTF Secondary curve and CVT are not 4964 * supported 4965 */ 4966 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 4967 return; 4968 4969 monitor_range->min_vfreq = range->min_vfreq; 4970 monitor_range->max_vfreq = range->max_vfreq; 4971 } 4972 4973 static 4974 void drm_get_monitor_range(struct drm_connector *connector, 4975 const struct edid *edid) 4976 { 4977 struct drm_display_info *info = &connector->display_info; 4978 4979 if (!version_greater(edid, 1, 1)) 4980 return; 4981 4982 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 4983 &info->monitor_range); 4984 4985 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 4986 info->monitor_range.min_vfreq, 4987 info->monitor_range.max_vfreq); 4988 } 4989 4990 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4991 * all of the values which would have been set from EDID 4992 */ 4993 void 4994 drm_reset_display_info(struct drm_connector *connector) 4995 { 4996 struct drm_display_info *info = &connector->display_info; 4997 4998 info->width_mm = 0; 4999 info->height_mm = 0; 5000 5001 info->bpc = 0; 5002 info->color_formats = 0; 5003 info->cea_rev = 0; 5004 info->max_tmds_clock = 0; 5005 info->dvi_dual = false; 5006 info->is_hdmi = false; 5007 info->has_hdmi_infoframe = false; 5008 info->rgb_quant_range_selectable = false; 5009 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5010 5011 info->non_desktop = 0; 5012 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5013 } 5014 5015 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5016 { 5017 struct drm_display_info *info = &connector->display_info; 5018 5019 u32 quirks = edid_get_quirks(edid); 5020 5021 drm_reset_display_info(connector); 5022 5023 info->width_mm = edid->width_cm * 10; 5024 info->height_mm = edid->height_cm * 10; 5025 5026 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5027 5028 drm_get_monitor_range(connector, edid); 5029 5030 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5031 5032 if (edid->revision < 3) 5033 return quirks; 5034 5035 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5036 return quirks; 5037 5038 drm_parse_cea_ext(connector, edid); 5039 5040 /* 5041 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5042 * 5043 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5044 * tells us to assume 8 bpc color depth if the EDID doesn't have 5045 * extensions which tell otherwise. 5046 */ 5047 if (info->bpc == 0 && edid->revision == 3 && 5048 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5049 info->bpc = 8; 5050 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5051 connector->name, info->bpc); 5052 } 5053 5054 /* Only defined for 1.4 with digital displays */ 5055 if (edid->revision < 4) 5056 return quirks; 5057 5058 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5059 case DRM_EDID_DIGITAL_DEPTH_6: 5060 info->bpc = 6; 5061 break; 5062 case DRM_EDID_DIGITAL_DEPTH_8: 5063 info->bpc = 8; 5064 break; 5065 case DRM_EDID_DIGITAL_DEPTH_10: 5066 info->bpc = 10; 5067 break; 5068 case DRM_EDID_DIGITAL_DEPTH_12: 5069 info->bpc = 12; 5070 break; 5071 case DRM_EDID_DIGITAL_DEPTH_14: 5072 info->bpc = 14; 5073 break; 5074 case DRM_EDID_DIGITAL_DEPTH_16: 5075 info->bpc = 16; 5076 break; 5077 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5078 default: 5079 info->bpc = 0; 5080 break; 5081 } 5082 5083 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5084 connector->name, info->bpc); 5085 5086 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5087 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5088 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5089 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5090 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5091 return quirks; 5092 } 5093 5094 static int validate_displayid(u8 *displayid, int length, int idx) 5095 { 5096 int i, dispid_length; 5097 u8 csum = 0; 5098 struct displayid_hdr *base; 5099 5100 base = (struct displayid_hdr *)&displayid[idx]; 5101 5102 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5103 base->rev, base->bytes, base->prod_id, base->ext_count); 5104 5105 /* +1 for DispID checksum */ 5106 dispid_length = sizeof(*base) + base->bytes + 1; 5107 if (dispid_length > length - idx) 5108 return -EINVAL; 5109 5110 for (i = 0; i < dispid_length; i++) 5111 csum += displayid[idx + i]; 5112 if (csum) { 5113 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5114 return -EINVAL; 5115 } 5116 5117 return 0; 5118 } 5119 5120 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5121 struct displayid_detailed_timings_1 *timings) 5122 { 5123 struct drm_display_mode *mode; 5124 unsigned pixel_clock = (timings->pixel_clock[0] | 5125 (timings->pixel_clock[1] << 8) | 5126 (timings->pixel_clock[2] << 16)); 5127 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5128 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5129 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5130 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5131 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5132 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5133 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5134 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5135 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5136 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5137 mode = drm_mode_create(dev); 5138 if (!mode) 5139 return NULL; 5140 5141 mode->clock = pixel_clock * 10; 5142 mode->hdisplay = hactive; 5143 mode->hsync_start = mode->hdisplay + hsync; 5144 mode->hsync_end = mode->hsync_start + hsync_width; 5145 mode->htotal = mode->hdisplay + hblank; 5146 5147 mode->vdisplay = vactive; 5148 mode->vsync_start = mode->vdisplay + vsync; 5149 mode->vsync_end = mode->vsync_start + vsync_width; 5150 mode->vtotal = mode->vdisplay + vblank; 5151 5152 mode->flags = 0; 5153 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5154 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5155 mode->type = DRM_MODE_TYPE_DRIVER; 5156 5157 if (timings->flags & 0x80) 5158 mode->type |= DRM_MODE_TYPE_PREFERRED; 5159 drm_mode_set_name(mode); 5160 5161 return mode; 5162 } 5163 5164 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5165 struct displayid_block *block) 5166 { 5167 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5168 int i; 5169 int num_timings; 5170 struct drm_display_mode *newmode; 5171 int num_modes = 0; 5172 /* blocks must be multiple of 20 bytes length */ 5173 if (block->num_bytes % 20) 5174 return 0; 5175 5176 num_timings = block->num_bytes / 20; 5177 for (i = 0; i < num_timings; i++) { 5178 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5179 5180 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5181 if (!newmode) 5182 continue; 5183 5184 drm_mode_probed_add(connector, newmode); 5185 num_modes++; 5186 } 5187 return num_modes; 5188 } 5189 5190 static int add_displayid_detailed_modes(struct drm_connector *connector, 5191 struct edid *edid) 5192 { 5193 u8 *displayid; 5194 int length, idx; 5195 struct displayid_block *block; 5196 int num_modes = 0; 5197 5198 displayid = drm_find_displayid_extension(edid, &length, &idx); 5199 if (!displayid) 5200 return 0; 5201 5202 idx += sizeof(struct displayid_hdr); 5203 for_each_displayid_db(displayid, block, idx, length) { 5204 switch (block->tag) { 5205 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5206 num_modes += add_displayid_detailed_1_modes(connector, block); 5207 break; 5208 } 5209 } 5210 return num_modes; 5211 } 5212 5213 /** 5214 * drm_add_edid_modes - add modes from EDID data, if available 5215 * @connector: connector we're probing 5216 * @edid: EDID data 5217 * 5218 * Add the specified modes to the connector's mode list. Also fills out the 5219 * &drm_display_info structure and ELD in @connector with any information which 5220 * can be derived from the edid. 5221 * 5222 * Return: The number of modes added or 0 if we couldn't find any. 5223 */ 5224 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5225 { 5226 int num_modes = 0; 5227 u32 quirks; 5228 5229 if (edid == NULL) { 5230 clear_eld(connector); 5231 return 0; 5232 } 5233 if (!drm_edid_is_valid(edid)) { 5234 clear_eld(connector); 5235 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5236 connector->name); 5237 return 0; 5238 } 5239 5240 drm_edid_to_eld(connector, edid); 5241 5242 /* 5243 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5244 * To avoid multiple parsing of same block, lets parse that map 5245 * from sink info, before parsing CEA modes. 5246 */ 5247 quirks = drm_add_display_info(connector, edid); 5248 5249 /* 5250 * EDID spec says modes should be preferred in this order: 5251 * - preferred detailed mode 5252 * - other detailed modes from base block 5253 * - detailed modes from extension blocks 5254 * - CVT 3-byte code modes 5255 * - standard timing codes 5256 * - established timing codes 5257 * - modes inferred from GTF or CVT range information 5258 * 5259 * We get this pretty much right. 5260 * 5261 * XXX order for additional mode types in extension blocks? 5262 */ 5263 num_modes += add_detailed_modes(connector, edid, quirks); 5264 num_modes += add_cvt_modes(connector, edid); 5265 num_modes += add_standard_modes(connector, edid); 5266 num_modes += add_established_modes(connector, edid); 5267 num_modes += add_cea_modes(connector, edid); 5268 num_modes += add_alternate_cea_modes(connector, edid); 5269 num_modes += add_displayid_detailed_modes(connector, edid); 5270 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5271 num_modes += add_inferred_modes(connector, edid); 5272 5273 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5274 edid_fixup_preferred(connector, quirks); 5275 5276 if (quirks & EDID_QUIRK_FORCE_6BPC) 5277 connector->display_info.bpc = 6; 5278 5279 if (quirks & EDID_QUIRK_FORCE_8BPC) 5280 connector->display_info.bpc = 8; 5281 5282 if (quirks & EDID_QUIRK_FORCE_10BPC) 5283 connector->display_info.bpc = 10; 5284 5285 if (quirks & EDID_QUIRK_FORCE_12BPC) 5286 connector->display_info.bpc = 12; 5287 5288 return num_modes; 5289 } 5290 EXPORT_SYMBOL(drm_add_edid_modes); 5291 5292 /** 5293 * drm_add_modes_noedid - add modes for the connectors without EDID 5294 * @connector: connector we're probing 5295 * @hdisplay: the horizontal display limit 5296 * @vdisplay: the vertical display limit 5297 * 5298 * Add the specified modes to the connector's mode list. Only when the 5299 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5300 * 5301 * Return: The number of modes added or 0 if we couldn't find any. 5302 */ 5303 int drm_add_modes_noedid(struct drm_connector *connector, 5304 int hdisplay, int vdisplay) 5305 { 5306 int i, count, num_modes = 0; 5307 struct drm_display_mode *mode; 5308 struct drm_device *dev = connector->dev; 5309 5310 count = ARRAY_SIZE(drm_dmt_modes); 5311 if (hdisplay < 0) 5312 hdisplay = 0; 5313 if (vdisplay < 0) 5314 vdisplay = 0; 5315 5316 for (i = 0; i < count; i++) { 5317 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5318 if (hdisplay && vdisplay) { 5319 /* 5320 * Only when two are valid, they will be used to check 5321 * whether the mode should be added to the mode list of 5322 * the connector. 5323 */ 5324 if (ptr->hdisplay > hdisplay || 5325 ptr->vdisplay > vdisplay) 5326 continue; 5327 } 5328 if (drm_mode_vrefresh(ptr) > 61) 5329 continue; 5330 mode = drm_mode_duplicate(dev, ptr); 5331 if (mode) { 5332 drm_mode_probed_add(connector, mode); 5333 num_modes++; 5334 } 5335 } 5336 return num_modes; 5337 } 5338 EXPORT_SYMBOL(drm_add_modes_noedid); 5339 5340 /** 5341 * drm_set_preferred_mode - Sets the preferred mode of a connector 5342 * @connector: connector whose mode list should be processed 5343 * @hpref: horizontal resolution of preferred mode 5344 * @vpref: vertical resolution of preferred mode 5345 * 5346 * Marks a mode as preferred if it matches the resolution specified by @hpref 5347 * and @vpref. 5348 */ 5349 void drm_set_preferred_mode(struct drm_connector *connector, 5350 int hpref, int vpref) 5351 { 5352 struct drm_display_mode *mode; 5353 5354 list_for_each_entry(mode, &connector->probed_modes, head) { 5355 if (mode->hdisplay == hpref && 5356 mode->vdisplay == vpref) 5357 mode->type |= DRM_MODE_TYPE_PREFERRED; 5358 } 5359 } 5360 EXPORT_SYMBOL(drm_set_preferred_mode); 5361 5362 static bool is_hdmi2_sink(struct drm_connector *connector) 5363 { 5364 /* 5365 * FIXME: sil-sii8620 doesn't have a connector around when 5366 * we need one, so we have to be prepared for a NULL connector. 5367 */ 5368 if (!connector) 5369 return true; 5370 5371 return connector->display_info.hdmi.scdc.supported || 5372 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5373 } 5374 5375 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5376 { 5377 return sink_eotf & BIT(output_eotf); 5378 } 5379 5380 /** 5381 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5382 * HDR metadata from userspace 5383 * @frame: HDMI DRM infoframe 5384 * @conn_state: Connector state containing HDR metadata 5385 * 5386 * Return: 0 on success or a negative error code on failure. 5387 */ 5388 int 5389 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5390 const struct drm_connector_state *conn_state) 5391 { 5392 struct drm_connector *connector; 5393 struct hdr_output_metadata *hdr_metadata; 5394 int err; 5395 5396 if (!frame || !conn_state) 5397 return -EINVAL; 5398 5399 connector = conn_state->connector; 5400 5401 if (!conn_state->hdr_output_metadata) 5402 return -EINVAL; 5403 5404 hdr_metadata = conn_state->hdr_output_metadata->data; 5405 5406 if (!hdr_metadata || !connector) 5407 return -EINVAL; 5408 5409 /* Sink EOTF is Bit map while infoframe is absolute values */ 5410 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5411 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5412 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5413 return -EINVAL; 5414 } 5415 5416 err = hdmi_drm_infoframe_init(frame); 5417 if (err < 0) 5418 return err; 5419 5420 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5421 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5422 5423 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5424 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5425 BUILD_BUG_ON(sizeof(frame->white_point) != 5426 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5427 5428 memcpy(&frame->display_primaries, 5429 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5430 sizeof(frame->display_primaries)); 5431 5432 memcpy(&frame->white_point, 5433 &hdr_metadata->hdmi_metadata_type1.white_point, 5434 sizeof(frame->white_point)); 5435 5436 frame->max_display_mastering_luminance = 5437 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5438 frame->min_display_mastering_luminance = 5439 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5440 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5441 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5442 5443 return 0; 5444 } 5445 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5446 5447 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5448 const struct drm_display_mode *mode) 5449 { 5450 bool has_hdmi_infoframe = connector ? 5451 connector->display_info.has_hdmi_infoframe : false; 5452 5453 if (!has_hdmi_infoframe) 5454 return 0; 5455 5456 /* No HDMI VIC when signalling 3D video format */ 5457 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5458 return 0; 5459 5460 return drm_match_hdmi_mode(mode); 5461 } 5462 5463 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5464 const struct drm_display_mode *mode) 5465 { 5466 u8 vic; 5467 5468 /* 5469 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5470 * we should send its VIC in vendor infoframes, else send the 5471 * VIC in AVI infoframes. Lets check if this mode is present in 5472 * HDMI 1.4b 4K modes 5473 */ 5474 if (drm_mode_hdmi_vic(connector, mode)) 5475 return 0; 5476 5477 vic = drm_match_cea_mode(mode); 5478 5479 /* 5480 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5481 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5482 * have to make sure we dont break HDMI 1.4 sinks. 5483 */ 5484 if (!is_hdmi2_sink(connector) && vic > 64) 5485 return 0; 5486 5487 return vic; 5488 } 5489 5490 /** 5491 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5492 * data from a DRM display mode 5493 * @frame: HDMI AVI infoframe 5494 * @connector: the connector 5495 * @mode: DRM display mode 5496 * 5497 * Return: 0 on success or a negative error code on failure. 5498 */ 5499 int 5500 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5501 struct drm_connector *connector, 5502 const struct drm_display_mode *mode) 5503 { 5504 enum hdmi_picture_aspect picture_aspect; 5505 u8 vic, hdmi_vic; 5506 5507 if (!frame || !mode) 5508 return -EINVAL; 5509 5510 hdmi_avi_infoframe_init(frame); 5511 5512 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5513 frame->pixel_repeat = 1; 5514 5515 vic = drm_mode_cea_vic(connector, mode); 5516 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5517 5518 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5519 5520 /* 5521 * As some drivers don't support atomic, we can't use connector state. 5522 * So just initialize the frame with default values, just the same way 5523 * as it's done with other properties here. 5524 */ 5525 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5526 frame->itc = 0; 5527 5528 /* 5529 * Populate picture aspect ratio from either 5530 * user input (if specified) or from the CEA/HDMI mode lists. 5531 */ 5532 picture_aspect = mode->picture_aspect_ratio; 5533 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5534 if (vic) 5535 picture_aspect = drm_get_cea_aspect_ratio(vic); 5536 else if (hdmi_vic) 5537 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5538 } 5539 5540 /* 5541 * The infoframe can't convey anything but none, 4:3 5542 * and 16:9, so if the user has asked for anything else 5543 * we can only satisfy it by specifying the right VIC. 5544 */ 5545 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5546 if (vic) { 5547 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5548 return -EINVAL; 5549 } else if (hdmi_vic) { 5550 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5551 return -EINVAL; 5552 } else { 5553 return -EINVAL; 5554 } 5555 5556 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5557 } 5558 5559 frame->video_code = vic; 5560 frame->picture_aspect = picture_aspect; 5561 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5562 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5563 5564 return 0; 5565 } 5566 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5567 5568 /* HDMI Colorspace Spec Definitions */ 5569 #define FULL_COLORIMETRY_MASK 0x1FF 5570 #define NORMAL_COLORIMETRY_MASK 0x3 5571 #define EXTENDED_COLORIMETRY_MASK 0x7 5572 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5573 5574 #define C(x) ((x) << 0) 5575 #define EC(x) ((x) << 2) 5576 #define ACE(x) ((x) << 5) 5577 5578 #define HDMI_COLORIMETRY_NO_DATA 0x0 5579 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5580 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5581 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5582 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5583 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5584 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5585 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5586 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5587 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5588 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5589 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5590 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5591 5592 static const u32 hdmi_colorimetry_val[] = { 5593 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5594 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5595 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5596 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5597 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5598 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5599 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5600 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5601 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5602 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5603 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5604 }; 5605 5606 #undef C 5607 #undef EC 5608 #undef ACE 5609 5610 /** 5611 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5612 * colorspace information 5613 * @frame: HDMI AVI infoframe 5614 * @conn_state: connector state 5615 */ 5616 void 5617 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5618 const struct drm_connector_state *conn_state) 5619 { 5620 u32 colorimetry_val; 5621 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5622 5623 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5624 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5625 else 5626 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5627 5628 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5629 /* 5630 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5631 * structure and extend it in drivers/video/hdmi 5632 */ 5633 frame->extended_colorimetry = (colorimetry_val >> 2) & 5634 EXTENDED_COLORIMETRY_MASK; 5635 } 5636 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5637 5638 /** 5639 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5640 * quantization range information 5641 * @frame: HDMI AVI infoframe 5642 * @connector: the connector 5643 * @mode: DRM display mode 5644 * @rgb_quant_range: RGB quantization range (Q) 5645 */ 5646 void 5647 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5648 struct drm_connector *connector, 5649 const struct drm_display_mode *mode, 5650 enum hdmi_quantization_range rgb_quant_range) 5651 { 5652 const struct drm_display_info *info = &connector->display_info; 5653 5654 /* 5655 * CEA-861: 5656 * "A Source shall not send a non-zero Q value that does not correspond 5657 * to the default RGB Quantization Range for the transmitted Picture 5658 * unless the Sink indicates support for the Q bit in a Video 5659 * Capabilities Data Block." 5660 * 5661 * HDMI 2.0 recommends sending non-zero Q when it does match the 5662 * default RGB quantization range for the mode, even when QS=0. 5663 */ 5664 if (info->rgb_quant_range_selectable || 5665 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5666 frame->quantization_range = rgb_quant_range; 5667 else 5668 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5669 5670 /* 5671 * CEA-861-F: 5672 * "When transmitting any RGB colorimetry, the Source should set the 5673 * YQ-field to match the RGB Quantization Range being transmitted 5674 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5675 * set YQ=1) and the Sink shall ignore the YQ-field." 5676 * 5677 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5678 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5679 * good way to tell which version of CEA-861 the sink supports, so 5680 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5681 * on on CEA-861-F. 5682 */ 5683 if (!is_hdmi2_sink(connector) || 5684 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5685 frame->ycc_quantization_range = 5686 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5687 else 5688 frame->ycc_quantization_range = 5689 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5690 } 5691 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5692 5693 /** 5694 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5695 * bar information 5696 * @frame: HDMI AVI infoframe 5697 * @conn_state: connector state 5698 */ 5699 void 5700 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5701 const struct drm_connector_state *conn_state) 5702 { 5703 frame->right_bar = conn_state->tv.margins.right; 5704 frame->left_bar = conn_state->tv.margins.left; 5705 frame->top_bar = conn_state->tv.margins.top; 5706 frame->bottom_bar = conn_state->tv.margins.bottom; 5707 } 5708 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5709 5710 static enum hdmi_3d_structure 5711 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5712 { 5713 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5714 5715 switch (layout) { 5716 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5717 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5718 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5719 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5720 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5721 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5722 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5723 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5724 case DRM_MODE_FLAG_3D_L_DEPTH: 5725 return HDMI_3D_STRUCTURE_L_DEPTH; 5726 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5727 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5728 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5729 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5730 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5731 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5732 default: 5733 return HDMI_3D_STRUCTURE_INVALID; 5734 } 5735 } 5736 5737 /** 5738 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5739 * data from a DRM display mode 5740 * @frame: HDMI vendor infoframe 5741 * @connector: the connector 5742 * @mode: DRM display mode 5743 * 5744 * Note that there's is a need to send HDMI vendor infoframes only when using a 5745 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5746 * function will return -EINVAL, error that can be safely ignored. 5747 * 5748 * Return: 0 on success or a negative error code on failure. 5749 */ 5750 int 5751 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5752 struct drm_connector *connector, 5753 const struct drm_display_mode *mode) 5754 { 5755 /* 5756 * FIXME: sil-sii8620 doesn't have a connector around when 5757 * we need one, so we have to be prepared for a NULL connector. 5758 */ 5759 bool has_hdmi_infoframe = connector ? 5760 connector->display_info.has_hdmi_infoframe : false; 5761 int err; 5762 5763 if (!frame || !mode) 5764 return -EINVAL; 5765 5766 if (!has_hdmi_infoframe) 5767 return -EINVAL; 5768 5769 err = hdmi_vendor_infoframe_init(frame); 5770 if (err < 0) 5771 return err; 5772 5773 /* 5774 * Even if it's not absolutely necessary to send the infoframe 5775 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5776 * know that the sink can handle it. This is based on a 5777 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5778 * have trouble realizing that they shuld switch from 3D to 2D 5779 * mode if the source simply stops sending the infoframe when 5780 * it wants to switch from 3D to 2D. 5781 */ 5782 frame->vic = drm_mode_hdmi_vic(connector, mode); 5783 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5784 5785 return 0; 5786 } 5787 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5788 5789 static int drm_parse_tiled_block(struct drm_connector *connector, 5790 const struct displayid_block *block) 5791 { 5792 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5793 u16 w, h; 5794 u8 tile_v_loc, tile_h_loc; 5795 u8 num_v_tile, num_h_tile; 5796 struct drm_tile_group *tg; 5797 5798 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5799 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5800 5801 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5802 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5803 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5804 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5805 5806 connector->has_tile = true; 5807 if (tile->tile_cap & 0x80) 5808 connector->tile_is_single_monitor = true; 5809 5810 connector->num_h_tile = num_h_tile + 1; 5811 connector->num_v_tile = num_v_tile + 1; 5812 connector->tile_h_loc = tile_h_loc; 5813 connector->tile_v_loc = tile_v_loc; 5814 connector->tile_h_size = w + 1; 5815 connector->tile_v_size = h + 1; 5816 5817 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5818 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5819 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5820 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5821 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5822 5823 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5824 if (!tg) { 5825 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5826 } 5827 if (!tg) 5828 return -ENOMEM; 5829 5830 if (connector->tile_group != tg) { 5831 /* if we haven't got a pointer, 5832 take the reference, drop ref to old tile group */ 5833 if (connector->tile_group) { 5834 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5835 } 5836 connector->tile_group = tg; 5837 } else 5838 /* if same tile group, then release the ref we just took. */ 5839 drm_mode_put_tile_group(connector->dev, tg); 5840 return 0; 5841 } 5842 5843 static int drm_displayid_parse_tiled(struct drm_connector *connector, 5844 const u8 *displayid, int length, int idx) 5845 { 5846 const struct displayid_block *block; 5847 int ret; 5848 5849 idx += sizeof(struct displayid_hdr); 5850 for_each_displayid_db(displayid, block, idx, length) { 5851 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5852 block->tag, block->rev, block->num_bytes); 5853 5854 switch (block->tag) { 5855 case DATA_BLOCK_TILED_DISPLAY: 5856 ret = drm_parse_tiled_block(connector, block); 5857 if (ret) 5858 return ret; 5859 break; 5860 default: 5861 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5862 break; 5863 } 5864 } 5865 return 0; 5866 } 5867 5868 void drm_update_tile_info(struct drm_connector *connector, 5869 const struct edid *edid) 5870 { 5871 const void *displayid = NULL; 5872 int length, idx; 5873 int ret; 5874 5875 connector->has_tile = false; 5876 displayid = drm_find_displayid_extension(edid, &length, &idx); 5877 if (!displayid) { 5878 /* drop reference to any tile group we had */ 5879 goto out_drop_ref; 5880 } 5881 5882 ret = drm_displayid_parse_tiled(connector, displayid, length, idx); 5883 if (ret < 0) 5884 goto out_drop_ref; 5885 if (!connector->has_tile) 5886 goto out_drop_ref; 5887 return; 5888 out_drop_ref: 5889 if (connector->tile_group) { 5890 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5891 connector->tile_group = NULL; 5892 } 5893 return; 5894 } 5895