1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 #define version_greater(edid, maj, min) \ 49 (((edid)->version > (maj)) || \ 50 ((edid)->version == (maj) && (edid)->revision > (min))) 51 52 static int oui(u8 first, u8 second, u8 third) 53 { 54 return (first << 16) | (second << 8) | third; 55 } 56 57 #define EDID_EST_TIMINGS 16 58 #define EDID_STD_TIMINGS 8 59 #define EDID_DETAILED_TIMINGS 4 60 61 /* 62 * EDID blocks out in the wild have a variety of bugs, try to collect 63 * them here (note that userspace may work around broken monitors first, 64 * but fixes should make their way here so that the kernel "just works" 65 * on as many displays as possible). 66 */ 67 68 /* First detailed mode wrong, use largest 60Hz mode */ 69 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 70 /* Reported 135MHz pixel clock is too high, needs adjustment */ 71 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 72 /* Prefer the largest mode at 75 Hz */ 73 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 74 /* Detail timing is in cm not mm */ 75 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 76 /* Detailed timing descriptors have bogus size values, so just take the 77 * maximum size and use that. 78 */ 79 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 80 /* use +hsync +vsync for detailed mode */ 81 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 82 /* Force reduced-blanking timings for detailed modes */ 83 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 84 /* Force 8bpc */ 85 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 86 /* Force 12bpc */ 87 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 88 /* Force 6bpc */ 89 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 90 /* Force 10bpc */ 91 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 92 /* Non desktop display (i.e. HMD) */ 93 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 94 95 #define MICROSOFT_IEEE_OUI 0xca125c 96 97 struct detailed_mode_closure { 98 struct drm_connector *connector; 99 const struct edid *edid; 100 bool preferred; 101 u32 quirks; 102 int modes; 103 }; 104 105 #define LEVEL_DMT 0 106 #define LEVEL_GTF 1 107 #define LEVEL_GTF2 2 108 #define LEVEL_CVT 3 109 110 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 111 { \ 112 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 113 product_id), \ 114 .quirks = _quirks \ 115 } 116 117 static const struct edid_quirk { 118 u32 panel_id; 119 u32 quirks; 120 } edid_quirk_list[] = { 121 /* Acer AL1706 */ 122 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 123 /* Acer F51 */ 124 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 125 126 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 127 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 128 129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 131 132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 134 135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 137 138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 140 141 /* Belinea 10 15 55 */ 142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 144 145 /* Envision Peripherals, Inc. EN-7100e */ 146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 147 /* Envision EN2028 */ 148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 149 150 /* Funai Electronics PM36B */ 151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 152 EDID_QUIRK_DETAILED_IN_CM), 153 154 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 155 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 156 157 /* LG Philips LCD LP154W01-A5 */ 158 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 159 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 160 161 /* Samsung SyncMaster 205BW. Note: irony */ 162 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 163 /* Samsung SyncMaster 22[5-6]BW */ 164 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 165 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 166 167 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 168 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 169 170 /* ViewSonic VA2026w */ 171 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 172 173 /* Medion MD 30217 PG */ 174 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 175 176 /* Lenovo G50 */ 177 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 178 179 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 180 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 181 182 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 183 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 184 185 /* Valve Index Headset */ 186 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 187 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 188 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 189 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 190 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 191 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 192 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 203 204 /* HTC Vive and Vive Pro VR Headsets */ 205 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 207 208 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 209 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 211 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 213 214 /* Windows Mixed Reality Headsets */ 215 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 221 222 /* Sony PlayStation VR Headset */ 223 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 224 225 /* Sensics VR Headsets */ 226 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 227 228 /* OSVR HDK and HDK2 VR Headsets */ 229 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 230 }; 231 232 /* 233 * Autogenerated from the DMT spec. 234 * This table is copied from xfree86/modes/xf86EdidModes.c. 235 */ 236 static const struct drm_display_mode drm_dmt_modes[] = { 237 /* 0x01 - 640x350@85Hz */ 238 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 239 736, 832, 0, 350, 382, 385, 445, 0, 240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x02 - 640x400@85Hz */ 242 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 243 736, 832, 0, 400, 401, 404, 445, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 0x03 - 720x400@85Hz */ 246 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 247 828, 936, 0, 400, 401, 404, 446, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x04 - 640x480@60Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 251 752, 800, 0, 480, 490, 492, 525, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x05 - 640x480@72Hz */ 254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 255 704, 832, 0, 480, 489, 492, 520, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 0x06 - 640x480@75Hz */ 258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 259 720, 840, 0, 480, 481, 484, 500, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x07 - 640x480@85Hz */ 262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 263 752, 832, 0, 480, 481, 484, 509, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x08 - 800x600@56Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 267 896, 1024, 0, 600, 601, 603, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x09 - 800x600@60Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 271 968, 1056, 0, 600, 601, 605, 628, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0a - 800x600@72Hz */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 275 976, 1040, 0, 600, 637, 643, 666, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x0b - 800x600@75Hz */ 278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 279 896, 1056, 0, 600, 601, 604, 625, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0c - 800x600@85Hz */ 282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 283 896, 1048, 0, 600, 601, 604, 631, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x0d - 800x600@120Hz RB */ 286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 287 880, 960, 0, 600, 603, 607, 636, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 0x0e - 848x480@60Hz */ 290 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 291 976, 1088, 0, 480, 486, 494, 517, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 293 /* 0x0f - 1024x768@43Hz, interlace */ 294 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 295 1208, 1264, 0, 768, 768, 776, 817, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 297 DRM_MODE_FLAG_INTERLACE) }, 298 /* 0x10 - 1024x768@60Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 300 1184, 1344, 0, 768, 771, 777, 806, 0, 301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 302 /* 0x11 - 1024x768@70Hz */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 304 1184, 1328, 0, 768, 771, 777, 806, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x12 - 1024x768@75Hz */ 307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 308 1136, 1312, 0, 768, 769, 772, 800, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x13 - 1024x768@85Hz */ 311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 312 1168, 1376, 0, 768, 769, 772, 808, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x14 - 1024x768@120Hz RB */ 315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 316 1104, 1184, 0, 768, 771, 775, 813, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x15 - 1152x864@75Hz */ 319 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 320 1344, 1600, 0, 864, 865, 868, 900, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x55 - 1280x720@60Hz */ 323 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 324 1430, 1650, 0, 720, 725, 730, 750, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x16 - 1280x768@60Hz RB */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 328 1360, 1440, 0, 768, 771, 778, 790, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 330 /* 0x17 - 1280x768@60Hz */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 332 1472, 1664, 0, 768, 771, 778, 798, 0, 333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 334 /* 0x18 - 1280x768@75Hz */ 335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 336 1488, 1696, 0, 768, 771, 778, 805, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x19 - 1280x768@85Hz */ 339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 340 1496, 1712, 0, 768, 771, 778, 809, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1a - 1280x768@120Hz RB */ 343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 344 1360, 1440, 0, 768, 771, 778, 813, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 346 /* 0x1b - 1280x800@60Hz RB */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 348 1360, 1440, 0, 800, 803, 809, 823, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x1c - 1280x800@60Hz */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 352 1480, 1680, 0, 800, 803, 809, 831, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 354 /* 0x1d - 1280x800@75Hz */ 355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 356 1488, 1696, 0, 800, 803, 809, 838, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x1e - 1280x800@85Hz */ 359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 360 1496, 1712, 0, 800, 803, 809, 843, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x1f - 1280x800@120Hz RB */ 363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 364 1360, 1440, 0, 800, 803, 809, 847, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x20 - 1280x960@60Hz */ 367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 368 1488, 1800, 0, 960, 961, 964, 1000, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x21 - 1280x960@85Hz */ 371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 372 1504, 1728, 0, 960, 961, 964, 1011, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x22 - 1280x960@120Hz RB */ 375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 376 1360, 1440, 0, 960, 963, 967, 1017, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 378 /* 0x23 - 1280x1024@60Hz */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x24 - 1280x1024@75Hz */ 383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x25 - 1280x1024@85Hz */ 387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 388 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x26 - 1280x1024@120Hz RB */ 391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 392 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 394 /* 0x27 - 1360x768@60Hz */ 395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 396 1536, 1792, 0, 768, 771, 777, 795, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x28 - 1360x768@120Hz RB */ 399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 400 1440, 1520, 0, 768, 771, 776, 813, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x51 - 1366x768@60Hz */ 403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 404 1579, 1792, 0, 768, 771, 774, 798, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x56 - 1366x768@60Hz */ 407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 408 1436, 1500, 0, 768, 769, 772, 800, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x29 - 1400x1050@60Hz RB */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 412 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 414 /* 0x2a - 1400x1050@60Hz */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 416 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 418 /* 0x2b - 1400x1050@75Hz */ 419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 420 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x2c - 1400x1050@85Hz */ 423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 424 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x2d - 1400x1050@120Hz RB */ 427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 428 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 430 /* 0x2e - 1440x900@60Hz RB */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 432 1520, 1600, 0, 900, 903, 909, 926, 0, 433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 434 /* 0x2f - 1440x900@60Hz */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 436 1672, 1904, 0, 900, 903, 909, 934, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x30 - 1440x900@75Hz */ 439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 440 1688, 1936, 0, 900, 903, 909, 942, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x31 - 1440x900@85Hz */ 443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 444 1696, 1952, 0, 900, 903, 909, 948, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x32 - 1440x900@120Hz RB */ 447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 448 1520, 1600, 0, 900, 903, 909, 953, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 450 /* 0x53 - 1600x900@60Hz */ 451 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 452 1704, 1800, 0, 900, 901, 904, 1000, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x33 - 1600x1200@60Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x34 - 1600x1200@65Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x35 - 1600x1200@70Hz */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 466 /* 0x36 - 1600x1200@75Hz */ 467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x37 - 1600x1200@85Hz */ 471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x38 - 1600x1200@120Hz RB */ 475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 476 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x39 - 1680x1050@60Hz RB */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 480 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 482 /* 0x3a - 1680x1050@60Hz */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 484 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 486 /* 0x3b - 1680x1050@75Hz */ 487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 488 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3c - 1680x1050@85Hz */ 491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 492 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x3d - 1680x1050@120Hz RB */ 495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 496 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x3e - 1792x1344@60Hz */ 499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 500 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x3f - 1792x1344@75Hz */ 503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 504 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x40 - 1792x1344@120Hz RB */ 507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 508 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x41 - 1856x1392@60Hz */ 511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 512 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x42 - 1856x1392@75Hz */ 515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 516 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x43 - 1856x1392@120Hz RB */ 519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 520 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 522 /* 0x52 - 1920x1080@60Hz */ 523 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 524 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x44 - 1920x1200@60Hz RB */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 528 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 /* 0x45 - 1920x1200@60Hz */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 532 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 534 /* 0x46 - 1920x1200@75Hz */ 535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 536 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x47 - 1920x1200@85Hz */ 539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 540 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x48 - 1920x1200@120Hz RB */ 543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 544 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x49 - 1920x1440@60Hz */ 547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 548 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4a - 1920x1440@75Hz */ 551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 552 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 554 /* 0x4b - 1920x1440@120Hz RB */ 555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 556 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 558 /* 0x54 - 2048x1152@60Hz */ 559 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 560 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4c - 2560x1600@60Hz RB */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 564 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 566 /* 0x4d - 2560x1600@60Hz */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 568 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 570 /* 0x4e - 2560x1600@75Hz */ 571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 572 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 574 /* 0x4f - 2560x1600@85Hz */ 575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 576 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 578 /* 0x50 - 2560x1600@120Hz RB */ 579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 580 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 582 /* 0x57 - 4096x2160@60Hz RB */ 583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 586 /* 0x58 - 4096x2160@59.94Hz RB */ 587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 590 }; 591 592 /* 593 * These more or less come from the DMT spec. The 720x400 modes are 594 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 595 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 596 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 597 * mode. 598 * 599 * The DMT modes have been fact-checked; the rest are mild guesses. 600 */ 601 static const struct drm_display_mode edid_est_modes[] = { 602 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 603 968, 1056, 0, 600, 601, 605, 628, 0, 604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 605 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 606 896, 1024, 0, 600, 601, 603, 625, 0, 607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 608 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 609 720, 840, 0, 480, 481, 484, 500, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 612 704, 832, 0, 480, 489, 492, 520, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 615 768, 864, 0, 480, 483, 486, 525, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 617 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 618 752, 800, 0, 480, 490, 492, 525, 0, 619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 620 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 621 846, 900, 0, 400, 421, 423, 449, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 623 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 624 846, 900, 0, 400, 412, 414, 449, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 626 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 627 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 629 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 630 1136, 1312, 0, 768, 769, 772, 800, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 632 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 633 1184, 1328, 0, 768, 771, 777, 806, 0, 634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 635 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 636 1184, 1344, 0, 768, 771, 777, 806, 0, 637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 638 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 639 1208, 1264, 0, 768, 768, 776, 817, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 641 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 642 928, 1152, 0, 624, 625, 628, 667, 0, 643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 644 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 645 896, 1056, 0, 600, 601, 604, 625, 0, 646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 647 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 648 976, 1040, 0, 600, 637, 643, 666, 0, 649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 650 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 651 1344, 1600, 0, 864, 865, 868, 900, 0, 652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 653 }; 654 655 struct minimode { 656 short w; 657 short h; 658 short r; 659 short rb; 660 }; 661 662 static const struct minimode est3_modes[] = { 663 /* byte 6 */ 664 { 640, 350, 85, 0 }, 665 { 640, 400, 85, 0 }, 666 { 720, 400, 85, 0 }, 667 { 640, 480, 85, 0 }, 668 { 848, 480, 60, 0 }, 669 { 800, 600, 85, 0 }, 670 { 1024, 768, 85, 0 }, 671 { 1152, 864, 75, 0 }, 672 /* byte 7 */ 673 { 1280, 768, 60, 1 }, 674 { 1280, 768, 60, 0 }, 675 { 1280, 768, 75, 0 }, 676 { 1280, 768, 85, 0 }, 677 { 1280, 960, 60, 0 }, 678 { 1280, 960, 85, 0 }, 679 { 1280, 1024, 60, 0 }, 680 { 1280, 1024, 85, 0 }, 681 /* byte 8 */ 682 { 1360, 768, 60, 0 }, 683 { 1440, 900, 60, 1 }, 684 { 1440, 900, 60, 0 }, 685 { 1440, 900, 75, 0 }, 686 { 1440, 900, 85, 0 }, 687 { 1400, 1050, 60, 1 }, 688 { 1400, 1050, 60, 0 }, 689 { 1400, 1050, 75, 0 }, 690 /* byte 9 */ 691 { 1400, 1050, 85, 0 }, 692 { 1680, 1050, 60, 1 }, 693 { 1680, 1050, 60, 0 }, 694 { 1680, 1050, 75, 0 }, 695 { 1680, 1050, 85, 0 }, 696 { 1600, 1200, 60, 0 }, 697 { 1600, 1200, 65, 0 }, 698 { 1600, 1200, 70, 0 }, 699 /* byte 10 */ 700 { 1600, 1200, 75, 0 }, 701 { 1600, 1200, 85, 0 }, 702 { 1792, 1344, 60, 0 }, 703 { 1792, 1344, 75, 0 }, 704 { 1856, 1392, 60, 0 }, 705 { 1856, 1392, 75, 0 }, 706 { 1920, 1200, 60, 1 }, 707 { 1920, 1200, 60, 0 }, 708 /* byte 11 */ 709 { 1920, 1200, 75, 0 }, 710 { 1920, 1200, 85, 0 }, 711 { 1920, 1440, 60, 0 }, 712 { 1920, 1440, 75, 0 }, 713 }; 714 715 static const struct minimode extra_modes[] = { 716 { 1024, 576, 60, 0 }, 717 { 1366, 768, 60, 0 }, 718 { 1600, 900, 60, 0 }, 719 { 1680, 945, 60, 0 }, 720 { 1920, 1080, 60, 0 }, 721 { 2048, 1152, 60, 0 }, 722 { 2048, 1536, 60, 0 }, 723 }; 724 725 /* 726 * From CEA/CTA-861 spec. 727 * 728 * Do not access directly, instead always use cea_mode_for_vic(). 729 */ 730 static const struct drm_display_mode edid_cea_modes_1[] = { 731 /* 1 - 640x480@60Hz 4:3 */ 732 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 733 752, 800, 0, 480, 490, 492, 525, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 736 /* 2 - 720x480@60Hz 4:3 */ 737 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 738 798, 858, 0, 480, 489, 495, 525, 0, 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 740 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 741 /* 3 - 720x480@60Hz 16:9 */ 742 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 743 798, 858, 0, 480, 489, 495, 525, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 4 - 1280x720@60Hz 16:9 */ 747 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 748 1430, 1650, 0, 720, 725, 730, 750, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 5 - 1920x1080i@60Hz 16:9 */ 752 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 753 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 755 DRM_MODE_FLAG_INTERLACE), 756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 6 - 720(1440)x480i@60Hz 4:3 */ 758 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 480, 488, 494, 525, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 7 - 720(1440)x480i@60Hz 16:9 */ 764 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 480, 488, 494, 525, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 8 - 720(1440)x240@60Hz 4:3 */ 770 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 771 801, 858, 0, 240, 244, 247, 262, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_DBLCLK), 774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 9 - 720(1440)x240@60Hz 16:9 */ 776 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 777 801, 858, 0, 240, 244, 247, 262, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_DBLCLK), 780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 10 - 2880x480i@60Hz 4:3 */ 782 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 480, 488, 494, 525, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 785 DRM_MODE_FLAG_INTERLACE), 786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 787 /* 11 - 2880x480i@60Hz 16:9 */ 788 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 789 3204, 3432, 0, 480, 488, 494, 525, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 791 DRM_MODE_FLAG_INTERLACE), 792 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 12 - 2880x240@60Hz 4:3 */ 794 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 795 3204, 3432, 0, 240, 244, 247, 262, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 13 - 2880x240@60Hz 16:9 */ 799 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 800 3204, 3432, 0, 240, 244, 247, 262, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 803 /* 14 - 1440x480@60Hz 4:3 */ 804 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 805 1596, 1716, 0, 480, 489, 495, 525, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 808 /* 15 - 1440x480@60Hz 16:9 */ 809 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 810 1596, 1716, 0, 480, 489, 495, 525, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 16 - 1920x1080@60Hz 16:9 */ 814 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 815 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 17 - 720x576@50Hz 4:3 */ 819 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 820 796, 864, 0, 576, 581, 586, 625, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 823 /* 18 - 720x576@50Hz 16:9 */ 824 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 825 796, 864, 0, 576, 581, 586, 625, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 19 - 1280x720@50Hz 16:9 */ 829 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 830 1760, 1980, 0, 720, 725, 730, 750, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 20 - 1920x1080i@50Hz 16:9 */ 834 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 835 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 837 DRM_MODE_FLAG_INTERLACE), 838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 21 - 720(1440)x576i@50Hz 4:3 */ 840 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 576, 580, 586, 625, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 22 - 720(1440)x576i@50Hz 16:9 */ 846 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 576, 580, 586, 625, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 23 - 720(1440)x288@50Hz 4:3 */ 852 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 853 795, 864, 0, 288, 290, 293, 312, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_DBLCLK), 856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 24 - 720(1440)x288@50Hz 16:9 */ 858 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 859 795, 864, 0, 288, 290, 293, 312, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_DBLCLK), 862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 25 - 2880x576i@50Hz 4:3 */ 864 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 576, 580, 586, 625, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 867 DRM_MODE_FLAG_INTERLACE), 868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 869 /* 26 - 2880x576i@50Hz 16:9 */ 870 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 871 3180, 3456, 0, 576, 580, 586, 625, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 873 DRM_MODE_FLAG_INTERLACE), 874 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 27 - 2880x288@50Hz 4:3 */ 876 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 877 3180, 3456, 0, 288, 290, 293, 312, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 880 /* 28 - 2880x288@50Hz 16:9 */ 881 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 882 3180, 3456, 0, 288, 290, 293, 312, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 29 - 1440x576@50Hz 4:3 */ 886 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 887 1592, 1728, 0, 576, 581, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 30 - 1440x576@50Hz 16:9 */ 891 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 892 1592, 1728, 0, 576, 581, 586, 625, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 31 - 1920x1080@50Hz 16:9 */ 896 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 897 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 32 - 1920x1080@24Hz 16:9 */ 901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 902 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 33 - 1920x1080@25Hz 16:9 */ 906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 907 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 910 /* 34 - 1920x1080@30Hz 16:9 */ 911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 912 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 35 - 2880x480@60Hz 4:3 */ 916 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 917 3192, 3432, 0, 480, 489, 495, 525, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 920 /* 36 - 2880x480@60Hz 16:9 */ 921 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 922 3192, 3432, 0, 480, 489, 495, 525, 0, 923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 37 - 2880x576@50Hz 4:3 */ 926 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 927 3184, 3456, 0, 576, 581, 586, 625, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 930 /* 38 - 2880x576@50Hz 16:9 */ 931 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 932 3184, 3456, 0, 576, 581, 586, 625, 0, 933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 39 - 1920x1080i@50Hz 16:9 */ 936 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 937 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 939 DRM_MODE_FLAG_INTERLACE), 940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 40 - 1920x1080i@100Hz 16:9 */ 942 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 943 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 945 DRM_MODE_FLAG_INTERLACE), 946 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 947 /* 41 - 1280x720@100Hz 16:9 */ 948 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 949 1760, 1980, 0, 720, 725, 730, 750, 0, 950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 951 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 952 /* 42 - 720x576@100Hz 4:3 */ 953 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 954 796, 864, 0, 576, 581, 586, 625, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 957 /* 43 - 720x576@100Hz 16:9 */ 958 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 959 796, 864, 0, 576, 581, 586, 625, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 44 - 720(1440)x576i@100Hz 4:3 */ 963 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 964 795, 864, 0, 576, 580, 586, 625, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 968 /* 45 - 720(1440)x576i@100Hz 16:9 */ 969 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 970 795, 864, 0, 576, 580, 586, 625, 0, 971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 46 - 1920x1080i@120Hz 16:9 */ 975 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 976 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 978 DRM_MODE_FLAG_INTERLACE), 979 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 47 - 1280x720@120Hz 16:9 */ 981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 982 1430, 1650, 0, 720, 725, 730, 750, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 48 - 720x480@120Hz 4:3 */ 986 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 987 798, 858, 0, 480, 489, 495, 525, 0, 988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 990 /* 49 - 720x480@120Hz 16:9 */ 991 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 992 798, 858, 0, 480, 489, 495, 525, 0, 993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 50 - 720(1440)x480i@120Hz 4:3 */ 996 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 997 801, 858, 0, 480, 488, 494, 525, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 999 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1001 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1002 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1003 801, 858, 0, 480, 488, 494, 525, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1005 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1006 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1007 /* 52 - 720x576@200Hz 4:3 */ 1008 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1009 796, 864, 0, 576, 581, 586, 625, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1012 /* 53 - 720x576@200Hz 16:9 */ 1013 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1014 796, 864, 0, 576, 581, 586, 625, 0, 1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1018 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1019 795, 864, 0, 576, 580, 586, 625, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1021 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1023 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1024 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1025 795, 864, 0, 576, 580, 586, 625, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1027 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1028 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1029 /* 56 - 720x480@240Hz 4:3 */ 1030 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1031 798, 858, 0, 480, 489, 495, 525, 0, 1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1034 /* 57 - 720x480@240Hz 16:9 */ 1035 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1036 798, 858, 0, 480, 489, 495, 525, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1040 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1041 801, 858, 0, 480, 488, 494, 525, 0, 1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1043 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1045 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1046 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1047 801, 858, 0, 480, 488, 494, 525, 0, 1048 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1049 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1050 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1051 /* 60 - 1280x720@24Hz 16:9 */ 1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1053 3080, 3300, 0, 720, 725, 730, 750, 0, 1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1055 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1056 /* 61 - 1280x720@25Hz 16:9 */ 1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1058 3740, 3960, 0, 720, 725, 730, 750, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1061 /* 62 - 1280x720@30Hz 16:9 */ 1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1063 3080, 3300, 0, 720, 725, 730, 750, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1066 /* 63 - 1920x1080@120Hz 16:9 */ 1067 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1068 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1071 /* 64 - 1920x1080@100Hz 16:9 */ 1072 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1073 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1076 /* 65 - 1280x720@24Hz 64:27 */ 1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1078 3080, 3300, 0, 720, 725, 730, 750, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1081 /* 66 - 1280x720@25Hz 64:27 */ 1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1083 3740, 3960, 0, 720, 725, 730, 750, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1086 /* 67 - 1280x720@30Hz 64:27 */ 1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1088 3080, 3300, 0, 720, 725, 730, 750, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 68 - 1280x720@50Hz 64:27 */ 1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1093 1760, 1980, 0, 720, 725, 730, 750, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 69 - 1280x720@60Hz 64:27 */ 1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1098 1430, 1650, 0, 720, 725, 730, 750, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 70 - 1280x720@100Hz 64:27 */ 1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1103 1760, 1980, 0, 720, 725, 730, 750, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 71 - 1280x720@120Hz 64:27 */ 1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1108 1430, 1650, 0, 720, 725, 730, 750, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 72 - 1920x1080@24Hz 64:27 */ 1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1113 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 73 - 1920x1080@25Hz 64:27 */ 1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1118 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 74 - 1920x1080@30Hz 64:27 */ 1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1123 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 75 - 1920x1080@50Hz 64:27 */ 1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 76 - 1920x1080@60Hz 64:27 */ 1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 77 - 1920x1080@100Hz 64:27 */ 1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 78 - 1920x1080@120Hz 64:27 */ 1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 79 - 1680x720@24Hz 64:27 */ 1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1148 3080, 3300, 0, 720, 725, 730, 750, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 80 - 1680x720@25Hz 64:27 */ 1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1153 2948, 3168, 0, 720, 725, 730, 750, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 81 - 1680x720@30Hz 64:27 */ 1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1158 2420, 2640, 0, 720, 725, 730, 750, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 82 - 1680x720@50Hz 64:27 */ 1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1163 1980, 2200, 0, 720, 725, 730, 750, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 83 - 1680x720@60Hz 64:27 */ 1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1168 1980, 2200, 0, 720, 725, 730, 750, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 84 - 1680x720@100Hz 64:27 */ 1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1173 1780, 2000, 0, 720, 725, 730, 825, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 85 - 1680x720@120Hz 64:27 */ 1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1178 1780, 2000, 0, 720, 725, 730, 825, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 86 - 2560x1080@24Hz 64:27 */ 1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1183 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 87 - 2560x1080@25Hz 64:27 */ 1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1188 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 88 - 2560x1080@30Hz 64:27 */ 1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1193 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 89 - 2560x1080@50Hz 64:27 */ 1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1198 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 90 - 2560x1080@60Hz 64:27 */ 1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1203 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 91 - 2560x1080@100Hz 64:27 */ 1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1208 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1211 /* 92 - 2560x1080@120Hz 64:27 */ 1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1213 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1216 /* 93 - 3840x2160@24Hz 16:9 */ 1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1218 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1221 /* 94 - 3840x2160@25Hz 16:9 */ 1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1223 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1226 /* 95 - 3840x2160@30Hz 16:9 */ 1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1228 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1231 /* 96 - 3840x2160@50Hz 16:9 */ 1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1236 /* 97 - 3840x2160@60Hz 16:9 */ 1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1241 /* 98 - 4096x2160@24Hz 256:135 */ 1242 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1243 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1246 /* 99 - 4096x2160@25Hz 256:135 */ 1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1248 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1251 /* 100 - 4096x2160@30Hz 256:135 */ 1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1253 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1256 /* 101 - 4096x2160@50Hz 256:135 */ 1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1258 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1261 /* 102 - 4096x2160@60Hz 256:135 */ 1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1263 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1266 /* 103 - 3840x2160@24Hz 64:27 */ 1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1268 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1271 /* 104 - 3840x2160@25Hz 64:27 */ 1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1273 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1276 /* 105 - 3840x2160@30Hz 64:27 */ 1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1278 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1281 /* 106 - 3840x2160@50Hz 64:27 */ 1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1283 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1286 /* 107 - 3840x2160@60Hz 64:27 */ 1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1288 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1291 /* 108 - 1280x720@48Hz 16:9 */ 1292 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1293 2280, 2500, 0, 720, 725, 730, 750, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1296 /* 109 - 1280x720@48Hz 64:27 */ 1297 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1298 2280, 2500, 0, 720, 725, 730, 750, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1301 /* 110 - 1680x720@48Hz 64:27 */ 1302 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1303 2530, 2750, 0, 720, 725, 730, 750, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1306 /* 111 - 1920x1080@48Hz 16:9 */ 1307 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1308 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1311 /* 112 - 1920x1080@48Hz 64:27 */ 1312 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1313 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1316 /* 113 - 2560x1080@48Hz 64:27 */ 1317 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1318 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1321 /* 114 - 3840x2160@48Hz 16:9 */ 1322 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1323 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1326 /* 115 - 4096x2160@48Hz 256:135 */ 1327 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1328 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1331 /* 116 - 3840x2160@48Hz 64:27 */ 1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1336 /* 117 - 3840x2160@100Hz 16:9 */ 1337 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1338 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1341 /* 118 - 3840x2160@120Hz 16:9 */ 1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1343 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1346 /* 119 - 3840x2160@100Hz 64:27 */ 1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1348 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1351 /* 120 - 3840x2160@120Hz 64:27 */ 1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1353 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1356 /* 121 - 5120x2160@24Hz 64:27 */ 1357 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1358 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1361 /* 122 - 5120x2160@25Hz 64:27 */ 1362 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1363 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1366 /* 123 - 5120x2160@30Hz 64:27 */ 1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1368 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1371 /* 124 - 5120x2160@48Hz 64:27 */ 1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1373 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1376 /* 125 - 5120x2160@50Hz 64:27 */ 1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1378 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1381 /* 126 - 5120x2160@60Hz 64:27 */ 1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1383 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1386 /* 127 - 5120x2160@100Hz 64:27 */ 1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1388 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1391 }; 1392 1393 /* 1394 * From CEA/CTA-861 spec. 1395 * 1396 * Do not access directly, instead always use cea_mode_for_vic(). 1397 */ 1398 static const struct drm_display_mode edid_cea_modes_193[] = { 1399 /* 193 - 5120x2160@120Hz 64:27 */ 1400 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1401 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1403 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1404 /* 194 - 7680x4320@24Hz 16:9 */ 1405 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1406 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1408 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1409 /* 195 - 7680x4320@25Hz 16:9 */ 1410 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1411 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1414 /* 196 - 7680x4320@30Hz 16:9 */ 1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1416 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1419 /* 197 - 7680x4320@48Hz 16:9 */ 1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1421 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1424 /* 198 - 7680x4320@50Hz 16:9 */ 1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1426 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1429 /* 199 - 7680x4320@60Hz 16:9 */ 1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1431 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1434 /* 200 - 7680x4320@100Hz 16:9 */ 1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1436 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1439 /* 201 - 7680x4320@120Hz 16:9 */ 1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1441 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1444 /* 202 - 7680x4320@24Hz 64:27 */ 1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1446 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1449 /* 203 - 7680x4320@25Hz 64:27 */ 1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1451 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1454 /* 204 - 7680x4320@30Hz 64:27 */ 1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1456 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1459 /* 205 - 7680x4320@48Hz 64:27 */ 1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1461 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1464 /* 206 - 7680x4320@50Hz 64:27 */ 1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1466 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1469 /* 207 - 7680x4320@60Hz 64:27 */ 1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1471 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1474 /* 208 - 7680x4320@100Hz 64:27 */ 1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1476 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1479 /* 209 - 7680x4320@120Hz 64:27 */ 1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1481 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1484 /* 210 - 10240x4320@24Hz 64:27 */ 1485 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1486 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1489 /* 211 - 10240x4320@25Hz 64:27 */ 1490 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1491 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1494 /* 212 - 10240x4320@30Hz 64:27 */ 1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1496 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1499 /* 213 - 10240x4320@48Hz 64:27 */ 1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1501 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1504 /* 214 - 10240x4320@50Hz 64:27 */ 1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1506 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1509 /* 215 - 10240x4320@60Hz 64:27 */ 1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1511 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1514 /* 216 - 10240x4320@100Hz 64:27 */ 1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1516 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1519 /* 217 - 10240x4320@120Hz 64:27 */ 1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1521 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1524 /* 218 - 4096x2160@100Hz 256:135 */ 1525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1526 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1529 /* 219 - 4096x2160@120Hz 256:135 */ 1530 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1531 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1534 }; 1535 1536 /* 1537 * HDMI 1.4 4k modes. Index using the VIC. 1538 */ 1539 static const struct drm_display_mode edid_4k_modes[] = { 1540 /* 0 - dummy, VICs start at 1 */ 1541 { }, 1542 /* 1 - 3840x2160@30Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 4016, 4104, 4400, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 2 - 3840x2160@25Hz */ 1549 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 3840, 4896, 4984, 5280, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1554 /* 3 - 3840x2160@24Hz */ 1555 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1556 3840, 5116, 5204, 5500, 0, 1557 2160, 2168, 2178, 2250, 0, 1558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1559 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1560 /* 4 - 4096x2160@24Hz (SMPTE) */ 1561 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1562 4096, 5116, 5204, 5500, 0, 1563 2160, 2168, 2178, 2250, 0, 1564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1565 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1566 }; 1567 1568 /*** DDC fetch and block validation ***/ 1569 1570 static int edid_extension_block_count(const struct edid *edid) 1571 { 1572 return edid->extensions; 1573 } 1574 1575 static int edid_block_count(const struct edid *edid) 1576 { 1577 return edid_extension_block_count(edid) + 1; 1578 } 1579 1580 static int edid_size_by_blocks(int num_blocks) 1581 { 1582 return num_blocks * EDID_LENGTH; 1583 } 1584 1585 static int edid_size(const struct edid *edid) 1586 { 1587 return edid_size_by_blocks(edid_block_count(edid)); 1588 } 1589 1590 static const void *edid_block_data(const struct edid *edid, int index) 1591 { 1592 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1593 1594 return edid + index; 1595 } 1596 1597 static const void *edid_extension_block_data(const struct edid *edid, int index) 1598 { 1599 return edid_block_data(edid, index + 1); 1600 } 1601 1602 /* 1603 * EDID base and extension block iterator. 1604 * 1605 * struct drm_edid_iter iter; 1606 * const u8 *block; 1607 * 1608 * drm_edid_iter_begin(edid, &iter); 1609 * drm_edid_iter_for_each(block, &iter) { 1610 * // do stuff with block 1611 * } 1612 * drm_edid_iter_end(&iter); 1613 */ 1614 struct drm_edid_iter { 1615 const struct edid *edid; 1616 1617 /* Current block index. */ 1618 int index; 1619 }; 1620 1621 static void drm_edid_iter_begin(const struct edid *edid, 1622 struct drm_edid_iter *iter) 1623 { 1624 memset(iter, 0, sizeof(*iter)); 1625 1626 iter->edid = edid; 1627 } 1628 1629 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1630 { 1631 const void *block = NULL; 1632 1633 if (!iter->edid) 1634 return NULL; 1635 1636 if (iter->index < edid_block_count(iter->edid)) 1637 block = edid_block_data(iter->edid, iter->index++); 1638 1639 return block; 1640 } 1641 1642 #define drm_edid_iter_for_each(__block, __iter) \ 1643 while (((__block) = __drm_edid_iter_next(__iter))) 1644 1645 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1646 { 1647 memset(iter, 0, sizeof(*iter)); 1648 } 1649 1650 static const u8 edid_header[] = { 1651 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1652 }; 1653 1654 static void edid_header_fix(void *edid) 1655 { 1656 memcpy(edid, edid_header, sizeof(edid_header)); 1657 } 1658 1659 /** 1660 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1661 * @_edid: pointer to raw base EDID block 1662 * 1663 * Sanity check the header of the base EDID block. 1664 * 1665 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1666 */ 1667 int drm_edid_header_is_valid(const void *_edid) 1668 { 1669 const struct edid *edid = _edid; 1670 int i, score = 0; 1671 1672 for (i = 0; i < sizeof(edid_header); i++) { 1673 if (edid->header[i] == edid_header[i]) 1674 score++; 1675 } 1676 1677 return score; 1678 } 1679 EXPORT_SYMBOL(drm_edid_header_is_valid); 1680 1681 static int edid_fixup __read_mostly = 6; 1682 module_param_named(edid_fixup, edid_fixup, int, 0400); 1683 MODULE_PARM_DESC(edid_fixup, 1684 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1685 1686 static int edid_block_compute_checksum(const void *_block) 1687 { 1688 const u8 *block = _block; 1689 int i; 1690 u8 csum = 0, crc = 0; 1691 1692 for (i = 0; i < EDID_LENGTH - 1; i++) 1693 csum += block[i]; 1694 1695 crc = 0x100 - csum; 1696 1697 return crc; 1698 } 1699 1700 static int edid_block_get_checksum(const void *_block) 1701 { 1702 const struct edid *block = _block; 1703 1704 return block->checksum; 1705 } 1706 1707 static int edid_block_tag(const void *_block) 1708 { 1709 const u8 *block = _block; 1710 1711 return block[0]; 1712 } 1713 1714 static bool edid_block_is_zero(const void *edid) 1715 { 1716 return !memchr_inv(edid, 0, EDID_LENGTH); 1717 } 1718 1719 /** 1720 * drm_edid_are_equal - compare two edid blobs. 1721 * @edid1: pointer to first blob 1722 * @edid2: pointer to second blob 1723 * This helper can be used during probing to determine if 1724 * edid had changed. 1725 */ 1726 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1727 { 1728 int edid1_len, edid2_len; 1729 bool edid1_present = edid1 != NULL; 1730 bool edid2_present = edid2 != NULL; 1731 1732 if (edid1_present != edid2_present) 1733 return false; 1734 1735 if (edid1) { 1736 edid1_len = edid_size(edid1); 1737 edid2_len = edid_size(edid2); 1738 1739 if (edid1_len != edid2_len) 1740 return false; 1741 1742 if (memcmp(edid1, edid2, edid1_len)) 1743 return false; 1744 } 1745 1746 return true; 1747 } 1748 EXPORT_SYMBOL(drm_edid_are_equal); 1749 1750 enum edid_block_status { 1751 EDID_BLOCK_OK = 0, 1752 EDID_BLOCK_READ_FAIL, 1753 EDID_BLOCK_NULL, 1754 EDID_BLOCK_ZERO, 1755 EDID_BLOCK_HEADER_CORRUPT, 1756 EDID_BLOCK_HEADER_REPAIR, 1757 EDID_BLOCK_HEADER_FIXED, 1758 EDID_BLOCK_CHECKSUM, 1759 EDID_BLOCK_VERSION, 1760 }; 1761 1762 static enum edid_block_status edid_block_check(const void *_block, 1763 bool is_base_block) 1764 { 1765 const struct edid *block = _block; 1766 1767 if (!block) 1768 return EDID_BLOCK_NULL; 1769 1770 if (is_base_block) { 1771 int score = drm_edid_header_is_valid(block); 1772 1773 if (score < clamp(edid_fixup, 0, 8)) { 1774 if (edid_block_is_zero(block)) 1775 return EDID_BLOCK_ZERO; 1776 else 1777 return EDID_BLOCK_HEADER_CORRUPT; 1778 } 1779 1780 if (score < 8) 1781 return EDID_BLOCK_HEADER_REPAIR; 1782 } 1783 1784 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1785 if (edid_block_is_zero(block)) 1786 return EDID_BLOCK_ZERO; 1787 else 1788 return EDID_BLOCK_CHECKSUM; 1789 } 1790 1791 if (is_base_block) { 1792 if (block->version != 1) 1793 return EDID_BLOCK_VERSION; 1794 } 1795 1796 return EDID_BLOCK_OK; 1797 } 1798 1799 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1800 { 1801 return status == EDID_BLOCK_OK || 1802 status == EDID_BLOCK_HEADER_FIXED || 1803 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1804 } 1805 1806 static bool edid_block_valid(const void *block, bool base) 1807 { 1808 return edid_block_status_valid(edid_block_check(block, base), 1809 edid_block_tag(block)); 1810 } 1811 1812 static void edid_block_status_print(enum edid_block_status status, 1813 const struct edid *block, 1814 int block_num) 1815 { 1816 switch (status) { 1817 case EDID_BLOCK_OK: 1818 break; 1819 case EDID_BLOCK_READ_FAIL: 1820 pr_debug("EDID block %d read failed\n", block_num); 1821 break; 1822 case EDID_BLOCK_NULL: 1823 pr_debug("EDID block %d pointer is NULL\n", block_num); 1824 break; 1825 case EDID_BLOCK_ZERO: 1826 pr_notice("EDID block %d is all zeroes\n", block_num); 1827 break; 1828 case EDID_BLOCK_HEADER_CORRUPT: 1829 pr_notice("EDID has corrupt header\n"); 1830 break; 1831 case EDID_BLOCK_HEADER_REPAIR: 1832 pr_debug("EDID corrupt header needs repair\n"); 1833 break; 1834 case EDID_BLOCK_HEADER_FIXED: 1835 pr_debug("EDID corrupt header fixed\n"); 1836 break; 1837 case EDID_BLOCK_CHECKSUM: 1838 if (edid_block_status_valid(status, edid_block_tag(block))) { 1839 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1840 block_num, edid_block_tag(block), 1841 edid_block_compute_checksum(block)); 1842 } else { 1843 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1844 block_num, edid_block_tag(block), 1845 edid_block_compute_checksum(block)); 1846 } 1847 break; 1848 case EDID_BLOCK_VERSION: 1849 pr_notice("EDID has major version %d, instead of 1\n", 1850 block->version); 1851 break; 1852 default: 1853 WARN(1, "EDID block %d unknown edid block status code %d\n", 1854 block_num, status); 1855 break; 1856 } 1857 } 1858 1859 static void edid_block_dump(const char *level, const void *block, int block_num) 1860 { 1861 enum edid_block_status status; 1862 char prefix[20]; 1863 1864 status = edid_block_check(block, block_num == 0); 1865 if (status == EDID_BLOCK_ZERO) 1866 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1867 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1868 sprintf(prefix, "\t[%02x] BAD ", block_num); 1869 else 1870 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1871 1872 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1873 block, EDID_LENGTH, false); 1874 } 1875 1876 /** 1877 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1878 * @_block: pointer to raw EDID block 1879 * @block_num: type of block to validate (0 for base, extension otherwise) 1880 * @print_bad_edid: if true, dump bad EDID blocks to the console 1881 * @edid_corrupt: if true, the header or checksum is invalid 1882 * 1883 * Validate a base or extension EDID block and optionally dump bad blocks to 1884 * the console. 1885 * 1886 * Return: True if the block is valid, false otherwise. 1887 */ 1888 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1889 bool *edid_corrupt) 1890 { 1891 struct edid *block = (struct edid *)_block; 1892 enum edid_block_status status; 1893 bool is_base_block = block_num == 0; 1894 bool valid; 1895 1896 if (WARN_ON(!block)) 1897 return false; 1898 1899 status = edid_block_check(block, is_base_block); 1900 if (status == EDID_BLOCK_HEADER_REPAIR) { 1901 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1902 edid_header_fix(block); 1903 1904 /* Retry with fixed header, update status if that worked. */ 1905 status = edid_block_check(block, is_base_block); 1906 if (status == EDID_BLOCK_OK) 1907 status = EDID_BLOCK_HEADER_FIXED; 1908 } 1909 1910 if (edid_corrupt) { 1911 /* 1912 * Unknown major version isn't corrupt but we can't use it. Only 1913 * the base block can reset edid_corrupt to false. 1914 */ 1915 if (is_base_block && 1916 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 1917 *edid_corrupt = false; 1918 else if (status != EDID_BLOCK_OK) 1919 *edid_corrupt = true; 1920 } 1921 1922 edid_block_status_print(status, block, block_num); 1923 1924 /* Determine whether we can use this block with this status. */ 1925 valid = edid_block_status_valid(status, edid_block_tag(block)); 1926 1927 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 1928 pr_notice("Raw EDID:\n"); 1929 edid_block_dump(KERN_NOTICE, block, block_num); 1930 } 1931 1932 return valid; 1933 } 1934 EXPORT_SYMBOL(drm_edid_block_valid); 1935 1936 /** 1937 * drm_edid_is_valid - sanity check EDID data 1938 * @edid: EDID data 1939 * 1940 * Sanity-check an entire EDID record (including extensions) 1941 * 1942 * Return: True if the EDID data is valid, false otherwise. 1943 */ 1944 bool drm_edid_is_valid(struct edid *edid) 1945 { 1946 int i; 1947 1948 if (!edid) 1949 return false; 1950 1951 for (i = 0; i < edid_block_count(edid); i++) { 1952 void *block = (void *)edid_block_data(edid, i); 1953 1954 if (!drm_edid_block_valid(block, i, true, NULL)) 1955 return false; 1956 } 1957 1958 return true; 1959 } 1960 EXPORT_SYMBOL(drm_edid_is_valid); 1961 1962 static struct edid *edid_filter_invalid_blocks(const struct edid *edid, 1963 int invalid_blocks) 1964 { 1965 struct edid *new, *dest_block; 1966 int valid_extensions = edid->extensions - invalid_blocks; 1967 int i; 1968 1969 new = kmalloc(edid_size_by_blocks(valid_extensions + 1), GFP_KERNEL); 1970 if (!new) 1971 goto out; 1972 1973 dest_block = new; 1974 for (i = 0; i < edid_block_count(edid); i++) { 1975 const void *block = edid_block_data(edid, i); 1976 1977 if (edid_block_valid(block, i == 0)) 1978 memcpy(dest_block++, block, EDID_LENGTH); 1979 } 1980 1981 new->extensions = valid_extensions; 1982 new->checksum = edid_block_compute_checksum(new); 1983 1984 out: 1985 kfree(edid); 1986 1987 return new; 1988 } 1989 1990 #define DDC_SEGMENT_ADDR 0x30 1991 /** 1992 * drm_do_probe_ddc_edid() - get EDID information via I2C 1993 * @data: I2C device adapter 1994 * @buf: EDID data buffer to be filled 1995 * @block: 128 byte EDID block to start fetching from 1996 * @len: EDID data buffer length to fetch 1997 * 1998 * Try to fetch EDID information by calling I2C driver functions. 1999 * 2000 * Return: 0 on success or -1 on failure. 2001 */ 2002 static int 2003 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2004 { 2005 struct i2c_adapter *adapter = data; 2006 unsigned char start = block * EDID_LENGTH; 2007 unsigned char segment = block >> 1; 2008 unsigned char xfers = segment ? 3 : 2; 2009 int ret, retries = 5; 2010 2011 /* 2012 * The core I2C driver will automatically retry the transfer if the 2013 * adapter reports EAGAIN. However, we find that bit-banging transfers 2014 * are susceptible to errors under a heavily loaded machine and 2015 * generate spurious NAKs and timeouts. Retrying the transfer 2016 * of the individual block a few times seems to overcome this. 2017 */ 2018 do { 2019 struct i2c_msg msgs[] = { 2020 { 2021 .addr = DDC_SEGMENT_ADDR, 2022 .flags = 0, 2023 .len = 1, 2024 .buf = &segment, 2025 }, { 2026 .addr = DDC_ADDR, 2027 .flags = 0, 2028 .len = 1, 2029 .buf = &start, 2030 }, { 2031 .addr = DDC_ADDR, 2032 .flags = I2C_M_RD, 2033 .len = len, 2034 .buf = buf, 2035 } 2036 }; 2037 2038 /* 2039 * Avoid sending the segment addr to not upset non-compliant 2040 * DDC monitors. 2041 */ 2042 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2043 2044 if (ret == -ENXIO) { 2045 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2046 adapter->name); 2047 break; 2048 } 2049 } while (ret != xfers && --retries); 2050 2051 return ret == xfers ? 0 : -1; 2052 } 2053 2054 static void connector_bad_edid(struct drm_connector *connector, 2055 const struct edid *edid, int num_blocks) 2056 { 2057 int i; 2058 u8 last_block; 2059 2060 /* 2061 * 0x7e in the EDID is the number of extension blocks. The EDID 2062 * is 1 (base block) + num_ext_blocks big. That means we can think 2063 * of 0x7e in the EDID of the _index_ of the last block in the 2064 * combined chunk of memory. 2065 */ 2066 last_block = edid->extensions; 2067 2068 /* Calculate real checksum for the last edid extension block data */ 2069 if (last_block < num_blocks) 2070 connector->real_edid_checksum = 2071 edid_block_compute_checksum(edid + last_block); 2072 2073 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2074 return; 2075 2076 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name); 2077 for (i = 0; i < num_blocks; i++) 2078 edid_block_dump(KERN_DEBUG, edid + i, i); 2079 } 2080 2081 /* Get override or firmware EDID */ 2082 static struct edid *drm_get_override_edid(struct drm_connector *connector) 2083 { 2084 struct edid *override = NULL; 2085 2086 if (connector->override_edid) 2087 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 2088 2089 if (!override) 2090 override = drm_load_edid_firmware(connector); 2091 2092 return IS_ERR(override) ? NULL : override; 2093 } 2094 2095 /** 2096 * drm_add_override_edid_modes - add modes from override/firmware EDID 2097 * @connector: connector we're probing 2098 * 2099 * Add modes from the override/firmware EDID, if available. Only to be used from 2100 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2101 * failed during drm_get_edid() and caused the override/firmware EDID to be 2102 * skipped. 2103 * 2104 * Return: The number of modes added or 0 if we couldn't find any. 2105 */ 2106 int drm_add_override_edid_modes(struct drm_connector *connector) 2107 { 2108 struct edid *override; 2109 int num_modes = 0; 2110 2111 override = drm_get_override_edid(connector); 2112 if (override) { 2113 drm_connector_update_edid_property(connector, override); 2114 num_modes = drm_add_edid_modes(connector, override); 2115 kfree(override); 2116 2117 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2118 connector->base.id, connector->name, num_modes); 2119 } 2120 2121 return num_modes; 2122 } 2123 EXPORT_SYMBOL(drm_add_override_edid_modes); 2124 2125 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2126 2127 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2128 read_block_fn read_block, 2129 void *context) 2130 { 2131 enum edid_block_status status; 2132 bool is_base_block = block_num == 0; 2133 int try; 2134 2135 for (try = 0; try < 4; try++) { 2136 if (read_block(context, block, block_num, EDID_LENGTH)) 2137 return EDID_BLOCK_READ_FAIL; 2138 2139 status = edid_block_check(block, is_base_block); 2140 if (status == EDID_BLOCK_HEADER_REPAIR) { 2141 edid_header_fix(block); 2142 2143 /* Retry with fixed header, update status if that worked. */ 2144 status = edid_block_check(block, is_base_block); 2145 if (status == EDID_BLOCK_OK) 2146 status = EDID_BLOCK_HEADER_FIXED; 2147 } 2148 2149 if (edid_block_status_valid(status, edid_block_tag(block))) 2150 break; 2151 2152 /* Fail early for unrepairable base block all zeros. */ 2153 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2154 break; 2155 } 2156 2157 return status; 2158 } 2159 2160 /** 2161 * drm_do_get_edid - get EDID data using a custom EDID block read function 2162 * @connector: connector we're probing 2163 * @read_block: EDID block read function 2164 * @context: private data passed to the block read function 2165 * 2166 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2167 * exposes a different interface to read EDID blocks this function can be used 2168 * to get EDID data using a custom block read function. 2169 * 2170 * As in the general case the DDC bus is accessible by the kernel at the I2C 2171 * level, drivers must make all reasonable efforts to expose it as an I2C 2172 * adapter and use drm_get_edid() instead of abusing this function. 2173 * 2174 * The EDID may be overridden using debugfs override_edid or firmware EDID 2175 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 2176 * order. Having either of them bypasses actual EDID reads. 2177 * 2178 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2179 */ 2180 struct edid *drm_do_get_edid(struct drm_connector *connector, 2181 read_block_fn read_block, 2182 void *context) 2183 { 2184 enum edid_block_status status; 2185 int i, invalid_blocks = 0; 2186 struct edid *edid, *new; 2187 2188 edid = drm_get_override_edid(connector); 2189 if (edid) 2190 goto ok; 2191 2192 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 2193 if (!edid) 2194 return NULL; 2195 2196 status = edid_block_read(edid, 0, read_block, context); 2197 2198 edid_block_status_print(status, edid, 0); 2199 2200 if (status == EDID_BLOCK_READ_FAIL) 2201 goto fail; 2202 2203 /* FIXME: Clarify what a corrupt EDID actually means. */ 2204 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2205 connector->edid_corrupt = false; 2206 else 2207 connector->edid_corrupt = true; 2208 2209 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2210 if (status == EDID_BLOCK_ZERO) 2211 connector->null_edid_counter++; 2212 2213 connector_bad_edid(connector, edid, 1); 2214 goto fail; 2215 } 2216 2217 if (!edid_extension_block_count(edid)) 2218 goto ok; 2219 2220 new = krealloc(edid, edid_size(edid), GFP_KERNEL); 2221 if (!new) 2222 goto fail; 2223 edid = new; 2224 2225 for (i = 1; i < edid_block_count(edid); i++) { 2226 void *block = (void *)edid_block_data(edid, i); 2227 2228 status = edid_block_read(block, i, read_block, context); 2229 2230 edid_block_status_print(status, block, i); 2231 2232 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2233 if (status == EDID_BLOCK_READ_FAIL) 2234 goto fail; 2235 invalid_blocks++; 2236 } 2237 } 2238 2239 if (invalid_blocks) { 2240 connector_bad_edid(connector, edid, edid_block_count(edid)); 2241 2242 edid = edid_filter_invalid_blocks(edid, invalid_blocks); 2243 } 2244 2245 ok: 2246 return edid; 2247 2248 fail: 2249 kfree(edid); 2250 return NULL; 2251 } 2252 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2253 2254 /** 2255 * drm_probe_ddc() - probe DDC presence 2256 * @adapter: I2C adapter to probe 2257 * 2258 * Return: True on success, false on failure. 2259 */ 2260 bool 2261 drm_probe_ddc(struct i2c_adapter *adapter) 2262 { 2263 unsigned char out; 2264 2265 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2266 } 2267 EXPORT_SYMBOL(drm_probe_ddc); 2268 2269 /** 2270 * drm_get_edid - get EDID data, if available 2271 * @connector: connector we're probing 2272 * @adapter: I2C adapter to use for DDC 2273 * 2274 * Poke the given I2C channel to grab EDID data if possible. If found, 2275 * attach it to the connector. 2276 * 2277 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2278 */ 2279 struct edid *drm_get_edid(struct drm_connector *connector, 2280 struct i2c_adapter *adapter) 2281 { 2282 struct edid *edid; 2283 2284 if (connector->force == DRM_FORCE_OFF) 2285 return NULL; 2286 2287 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2288 return NULL; 2289 2290 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2291 drm_connector_update_edid_property(connector, edid); 2292 return edid; 2293 } 2294 EXPORT_SYMBOL(drm_get_edid); 2295 2296 static u32 edid_extract_panel_id(const struct edid *edid) 2297 { 2298 /* 2299 * We represent the ID as a 32-bit number so it can easily be compared 2300 * with "==". 2301 * 2302 * NOTE that we deal with endianness differently for the top half 2303 * of this ID than for the bottom half. The bottom half (the product 2304 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2305 * that's how everyone seems to interpret it. The top half (the mfg_id) 2306 * gets stored as big endian because that makes 2307 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2308 * to write (it's easier to extract the ASCII). It doesn't really 2309 * matter, though, as long as the number here is unique. 2310 */ 2311 return (u32)edid->mfg_id[0] << 24 | 2312 (u32)edid->mfg_id[1] << 16 | 2313 (u32)EDID_PRODUCT_ID(edid); 2314 } 2315 2316 /** 2317 * drm_edid_get_panel_id - Get a panel's ID through DDC 2318 * @adapter: I2C adapter to use for DDC 2319 * 2320 * This function reads the first block of the EDID of a panel and (assuming 2321 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2322 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2323 * supposed to be different for each different modem of panel. 2324 * 2325 * This function is intended to be used during early probing on devices where 2326 * more than one panel might be present. Because of its intended use it must 2327 * assume that the EDID of the panel is correct, at least as far as the ID 2328 * is concerned (in other words, we don't process any overrides here). 2329 * 2330 * NOTE: it's expected that this function and drm_do_get_edid() will both 2331 * be read the EDID, but there is no caching between them. Since we're only 2332 * reading the first block, hopefully this extra overhead won't be too big. 2333 * 2334 * Return: A 32-bit ID that should be different for each make/model of panel. 2335 * See the functions drm_edid_encode_panel_id() and 2336 * drm_edid_decode_panel_id() for some details on the structure of this 2337 * ID. 2338 */ 2339 2340 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2341 { 2342 enum edid_block_status status; 2343 void *base_block; 2344 u32 panel_id = 0; 2345 2346 /* 2347 * There are no manufacturer IDs of 0, so if there is a problem reading 2348 * the EDID then we'll just return 0. 2349 */ 2350 2351 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL); 2352 if (!base_block) 2353 return 0; 2354 2355 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2356 2357 edid_block_status_print(status, base_block, 0); 2358 2359 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2360 panel_id = edid_extract_panel_id(base_block); 2361 2362 kfree(base_block); 2363 2364 return panel_id; 2365 } 2366 EXPORT_SYMBOL(drm_edid_get_panel_id); 2367 2368 /** 2369 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2370 * @connector: connector we're probing 2371 * @adapter: I2C adapter to use for DDC 2372 * 2373 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2374 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2375 * switch DDC to the GPU which is retrieving EDID. 2376 * 2377 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2378 */ 2379 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2380 struct i2c_adapter *adapter) 2381 { 2382 struct drm_device *dev = connector->dev; 2383 struct pci_dev *pdev = to_pci_dev(dev->dev); 2384 struct edid *edid; 2385 2386 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2387 return NULL; 2388 2389 vga_switcheroo_lock_ddc(pdev); 2390 edid = drm_get_edid(connector, adapter); 2391 vga_switcheroo_unlock_ddc(pdev); 2392 2393 return edid; 2394 } 2395 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2396 2397 /** 2398 * drm_edid_duplicate - duplicate an EDID and the extensions 2399 * @edid: EDID to duplicate 2400 * 2401 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2402 */ 2403 struct edid *drm_edid_duplicate(const struct edid *edid) 2404 { 2405 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2406 } 2407 EXPORT_SYMBOL(drm_edid_duplicate); 2408 2409 /*** EDID parsing ***/ 2410 2411 /** 2412 * edid_get_quirks - return quirk flags for a given EDID 2413 * @edid: EDID to process 2414 * 2415 * This tells subsequent routines what fixes they need to apply. 2416 */ 2417 static u32 edid_get_quirks(const struct edid *edid) 2418 { 2419 u32 panel_id = edid_extract_panel_id(edid); 2420 const struct edid_quirk *quirk; 2421 int i; 2422 2423 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2424 quirk = &edid_quirk_list[i]; 2425 if (quirk->panel_id == panel_id) 2426 return quirk->quirks; 2427 } 2428 2429 return 0; 2430 } 2431 2432 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2433 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2434 2435 /* 2436 * Walk the mode list for connector, clearing the preferred status on existing 2437 * modes and setting it anew for the right mode ala quirks. 2438 */ 2439 static void edid_fixup_preferred(struct drm_connector *connector, 2440 u32 quirks) 2441 { 2442 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2443 int target_refresh = 0; 2444 int cur_vrefresh, preferred_vrefresh; 2445 2446 if (list_empty(&connector->probed_modes)) 2447 return; 2448 2449 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2450 target_refresh = 60; 2451 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2452 target_refresh = 75; 2453 2454 preferred_mode = list_first_entry(&connector->probed_modes, 2455 struct drm_display_mode, head); 2456 2457 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2458 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2459 2460 if (cur_mode == preferred_mode) 2461 continue; 2462 2463 /* Largest mode is preferred */ 2464 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2465 preferred_mode = cur_mode; 2466 2467 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2468 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2469 /* At a given size, try to get closest to target refresh */ 2470 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2471 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2472 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2473 preferred_mode = cur_mode; 2474 } 2475 } 2476 2477 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2478 } 2479 2480 static bool 2481 mode_is_rb(const struct drm_display_mode *mode) 2482 { 2483 return (mode->htotal - mode->hdisplay == 160) && 2484 (mode->hsync_end - mode->hdisplay == 80) && 2485 (mode->hsync_end - mode->hsync_start == 32) && 2486 (mode->vsync_start - mode->vdisplay == 3); 2487 } 2488 2489 /* 2490 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2491 * @dev: Device to duplicate against 2492 * @hsize: Mode width 2493 * @vsize: Mode height 2494 * @fresh: Mode refresh rate 2495 * @rb: Mode reduced-blanking-ness 2496 * 2497 * Walk the DMT mode list looking for a match for the given parameters. 2498 * 2499 * Return: A newly allocated copy of the mode, or NULL if not found. 2500 */ 2501 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2502 int hsize, int vsize, int fresh, 2503 bool rb) 2504 { 2505 int i; 2506 2507 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2508 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2509 2510 if (hsize != ptr->hdisplay) 2511 continue; 2512 if (vsize != ptr->vdisplay) 2513 continue; 2514 if (fresh != drm_mode_vrefresh(ptr)) 2515 continue; 2516 if (rb != mode_is_rb(ptr)) 2517 continue; 2518 2519 return drm_mode_duplicate(dev, ptr); 2520 } 2521 2522 return NULL; 2523 } 2524 EXPORT_SYMBOL(drm_mode_find_dmt); 2525 2526 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 2527 { 2528 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2529 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 2530 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 2531 2532 return descriptor->pixel_clock == 0 && 2533 descriptor->data.other_data.pad1 == 0 && 2534 descriptor->data.other_data.type == type; 2535 } 2536 2537 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 2538 { 2539 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 2540 2541 return descriptor->pixel_clock != 0; 2542 } 2543 2544 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 2545 2546 static void 2547 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2548 { 2549 int i, n; 2550 u8 d = ext[0x02]; 2551 const u8 *det_base = ext + d; 2552 2553 if (d < 4 || d > 127) 2554 return; 2555 2556 n = (127 - d) / 18; 2557 for (i = 0; i < n; i++) 2558 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2559 } 2560 2561 static void 2562 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 2563 { 2564 unsigned int i, n = min((int)ext[0x02], 6); 2565 const u8 *det_base = ext + 5; 2566 2567 if (ext[0x01] != 1) 2568 return; /* unknown version */ 2569 2570 for (i = 0; i < n; i++) 2571 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 2572 } 2573 2574 static void 2575 drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure) 2576 { 2577 int i; 2578 2579 if (edid == NULL) 2580 return; 2581 2582 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2583 cb(&(edid->detailed_timings[i]), closure); 2584 2585 for (i = 0; i < edid_extension_block_count(edid); i++) { 2586 const u8 *ext = edid_extension_block_data(edid, i); 2587 2588 switch (*ext) { 2589 case CEA_EXT: 2590 cea_for_each_detailed_block(ext, cb, closure); 2591 break; 2592 case VTB_EXT: 2593 vtb_for_each_detailed_block(ext, cb, closure); 2594 break; 2595 default: 2596 break; 2597 } 2598 } 2599 } 2600 2601 static void 2602 is_rb(const struct detailed_timing *descriptor, void *data) 2603 { 2604 bool *res = data; 2605 2606 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2607 return; 2608 2609 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2610 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 2611 2612 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 2613 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) 2614 *res = true; 2615 } 2616 2617 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2618 static bool 2619 drm_monitor_supports_rb(const struct edid *edid) 2620 { 2621 if (edid->revision >= 4) { 2622 bool ret = false; 2623 2624 drm_for_each_detailed_block(edid, is_rb, &ret); 2625 return ret; 2626 } 2627 2628 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2629 } 2630 2631 static void 2632 find_gtf2(const struct detailed_timing *descriptor, void *data) 2633 { 2634 const struct detailed_timing **res = data; 2635 2636 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 2637 return; 2638 2639 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 2640 2641 if (descriptor->data.other_data.data.range.flags == 0x02) 2642 *res = descriptor; 2643 } 2644 2645 /* Secondary GTF curve kicks in above some break frequency */ 2646 static int 2647 drm_gtf2_hbreak(const struct edid *edid) 2648 { 2649 const struct detailed_timing *descriptor = NULL; 2650 2651 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2652 2653 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 2654 2655 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 2656 } 2657 2658 static int 2659 drm_gtf2_2c(const struct edid *edid) 2660 { 2661 const struct detailed_timing *descriptor = NULL; 2662 2663 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2664 2665 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 2666 2667 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 2668 } 2669 2670 static int 2671 drm_gtf2_m(const struct edid *edid) 2672 { 2673 const struct detailed_timing *descriptor = NULL; 2674 2675 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2676 2677 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 2678 2679 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 2680 } 2681 2682 static int 2683 drm_gtf2_k(const struct edid *edid) 2684 { 2685 const struct detailed_timing *descriptor = NULL; 2686 2687 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2688 2689 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 2690 2691 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 2692 } 2693 2694 static int 2695 drm_gtf2_2j(const struct edid *edid) 2696 { 2697 const struct detailed_timing *descriptor = NULL; 2698 2699 drm_for_each_detailed_block(edid, find_gtf2, &descriptor); 2700 2701 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 2702 2703 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 2704 } 2705 2706 /* Get standard timing level (CVT/GTF/DMT). */ 2707 static int standard_timing_level(const struct edid *edid) 2708 { 2709 if (edid->revision >= 2) { 2710 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2711 return LEVEL_CVT; 2712 if (drm_gtf2_hbreak(edid)) 2713 return LEVEL_GTF2; 2714 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2715 return LEVEL_GTF; 2716 } 2717 return LEVEL_DMT; 2718 } 2719 2720 /* 2721 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2722 * monitors fill with ascii space (0x20) instead. 2723 */ 2724 static int 2725 bad_std_timing(u8 a, u8 b) 2726 { 2727 return (a == 0x00 && b == 0x00) || 2728 (a == 0x01 && b == 0x01) || 2729 (a == 0x20 && b == 0x20); 2730 } 2731 2732 static int drm_mode_hsync(const struct drm_display_mode *mode) 2733 { 2734 if (mode->htotal <= 0) 2735 return 0; 2736 2737 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 2738 } 2739 2740 /* 2741 * Take the standard timing params (in this case width, aspect, and refresh) 2742 * and convert them into a real mode using CVT/GTF/DMT. 2743 */ 2744 static struct drm_display_mode * 2745 drm_mode_std(struct drm_connector *connector, const struct edid *edid, 2746 const struct std_timing *t) 2747 { 2748 struct drm_device *dev = connector->dev; 2749 struct drm_display_mode *m, *mode = NULL; 2750 int hsize, vsize; 2751 int vrefresh_rate; 2752 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2753 >> EDID_TIMING_ASPECT_SHIFT; 2754 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2755 >> EDID_TIMING_VFREQ_SHIFT; 2756 int timing_level = standard_timing_level(edid); 2757 2758 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2759 return NULL; 2760 2761 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2762 hsize = t->hsize * 8 + 248; 2763 /* vrefresh_rate = vfreq + 60 */ 2764 vrefresh_rate = vfreq + 60; 2765 /* the vdisplay is calculated based on the aspect ratio */ 2766 if (aspect_ratio == 0) { 2767 if (edid->revision < 3) 2768 vsize = hsize; 2769 else 2770 vsize = (hsize * 10) / 16; 2771 } else if (aspect_ratio == 1) 2772 vsize = (hsize * 3) / 4; 2773 else if (aspect_ratio == 2) 2774 vsize = (hsize * 4) / 5; 2775 else 2776 vsize = (hsize * 9) / 16; 2777 2778 /* HDTV hack, part 1 */ 2779 if (vrefresh_rate == 60 && 2780 ((hsize == 1360 && vsize == 765) || 2781 (hsize == 1368 && vsize == 769))) { 2782 hsize = 1366; 2783 vsize = 768; 2784 } 2785 2786 /* 2787 * If this connector already has a mode for this size and refresh 2788 * rate (because it came from detailed or CVT info), use that 2789 * instead. This way we don't have to guess at interlace or 2790 * reduced blanking. 2791 */ 2792 list_for_each_entry(m, &connector->probed_modes, head) 2793 if (m->hdisplay == hsize && m->vdisplay == vsize && 2794 drm_mode_vrefresh(m) == vrefresh_rate) 2795 return NULL; 2796 2797 /* HDTV hack, part 2 */ 2798 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2799 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2800 false); 2801 if (!mode) 2802 return NULL; 2803 mode->hdisplay = 1366; 2804 mode->hsync_start = mode->hsync_start - 1; 2805 mode->hsync_end = mode->hsync_end - 1; 2806 return mode; 2807 } 2808 2809 /* check whether it can be found in default mode table */ 2810 if (drm_monitor_supports_rb(edid)) { 2811 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2812 true); 2813 if (mode) 2814 return mode; 2815 } 2816 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2817 if (mode) 2818 return mode; 2819 2820 /* okay, generate it */ 2821 switch (timing_level) { 2822 case LEVEL_DMT: 2823 break; 2824 case LEVEL_GTF: 2825 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2826 break; 2827 case LEVEL_GTF2: 2828 /* 2829 * This is potentially wrong if there's ever a monitor with 2830 * more than one ranges section, each claiming a different 2831 * secondary GTF curve. Please don't do that. 2832 */ 2833 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2834 if (!mode) 2835 return NULL; 2836 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2837 drm_mode_destroy(dev, mode); 2838 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2839 vrefresh_rate, 0, 0, 2840 drm_gtf2_m(edid), 2841 drm_gtf2_2c(edid), 2842 drm_gtf2_k(edid), 2843 drm_gtf2_2j(edid)); 2844 } 2845 break; 2846 case LEVEL_CVT: 2847 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2848 false); 2849 break; 2850 } 2851 return mode; 2852 } 2853 2854 /* 2855 * EDID is delightfully ambiguous about how interlaced modes are to be 2856 * encoded. Our internal representation is of frame height, but some 2857 * HDTV detailed timings are encoded as field height. 2858 * 2859 * The format list here is from CEA, in frame size. Technically we 2860 * should be checking refresh rate too. Whatever. 2861 */ 2862 static void 2863 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2864 const struct detailed_pixel_timing *pt) 2865 { 2866 int i; 2867 static const struct { 2868 int w, h; 2869 } cea_interlaced[] = { 2870 { 1920, 1080 }, 2871 { 720, 480 }, 2872 { 1440, 480 }, 2873 { 2880, 480 }, 2874 { 720, 576 }, 2875 { 1440, 576 }, 2876 { 2880, 576 }, 2877 }; 2878 2879 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2880 return; 2881 2882 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2883 if ((mode->hdisplay == cea_interlaced[i].w) && 2884 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2885 mode->vdisplay *= 2; 2886 mode->vsync_start *= 2; 2887 mode->vsync_end *= 2; 2888 mode->vtotal *= 2; 2889 mode->vtotal |= 1; 2890 } 2891 } 2892 2893 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2894 } 2895 2896 /* 2897 * Create a new mode from an EDID detailed timing section. An EDID detailed 2898 * timing block contains enough info for us to create and return a new struct 2899 * drm_display_mode. 2900 */ 2901 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2902 const struct edid *edid, 2903 const struct detailed_timing *timing, 2904 u32 quirks) 2905 { 2906 struct drm_display_mode *mode; 2907 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2908 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2909 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2910 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2911 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2912 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2913 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2914 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2915 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2916 2917 /* ignore tiny modes */ 2918 if (hactive < 64 || vactive < 64) 2919 return NULL; 2920 2921 if (pt->misc & DRM_EDID_PT_STEREO) { 2922 DRM_DEBUG_KMS("stereo mode not supported\n"); 2923 return NULL; 2924 } 2925 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2926 DRM_DEBUG_KMS("composite sync not supported\n"); 2927 } 2928 2929 /* it is incorrect if hsync/vsync width is zero */ 2930 if (!hsync_pulse_width || !vsync_pulse_width) { 2931 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2932 "Wrong Hsync/Vsync pulse width\n"); 2933 return NULL; 2934 } 2935 2936 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2937 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2938 if (!mode) 2939 return NULL; 2940 2941 goto set_size; 2942 } 2943 2944 mode = drm_mode_create(dev); 2945 if (!mode) 2946 return NULL; 2947 2948 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2949 mode->clock = 1088 * 10; 2950 else 2951 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2952 2953 mode->hdisplay = hactive; 2954 mode->hsync_start = mode->hdisplay + hsync_offset; 2955 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2956 mode->htotal = mode->hdisplay + hblank; 2957 2958 mode->vdisplay = vactive; 2959 mode->vsync_start = mode->vdisplay + vsync_offset; 2960 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2961 mode->vtotal = mode->vdisplay + vblank; 2962 2963 /* Some EDIDs have bogus h/vtotal values */ 2964 if (mode->hsync_end > mode->htotal) 2965 mode->htotal = mode->hsync_end + 1; 2966 if (mode->vsync_end > mode->vtotal) 2967 mode->vtotal = mode->vsync_end + 1; 2968 2969 drm_mode_do_interlace_quirk(mode, pt); 2970 2971 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2972 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 2973 } else { 2974 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2975 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2976 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2977 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2978 } 2979 2980 set_size: 2981 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2982 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2983 2984 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2985 mode->width_mm *= 10; 2986 mode->height_mm *= 10; 2987 } 2988 2989 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2990 mode->width_mm = edid->width_cm * 10; 2991 mode->height_mm = edid->height_cm * 10; 2992 } 2993 2994 mode->type = DRM_MODE_TYPE_DRIVER; 2995 drm_mode_set_name(mode); 2996 2997 return mode; 2998 } 2999 3000 static bool 3001 mode_in_hsync_range(const struct drm_display_mode *mode, 3002 const struct edid *edid, const u8 *t) 3003 { 3004 int hsync, hmin, hmax; 3005 3006 hmin = t[7]; 3007 if (edid->revision >= 4) 3008 hmin += ((t[4] & 0x04) ? 255 : 0); 3009 hmax = t[8]; 3010 if (edid->revision >= 4) 3011 hmax += ((t[4] & 0x08) ? 255 : 0); 3012 hsync = drm_mode_hsync(mode); 3013 3014 return (hsync <= hmax && hsync >= hmin); 3015 } 3016 3017 static bool 3018 mode_in_vsync_range(const struct drm_display_mode *mode, 3019 const struct edid *edid, const u8 *t) 3020 { 3021 int vsync, vmin, vmax; 3022 3023 vmin = t[5]; 3024 if (edid->revision >= 4) 3025 vmin += ((t[4] & 0x01) ? 255 : 0); 3026 vmax = t[6]; 3027 if (edid->revision >= 4) 3028 vmax += ((t[4] & 0x02) ? 255 : 0); 3029 vsync = drm_mode_vrefresh(mode); 3030 3031 return (vsync <= vmax && vsync >= vmin); 3032 } 3033 3034 static u32 3035 range_pixel_clock(const struct edid *edid, const u8 *t) 3036 { 3037 /* unspecified */ 3038 if (t[9] == 0 || t[9] == 255) 3039 return 0; 3040 3041 /* 1.4 with CVT support gives us real precision, yay */ 3042 if (edid->revision >= 4 && t[10] == 0x04) 3043 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3044 3045 /* 1.3 is pathetic, so fuzz up a bit */ 3046 return t[9] * 10000 + 5001; 3047 } 3048 3049 static bool 3050 mode_in_range(const struct drm_display_mode *mode, const struct edid *edid, 3051 const struct detailed_timing *timing) 3052 { 3053 u32 max_clock; 3054 const u8 *t = (const u8 *)timing; 3055 3056 if (!mode_in_hsync_range(mode, edid, t)) 3057 return false; 3058 3059 if (!mode_in_vsync_range(mode, edid, t)) 3060 return false; 3061 3062 if ((max_clock = range_pixel_clock(edid, t))) 3063 if (mode->clock > max_clock) 3064 return false; 3065 3066 /* 1.4 max horizontal check */ 3067 if (edid->revision >= 4 && t[10] == 0x04) 3068 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3069 return false; 3070 3071 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 3072 return false; 3073 3074 return true; 3075 } 3076 3077 static bool valid_inferred_mode(const struct drm_connector *connector, 3078 const struct drm_display_mode *mode) 3079 { 3080 const struct drm_display_mode *m; 3081 bool ok = false; 3082 3083 list_for_each_entry(m, &connector->probed_modes, head) { 3084 if (mode->hdisplay == m->hdisplay && 3085 mode->vdisplay == m->vdisplay && 3086 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3087 return false; /* duplicated */ 3088 if (mode->hdisplay <= m->hdisplay && 3089 mode->vdisplay <= m->vdisplay) 3090 ok = true; 3091 } 3092 return ok; 3093 } 3094 3095 static int 3096 drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid, 3097 const struct detailed_timing *timing) 3098 { 3099 int i, modes = 0; 3100 struct drm_display_mode *newmode; 3101 struct drm_device *dev = connector->dev; 3102 3103 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3104 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 3105 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3106 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3107 if (newmode) { 3108 drm_mode_probed_add(connector, newmode); 3109 modes++; 3110 } 3111 } 3112 } 3113 3114 return modes; 3115 } 3116 3117 /* fix up 1366x768 mode from 1368x768; 3118 * GFT/CVT can't express 1366 width which isn't dividable by 8 3119 */ 3120 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3121 { 3122 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3123 mode->hdisplay = 1366; 3124 mode->hsync_start--; 3125 mode->hsync_end--; 3126 drm_mode_set_name(mode); 3127 } 3128 } 3129 3130 static int 3131 drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid, 3132 const struct detailed_timing *timing) 3133 { 3134 int i, modes = 0; 3135 struct drm_display_mode *newmode; 3136 struct drm_device *dev = connector->dev; 3137 3138 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3139 const struct minimode *m = &extra_modes[i]; 3140 3141 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3142 if (!newmode) 3143 return modes; 3144 3145 drm_mode_fixup_1366x768(newmode); 3146 if (!mode_in_range(newmode, edid, timing) || 3147 !valid_inferred_mode(connector, newmode)) { 3148 drm_mode_destroy(dev, newmode); 3149 continue; 3150 } 3151 3152 drm_mode_probed_add(connector, newmode); 3153 modes++; 3154 } 3155 3156 return modes; 3157 } 3158 3159 static int 3160 drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid, 3161 const struct detailed_timing *timing) 3162 { 3163 int i, modes = 0; 3164 struct drm_display_mode *newmode; 3165 struct drm_device *dev = connector->dev; 3166 bool rb = drm_monitor_supports_rb(edid); 3167 3168 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3169 const struct minimode *m = &extra_modes[i]; 3170 3171 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3172 if (!newmode) 3173 return modes; 3174 3175 drm_mode_fixup_1366x768(newmode); 3176 if (!mode_in_range(newmode, edid, timing) || 3177 !valid_inferred_mode(connector, newmode)) { 3178 drm_mode_destroy(dev, newmode); 3179 continue; 3180 } 3181 3182 drm_mode_probed_add(connector, newmode); 3183 modes++; 3184 } 3185 3186 return modes; 3187 } 3188 3189 static void 3190 do_inferred_modes(const struct detailed_timing *timing, void *c) 3191 { 3192 struct detailed_mode_closure *closure = c; 3193 const struct detailed_non_pixel *data = &timing->data.other_data; 3194 const struct detailed_data_monitor_range *range = &data->data.range; 3195 3196 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3197 return; 3198 3199 closure->modes += drm_dmt_modes_for_range(closure->connector, 3200 closure->edid, 3201 timing); 3202 3203 if (!version_greater(closure->edid, 1, 1)) 3204 return; /* GTF not defined yet */ 3205 3206 switch (range->flags) { 3207 case 0x02: /* secondary gtf, XXX could do more */ 3208 case 0x00: /* default gtf */ 3209 closure->modes += drm_gtf_modes_for_range(closure->connector, 3210 closure->edid, 3211 timing); 3212 break; 3213 case 0x04: /* cvt, only in 1.4+ */ 3214 if (!version_greater(closure->edid, 1, 3)) 3215 break; 3216 3217 closure->modes += drm_cvt_modes_for_range(closure->connector, 3218 closure->edid, 3219 timing); 3220 break; 3221 case 0x01: /* just the ranges, no formula */ 3222 default: 3223 break; 3224 } 3225 } 3226 3227 static int 3228 add_inferred_modes(struct drm_connector *connector, const struct edid *edid) 3229 { 3230 struct detailed_mode_closure closure = { 3231 .connector = connector, 3232 .edid = edid, 3233 }; 3234 3235 if (version_greater(edid, 1, 0)) 3236 drm_for_each_detailed_block(edid, do_inferred_modes, &closure); 3237 3238 return closure.modes; 3239 } 3240 3241 static int 3242 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3243 { 3244 int i, j, m, modes = 0; 3245 struct drm_display_mode *mode; 3246 const u8 *est = ((const u8 *)timing) + 6; 3247 3248 for (i = 0; i < 6; i++) { 3249 for (j = 7; j >= 0; j--) { 3250 m = (i * 8) + (7 - j); 3251 if (m >= ARRAY_SIZE(est3_modes)) 3252 break; 3253 if (est[i] & (1 << j)) { 3254 mode = drm_mode_find_dmt(connector->dev, 3255 est3_modes[m].w, 3256 est3_modes[m].h, 3257 est3_modes[m].r, 3258 est3_modes[m].rb); 3259 if (mode) { 3260 drm_mode_probed_add(connector, mode); 3261 modes++; 3262 } 3263 } 3264 } 3265 } 3266 3267 return modes; 3268 } 3269 3270 static void 3271 do_established_modes(const struct detailed_timing *timing, void *c) 3272 { 3273 struct detailed_mode_closure *closure = c; 3274 3275 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3276 return; 3277 3278 closure->modes += drm_est3_modes(closure->connector, timing); 3279 } 3280 3281 /* 3282 * Get established modes from EDID and add them. Each EDID block contains a 3283 * bitmap of the supported "established modes" list (defined above). Tease them 3284 * out and add them to the global modes list. 3285 */ 3286 static int 3287 add_established_modes(struct drm_connector *connector, const struct edid *edid) 3288 { 3289 struct drm_device *dev = connector->dev; 3290 unsigned long est_bits = edid->established_timings.t1 | 3291 (edid->established_timings.t2 << 8) | 3292 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3293 int i, modes = 0; 3294 struct detailed_mode_closure closure = { 3295 .connector = connector, 3296 .edid = edid, 3297 }; 3298 3299 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3300 if (est_bits & (1<<i)) { 3301 struct drm_display_mode *newmode; 3302 3303 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3304 if (newmode) { 3305 drm_mode_probed_add(connector, newmode); 3306 modes++; 3307 } 3308 } 3309 } 3310 3311 if (version_greater(edid, 1, 0)) 3312 drm_for_each_detailed_block(edid, do_established_modes, 3313 &closure); 3314 3315 return modes + closure.modes; 3316 } 3317 3318 static void 3319 do_standard_modes(const struct detailed_timing *timing, void *c) 3320 { 3321 struct detailed_mode_closure *closure = c; 3322 const struct detailed_non_pixel *data = &timing->data.other_data; 3323 struct drm_connector *connector = closure->connector; 3324 const struct edid *edid = closure->edid; 3325 int i; 3326 3327 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3328 return; 3329 3330 for (i = 0; i < 6; i++) { 3331 const struct std_timing *std = &data->data.timings[i]; 3332 struct drm_display_mode *newmode; 3333 3334 newmode = drm_mode_std(connector, edid, std); 3335 if (newmode) { 3336 drm_mode_probed_add(connector, newmode); 3337 closure->modes++; 3338 } 3339 } 3340 } 3341 3342 /* 3343 * Get standard modes from EDID and add them. Standard modes can be calculated 3344 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3345 * add them to the list. 3346 */ 3347 static int 3348 add_standard_modes(struct drm_connector *connector, const struct edid *edid) 3349 { 3350 int i, modes = 0; 3351 struct detailed_mode_closure closure = { 3352 .connector = connector, 3353 .edid = edid, 3354 }; 3355 3356 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3357 struct drm_display_mode *newmode; 3358 3359 newmode = drm_mode_std(connector, edid, 3360 &edid->standard_timings[i]); 3361 if (newmode) { 3362 drm_mode_probed_add(connector, newmode); 3363 modes++; 3364 } 3365 } 3366 3367 if (version_greater(edid, 1, 0)) 3368 drm_for_each_detailed_block(edid, do_standard_modes, 3369 &closure); 3370 3371 /* XXX should also look for standard codes in VTB blocks */ 3372 3373 return modes + closure.modes; 3374 } 3375 3376 static int drm_cvt_modes(struct drm_connector *connector, 3377 const struct detailed_timing *timing) 3378 { 3379 int i, j, modes = 0; 3380 struct drm_display_mode *newmode; 3381 struct drm_device *dev = connector->dev; 3382 const struct cvt_timing *cvt; 3383 const int rates[] = { 60, 85, 75, 60, 50 }; 3384 const u8 empty[3] = { 0, 0, 0 }; 3385 3386 for (i = 0; i < 4; i++) { 3387 int width, height; 3388 3389 cvt = &(timing->data.other_data.data.cvt[i]); 3390 3391 if (!memcmp(cvt->code, empty, 3)) 3392 continue; 3393 3394 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3395 switch (cvt->code[1] & 0x0c) { 3396 /* default - because compiler doesn't see that we've enumerated all cases */ 3397 default: 3398 case 0x00: 3399 width = height * 4 / 3; 3400 break; 3401 case 0x04: 3402 width = height * 16 / 9; 3403 break; 3404 case 0x08: 3405 width = height * 16 / 10; 3406 break; 3407 case 0x0c: 3408 width = height * 15 / 9; 3409 break; 3410 } 3411 3412 for (j = 1; j < 5; j++) { 3413 if (cvt->code[2] & (1 << j)) { 3414 newmode = drm_cvt_mode(dev, width, height, 3415 rates[j], j == 0, 3416 false, false); 3417 if (newmode) { 3418 drm_mode_probed_add(connector, newmode); 3419 modes++; 3420 } 3421 } 3422 } 3423 } 3424 3425 return modes; 3426 } 3427 3428 static void 3429 do_cvt_mode(const struct detailed_timing *timing, void *c) 3430 { 3431 struct detailed_mode_closure *closure = c; 3432 3433 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 3434 return; 3435 3436 closure->modes += drm_cvt_modes(closure->connector, timing); 3437 } 3438 3439 static int 3440 add_cvt_modes(struct drm_connector *connector, const struct edid *edid) 3441 { 3442 struct detailed_mode_closure closure = { 3443 .connector = connector, 3444 .edid = edid, 3445 }; 3446 3447 if (version_greater(edid, 1, 2)) 3448 drm_for_each_detailed_block(edid, do_cvt_mode, &closure); 3449 3450 /* XXX should also look for CVT codes in VTB blocks */ 3451 3452 return closure.modes; 3453 } 3454 3455 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3456 3457 static void 3458 do_detailed_mode(const struct detailed_timing *timing, void *c) 3459 { 3460 struct detailed_mode_closure *closure = c; 3461 struct drm_display_mode *newmode; 3462 3463 if (!is_detailed_timing_descriptor(timing)) 3464 return; 3465 3466 newmode = drm_mode_detailed(closure->connector->dev, 3467 closure->edid, timing, 3468 closure->quirks); 3469 if (!newmode) 3470 return; 3471 3472 if (closure->preferred) 3473 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3474 3475 /* 3476 * Detailed modes are limited to 10kHz pixel clock resolution, 3477 * so fix up anything that looks like CEA/HDMI mode, but the clock 3478 * is just slightly off. 3479 */ 3480 fixup_detailed_cea_mode_clock(newmode); 3481 3482 drm_mode_probed_add(closure->connector, newmode); 3483 closure->modes++; 3484 closure->preferred = false; 3485 } 3486 3487 /* 3488 * add_detailed_modes - Add modes from detailed timings 3489 * @connector: attached connector 3490 * @edid: EDID block to scan 3491 * @quirks: quirks to apply 3492 */ 3493 static int 3494 add_detailed_modes(struct drm_connector *connector, const struct edid *edid, 3495 u32 quirks) 3496 { 3497 struct detailed_mode_closure closure = { 3498 .connector = connector, 3499 .edid = edid, 3500 .preferred = true, 3501 .quirks = quirks, 3502 }; 3503 3504 if (closure.preferred && !version_greater(edid, 1, 3)) 3505 closure.preferred = 3506 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3507 3508 drm_for_each_detailed_block(edid, do_detailed_mode, &closure); 3509 3510 return closure.modes; 3511 } 3512 3513 /* CTA-861-H Table 60 - CTA Tag Codes */ 3514 #define CTA_DB_AUDIO 1 3515 #define CTA_DB_VIDEO 2 3516 #define CTA_DB_VENDOR 3 3517 #define CTA_DB_SPEAKER 4 3518 #define CTA_DB_EXTENDED_TAG 7 3519 3520 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 3521 #define CTA_EXT_DB_VIDEO_CAP 0 3522 #define CTA_EXT_DB_VENDOR 1 3523 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 3524 #define CTA_EXT_DB_420_VIDEO_DATA 14 3525 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 3526 #define CTA_EXT_DB_HF_SCDB 0x79 3527 3528 #define EDID_BASIC_AUDIO (1 << 6) 3529 #define EDID_CEA_YCRCB444 (1 << 5) 3530 #define EDID_CEA_YCRCB422 (1 << 4) 3531 #define EDID_CEA_VCDB_QS (1 << 6) 3532 3533 /* 3534 * Search EDID for CEA extension block. 3535 */ 3536 const u8 *drm_find_edid_extension(const struct edid *edid, 3537 int ext_id, int *ext_index) 3538 { 3539 const u8 *edid_ext = NULL; 3540 int i; 3541 3542 /* No EDID or EDID extensions */ 3543 if (!edid || !edid_extension_block_count(edid)) 3544 return NULL; 3545 3546 /* Find CEA extension */ 3547 for (i = *ext_index; i < edid_extension_block_count(edid); i++) { 3548 edid_ext = edid_extension_block_data(edid, i); 3549 if (edid_block_tag(edid_ext) == ext_id) 3550 break; 3551 } 3552 3553 if (i >= edid_extension_block_count(edid)) 3554 return NULL; 3555 3556 *ext_index = i + 1; 3557 3558 return edid_ext; 3559 } 3560 3561 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 3562 static bool drm_edid_has_cta_extension(const struct edid *edid) 3563 { 3564 const struct displayid_block *block; 3565 struct displayid_iter iter; 3566 int ext_index = 0; 3567 bool found = false; 3568 3569 /* Look for a top level CEA extension block */ 3570 if (drm_find_edid_extension(edid, CEA_EXT, &ext_index)) 3571 return true; 3572 3573 /* CEA blocks can also be found embedded in a DisplayID block */ 3574 displayid_iter_edid_begin(edid, &iter); 3575 displayid_iter_for_each(block, &iter) { 3576 if (block->tag == DATA_BLOCK_CTA) { 3577 found = true; 3578 break; 3579 } 3580 } 3581 displayid_iter_end(&iter); 3582 3583 return found; 3584 } 3585 3586 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3587 { 3588 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3589 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3590 3591 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3592 return &edid_cea_modes_1[vic - 1]; 3593 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3594 return &edid_cea_modes_193[vic - 193]; 3595 return NULL; 3596 } 3597 3598 static u8 cea_num_vics(void) 3599 { 3600 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3601 } 3602 3603 static u8 cea_next_vic(u8 vic) 3604 { 3605 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3606 vic = 193; 3607 return vic; 3608 } 3609 3610 /* 3611 * Calculate the alternate clock for the CEA mode 3612 * (60Hz vs. 59.94Hz etc.) 3613 */ 3614 static unsigned int 3615 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3616 { 3617 unsigned int clock = cea_mode->clock; 3618 3619 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 3620 return clock; 3621 3622 /* 3623 * edid_cea_modes contains the 59.94Hz 3624 * variant for 240 and 480 line modes, 3625 * and the 60Hz variant otherwise. 3626 */ 3627 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3628 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3629 else 3630 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3631 3632 return clock; 3633 } 3634 3635 static bool 3636 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3637 { 3638 /* 3639 * For certain VICs the spec allows the vertical 3640 * front porch to vary by one or two lines. 3641 * 3642 * cea_modes[] stores the variant with the shortest 3643 * vertical front porch. We can adjust the mode to 3644 * get the other variants by simply increasing the 3645 * vertical front porch length. 3646 */ 3647 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3648 cea_mode_for_vic(9)->vtotal != 262 || 3649 cea_mode_for_vic(12)->vtotal != 262 || 3650 cea_mode_for_vic(13)->vtotal != 262 || 3651 cea_mode_for_vic(23)->vtotal != 312 || 3652 cea_mode_for_vic(24)->vtotal != 312 || 3653 cea_mode_for_vic(27)->vtotal != 312 || 3654 cea_mode_for_vic(28)->vtotal != 312); 3655 3656 if (((vic == 8 || vic == 9 || 3657 vic == 12 || vic == 13) && mode->vtotal < 263) || 3658 ((vic == 23 || vic == 24 || 3659 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3660 mode->vsync_start++; 3661 mode->vsync_end++; 3662 mode->vtotal++; 3663 3664 return true; 3665 } 3666 3667 return false; 3668 } 3669 3670 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3671 unsigned int clock_tolerance) 3672 { 3673 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3674 u8 vic; 3675 3676 if (!to_match->clock) 3677 return 0; 3678 3679 if (to_match->picture_aspect_ratio) 3680 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3681 3682 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3683 struct drm_display_mode cea_mode; 3684 unsigned int clock1, clock2; 3685 3686 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 3687 3688 /* Check both 60Hz and 59.94Hz */ 3689 clock1 = cea_mode.clock; 3690 clock2 = cea_mode_alternate_clock(&cea_mode); 3691 3692 if (abs(to_match->clock - clock1) > clock_tolerance && 3693 abs(to_match->clock - clock2) > clock_tolerance) 3694 continue; 3695 3696 do { 3697 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3698 return vic; 3699 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3700 } 3701 3702 return 0; 3703 } 3704 3705 /** 3706 * drm_match_cea_mode - look for a CEA mode matching given mode 3707 * @to_match: display mode 3708 * 3709 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3710 * mode. 3711 */ 3712 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3713 { 3714 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3715 u8 vic; 3716 3717 if (!to_match->clock) 3718 return 0; 3719 3720 if (to_match->picture_aspect_ratio) 3721 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3722 3723 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3724 struct drm_display_mode cea_mode; 3725 unsigned int clock1, clock2; 3726 3727 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 3728 3729 /* Check both 60Hz and 59.94Hz */ 3730 clock1 = cea_mode.clock; 3731 clock2 = cea_mode_alternate_clock(&cea_mode); 3732 3733 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3734 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3735 continue; 3736 3737 do { 3738 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3739 return vic; 3740 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3741 } 3742 3743 return 0; 3744 } 3745 EXPORT_SYMBOL(drm_match_cea_mode); 3746 3747 static bool drm_valid_cea_vic(u8 vic) 3748 { 3749 return cea_mode_for_vic(vic) != NULL; 3750 } 3751 3752 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3753 { 3754 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3755 3756 if (mode) 3757 return mode->picture_aspect_ratio; 3758 3759 return HDMI_PICTURE_ASPECT_NONE; 3760 } 3761 3762 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3763 { 3764 return edid_4k_modes[video_code].picture_aspect_ratio; 3765 } 3766 3767 /* 3768 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3769 * specific block). 3770 */ 3771 static unsigned int 3772 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3773 { 3774 return cea_mode_alternate_clock(hdmi_mode); 3775 } 3776 3777 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3778 unsigned int clock_tolerance) 3779 { 3780 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3781 u8 vic; 3782 3783 if (!to_match->clock) 3784 return 0; 3785 3786 if (to_match->picture_aspect_ratio) 3787 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3788 3789 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3790 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3791 unsigned int clock1, clock2; 3792 3793 /* Make sure to also match alternate clocks */ 3794 clock1 = hdmi_mode->clock; 3795 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3796 3797 if (abs(to_match->clock - clock1) > clock_tolerance && 3798 abs(to_match->clock - clock2) > clock_tolerance) 3799 continue; 3800 3801 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3802 return vic; 3803 } 3804 3805 return 0; 3806 } 3807 3808 /* 3809 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3810 * @to_match: display mode 3811 * 3812 * An HDMI mode is one defined in the HDMI vendor specific block. 3813 * 3814 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3815 */ 3816 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3817 { 3818 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3819 u8 vic; 3820 3821 if (!to_match->clock) 3822 return 0; 3823 3824 if (to_match->picture_aspect_ratio) 3825 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3826 3827 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3828 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3829 unsigned int clock1, clock2; 3830 3831 /* Make sure to also match alternate clocks */ 3832 clock1 = hdmi_mode->clock; 3833 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3834 3835 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3836 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3837 drm_mode_match(to_match, hdmi_mode, match_flags)) 3838 return vic; 3839 } 3840 return 0; 3841 } 3842 3843 static bool drm_valid_hdmi_vic(u8 vic) 3844 { 3845 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3846 } 3847 3848 static int 3849 add_alternate_cea_modes(struct drm_connector *connector, const struct edid *edid) 3850 { 3851 struct drm_device *dev = connector->dev; 3852 struct drm_display_mode *mode, *tmp; 3853 LIST_HEAD(list); 3854 int modes = 0; 3855 3856 /* Don't add CTA modes if the CTA extension block is missing */ 3857 if (!drm_edid_has_cta_extension(edid)) 3858 return 0; 3859 3860 /* 3861 * Go through all probed modes and create a new mode 3862 * with the alternate clock for certain CEA modes. 3863 */ 3864 list_for_each_entry(mode, &connector->probed_modes, head) { 3865 const struct drm_display_mode *cea_mode = NULL; 3866 struct drm_display_mode *newmode; 3867 u8 vic = drm_match_cea_mode(mode); 3868 unsigned int clock1, clock2; 3869 3870 if (drm_valid_cea_vic(vic)) { 3871 cea_mode = cea_mode_for_vic(vic); 3872 clock2 = cea_mode_alternate_clock(cea_mode); 3873 } else { 3874 vic = drm_match_hdmi_mode(mode); 3875 if (drm_valid_hdmi_vic(vic)) { 3876 cea_mode = &edid_4k_modes[vic]; 3877 clock2 = hdmi_mode_alternate_clock(cea_mode); 3878 } 3879 } 3880 3881 if (!cea_mode) 3882 continue; 3883 3884 clock1 = cea_mode->clock; 3885 3886 if (clock1 == clock2) 3887 continue; 3888 3889 if (mode->clock != clock1 && mode->clock != clock2) 3890 continue; 3891 3892 newmode = drm_mode_duplicate(dev, cea_mode); 3893 if (!newmode) 3894 continue; 3895 3896 /* Carry over the stereo flags */ 3897 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3898 3899 /* 3900 * The current mode could be either variant. Make 3901 * sure to pick the "other" clock for the new mode. 3902 */ 3903 if (mode->clock != clock1) 3904 newmode->clock = clock1; 3905 else 3906 newmode->clock = clock2; 3907 3908 list_add_tail(&newmode->head, &list); 3909 } 3910 3911 list_for_each_entry_safe(mode, tmp, &list, head) { 3912 list_del(&mode->head); 3913 drm_mode_probed_add(connector, mode); 3914 modes++; 3915 } 3916 3917 return modes; 3918 } 3919 3920 static u8 svd_to_vic(u8 svd) 3921 { 3922 /* 0-6 bit vic, 7th bit native mode indicator */ 3923 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3924 return svd & 127; 3925 3926 return svd; 3927 } 3928 3929 static struct drm_display_mode * 3930 drm_display_mode_from_vic_index(struct drm_connector *connector, 3931 const u8 *video_db, u8 video_len, 3932 u8 video_index) 3933 { 3934 struct drm_device *dev = connector->dev; 3935 struct drm_display_mode *newmode; 3936 u8 vic; 3937 3938 if (video_db == NULL || video_index >= video_len) 3939 return NULL; 3940 3941 /* CEA modes are numbered 1..127 */ 3942 vic = svd_to_vic(video_db[video_index]); 3943 if (!drm_valid_cea_vic(vic)) 3944 return NULL; 3945 3946 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3947 if (!newmode) 3948 return NULL; 3949 3950 return newmode; 3951 } 3952 3953 /* 3954 * do_y420vdb_modes - Parse YCBCR 420 only modes 3955 * @connector: connector corresponding to the HDMI sink 3956 * @svds: start of the data block of CEA YCBCR 420 VDB 3957 * @len: length of the CEA YCBCR 420 VDB 3958 * 3959 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3960 * which contains modes which can be supported in YCBCR 420 3961 * output format only. 3962 */ 3963 static int do_y420vdb_modes(struct drm_connector *connector, 3964 const u8 *svds, u8 svds_len) 3965 { 3966 int modes = 0, i; 3967 struct drm_device *dev = connector->dev; 3968 struct drm_display_info *info = &connector->display_info; 3969 struct drm_hdmi_info *hdmi = &info->hdmi; 3970 3971 for (i = 0; i < svds_len; i++) { 3972 u8 vic = svd_to_vic(svds[i]); 3973 struct drm_display_mode *newmode; 3974 3975 if (!drm_valid_cea_vic(vic)) 3976 continue; 3977 3978 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3979 if (!newmode) 3980 break; 3981 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3982 drm_mode_probed_add(connector, newmode); 3983 modes++; 3984 } 3985 3986 if (modes > 0) 3987 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 3988 return modes; 3989 } 3990 3991 /* 3992 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3993 * @connector: connector corresponding to the HDMI sink 3994 * @vic: CEA vic for the video mode to be added in the map 3995 * 3996 * Makes an entry for a videomode in the YCBCR 420 bitmap 3997 */ 3998 static void 3999 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 4000 { 4001 u8 vic = svd_to_vic(svd); 4002 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4003 4004 if (!drm_valid_cea_vic(vic)) 4005 return; 4006 4007 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 4008 } 4009 4010 /** 4011 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4012 * @dev: DRM device 4013 * @video_code: CEA VIC of the mode 4014 * 4015 * Creates a new mode matching the specified CEA VIC. 4016 * 4017 * Returns: A new drm_display_mode on success or NULL on failure 4018 */ 4019 struct drm_display_mode * 4020 drm_display_mode_from_cea_vic(struct drm_device *dev, 4021 u8 video_code) 4022 { 4023 const struct drm_display_mode *cea_mode; 4024 struct drm_display_mode *newmode; 4025 4026 cea_mode = cea_mode_for_vic(video_code); 4027 if (!cea_mode) 4028 return NULL; 4029 4030 newmode = drm_mode_duplicate(dev, cea_mode); 4031 if (!newmode) 4032 return NULL; 4033 4034 return newmode; 4035 } 4036 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4037 4038 static int 4039 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 4040 { 4041 int i, modes = 0; 4042 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4043 4044 for (i = 0; i < len; i++) { 4045 struct drm_display_mode *mode; 4046 4047 mode = drm_display_mode_from_vic_index(connector, db, len, i); 4048 if (mode) { 4049 /* 4050 * YCBCR420 capability block contains a bitmap which 4051 * gives the index of CEA modes from CEA VDB, which 4052 * can support YCBCR 420 sampling output also (apart 4053 * from RGB/YCBCR444 etc). 4054 * For example, if the bit 0 in bitmap is set, 4055 * first mode in VDB can support YCBCR420 output too. 4056 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 4057 */ 4058 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 4059 drm_add_cmdb_modes(connector, db[i]); 4060 4061 drm_mode_probed_add(connector, mode); 4062 modes++; 4063 } 4064 } 4065 4066 return modes; 4067 } 4068 4069 struct stereo_mandatory_mode { 4070 int width, height, vrefresh; 4071 unsigned int flags; 4072 }; 4073 4074 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4075 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4076 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4077 { 1920, 1080, 50, 4078 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4079 { 1920, 1080, 60, 4080 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4081 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4082 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4083 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4084 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4085 }; 4086 4087 static bool 4088 stereo_match_mandatory(const struct drm_display_mode *mode, 4089 const struct stereo_mandatory_mode *stereo_mode) 4090 { 4091 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4092 4093 return mode->hdisplay == stereo_mode->width && 4094 mode->vdisplay == stereo_mode->height && 4095 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4096 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4097 } 4098 4099 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4100 { 4101 struct drm_device *dev = connector->dev; 4102 const struct drm_display_mode *mode; 4103 struct list_head stereo_modes; 4104 int modes = 0, i; 4105 4106 INIT_LIST_HEAD(&stereo_modes); 4107 4108 list_for_each_entry(mode, &connector->probed_modes, head) { 4109 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4110 const struct stereo_mandatory_mode *mandatory; 4111 struct drm_display_mode *new_mode; 4112 4113 if (!stereo_match_mandatory(mode, 4114 &stereo_mandatory_modes[i])) 4115 continue; 4116 4117 mandatory = &stereo_mandatory_modes[i]; 4118 new_mode = drm_mode_duplicate(dev, mode); 4119 if (!new_mode) 4120 continue; 4121 4122 new_mode->flags |= mandatory->flags; 4123 list_add_tail(&new_mode->head, &stereo_modes); 4124 modes++; 4125 } 4126 } 4127 4128 list_splice_tail(&stereo_modes, &connector->probed_modes); 4129 4130 return modes; 4131 } 4132 4133 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4134 { 4135 struct drm_device *dev = connector->dev; 4136 struct drm_display_mode *newmode; 4137 4138 if (!drm_valid_hdmi_vic(vic)) { 4139 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 4140 return 0; 4141 } 4142 4143 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4144 if (!newmode) 4145 return 0; 4146 4147 drm_mode_probed_add(connector, newmode); 4148 4149 return 1; 4150 } 4151 4152 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4153 const u8 *video_db, u8 video_len, u8 video_index) 4154 { 4155 struct drm_display_mode *newmode; 4156 int modes = 0; 4157 4158 if (structure & (1 << 0)) { 4159 newmode = drm_display_mode_from_vic_index(connector, video_db, 4160 video_len, 4161 video_index); 4162 if (newmode) { 4163 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4164 drm_mode_probed_add(connector, newmode); 4165 modes++; 4166 } 4167 } 4168 if (structure & (1 << 6)) { 4169 newmode = drm_display_mode_from_vic_index(connector, video_db, 4170 video_len, 4171 video_index); 4172 if (newmode) { 4173 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4174 drm_mode_probed_add(connector, newmode); 4175 modes++; 4176 } 4177 } 4178 if (structure & (1 << 8)) { 4179 newmode = drm_display_mode_from_vic_index(connector, video_db, 4180 video_len, 4181 video_index); 4182 if (newmode) { 4183 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4184 drm_mode_probed_add(connector, newmode); 4185 modes++; 4186 } 4187 } 4188 4189 return modes; 4190 } 4191 4192 /* 4193 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4194 * @connector: connector corresponding to the HDMI sink 4195 * @db: start of the CEA vendor specific block 4196 * @len: length of the CEA block payload, ie. one can access up to db[len] 4197 * 4198 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4199 * also adds the stereo 3d modes when applicable. 4200 */ 4201 static int 4202 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 4203 const u8 *video_db, u8 video_len) 4204 { 4205 struct drm_display_info *info = &connector->display_info; 4206 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4207 u8 vic_len, hdmi_3d_len = 0; 4208 u16 mask; 4209 u16 structure_all; 4210 4211 if (len < 8) 4212 goto out; 4213 4214 /* no HDMI_Video_Present */ 4215 if (!(db[8] & (1 << 5))) 4216 goto out; 4217 4218 /* Latency_Fields_Present */ 4219 if (db[8] & (1 << 7)) 4220 offset += 2; 4221 4222 /* I_Latency_Fields_Present */ 4223 if (db[8] & (1 << 6)) 4224 offset += 2; 4225 4226 /* the declared length is not long enough for the 2 first bytes 4227 * of additional video format capabilities */ 4228 if (len < (8 + offset + 2)) 4229 goto out; 4230 4231 /* 3D_Present */ 4232 offset++; 4233 if (db[8 + offset] & (1 << 7)) { 4234 modes += add_hdmi_mandatory_stereo_modes(connector); 4235 4236 /* 3D_Multi_present */ 4237 multi_present = (db[8 + offset] & 0x60) >> 5; 4238 } 4239 4240 offset++; 4241 vic_len = db[8 + offset] >> 5; 4242 hdmi_3d_len = db[8 + offset] & 0x1f; 4243 4244 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4245 u8 vic; 4246 4247 vic = db[9 + offset + i]; 4248 modes += add_hdmi_mode(connector, vic); 4249 } 4250 offset += 1 + vic_len; 4251 4252 if (multi_present == 1) 4253 multi_len = 2; 4254 else if (multi_present == 2) 4255 multi_len = 4; 4256 else 4257 multi_len = 0; 4258 4259 if (len < (8 + offset + hdmi_3d_len - 1)) 4260 goto out; 4261 4262 if (hdmi_3d_len < multi_len) 4263 goto out; 4264 4265 if (multi_present == 1 || multi_present == 2) { 4266 /* 3D_Structure_ALL */ 4267 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4268 4269 /* check if 3D_MASK is present */ 4270 if (multi_present == 2) 4271 mask = (db[10 + offset] << 8) | db[11 + offset]; 4272 else 4273 mask = 0xffff; 4274 4275 for (i = 0; i < 16; i++) { 4276 if (mask & (1 << i)) 4277 modes += add_3d_struct_modes(connector, 4278 structure_all, 4279 video_db, 4280 video_len, i); 4281 } 4282 } 4283 4284 offset += multi_len; 4285 4286 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4287 int vic_index; 4288 struct drm_display_mode *newmode = NULL; 4289 unsigned int newflag = 0; 4290 bool detail_present; 4291 4292 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4293 4294 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4295 break; 4296 4297 /* 2D_VIC_order_X */ 4298 vic_index = db[8 + offset + i] >> 4; 4299 4300 /* 3D_Structure_X */ 4301 switch (db[8 + offset + i] & 0x0f) { 4302 case 0: 4303 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4304 break; 4305 case 6: 4306 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4307 break; 4308 case 8: 4309 /* 3D_Detail_X */ 4310 if ((db[9 + offset + i] >> 4) == 1) 4311 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4312 break; 4313 } 4314 4315 if (newflag != 0) { 4316 newmode = drm_display_mode_from_vic_index(connector, 4317 video_db, 4318 video_len, 4319 vic_index); 4320 4321 if (newmode) { 4322 newmode->flags |= newflag; 4323 drm_mode_probed_add(connector, newmode); 4324 modes++; 4325 } 4326 } 4327 4328 if (detail_present) 4329 i++; 4330 } 4331 4332 out: 4333 if (modes > 0) 4334 info->has_hdmi_infoframe = true; 4335 return modes; 4336 } 4337 4338 static int 4339 cea_revision(const u8 *cea) 4340 { 4341 /* 4342 * FIXME is this correct for the DispID variant? 4343 * The DispID spec doesn't really specify whether 4344 * this is the revision of the CEA extension or 4345 * the DispID CEA data block. And the only value 4346 * given as an example is 0. 4347 */ 4348 return cea[1]; 4349 } 4350 4351 /* 4352 * CTA Data Block iterator. 4353 * 4354 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4355 * CTA Data Blocks. 4356 * 4357 * struct cea_db *db: 4358 * struct cea_db_iter iter; 4359 * 4360 * cea_db_iter_edid_begin(edid, &iter); 4361 * cea_db_iter_for_each(db, &iter) { 4362 * // do stuff with db 4363 * } 4364 * cea_db_iter_end(&iter); 4365 */ 4366 struct cea_db_iter { 4367 struct drm_edid_iter edid_iter; 4368 struct displayid_iter displayid_iter; 4369 4370 /* Current Data Block Collection. */ 4371 const u8 *collection; 4372 4373 /* Current Data Block index in current collection. */ 4374 int index; 4375 4376 /* End index in current collection. */ 4377 int end; 4378 }; 4379 4380 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4381 struct cea_db { 4382 u8 tag_length; 4383 u8 data[]; 4384 } __packed; 4385 4386 static int cea_db_tag(const struct cea_db *db) 4387 { 4388 return db->tag_length >> 5; 4389 } 4390 4391 static int cea_db_payload_len(const void *_db) 4392 { 4393 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4394 const struct cea_db *db = _db; 4395 4396 return db->tag_length & 0x1f; 4397 } 4398 4399 static const void *cea_db_data(const struct cea_db *db) 4400 { 4401 return db->data; 4402 } 4403 4404 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4405 { 4406 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4407 cea_db_payload_len(db) >= 1 && 4408 db->data[0] == tag; 4409 } 4410 4411 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4412 { 4413 const u8 *data = cea_db_data(db); 4414 4415 return cea_db_tag(db) == CTA_DB_VENDOR && 4416 cea_db_payload_len(db) >= 3 && 4417 oui(data[2], data[1], data[0]) == vendor_oui; 4418 } 4419 4420 static void cea_db_iter_edid_begin(const struct edid *edid, struct cea_db_iter *iter) 4421 { 4422 memset(iter, 0, sizeof(*iter)); 4423 4424 drm_edid_iter_begin(edid, &iter->edid_iter); 4425 displayid_iter_edid_begin(edid, &iter->displayid_iter); 4426 } 4427 4428 static const struct cea_db * 4429 __cea_db_iter_current_block(const struct cea_db_iter *iter) 4430 { 4431 const struct cea_db *db; 4432 4433 if (!iter->collection) 4434 return NULL; 4435 4436 db = (const struct cea_db *)&iter->collection[iter->index]; 4437 4438 if (iter->index + sizeof(*db) <= iter->end && 4439 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4440 return db; 4441 4442 return NULL; 4443 } 4444 4445 /* 4446 * References: 4447 * - VESA E-EDID v1.4 4448 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4449 */ 4450 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 4451 { 4452 const u8 *ext; 4453 4454 drm_edid_iter_for_each(ext, &iter->edid_iter) { 4455 /* Only support CTA Extension revision 3+ */ 4456 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 4457 continue; 4458 4459 iter->index = 4; 4460 iter->end = ext[2]; 4461 if (iter->end == 0) 4462 iter->end = 127; 4463 if (iter->end < 4 || iter->end > 127) 4464 continue; 4465 4466 return ext; 4467 } 4468 4469 return NULL; 4470 } 4471 4472 /* 4473 * References: 4474 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 4475 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 4476 * 4477 * Note that the above do not specify any connection between DisplayID Data 4478 * Block revision and CTA Extension versions. 4479 */ 4480 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 4481 { 4482 const struct displayid_block *block; 4483 4484 displayid_iter_for_each(block, &iter->displayid_iter) { 4485 if (block->tag != DATA_BLOCK_CTA) 4486 continue; 4487 4488 /* 4489 * The displayid iterator has already verified the block bounds 4490 * in displayid_iter_block(). 4491 */ 4492 iter->index = sizeof(*block); 4493 iter->end = iter->index + block->num_bytes; 4494 4495 return block; 4496 } 4497 4498 return NULL; 4499 } 4500 4501 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 4502 { 4503 const struct cea_db *db; 4504 4505 if (iter->collection) { 4506 /* Current collection should always be valid. */ 4507 db = __cea_db_iter_current_block(iter); 4508 if (WARN_ON(!db)) { 4509 iter->collection = NULL; 4510 return NULL; 4511 } 4512 4513 /* Next block in CTA Data Block Collection */ 4514 iter->index += sizeof(*db) + cea_db_payload_len(db); 4515 4516 db = __cea_db_iter_current_block(iter); 4517 if (db) 4518 return db; 4519 } 4520 4521 for (;;) { 4522 /* 4523 * Find the next CTA Data Block Collection. First iterate all 4524 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 4525 * 4526 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 4527 * Extension, it's recommended that DisplayID extensions are 4528 * exposed after all of the CTA Extensions. 4529 */ 4530 iter->collection = __cea_db_iter_edid_next(iter); 4531 if (!iter->collection) 4532 iter->collection = __cea_db_iter_displayid_next(iter); 4533 4534 if (!iter->collection) 4535 return NULL; 4536 4537 db = __cea_db_iter_current_block(iter); 4538 if (db) 4539 return db; 4540 } 4541 } 4542 4543 #define cea_db_iter_for_each(__db, __iter) \ 4544 while (((__db) = __cea_db_iter_next(__iter))) 4545 4546 static void cea_db_iter_end(struct cea_db_iter *iter) 4547 { 4548 displayid_iter_end(&iter->displayid_iter); 4549 drm_edid_iter_end(&iter->edid_iter); 4550 4551 memset(iter, 0, sizeof(*iter)); 4552 } 4553 4554 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 4555 { 4556 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 4557 cea_db_payload_len(db) >= 5; 4558 } 4559 4560 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 4561 { 4562 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 4563 cea_db_payload_len(db) >= 7; 4564 } 4565 4566 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 4567 { 4568 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 4569 cea_db_payload_len(db) == 21; 4570 } 4571 4572 static bool cea_db_is_vcdb(const struct cea_db *db) 4573 { 4574 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 4575 cea_db_payload_len(db) == 2; 4576 } 4577 4578 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 4579 { 4580 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 4581 cea_db_payload_len(db) >= 7; 4582 } 4583 4584 static bool cea_db_is_y420cmdb(const struct cea_db *db) 4585 { 4586 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 4587 } 4588 4589 static bool cea_db_is_y420vdb(const struct cea_db *db) 4590 { 4591 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 4592 } 4593 4594 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 4595 { 4596 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 4597 cea_db_payload_len(db) >= 3; 4598 } 4599 4600 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4601 const u8 *db) 4602 { 4603 struct drm_display_info *info = &connector->display_info; 4604 struct drm_hdmi_info *hdmi = &info->hdmi; 4605 u8 map_len = cea_db_payload_len(db) - 1; 4606 u8 count; 4607 u64 map = 0; 4608 4609 if (map_len == 0) { 4610 /* All CEA modes support ycbcr420 sampling also.*/ 4611 hdmi->y420_cmdb_map = U64_MAX; 4612 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4613 return; 4614 } 4615 4616 /* 4617 * This map indicates which of the existing CEA block modes 4618 * from VDB can support YCBCR420 output too. So if bit=0 is 4619 * set, first mode from VDB can support YCBCR420 output too. 4620 * We will parse and keep this map, before parsing VDB itself 4621 * to avoid going through the same block again and again. 4622 * 4623 * Spec is not clear about max possible size of this block. 4624 * Clamping max bitmap block size at 8 bytes. Every byte can 4625 * address 8 CEA modes, in this way this map can address 4626 * 8*8 = first 64 SVDs. 4627 */ 4628 if (WARN_ON_ONCE(map_len > 8)) 4629 map_len = 8; 4630 4631 for (count = 0; count < map_len; count++) 4632 map |= (u64)db[2 + count] << (8 * count); 4633 4634 if (map) 4635 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 4636 4637 hdmi->y420_cmdb_map = map; 4638 } 4639 4640 static int 4641 add_cea_modes(struct drm_connector *connector, const struct edid *edid) 4642 { 4643 const struct cea_db *db; 4644 struct cea_db_iter iter; 4645 int modes = 0; 4646 4647 cea_db_iter_edid_begin(edid, &iter); 4648 cea_db_iter_for_each(db, &iter) { 4649 const u8 *hdmi = NULL, *video = NULL; 4650 u8 hdmi_len = 0, video_len = 0; 4651 4652 if (cea_db_tag(db) == CTA_DB_VIDEO) { 4653 video = cea_db_data(db); 4654 video_len = cea_db_payload_len(db); 4655 modes += do_cea_modes(connector, video, video_len); 4656 } else if (cea_db_is_hdmi_vsdb(db)) { 4657 /* FIXME: Switch to use cea_db_data() */ 4658 hdmi = (const u8 *)db; 4659 hdmi_len = cea_db_payload_len(db); 4660 } else if (cea_db_is_y420vdb(db)) { 4661 const u8 *vdb420 = cea_db_data(db) + 1; 4662 4663 /* Add 4:2:0(only) modes present in EDID */ 4664 modes += do_y420vdb_modes(connector, vdb420, 4665 cea_db_payload_len(db) - 1); 4666 } 4667 4668 /* 4669 * We parse the HDMI VSDB after having added the cea modes as we 4670 * will be patching their flags when the sink supports stereo 4671 * 3D. 4672 */ 4673 if (hdmi) 4674 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, 4675 video, video_len); 4676 } 4677 cea_db_iter_end(&iter); 4678 4679 return modes; 4680 } 4681 4682 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4683 { 4684 const struct drm_display_mode *cea_mode; 4685 int clock1, clock2, clock; 4686 u8 vic; 4687 const char *type; 4688 4689 /* 4690 * allow 5kHz clock difference either way to account for 4691 * the 10kHz clock resolution limit of detailed timings. 4692 */ 4693 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4694 if (drm_valid_cea_vic(vic)) { 4695 type = "CEA"; 4696 cea_mode = cea_mode_for_vic(vic); 4697 clock1 = cea_mode->clock; 4698 clock2 = cea_mode_alternate_clock(cea_mode); 4699 } else { 4700 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4701 if (drm_valid_hdmi_vic(vic)) { 4702 type = "HDMI"; 4703 cea_mode = &edid_4k_modes[vic]; 4704 clock1 = cea_mode->clock; 4705 clock2 = hdmi_mode_alternate_clock(cea_mode); 4706 } else { 4707 return; 4708 } 4709 } 4710 4711 /* pick whichever is closest */ 4712 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4713 clock = clock1; 4714 else 4715 clock = clock2; 4716 4717 if (mode->clock == clock) 4718 return; 4719 4720 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4721 type, vic, mode->clock, clock); 4722 mode->clock = clock; 4723 } 4724 4725 static uint8_t eotf_supported(const u8 *edid_ext) 4726 { 4727 return edid_ext[2] & 4728 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4729 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4730 BIT(HDMI_EOTF_SMPTE_ST2084) | 4731 BIT(HDMI_EOTF_BT_2100_HLG)); 4732 } 4733 4734 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4735 { 4736 return edid_ext[3] & 4737 BIT(HDMI_STATIC_METADATA_TYPE1); 4738 } 4739 4740 static void 4741 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4742 { 4743 u16 len; 4744 4745 len = cea_db_payload_len(db); 4746 4747 connector->hdr_sink_metadata.hdmi_type1.eotf = 4748 eotf_supported(db); 4749 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4750 hdr_metadata_type(db); 4751 4752 if (len >= 4) 4753 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4754 if (len >= 5) 4755 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4756 if (len >= 6) 4757 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4758 } 4759 4760 static void 4761 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4762 { 4763 u8 len = cea_db_payload_len(db); 4764 4765 if (len >= 6 && (db[6] & (1 << 7))) 4766 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4767 if (len >= 8) { 4768 connector->latency_present[0] = db[8] >> 7; 4769 connector->latency_present[1] = (db[8] >> 6) & 1; 4770 } 4771 if (len >= 9) 4772 connector->video_latency[0] = db[9]; 4773 if (len >= 10) 4774 connector->audio_latency[0] = db[10]; 4775 if (len >= 11) 4776 connector->video_latency[1] = db[11]; 4777 if (len >= 12) 4778 connector->audio_latency[1] = db[12]; 4779 4780 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4781 "video latency %d %d, " 4782 "audio latency %d %d\n", 4783 connector->latency_present[0], 4784 connector->latency_present[1], 4785 connector->video_latency[0], 4786 connector->video_latency[1], 4787 connector->audio_latency[0], 4788 connector->audio_latency[1]); 4789 } 4790 4791 static void 4792 monitor_name(const struct detailed_timing *timing, void *data) 4793 { 4794 const char **res = data; 4795 4796 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 4797 return; 4798 4799 *res = timing->data.other_data.data.str.str; 4800 } 4801 4802 static int get_monitor_name(const struct edid *edid, char name[13]) 4803 { 4804 const char *edid_name = NULL; 4805 int mnl; 4806 4807 if (!edid || !name) 4808 return 0; 4809 4810 drm_for_each_detailed_block(edid, monitor_name, &edid_name); 4811 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4812 if (edid_name[mnl] == 0x0a) 4813 break; 4814 4815 name[mnl] = edid_name[mnl]; 4816 } 4817 4818 return mnl; 4819 } 4820 4821 /** 4822 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4823 * @edid: monitor EDID information 4824 * @name: pointer to a character array to hold the name of the monitor 4825 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4826 * 4827 */ 4828 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 4829 { 4830 int name_length; 4831 char buf[13]; 4832 4833 if (bufsize <= 0) 4834 return; 4835 4836 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4837 memcpy(name, buf, name_length); 4838 name[name_length] = '\0'; 4839 } 4840 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4841 4842 static void clear_eld(struct drm_connector *connector) 4843 { 4844 memset(connector->eld, 0, sizeof(connector->eld)); 4845 4846 connector->latency_present[0] = false; 4847 connector->latency_present[1] = false; 4848 connector->video_latency[0] = 0; 4849 connector->audio_latency[0] = 0; 4850 connector->video_latency[1] = 0; 4851 connector->audio_latency[1] = 0; 4852 } 4853 4854 /* 4855 * drm_edid_to_eld - build ELD from EDID 4856 * @connector: connector corresponding to the HDMI/DP sink 4857 * @edid: EDID to parse 4858 * 4859 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4860 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4861 */ 4862 static void drm_edid_to_eld(struct drm_connector *connector, 4863 const struct edid *edid) 4864 { 4865 const struct drm_display_info *info = &connector->display_info; 4866 const struct cea_db *db; 4867 struct cea_db_iter iter; 4868 uint8_t *eld = connector->eld; 4869 int total_sad_count = 0; 4870 int mnl; 4871 4872 clear_eld(connector); 4873 4874 if (!edid) 4875 return; 4876 4877 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4878 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4879 4880 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 4881 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4882 4883 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4884 4885 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4886 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4887 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4888 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4889 4890 cea_db_iter_edid_begin(edid, &iter); 4891 cea_db_iter_for_each(db, &iter) { 4892 const u8 *data = cea_db_data(db); 4893 int len = cea_db_payload_len(db); 4894 int sad_count; 4895 4896 switch (cea_db_tag(db)) { 4897 case CTA_DB_AUDIO: 4898 /* Audio Data Block, contains SADs */ 4899 sad_count = min(len / 3, 15 - total_sad_count); 4900 if (sad_count >= 1) 4901 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4902 data, sad_count * 3); 4903 total_sad_count += sad_count; 4904 break; 4905 case CTA_DB_SPEAKER: 4906 /* Speaker Allocation Data Block */ 4907 if (len >= 1) 4908 eld[DRM_ELD_SPEAKER] = data[0]; 4909 break; 4910 case CTA_DB_VENDOR: 4911 /* HDMI Vendor-Specific Data Block */ 4912 if (cea_db_is_hdmi_vsdb(db)) 4913 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 4914 break; 4915 default: 4916 break; 4917 } 4918 } 4919 cea_db_iter_end(&iter); 4920 4921 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4922 4923 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4924 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4925 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4926 else 4927 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4928 4929 eld[DRM_ELD_BASELINE_ELD_LEN] = 4930 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4931 4932 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4933 drm_eld_size(eld), total_sad_count); 4934 } 4935 4936 /** 4937 * drm_edid_to_sad - extracts SADs from EDID 4938 * @edid: EDID to parse 4939 * @sads: pointer that will be set to the extracted SADs 4940 * 4941 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4942 * 4943 * Note: The returned pointer needs to be freed using kfree(). 4944 * 4945 * Return: The number of found SADs or negative number on error. 4946 */ 4947 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 4948 { 4949 const struct cea_db *db; 4950 struct cea_db_iter iter; 4951 int count = 0; 4952 4953 cea_db_iter_edid_begin(edid, &iter); 4954 cea_db_iter_for_each(db, &iter) { 4955 if (cea_db_tag(db) == CTA_DB_AUDIO) { 4956 int j; 4957 4958 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 4959 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4960 if (!*sads) 4961 return -ENOMEM; 4962 for (j = 0; j < count; j++) { 4963 const u8 *sad = &db->data[j * 3]; 4964 4965 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4966 (*sads)[j].channels = sad[0] & 0x7; 4967 (*sads)[j].freq = sad[1] & 0x7F; 4968 (*sads)[j].byte2 = sad[2]; 4969 } 4970 break; 4971 } 4972 } 4973 cea_db_iter_end(&iter); 4974 4975 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 4976 4977 return count; 4978 } 4979 EXPORT_SYMBOL(drm_edid_to_sad); 4980 4981 /** 4982 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4983 * @edid: EDID to parse 4984 * @sadb: pointer to the speaker block 4985 * 4986 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4987 * 4988 * Note: The returned pointer needs to be freed using kfree(). 4989 * 4990 * Return: The number of found Speaker Allocation Blocks or negative number on 4991 * error. 4992 */ 4993 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 4994 { 4995 const struct cea_db *db; 4996 struct cea_db_iter iter; 4997 int count = 0; 4998 4999 cea_db_iter_edid_begin(edid, &iter); 5000 cea_db_iter_for_each(db, &iter) { 5001 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5002 cea_db_payload_len(db) == 3) { 5003 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5004 GFP_KERNEL); 5005 if (!*sadb) 5006 return -ENOMEM; 5007 count = cea_db_payload_len(db); 5008 break; 5009 } 5010 } 5011 cea_db_iter_end(&iter); 5012 5013 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5014 5015 return count; 5016 } 5017 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5018 5019 /** 5020 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5021 * @connector: connector associated with the HDMI/DP sink 5022 * @mode: the display mode 5023 * 5024 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5025 * the sink doesn't support audio or video. 5026 */ 5027 int drm_av_sync_delay(struct drm_connector *connector, 5028 const struct drm_display_mode *mode) 5029 { 5030 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5031 int a, v; 5032 5033 if (!connector->latency_present[0]) 5034 return 0; 5035 if (!connector->latency_present[1]) 5036 i = 0; 5037 5038 a = connector->audio_latency[i]; 5039 v = connector->video_latency[i]; 5040 5041 /* 5042 * HDMI/DP sink doesn't support audio or video? 5043 */ 5044 if (a == 255 || v == 255) 5045 return 0; 5046 5047 /* 5048 * Convert raw EDID values to millisecond. 5049 * Treat unknown latency as 0ms. 5050 */ 5051 if (a) 5052 a = min(2 * (a - 1), 500); 5053 if (v) 5054 v = min(2 * (v - 1), 500); 5055 5056 return max(v - a, 0); 5057 } 5058 EXPORT_SYMBOL(drm_av_sync_delay); 5059 5060 /** 5061 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5062 * @edid: monitor EDID information 5063 * 5064 * Parse the CEA extension according to CEA-861-B. 5065 * 5066 * Drivers that have added the modes parsed from EDID to drm_display_info 5067 * should use &drm_display_info.is_hdmi instead of calling this function. 5068 * 5069 * Return: True if the monitor is HDMI, false if not or unknown. 5070 */ 5071 bool drm_detect_hdmi_monitor(const struct edid *edid) 5072 { 5073 const struct cea_db *db; 5074 struct cea_db_iter iter; 5075 bool hdmi = false; 5076 5077 /* 5078 * Because HDMI identifier is in Vendor Specific Block, 5079 * search it from all data blocks of CEA extension. 5080 */ 5081 cea_db_iter_edid_begin(edid, &iter); 5082 cea_db_iter_for_each(db, &iter) { 5083 if (cea_db_is_hdmi_vsdb(db)) { 5084 hdmi = true; 5085 break; 5086 } 5087 } 5088 cea_db_iter_end(&iter); 5089 5090 return hdmi; 5091 } 5092 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5093 5094 /** 5095 * drm_detect_monitor_audio - check monitor audio capability 5096 * @edid: EDID block to scan 5097 * 5098 * Monitor should have CEA extension block. 5099 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5100 * audio' only. If there is any audio extension block and supported 5101 * audio format, assume at least 'basic audio' support, even if 'basic 5102 * audio' is not defined in EDID. 5103 * 5104 * Return: True if the monitor supports audio, false otherwise. 5105 */ 5106 bool drm_detect_monitor_audio(const struct edid *edid) 5107 { 5108 struct drm_edid_iter edid_iter; 5109 const struct cea_db *db; 5110 struct cea_db_iter iter; 5111 const u8 *edid_ext; 5112 bool has_audio = false; 5113 5114 drm_edid_iter_begin(edid, &edid_iter); 5115 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5116 if (edid_ext[0] == CEA_EXT) { 5117 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5118 if (has_audio) 5119 break; 5120 } 5121 } 5122 drm_edid_iter_end(&edid_iter); 5123 5124 if (has_audio) { 5125 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5126 goto end; 5127 } 5128 5129 cea_db_iter_edid_begin(edid, &iter); 5130 cea_db_iter_for_each(db, &iter) { 5131 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5132 const u8 *data = cea_db_data(db); 5133 int i; 5134 5135 for (i = 0; i < cea_db_payload_len(db); i += 3) 5136 DRM_DEBUG_KMS("CEA audio format %d\n", 5137 (data[i] >> 3) & 0xf); 5138 has_audio = true; 5139 break; 5140 } 5141 } 5142 cea_db_iter_end(&iter); 5143 5144 end: 5145 return has_audio; 5146 } 5147 EXPORT_SYMBOL(drm_detect_monitor_audio); 5148 5149 5150 /** 5151 * drm_default_rgb_quant_range - default RGB quantization range 5152 * @mode: display mode 5153 * 5154 * Determine the default RGB quantization range for the mode, 5155 * as specified in CEA-861. 5156 * 5157 * Return: The default RGB quantization range for the mode 5158 */ 5159 enum hdmi_quantization_range 5160 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5161 { 5162 /* All CEA modes other than VIC 1 use limited quantization range. */ 5163 return drm_match_cea_mode(mode) > 1 ? 5164 HDMI_QUANTIZATION_RANGE_LIMITED : 5165 HDMI_QUANTIZATION_RANGE_FULL; 5166 } 5167 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5168 5169 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5170 { 5171 struct drm_display_info *info = &connector->display_info; 5172 5173 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 5174 5175 if (db[2] & EDID_CEA_VCDB_QS) 5176 info->rgb_quant_range_selectable = true; 5177 } 5178 5179 static 5180 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5181 { 5182 switch (max_frl_rate) { 5183 case 1: 5184 *max_lanes = 3; 5185 *max_rate_per_lane = 3; 5186 break; 5187 case 2: 5188 *max_lanes = 3; 5189 *max_rate_per_lane = 6; 5190 break; 5191 case 3: 5192 *max_lanes = 4; 5193 *max_rate_per_lane = 6; 5194 break; 5195 case 4: 5196 *max_lanes = 4; 5197 *max_rate_per_lane = 8; 5198 break; 5199 case 5: 5200 *max_lanes = 4; 5201 *max_rate_per_lane = 10; 5202 break; 5203 case 6: 5204 *max_lanes = 4; 5205 *max_rate_per_lane = 12; 5206 break; 5207 case 0: 5208 default: 5209 *max_lanes = 0; 5210 *max_rate_per_lane = 0; 5211 } 5212 } 5213 5214 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5215 const u8 *db) 5216 { 5217 u8 dc_mask; 5218 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5219 5220 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5221 hdmi->y420_dc_modes = dc_mask; 5222 } 5223 5224 /* Sink Capability Data Structure */ 5225 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 5226 const u8 *hf_scds) 5227 { 5228 struct drm_display_info *display = &connector->display_info; 5229 struct drm_hdmi_info *hdmi = &display->hdmi; 5230 5231 display->has_hdmi_infoframe = true; 5232 5233 if (hf_scds[6] & 0x80) { 5234 hdmi->scdc.supported = true; 5235 if (hf_scds[6] & 0x40) 5236 hdmi->scdc.read_request = true; 5237 } 5238 5239 /* 5240 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 5241 * And as per the spec, three factors confirm this: 5242 * * Availability of a HF-VSDB block in EDID (check) 5243 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 5244 * * SCDC support available (let's check) 5245 * Lets check it out. 5246 */ 5247 5248 if (hf_scds[5]) { 5249 /* max clock is 5000 KHz times block value */ 5250 u32 max_tmds_clock = hf_scds[5] * 5000; 5251 struct drm_scdc *scdc = &hdmi->scdc; 5252 5253 if (max_tmds_clock > 340000) { 5254 display->max_tmds_clock = max_tmds_clock; 5255 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 5256 display->max_tmds_clock); 5257 } 5258 5259 if (scdc->supported) { 5260 scdc->scrambling.supported = true; 5261 5262 /* Few sinks support scrambling for clocks < 340M */ 5263 if ((hf_scds[6] & 0x8)) 5264 scdc->scrambling.low_rates = true; 5265 } 5266 } 5267 5268 if (hf_scds[7]) { 5269 u8 max_frl_rate; 5270 u8 dsc_max_frl_rate; 5271 u8 dsc_max_slices; 5272 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 5273 5274 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); 5275 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 5276 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 5277 &hdmi->max_frl_rate_per_lane); 5278 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 5279 5280 if (hdmi_dsc->v_1p2) { 5281 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 5282 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 5283 5284 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 5285 hdmi_dsc->bpc_supported = 16; 5286 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 5287 hdmi_dsc->bpc_supported = 12; 5288 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 5289 hdmi_dsc->bpc_supported = 10; 5290 else 5291 hdmi_dsc->bpc_supported = 0; 5292 5293 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 5294 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 5295 &hdmi_dsc->max_frl_rate_per_lane); 5296 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 5297 5298 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 5299 switch (dsc_max_slices) { 5300 case 1: 5301 hdmi_dsc->max_slices = 1; 5302 hdmi_dsc->clk_per_slice = 340; 5303 break; 5304 case 2: 5305 hdmi_dsc->max_slices = 2; 5306 hdmi_dsc->clk_per_slice = 340; 5307 break; 5308 case 3: 5309 hdmi_dsc->max_slices = 4; 5310 hdmi_dsc->clk_per_slice = 340; 5311 break; 5312 case 4: 5313 hdmi_dsc->max_slices = 8; 5314 hdmi_dsc->clk_per_slice = 340; 5315 break; 5316 case 5: 5317 hdmi_dsc->max_slices = 8; 5318 hdmi_dsc->clk_per_slice = 400; 5319 break; 5320 case 6: 5321 hdmi_dsc->max_slices = 12; 5322 hdmi_dsc->clk_per_slice = 400; 5323 break; 5324 case 7: 5325 hdmi_dsc->max_slices = 16; 5326 hdmi_dsc->clk_per_slice = 400; 5327 break; 5328 case 0: 5329 default: 5330 hdmi_dsc->max_slices = 0; 5331 hdmi_dsc->clk_per_slice = 0; 5332 } 5333 } 5334 } 5335 5336 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 5337 } 5338 5339 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 5340 const u8 *hdmi) 5341 { 5342 struct drm_display_info *info = &connector->display_info; 5343 unsigned int dc_bpc = 0; 5344 5345 /* HDMI supports at least 8 bpc */ 5346 info->bpc = 8; 5347 5348 if (cea_db_payload_len(hdmi) < 6) 5349 return; 5350 5351 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 5352 dc_bpc = 10; 5353 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 5354 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 5355 connector->name); 5356 } 5357 5358 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 5359 dc_bpc = 12; 5360 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 5361 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 5362 connector->name); 5363 } 5364 5365 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 5366 dc_bpc = 16; 5367 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 5368 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 5369 connector->name); 5370 } 5371 5372 if (dc_bpc == 0) { 5373 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 5374 connector->name); 5375 return; 5376 } 5377 5378 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 5379 connector->name, dc_bpc); 5380 info->bpc = dc_bpc; 5381 5382 /* YCRCB444 is optional according to spec. */ 5383 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 5384 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 5385 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 5386 connector->name); 5387 } 5388 5389 /* 5390 * Spec says that if any deep color mode is supported at all, 5391 * then deep color 36 bit must be supported. 5392 */ 5393 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 5394 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 5395 connector->name); 5396 } 5397 } 5398 5399 static void 5400 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 5401 { 5402 struct drm_display_info *info = &connector->display_info; 5403 u8 len = cea_db_payload_len(db); 5404 5405 info->is_hdmi = true; 5406 5407 if (len >= 6) 5408 info->dvi_dual = db[6] & 1; 5409 if (len >= 7) 5410 info->max_tmds_clock = db[7] * 5000; 5411 5412 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 5413 "max TMDS clock %d kHz\n", 5414 info->dvi_dual, 5415 info->max_tmds_clock); 5416 5417 drm_parse_hdmi_deep_color_info(connector, db); 5418 } 5419 5420 /* 5421 * See EDID extension for head-mounted and specialized monitors, specified at: 5422 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 5423 */ 5424 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 5425 const u8 *db) 5426 { 5427 struct drm_display_info *info = &connector->display_info; 5428 u8 version = db[4]; 5429 bool desktop_usage = db[5] & BIT(6); 5430 5431 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 5432 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 5433 info->non_desktop = true; 5434 5435 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n", 5436 version, db[5]); 5437 } 5438 5439 static void drm_parse_cea_ext(struct drm_connector *connector, 5440 const struct edid *edid) 5441 { 5442 struct drm_display_info *info = &connector->display_info; 5443 struct drm_edid_iter edid_iter; 5444 const struct cea_db *db; 5445 struct cea_db_iter iter; 5446 const u8 *edid_ext; 5447 5448 drm_edid_iter_begin(edid, &edid_iter); 5449 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5450 if (edid_ext[0] != CEA_EXT) 5451 continue; 5452 5453 if (!info->cea_rev) 5454 info->cea_rev = edid_ext[1]; 5455 5456 if (info->cea_rev != edid_ext[1]) 5457 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n", 5458 info->cea_rev, edid_ext[1]); 5459 5460 /* The existence of a CTA extension should imply RGB support */ 5461 info->color_formats = DRM_COLOR_FORMAT_RGB444; 5462 if (edid_ext[3] & EDID_CEA_YCRCB444) 5463 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5464 if (edid_ext[3] & EDID_CEA_YCRCB422) 5465 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5466 } 5467 drm_edid_iter_end(&edid_iter); 5468 5469 cea_db_iter_edid_begin(edid, &iter); 5470 cea_db_iter_for_each(db, &iter) { 5471 /* FIXME: convert parsers to use struct cea_db */ 5472 const u8 *data = (const u8 *)db; 5473 5474 if (cea_db_is_hdmi_vsdb(db)) 5475 drm_parse_hdmi_vsdb_video(connector, data); 5476 if (cea_db_is_hdmi_forum_vsdb(db) || 5477 cea_db_is_hdmi_forum_scdb(db)) 5478 drm_parse_hdmi_forum_scds(connector, data); 5479 if (cea_db_is_microsoft_vsdb(db)) 5480 drm_parse_microsoft_vsdb(connector, data); 5481 if (cea_db_is_y420cmdb(db)) 5482 drm_parse_y420cmdb_bitmap(connector, data); 5483 if (cea_db_is_vcdb(db)) 5484 drm_parse_vcdb(connector, data); 5485 if (cea_db_is_hdmi_hdr_metadata_block(db)) 5486 drm_parse_hdr_metadata_block(connector, data); 5487 } 5488 cea_db_iter_end(&iter); 5489 } 5490 5491 static 5492 void get_monitor_range(const struct detailed_timing *timing, 5493 void *info_monitor_range) 5494 { 5495 struct drm_monitor_range_info *monitor_range = info_monitor_range; 5496 const struct detailed_non_pixel *data = &timing->data.other_data; 5497 const struct detailed_data_monitor_range *range = &data->data.range; 5498 5499 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 5500 return; 5501 5502 /* 5503 * Check for flag range limits only. If flag == 1 then 5504 * no additional timing information provided. 5505 * Default GTF, GTF Secondary curve and CVT are not 5506 * supported 5507 */ 5508 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 5509 return; 5510 5511 monitor_range->min_vfreq = range->min_vfreq; 5512 monitor_range->max_vfreq = range->max_vfreq; 5513 } 5514 5515 static 5516 void drm_get_monitor_range(struct drm_connector *connector, 5517 const struct edid *edid) 5518 { 5519 struct drm_display_info *info = &connector->display_info; 5520 5521 if (!version_greater(edid, 1, 1)) 5522 return; 5523 5524 drm_for_each_detailed_block(edid, get_monitor_range, 5525 &info->monitor_range); 5526 5527 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 5528 info->monitor_range.min_vfreq, 5529 info->monitor_range.max_vfreq); 5530 } 5531 5532 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 5533 const struct displayid_block *block) 5534 { 5535 struct displayid_vesa_vendor_specific_block *vesa = 5536 (struct displayid_vesa_vendor_specific_block *)block; 5537 struct drm_display_info *info = &connector->display_info; 5538 5539 if (block->num_bytes < 3) { 5540 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n", 5541 block->num_bytes); 5542 return; 5543 } 5544 5545 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 5546 return; 5547 5548 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 5549 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n"); 5550 return; 5551 } 5552 5553 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 5554 default: 5555 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n"); 5556 fallthrough; 5557 case 0: 5558 info->mso_stream_count = 0; 5559 break; 5560 case 1: 5561 info->mso_stream_count = 2; /* 2 or 4 links */ 5562 break; 5563 case 2: 5564 info->mso_stream_count = 4; /* 4 links */ 5565 break; 5566 } 5567 5568 if (!info->mso_stream_count) { 5569 info->mso_pixel_overlap = 0; 5570 return; 5571 } 5572 5573 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 5574 if (info->mso_pixel_overlap > 8) { 5575 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n", 5576 info->mso_pixel_overlap); 5577 info->mso_pixel_overlap = 8; 5578 } 5579 5580 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n", 5581 info->mso_stream_count, info->mso_pixel_overlap); 5582 } 5583 5584 static void drm_update_mso(struct drm_connector *connector, const struct edid *edid) 5585 { 5586 const struct displayid_block *block; 5587 struct displayid_iter iter; 5588 5589 displayid_iter_edid_begin(edid, &iter); 5590 displayid_iter_for_each(block, &iter) { 5591 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 5592 drm_parse_vesa_mso_data(connector, block); 5593 } 5594 displayid_iter_end(&iter); 5595 } 5596 5597 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 5598 * all of the values which would have been set from EDID 5599 */ 5600 void 5601 drm_reset_display_info(struct drm_connector *connector) 5602 { 5603 struct drm_display_info *info = &connector->display_info; 5604 5605 info->width_mm = 0; 5606 info->height_mm = 0; 5607 5608 info->bpc = 0; 5609 info->color_formats = 0; 5610 info->cea_rev = 0; 5611 info->max_tmds_clock = 0; 5612 info->dvi_dual = false; 5613 info->is_hdmi = false; 5614 info->has_hdmi_infoframe = false; 5615 info->rgb_quant_range_selectable = false; 5616 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5617 5618 info->edid_hdmi_rgb444_dc_modes = 0; 5619 info->edid_hdmi_ycbcr444_dc_modes = 0; 5620 5621 info->non_desktop = 0; 5622 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5623 5624 info->mso_stream_count = 0; 5625 info->mso_pixel_overlap = 0; 5626 } 5627 5628 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5629 { 5630 struct drm_display_info *info = &connector->display_info; 5631 5632 u32 quirks = edid_get_quirks(edid); 5633 5634 drm_reset_display_info(connector); 5635 5636 info->width_mm = edid->width_cm * 10; 5637 info->height_mm = edid->height_cm * 10; 5638 5639 drm_get_monitor_range(connector, edid); 5640 5641 if (edid->revision < 3) 5642 goto out; 5643 5644 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5645 goto out; 5646 5647 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5648 drm_parse_cea_ext(connector, edid); 5649 5650 /* 5651 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5652 * 5653 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5654 * tells us to assume 8 bpc color depth if the EDID doesn't have 5655 * extensions which tell otherwise. 5656 */ 5657 if (info->bpc == 0 && edid->revision == 3 && 5658 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5659 info->bpc = 8; 5660 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5661 connector->name, info->bpc); 5662 } 5663 5664 /* Only defined for 1.4 with digital displays */ 5665 if (edid->revision < 4) 5666 goto out; 5667 5668 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5669 case DRM_EDID_DIGITAL_DEPTH_6: 5670 info->bpc = 6; 5671 break; 5672 case DRM_EDID_DIGITAL_DEPTH_8: 5673 info->bpc = 8; 5674 break; 5675 case DRM_EDID_DIGITAL_DEPTH_10: 5676 info->bpc = 10; 5677 break; 5678 case DRM_EDID_DIGITAL_DEPTH_12: 5679 info->bpc = 12; 5680 break; 5681 case DRM_EDID_DIGITAL_DEPTH_14: 5682 info->bpc = 14; 5683 break; 5684 case DRM_EDID_DIGITAL_DEPTH_16: 5685 info->bpc = 16; 5686 break; 5687 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5688 default: 5689 info->bpc = 0; 5690 break; 5691 } 5692 5693 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5694 connector->name, info->bpc); 5695 5696 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5697 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 5698 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5699 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 5700 5701 drm_update_mso(connector, edid); 5702 5703 out: 5704 if (quirks & EDID_QUIRK_NON_DESKTOP) { 5705 drm_dbg_kms(connector->dev, "Non-desktop display%s\n", 5706 info->non_desktop ? " (redundant quirk)" : ""); 5707 info->non_desktop = true; 5708 } 5709 5710 return quirks; 5711 } 5712 5713 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5714 struct displayid_detailed_timings_1 *timings, 5715 bool type_7) 5716 { 5717 struct drm_display_mode *mode; 5718 unsigned pixel_clock = (timings->pixel_clock[0] | 5719 (timings->pixel_clock[1] << 8) | 5720 (timings->pixel_clock[2] << 16)) + 1; 5721 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5722 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5723 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5724 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5725 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5726 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5727 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5728 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5729 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5730 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5731 5732 mode = drm_mode_create(dev); 5733 if (!mode) 5734 return NULL; 5735 5736 /* resolution is kHz for type VII, and 10 kHz for type I */ 5737 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 5738 mode->hdisplay = hactive; 5739 mode->hsync_start = mode->hdisplay + hsync; 5740 mode->hsync_end = mode->hsync_start + hsync_width; 5741 mode->htotal = mode->hdisplay + hblank; 5742 5743 mode->vdisplay = vactive; 5744 mode->vsync_start = mode->vdisplay + vsync; 5745 mode->vsync_end = mode->vsync_start + vsync_width; 5746 mode->vtotal = mode->vdisplay + vblank; 5747 5748 mode->flags = 0; 5749 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5750 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5751 mode->type = DRM_MODE_TYPE_DRIVER; 5752 5753 if (timings->flags & 0x80) 5754 mode->type |= DRM_MODE_TYPE_PREFERRED; 5755 drm_mode_set_name(mode); 5756 5757 return mode; 5758 } 5759 5760 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5761 const struct displayid_block *block) 5762 { 5763 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5764 int i; 5765 int num_timings; 5766 struct drm_display_mode *newmode; 5767 int num_modes = 0; 5768 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 5769 /* blocks must be multiple of 20 bytes length */ 5770 if (block->num_bytes % 20) 5771 return 0; 5772 5773 num_timings = block->num_bytes / 20; 5774 for (i = 0; i < num_timings; i++) { 5775 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5776 5777 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 5778 if (!newmode) 5779 continue; 5780 5781 drm_mode_probed_add(connector, newmode); 5782 num_modes++; 5783 } 5784 return num_modes; 5785 } 5786 5787 static int add_displayid_detailed_modes(struct drm_connector *connector, 5788 const struct edid *edid) 5789 { 5790 const struct displayid_block *block; 5791 struct displayid_iter iter; 5792 int num_modes = 0; 5793 5794 displayid_iter_edid_begin(edid, &iter); 5795 displayid_iter_for_each(block, &iter) { 5796 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 5797 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 5798 num_modes += add_displayid_detailed_1_modes(connector, block); 5799 } 5800 displayid_iter_end(&iter); 5801 5802 return num_modes; 5803 } 5804 5805 static int drm_edid_connector_update(struct drm_connector *connector, 5806 const struct edid *edid) 5807 { 5808 int num_modes = 0; 5809 u32 quirks; 5810 5811 if (edid == NULL) { 5812 drm_reset_display_info(connector); 5813 clear_eld(connector); 5814 return 0; 5815 } 5816 5817 /* 5818 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5819 * To avoid multiple parsing of same block, lets parse that map 5820 * from sink info, before parsing CEA modes. 5821 */ 5822 quirks = drm_add_display_info(connector, edid); 5823 5824 /* Depends on info->cea_rev set by drm_add_display_info() above */ 5825 drm_edid_to_eld(connector, edid); 5826 5827 /* 5828 * EDID spec says modes should be preferred in this order: 5829 * - preferred detailed mode 5830 * - other detailed modes from base block 5831 * - detailed modes from extension blocks 5832 * - CVT 3-byte code modes 5833 * - standard timing codes 5834 * - established timing codes 5835 * - modes inferred from GTF or CVT range information 5836 * 5837 * We get this pretty much right. 5838 * 5839 * XXX order for additional mode types in extension blocks? 5840 */ 5841 num_modes += add_detailed_modes(connector, edid, quirks); 5842 num_modes += add_cvt_modes(connector, edid); 5843 num_modes += add_standard_modes(connector, edid); 5844 num_modes += add_established_modes(connector, edid); 5845 num_modes += add_cea_modes(connector, edid); 5846 num_modes += add_alternate_cea_modes(connector, edid); 5847 num_modes += add_displayid_detailed_modes(connector, edid); 5848 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5849 num_modes += add_inferred_modes(connector, edid); 5850 5851 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5852 edid_fixup_preferred(connector, quirks); 5853 5854 if (quirks & EDID_QUIRK_FORCE_6BPC) 5855 connector->display_info.bpc = 6; 5856 5857 if (quirks & EDID_QUIRK_FORCE_8BPC) 5858 connector->display_info.bpc = 8; 5859 5860 if (quirks & EDID_QUIRK_FORCE_10BPC) 5861 connector->display_info.bpc = 10; 5862 5863 if (quirks & EDID_QUIRK_FORCE_12BPC) 5864 connector->display_info.bpc = 12; 5865 5866 return num_modes; 5867 } 5868 5869 /** 5870 * drm_add_edid_modes - add modes from EDID data, if available 5871 * @connector: connector we're probing 5872 * @edid: EDID data 5873 * 5874 * Add the specified modes to the connector's mode list. Also fills out the 5875 * &drm_display_info structure and ELD in @connector with any information which 5876 * can be derived from the edid. 5877 * 5878 * Return: The number of modes added or 0 if we couldn't find any. 5879 */ 5880 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5881 { 5882 if (edid && !drm_edid_is_valid(edid)) { 5883 drm_warn(connector->dev, "%s: EDID invalid.\n", 5884 connector->name); 5885 edid = NULL; 5886 } 5887 5888 return drm_edid_connector_update(connector, edid); 5889 } 5890 EXPORT_SYMBOL(drm_add_edid_modes); 5891 5892 /** 5893 * drm_add_modes_noedid - add modes for the connectors without EDID 5894 * @connector: connector we're probing 5895 * @hdisplay: the horizontal display limit 5896 * @vdisplay: the vertical display limit 5897 * 5898 * Add the specified modes to the connector's mode list. Only when the 5899 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5900 * 5901 * Return: The number of modes added or 0 if we couldn't find any. 5902 */ 5903 int drm_add_modes_noedid(struct drm_connector *connector, 5904 int hdisplay, int vdisplay) 5905 { 5906 int i, count, num_modes = 0; 5907 struct drm_display_mode *mode; 5908 struct drm_device *dev = connector->dev; 5909 5910 count = ARRAY_SIZE(drm_dmt_modes); 5911 if (hdisplay < 0) 5912 hdisplay = 0; 5913 if (vdisplay < 0) 5914 vdisplay = 0; 5915 5916 for (i = 0; i < count; i++) { 5917 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5918 5919 if (hdisplay && vdisplay) { 5920 /* 5921 * Only when two are valid, they will be used to check 5922 * whether the mode should be added to the mode list of 5923 * the connector. 5924 */ 5925 if (ptr->hdisplay > hdisplay || 5926 ptr->vdisplay > vdisplay) 5927 continue; 5928 } 5929 if (drm_mode_vrefresh(ptr) > 61) 5930 continue; 5931 mode = drm_mode_duplicate(dev, ptr); 5932 if (mode) { 5933 drm_mode_probed_add(connector, mode); 5934 num_modes++; 5935 } 5936 } 5937 return num_modes; 5938 } 5939 EXPORT_SYMBOL(drm_add_modes_noedid); 5940 5941 /** 5942 * drm_set_preferred_mode - Sets the preferred mode of a connector 5943 * @connector: connector whose mode list should be processed 5944 * @hpref: horizontal resolution of preferred mode 5945 * @vpref: vertical resolution of preferred mode 5946 * 5947 * Marks a mode as preferred if it matches the resolution specified by @hpref 5948 * and @vpref. 5949 */ 5950 void drm_set_preferred_mode(struct drm_connector *connector, 5951 int hpref, int vpref) 5952 { 5953 struct drm_display_mode *mode; 5954 5955 list_for_each_entry(mode, &connector->probed_modes, head) { 5956 if (mode->hdisplay == hpref && 5957 mode->vdisplay == vpref) 5958 mode->type |= DRM_MODE_TYPE_PREFERRED; 5959 } 5960 } 5961 EXPORT_SYMBOL(drm_set_preferred_mode); 5962 5963 static bool is_hdmi2_sink(const struct drm_connector *connector) 5964 { 5965 /* 5966 * FIXME: sil-sii8620 doesn't have a connector around when 5967 * we need one, so we have to be prepared for a NULL connector. 5968 */ 5969 if (!connector) 5970 return true; 5971 5972 return connector->display_info.hdmi.scdc.supported || 5973 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 5974 } 5975 5976 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 5977 const struct drm_display_mode *mode) 5978 { 5979 bool has_hdmi_infoframe = connector ? 5980 connector->display_info.has_hdmi_infoframe : false; 5981 5982 if (!has_hdmi_infoframe) 5983 return 0; 5984 5985 /* No HDMI VIC when signalling 3D video format */ 5986 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5987 return 0; 5988 5989 return drm_match_hdmi_mode(mode); 5990 } 5991 5992 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 5993 const struct drm_display_mode *mode) 5994 { 5995 u8 vic; 5996 5997 /* 5998 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5999 * we should send its VIC in vendor infoframes, else send the 6000 * VIC in AVI infoframes. Lets check if this mode is present in 6001 * HDMI 1.4b 4K modes 6002 */ 6003 if (drm_mode_hdmi_vic(connector, mode)) 6004 return 0; 6005 6006 vic = drm_match_cea_mode(mode); 6007 6008 /* 6009 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 6010 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 6011 * have to make sure we dont break HDMI 1.4 sinks. 6012 */ 6013 if (!is_hdmi2_sink(connector) && vic > 64) 6014 return 0; 6015 6016 return vic; 6017 } 6018 6019 /** 6020 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 6021 * data from a DRM display mode 6022 * @frame: HDMI AVI infoframe 6023 * @connector: the connector 6024 * @mode: DRM display mode 6025 * 6026 * Return: 0 on success or a negative error code on failure. 6027 */ 6028 int 6029 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 6030 const struct drm_connector *connector, 6031 const struct drm_display_mode *mode) 6032 { 6033 enum hdmi_picture_aspect picture_aspect; 6034 u8 vic, hdmi_vic; 6035 6036 if (!frame || !mode) 6037 return -EINVAL; 6038 6039 hdmi_avi_infoframe_init(frame); 6040 6041 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 6042 frame->pixel_repeat = 1; 6043 6044 vic = drm_mode_cea_vic(connector, mode); 6045 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 6046 6047 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6048 6049 /* 6050 * As some drivers don't support atomic, we can't use connector state. 6051 * So just initialize the frame with default values, just the same way 6052 * as it's done with other properties here. 6053 */ 6054 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 6055 frame->itc = 0; 6056 6057 /* 6058 * Populate picture aspect ratio from either 6059 * user input (if specified) or from the CEA/HDMI mode lists. 6060 */ 6061 picture_aspect = mode->picture_aspect_ratio; 6062 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 6063 if (vic) 6064 picture_aspect = drm_get_cea_aspect_ratio(vic); 6065 else if (hdmi_vic) 6066 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 6067 } 6068 6069 /* 6070 * The infoframe can't convey anything but none, 4:3 6071 * and 16:9, so if the user has asked for anything else 6072 * we can only satisfy it by specifying the right VIC. 6073 */ 6074 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 6075 if (vic) { 6076 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 6077 return -EINVAL; 6078 } else if (hdmi_vic) { 6079 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 6080 return -EINVAL; 6081 } else { 6082 return -EINVAL; 6083 } 6084 6085 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 6086 } 6087 6088 frame->video_code = vic; 6089 frame->picture_aspect = picture_aspect; 6090 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 6091 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 6092 6093 return 0; 6094 } 6095 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 6096 6097 /** 6098 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 6099 * quantization range information 6100 * @frame: HDMI AVI infoframe 6101 * @connector: the connector 6102 * @mode: DRM display mode 6103 * @rgb_quant_range: RGB quantization range (Q) 6104 */ 6105 void 6106 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 6107 const struct drm_connector *connector, 6108 const struct drm_display_mode *mode, 6109 enum hdmi_quantization_range rgb_quant_range) 6110 { 6111 const struct drm_display_info *info = &connector->display_info; 6112 6113 /* 6114 * CEA-861: 6115 * "A Source shall not send a non-zero Q value that does not correspond 6116 * to the default RGB Quantization Range for the transmitted Picture 6117 * unless the Sink indicates support for the Q bit in a Video 6118 * Capabilities Data Block." 6119 * 6120 * HDMI 2.0 recommends sending non-zero Q when it does match the 6121 * default RGB quantization range for the mode, even when QS=0. 6122 */ 6123 if (info->rgb_quant_range_selectable || 6124 rgb_quant_range == drm_default_rgb_quant_range(mode)) 6125 frame->quantization_range = rgb_quant_range; 6126 else 6127 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 6128 6129 /* 6130 * CEA-861-F: 6131 * "When transmitting any RGB colorimetry, the Source should set the 6132 * YQ-field to match the RGB Quantization Range being transmitted 6133 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 6134 * set YQ=1) and the Sink shall ignore the YQ-field." 6135 * 6136 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 6137 * by non-zero YQ when receiving RGB. There doesn't seem to be any 6138 * good way to tell which version of CEA-861 the sink supports, so 6139 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 6140 * on on CEA-861-F. 6141 */ 6142 if (!is_hdmi2_sink(connector) || 6143 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 6144 frame->ycc_quantization_range = 6145 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 6146 else 6147 frame->ycc_quantization_range = 6148 HDMI_YCC_QUANTIZATION_RANGE_FULL; 6149 } 6150 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 6151 6152 static enum hdmi_3d_structure 6153 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 6154 { 6155 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 6156 6157 switch (layout) { 6158 case DRM_MODE_FLAG_3D_FRAME_PACKING: 6159 return HDMI_3D_STRUCTURE_FRAME_PACKING; 6160 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 6161 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 6162 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 6163 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 6164 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 6165 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 6166 case DRM_MODE_FLAG_3D_L_DEPTH: 6167 return HDMI_3D_STRUCTURE_L_DEPTH; 6168 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 6169 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 6170 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 6171 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 6172 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 6173 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 6174 default: 6175 return HDMI_3D_STRUCTURE_INVALID; 6176 } 6177 } 6178 6179 /** 6180 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 6181 * data from a DRM display mode 6182 * @frame: HDMI vendor infoframe 6183 * @connector: the connector 6184 * @mode: DRM display mode 6185 * 6186 * Note that there's is a need to send HDMI vendor infoframes only when using a 6187 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 6188 * function will return -EINVAL, error that can be safely ignored. 6189 * 6190 * Return: 0 on success or a negative error code on failure. 6191 */ 6192 int 6193 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 6194 const struct drm_connector *connector, 6195 const struct drm_display_mode *mode) 6196 { 6197 /* 6198 * FIXME: sil-sii8620 doesn't have a connector around when 6199 * we need one, so we have to be prepared for a NULL connector. 6200 */ 6201 bool has_hdmi_infoframe = connector ? 6202 connector->display_info.has_hdmi_infoframe : false; 6203 int err; 6204 6205 if (!frame || !mode) 6206 return -EINVAL; 6207 6208 if (!has_hdmi_infoframe) 6209 return -EINVAL; 6210 6211 err = hdmi_vendor_infoframe_init(frame); 6212 if (err < 0) 6213 return err; 6214 6215 /* 6216 * Even if it's not absolutely necessary to send the infoframe 6217 * (ie.vic==0 and s3d_struct==0) we will still send it if we 6218 * know that the sink can handle it. This is based on a 6219 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 6220 * have trouble realizing that they should switch from 3D to 2D 6221 * mode if the source simply stops sending the infoframe when 6222 * it wants to switch from 3D to 2D. 6223 */ 6224 frame->vic = drm_mode_hdmi_vic(connector, mode); 6225 frame->s3d_struct = s3d_structure_from_display_mode(mode); 6226 6227 return 0; 6228 } 6229 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 6230 6231 static void drm_parse_tiled_block(struct drm_connector *connector, 6232 const struct displayid_block *block) 6233 { 6234 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 6235 u16 w, h; 6236 u8 tile_v_loc, tile_h_loc; 6237 u8 num_v_tile, num_h_tile; 6238 struct drm_tile_group *tg; 6239 6240 w = tile->tile_size[0] | tile->tile_size[1] << 8; 6241 h = tile->tile_size[2] | tile->tile_size[3] << 8; 6242 6243 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 6244 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 6245 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 6246 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 6247 6248 connector->has_tile = true; 6249 if (tile->tile_cap & 0x80) 6250 connector->tile_is_single_monitor = true; 6251 6252 connector->num_h_tile = num_h_tile + 1; 6253 connector->num_v_tile = num_v_tile + 1; 6254 connector->tile_h_loc = tile_h_loc; 6255 connector->tile_v_loc = tile_v_loc; 6256 connector->tile_h_size = w + 1; 6257 connector->tile_v_size = h + 1; 6258 6259 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 6260 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 6261 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 6262 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 6263 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 6264 6265 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 6266 if (!tg) 6267 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 6268 if (!tg) 6269 return; 6270 6271 if (connector->tile_group != tg) { 6272 /* if we haven't got a pointer, 6273 take the reference, drop ref to old tile group */ 6274 if (connector->tile_group) 6275 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6276 connector->tile_group = tg; 6277 } else { 6278 /* if same tile group, then release the ref we just took. */ 6279 drm_mode_put_tile_group(connector->dev, tg); 6280 } 6281 } 6282 6283 void drm_update_tile_info(struct drm_connector *connector, 6284 const struct edid *edid) 6285 { 6286 const struct displayid_block *block; 6287 struct displayid_iter iter; 6288 6289 connector->has_tile = false; 6290 6291 displayid_iter_edid_begin(edid, &iter); 6292 displayid_iter_for_each(block, &iter) { 6293 if (block->tag == DATA_BLOCK_TILED_DISPLAY) 6294 drm_parse_tiled_block(connector, block); 6295 } 6296 displayid_iter_end(&iter); 6297 6298 if (!connector->has_tile && connector->tile_group) { 6299 drm_mode_put_tile_group(connector->dev, connector->tile_group); 6300 connector->tile_group = NULL; 6301 } 6302 } 6303