1 /* 2 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/i2c.h> 25 #include <linux/slab.h> 26 #include <linux/delay.h> 27 28 #include <drm/display/drm_scdc_helper.h> 29 #include <drm/drm_print.h> 30 31 /** 32 * DOC: scdc helpers 33 * 34 * Status and Control Data Channel (SCDC) is a mechanism introduced by the 35 * HDMI 2.0 specification. It is a point-to-point protocol that allows the 36 * HDMI source and HDMI sink to exchange data. The same I2C interface that 37 * is used to access EDID serves as the transport mechanism for SCDC. 38 * 39 * Note: The SCDC status is going to be lost when the display is 40 * disconnected. This can happen physically when the user disconnects 41 * the cable, but also when a display is switched on (such as waking up 42 * a TV). 43 * 44 * This is further complicated by the fact that, upon a disconnection / 45 * reconnection, KMS won't change the mode on its own. This means that 46 * one can't just rely on setting the SCDC status on enable, but also 47 * has to track the connector status changes using interrupts and 48 * restore the SCDC status. The typical solution for this is to trigger an 49 * empty modeset in drm_connector_helper_funcs.detect_ctx(), like what vc4 does 50 * in vc4_hdmi_reset_link(). 51 */ 52 53 #define SCDC_I2C_SLAVE_ADDRESS 0x54 54 55 /** 56 * drm_scdc_read - read a block of data from SCDC 57 * @adapter: I2C controller 58 * @offset: start offset of block to read 59 * @buffer: return location for the block to read 60 * @size: size of the block to read 61 * 62 * Reads a block of data from SCDC, starting at a given offset. 63 * 64 * Returns: 65 * 0 on success, negative error code on failure. 66 */ 67 ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer, 68 size_t size) 69 { 70 int ret; 71 struct i2c_msg msgs[2] = { 72 { 73 .addr = SCDC_I2C_SLAVE_ADDRESS, 74 .flags = 0, 75 .len = 1, 76 .buf = &offset, 77 }, { 78 .addr = SCDC_I2C_SLAVE_ADDRESS, 79 .flags = I2C_M_RD, 80 .len = size, 81 .buf = buffer, 82 } 83 }; 84 85 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 86 if (ret < 0) 87 return ret; 88 if (ret != ARRAY_SIZE(msgs)) 89 return -EPROTO; 90 91 return 0; 92 } 93 EXPORT_SYMBOL(drm_scdc_read); 94 95 /** 96 * drm_scdc_write - write a block of data to SCDC 97 * @adapter: I2C controller 98 * @offset: start offset of block to write 99 * @buffer: block of data to write 100 * @size: size of the block to write 101 * 102 * Writes a block of data to SCDC, starting at a given offset. 103 * 104 * Returns: 105 * 0 on success, negative error code on failure. 106 */ 107 ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, 108 const void *buffer, size_t size) 109 { 110 struct i2c_msg msg = { 111 .addr = SCDC_I2C_SLAVE_ADDRESS, 112 .flags = 0, 113 .len = 1 + size, 114 .buf = NULL, 115 }; 116 void *data; 117 int err; 118 119 data = kmalloc(1 + size, GFP_KERNEL); 120 if (!data) 121 return -ENOMEM; 122 123 msg.buf = data; 124 125 memcpy(data, &offset, sizeof(offset)); 126 memcpy(data + 1, buffer, size); 127 128 err = i2c_transfer(adapter, &msg, 1); 129 130 kfree(data); 131 132 if (err < 0) 133 return err; 134 if (err != 1) 135 return -EPROTO; 136 137 return 0; 138 } 139 EXPORT_SYMBOL(drm_scdc_write); 140 141 /** 142 * drm_scdc_get_scrambling_status - what is status of scrambling? 143 * @adapter: I2C adapter for DDC channel 144 * 145 * Reads the scrambler status over SCDC, and checks the 146 * scrambling status. 147 * 148 * Returns: 149 * True if the scrambling is enabled, false otherwise. 150 */ 151 bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter) 152 { 153 u8 status; 154 int ret; 155 156 ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status); 157 if (ret < 0) { 158 DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret); 159 return false; 160 } 161 162 return status & SCDC_SCRAMBLING_STATUS; 163 } 164 EXPORT_SYMBOL(drm_scdc_get_scrambling_status); 165 166 /** 167 * drm_scdc_set_scrambling - enable scrambling 168 * @adapter: I2C adapter for DDC channel 169 * @enable: bool to indicate if scrambling is to be enabled/disabled 170 * 171 * Writes the TMDS config register over SCDC channel, and: 172 * enables scrambling when enable = 1 173 * disables scrambling when enable = 0 174 * 175 * Returns: 176 * True if scrambling is set/reset successfully, false otherwise. 177 */ 178 bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable) 179 { 180 u8 config; 181 int ret; 182 183 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 184 if (ret < 0) { 185 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret); 186 return false; 187 } 188 189 if (enable) 190 config |= SCDC_SCRAMBLING_ENABLE; 191 else 192 config &= ~SCDC_SCRAMBLING_ENABLE; 193 194 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 195 if (ret < 0) { 196 DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret); 197 return false; 198 } 199 200 return true; 201 } 202 EXPORT_SYMBOL(drm_scdc_set_scrambling); 203 204 /** 205 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio 206 * @adapter: I2C adapter for DDC channel 207 * @set: ret or reset the high clock ratio 208 * 209 * 210 * TMDS clock ratio calculations go like this: 211 * TMDS character = 10 bit TMDS encoded value 212 * 213 * TMDS character rate = The rate at which TMDS characters are 214 * transmitted (Mcsc) 215 * 216 * TMDS bit rate = 10x TMDS character rate 217 * 218 * As per the spec: 219 * TMDS clock rate for pixel clock < 340 MHz = 1x the character 220 * rate = 1/10 pixel clock rate 221 * 222 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character 223 * rate = 1/40 pixel clock rate 224 * 225 * Writes to the TMDS config register over SCDC channel, and: 226 * sets TMDS clock ratio to 1/40 when set = 1 227 * 228 * sets TMDS clock ratio to 1/10 when set = 0 229 * 230 * Returns: 231 * True if write is successful, false otherwise. 232 */ 233 bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set) 234 { 235 u8 config; 236 int ret; 237 238 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 239 if (ret < 0) { 240 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret); 241 return false; 242 } 243 244 if (set) 245 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 246 else 247 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 248 249 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 250 if (ret < 0) { 251 DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret); 252 return false; 253 } 254 255 /* 256 * The spec says that a source should wait minimum 1ms and maximum 257 * 100ms after writing the TMDS config for clock ratio. Lets allow a 258 * wait of up to 2ms here. 259 */ 260 usleep_range(1000, 2000); 261 return true; 262 } 263 EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio); 264