1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2018 Intel Corp
4  *
5  * Author:
6  * Manasi Navare <manasi.d.navare@intel.com>
7  */
8 
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/byteorder/generic.h>
14 
15 #include <drm/display/drm_dp_helper.h>
16 #include <drm/display/drm_dsc_helper.h>
17 #include <drm/drm_print.h>
18 
19 /**
20  * DOC: dsc helpers
21  *
22  * VESA specification for DP 1.4 adds a new feature called Display Stream
23  * Compression (DSC) used to compress the pixel bits before sending it on
24  * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
25  * display interfaces can support high resolutions at higher frames rates uisng
26  * the maximum available link capacity of these interfaces.
27  *
28  * These functions contain some common logic and helpers to deal with VESA
29  * Display Stream Compression standard required for DSC on Display Port/eDP or
30  * MIPI display interfaces.
31  */
32 
33 /**
34  * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
35  * for DisplayPort as per the DP 1.4 spec.
36  * @pps_header: Secondary data packet header for DSC Picture
37  *              Parameter Set as defined in &struct dp_sdp_header
38  *
39  * DP 1.4 spec defines the secondary data packet for sending the
40  * picture parameter infoframes from the source to the sink.
41  * This function populates the SDP header defined in
42  * &struct dp_sdp_header.
43  */
44 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
45 {
46 	memset(pps_header, 0, sizeof(*pps_header));
47 
48 	pps_header->HB1 = DP_SDP_PPS;
49 	pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
50 }
51 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
52 
53 /**
54  * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
55  * @rc_buffer_block_size: block size code, according to DPCD offset 62h
56  * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
57  *
58  * return:
59  * buffer size in bytes, or 0 on invalid input
60  */
61 int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)
62 {
63 	int size = 1024 * (rc_buffer_size + 1);
64 
65 	switch (rc_buffer_block_size) {
66 	case DP_DSC_RC_BUF_BLK_SIZE_1:
67 		return 1 * size;
68 	case DP_DSC_RC_BUF_BLK_SIZE_4:
69 		return 4 * size;
70 	case DP_DSC_RC_BUF_BLK_SIZE_16:
71 		return 16 * size;
72 	case DP_DSC_RC_BUF_BLK_SIZE_64:
73 		return 64 * size;
74 	default:
75 		return 0;
76 	}
77 }
78 EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size);
79 
80 /**
81  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
82  *
83  * @pps_payload:
84  * Bitwise struct for DSC Picture Parameter Set. This is defined
85  * by &struct drm_dsc_picture_parameter_set
86  * @dsc_cfg:
87  * DSC Configuration data filled by driver as defined by
88  * &struct drm_dsc_config
89  *
90  * DSC source device sends a picture parameter set (PPS) containing the
91  * information required by the sink to decode the compressed frame. Driver
92  * populates the DSC PPS struct using the DSC configuration parameters in
93  * the order expected by the DSC Display Sink device. For the DSC, the sink
94  * device expects the PPS payload in big endian format for fields
95  * that span more than 1 byte.
96  */
97 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
98 				const struct drm_dsc_config *dsc_cfg)
99 {
100 	int i;
101 
102 	/* Protect against someone accidentally changing struct size */
103 	BUILD_BUG_ON(sizeof(*pps_payload) !=
104 		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
105 
106 	memset(pps_payload, 0, sizeof(*pps_payload));
107 
108 	/* PPS 0 */
109 	pps_payload->dsc_version =
110 		dsc_cfg->dsc_version_minor |
111 		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
112 
113 	/* PPS 1, 2 is 0 */
114 
115 	/* PPS 3 */
116 	pps_payload->pps_3 =
117 		dsc_cfg->line_buf_depth |
118 		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
119 
120 	/* PPS 4 */
121 	pps_payload->pps_4 =
122 		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
123 		 DSC_PPS_MSB_SHIFT) |
124 		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
125 		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
126 		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
127 		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
128 
129 	/* PPS 5 */
130 	pps_payload->bits_per_pixel_low =
131 		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
132 
133 	/*
134 	 * The DSC panel expects the PPS packet to have big endian format
135 	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
136 	 * to big endian format. If format is little endian, it will swap
137 	 * bytes to convert to Big endian else keep it unchanged.
138 	 */
139 
140 	/* PPS 6, 7 */
141 	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
142 
143 	/* PPS 8, 9 */
144 	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
145 
146 	/* PPS 10, 11 */
147 	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
148 
149 	/* PPS 12, 13 */
150 	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
151 
152 	/* PPS 14, 15 */
153 	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
154 
155 	/* PPS 16 */
156 	pps_payload->initial_xmit_delay_high =
157 		((dsc_cfg->initial_xmit_delay &
158 		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
159 		 DSC_PPS_MSB_SHIFT);
160 
161 	/* PPS 17 */
162 	pps_payload->initial_xmit_delay_low =
163 		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
164 
165 	/* PPS 18, 19 */
166 	pps_payload->initial_dec_delay =
167 		cpu_to_be16(dsc_cfg->initial_dec_delay);
168 
169 	/* PPS 20 is 0 */
170 
171 	/* PPS 21 */
172 	pps_payload->initial_scale_value =
173 		dsc_cfg->initial_scale_value;
174 
175 	/* PPS 22, 23 */
176 	pps_payload->scale_increment_interval =
177 		cpu_to_be16(dsc_cfg->scale_increment_interval);
178 
179 	/* PPS 24 */
180 	pps_payload->scale_decrement_interval_high =
181 		((dsc_cfg->scale_decrement_interval &
182 		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
183 		 DSC_PPS_MSB_SHIFT);
184 
185 	/* PPS 25 */
186 	pps_payload->scale_decrement_interval_low =
187 		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
188 
189 	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
190 
191 	/* PPS 27 */
192 	pps_payload->first_line_bpg_offset =
193 		dsc_cfg->first_line_bpg_offset;
194 
195 	/* PPS 28, 29 */
196 	pps_payload->nfl_bpg_offset =
197 		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
198 
199 	/* PPS 30, 31 */
200 	pps_payload->slice_bpg_offset =
201 		cpu_to_be16(dsc_cfg->slice_bpg_offset);
202 
203 	/* PPS 32, 33 */
204 	pps_payload->initial_offset =
205 		cpu_to_be16(dsc_cfg->initial_offset);
206 
207 	/* PPS 34, 35 */
208 	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
209 
210 	/* PPS 36 */
211 	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
212 
213 	/* PPS 37 */
214 	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
215 
216 	/* PPS 38, 39 */
217 	pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
218 
219 	/* PPS 40 */
220 	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
221 
222 	/* PPS 41 */
223 	pps_payload->rc_quant_incr_limit0 =
224 		dsc_cfg->rc_quant_incr_limit0;
225 
226 	/* PPS 42 */
227 	pps_payload->rc_quant_incr_limit1 =
228 		dsc_cfg->rc_quant_incr_limit1;
229 
230 	/* PPS 43 */
231 	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
232 		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
233 
234 	/* PPS 44 - 57 */
235 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
236 		pps_payload->rc_buf_thresh[i] =
237 			dsc_cfg->rc_buf_thresh[i];
238 
239 	/* PPS 58 - 87 */
240 	/*
241 	 * For DSC sink programming the RC Range parameter fields
242 	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
243 	 */
244 	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
245 		pps_payload->rc_range_parameters[i] =
246 			cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
247 				     DSC_PPS_RC_RANGE_MINQP_SHIFT) |
248 				    (dsc_cfg->rc_range_params[i].range_max_qp <<
249 				     DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
250 				    (dsc_cfg->rc_range_params[i].range_bpg_offset));
251 	}
252 
253 	/* PPS 88 */
254 	pps_payload->native_422_420 = dsc_cfg->native_422 |
255 		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
256 
257 	/* PPS 89 */
258 	pps_payload->second_line_bpg_offset =
259 		dsc_cfg->second_line_bpg_offset;
260 
261 	/* PPS 90, 91 */
262 	pps_payload->nsl_bpg_offset =
263 		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
264 
265 	/* PPS 92, 93 */
266 	pps_payload->second_line_offset_adj =
267 		cpu_to_be16(dsc_cfg->second_line_offset_adj);
268 
269 	/* PPS 94 - 127 are O */
270 }
271 EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
272 
273 /**
274  * drm_dsc_set_const_params() - Set DSC parameters considered typically
275  * constant across operation modes
276  *
277  * @vdsc_cfg:
278  * DSC Configuration data partially filled by driver
279  */
280 void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
281 {
282 	if (!vdsc_cfg->rc_model_size)
283 		vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
284 	vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
285 	vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
286 	vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
287 
288 	if (vdsc_cfg->bits_per_component <= 10)
289 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
290 	else
291 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
292 }
293 EXPORT_SYMBOL(drm_dsc_set_const_params);
294 
295 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
296 static const u16 drm_dsc_rc_buf_thresh[] = {
297 	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
298 	7744, 7872, 8000, 8064
299 };
300 
301 /**
302  * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
303  * in accordance with the DSC 1.2 specification.
304  *
305  * @vdsc_cfg: DSC Configuration data partially filled by driver
306  */
307 void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
308 {
309 	int i;
310 
311 	BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
312 		     DSC_NUM_BUF_RANGES - 1);
313 	BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
314 		     ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
315 
316 	for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
317 		vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
318 
319 	/*
320 	 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
321 	 * as per C Model
322 	 */
323 	if (vdsc_cfg->bits_per_pixel == 6 << 4) {
324 		vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
325 		vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
326 	}
327 }
328 EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
329 
330 struct rc_parameters {
331 	u16 initial_xmit_delay;
332 	u8 first_line_bpg_offset;
333 	u16 initial_offset;
334 	u8 flatness_min_qp;
335 	u8 flatness_max_qp;
336 	u8 rc_quant_incr_limit0;
337 	u8 rc_quant_incr_limit1;
338 	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
339 };
340 
341 struct rc_parameters_data {
342 	u8 bpp;
343 	u8 bpc;
344 	struct rc_parameters params;
345 };
346 
347 #define DSC_BPP(bpp)	((bpp) << 4)
348 
349 /*
350  * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior
351  * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
352  *
353  * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
354  */
355 static const struct rc_parameters_data rc_parameters_pre_scr[] = {
356 	{
357 		.bpp = DSC_BPP(6), .bpc = 8,
358 		{ 683, 15, 6144, 3, 13, 11, 11, {
359 			{ 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
360 			{ 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
361 			{ 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
362 			{ 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
363 			}
364 		}
365 	},
366 	{
367 		.bpp = DSC_BPP(8), .bpc = 8,
368 		{ 512, 12, 6144, 3, 12, 11, 11, {
369 			{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
370 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
371 			{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
372 			{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
373 			}
374 		}
375 	},
376 	{
377 		.bpp = DSC_BPP(8), .bpc = 10,
378 		{ 512, 12, 6144, 7, 16, 15, 15, {
379 			/*
380 			 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
381 			 * VESA DSC 1.1 Table E-5 sets it to 4.
382 			 */
383 			{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
384 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
385 			{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
386 			{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
387 			}
388 		}
389 	},
390 	{
391 		.bpp = DSC_BPP(8), .bpc = 12,
392 		{ 512, 12, 6144, 11, 20, 19, 19, {
393 			{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
394 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
395 			{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
396 			{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
397 			{ 21, 23, -12 }
398 			}
399 		}
400 	},
401 	{
402 		.bpp = DSC_BPP(10), .bpc = 8,
403 		{ 410, 12, 5632, 3, 12, 11, 11, {
404 			{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
405 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
406 			{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
407 			{ 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
408 			}
409 		}
410 	},
411 	{
412 		.bpp = DSC_BPP(10), .bpc = 10,
413 		{ 410, 12, 5632, 7, 16, 15, 15, {
414 			{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
415 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
416 			{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
417 			{ 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
418 			}
419 		}
420 	},
421 	{
422 		.bpp = DSC_BPP(10), .bpc = 12,
423 		{ 410, 12, 5632, 11, 20, 19, 19, {
424 			{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
425 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
426 			{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
427 			{ 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
428 			{ 21, 23, -12 }
429 			}
430 		}
431 	},
432 	{
433 		.bpp = DSC_BPP(12), .bpc = 8,
434 		{ 341, 15, 2048, 3, 12, 11, 11, {
435 			{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
436 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
437 			{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
438 			{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
439 			}
440 		}
441 	},
442 	{
443 		.bpp = DSC_BPP(12), .bpc = 10,
444 		{ 341, 15, 2048, 7, 16, 15, 15, {
445 			{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
446 			{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
447 			{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
448 			{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
449 			}
450 		}
451 	},
452 	{
453 		.bpp = DSC_BPP(12), .bpc = 12,
454 		{ 341, 15, 2048, 11, 20, 19, 19, {
455 			{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
456 			{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
457 			{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
458 			{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
459 			{ 21, 23, -12 }
460 			}
461 		}
462 	},
463 	{
464 		.bpp = DSC_BPP(15), .bpc = 8,
465 		{ 273, 15, 2048, 3, 12, 11, 11, {
466 			{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
467 			{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
468 			{ 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
469 			{ 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
470 			}
471 		}
472 	},
473 	{
474 		.bpp = DSC_BPP(15), .bpc = 10,
475 		{ 273, 15, 2048, 7, 16, 15, 15, {
476 			{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
477 			{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
478 			{ 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
479 			{ 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
480 			}
481 		}
482 	},
483 	{
484 		.bpp = DSC_BPP(15), .bpc = 12,
485 		{ 273, 15, 2048, 11, 20, 19, 19, {
486 			{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
487 			{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
488 			{ 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
489 			{ 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
490 			{ 21, 23, -12 }
491 			}
492 		}
493 	},
494 	{ /* sentinel */ }
495 };
496 
497 /*
498  * Selected Rate Control Related Parameter Recommended Values from DSC v1.2, v1.2a, v1.2b and
499  * DSC_v1.1_E1 specs.
500  *
501  * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
502  */
503 static const struct rc_parameters_data rc_parameters_1_2_444[] = {
504 	{
505 		.bpp = DSC_BPP(6), .bpc = 8,
506 		{ 768, 15, 6144, 3, 13, 11, 11, {
507 			{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
508 			{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
509 			{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
510 			{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
511 			}
512 		}
513 	},
514 	{
515 		.bpp = DSC_BPP(6), .bpc = 10,
516 		{ 768, 15, 6144, 7, 17, 15, 15, {
517 			{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
518 			{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
519 			{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
520 			{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
521 			{ 17, 18, -12 }
522 			}
523 		}
524 	},
525 	{
526 		.bpp = DSC_BPP(6), .bpc = 12,
527 		{ 768, 15, 6144, 11, 21, 19, 19, {
528 			{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
529 			{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
530 			{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
531 			{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
532 			{ 21, 22, -12 }
533 			}
534 		}
535 	},
536 	{
537 		.bpp = DSC_BPP(6), .bpc = 14,
538 		{ 768, 15, 6144, 15, 25, 23, 23, {
539 			{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
540 			{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
541 			{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
542 			{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
543 			{ 25, 26, -12 }
544 			}
545 		}
546 	},
547 	{
548 		.bpp = DSC_BPP(6), .bpc = 16,
549 		{ 768, 15, 6144, 19, 29, 27, 27, {
550 			{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
551 			{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
552 			{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
553 			{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
554 			{ 29, 30, -12 }
555 			}
556 		}
557 	},
558 	{
559 		.bpp = DSC_BPP(8), .bpc = 8,
560 		{ 512, 12, 6144, 3, 12, 11, 11, {
561 			{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
562 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
563 			{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
564 			{ 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
565 			}
566 		}
567 	},
568 	{
569 		.bpp = DSC_BPP(8), .bpc = 10,
570 		{ 512, 12, 6144, 7, 16, 15, 15, {
571 			{ 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
572 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
573 			{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
574 			{ 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
575 			}
576 		}
577 	},
578 	{
579 		.bpp = DSC_BPP(8), .bpc = 12,
580 		{ 512, 12, 6144, 11, 20, 19, 19, {
581 			{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
582 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
583 			{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
584 			{ 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
585 			{ 20, 21, -12 }
586 			}
587 		}
588 	},
589 	{
590 		.bpp = DSC_BPP(8), .bpc = 14,
591 		{ 512, 12, 6144, 15, 24, 23, 23, {
592 			{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
593 			{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
594 			{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
595 			{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
596 			{ 24, 25, -12 }
597 			}
598 		}
599 	},
600 	{
601 		.bpp = DSC_BPP(8), .bpc = 16,
602 		{ 512, 12, 6144, 19, 28, 27, 27, {
603 			{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
604 			{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
605 			{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
606 			{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
607 			{ 28, 29, -12 }
608 			}
609 		}
610 	},
611 	{
612 		.bpp = DSC_BPP(10), .bpc = 8,
613 		{ 410, 15, 5632, 3, 12, 11, 11, {
614 			{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
615 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
616 			{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
617 			{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
618 			}
619 		}
620 	},
621 	{
622 		.bpp = DSC_BPP(10), .bpc = 10,
623 		{ 410, 15, 5632, 7, 16, 15, 15, {
624 			{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
625 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
626 			{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
627 			{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
628 			}
629 		}
630 	},
631 	{
632 		.bpp = DSC_BPP(10), .bpc = 12,
633 		{ 410, 15, 5632, 11, 20, 19, 19, {
634 			{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
635 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
636 			{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
637 			{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
638 			{ 19, 20, -12 }
639 			}
640 		}
641 	},
642 	{
643 		.bpp = DSC_BPP(10), .bpc = 14,
644 		{ 410, 15, 5632, 15, 24, 23, 23, {
645 			{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
646 			{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
647 			{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
648 			{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
649 			{ 23, 24, -12 }
650 			}
651 		}
652 	},
653 	{
654 		.bpp = DSC_BPP(10), .bpc = 16,
655 		{ 410, 15, 5632, 19, 28, 27, 27, {
656 			{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
657 			{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
658 			{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
659 			{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
660 			{ 27, 28, -12 }
661 			}
662 		}
663 	},
664 	{
665 		.bpp = DSC_BPP(12), .bpc = 8,
666 		{ 341, 15, 2048, 3, 12, 11, 11, {
667 			{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
668 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
669 			{ 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
670 			{ 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
671 			}
672 		}
673 	},
674 	{
675 		.bpp = DSC_BPP(12), .bpc = 10,
676 		{ 341, 15, 2048, 7, 16, 15, 15, {
677 			{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
678 			{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
679 			{ 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
680 			{ 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
681 			}
682 		}
683 	},
684 	{
685 		.bpp = DSC_BPP(12), .bpc = 12,
686 		{ 341, 15, 2048, 11, 20, 19, 19, {
687 			{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
688 			{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
689 			{ 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
690 			{ 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
691 			{ 18, 19, -12 }
692 			}
693 		}
694 	},
695 	{
696 		.bpp = DSC_BPP(12), .bpc = 14,
697 		{ 341, 15, 2048, 15, 24, 23, 23, {
698 			{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
699 			{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
700 			{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
701 			{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
702 			{ 22, 23, -12 }
703 			}
704 		}
705 	},
706 	{
707 		.bpp = DSC_BPP(12), .bpc = 16,
708 		{ 341, 15, 2048, 19, 28, 27, 27, {
709 			{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
710 			{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
711 			{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
712 			{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
713 			{ 26, 27, -12 }
714 			}
715 		}
716 	},
717 	{
718 		.bpp = DSC_BPP(15), .bpc = 8,
719 		{ 273, 15, 2048, 3, 12, 11, 11, {
720 			{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
721 			{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
722 			{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
723 			{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
724 			}
725 		}
726 	},
727 	{
728 		.bpp = DSC_BPP(15), .bpc = 10,
729 		{ 273, 15, 2048, 7, 16, 15, 15, {
730 			{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
731 			{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
732 			{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
733 			{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
734 			}
735 		}
736 	},
737 	{
738 		.bpp = DSC_BPP(15), .bpc = 12,
739 		{ 273, 15, 2048, 11, 20, 19, 19, {
740 			{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
741 			{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
742 			{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
743 			{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
744 			{ 16, 17, -12 }
745 			}
746 		}
747 	},
748 	{
749 		.bpp = DSC_BPP(15), .bpc = 14,
750 		{ 273, 15, 2048, 15, 24, 23, 23, {
751 			{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
752 			{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
753 			{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
754 			{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
755 			{ 20, 21, -12 }
756 			}
757 		}
758 	},
759 	{
760 		.bpp = DSC_BPP(15), .bpc = 16,
761 		{ 273, 15, 2048, 19, 28, 27, 27, {
762 			{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
763 			{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
764 			{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
765 			{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
766 			{ 24, 25, -12 }
767 			}
768 		}
769 	},
770 	{ /* sentinel */ }
771 };
772 
773 /*
774  * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from
775  * DSC v1.2, v1.2a, v1.2b
776  *
777  * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
778  */
779 static const struct rc_parameters_data rc_parameters_1_2_422[] = {
780 	{
781 		.bpp = DSC_BPP(6), .bpc = 8,
782 		{ 512, 15, 6144, 3, 12, 11, 11, {
783 			{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
784 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
785 			{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
786 			{ 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
787 			}
788 		}
789 	},
790 	{
791 		.bpp = DSC_BPP(6), .bpc = 10,
792 		{ 512, 15, 6144, 7, 16, 15, 15, {
793 			{ 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
794 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
795 			{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
796 			{ 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
797 			}
798 		}
799 	},
800 	{
801 		.bpp = DSC_BPP(6), .bpc = 12,
802 		{ 512, 15, 6144, 11, 20, 19, 19, {
803 			{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
804 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
805 			{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
806 			{ 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
807 			{ 20, 21, -12 }
808 			}
809 		}
810 	},
811 	{
812 		.bpp = DSC_BPP(6), .bpc = 14,
813 		{ 512, 15, 6144, 15, 24, 23, 23, {
814 			{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
815 			{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
816 			{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
817 			{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
818 			{ 24, 25, -12 }
819 			}
820 		}
821 	},
822 	{
823 		.bpp = DSC_BPP(6), .bpc = 16,
824 		{ 512, 15, 6144, 19, 28, 27, 27, {
825 			{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
826 			{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
827 			{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
828 			{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
829 			{ 28, 29, -12 }
830 			}
831 		}
832 	},
833 	{
834 		.bpp = DSC_BPP(7), .bpc = 8,
835 		{ 410, 15, 5632, 3, 12, 11, 11, {
836 			{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
837 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
838 			{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
839 			{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
840 			}
841 		}
842 	},
843 	{
844 		.bpp = DSC_BPP(7), .bpc = 10,
845 		{ 410, 15, 5632, 7, 16, 15, 15, {
846 			{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
847 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
848 			{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
849 			{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
850 			}
851 		}
852 	},
853 	{
854 		.bpp = DSC_BPP(7), .bpc = 12,
855 		{ 410, 15, 5632, 11, 20, 19, 19, {
856 			{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
857 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
858 			{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
859 			{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
860 			{ 19, 20, -12 }
861 			}
862 		}
863 	},
864 	{
865 		.bpp = DSC_BPP(7), .bpc = 14,
866 		{ 410, 15, 5632, 15, 24, 23, 23, {
867 			{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
868 			{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
869 			{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
870 			{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
871 			{ 23, 24, -12 }
872 			}
873 		}
874 	},
875 	{
876 		.bpp = DSC_BPP(7), .bpc = 16,
877 		{ 410, 15, 5632, 19, 28, 27, 27, {
878 			{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
879 			{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
880 			{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
881 			{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
882 			{ 27, 28, -12 }
883 			}
884 		}
885 	},
886 	{
887 		.bpp = DSC_BPP(8), .bpc = 8,
888 		{ 341, 15, 2048, 3, 12, 11, 11, {
889 			{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
890 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
891 			{ 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
892 			{ 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
893 			}
894 		}
895 	},
896 	{
897 		.bpp = DSC_BPP(8), .bpc = 10,
898 		{ 341, 15, 2048, 7, 16, 15, 15, {
899 			{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
900 			{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
901 			{ 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
902 			{ 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
903 			}
904 		}
905 	},
906 	{
907 		.bpp = DSC_BPP(8), .bpc = 12,
908 		{ 341, 15, 2048, 11, 20, 19, 19, {
909 			{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
910 			{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
911 			{ 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
912 			{ 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
913 			{ 18, 19, -12 }
914 			}
915 		}
916 	},
917 	{
918 		.bpp = DSC_BPP(8), .bpc = 14,
919 		{ 341, 15, 2048, 15, 24, 23, 23, {
920 			{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
921 			{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
922 			{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
923 			{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
924 			{ 22, 23, -12 }
925 			}
926 		}
927 	},
928 	{
929 		.bpp = DSC_BPP(8), .bpc = 16,
930 		{ 341, 15, 2048, 19, 28, 27, 27, {
931 			{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
932 			{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
933 			{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
934 			{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
935 			{ 26, 27, -12 }
936 			}
937 		}
938 	},
939 	{
940 		.bpp = DSC_BPP(10), .bpc = 8,
941 		{ 273, 15, 2048, 3, 12, 11, 11, {
942 			{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
943 			{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
944 			{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
945 			{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
946 			}
947 		}
948 	},
949 	{
950 		.bpp = DSC_BPP(10), .bpc = 10,
951 		{ 273, 15, 2048, 7, 16, 15, 15, {
952 			{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
953 			{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
954 			{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
955 			{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
956 			}
957 		}
958 	},
959 	{
960 		.bpp = DSC_BPP(10), .bpc = 12,
961 		{ 273, 15, 2048, 11, 20, 19, 19, {
962 			{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
963 			{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
964 			{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
965 			{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
966 			{ 16, 17, -12 }
967 			}
968 		}
969 	},
970 	{
971 		.bpp = DSC_BPP(10), .bpc = 14,
972 		{ 273, 15, 2048, 15, 24, 23, 23, {
973 			{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
974 			{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
975 			{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
976 			{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
977 			{ 20, 21, -12 }
978 			}
979 		}
980 	},
981 	{
982 		.bpp = DSC_BPP(10), .bpc = 16,
983 		{ 273, 15, 2048, 19, 28, 27, 27, {
984 			{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
985 			{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
986 			{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
987 			{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
988 			{ 24, 25, -12 }
989 			}
990 		}
991 	},
992 	{ /* sentinel */ }
993 };
994 
995 /*
996  * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from
997  * DSC v1.2, v1.2a, v1.2b
998  *
999  * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
1000  */
1001 static const struct rc_parameters_data rc_parameters_1_2_420[] = {
1002 	{
1003 		.bpp = DSC_BPP(4), .bpc = 8,
1004 		{ 512, 12, 6144, 3, 12, 11, 11, {
1005 			{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
1006 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
1007 			{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
1008 			{ 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
1009 			}
1010 		}
1011 	},
1012 	{
1013 		.bpp = DSC_BPP(4), .bpc = 10,
1014 		{ 512, 12, 6144, 7, 16, 15, 15, {
1015 			{ 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
1016 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
1017 			{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
1018 			{ 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
1019 			}
1020 		}
1021 	},
1022 	{
1023 		.bpp = DSC_BPP(4), .bpc = 12,
1024 		{ 512, 12, 6144, 11, 20, 19, 19, {
1025 			{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
1026 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
1027 			{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
1028 			{ 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
1029 			{ 20, 21, -12 }
1030 			}
1031 		}
1032 	},
1033 	{
1034 		.bpp = DSC_BPP(4), .bpc = 14,
1035 		{ 512, 12, 6144, 15, 24, 23, 23, {
1036 			{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
1037 			{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
1038 			{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
1039 			{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
1040 			{ 24, 25, -12 }
1041 			}
1042 		}
1043 	},
1044 	{
1045 		.bpp = DSC_BPP(4), .bpc = 16,
1046 		{ 512, 12, 6144, 19, 28, 27, 27, {
1047 			{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
1048 			{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
1049 			{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
1050 			{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
1051 			{ 28, 29, -12 }
1052 			}
1053 		}
1054 	},
1055 	{
1056 		.bpp = DSC_BPP(5), .bpc = 8,
1057 		{ 410, 15, 5632, 3, 12, 11, 11, {
1058 			{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
1059 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
1060 			{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
1061 			{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
1062 			}
1063 		}
1064 	},
1065 	{
1066 		.bpp = DSC_BPP(5), .bpc = 10,
1067 		{ 410, 15, 5632, 7, 16, 15, 15, {
1068 			{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
1069 			{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
1070 			{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
1071 			{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
1072 			}
1073 		}
1074 	},
1075 	{
1076 		.bpp = DSC_BPP(5), .bpc = 12,
1077 		{ 410, 15, 5632, 11, 20, 19, 19, {
1078 			{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
1079 			{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
1080 			{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
1081 			{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
1082 			{ 19, 20, -12 }
1083 			}
1084 		}
1085 	},
1086 	{
1087 		.bpp = DSC_BPP(5), .bpc = 14,
1088 		{ 410, 15, 5632, 15, 24, 23, 23, {
1089 			{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
1090 			{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
1091 			{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
1092 			{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
1093 			{ 23, 24, -12 }
1094 			}
1095 		}
1096 	},
1097 	{
1098 		.bpp = DSC_BPP(5), .bpc = 16,
1099 		{ 410, 15, 5632, 19, 28, 27, 27, {
1100 			{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
1101 			{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
1102 			{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
1103 			{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
1104 			{ 27, 28, -12 }
1105 			}
1106 		}
1107 	},
1108 	{
1109 		.bpp = DSC_BPP(6), .bpc = 8,
1110 		{ 341, 15, 2048, 3, 12, 11, 11, {
1111 			{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
1112 			{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
1113 			{ 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
1114 			{ 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
1115 			}
1116 		}
1117 	},
1118 	{
1119 		.bpp = DSC_BPP(6), .bpc = 10,
1120 		{ 341, 15, 2048, 7, 16, 15, 15, {
1121 			{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
1122 			{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
1123 			{ 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
1124 			{ 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
1125 			}
1126 		}
1127 	},
1128 	{
1129 		.bpp = DSC_BPP(6), .bpc = 12,
1130 		{ 341, 15, 2048, 11, 20, 19, 19, {
1131 			{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
1132 			{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
1133 			{ 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
1134 			{ 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
1135 			{ 18, 19, -12 }
1136 			}
1137 		}
1138 	},
1139 	{
1140 		.bpp = DSC_BPP(6), .bpc = 14,
1141 		{ 341, 15, 2048, 15, 24, 23, 23, {
1142 			{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
1143 			{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
1144 			{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
1145 			{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
1146 			{ 22, 23, -12 }
1147 			}
1148 		}
1149 	},
1150 	{
1151 		.bpp = DSC_BPP(6), .bpc = 16,
1152 		{ 341, 15, 2048, 19, 28, 27, 27, {
1153 			{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
1154 			{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
1155 			{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
1156 			{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
1157 			{ 26, 27, -12 }
1158 			}
1159 		}
1160 	},
1161 	{
1162 		.bpp = DSC_BPP(8), .bpc = 8,
1163 		{ 256, 15, 2048, 3, 12, 11, 11, {
1164 			{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
1165 			{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
1166 			{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
1167 			{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
1168 			}
1169 		}
1170 	},
1171 	{
1172 		.bpp = DSC_BPP(8), .bpc = 10,
1173 		{ 256, 15, 2048, 7, 16, 15, 15, {
1174 			{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
1175 			{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
1176 			{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
1177 			{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
1178 			}
1179 		}
1180 	},
1181 	{
1182 		.bpp = DSC_BPP(8), .bpc = 12,
1183 		{ 256, 15, 2048, 11, 20, 19, 19, {
1184 			{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
1185 			{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
1186 			{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
1187 			{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
1188 			{ 16, 17, -12 }
1189 			}
1190 		}
1191 	},
1192 	{
1193 		.bpp = DSC_BPP(8), .bpc = 14,
1194 		{ 256, 15, 2048, 15, 24, 23, 23, {
1195 			{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
1196 			{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
1197 			{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
1198 			{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
1199 			{ 20, 21, -12 }
1200 			}
1201 		}
1202 	},
1203 	{
1204 		.bpp = DSC_BPP(8), .bpc = 16,
1205 		{ 256, 15, 2048, 19, 28, 27, 27, {
1206 			{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
1207 			{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
1208 			{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
1209 			{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
1210 			{ 24, 25, -12 }
1211 			}
1212 		}
1213 	},
1214 	{ /* sentinel */ }
1215 };
1216 
1217 static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
1218 						 u16 dsc_bpp,
1219 						 u8 bits_per_component)
1220 {
1221 	int i;
1222 
1223 	for (i = 0; rc_parameters[i].bpp; i++)
1224 		if (rc_parameters[i].bpp == dsc_bpp &&
1225 		    rc_parameters[i].bpc == bits_per_component)
1226 			return &rc_parameters[i].params;
1227 
1228 	return NULL;
1229 }
1230 
1231 /**
1232  * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
1233  * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
1234  * Required bits_per_pixel and bits_per_component to be set before calling this
1235  * function.
1236  *
1237  * @vdsc_cfg: DSC Configuration data partially filled by driver
1238  * @type: operating mode and standard to follow
1239  *
1240  * Return: 0 or -error code in case of an error
1241  */
1242 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type)
1243 {
1244 	const struct rc_parameters_data *data;
1245 	const struct rc_parameters *rc_params;
1246 	int i;
1247 
1248 	if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
1249 			 !vdsc_cfg->bits_per_component))
1250 		return -EINVAL;
1251 
1252 	switch (type) {
1253 	case DRM_DSC_1_2_444:
1254 		data = rc_parameters_1_2_444;
1255 		break;
1256 	case DRM_DSC_1_1_PRE_SCR:
1257 		data = rc_parameters_pre_scr;
1258 		break;
1259 	case DRM_DSC_1_2_422:
1260 		data = rc_parameters_1_2_422;
1261 		break;
1262 	case DRM_DSC_1_2_420:
1263 		data = rc_parameters_1_2_420;
1264 		break;
1265 	default:
1266 		return -EINVAL;
1267 	}
1268 
1269 	rc_params = get_rc_params(data,
1270 				  vdsc_cfg->bits_per_pixel,
1271 				  vdsc_cfg->bits_per_component);
1272 	if (!rc_params)
1273 		return -EINVAL;
1274 
1275 	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
1276 	vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
1277 	vdsc_cfg->initial_offset = rc_params->initial_offset;
1278 	vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
1279 	vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
1280 	vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
1281 	vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
1282 
1283 	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
1284 		vdsc_cfg->rc_range_params[i].range_min_qp =
1285 			rc_params->rc_range_params[i].range_min_qp;
1286 		vdsc_cfg->rc_range_params[i].range_max_qp =
1287 			rc_params->rc_range_params[i].range_max_qp;
1288 		/*
1289 		 * Range BPG Offset uses 2's complement and is only a 6 bits. So
1290 		 * mask it to get only 6 bits.
1291 		 */
1292 		vdsc_cfg->rc_range_params[i].range_bpg_offset =
1293 			rc_params->rc_range_params[i].range_bpg_offset &
1294 			DSC_RANGE_BPG_OFFSET_MASK;
1295 	}
1296 
1297 	return 0;
1298 }
1299 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
1300 
1301 /**
1302  * drm_dsc_compute_rc_parameters() - Write rate control
1303  * parameters to the dsc configuration defined in
1304  * &struct drm_dsc_config in accordance with the DSC 1.2
1305  * specification. Some configuration fields must be present
1306  * beforehand.
1307  *
1308  * @vdsc_cfg:
1309  * DSC Configuration data partially filled by driver
1310  */
1311 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
1312 {
1313 	unsigned long groups_per_line = 0;
1314 	unsigned long groups_total = 0;
1315 	unsigned long num_extra_mux_bits = 0;
1316 	unsigned long slice_bits = 0;
1317 	unsigned long hrd_delay = 0;
1318 	unsigned long final_scale = 0;
1319 	unsigned long rbs_min = 0;
1320 
1321 	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
1322 		/* Number of groups used to code each line of a slice */
1323 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
1324 					       DSC_RC_PIXELS_PER_GROUP);
1325 
1326 		/* chunksize in Bytes */
1327 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
1328 							  vdsc_cfg->bits_per_pixel,
1329 							  (8 * 16));
1330 	} else {
1331 		/* Number of groups used to code each line of a slice */
1332 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
1333 					       DSC_RC_PIXELS_PER_GROUP);
1334 
1335 		/* chunksize in Bytes */
1336 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
1337 							  vdsc_cfg->bits_per_pixel,
1338 							  (8 * 16));
1339 	}
1340 
1341 	if (vdsc_cfg->convert_rgb)
1342 		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
1343 					  (4 * vdsc_cfg->bits_per_component + 4)
1344 					  - 2);
1345 	else if (vdsc_cfg->native_422)
1346 		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
1347 			(4 * vdsc_cfg->bits_per_component + 4) +
1348 			3 * (4 * vdsc_cfg->bits_per_component) - 2;
1349 	else
1350 		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
1351 			(4 * vdsc_cfg->bits_per_component + 4) +
1352 			2 * (4 * vdsc_cfg->bits_per_component) - 2;
1353 	/* Number of bits in one Slice */
1354 	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
1355 
1356 	while ((num_extra_mux_bits > 0) &&
1357 	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
1358 		num_extra_mux_bits--;
1359 
1360 	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
1361 		vdsc_cfg->initial_scale_value = groups_per_line + 8;
1362 
1363 	/* scale_decrement_interval calculation according to DSC spec 1.11 */
1364 	if (vdsc_cfg->initial_scale_value > 8)
1365 		vdsc_cfg->scale_decrement_interval = groups_per_line /
1366 			(vdsc_cfg->initial_scale_value - 8);
1367 	else
1368 		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
1369 
1370 	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
1371 		(vdsc_cfg->initial_xmit_delay *
1372 		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
1373 
1374 	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
1375 		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
1376 		return -ERANGE;
1377 	}
1378 
1379 	final_scale = (vdsc_cfg->rc_model_size * 8) /
1380 		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
1381 	if (vdsc_cfg->slice_height > 1)
1382 		/*
1383 		 * NflBpgOffset is 16 bit value with 11 fractional bits
1384 		 * hence we multiply by 2^11 for preserving the
1385 		 * fractional part
1386 		 */
1387 		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
1388 							(vdsc_cfg->slice_height - 1));
1389 	else
1390 		vdsc_cfg->nfl_bpg_offset = 0;
1391 
1392 	/* Number of groups used to code the entire slice */
1393 	groups_total = groups_per_line * vdsc_cfg->slice_height;
1394 
1395 	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
1396 	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
1397 						    vdsc_cfg->initial_offset +
1398 						    num_extra_mux_bits) << 11),
1399 						  groups_total);
1400 
1401 	if (final_scale > 9) {
1402 		/*
1403 		 * ScaleIncrementInterval =
1404 		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
1405 		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
1406 		 * we need divide by 2^11 from pstDscCfg values
1407 		 */
1408 		vdsc_cfg->scale_increment_interval =
1409 				(vdsc_cfg->final_offset * (1 << 11)) /
1410 				((vdsc_cfg->nfl_bpg_offset +
1411 				vdsc_cfg->slice_bpg_offset) *
1412 				(final_scale - 9));
1413 	} else {
1414 		/*
1415 		 * If finalScaleValue is less than or equal to 9, a value of 0 should
1416 		 * be used to disable the scale increment at the end of the slice
1417 		 */
1418 		vdsc_cfg->scale_increment_interval = 0;
1419 	}
1420 
1421 	/*
1422 	 * DSC spec mentions that bits_per_pixel specifies the target
1423 	 * bits/pixel (bpp) rate that is used by the encoder,
1424 	 * in steps of 1/16 of a bit per pixel
1425 	 */
1426 	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
1427 		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
1428 			     vdsc_cfg->bits_per_pixel, 16) +
1429 		groups_per_line * vdsc_cfg->first_line_bpg_offset;
1430 
1431 	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
1432 	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
1433 	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
1434 
1435 	return 0;
1436 }
1437 EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
1438 
1439 /**
1440  * drm_dsc_get_bpp_int() - Get integer bits per pixel value for the given DRM DSC config
1441  * @vdsc_cfg: Pointer to DRM DSC config struct
1442  *
1443  * Return: Integer BPP value
1444  */
1445 u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg)
1446 {
1447 	WARN_ON_ONCE(vdsc_cfg->bits_per_pixel & 0xf);
1448 	return vdsc_cfg->bits_per_pixel >> 4;
1449 }
1450 EXPORT_SYMBOL(drm_dsc_get_bpp_int);
1451 
1452 /**
1453  * drm_dsc_initial_scale_value() - Calculate the initial scale value for the given DSC config
1454  * @dsc: Pointer to DRM DSC config struct
1455  *
1456  * Return: Calculated initial scale value
1457  */
1458 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc)
1459 {
1460 	return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset);
1461 }
1462 EXPORT_SYMBOL(drm_dsc_initial_scale_value);
1463 
1464 /**
1465  * drm_dsc_flatness_det_thresh() - Calculate the flatness_det_thresh for the given DSC config
1466  * @dsc: Pointer to DRM DSC config struct
1467  *
1468  * Return: Calculated flatness det thresh value
1469  */
1470 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc)
1471 {
1472 	return 2 << (dsc->bits_per_component - 8);
1473 }
1474 EXPORT_SYMBOL(drm_dsc_flatness_det_thresh);
1475