1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/backlight.h> 24 #include <linux/delay.h> 25 #include <linux/errno.h> 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/sched.h> 31 #include <linux/seq_file.h> 32 #include <linux/string_helpers.h> 33 34 #include <drm/display/drm_dp_helper.h> 35 #include <drm/display/drm_dp_mst_helper.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_print.h> 38 #include <drm/drm_vblank.h> 39 #include <drm/drm_panel.h> 40 41 #include "drm_dp_helper_internal.h" 42 43 struct dp_aux_backlight { 44 struct backlight_device *base; 45 struct drm_dp_aux *aux; 46 struct drm_edp_backlight_info info; 47 bool enabled; 48 }; 49 50 /** 51 * DOC: dp helpers 52 * 53 * These functions contain some common logic and helpers at various abstraction 54 * levels to deal with Display Port sink devices and related things like DP aux 55 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 56 * blocks, ... 57 */ 58 59 /* Helpers for DP link training */ 60 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 61 { 62 return link_status[r - DP_LANE0_1_STATUS]; 63 } 64 65 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 66 int lane) 67 { 68 int i = DP_LANE0_1_STATUS + (lane >> 1); 69 int s = (lane & 1) * 4; 70 u8 l = dp_link_status(link_status, i); 71 72 return (l >> s) & 0xf; 73 } 74 75 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 76 int lane_count) 77 { 78 u8 lane_align; 79 u8 lane_status; 80 int lane; 81 82 lane_align = dp_link_status(link_status, 83 DP_LANE_ALIGN_STATUS_UPDATED); 84 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 85 return false; 86 for (lane = 0; lane < lane_count; lane++) { 87 lane_status = dp_get_lane_status(link_status, lane); 88 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 89 return false; 90 } 91 return true; 92 } 93 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 94 95 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 96 int lane_count) 97 { 98 int lane; 99 u8 lane_status; 100 101 for (lane = 0; lane < lane_count; lane++) { 102 lane_status = dp_get_lane_status(link_status, lane); 103 if ((lane_status & DP_LANE_CR_DONE) == 0) 104 return false; 105 } 106 return true; 107 } 108 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 109 110 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 111 int lane) 112 { 113 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 114 int s = ((lane & 1) ? 115 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 116 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 117 u8 l = dp_link_status(link_status, i); 118 119 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 120 } 121 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 122 123 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 124 int lane) 125 { 126 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 127 int s = ((lane & 1) ? 128 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 129 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 130 u8 l = dp_link_status(link_status, i); 131 132 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 133 } 134 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 135 136 /* DP 2.0 128b/132b */ 137 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 138 int lane) 139 { 140 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 141 int s = ((lane & 1) ? 142 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : 143 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); 144 u8 l = dp_link_status(link_status, i); 145 146 return (l >> s) & 0xf; 147 } 148 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); 149 150 /* DP 2.0 errata for 128b/132b */ 151 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 152 int lane_count) 153 { 154 u8 lane_align, lane_status; 155 int lane; 156 157 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 158 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 159 return false; 160 161 for (lane = 0; lane < lane_count; lane++) { 162 lane_status = dp_get_lane_status(link_status, lane); 163 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE)) 164 return false; 165 } 166 return true; 167 } 168 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done); 169 170 /* DP 2.0 errata for 128b/132b */ 171 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 172 int lane_count) 173 { 174 u8 lane_status; 175 int lane; 176 177 for (lane = 0; lane < lane_count; lane++) { 178 lane_status = dp_get_lane_status(link_status, lane); 179 if (!(lane_status & DP_LANE_SYMBOL_LOCKED)) 180 return false; 181 } 182 return true; 183 } 184 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked); 185 186 /* DP 2.0 errata for 128b/132b */ 187 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 188 { 189 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 190 191 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE; 192 } 193 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done); 194 195 /* DP 2.0 errata for 128b/132b */ 196 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 197 { 198 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 199 200 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE; 201 } 202 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done); 203 204 /* DP 2.0 errata for 128b/132b */ 205 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) 206 { 207 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 208 209 return status & DP_128B132B_LT_FAILED; 210 } 211 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed); 212 213 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 214 { 215 if (rd_interval > 4) 216 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 217 aux->name, rd_interval); 218 219 if (rd_interval == 0) 220 return 100; 221 222 return rd_interval * 4 * USEC_PER_MSEC; 223 } 224 225 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 226 { 227 if (rd_interval > 4) 228 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 229 aux->name, rd_interval); 230 231 if (rd_interval == 0) 232 return 400; 233 234 return rd_interval * 4 * USEC_PER_MSEC; 235 } 236 237 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 238 { 239 switch (rd_interval) { 240 default: 241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", 242 aux->name, rd_interval); 243 fallthrough; 244 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US: 245 return 400; 246 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS: 247 return 4000; 248 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS: 249 return 8000; 250 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS: 251 return 12000; 252 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS: 253 return 16000; 254 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS: 255 return 32000; 256 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS: 257 return 64000; 258 } 259 } 260 261 /* 262 * The link training delays are different for: 263 * 264 * - Clock recovery vs. channel equalization 265 * - DPRX vs. LTTPR 266 * - 128b/132b vs. 8b/10b 267 * - DPCD rev 1.3 vs. later 268 * 269 * Get the correct delay in us, reading DPCD if necessary. 270 */ 271 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 272 enum drm_dp_phy dp_phy, bool uhbr, bool cr) 273 { 274 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); 275 unsigned int offset; 276 u8 rd_interval, mask; 277 278 if (dp_phy == DP_PHY_DPRX) { 279 if (uhbr) { 280 if (cr) 281 return 100; 282 283 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL; 284 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 285 parse = __128b132b_channel_eq_delay_us; 286 } else { 287 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 288 return 100; 289 290 offset = DP_TRAINING_AUX_RD_INTERVAL; 291 mask = DP_TRAINING_AUX_RD_MASK; 292 if (cr) 293 parse = __8b10b_clock_recovery_delay_us; 294 else 295 parse = __8b10b_channel_eq_delay_us; 296 } 297 } else { 298 if (uhbr) { 299 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 300 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 301 parse = __128b132b_channel_eq_delay_us; 302 } else { 303 if (cr) 304 return 100; 305 306 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 307 mask = DP_TRAINING_AUX_RD_MASK; 308 parse = __8b10b_channel_eq_delay_us; 309 } 310 } 311 312 if (offset < DP_RECEIVER_CAP_SIZE) { 313 rd_interval = dpcd[offset]; 314 } else { 315 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { 316 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", 317 aux->name); 318 /* arbitrary default delay */ 319 return 400; 320 } 321 } 322 323 return parse(aux, rd_interval & mask); 324 } 325 326 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 327 enum drm_dp_phy dp_phy, bool uhbr) 328 { 329 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 330 } 331 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay); 332 333 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 334 enum drm_dp_phy dp_phy, bool uhbr) 335 { 336 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 337 } 338 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); 339 340 /* Per DP 2.0 Errata */ 341 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) 342 { 343 int unit; 344 u8 val; 345 346 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { 347 drm_err(aux->drm_dev, "%s: failed rd interval read\n", 348 aux->name); 349 /* default to max */ 350 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 351 } 352 353 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; 354 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 355 356 return (val + 1) * unit * 1000; 357 } 358 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); 359 360 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 361 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 362 { 363 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 364 DP_TRAINING_AUX_RD_MASK; 365 int delay_us; 366 367 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 368 delay_us = 100; 369 else 370 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); 371 372 usleep_range(delay_us, delay_us * 2); 373 } 374 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 375 376 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 377 u8 rd_interval) 378 { 379 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); 380 381 usleep_range(delay_us, delay_us * 2); 382 } 383 384 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 385 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 386 { 387 __drm_dp_link_train_channel_eq_delay(aux, 388 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 389 DP_TRAINING_AUX_RD_MASK); 390 } 391 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 392 393 /** 394 * drm_dp_phy_name() - Get the name of the given DP PHY 395 * @dp_phy: The DP PHY identifier 396 * 397 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or 398 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always 399 * non-NULL and valid. 400 * 401 * Returns: Name of the DP PHY. 402 */ 403 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy) 404 { 405 static const char * const phy_names[] = { 406 [DP_PHY_DPRX] = "DPRX", 407 [DP_PHY_LTTPR1] = "LTTPR 1", 408 [DP_PHY_LTTPR2] = "LTTPR 2", 409 [DP_PHY_LTTPR3] = "LTTPR 3", 410 [DP_PHY_LTTPR4] = "LTTPR 4", 411 [DP_PHY_LTTPR5] = "LTTPR 5", 412 [DP_PHY_LTTPR6] = "LTTPR 6", 413 [DP_PHY_LTTPR7] = "LTTPR 7", 414 [DP_PHY_LTTPR8] = "LTTPR 8", 415 }; 416 417 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || 418 WARN_ON(!phy_names[dp_phy])) 419 return "<INVALID DP PHY>"; 420 421 return phy_names[dp_phy]; 422 } 423 EXPORT_SYMBOL(drm_dp_phy_name); 424 425 void drm_dp_lttpr_link_train_clock_recovery_delay(void) 426 { 427 usleep_range(100, 200); 428 } 429 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); 430 431 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) 432 { 433 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; 434 } 435 436 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 437 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) 438 { 439 u8 interval = dp_lttpr_phy_cap(phy_cap, 440 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & 441 DP_TRAINING_AUX_RD_MASK; 442 443 __drm_dp_link_train_channel_eq_delay(aux, interval); 444 } 445 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 446 447 u8 drm_dp_link_rate_to_bw_code(int link_rate) 448 { 449 switch (link_rate) { 450 case 1000000: 451 return DP_LINK_BW_10; 452 case 1350000: 453 return DP_LINK_BW_13_5; 454 case 2000000: 455 return DP_LINK_BW_20; 456 default: 457 /* Spec says link_bw = link_rate / 0.27Gbps */ 458 return link_rate / 27000; 459 } 460 } 461 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 462 463 int drm_dp_bw_code_to_link_rate(u8 link_bw) 464 { 465 switch (link_bw) { 466 case DP_LINK_BW_10: 467 return 1000000; 468 case DP_LINK_BW_13_5: 469 return 1350000; 470 case DP_LINK_BW_20: 471 return 2000000; 472 default: 473 /* Spec says link_rate = link_bw * 0.27Gbps */ 474 return link_bw * 27000; 475 } 476 } 477 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 478 479 #define AUX_RETRY_INTERVAL 500 /* us */ 480 481 static inline void 482 drm_dp_dump_access(const struct drm_dp_aux *aux, 483 u8 request, uint offset, void *buffer, int ret) 484 { 485 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 486 487 if (ret > 0) 488 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 489 aux->name, offset, arrow, ret, min(ret, 20), buffer); 490 else 491 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", 492 aux->name, offset, arrow, ret); 493 } 494 495 /** 496 * DOC: dp helpers 497 * 498 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 499 * independent access to AUX functionality. Drivers can take advantage of 500 * this by filling in the fields of the drm_dp_aux structure. 501 * 502 * Transactions are described using a hardware-independent drm_dp_aux_msg 503 * structure, which is passed into a driver's .transfer() implementation. 504 * Both native and I2C-over-AUX transactions are supported. 505 */ 506 507 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 508 unsigned int offset, void *buffer, size_t size) 509 { 510 struct drm_dp_aux_msg msg; 511 unsigned int retry, native_reply; 512 int err = 0, ret = 0; 513 514 memset(&msg, 0, sizeof(msg)); 515 msg.address = offset; 516 msg.request = request; 517 msg.buffer = buffer; 518 msg.size = size; 519 520 mutex_lock(&aux->hw_mutex); 521 522 /* 523 * The specification doesn't give any recommendation on how often to 524 * retry native transactions. We used to retry 7 times like for 525 * aux i2c transactions but real world devices this wasn't 526 * sufficient, bump to 32 which makes Dell 4k monitors happier. 527 */ 528 for (retry = 0; retry < 32; retry++) { 529 if (ret != 0 && ret != -ETIMEDOUT) { 530 usleep_range(AUX_RETRY_INTERVAL, 531 AUX_RETRY_INTERVAL + 100); 532 } 533 534 ret = aux->transfer(aux, &msg); 535 if (ret >= 0) { 536 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 537 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 538 if (ret == size) 539 goto unlock; 540 541 ret = -EPROTO; 542 } else 543 ret = -EIO; 544 } 545 546 /* 547 * We want the error we return to be the error we received on 548 * the first transaction, since we may get a different error the 549 * next time we retry 550 */ 551 if (!err) 552 err = ret; 553 } 554 555 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", 556 aux->name, err); 557 ret = err; 558 559 unlock: 560 mutex_unlock(&aux->hw_mutex); 561 return ret; 562 } 563 564 /** 565 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access 566 * @aux: DisplayPort AUX channel (SST) 567 * @offset: address of the register to probe 568 * 569 * Probe the provided DPCD address by reading 1 byte from it. The function can 570 * be used to trigger some side-effect the read access has, like waking up the 571 * sink, without the need for the read-out value. 572 * 573 * Returns 0 if the read access suceeded, or a negative error code on failure. 574 */ 575 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) 576 { 577 u8 buffer; 578 int ret; 579 580 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); 581 WARN_ON(ret == 0); 582 583 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); 584 585 return ret < 0 ? ret : 0; 586 } 587 EXPORT_SYMBOL(drm_dp_dpcd_probe); 588 589 /** 590 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 591 * @aux: DisplayPort AUX channel (SST or MST) 592 * @offset: address of the (first) register to read 593 * @buffer: buffer to store the register values 594 * @size: number of bytes in @buffer 595 * 596 * Returns the number of bytes transferred on success, or a negative error 597 * code on failure. -EIO is returned if the request was NAKed by the sink or 598 * if the retry count was exceeded. If not all bytes were transferred, this 599 * function returns -EPROTO. Errors from the underlying AUX channel transfer 600 * function, with the exception of -EBUSY (which causes the transaction to 601 * be retried), are propagated to the caller. 602 */ 603 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 604 void *buffer, size_t size) 605 { 606 int ret; 607 608 /* 609 * HP ZR24w corrupts the first DPCD access after entering power save 610 * mode. Eg. on a read, the entire buffer will be filled with the same 611 * byte. Do a throw away read to avoid corrupting anything we care 612 * about. Afterwards things will work correctly until the monitor 613 * gets woken up and subsequently re-enters power save mode. 614 * 615 * The user pressing any button on the monitor is enough to wake it 616 * up, so there is no particularly good place to do the workaround. 617 * We just have to do it before any DPCD access and hope that the 618 * monitor doesn't power down exactly after the throw away read. 619 */ 620 if (!aux->is_remote) { 621 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); 622 if (ret < 0) 623 return ret; 624 } 625 626 if (aux->is_remote) 627 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 628 else 629 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 630 buffer, size); 631 632 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 633 return ret; 634 } 635 EXPORT_SYMBOL(drm_dp_dpcd_read); 636 637 /** 638 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 639 * @aux: DisplayPort AUX channel (SST or MST) 640 * @offset: address of the (first) register to write 641 * @buffer: buffer containing the values to write 642 * @size: number of bytes in @buffer 643 * 644 * Returns the number of bytes transferred on success, or a negative error 645 * code on failure. -EIO is returned if the request was NAKed by the sink or 646 * if the retry count was exceeded. If not all bytes were transferred, this 647 * function returns -EPROTO. Errors from the underlying AUX channel transfer 648 * function, with the exception of -EBUSY (which causes the transaction to 649 * be retried), are propagated to the caller. 650 */ 651 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 652 void *buffer, size_t size) 653 { 654 int ret; 655 656 if (aux->is_remote) 657 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 658 else 659 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 660 buffer, size); 661 662 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 663 return ret; 664 } 665 EXPORT_SYMBOL(drm_dp_dpcd_write); 666 667 /** 668 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 669 * @aux: DisplayPort AUX channel 670 * @status: buffer to store the link status in (must be at least 6 bytes) 671 * 672 * Returns the number of bytes transferred on success or a negative error 673 * code on failure. 674 */ 675 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 676 u8 status[DP_LINK_STATUS_SIZE]) 677 { 678 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 679 DP_LINK_STATUS_SIZE); 680 } 681 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 682 683 /** 684 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY 685 * @aux: DisplayPort AUX channel 686 * @dp_phy: the DP PHY to get the link status for 687 * @link_status: buffer to return the status in 688 * 689 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The 690 * layout of the returned @link_status matches the DPCD register layout of the 691 * DPRX PHY link status. 692 * 693 * Returns 0 if the information was read successfully or a negative error code 694 * on failure. 695 */ 696 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 697 enum drm_dp_phy dp_phy, 698 u8 link_status[DP_LINK_STATUS_SIZE]) 699 { 700 int ret; 701 702 if (dp_phy == DP_PHY_DPRX) { 703 ret = drm_dp_dpcd_read(aux, 704 DP_LANE0_1_STATUS, 705 link_status, 706 DP_LINK_STATUS_SIZE); 707 708 if (ret < 0) 709 return ret; 710 711 WARN_ON(ret != DP_LINK_STATUS_SIZE); 712 713 return 0; 714 } 715 716 ret = drm_dp_dpcd_read(aux, 717 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), 718 link_status, 719 DP_LINK_STATUS_SIZE - 1); 720 721 if (ret < 0) 722 return ret; 723 724 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); 725 726 /* Convert the LTTPR to the sink PHY link status layout */ 727 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], 728 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], 729 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); 730 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; 731 732 return 0; 733 } 734 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 735 736 static bool is_edid_digital_input_dp(const struct edid *edid) 737 { 738 return edid && edid->revision >= 4 && 739 edid->input & DRM_EDID_INPUT_DIGITAL && 740 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 741 } 742 743 /** 744 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 745 * @dpcd: DisplayPort configuration data 746 * @port_cap: port capabilities 747 * @type: port type to be checked. Can be: 748 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 749 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 750 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 751 * 752 * Caveat: Only works with DPCD 1.1+ port caps. 753 * 754 * Returns: whether the downstream facing port matches the type. 755 */ 756 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 757 const u8 port_cap[4], u8 type) 758 { 759 return drm_dp_is_branch(dpcd) && 760 dpcd[DP_DPCD_REV] >= 0x11 && 761 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 762 } 763 EXPORT_SYMBOL(drm_dp_downstream_is_type); 764 765 /** 766 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 767 * @dpcd: DisplayPort configuration data 768 * @port_cap: port capabilities 769 * @edid: EDID 770 * 771 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 772 */ 773 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 774 const u8 port_cap[4], 775 const struct edid *edid) 776 { 777 if (dpcd[DP_DPCD_REV] < 0x11) { 778 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 779 case DP_DWN_STRM_PORT_TYPE_TMDS: 780 return true; 781 default: 782 return false; 783 } 784 } 785 786 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 787 case DP_DS_PORT_TYPE_DP_DUALMODE: 788 if (is_edid_digital_input_dp(edid)) 789 return false; 790 fallthrough; 791 case DP_DS_PORT_TYPE_DVI: 792 case DP_DS_PORT_TYPE_HDMI: 793 return true; 794 default: 795 return false; 796 } 797 } 798 EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 799 800 /** 801 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 802 * @aux: DisplayPort AUX channel 803 * @real_edid_checksum: real edid checksum for the last block 804 * 805 * Returns: 806 * True on success 807 */ 808 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 809 u8 real_edid_checksum) 810 { 811 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 812 813 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 814 &auto_test_req, 1) < 1) { 815 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 816 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 817 return false; 818 } 819 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 820 821 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 822 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 823 aux->name, DP_TEST_REQUEST); 824 return false; 825 } 826 link_edid_read &= DP_TEST_LINK_EDID_READ; 827 828 if (!auto_test_req || !link_edid_read) { 829 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", 830 aux->name); 831 return false; 832 } 833 834 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 835 &auto_test_req, 1) < 1) { 836 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 837 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 838 return false; 839 } 840 841 /* send back checksum for the last edid extension block data */ 842 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 843 &real_edid_checksum, 1) < 1) { 844 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 845 aux->name, DP_TEST_EDID_CHECKSUM); 846 return false; 847 } 848 849 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 850 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 851 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 852 aux->name, DP_TEST_RESPONSE); 853 return false; 854 } 855 856 return true; 857 } 858 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 859 860 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 861 { 862 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 863 864 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 865 port_count = 4; 866 867 return port_count; 868 } 869 870 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 871 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 872 { 873 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; 874 int ret; 875 876 /* 877 * Prior to DP1.3 the bit represented by 878 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 879 * If it is set DP_DPCD_REV at 0000h could be at a value less than 880 * the true capability of the panel. The only way to check is to 881 * then compare 0000h and 2200h. 882 */ 883 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 884 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 885 return 0; 886 887 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 888 sizeof(dpcd_ext)); 889 if (ret < 0) 890 return ret; 891 if (ret != sizeof(dpcd_ext)) 892 return -EIO; 893 894 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 895 drm_dbg_kms(aux->drm_dev, 896 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 897 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 898 return 0; 899 } 900 901 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 902 return 0; 903 904 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 905 906 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 907 908 return 0; 909 } 910 911 /** 912 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 913 * available 914 * @aux: DisplayPort AUX channel 915 * @dpcd: Buffer to store the resulting DPCD in 916 * 917 * Attempts to read the base DPCD caps for @aux. Additionally, this function 918 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 919 * present. 920 * 921 * Returns: %0 if the DPCD was read successfully, negative error code 922 * otherwise. 923 */ 924 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 925 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 926 { 927 int ret; 928 929 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 930 if (ret < 0) 931 return ret; 932 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 933 return -EIO; 934 935 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 936 if (ret < 0) 937 return ret; 938 939 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 940 941 return ret; 942 } 943 EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 944 945 /** 946 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 947 * @aux: DisplayPort AUX channel 948 * @dpcd: A cached copy of the port's DPCD 949 * @downstream_ports: buffer to store the downstream port info in 950 * 951 * See also: 952 * drm_dp_downstream_max_clock() 953 * drm_dp_downstream_max_bpc() 954 * 955 * Returns: 0 if either the downstream port info was read successfully or 956 * there was no downstream info to read, or a negative error code otherwise. 957 */ 958 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 959 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 960 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 961 { 962 int ret; 963 u8 len; 964 965 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 966 967 /* No downstream info to read */ 968 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) 969 return 0; 970 971 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 972 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 973 * some branches do it we need to handle it regardless. 974 */ 975 len = drm_dp_downstream_port_count(dpcd); 976 if (!len) 977 return 0; 978 979 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 980 len *= 4; 981 982 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 983 if (ret < 0) 984 return ret; 985 if (ret != len) 986 return -EIO; 987 988 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); 989 990 return 0; 991 } 992 EXPORT_SYMBOL(drm_dp_read_downstream_info); 993 994 /** 995 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 996 * @dpcd: DisplayPort configuration data 997 * @port_cap: port capabilities 998 * 999 * Returns: Downstream facing port max dot clock in kHz on success, 1000 * or 0 if max clock not defined 1001 */ 1002 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1003 const u8 port_cap[4]) 1004 { 1005 if (!drm_dp_is_branch(dpcd)) 1006 return 0; 1007 1008 if (dpcd[DP_DPCD_REV] < 0x11) 1009 return 0; 1010 1011 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1012 case DP_DS_PORT_TYPE_VGA: 1013 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1014 return 0; 1015 return port_cap[1] * 8000; 1016 default: 1017 return 0; 1018 } 1019 } 1020 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 1021 1022 /** 1023 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 1024 * @dpcd: DisplayPort configuration data 1025 * @port_cap: port capabilities 1026 * @edid: EDID 1027 * 1028 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 1029 * or 0 if max TMDS clock not defined 1030 */ 1031 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1032 const u8 port_cap[4], 1033 const struct edid *edid) 1034 { 1035 if (!drm_dp_is_branch(dpcd)) 1036 return 0; 1037 1038 if (dpcd[DP_DPCD_REV] < 0x11) { 1039 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1040 case DP_DWN_STRM_PORT_TYPE_TMDS: 1041 return 165000; 1042 default: 1043 return 0; 1044 } 1045 } 1046 1047 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1048 case DP_DS_PORT_TYPE_DP_DUALMODE: 1049 if (is_edid_digital_input_dp(edid)) 1050 return 0; 1051 /* 1052 * It's left up to the driver to check the 1053 * DP dual mode adapter's max TMDS clock. 1054 * 1055 * Unfortunately it looks like branch devices 1056 * may not fordward that the DP dual mode i2c 1057 * access so we just usually get i2c nak :( 1058 */ 1059 fallthrough; 1060 case DP_DS_PORT_TYPE_HDMI: 1061 /* 1062 * We should perhaps assume 165 MHz when detailed cap 1063 * info is not available. But looks like many typical 1064 * branch devices fall into that category and so we'd 1065 * probably end up with users complaining that they can't 1066 * get high resolution modes with their favorite dongle. 1067 * 1068 * So let's limit to 300 MHz instead since DPCD 1.4 1069 * HDMI 2.0 DFPs are required to have the detailed cap 1070 * info. So it's more likely we're dealing with a HDMI 1.4 1071 * compatible* device here. 1072 */ 1073 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1074 return 300000; 1075 return port_cap[1] * 2500; 1076 case DP_DS_PORT_TYPE_DVI: 1077 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1078 return 165000; 1079 /* FIXME what to do about DVI dual link? */ 1080 return port_cap[1] * 2500; 1081 default: 1082 return 0; 1083 } 1084 } 1085 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 1086 1087 /** 1088 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1089 * @dpcd: DisplayPort configuration data 1090 * @port_cap: port capabilities 1091 * @edid: EDID 1092 * 1093 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1094 * or 0 if max TMDS clock not defined 1095 */ 1096 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1097 const u8 port_cap[4], 1098 const struct edid *edid) 1099 { 1100 if (!drm_dp_is_branch(dpcd)) 1101 return 0; 1102 1103 if (dpcd[DP_DPCD_REV] < 0x11) { 1104 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1105 case DP_DWN_STRM_PORT_TYPE_TMDS: 1106 return 25000; 1107 default: 1108 return 0; 1109 } 1110 } 1111 1112 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1113 case DP_DS_PORT_TYPE_DP_DUALMODE: 1114 if (is_edid_digital_input_dp(edid)) 1115 return 0; 1116 fallthrough; 1117 case DP_DS_PORT_TYPE_DVI: 1118 case DP_DS_PORT_TYPE_HDMI: 1119 /* 1120 * Unclear whether the protocol converter could 1121 * utilize pixel replication. Assume it won't. 1122 */ 1123 return 25000; 1124 default: 1125 return 0; 1126 } 1127 } 1128 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 1129 1130 /** 1131 * drm_dp_downstream_max_bpc() - extract downstream facing port max 1132 * bits per component 1133 * @dpcd: DisplayPort configuration data 1134 * @port_cap: downstream facing port capabilities 1135 * @edid: EDID 1136 * 1137 * Returns: Max bpc on success or 0 if max bpc not defined 1138 */ 1139 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1140 const u8 port_cap[4], 1141 const struct edid *edid) 1142 { 1143 if (!drm_dp_is_branch(dpcd)) 1144 return 0; 1145 1146 if (dpcd[DP_DPCD_REV] < 0x11) { 1147 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1148 case DP_DWN_STRM_PORT_TYPE_DP: 1149 return 0; 1150 default: 1151 return 8; 1152 } 1153 } 1154 1155 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1156 case DP_DS_PORT_TYPE_DP: 1157 return 0; 1158 case DP_DS_PORT_TYPE_DP_DUALMODE: 1159 if (is_edid_digital_input_dp(edid)) 1160 return 0; 1161 fallthrough; 1162 case DP_DS_PORT_TYPE_HDMI: 1163 case DP_DS_PORT_TYPE_DVI: 1164 case DP_DS_PORT_TYPE_VGA: 1165 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1166 return 8; 1167 1168 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 1169 case DP_DS_8BPC: 1170 return 8; 1171 case DP_DS_10BPC: 1172 return 10; 1173 case DP_DS_12BPC: 1174 return 12; 1175 case DP_DS_16BPC: 1176 return 16; 1177 default: 1178 return 8; 1179 } 1180 break; 1181 default: 1182 return 8; 1183 } 1184 } 1185 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 1186 1187 /** 1188 * drm_dp_downstream_420_passthrough() - determine downstream facing port 1189 * YCbCr 4:2:0 pass-through capability 1190 * @dpcd: DisplayPort configuration data 1191 * @port_cap: downstream facing port capabilities 1192 * 1193 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 1194 */ 1195 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1196 const u8 port_cap[4]) 1197 { 1198 if (!drm_dp_is_branch(dpcd)) 1199 return false; 1200 1201 if (dpcd[DP_DPCD_REV] < 0x13) 1202 return false; 1203 1204 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1205 case DP_DS_PORT_TYPE_DP: 1206 return true; 1207 case DP_DS_PORT_TYPE_HDMI: 1208 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1209 return false; 1210 1211 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 1212 default: 1213 return false; 1214 } 1215 } 1216 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 1217 1218 /** 1219 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 1220 * YCbCr 4:4:4->4:2:0 conversion capability 1221 * @dpcd: DisplayPort configuration data 1222 * @port_cap: downstream facing port capabilities 1223 * 1224 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 1225 */ 1226 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1227 const u8 port_cap[4]) 1228 { 1229 if (!drm_dp_is_branch(dpcd)) 1230 return false; 1231 1232 if (dpcd[DP_DPCD_REV] < 0x13) 1233 return false; 1234 1235 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1236 case DP_DS_PORT_TYPE_HDMI: 1237 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1238 return false; 1239 1240 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 1241 default: 1242 return false; 1243 } 1244 } 1245 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 1246 1247 /** 1248 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port 1249 * RGB->YCbCr conversion capability 1250 * @dpcd: DisplayPort configuration data 1251 * @port_cap: downstream facing port capabilities 1252 * @color_spc: Colorspace for which conversion cap is sought 1253 * 1254 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given 1255 * colorspace. 1256 */ 1257 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1258 const u8 port_cap[4], 1259 u8 color_spc) 1260 { 1261 if (!drm_dp_is_branch(dpcd)) 1262 return false; 1263 1264 if (dpcd[DP_DPCD_REV] < 0x13) 1265 return false; 1266 1267 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1268 case DP_DS_PORT_TYPE_HDMI: 1269 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1270 return false; 1271 1272 return port_cap[3] & color_spc; 1273 default: 1274 return false; 1275 } 1276 } 1277 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion); 1278 1279 /** 1280 * drm_dp_downstream_mode() - return a mode for downstream facing port 1281 * @dev: DRM device 1282 * @dpcd: DisplayPort configuration data 1283 * @port_cap: port capabilities 1284 * 1285 * Provides a suitable mode for downstream facing ports without EDID. 1286 * 1287 * Returns: A new drm_display_mode on success or NULL on failure 1288 */ 1289 struct drm_display_mode * 1290 drm_dp_downstream_mode(struct drm_device *dev, 1291 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1292 const u8 port_cap[4]) 1293 1294 { 1295 u8 vic; 1296 1297 if (!drm_dp_is_branch(dpcd)) 1298 return NULL; 1299 1300 if (dpcd[DP_DPCD_REV] < 0x11) 1301 return NULL; 1302 1303 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1304 case DP_DS_PORT_TYPE_NON_EDID: 1305 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 1306 case DP_DS_NON_EDID_720x480i_60: 1307 vic = 6; 1308 break; 1309 case DP_DS_NON_EDID_720x480i_50: 1310 vic = 21; 1311 break; 1312 case DP_DS_NON_EDID_1920x1080i_60: 1313 vic = 5; 1314 break; 1315 case DP_DS_NON_EDID_1920x1080i_50: 1316 vic = 20; 1317 break; 1318 case DP_DS_NON_EDID_1280x720_60: 1319 vic = 4; 1320 break; 1321 case DP_DS_NON_EDID_1280x720_50: 1322 vic = 19; 1323 break; 1324 default: 1325 return NULL; 1326 } 1327 return drm_display_mode_from_cea_vic(dev, vic); 1328 default: 1329 return NULL; 1330 } 1331 } 1332 EXPORT_SYMBOL(drm_dp_downstream_mode); 1333 1334 /** 1335 * drm_dp_downstream_id() - identify branch device 1336 * @aux: DisplayPort AUX channel 1337 * @id: DisplayPort branch device id 1338 * 1339 * Returns branch device id on success or NULL on failure 1340 */ 1341 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 1342 { 1343 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 1344 } 1345 EXPORT_SYMBOL(drm_dp_downstream_id); 1346 1347 /** 1348 * drm_dp_downstream_debug() - debug DP branch devices 1349 * @m: pointer for debugfs file 1350 * @dpcd: DisplayPort configuration data 1351 * @port_cap: port capabilities 1352 * @edid: EDID 1353 * @aux: DisplayPort AUX channel 1354 * 1355 */ 1356 void drm_dp_downstream_debug(struct seq_file *m, 1357 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1358 const u8 port_cap[4], 1359 const struct edid *edid, 1360 struct drm_dp_aux *aux) 1361 { 1362 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1363 DP_DETAILED_CAP_INFO_AVAILABLE; 1364 int clk; 1365 int bpc; 1366 char id[7]; 1367 int len; 1368 uint8_t rev[2]; 1369 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1370 bool branch_device = drm_dp_is_branch(dpcd); 1371 1372 seq_printf(m, "\tDP branch device present: %s\n", 1373 str_yes_no(branch_device)); 1374 1375 if (!branch_device) 1376 return; 1377 1378 switch (type) { 1379 case DP_DS_PORT_TYPE_DP: 1380 seq_puts(m, "\t\tType: DisplayPort\n"); 1381 break; 1382 case DP_DS_PORT_TYPE_VGA: 1383 seq_puts(m, "\t\tType: VGA\n"); 1384 break; 1385 case DP_DS_PORT_TYPE_DVI: 1386 seq_puts(m, "\t\tType: DVI\n"); 1387 break; 1388 case DP_DS_PORT_TYPE_HDMI: 1389 seq_puts(m, "\t\tType: HDMI\n"); 1390 break; 1391 case DP_DS_PORT_TYPE_NON_EDID: 1392 seq_puts(m, "\t\tType: others without EDID support\n"); 1393 break; 1394 case DP_DS_PORT_TYPE_DP_DUALMODE: 1395 seq_puts(m, "\t\tType: DP++\n"); 1396 break; 1397 case DP_DS_PORT_TYPE_WIRELESS: 1398 seq_puts(m, "\t\tType: Wireless\n"); 1399 break; 1400 default: 1401 seq_puts(m, "\t\tType: N/A\n"); 1402 } 1403 1404 memset(id, 0, sizeof(id)); 1405 drm_dp_downstream_id(aux, id); 1406 seq_printf(m, "\t\tID: %s\n", id); 1407 1408 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1409 if (len > 0) 1410 seq_printf(m, "\t\tHW: %d.%d\n", 1411 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1412 1413 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1414 if (len > 0) 1415 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1416 1417 if (detailed_cap_info) { 1418 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1419 if (clk > 0) 1420 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1421 1422 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); 1423 if (clk > 0) 1424 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1425 1426 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); 1427 if (clk > 0) 1428 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1429 1430 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); 1431 1432 if (bpc > 0) 1433 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1434 } 1435 } 1436 EXPORT_SYMBOL(drm_dp_downstream_debug); 1437 1438 /** 1439 * drm_dp_subconnector_type() - get DP branch device type 1440 * @dpcd: DisplayPort configuration data 1441 * @port_cap: port capabilities 1442 */ 1443 enum drm_mode_subconnector 1444 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1445 const u8 port_cap[4]) 1446 { 1447 int type; 1448 if (!drm_dp_is_branch(dpcd)) 1449 return DRM_MODE_SUBCONNECTOR_Native; 1450 /* DP 1.0 approach */ 1451 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1452 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1453 DP_DWN_STRM_PORT_TYPE_MASK; 1454 1455 switch (type) { 1456 case DP_DWN_STRM_PORT_TYPE_TMDS: 1457 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1458 return DRM_MODE_SUBCONNECTOR_DVID; 1459 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1460 /* Can be VGA or DVI-A, VGA is more popular */ 1461 return DRM_MODE_SUBCONNECTOR_VGA; 1462 case DP_DWN_STRM_PORT_TYPE_DP: 1463 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1464 case DP_DWN_STRM_PORT_TYPE_OTHER: 1465 default: 1466 return DRM_MODE_SUBCONNECTOR_Unknown; 1467 } 1468 } 1469 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1470 1471 switch (type) { 1472 case DP_DS_PORT_TYPE_DP: 1473 case DP_DS_PORT_TYPE_DP_DUALMODE: 1474 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1475 case DP_DS_PORT_TYPE_VGA: 1476 return DRM_MODE_SUBCONNECTOR_VGA; 1477 case DP_DS_PORT_TYPE_DVI: 1478 return DRM_MODE_SUBCONNECTOR_DVID; 1479 case DP_DS_PORT_TYPE_HDMI: 1480 return DRM_MODE_SUBCONNECTOR_HDMIA; 1481 case DP_DS_PORT_TYPE_WIRELESS: 1482 return DRM_MODE_SUBCONNECTOR_Wireless; 1483 case DP_DS_PORT_TYPE_NON_EDID: 1484 default: 1485 return DRM_MODE_SUBCONNECTOR_Unknown; 1486 } 1487 } 1488 EXPORT_SYMBOL(drm_dp_subconnector_type); 1489 1490 /** 1491 * drm_dp_set_subconnector_property - set subconnector for DP connector 1492 * @connector: connector to set property on 1493 * @status: connector status 1494 * @dpcd: DisplayPort configuration data 1495 * @port_cap: port capabilities 1496 * 1497 * Called by a driver on every detect event. 1498 */ 1499 void drm_dp_set_subconnector_property(struct drm_connector *connector, 1500 enum drm_connector_status status, 1501 const u8 *dpcd, 1502 const u8 port_cap[4]) 1503 { 1504 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1505 1506 if (status == connector_status_connected) 1507 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1508 drm_object_property_set_value(&connector->base, 1509 connector->dev->mode_config.dp_subconnector_property, 1510 subconnector); 1511 } 1512 EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1513 1514 /** 1515 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1516 * count 1517 * @connector: The DRM connector to check 1518 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1519 * @desc: A cached copy of the connector's DP descriptor 1520 * 1521 * See also: drm_dp_read_sink_count() 1522 * 1523 * Returns: %True if the (e)DP connector has a valid sink count that should 1524 * be probed, %false otherwise. 1525 */ 1526 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1527 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1528 const struct drm_dp_desc *desc) 1529 { 1530 /* Some eDP panels don't set a valid value for the sink count */ 1531 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1532 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1533 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1534 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT); 1535 } 1536 EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1537 1538 /** 1539 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1540 * @aux: The DP AUX channel to use 1541 * 1542 * See also: drm_dp_read_sink_count_cap() 1543 * 1544 * Returns: The current sink count reported by @aux, or a negative error code 1545 * otherwise. 1546 */ 1547 int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1548 { 1549 u8 count; 1550 int ret; 1551 1552 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1553 if (ret < 0) 1554 return ret; 1555 if (ret != 1) 1556 return -EIO; 1557 1558 return DP_GET_SINK_COUNT(count); 1559 } 1560 EXPORT_SYMBOL(drm_dp_read_sink_count); 1561 1562 /* 1563 * I2C-over-AUX implementation 1564 */ 1565 1566 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1567 { 1568 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1569 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1570 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1571 I2C_FUNC_10BIT_ADDR; 1572 } 1573 1574 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1575 { 1576 /* 1577 * In case of i2c defer or short i2c ack reply to a write, 1578 * we need to switch to WRITE_STATUS_UPDATE to drain the 1579 * rest of the message 1580 */ 1581 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1582 msg->request &= DP_AUX_I2C_MOT; 1583 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1584 } 1585 } 1586 1587 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1588 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1589 #define AUX_STOP_LEN 4 1590 #define AUX_CMD_LEN 4 1591 #define AUX_ADDRESS_LEN 20 1592 #define AUX_REPLY_PAD_LEN 4 1593 #define AUX_LENGTH_LEN 8 1594 1595 /* 1596 * Calculate the duration of the AUX request/reply in usec. Gives the 1597 * "best" case estimate, ie. successful while as short as possible. 1598 */ 1599 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1600 { 1601 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1602 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1603 1604 if ((msg->request & DP_AUX_I2C_READ) == 0) 1605 len += msg->size * 8; 1606 1607 return len; 1608 } 1609 1610 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1611 { 1612 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1613 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1614 1615 /* 1616 * For read we expect what was asked. For writes there will 1617 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1618 */ 1619 if (msg->request & DP_AUX_I2C_READ) 1620 len += msg->size * 8; 1621 1622 return len; 1623 } 1624 1625 #define I2C_START_LEN 1 1626 #define I2C_STOP_LEN 1 1627 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1628 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1629 1630 /* 1631 * Calculate the length of the i2c transfer in usec, assuming 1632 * the i2c bus speed is as specified. Gives the "worst" 1633 * case estimate, ie. successful while as long as possible. 1634 * Doesn't account the "MOT" bit, and instead assumes each 1635 * message includes a START, ADDRESS and STOP. Neither does it 1636 * account for additional random variables such as clock stretching. 1637 */ 1638 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1639 int i2c_speed_khz) 1640 { 1641 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1642 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1643 msg->size * I2C_DATA_LEN + 1644 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1645 } 1646 1647 /* 1648 * Determine how many retries should be attempted to successfully transfer 1649 * the specified message, based on the estimated durations of the 1650 * i2c and AUX transfers. 1651 */ 1652 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1653 int i2c_speed_khz) 1654 { 1655 int aux_time_us = drm_dp_aux_req_duration(msg) + 1656 drm_dp_aux_reply_duration(msg); 1657 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1658 1659 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1660 } 1661 1662 /* 1663 * FIXME currently assumes 10 kHz as some real world devices seem 1664 * to require it. We should query/set the speed via DPCD if supported. 1665 */ 1666 static int dp_aux_i2c_speed_khz __read_mostly = 10; 1667 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1668 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1669 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1670 1671 /* 1672 * Transfer a single I2C-over-AUX message and handle various error conditions, 1673 * retrying the transaction as appropriate. It is assumed that the 1674 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1675 * reply field. 1676 * 1677 * Returns bytes transferred on success, or a negative error code on failure. 1678 */ 1679 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1680 { 1681 unsigned int retry, defer_i2c; 1682 int ret; 1683 /* 1684 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1685 * is required to retry at least seven times upon receiving AUX_DEFER 1686 * before giving up the AUX transaction. 1687 * 1688 * We also try to account for the i2c bus speed. 1689 */ 1690 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1691 1692 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1693 ret = aux->transfer(aux, msg); 1694 if (ret < 0) { 1695 if (ret == -EBUSY) 1696 continue; 1697 1698 /* 1699 * While timeouts can be errors, they're usually normal 1700 * behavior (for instance, when a driver tries to 1701 * communicate with a non-existent DisplayPort device). 1702 * Avoid spamming the kernel log with timeout errors. 1703 */ 1704 if (ret == -ETIMEDOUT) 1705 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", 1706 aux->name); 1707 else 1708 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", 1709 aux->name, ret); 1710 return ret; 1711 } 1712 1713 1714 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1715 case DP_AUX_NATIVE_REPLY_ACK: 1716 /* 1717 * For I2C-over-AUX transactions this isn't enough, we 1718 * need to check for the I2C ACK reply. 1719 */ 1720 break; 1721 1722 case DP_AUX_NATIVE_REPLY_NACK: 1723 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", 1724 aux->name, ret, msg->size); 1725 return -EREMOTEIO; 1726 1727 case DP_AUX_NATIVE_REPLY_DEFER: 1728 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); 1729 /* 1730 * We could check for I2C bit rate capabilities and if 1731 * available adjust this interval. We could also be 1732 * more careful with DP-to-legacy adapters where a 1733 * long legacy cable may force very low I2C bit rates. 1734 * 1735 * For now just defer for long enough to hopefully be 1736 * safe for all use-cases. 1737 */ 1738 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1739 continue; 1740 1741 default: 1742 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", 1743 aux->name, msg->reply); 1744 return -EREMOTEIO; 1745 } 1746 1747 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1748 case DP_AUX_I2C_REPLY_ACK: 1749 /* 1750 * Both native ACK and I2C ACK replies received. We 1751 * can assume the transfer was successful. 1752 */ 1753 if (ret != msg->size) 1754 drm_dp_i2c_msg_write_status_update(msg); 1755 return ret; 1756 1757 case DP_AUX_I2C_REPLY_NACK: 1758 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", 1759 aux->name, ret, msg->size); 1760 aux->i2c_nack_count++; 1761 return -EREMOTEIO; 1762 1763 case DP_AUX_I2C_REPLY_DEFER: 1764 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); 1765 /* DP Compliance Test 4.2.2.5 Requirement: 1766 * Must have at least 7 retries for I2C defers on the 1767 * transaction to pass this test 1768 */ 1769 aux->i2c_defer_count++; 1770 if (defer_i2c < 7) 1771 defer_i2c++; 1772 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1773 drm_dp_i2c_msg_write_status_update(msg); 1774 1775 continue; 1776 1777 default: 1778 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", 1779 aux->name, msg->reply); 1780 return -EREMOTEIO; 1781 } 1782 } 1783 1784 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); 1785 return -EREMOTEIO; 1786 } 1787 1788 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 1789 const struct i2c_msg *i2c_msg) 1790 { 1791 msg->request = (i2c_msg->flags & I2C_M_RD) ? 1792 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 1793 if (!(i2c_msg->flags & I2C_M_STOP)) 1794 msg->request |= DP_AUX_I2C_MOT; 1795 } 1796 1797 /* 1798 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 1799 * 1800 * Returns an error code on failure, or a recommended transfer size on success. 1801 */ 1802 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 1803 { 1804 int err, ret = orig_msg->size; 1805 struct drm_dp_aux_msg msg = *orig_msg; 1806 1807 while (msg.size > 0) { 1808 err = drm_dp_i2c_do_msg(aux, &msg); 1809 if (err <= 0) 1810 return err == 0 ? -EPROTO : err; 1811 1812 if (err < msg.size && err < ret) { 1813 drm_dbg_kms(aux->drm_dev, 1814 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 1815 aux->name, msg.size, err); 1816 ret = err; 1817 } 1818 1819 msg.size -= err; 1820 msg.buffer += err; 1821 } 1822 1823 return ret; 1824 } 1825 1826 /* 1827 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 1828 * packets to be as large as possible. If not, the I2C transactions never 1829 * succeed. Hence the default is maximum. 1830 */ 1831 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 1832 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 1833 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 1834 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 1835 1836 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 1837 int num) 1838 { 1839 struct drm_dp_aux *aux = adapter->algo_data; 1840 unsigned int i, j; 1841 unsigned transfer_size; 1842 struct drm_dp_aux_msg msg; 1843 int err = 0; 1844 1845 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 1846 1847 memset(&msg, 0, sizeof(msg)); 1848 1849 for (i = 0; i < num; i++) { 1850 msg.address = msgs[i].addr; 1851 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1852 /* Send a bare address packet to start the transaction. 1853 * Zero sized messages specify an address only (bare 1854 * address) transaction. 1855 */ 1856 msg.buffer = NULL; 1857 msg.size = 0; 1858 err = drm_dp_i2c_do_msg(aux, &msg); 1859 1860 /* 1861 * Reset msg.request in case in case it got 1862 * changed into a WRITE_STATUS_UPDATE. 1863 */ 1864 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1865 1866 if (err < 0) 1867 break; 1868 /* We want each transaction to be as large as possible, but 1869 * we'll go to smaller sizes if the hardware gives us a 1870 * short reply. 1871 */ 1872 transfer_size = dp_aux_i2c_transfer_size; 1873 for (j = 0; j < msgs[i].len; j += msg.size) { 1874 msg.buffer = msgs[i].buf + j; 1875 msg.size = min(transfer_size, msgs[i].len - j); 1876 1877 err = drm_dp_i2c_drain_msg(aux, &msg); 1878 1879 /* 1880 * Reset msg.request in case in case it got 1881 * changed into a WRITE_STATUS_UPDATE. 1882 */ 1883 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1884 1885 if (err < 0) 1886 break; 1887 transfer_size = err; 1888 } 1889 if (err < 0) 1890 break; 1891 } 1892 if (err >= 0) 1893 err = num; 1894 /* Send a bare address packet to close out the transaction. 1895 * Zero sized messages specify an address only (bare 1896 * address) transaction. 1897 */ 1898 msg.request &= ~DP_AUX_I2C_MOT; 1899 msg.buffer = NULL; 1900 msg.size = 0; 1901 (void)drm_dp_i2c_do_msg(aux, &msg); 1902 1903 return err; 1904 } 1905 1906 static const struct i2c_algorithm drm_dp_i2c_algo = { 1907 .functionality = drm_dp_i2c_functionality, 1908 .master_xfer = drm_dp_i2c_xfer, 1909 }; 1910 1911 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 1912 { 1913 return container_of(i2c, struct drm_dp_aux, ddc); 1914 } 1915 1916 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 1917 { 1918 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 1919 } 1920 1921 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 1922 { 1923 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 1924 } 1925 1926 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 1927 { 1928 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 1929 } 1930 1931 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 1932 .lock_bus = lock_bus, 1933 .trylock_bus = trylock_bus, 1934 .unlock_bus = unlock_bus, 1935 }; 1936 1937 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 1938 { 1939 u8 buf, count; 1940 int ret; 1941 1942 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1943 if (ret < 0) 1944 return ret; 1945 1946 WARN_ON(!(buf & DP_TEST_SINK_START)); 1947 1948 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 1949 if (ret < 0) 1950 return ret; 1951 1952 count = buf & DP_TEST_COUNT_MASK; 1953 if (count == aux->crc_count) 1954 return -EAGAIN; /* No CRC yet */ 1955 1956 aux->crc_count = count; 1957 1958 /* 1959 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 1960 * per component (RGB or CrYCb). 1961 */ 1962 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 1963 if (ret < 0) 1964 return ret; 1965 1966 return 0; 1967 } 1968 1969 static void drm_dp_aux_crc_work(struct work_struct *work) 1970 { 1971 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 1972 crc_work); 1973 struct drm_crtc *crtc; 1974 u8 crc_bytes[6]; 1975 uint32_t crcs[3]; 1976 int ret; 1977 1978 if (WARN_ON(!aux->crtc)) 1979 return; 1980 1981 crtc = aux->crtc; 1982 while (crtc->crc.opened) { 1983 drm_crtc_wait_one_vblank(crtc); 1984 if (!crtc->crc.opened) 1985 break; 1986 1987 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1988 if (ret == -EAGAIN) { 1989 usleep_range(1000, 2000); 1990 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1991 } 1992 1993 if (ret == -EAGAIN) { 1994 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", 1995 aux->name, ret); 1996 continue; 1997 } else if (ret) { 1998 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); 1999 continue; 2000 } 2001 2002 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 2003 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 2004 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 2005 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 2006 } 2007 } 2008 2009 /** 2010 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 2011 * @aux: DisplayPort AUX channel 2012 * 2013 * Used for remote aux channel in general. Merely initialize the crc work 2014 * struct. 2015 */ 2016 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 2017 { 2018 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2019 } 2020 EXPORT_SYMBOL(drm_dp_remote_aux_init); 2021 2022 /** 2023 * drm_dp_aux_init() - minimally initialise an aux channel 2024 * @aux: DisplayPort AUX channel 2025 * 2026 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with 2027 * the outside world, call drm_dp_aux_init() first. For drivers which are 2028 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a 2029 * &drm_connector), you must still call drm_dp_aux_register() once the connector 2030 * has been registered to allow userspace access to the auxiliary DP channel. 2031 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as 2032 * early as possible so that the &drm_device that corresponds to the AUX adapter 2033 * may be mentioned in debugging output from the DRM DP helpers. 2034 * 2035 * For devices which use a separate platform device for their AUX adapters, this 2036 * may be called as early as required by the driver. 2037 * 2038 */ 2039 void drm_dp_aux_init(struct drm_dp_aux *aux) 2040 { 2041 mutex_init(&aux->hw_mutex); 2042 mutex_init(&aux->cec.lock); 2043 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2044 2045 aux->ddc.algo = &drm_dp_i2c_algo; 2046 aux->ddc.algo_data = aux; 2047 aux->ddc.retries = 3; 2048 2049 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 2050 } 2051 EXPORT_SYMBOL(drm_dp_aux_init); 2052 2053 /** 2054 * drm_dp_aux_register() - initialise and register aux channel 2055 * @aux: DisplayPort AUX channel 2056 * 2057 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This 2058 * should only be called once the parent of @aux, &drm_dp_aux.dev, is 2059 * initialized. For devices which are grandparents of their AUX channels, 2060 * &drm_dp_aux.dev will typically be the &drm_connector &device which 2061 * corresponds to @aux. For these devices, it's advised to call 2062 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to 2063 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. 2064 * Functions which don't follow this will likely Oops when 2065 * %CONFIG_DRM_DP_AUX_CHARDEV is enabled. 2066 * 2067 * For devices where the AUX channel is a device that exists independently of 2068 * the &drm_device that uses it, such as SoCs and bridge devices, it is 2069 * recommended to call drm_dp_aux_register() after a &drm_device has been 2070 * assigned to &drm_dp_aux.drm_dev, and likewise to call 2071 * drm_dp_aux_unregister() once the &drm_device should no longer be associated 2072 * with the AUX channel (e.g. on bridge detach). 2073 * 2074 * Drivers which need to use the aux channel before either of the two points 2075 * mentioned above need to call drm_dp_aux_init() in order to use the AUX 2076 * channel before registration. 2077 * 2078 * Returns 0 on success or a negative error code on failure. 2079 */ 2080 int drm_dp_aux_register(struct drm_dp_aux *aux) 2081 { 2082 int ret; 2083 2084 WARN_ON_ONCE(!aux->drm_dev); 2085 2086 if (!aux->ddc.algo) 2087 drm_dp_aux_init(aux); 2088 2089 aux->ddc.class = I2C_CLASS_DDC; 2090 aux->ddc.owner = THIS_MODULE; 2091 aux->ddc.dev.parent = aux->dev; 2092 2093 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 2094 sizeof(aux->ddc.name)); 2095 2096 ret = drm_dp_aux_register_devnode(aux); 2097 if (ret) 2098 return ret; 2099 2100 ret = i2c_add_adapter(&aux->ddc); 2101 if (ret) { 2102 drm_dp_aux_unregister_devnode(aux); 2103 return ret; 2104 } 2105 2106 return 0; 2107 } 2108 EXPORT_SYMBOL(drm_dp_aux_register); 2109 2110 /** 2111 * drm_dp_aux_unregister() - unregister an AUX adapter 2112 * @aux: DisplayPort AUX channel 2113 */ 2114 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 2115 { 2116 drm_dp_aux_unregister_devnode(aux); 2117 i2c_del_adapter(&aux->ddc); 2118 } 2119 EXPORT_SYMBOL(drm_dp_aux_unregister); 2120 2121 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 2122 2123 /** 2124 * drm_dp_psr_setup_time() - PSR setup in time usec 2125 * @psr_cap: PSR capabilities from DPCD 2126 * 2127 * Returns: 2128 * PSR setup time for the panel in microseconds, negative 2129 * error code on failure. 2130 */ 2131 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 2132 { 2133 static const u16 psr_setup_time_us[] = { 2134 PSR_SETUP_TIME(330), 2135 PSR_SETUP_TIME(275), 2136 PSR_SETUP_TIME(220), 2137 PSR_SETUP_TIME(165), 2138 PSR_SETUP_TIME(110), 2139 PSR_SETUP_TIME(55), 2140 PSR_SETUP_TIME(0), 2141 }; 2142 int i; 2143 2144 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 2145 if (i >= ARRAY_SIZE(psr_setup_time_us)) 2146 return -EINVAL; 2147 2148 return psr_setup_time_us[i]; 2149 } 2150 EXPORT_SYMBOL(drm_dp_psr_setup_time); 2151 2152 #undef PSR_SETUP_TIME 2153 2154 /** 2155 * drm_dp_start_crc() - start capture of frame CRCs 2156 * @aux: DisplayPort AUX channel 2157 * @crtc: CRTC displaying the frames whose CRCs are to be captured 2158 * 2159 * Returns 0 on success or a negative error code on failure. 2160 */ 2161 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 2162 { 2163 u8 buf; 2164 int ret; 2165 2166 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2167 if (ret < 0) 2168 return ret; 2169 2170 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 2171 if (ret < 0) 2172 return ret; 2173 2174 aux->crc_count = 0; 2175 aux->crtc = crtc; 2176 schedule_work(&aux->crc_work); 2177 2178 return 0; 2179 } 2180 EXPORT_SYMBOL(drm_dp_start_crc); 2181 2182 /** 2183 * drm_dp_stop_crc() - stop capture of frame CRCs 2184 * @aux: DisplayPort AUX channel 2185 * 2186 * Returns 0 on success or a negative error code on failure. 2187 */ 2188 int drm_dp_stop_crc(struct drm_dp_aux *aux) 2189 { 2190 u8 buf; 2191 int ret; 2192 2193 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2194 if (ret < 0) 2195 return ret; 2196 2197 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 2198 if (ret < 0) 2199 return ret; 2200 2201 flush_work(&aux->crc_work); 2202 aux->crtc = NULL; 2203 2204 return 0; 2205 } 2206 EXPORT_SYMBOL(drm_dp_stop_crc); 2207 2208 struct dpcd_quirk { 2209 u8 oui[3]; 2210 u8 device_id[6]; 2211 bool is_branch; 2212 u32 quirks; 2213 }; 2214 2215 #define OUI(first, second, third) { (first), (second), (third) } 2216 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 2217 { (first), (second), (third), (fourth), (fifth), (sixth) } 2218 2219 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 2220 2221 static const struct dpcd_quirk dpcd_quirk_list[] = { 2222 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 2223 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2224 /* LG LP140WF6-SPM1 eDP panel */ 2225 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2226 /* Apple panels need some additional handling to support PSR */ 2227 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 2228 /* CH7511 seems to leave SINK_COUNT zeroed */ 2229 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 2230 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 2231 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 2232 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 2233 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 2234 }; 2235 2236 #undef OUI 2237 2238 /* 2239 * Get a bit mask of DPCD quirks for the sink/branch device identified by 2240 * ident. The quirk data is shared but it's up to the drivers to act on the 2241 * data. 2242 * 2243 * For now, only the OUI (first three bytes) is used, but this may be extended 2244 * to device identification string and hardware/firmware revisions later. 2245 */ 2246 static u32 2247 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 2248 { 2249 const struct dpcd_quirk *quirk; 2250 u32 quirks = 0; 2251 int i; 2252 u8 any_device[] = DEVICE_ID_ANY; 2253 2254 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 2255 quirk = &dpcd_quirk_list[i]; 2256 2257 if (quirk->is_branch != is_branch) 2258 continue; 2259 2260 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 2261 continue; 2262 2263 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 2264 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 2265 continue; 2266 2267 quirks |= quirk->quirks; 2268 } 2269 2270 return quirks; 2271 } 2272 2273 #undef DEVICE_ID_ANY 2274 #undef DEVICE_ID 2275 2276 /** 2277 * drm_dp_read_desc - read sink/branch descriptor from DPCD 2278 * @aux: DisplayPort AUX channel 2279 * @desc: Device descriptor to fill from DPCD 2280 * @is_branch: true for branch devices, false for sink devices 2281 * 2282 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 2283 * identification. 2284 * 2285 * Returns 0 on success or a negative error code on failure. 2286 */ 2287 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 2288 bool is_branch) 2289 { 2290 struct drm_dp_dpcd_ident *ident = &desc->ident; 2291 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 2292 int ret, dev_id_len; 2293 2294 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 2295 if (ret < 0) 2296 return ret; 2297 2298 desc->quirks = drm_dp_get_quirks(ident, is_branch); 2299 2300 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); 2301 2302 drm_dbg_kms(aux->drm_dev, 2303 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 2304 aux->name, is_branch ? "branch" : "sink", 2305 (int)sizeof(ident->oui), ident->oui, dev_id_len, 2306 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf, 2307 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks); 2308 2309 return 0; 2310 } 2311 EXPORT_SYMBOL(drm_dp_read_desc); 2312 2313 /** 2314 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2315 * supported by the DSC sink. 2316 * @dsc_dpcd: DSC capabilities from DPCD 2317 * @is_edp: true if its eDP, false for DP 2318 * 2319 * Read the slice capabilities DPCD register from DSC sink to get 2320 * the maximum slice count supported. This is used to populate 2321 * the DSC parameters in the &struct drm_dsc_config by the driver. 2322 * Driver creates an infoframe using these parameters to populate 2323 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2324 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2325 * 2326 * Returns: 2327 * Maximum slice count supported by DSC sink or 0 its invalid 2328 */ 2329 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2330 bool is_edp) 2331 { 2332 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2333 2334 if (is_edp) { 2335 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2336 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2337 return 4; 2338 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2339 return 2; 2340 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2341 return 1; 2342 } else { 2343 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2344 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2345 2346 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2347 return 24; 2348 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2349 return 20; 2350 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2351 return 16; 2352 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2353 return 12; 2354 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2355 return 10; 2356 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2357 return 8; 2358 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2359 return 6; 2360 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2361 return 4; 2362 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2363 return 2; 2364 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2365 return 1; 2366 } 2367 2368 return 0; 2369 } 2370 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2371 2372 /** 2373 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2374 * @dsc_dpcd: DSC capabilities from DPCD 2375 * 2376 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2377 * number of bits of precision within the decoder line buffer supported by 2378 * the DSC sink. This is used to populate the DSC parameters in the 2379 * &struct drm_dsc_config by the driver. 2380 * Driver creates an infoframe using these parameters to populate 2381 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2382 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2383 * 2384 * Returns: 2385 * Line buffer depth supported by DSC panel or 0 its invalid 2386 */ 2387 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2388 { 2389 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2390 2391 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2392 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2393 return 9; 2394 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2395 return 10; 2396 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2397 return 11; 2398 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2399 return 12; 2400 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2401 return 13; 2402 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2403 return 14; 2404 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2405 return 15; 2406 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2407 return 16; 2408 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2409 return 8; 2410 } 2411 2412 return 0; 2413 } 2414 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2415 2416 /** 2417 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2418 * values supported by the DSC sink. 2419 * @dsc_dpcd: DSC capabilities from DPCD 2420 * @dsc_bpc: An array to be filled by this helper with supported 2421 * input bpcs. 2422 * 2423 * Read the DSC DPCD from the sink device to parse the supported bits per 2424 * component values. This is used to populate the DSC parameters 2425 * in the &struct drm_dsc_config by the driver. 2426 * Driver creates an infoframe using these parameters to populate 2427 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2428 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2429 * 2430 * Returns: 2431 * Number of input BPC values parsed from the DPCD 2432 */ 2433 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2434 u8 dsc_bpc[3]) 2435 { 2436 int num_bpc = 0; 2437 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2438 2439 if (color_depth & DP_DSC_12_BPC) 2440 dsc_bpc[num_bpc++] = 12; 2441 if (color_depth & DP_DSC_10_BPC) 2442 dsc_bpc[num_bpc++] = 10; 2443 if (color_depth & DP_DSC_8_BPC) 2444 dsc_bpc[num_bpc++] = 8; 2445 2446 return num_bpc; 2447 } 2448 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2449 2450 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, 2451 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, 2452 u8 *buf, int buf_size) 2453 { 2454 /* 2455 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns 2456 * corrupted values when reading from the 0xF0000- range with a block 2457 * size bigger than 1. 2458 */ 2459 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; 2460 int offset; 2461 int ret; 2462 2463 for (offset = 0; offset < buf_size; offset += block_size) { 2464 ret = drm_dp_dpcd_read(aux, 2465 address + offset, 2466 &buf[offset], block_size); 2467 if (ret < 0) 2468 return ret; 2469 2470 WARN_ON(ret != block_size); 2471 } 2472 2473 return 0; 2474 } 2475 2476 /** 2477 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities 2478 * @aux: DisplayPort AUX channel 2479 * @dpcd: DisplayPort configuration data 2480 * @caps: buffer to return the capability info in 2481 * 2482 * Read capabilities common to all LTTPRs. 2483 * 2484 * Returns 0 on success or a negative error code on failure. 2485 */ 2486 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 2487 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2488 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2489 { 2490 return drm_dp_read_lttpr_regs(aux, dpcd, 2491 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 2492 caps, DP_LTTPR_COMMON_CAP_SIZE); 2493 } 2494 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 2495 2496 /** 2497 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY 2498 * @aux: DisplayPort AUX channel 2499 * @dpcd: DisplayPort configuration data 2500 * @dp_phy: LTTPR PHY to read the capabilities for 2501 * @caps: buffer to return the capability info in 2502 * 2503 * Read the capabilities for the given LTTPR PHY. 2504 * 2505 * Returns 0 on success or a negative error code on failure. 2506 */ 2507 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 2508 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2509 enum drm_dp_phy dp_phy, 2510 u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2511 { 2512 return drm_dp_read_lttpr_regs(aux, dpcd, 2513 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), 2514 caps, DP_LTTPR_PHY_CAP_SIZE); 2515 } 2516 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); 2517 2518 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) 2519 { 2520 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 2521 } 2522 2523 /** 2524 * drm_dp_lttpr_count - get the number of detected LTTPRs 2525 * @caps: LTTPR common capabilities 2526 * 2527 * Get the number of detected LTTPRs from the LTTPR common capabilities info. 2528 * 2529 * Returns: 2530 * -ERANGE if more than supported number (8) of LTTPRs are detected 2531 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value 2532 * otherwise the number of detected LTTPRs 2533 */ 2534 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2535 { 2536 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); 2537 2538 switch (hweight8(count)) { 2539 case 0: 2540 return 0; 2541 case 1: 2542 return 8 - ilog2(count); 2543 case 8: 2544 return -ERANGE; 2545 default: 2546 return -EINVAL; 2547 } 2548 } 2549 EXPORT_SYMBOL(drm_dp_lttpr_count); 2550 2551 /** 2552 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs 2553 * @caps: LTTPR common capabilities 2554 * 2555 * Returns the maximum link rate supported by all detected LTTPRs. 2556 */ 2557 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2558 { 2559 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); 2560 2561 return drm_dp_bw_code_to_link_rate(rate); 2562 } 2563 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2564 2565 /** 2566 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2567 * @caps: LTTPR common capabilities 2568 * 2569 * Returns the maximum lane count supported by all detected LTTPRs. 2570 */ 2571 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2572 { 2573 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); 2574 2575 return max_lanes & DP_MAX_LANE_COUNT_MASK; 2576 } 2577 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); 2578 2579 /** 2580 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support 2581 * @caps: LTTPR PHY capabilities 2582 * 2583 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2584 * voltage swing level 3. 2585 */ 2586 bool 2587 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2588 { 2589 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2590 2591 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; 2592 } 2593 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); 2594 2595 /** 2596 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support 2597 * @caps: LTTPR PHY capabilities 2598 * 2599 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2600 * pre-emphasis level 3. 2601 */ 2602 bool 2603 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2604 { 2605 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2606 2607 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; 2608 } 2609 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); 2610 2611 /** 2612 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2613 * @aux: DisplayPort AUX channel 2614 * @data: DP phy compliance test parameters. 2615 * 2616 * Returns 0 on success or a negative error code on failure. 2617 */ 2618 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2619 struct drm_dp_phy_test_params *data) 2620 { 2621 int err; 2622 u8 rate, lanes; 2623 2624 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2625 if (err < 0) 2626 return err; 2627 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 2628 2629 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2630 if (err < 0) 2631 return err; 2632 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2633 2634 if (lanes & DP_ENHANCED_FRAME_CAP) 2635 data->enhanced_frame_cap = true; 2636 2637 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 2638 if (err < 0) 2639 return err; 2640 2641 switch (data->phy_pattern) { 2642 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2643 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 2644 &data->custom80, sizeof(data->custom80)); 2645 if (err < 0) 2646 return err; 2647 2648 break; 2649 case DP_PHY_TEST_PATTERN_CP2520: 2650 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 2651 &data->hbr2_reset, 2652 sizeof(data->hbr2_reset)); 2653 if (err < 0) 2654 return err; 2655 } 2656 2657 return 0; 2658 } 2659 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 2660 2661 /** 2662 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 2663 * @aux: DisplayPort AUX channel 2664 * @data: DP phy compliance test parameters. 2665 * @dp_rev: DP revision to use for compliance testing 2666 * 2667 * Returns 0 on success or a negative error code on failure. 2668 */ 2669 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 2670 struct drm_dp_phy_test_params *data, u8 dp_rev) 2671 { 2672 int err, i; 2673 u8 test_pattern; 2674 2675 test_pattern = data->phy_pattern; 2676 if (dp_rev < 0x12) { 2677 test_pattern = (test_pattern << 2) & 2678 DP_LINK_QUAL_PATTERN_11_MASK; 2679 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 2680 test_pattern); 2681 if (err < 0) 2682 return err; 2683 } else { 2684 for (i = 0; i < data->num_lanes; i++) { 2685 err = drm_dp_dpcd_writeb(aux, 2686 DP_LINK_QUAL_LANE0_SET + i, 2687 test_pattern); 2688 if (err < 0) 2689 return err; 2690 } 2691 } 2692 2693 return 0; 2694 } 2695 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 2696 2697 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 2698 { 2699 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2700 return "Invalid"; 2701 2702 switch (pixelformat) { 2703 case DP_PIXELFORMAT_RGB: 2704 return "RGB"; 2705 case DP_PIXELFORMAT_YUV444: 2706 return "YUV444"; 2707 case DP_PIXELFORMAT_YUV422: 2708 return "YUV422"; 2709 case DP_PIXELFORMAT_YUV420: 2710 return "YUV420"; 2711 case DP_PIXELFORMAT_Y_ONLY: 2712 return "Y_ONLY"; 2713 case DP_PIXELFORMAT_RAW: 2714 return "RAW"; 2715 default: 2716 return "Reserved"; 2717 } 2718 } 2719 2720 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 2721 enum dp_colorimetry colorimetry) 2722 { 2723 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2724 return "Invalid"; 2725 2726 switch (colorimetry) { 2727 case DP_COLORIMETRY_DEFAULT: 2728 switch (pixelformat) { 2729 case DP_PIXELFORMAT_RGB: 2730 return "sRGB"; 2731 case DP_PIXELFORMAT_YUV444: 2732 case DP_PIXELFORMAT_YUV422: 2733 case DP_PIXELFORMAT_YUV420: 2734 return "BT.601"; 2735 case DP_PIXELFORMAT_Y_ONLY: 2736 return "DICOM PS3.14"; 2737 case DP_PIXELFORMAT_RAW: 2738 return "Custom Color Profile"; 2739 default: 2740 return "Reserved"; 2741 } 2742 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 2743 switch (pixelformat) { 2744 case DP_PIXELFORMAT_RGB: 2745 return "Wide Fixed"; 2746 case DP_PIXELFORMAT_YUV444: 2747 case DP_PIXELFORMAT_YUV422: 2748 case DP_PIXELFORMAT_YUV420: 2749 return "BT.709"; 2750 default: 2751 return "Reserved"; 2752 } 2753 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 2754 switch (pixelformat) { 2755 case DP_PIXELFORMAT_RGB: 2756 return "Wide Float"; 2757 case DP_PIXELFORMAT_YUV444: 2758 case DP_PIXELFORMAT_YUV422: 2759 case DP_PIXELFORMAT_YUV420: 2760 return "xvYCC 601"; 2761 default: 2762 return "Reserved"; 2763 } 2764 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 2765 switch (pixelformat) { 2766 case DP_PIXELFORMAT_RGB: 2767 return "OpRGB"; 2768 case DP_PIXELFORMAT_YUV444: 2769 case DP_PIXELFORMAT_YUV422: 2770 case DP_PIXELFORMAT_YUV420: 2771 return "xvYCC 709"; 2772 default: 2773 return "Reserved"; 2774 } 2775 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 2776 switch (pixelformat) { 2777 case DP_PIXELFORMAT_RGB: 2778 return "DCI-P3"; 2779 case DP_PIXELFORMAT_YUV444: 2780 case DP_PIXELFORMAT_YUV422: 2781 case DP_PIXELFORMAT_YUV420: 2782 return "sYCC 601"; 2783 default: 2784 return "Reserved"; 2785 } 2786 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 2787 switch (pixelformat) { 2788 case DP_PIXELFORMAT_RGB: 2789 return "Custom Profile"; 2790 case DP_PIXELFORMAT_YUV444: 2791 case DP_PIXELFORMAT_YUV422: 2792 case DP_PIXELFORMAT_YUV420: 2793 return "OpYCC 601"; 2794 default: 2795 return "Reserved"; 2796 } 2797 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 2798 switch (pixelformat) { 2799 case DP_PIXELFORMAT_RGB: 2800 return "BT.2020 RGB"; 2801 case DP_PIXELFORMAT_YUV444: 2802 case DP_PIXELFORMAT_YUV422: 2803 case DP_PIXELFORMAT_YUV420: 2804 return "BT.2020 CYCC"; 2805 default: 2806 return "Reserved"; 2807 } 2808 case DP_COLORIMETRY_BT2020_YCC: 2809 switch (pixelformat) { 2810 case DP_PIXELFORMAT_YUV444: 2811 case DP_PIXELFORMAT_YUV422: 2812 case DP_PIXELFORMAT_YUV420: 2813 return "BT.2020 YCC"; 2814 default: 2815 return "Reserved"; 2816 } 2817 default: 2818 return "Invalid"; 2819 } 2820 } 2821 2822 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 2823 { 2824 switch (dynamic_range) { 2825 case DP_DYNAMIC_RANGE_VESA: 2826 return "VESA range"; 2827 case DP_DYNAMIC_RANGE_CTA: 2828 return "CTA range"; 2829 default: 2830 return "Invalid"; 2831 } 2832 } 2833 2834 static const char *dp_content_type_get_name(enum dp_content_type content_type) 2835 { 2836 switch (content_type) { 2837 case DP_CONTENT_TYPE_NOT_DEFINED: 2838 return "Not defined"; 2839 case DP_CONTENT_TYPE_GRAPHICS: 2840 return "Graphics"; 2841 case DP_CONTENT_TYPE_PHOTO: 2842 return "Photo"; 2843 case DP_CONTENT_TYPE_VIDEO: 2844 return "Video"; 2845 case DP_CONTENT_TYPE_GAME: 2846 return "Game"; 2847 default: 2848 return "Reserved"; 2849 } 2850 } 2851 2852 void drm_dp_vsc_sdp_log(const char *level, struct device *dev, 2853 const struct drm_dp_vsc_sdp *vsc) 2854 { 2855 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__) 2856 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", 2857 vsc->revision, vsc->length); 2858 DP_SDP_LOG(" pixelformat: %s\n", 2859 dp_pixelformat_get_name(vsc->pixelformat)); 2860 DP_SDP_LOG(" colorimetry: %s\n", 2861 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 2862 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); 2863 DP_SDP_LOG(" dynamic range: %s\n", 2864 dp_dynamic_range_get_name(vsc->dynamic_range)); 2865 DP_SDP_LOG(" content type: %s\n", 2866 dp_content_type_get_name(vsc->content_type)); 2867 #undef DP_SDP_LOG 2868 } 2869 EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 2870 2871 /** 2872 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON 2873 * @dpcd: DisplayPort configuration data 2874 * @port_cap: port capabilities 2875 * 2876 * Returns maximum frl bandwidth supported by PCON in GBPS, 2877 * returns 0 if not supported. 2878 */ 2879 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2880 const u8 port_cap[4]) 2881 { 2882 int bw; 2883 u8 buf; 2884 2885 buf = port_cap[2]; 2886 bw = buf & DP_PCON_MAX_FRL_BW; 2887 2888 switch (bw) { 2889 case DP_PCON_MAX_9GBPS: 2890 return 9; 2891 case DP_PCON_MAX_18GBPS: 2892 return 18; 2893 case DP_PCON_MAX_24GBPS: 2894 return 24; 2895 case DP_PCON_MAX_32GBPS: 2896 return 32; 2897 case DP_PCON_MAX_40GBPS: 2898 return 40; 2899 case DP_PCON_MAX_48GBPS: 2900 return 48; 2901 case DP_PCON_MAX_0GBPS: 2902 default: 2903 return 0; 2904 } 2905 2906 return 0; 2907 } 2908 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); 2909 2910 /** 2911 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. 2912 * @aux: DisplayPort AUX channel 2913 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. 2914 * 2915 * Returns 0 if success, else returns negative error code. 2916 */ 2917 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) 2918 { 2919 int ret; 2920 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE | 2921 DP_PCON_ENABLE_LINK_FRL_MODE; 2922 2923 if (enable_frl_ready_hpd) 2924 buf |= DP_PCON_ENABLE_HPD_READY; 2925 2926 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 2927 2928 return ret; 2929 } 2930 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare); 2931 2932 /** 2933 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL 2934 * @aux: DisplayPort AUX channel 2935 * 2936 * Returns true if success, else returns false. 2937 */ 2938 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) 2939 { 2940 int ret; 2941 u8 buf; 2942 2943 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 2944 if (ret < 0) 2945 return false; 2946 2947 if (buf & DP_PCON_FRL_READY) 2948 return true; 2949 2950 return false; 2951 } 2952 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); 2953 2954 /** 2955 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 2956 * @aux: DisplayPort AUX channel 2957 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink 2958 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. 2959 * In Concurrent Mode, the FRL link bring up can be done along with 2960 * DP Link training. In Sequential mode, the FRL link bring up is done prior to 2961 * the DP Link training. 2962 * 2963 * Returns 0 if success, else returns negative error code. 2964 */ 2965 2966 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 2967 u8 frl_mode) 2968 { 2969 int ret; 2970 u8 buf; 2971 2972 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 2973 if (ret < 0) 2974 return ret; 2975 2976 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) 2977 buf |= DP_PCON_ENABLE_CONCURRENT_LINK; 2978 else 2979 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; 2980 2981 switch (max_frl_gbps) { 2982 case 9: 2983 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS; 2984 break; 2985 case 18: 2986 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS; 2987 break; 2988 case 24: 2989 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS; 2990 break; 2991 case 32: 2992 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS; 2993 break; 2994 case 40: 2995 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS; 2996 break; 2997 case 48: 2998 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS; 2999 break; 3000 case 0: 3001 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS; 3002 break; 3003 default: 3004 return -EINVAL; 3005 } 3006 3007 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3008 if (ret < 0) 3009 return ret; 3010 3011 return 0; 3012 } 3013 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); 3014 3015 /** 3016 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 3017 * @aux: DisplayPort AUX channel 3018 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink 3019 * @frl_type : FRL training type, can be Extended, or Normal. 3020 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask 3021 * starting from min, and stops when link training is successful. In Extended 3022 * FRL training, all frl bw selected in the mask are trained by the PCON. 3023 * 3024 * Returns 0 if success, else returns negative error code. 3025 */ 3026 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 3027 u8 frl_type) 3028 { 3029 int ret; 3030 u8 buf = max_frl_mask; 3031 3032 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) 3033 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3034 else 3035 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3036 3037 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); 3038 if (ret < 0) 3039 return ret; 3040 3041 return 0; 3042 } 3043 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2); 3044 3045 /** 3046 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. 3047 * @aux: DisplayPort AUX channel 3048 * 3049 * Returns 0 if success, else returns negative error code. 3050 */ 3051 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) 3052 { 3053 int ret; 3054 3055 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); 3056 if (ret < 0) 3057 return ret; 3058 3059 return 0; 3060 } 3061 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config); 3062 3063 /** 3064 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL 3065 * @aux: DisplayPort AUX channel 3066 * 3067 * Returns 0 if success, else returns negative error code. 3068 */ 3069 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) 3070 { 3071 int ret; 3072 u8 buf = 0; 3073 3074 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3075 if (ret < 0) 3076 return ret; 3077 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) { 3078 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", 3079 aux->name); 3080 return -EINVAL; 3081 } 3082 buf |= DP_PCON_ENABLE_HDMI_LINK; 3083 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3084 if (ret < 0) 3085 return ret; 3086 3087 return 0; 3088 } 3089 EXPORT_SYMBOL(drm_dp_pcon_frl_enable); 3090 3091 /** 3092 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. 3093 * @aux: DisplayPort AUX channel 3094 * 3095 * Returns true if link is active else returns false. 3096 */ 3097 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) 3098 { 3099 u8 buf; 3100 int ret; 3101 3102 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3103 if (ret < 0) 3104 return false; 3105 3106 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; 3107 } 3108 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active); 3109 3110 /** 3111 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE 3112 * @aux: DisplayPort AUX channel 3113 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. 3114 * Valid only if the MODE returned is FRL. For Normal Link training mode 3115 * only 1 of the bits will be set, but in case of Extended mode, more than 3116 * one bits can be set. 3117 * 3118 * Returns the link mode : TMDS or FRL on success, else returns negative error 3119 * code. 3120 */ 3121 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) 3122 { 3123 u8 buf; 3124 int mode; 3125 int ret; 3126 3127 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); 3128 if (ret < 0) 3129 return ret; 3130 3131 mode = buf & DP_PCON_HDMI_LINK_MODE; 3132 3133 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode) 3134 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1; 3135 3136 return mode; 3137 } 3138 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode); 3139 3140 /** 3141 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane 3142 * during link failure between PCON and HDMI sink 3143 * @aux: DisplayPort AUX channel 3144 * @connector: DRM connector 3145 * code. 3146 **/ 3147 3148 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 3149 struct drm_connector *connector) 3150 { 3151 u8 buf, error_count; 3152 int i, num_error; 3153 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3154 3155 for (i = 0; i < hdmi->max_lanes; i++) { 3156 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) 3157 return; 3158 3159 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK; 3160 switch (error_count) { 3161 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS: 3162 num_error = 100; 3163 break; 3164 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS: 3165 num_error = 10; 3166 break; 3167 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS: 3168 num_error = 3; 3169 break; 3170 default: 3171 num_error = 0; 3172 } 3173 3174 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", 3175 aux->name, num_error, i); 3176 } 3177 } 3178 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count); 3179 3180 /* 3181 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 3182 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3183 * 3184 * Returns true is PCON encoder is DSC 1.2 else returns false. 3185 */ 3186 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3187 { 3188 u8 buf; 3189 u8 major_v, minor_v; 3190 3191 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; 3192 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT; 3193 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT; 3194 3195 if (major_v == 1 && minor_v == 2) 3196 return true; 3197 3198 return false; 3199 } 3200 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2); 3201 3202 /* 3203 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder 3204 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3205 * 3206 * Returns maximum no. of slices supported by the PCON DSC Encoder. 3207 */ 3208 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3209 { 3210 u8 slice_cap1, slice_cap2; 3211 3212 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; 3213 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; 3214 3215 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC) 3216 return 24; 3217 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC) 3218 return 20; 3219 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC) 3220 return 16; 3221 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC) 3222 return 12; 3223 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC) 3224 return 10; 3225 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC) 3226 return 8; 3227 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC) 3228 return 6; 3229 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC) 3230 return 4; 3231 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC) 3232 return 2; 3233 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC) 3234 return 1; 3235 3236 return 0; 3237 } 3238 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices); 3239 3240 /* 3241 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder 3242 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3243 * 3244 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. 3245 */ 3246 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3247 { 3248 u8 buf; 3249 3250 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; 3251 3252 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; 3253 } 3254 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width); 3255 3256 /* 3257 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder 3258 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3259 * 3260 * Returns the bpp precision supported by the PCON encoder. 3261 */ 3262 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3263 { 3264 u8 buf; 3265 3266 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; 3267 3268 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) { 3269 case DP_PCON_DSC_ONE_16TH_BPP: 3270 return 16; 3271 case DP_PCON_DSC_ONE_8TH_BPP: 3272 return 8; 3273 case DP_PCON_DSC_ONE_4TH_BPP: 3274 return 4; 3275 case DP_PCON_DSC_ONE_HALF_BPP: 3276 return 2; 3277 case DP_PCON_DSC_ONE_BPP: 3278 return 1; 3279 } 3280 3281 return 0; 3282 } 3283 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr); 3284 3285 static 3286 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) 3287 { 3288 u8 buf; 3289 int ret; 3290 3291 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3292 if (ret < 0) 3293 return ret; 3294 3295 buf |= DP_PCON_ENABLE_DSC_ENCODER; 3296 3297 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) { 3298 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK; 3299 buf |= pps_buf_config << 2; 3300 } 3301 3302 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3303 if (ret < 0) 3304 return ret; 3305 3306 return 0; 3307 } 3308 3309 /** 3310 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters 3311 * for DSC1.2 between PCON & HDMI2.1 sink 3312 * @aux: DisplayPort AUX channel 3313 * 3314 * Returns 0 on success, else returns negative error code. 3315 */ 3316 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) 3317 { 3318 int ret; 3319 3320 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); 3321 if (ret < 0) 3322 return ret; 3323 3324 return 0; 3325 } 3326 EXPORT_SYMBOL(drm_dp_pcon_pps_default); 3327 3328 /** 3329 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for 3330 * HDMI sink 3331 * @aux: DisplayPort AUX channel 3332 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. 3333 * 3334 * Returns 0 on success, else returns negative error code. 3335 */ 3336 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) 3337 { 3338 int ret; 3339 3340 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); 3341 if (ret < 0) 3342 return ret; 3343 3344 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3345 if (ret < 0) 3346 return ret; 3347 3348 return 0; 3349 } 3350 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf); 3351 3352 /* 3353 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder 3354 * override registers 3355 * @aux: DisplayPort AUX channel 3356 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, 3357 * bits_per_pixel. 3358 * 3359 * Returns 0 on success, else returns negative error code. 3360 */ 3361 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) 3362 { 3363 int ret; 3364 3365 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); 3366 if (ret < 0) 3367 return ret; 3368 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); 3369 if (ret < 0) 3370 return ret; 3371 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); 3372 if (ret < 0) 3373 return ret; 3374 3375 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3376 if (ret < 0) 3377 return ret; 3378 3379 return 0; 3380 } 3381 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param); 3382 3383 /* 3384 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr 3385 * @aux: displayPort AUX channel 3386 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. 3387 * 3388 * Returns 0 on success, else returns negative error code. 3389 */ 3390 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) 3391 { 3392 int ret; 3393 u8 buf; 3394 3395 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3396 if (ret < 0) 3397 return ret; 3398 3399 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK) 3400 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK); 3401 else 3402 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK; 3403 3404 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3405 if (ret < 0) 3406 return ret; 3407 3408 return 0; 3409 } 3410 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr); 3411 3412 /** 3413 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX 3414 * @aux: The DP AUX channel to use 3415 * @bl: Backlight capability info from drm_edp_backlight_init() 3416 * @level: The brightness level to set 3417 * 3418 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must 3419 * already have been enabled by the driver by calling drm_edp_backlight_enable(). 3420 * 3421 * Returns: %0 on success, negative error code on failure 3422 */ 3423 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3424 u16 level) 3425 { 3426 int ret; 3427 u8 buf[2] = { 0 }; 3428 3429 /* The panel uses the PWM for controlling brightness levels */ 3430 if (!bl->aux_set) 3431 return 0; 3432 3433 if (bl->lsb_reg_used) { 3434 buf[0] = (level & 0xff00) >> 8; 3435 buf[1] = (level & 0x00ff); 3436 } else { 3437 buf[0] = level; 3438 } 3439 3440 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); 3441 if (ret != sizeof(buf)) { 3442 drm_err(aux->drm_dev, 3443 "%s: Failed to write aux backlight level: %d\n", 3444 aux->name, ret); 3445 return ret < 0 ? ret : -EIO; 3446 } 3447 3448 return 0; 3449 } 3450 EXPORT_SYMBOL(drm_edp_backlight_set_level); 3451 3452 static int 3453 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3454 bool enable) 3455 { 3456 int ret; 3457 u8 buf; 3458 3459 /* This panel uses the EDP_BL_PWR GPIO for enablement */ 3460 if (!bl->aux_enable) 3461 return 0; 3462 3463 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); 3464 if (ret != 1) { 3465 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", 3466 aux->name, ret); 3467 return ret < 0 ? ret : -EIO; 3468 } 3469 if (enable) 3470 buf |= DP_EDP_BACKLIGHT_ENABLE; 3471 else 3472 buf &= ~DP_EDP_BACKLIGHT_ENABLE; 3473 3474 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); 3475 if (ret != 1) { 3476 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", 3477 aux->name, ret); 3478 return ret < 0 ? ret : -EIO; 3479 } 3480 3481 return 0; 3482 } 3483 3484 /** 3485 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD 3486 * @aux: The DP AUX channel to use 3487 * @bl: Backlight capability info from drm_edp_backlight_init() 3488 * @level: The initial backlight level to set via AUX, if there is one 3489 * 3490 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally 3491 * restoring any important backlight state such as the given backlight level, the brightness byte 3492 * count, backlight frequency, etc. 3493 * 3494 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3495 * that the driver handle enabling/disabling the panel through implementation-specific means using 3496 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3497 * this function becomes a no-op, and the driver is expected to handle powering the panel on using 3498 * the EDP_BL_PWR GPIO. 3499 * 3500 * Returns: %0 on success, negative error code on failure. 3501 */ 3502 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3503 const u16 level) 3504 { 3505 int ret; 3506 u8 dpcd_buf; 3507 3508 if (bl->aux_set) 3509 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; 3510 else 3511 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM; 3512 3513 if (bl->pwmgen_bit_count) { 3514 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); 3515 if (ret != 1) 3516 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3517 aux->name, ret); 3518 } 3519 3520 if (bl->pwm_freq_pre_divider) { 3521 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); 3522 if (ret != 1) 3523 drm_dbg_kms(aux->drm_dev, 3524 "%s: Failed to write aux backlight frequency: %d\n", 3525 aux->name, ret); 3526 else 3527 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; 3528 } 3529 3530 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); 3531 if (ret != 1) { 3532 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", 3533 aux->name, ret); 3534 return ret < 0 ? ret : -EIO; 3535 } 3536 3537 ret = drm_edp_backlight_set_level(aux, bl, level); 3538 if (ret < 0) 3539 return ret; 3540 ret = drm_edp_backlight_set_enable(aux, bl, true); 3541 if (ret < 0) 3542 return ret; 3543 3544 return 0; 3545 } 3546 EXPORT_SYMBOL(drm_edp_backlight_enable); 3547 3548 /** 3549 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported 3550 * @aux: The DP AUX channel to use 3551 * @bl: Backlight capability info from drm_edp_backlight_init() 3552 * 3553 * This function handles disabling DPCD backlight controls on a panel over AUX. 3554 * 3555 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3556 * that the driver handle enabling/disabling the panel through implementation-specific means using 3557 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3558 * this function becomes a no-op, and the driver is expected to handle powering the panel off using 3559 * the EDP_BL_PWR GPIO. 3560 * 3561 * Returns: %0 on success or no-op, negative error code on failure. 3562 */ 3563 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) 3564 { 3565 int ret; 3566 3567 ret = drm_edp_backlight_set_enable(aux, bl, false); 3568 if (ret < 0) 3569 return ret; 3570 3571 return 0; 3572 } 3573 EXPORT_SYMBOL(drm_edp_backlight_disable); 3574 3575 static inline int 3576 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3577 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 3578 { 3579 int fxp, fxp_min, fxp_max, fxp_actual, f = 1; 3580 int ret; 3581 u8 pn, pn_min, pn_max; 3582 3583 if (!bl->aux_set) 3584 return 0; 3585 3586 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); 3587 if (ret != 1) { 3588 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", 3589 aux->name, ret); 3590 return -ENODEV; 3591 } 3592 3593 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3594 bl->max = (1 << pn) - 1; 3595 if (!driver_pwm_freq_hz) 3596 return 0; 3597 3598 /* 3599 * Set PWM Frequency divider to match desired frequency provided by the driver. 3600 * The PWM Frequency is calculated as 27Mhz / (F x P). 3601 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the 3602 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) 3603 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the 3604 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) 3605 */ 3606 3607 /* Find desired value of (F x P) 3608 * Note that, if F x P is out of supported range, the maximum value or minimum value will 3609 * applied automatically. So no need to check that. 3610 */ 3611 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz); 3612 3613 /* Use highest possible value of Pn for more granularity of brightness adjustment while 3614 * satisfying the conditions below. 3615 * - Pn is in the range of Pn_min and Pn_max 3616 * - F is in the range of 1 and 255 3617 * - FxP is within 25% of desired value. 3618 * Note: 25% is arbitrary value and may need some tweak. 3619 */ 3620 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); 3621 if (ret != 1) { 3622 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", 3623 aux->name, ret); 3624 return 0; 3625 } 3626 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); 3627 if (ret != 1) { 3628 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", 3629 aux->name, ret); 3630 return 0; 3631 } 3632 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3633 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3634 3635 /* Ensure frequency is within 25% of desired value */ 3636 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); 3637 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); 3638 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { 3639 drm_dbg_kms(aux->drm_dev, 3640 "%s: Driver defined backlight frequency (%d) out of range\n", 3641 aux->name, driver_pwm_freq_hz); 3642 return 0; 3643 } 3644 3645 for (pn = pn_max; pn >= pn_min; pn--) { 3646 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); 3647 fxp_actual = f << pn; 3648 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) 3649 break; 3650 } 3651 3652 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); 3653 if (ret != 1) { 3654 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3655 aux->name, ret); 3656 return 0; 3657 } 3658 bl->pwmgen_bit_count = pn; 3659 bl->max = (1 << pn) - 1; 3660 3661 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) { 3662 bl->pwm_freq_pre_divider = f; 3663 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", 3664 aux->name, driver_pwm_freq_hz); 3665 } 3666 3667 return 0; 3668 } 3669 3670 static inline int 3671 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3672 u8 *current_mode) 3673 { 3674 int ret; 3675 u8 buf[2]; 3676 u8 mode_reg; 3677 3678 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); 3679 if (ret != 1) { 3680 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", 3681 aux->name, ret); 3682 return ret < 0 ? ret : -EIO; 3683 } 3684 3685 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK); 3686 if (!bl->aux_set) 3687 return 0; 3688 3689 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { 3690 int size = 1 + bl->lsb_reg_used; 3691 3692 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); 3693 if (ret != size) { 3694 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", 3695 aux->name, ret); 3696 return ret < 0 ? ret : -EIO; 3697 } 3698 3699 if (bl->lsb_reg_used) 3700 return (buf[0] << 8) | buf[1]; 3701 else 3702 return buf[0]; 3703 } 3704 3705 /* 3706 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and 3707 * the driver should assume max brightness 3708 */ 3709 return bl->max; 3710 } 3711 3712 /** 3713 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight 3714 * interface. 3715 * @aux: The DP aux device to use for probing 3716 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight 3717 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz 3718 * @edp_dpcd: A cached copy of the eDP DPCD 3719 * @current_level: Where to store the probed brightness level, if any 3720 * @current_mode: Where to store the currently set backlight control mode 3721 * 3722 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, 3723 * along with also probing the current and maximum supported brightness levels. 3724 * 3725 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the 3726 * default frequency from the panel is used. 3727 * 3728 * Returns: %0 on success, negative error code on failure. 3729 */ 3730 int 3731 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3732 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 3733 u16 *current_level, u8 *current_mode) 3734 { 3735 int ret; 3736 3737 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) 3738 bl->aux_enable = true; 3739 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) 3740 bl->aux_set = true; 3741 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 3742 bl->lsb_reg_used = true; 3743 3744 /* Sanity check caps */ 3745 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { 3746 drm_dbg_kms(aux->drm_dev, 3747 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", 3748 aux->name); 3749 return -EINVAL; 3750 } 3751 3752 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); 3753 if (ret < 0) 3754 return ret; 3755 3756 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); 3757 if (ret < 0) 3758 return ret; 3759 *current_level = ret; 3760 3761 drm_dbg_kms(aux->drm_dev, 3762 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n", 3763 aux->name, bl->aux_set, bl->aux_enable, *current_mode); 3764 if (bl->aux_set) { 3765 drm_dbg_kms(aux->drm_dev, 3766 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n", 3767 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, 3768 bl->lsb_reg_used); 3769 } 3770 3771 return 0; 3772 } 3773 EXPORT_SYMBOL(drm_edp_backlight_init); 3774 3775 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 3776 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) 3777 3778 static int dp_aux_backlight_update_status(struct backlight_device *bd) 3779 { 3780 struct dp_aux_backlight *bl = bl_get_data(bd); 3781 u16 brightness = backlight_get_brightness(bd); 3782 int ret = 0; 3783 3784 if (!backlight_is_blank(bd)) { 3785 if (!bl->enabled) { 3786 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); 3787 bl->enabled = true; 3788 return 0; 3789 } 3790 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); 3791 } else { 3792 if (bl->enabled) { 3793 drm_edp_backlight_disable(bl->aux, &bl->info); 3794 bl->enabled = false; 3795 } 3796 } 3797 3798 return ret; 3799 } 3800 3801 static const struct backlight_ops dp_aux_bl_ops = { 3802 .update_status = dp_aux_backlight_update_status, 3803 }; 3804 3805 /** 3806 * drm_panel_dp_aux_backlight - create and use DP AUX backlight 3807 * @panel: DRM panel 3808 * @aux: The DP AUX channel to use 3809 * 3810 * Use this function to create and handle backlight if your panel 3811 * supports backlight control over DP AUX channel using DPCD 3812 * registers as per VESA's standard backlight control interface. 3813 * 3814 * When the panel is enabled backlight will be enabled after a 3815 * successful call to &drm_panel_funcs.enable() 3816 * 3817 * When the panel is disabled backlight will be disabled before the 3818 * call to &drm_panel_funcs.disable(). 3819 * 3820 * A typical implementation for a panel driver supporting backlight 3821 * control over DP AUX will call this function at probe time. 3822 * Backlight will then be handled transparently without requiring 3823 * any intervention from the driver. 3824 * 3825 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). 3826 * 3827 * Return: 0 on success or a negative error code on failure. 3828 */ 3829 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 3830 { 3831 struct dp_aux_backlight *bl; 3832 struct backlight_properties props = { 0 }; 3833 u16 current_level; 3834 u8 current_mode; 3835 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 3836 int ret; 3837 3838 if (!panel || !panel->dev || !aux) 3839 return -EINVAL; 3840 3841 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, 3842 EDP_DISPLAY_CTL_CAP_SIZE); 3843 if (ret < 0) 3844 return ret; 3845 3846 if (!drm_edp_backlight_supported(edp_dpcd)) { 3847 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); 3848 return 0; 3849 } 3850 3851 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); 3852 if (!bl) 3853 return -ENOMEM; 3854 3855 bl->aux = aux; 3856 3857 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, 3858 ¤t_level, ¤t_mode); 3859 if (ret < 0) 3860 return ret; 3861 3862 props.type = BACKLIGHT_RAW; 3863 props.brightness = current_level; 3864 props.max_brightness = bl->info.max; 3865 3866 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", 3867 panel->dev, bl, 3868 &dp_aux_bl_ops, &props); 3869 if (IS_ERR(bl->base)) 3870 return PTR_ERR(bl->base); 3871 3872 backlight_disable(bl->base); 3873 3874 panel->backlight = bl->base; 3875 3876 return 0; 3877 } 3878 EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 3879 3880 #endif 3881