1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/backlight.h> 24 #include <linux/delay.h> 25 #include <linux/errno.h> 26 #include <linux/i2c.h> 27 #include <linux/init.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/sched.h> 31 #include <linux/seq_file.h> 32 #include <linux/string_helpers.h> 33 34 #include <drm/display/drm_dp_helper.h> 35 #include <drm/display/drm_dp_mst_helper.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_print.h> 38 #include <drm/drm_vblank.h> 39 #include <drm/drm_panel.h> 40 41 #include "drm_dp_helper_internal.h" 42 43 struct dp_aux_backlight { 44 struct backlight_device *base; 45 struct drm_dp_aux *aux; 46 struct drm_edp_backlight_info info; 47 bool enabled; 48 }; 49 50 /** 51 * DOC: dp helpers 52 * 53 * These functions contain some common logic and helpers at various abstraction 54 * levels to deal with Display Port sink devices and related things like DP aux 55 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 56 * blocks, ... 57 */ 58 59 /* Helpers for DP link training */ 60 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 61 { 62 return link_status[r - DP_LANE0_1_STATUS]; 63 } 64 65 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 66 int lane) 67 { 68 int i = DP_LANE0_1_STATUS + (lane >> 1); 69 int s = (lane & 1) * 4; 70 u8 l = dp_link_status(link_status, i); 71 72 return (l >> s) & 0xf; 73 } 74 75 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 76 int lane_count) 77 { 78 u8 lane_align; 79 u8 lane_status; 80 int lane; 81 82 lane_align = dp_link_status(link_status, 83 DP_LANE_ALIGN_STATUS_UPDATED); 84 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 85 return false; 86 for (lane = 0; lane < lane_count; lane++) { 87 lane_status = dp_get_lane_status(link_status, lane); 88 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 89 return false; 90 } 91 return true; 92 } 93 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 94 95 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 96 int lane_count) 97 { 98 int lane; 99 u8 lane_status; 100 101 for (lane = 0; lane < lane_count; lane++) { 102 lane_status = dp_get_lane_status(link_status, lane); 103 if ((lane_status & DP_LANE_CR_DONE) == 0) 104 return false; 105 } 106 return true; 107 } 108 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 109 110 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 111 int lane) 112 { 113 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 114 int s = ((lane & 1) ? 115 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 116 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 117 u8 l = dp_link_status(link_status, i); 118 119 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 120 } 121 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 122 123 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 124 int lane) 125 { 126 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 127 int s = ((lane & 1) ? 128 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 129 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 130 u8 l = dp_link_status(link_status, i); 131 132 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 133 } 134 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 135 136 /* DP 2.0 128b/132b */ 137 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 138 int lane) 139 { 140 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 141 int s = ((lane & 1) ? 142 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : 143 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); 144 u8 l = dp_link_status(link_status, i); 145 146 return (l >> s) & 0xf; 147 } 148 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); 149 150 /* DP 2.0 errata for 128b/132b */ 151 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 152 int lane_count) 153 { 154 u8 lane_align, lane_status; 155 int lane; 156 157 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 158 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 159 return false; 160 161 for (lane = 0; lane < lane_count; lane++) { 162 lane_status = dp_get_lane_status(link_status, lane); 163 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE)) 164 return false; 165 } 166 return true; 167 } 168 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done); 169 170 /* DP 2.0 errata for 128b/132b */ 171 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 172 int lane_count) 173 { 174 u8 lane_status; 175 int lane; 176 177 for (lane = 0; lane < lane_count; lane++) { 178 lane_status = dp_get_lane_status(link_status, lane); 179 if (!(lane_status & DP_LANE_SYMBOL_LOCKED)) 180 return false; 181 } 182 return true; 183 } 184 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked); 185 186 /* DP 2.0 errata for 128b/132b */ 187 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 188 { 189 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 190 191 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE; 192 } 193 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done); 194 195 /* DP 2.0 errata for 128b/132b */ 196 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 197 { 198 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 199 200 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE; 201 } 202 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done); 203 204 /* DP 2.0 errata for 128b/132b */ 205 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) 206 { 207 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 208 209 return status & DP_128B132B_LT_FAILED; 210 } 211 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed); 212 213 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 214 { 215 if (rd_interval > 4) 216 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 217 aux->name, rd_interval); 218 219 if (rd_interval == 0) 220 return 100; 221 222 return rd_interval * 4 * USEC_PER_MSEC; 223 } 224 225 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 226 { 227 if (rd_interval > 4) 228 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 229 aux->name, rd_interval); 230 231 if (rd_interval == 0) 232 return 400; 233 234 return rd_interval * 4 * USEC_PER_MSEC; 235 } 236 237 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 238 { 239 switch (rd_interval) { 240 default: 241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", 242 aux->name, rd_interval); 243 fallthrough; 244 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US: 245 return 400; 246 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS: 247 return 4000; 248 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS: 249 return 8000; 250 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS: 251 return 12000; 252 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS: 253 return 16000; 254 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS: 255 return 32000; 256 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS: 257 return 64000; 258 } 259 } 260 261 /* 262 * The link training delays are different for: 263 * 264 * - Clock recovery vs. channel equalization 265 * - DPRX vs. LTTPR 266 * - 128b/132b vs. 8b/10b 267 * - DPCD rev 1.3 vs. later 268 * 269 * Get the correct delay in us, reading DPCD if necessary. 270 */ 271 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 272 enum drm_dp_phy dp_phy, bool uhbr, bool cr) 273 { 274 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); 275 unsigned int offset; 276 u8 rd_interval, mask; 277 278 if (dp_phy == DP_PHY_DPRX) { 279 if (uhbr) { 280 if (cr) 281 return 100; 282 283 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL; 284 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 285 parse = __128b132b_channel_eq_delay_us; 286 } else { 287 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 288 return 100; 289 290 offset = DP_TRAINING_AUX_RD_INTERVAL; 291 mask = DP_TRAINING_AUX_RD_MASK; 292 if (cr) 293 parse = __8b10b_clock_recovery_delay_us; 294 else 295 parse = __8b10b_channel_eq_delay_us; 296 } 297 } else { 298 if (uhbr) { 299 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 300 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 301 parse = __128b132b_channel_eq_delay_us; 302 } else { 303 if (cr) 304 return 100; 305 306 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 307 mask = DP_TRAINING_AUX_RD_MASK; 308 parse = __8b10b_channel_eq_delay_us; 309 } 310 } 311 312 if (offset < DP_RECEIVER_CAP_SIZE) { 313 rd_interval = dpcd[offset]; 314 } else { 315 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { 316 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", 317 aux->name); 318 /* arbitrary default delay */ 319 return 400; 320 } 321 } 322 323 return parse(aux, rd_interval & mask); 324 } 325 326 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 327 enum drm_dp_phy dp_phy, bool uhbr) 328 { 329 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 330 } 331 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay); 332 333 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 334 enum drm_dp_phy dp_phy, bool uhbr) 335 { 336 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 337 } 338 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); 339 340 /* Per DP 2.0 Errata */ 341 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) 342 { 343 int unit; 344 u8 val; 345 346 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { 347 drm_err(aux->drm_dev, "%s: failed rd interval read\n", 348 aux->name); 349 /* default to max */ 350 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 351 } 352 353 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; 354 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 355 356 return (val + 1) * unit * 1000; 357 } 358 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); 359 360 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 361 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 362 { 363 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 364 DP_TRAINING_AUX_RD_MASK; 365 int delay_us; 366 367 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 368 delay_us = 100; 369 else 370 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); 371 372 usleep_range(delay_us, delay_us * 2); 373 } 374 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 375 376 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 377 u8 rd_interval) 378 { 379 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); 380 381 usleep_range(delay_us, delay_us * 2); 382 } 383 384 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 385 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 386 { 387 __drm_dp_link_train_channel_eq_delay(aux, 388 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 389 DP_TRAINING_AUX_RD_MASK); 390 } 391 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 392 393 void drm_dp_lttpr_link_train_clock_recovery_delay(void) 394 { 395 usleep_range(100, 200); 396 } 397 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); 398 399 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) 400 { 401 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; 402 } 403 404 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 405 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) 406 { 407 u8 interval = dp_lttpr_phy_cap(phy_cap, 408 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & 409 DP_TRAINING_AUX_RD_MASK; 410 411 __drm_dp_link_train_channel_eq_delay(aux, interval); 412 } 413 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 414 415 u8 drm_dp_link_rate_to_bw_code(int link_rate) 416 { 417 switch (link_rate) { 418 case 1000000: 419 return DP_LINK_BW_10; 420 case 1350000: 421 return DP_LINK_BW_13_5; 422 case 2000000: 423 return DP_LINK_BW_20; 424 default: 425 /* Spec says link_bw = link_rate / 0.27Gbps */ 426 return link_rate / 27000; 427 } 428 } 429 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 430 431 int drm_dp_bw_code_to_link_rate(u8 link_bw) 432 { 433 switch (link_bw) { 434 case DP_LINK_BW_10: 435 return 1000000; 436 case DP_LINK_BW_13_5: 437 return 1350000; 438 case DP_LINK_BW_20: 439 return 2000000; 440 default: 441 /* Spec says link_rate = link_bw * 0.27Gbps */ 442 return link_bw * 27000; 443 } 444 } 445 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 446 447 #define AUX_RETRY_INTERVAL 500 /* us */ 448 449 static inline void 450 drm_dp_dump_access(const struct drm_dp_aux *aux, 451 u8 request, uint offset, void *buffer, int ret) 452 { 453 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 454 455 if (ret > 0) 456 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 457 aux->name, offset, arrow, ret, min(ret, 20), buffer); 458 else 459 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", 460 aux->name, offset, arrow, ret); 461 } 462 463 /** 464 * DOC: dp helpers 465 * 466 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 467 * independent access to AUX functionality. Drivers can take advantage of 468 * this by filling in the fields of the drm_dp_aux structure. 469 * 470 * Transactions are described using a hardware-independent drm_dp_aux_msg 471 * structure, which is passed into a driver's .transfer() implementation. 472 * Both native and I2C-over-AUX transactions are supported. 473 */ 474 475 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 476 unsigned int offset, void *buffer, size_t size) 477 { 478 struct drm_dp_aux_msg msg; 479 unsigned int retry, native_reply; 480 int err = 0, ret = 0; 481 482 memset(&msg, 0, sizeof(msg)); 483 msg.address = offset; 484 msg.request = request; 485 msg.buffer = buffer; 486 msg.size = size; 487 488 mutex_lock(&aux->hw_mutex); 489 490 /* 491 * The specification doesn't give any recommendation on how often to 492 * retry native transactions. We used to retry 7 times like for 493 * aux i2c transactions but real world devices this wasn't 494 * sufficient, bump to 32 which makes Dell 4k monitors happier. 495 */ 496 for (retry = 0; retry < 32; retry++) { 497 if (ret != 0 && ret != -ETIMEDOUT) { 498 usleep_range(AUX_RETRY_INTERVAL, 499 AUX_RETRY_INTERVAL + 100); 500 } 501 502 ret = aux->transfer(aux, &msg); 503 if (ret >= 0) { 504 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 505 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 506 if (ret == size) 507 goto unlock; 508 509 ret = -EPROTO; 510 } else 511 ret = -EIO; 512 } 513 514 /* 515 * We want the error we return to be the error we received on 516 * the first transaction, since we may get a different error the 517 * next time we retry 518 */ 519 if (!err) 520 err = ret; 521 } 522 523 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", 524 aux->name, err); 525 ret = err; 526 527 unlock: 528 mutex_unlock(&aux->hw_mutex); 529 return ret; 530 } 531 532 /** 533 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access 534 * @aux: DisplayPort AUX channel (SST) 535 * @offset: address of the register to probe 536 * 537 * Probe the provided DPCD address by reading 1 byte from it. The function can 538 * be used to trigger some side-effect the read access has, like waking up the 539 * sink, without the need for the read-out value. 540 * 541 * Returns 0 if the read access suceeded, or a negative error code on failure. 542 */ 543 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) 544 { 545 u8 buffer; 546 int ret; 547 548 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); 549 WARN_ON(ret == 0); 550 551 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); 552 553 return ret < 0 ? ret : 0; 554 } 555 EXPORT_SYMBOL(drm_dp_dpcd_probe); 556 557 /** 558 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 559 * @aux: DisplayPort AUX channel (SST or MST) 560 * @offset: address of the (first) register to read 561 * @buffer: buffer to store the register values 562 * @size: number of bytes in @buffer 563 * 564 * Returns the number of bytes transferred on success, or a negative error 565 * code on failure. -EIO is returned if the request was NAKed by the sink or 566 * if the retry count was exceeded. If not all bytes were transferred, this 567 * function returns -EPROTO. Errors from the underlying AUX channel transfer 568 * function, with the exception of -EBUSY (which causes the transaction to 569 * be retried), are propagated to the caller. 570 */ 571 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 572 void *buffer, size_t size) 573 { 574 int ret; 575 576 /* 577 * HP ZR24w corrupts the first DPCD access after entering power save 578 * mode. Eg. on a read, the entire buffer will be filled with the same 579 * byte. Do a throw away read to avoid corrupting anything we care 580 * about. Afterwards things will work correctly until the monitor 581 * gets woken up and subsequently re-enters power save mode. 582 * 583 * The user pressing any button on the monitor is enough to wake it 584 * up, so there is no particularly good place to do the workaround. 585 * We just have to do it before any DPCD access and hope that the 586 * monitor doesn't power down exactly after the throw away read. 587 */ 588 if (!aux->is_remote) { 589 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); 590 if (ret < 0) 591 return ret; 592 } 593 594 if (aux->is_remote) 595 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 596 else 597 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 598 buffer, size); 599 600 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 601 return ret; 602 } 603 EXPORT_SYMBOL(drm_dp_dpcd_read); 604 605 /** 606 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 607 * @aux: DisplayPort AUX channel (SST or MST) 608 * @offset: address of the (first) register to write 609 * @buffer: buffer containing the values to write 610 * @size: number of bytes in @buffer 611 * 612 * Returns the number of bytes transferred on success, or a negative error 613 * code on failure. -EIO is returned if the request was NAKed by the sink or 614 * if the retry count was exceeded. If not all bytes were transferred, this 615 * function returns -EPROTO. Errors from the underlying AUX channel transfer 616 * function, with the exception of -EBUSY (which causes the transaction to 617 * be retried), are propagated to the caller. 618 */ 619 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 620 void *buffer, size_t size) 621 { 622 int ret; 623 624 if (aux->is_remote) 625 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 626 else 627 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 628 buffer, size); 629 630 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 631 return ret; 632 } 633 EXPORT_SYMBOL(drm_dp_dpcd_write); 634 635 /** 636 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 637 * @aux: DisplayPort AUX channel 638 * @status: buffer to store the link status in (must be at least 6 bytes) 639 * 640 * Returns the number of bytes transferred on success or a negative error 641 * code on failure. 642 */ 643 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 644 u8 status[DP_LINK_STATUS_SIZE]) 645 { 646 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 647 DP_LINK_STATUS_SIZE); 648 } 649 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 650 651 /** 652 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY 653 * @aux: DisplayPort AUX channel 654 * @dp_phy: the DP PHY to get the link status for 655 * @link_status: buffer to return the status in 656 * 657 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The 658 * layout of the returned @link_status matches the DPCD register layout of the 659 * DPRX PHY link status. 660 * 661 * Returns 0 if the information was read successfully or a negative error code 662 * on failure. 663 */ 664 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 665 enum drm_dp_phy dp_phy, 666 u8 link_status[DP_LINK_STATUS_SIZE]) 667 { 668 int ret; 669 670 if (dp_phy == DP_PHY_DPRX) { 671 ret = drm_dp_dpcd_read(aux, 672 DP_LANE0_1_STATUS, 673 link_status, 674 DP_LINK_STATUS_SIZE); 675 676 if (ret < 0) 677 return ret; 678 679 WARN_ON(ret != DP_LINK_STATUS_SIZE); 680 681 return 0; 682 } 683 684 ret = drm_dp_dpcd_read(aux, 685 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), 686 link_status, 687 DP_LINK_STATUS_SIZE - 1); 688 689 if (ret < 0) 690 return ret; 691 692 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); 693 694 /* Convert the LTTPR to the sink PHY link status layout */ 695 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], 696 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], 697 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); 698 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; 699 700 return 0; 701 } 702 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 703 704 static bool is_edid_digital_input_dp(const struct edid *edid) 705 { 706 return edid && edid->revision >= 4 && 707 edid->input & DRM_EDID_INPUT_DIGITAL && 708 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 709 } 710 711 /** 712 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 713 * @dpcd: DisplayPort configuration data 714 * @port_cap: port capabilities 715 * @type: port type to be checked. Can be: 716 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 717 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 718 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 719 * 720 * Caveat: Only works with DPCD 1.1+ port caps. 721 * 722 * Returns: whether the downstream facing port matches the type. 723 */ 724 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 725 const u8 port_cap[4], u8 type) 726 { 727 return drm_dp_is_branch(dpcd) && 728 dpcd[DP_DPCD_REV] >= 0x11 && 729 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 730 } 731 EXPORT_SYMBOL(drm_dp_downstream_is_type); 732 733 /** 734 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 735 * @dpcd: DisplayPort configuration data 736 * @port_cap: port capabilities 737 * @edid: EDID 738 * 739 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 740 */ 741 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 742 const u8 port_cap[4], 743 const struct edid *edid) 744 { 745 if (dpcd[DP_DPCD_REV] < 0x11) { 746 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 747 case DP_DWN_STRM_PORT_TYPE_TMDS: 748 return true; 749 default: 750 return false; 751 } 752 } 753 754 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 755 case DP_DS_PORT_TYPE_DP_DUALMODE: 756 if (is_edid_digital_input_dp(edid)) 757 return false; 758 fallthrough; 759 case DP_DS_PORT_TYPE_DVI: 760 case DP_DS_PORT_TYPE_HDMI: 761 return true; 762 default: 763 return false; 764 } 765 } 766 EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 767 768 /** 769 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 770 * @aux: DisplayPort AUX channel 771 * @real_edid_checksum: real edid checksum for the last block 772 * 773 * Returns: 774 * True on success 775 */ 776 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 777 u8 real_edid_checksum) 778 { 779 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 780 781 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 782 &auto_test_req, 1) < 1) { 783 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 784 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 785 return false; 786 } 787 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 788 789 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 790 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 791 aux->name, DP_TEST_REQUEST); 792 return false; 793 } 794 link_edid_read &= DP_TEST_LINK_EDID_READ; 795 796 if (!auto_test_req || !link_edid_read) { 797 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", 798 aux->name); 799 return false; 800 } 801 802 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 803 &auto_test_req, 1) < 1) { 804 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 805 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 806 return false; 807 } 808 809 /* send back checksum for the last edid extension block data */ 810 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 811 &real_edid_checksum, 1) < 1) { 812 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 813 aux->name, DP_TEST_EDID_CHECKSUM); 814 return false; 815 } 816 817 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 818 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 819 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 820 aux->name, DP_TEST_RESPONSE); 821 return false; 822 } 823 824 return true; 825 } 826 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 827 828 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 829 { 830 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 831 832 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 833 port_count = 4; 834 835 return port_count; 836 } 837 838 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 839 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 840 { 841 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; 842 int ret; 843 844 /* 845 * Prior to DP1.3 the bit represented by 846 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 847 * If it is set DP_DPCD_REV at 0000h could be at a value less than 848 * the true capability of the panel. The only way to check is to 849 * then compare 0000h and 2200h. 850 */ 851 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 852 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 853 return 0; 854 855 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 856 sizeof(dpcd_ext)); 857 if (ret < 0) 858 return ret; 859 if (ret != sizeof(dpcd_ext)) 860 return -EIO; 861 862 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 863 drm_dbg_kms(aux->drm_dev, 864 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 865 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 866 return 0; 867 } 868 869 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 870 return 0; 871 872 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 873 874 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 875 876 return 0; 877 } 878 879 /** 880 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 881 * available 882 * @aux: DisplayPort AUX channel 883 * @dpcd: Buffer to store the resulting DPCD in 884 * 885 * Attempts to read the base DPCD caps for @aux. Additionally, this function 886 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 887 * present. 888 * 889 * Returns: %0 if the DPCD was read successfully, negative error code 890 * otherwise. 891 */ 892 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 893 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 894 { 895 int ret; 896 897 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 898 if (ret < 0) 899 return ret; 900 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 901 return -EIO; 902 903 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 904 if (ret < 0) 905 return ret; 906 907 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 908 909 return ret; 910 } 911 EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 912 913 /** 914 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 915 * @aux: DisplayPort AUX channel 916 * @dpcd: A cached copy of the port's DPCD 917 * @downstream_ports: buffer to store the downstream port info in 918 * 919 * See also: 920 * drm_dp_downstream_max_clock() 921 * drm_dp_downstream_max_bpc() 922 * 923 * Returns: 0 if either the downstream port info was read successfully or 924 * there was no downstream info to read, or a negative error code otherwise. 925 */ 926 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 927 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 928 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 929 { 930 int ret; 931 u8 len; 932 933 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 934 935 /* No downstream info to read */ 936 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) 937 return 0; 938 939 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 940 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 941 * some branches do it we need to handle it regardless. 942 */ 943 len = drm_dp_downstream_port_count(dpcd); 944 if (!len) 945 return 0; 946 947 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 948 len *= 4; 949 950 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 951 if (ret < 0) 952 return ret; 953 if (ret != len) 954 return -EIO; 955 956 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); 957 958 return 0; 959 } 960 EXPORT_SYMBOL(drm_dp_read_downstream_info); 961 962 /** 963 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 964 * @dpcd: DisplayPort configuration data 965 * @port_cap: port capabilities 966 * 967 * Returns: Downstream facing port max dot clock in kHz on success, 968 * or 0 if max clock not defined 969 */ 970 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 971 const u8 port_cap[4]) 972 { 973 if (!drm_dp_is_branch(dpcd)) 974 return 0; 975 976 if (dpcd[DP_DPCD_REV] < 0x11) 977 return 0; 978 979 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 980 case DP_DS_PORT_TYPE_VGA: 981 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 982 return 0; 983 return port_cap[1] * 8000; 984 default: 985 return 0; 986 } 987 } 988 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 989 990 /** 991 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 992 * @dpcd: DisplayPort configuration data 993 * @port_cap: port capabilities 994 * @edid: EDID 995 * 996 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 997 * or 0 if max TMDS clock not defined 998 */ 999 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1000 const u8 port_cap[4], 1001 const struct edid *edid) 1002 { 1003 if (!drm_dp_is_branch(dpcd)) 1004 return 0; 1005 1006 if (dpcd[DP_DPCD_REV] < 0x11) { 1007 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1008 case DP_DWN_STRM_PORT_TYPE_TMDS: 1009 return 165000; 1010 default: 1011 return 0; 1012 } 1013 } 1014 1015 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1016 case DP_DS_PORT_TYPE_DP_DUALMODE: 1017 if (is_edid_digital_input_dp(edid)) 1018 return 0; 1019 /* 1020 * It's left up to the driver to check the 1021 * DP dual mode adapter's max TMDS clock. 1022 * 1023 * Unfortunately it looks like branch devices 1024 * may not fordward that the DP dual mode i2c 1025 * access so we just usually get i2c nak :( 1026 */ 1027 fallthrough; 1028 case DP_DS_PORT_TYPE_HDMI: 1029 /* 1030 * We should perhaps assume 165 MHz when detailed cap 1031 * info is not available. But looks like many typical 1032 * branch devices fall into that category and so we'd 1033 * probably end up with users complaining that they can't 1034 * get high resolution modes with their favorite dongle. 1035 * 1036 * So let's limit to 300 MHz instead since DPCD 1.4 1037 * HDMI 2.0 DFPs are required to have the detailed cap 1038 * info. So it's more likely we're dealing with a HDMI 1.4 1039 * compatible* device here. 1040 */ 1041 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1042 return 300000; 1043 return port_cap[1] * 2500; 1044 case DP_DS_PORT_TYPE_DVI: 1045 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1046 return 165000; 1047 /* FIXME what to do about DVI dual link? */ 1048 return port_cap[1] * 2500; 1049 default: 1050 return 0; 1051 } 1052 } 1053 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 1054 1055 /** 1056 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1057 * @dpcd: DisplayPort configuration data 1058 * @port_cap: port capabilities 1059 * @edid: EDID 1060 * 1061 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1062 * or 0 if max TMDS clock not defined 1063 */ 1064 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1065 const u8 port_cap[4], 1066 const struct edid *edid) 1067 { 1068 if (!drm_dp_is_branch(dpcd)) 1069 return 0; 1070 1071 if (dpcd[DP_DPCD_REV] < 0x11) { 1072 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1073 case DP_DWN_STRM_PORT_TYPE_TMDS: 1074 return 25000; 1075 default: 1076 return 0; 1077 } 1078 } 1079 1080 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1081 case DP_DS_PORT_TYPE_DP_DUALMODE: 1082 if (is_edid_digital_input_dp(edid)) 1083 return 0; 1084 fallthrough; 1085 case DP_DS_PORT_TYPE_DVI: 1086 case DP_DS_PORT_TYPE_HDMI: 1087 /* 1088 * Unclear whether the protocol converter could 1089 * utilize pixel replication. Assume it won't. 1090 */ 1091 return 25000; 1092 default: 1093 return 0; 1094 } 1095 } 1096 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 1097 1098 /** 1099 * drm_dp_downstream_max_bpc() - extract downstream facing port max 1100 * bits per component 1101 * @dpcd: DisplayPort configuration data 1102 * @port_cap: downstream facing port capabilities 1103 * @edid: EDID 1104 * 1105 * Returns: Max bpc on success or 0 if max bpc not defined 1106 */ 1107 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1108 const u8 port_cap[4], 1109 const struct edid *edid) 1110 { 1111 if (!drm_dp_is_branch(dpcd)) 1112 return 0; 1113 1114 if (dpcd[DP_DPCD_REV] < 0x11) { 1115 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1116 case DP_DWN_STRM_PORT_TYPE_DP: 1117 return 0; 1118 default: 1119 return 8; 1120 } 1121 } 1122 1123 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1124 case DP_DS_PORT_TYPE_DP: 1125 return 0; 1126 case DP_DS_PORT_TYPE_DP_DUALMODE: 1127 if (is_edid_digital_input_dp(edid)) 1128 return 0; 1129 fallthrough; 1130 case DP_DS_PORT_TYPE_HDMI: 1131 case DP_DS_PORT_TYPE_DVI: 1132 case DP_DS_PORT_TYPE_VGA: 1133 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1134 return 8; 1135 1136 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 1137 case DP_DS_8BPC: 1138 return 8; 1139 case DP_DS_10BPC: 1140 return 10; 1141 case DP_DS_12BPC: 1142 return 12; 1143 case DP_DS_16BPC: 1144 return 16; 1145 default: 1146 return 8; 1147 } 1148 break; 1149 default: 1150 return 8; 1151 } 1152 } 1153 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 1154 1155 /** 1156 * drm_dp_downstream_420_passthrough() - determine downstream facing port 1157 * YCbCr 4:2:0 pass-through capability 1158 * @dpcd: DisplayPort configuration data 1159 * @port_cap: downstream facing port capabilities 1160 * 1161 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 1162 */ 1163 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1164 const u8 port_cap[4]) 1165 { 1166 if (!drm_dp_is_branch(dpcd)) 1167 return false; 1168 1169 if (dpcd[DP_DPCD_REV] < 0x13) 1170 return false; 1171 1172 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1173 case DP_DS_PORT_TYPE_DP: 1174 return true; 1175 case DP_DS_PORT_TYPE_HDMI: 1176 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1177 return false; 1178 1179 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 1180 default: 1181 return false; 1182 } 1183 } 1184 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 1185 1186 /** 1187 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 1188 * YCbCr 4:4:4->4:2:0 conversion capability 1189 * @dpcd: DisplayPort configuration data 1190 * @port_cap: downstream facing port capabilities 1191 * 1192 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 1193 */ 1194 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1195 const u8 port_cap[4]) 1196 { 1197 if (!drm_dp_is_branch(dpcd)) 1198 return false; 1199 1200 if (dpcd[DP_DPCD_REV] < 0x13) 1201 return false; 1202 1203 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1204 case DP_DS_PORT_TYPE_HDMI: 1205 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1206 return false; 1207 1208 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 1209 default: 1210 return false; 1211 } 1212 } 1213 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 1214 1215 /** 1216 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port 1217 * RGB->YCbCr conversion capability 1218 * @dpcd: DisplayPort configuration data 1219 * @port_cap: downstream facing port capabilities 1220 * @color_spc: Colorspace for which conversion cap is sought 1221 * 1222 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given 1223 * colorspace. 1224 */ 1225 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1226 const u8 port_cap[4], 1227 u8 color_spc) 1228 { 1229 if (!drm_dp_is_branch(dpcd)) 1230 return false; 1231 1232 if (dpcd[DP_DPCD_REV] < 0x13) 1233 return false; 1234 1235 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1236 case DP_DS_PORT_TYPE_HDMI: 1237 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1238 return false; 1239 1240 return port_cap[3] & color_spc; 1241 default: 1242 return false; 1243 } 1244 } 1245 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion); 1246 1247 /** 1248 * drm_dp_downstream_mode() - return a mode for downstream facing port 1249 * @dev: DRM device 1250 * @dpcd: DisplayPort configuration data 1251 * @port_cap: port capabilities 1252 * 1253 * Provides a suitable mode for downstream facing ports without EDID. 1254 * 1255 * Returns: A new drm_display_mode on success or NULL on failure 1256 */ 1257 struct drm_display_mode * 1258 drm_dp_downstream_mode(struct drm_device *dev, 1259 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1260 const u8 port_cap[4]) 1261 1262 { 1263 u8 vic; 1264 1265 if (!drm_dp_is_branch(dpcd)) 1266 return NULL; 1267 1268 if (dpcd[DP_DPCD_REV] < 0x11) 1269 return NULL; 1270 1271 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1272 case DP_DS_PORT_TYPE_NON_EDID: 1273 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 1274 case DP_DS_NON_EDID_720x480i_60: 1275 vic = 6; 1276 break; 1277 case DP_DS_NON_EDID_720x480i_50: 1278 vic = 21; 1279 break; 1280 case DP_DS_NON_EDID_1920x1080i_60: 1281 vic = 5; 1282 break; 1283 case DP_DS_NON_EDID_1920x1080i_50: 1284 vic = 20; 1285 break; 1286 case DP_DS_NON_EDID_1280x720_60: 1287 vic = 4; 1288 break; 1289 case DP_DS_NON_EDID_1280x720_50: 1290 vic = 19; 1291 break; 1292 default: 1293 return NULL; 1294 } 1295 return drm_display_mode_from_cea_vic(dev, vic); 1296 default: 1297 return NULL; 1298 } 1299 } 1300 EXPORT_SYMBOL(drm_dp_downstream_mode); 1301 1302 /** 1303 * drm_dp_downstream_id() - identify branch device 1304 * @aux: DisplayPort AUX channel 1305 * @id: DisplayPort branch device id 1306 * 1307 * Returns branch device id on success or NULL on failure 1308 */ 1309 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 1310 { 1311 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 1312 } 1313 EXPORT_SYMBOL(drm_dp_downstream_id); 1314 1315 /** 1316 * drm_dp_downstream_debug() - debug DP branch devices 1317 * @m: pointer for debugfs file 1318 * @dpcd: DisplayPort configuration data 1319 * @port_cap: port capabilities 1320 * @edid: EDID 1321 * @aux: DisplayPort AUX channel 1322 * 1323 */ 1324 void drm_dp_downstream_debug(struct seq_file *m, 1325 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1326 const u8 port_cap[4], 1327 const struct edid *edid, 1328 struct drm_dp_aux *aux) 1329 { 1330 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1331 DP_DETAILED_CAP_INFO_AVAILABLE; 1332 int clk; 1333 int bpc; 1334 char id[7]; 1335 int len; 1336 uint8_t rev[2]; 1337 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1338 bool branch_device = drm_dp_is_branch(dpcd); 1339 1340 seq_printf(m, "\tDP branch device present: %s\n", 1341 str_yes_no(branch_device)); 1342 1343 if (!branch_device) 1344 return; 1345 1346 switch (type) { 1347 case DP_DS_PORT_TYPE_DP: 1348 seq_puts(m, "\t\tType: DisplayPort\n"); 1349 break; 1350 case DP_DS_PORT_TYPE_VGA: 1351 seq_puts(m, "\t\tType: VGA\n"); 1352 break; 1353 case DP_DS_PORT_TYPE_DVI: 1354 seq_puts(m, "\t\tType: DVI\n"); 1355 break; 1356 case DP_DS_PORT_TYPE_HDMI: 1357 seq_puts(m, "\t\tType: HDMI\n"); 1358 break; 1359 case DP_DS_PORT_TYPE_NON_EDID: 1360 seq_puts(m, "\t\tType: others without EDID support\n"); 1361 break; 1362 case DP_DS_PORT_TYPE_DP_DUALMODE: 1363 seq_puts(m, "\t\tType: DP++\n"); 1364 break; 1365 case DP_DS_PORT_TYPE_WIRELESS: 1366 seq_puts(m, "\t\tType: Wireless\n"); 1367 break; 1368 default: 1369 seq_puts(m, "\t\tType: N/A\n"); 1370 } 1371 1372 memset(id, 0, sizeof(id)); 1373 drm_dp_downstream_id(aux, id); 1374 seq_printf(m, "\t\tID: %s\n", id); 1375 1376 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1377 if (len > 0) 1378 seq_printf(m, "\t\tHW: %d.%d\n", 1379 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1380 1381 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1382 if (len > 0) 1383 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1384 1385 if (detailed_cap_info) { 1386 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1387 if (clk > 0) 1388 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1389 1390 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); 1391 if (clk > 0) 1392 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1393 1394 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); 1395 if (clk > 0) 1396 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1397 1398 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); 1399 1400 if (bpc > 0) 1401 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1402 } 1403 } 1404 EXPORT_SYMBOL(drm_dp_downstream_debug); 1405 1406 /** 1407 * drm_dp_subconnector_type() - get DP branch device type 1408 * @dpcd: DisplayPort configuration data 1409 * @port_cap: port capabilities 1410 */ 1411 enum drm_mode_subconnector 1412 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1413 const u8 port_cap[4]) 1414 { 1415 int type; 1416 if (!drm_dp_is_branch(dpcd)) 1417 return DRM_MODE_SUBCONNECTOR_Native; 1418 /* DP 1.0 approach */ 1419 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1420 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1421 DP_DWN_STRM_PORT_TYPE_MASK; 1422 1423 switch (type) { 1424 case DP_DWN_STRM_PORT_TYPE_TMDS: 1425 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1426 return DRM_MODE_SUBCONNECTOR_DVID; 1427 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1428 /* Can be VGA or DVI-A, VGA is more popular */ 1429 return DRM_MODE_SUBCONNECTOR_VGA; 1430 case DP_DWN_STRM_PORT_TYPE_DP: 1431 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1432 case DP_DWN_STRM_PORT_TYPE_OTHER: 1433 default: 1434 return DRM_MODE_SUBCONNECTOR_Unknown; 1435 } 1436 } 1437 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1438 1439 switch (type) { 1440 case DP_DS_PORT_TYPE_DP: 1441 case DP_DS_PORT_TYPE_DP_DUALMODE: 1442 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1443 case DP_DS_PORT_TYPE_VGA: 1444 return DRM_MODE_SUBCONNECTOR_VGA; 1445 case DP_DS_PORT_TYPE_DVI: 1446 return DRM_MODE_SUBCONNECTOR_DVID; 1447 case DP_DS_PORT_TYPE_HDMI: 1448 return DRM_MODE_SUBCONNECTOR_HDMIA; 1449 case DP_DS_PORT_TYPE_WIRELESS: 1450 return DRM_MODE_SUBCONNECTOR_Wireless; 1451 case DP_DS_PORT_TYPE_NON_EDID: 1452 default: 1453 return DRM_MODE_SUBCONNECTOR_Unknown; 1454 } 1455 } 1456 EXPORT_SYMBOL(drm_dp_subconnector_type); 1457 1458 /** 1459 * drm_dp_set_subconnector_property - set subconnector for DP connector 1460 * @connector: connector to set property on 1461 * @status: connector status 1462 * @dpcd: DisplayPort configuration data 1463 * @port_cap: port capabilities 1464 * 1465 * Called by a driver on every detect event. 1466 */ 1467 void drm_dp_set_subconnector_property(struct drm_connector *connector, 1468 enum drm_connector_status status, 1469 const u8 *dpcd, 1470 const u8 port_cap[4]) 1471 { 1472 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1473 1474 if (status == connector_status_connected) 1475 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1476 drm_object_property_set_value(&connector->base, 1477 connector->dev->mode_config.dp_subconnector_property, 1478 subconnector); 1479 } 1480 EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1481 1482 /** 1483 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1484 * count 1485 * @connector: The DRM connector to check 1486 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1487 * @desc: A cached copy of the connector's DP descriptor 1488 * 1489 * See also: drm_dp_read_sink_count() 1490 * 1491 * Returns: %True if the (e)DP connector has a valid sink count that should 1492 * be probed, %false otherwise. 1493 */ 1494 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1495 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1496 const struct drm_dp_desc *desc) 1497 { 1498 /* Some eDP panels don't set a valid value for the sink count */ 1499 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1500 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1501 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1502 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT); 1503 } 1504 EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1505 1506 /** 1507 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1508 * @aux: The DP AUX channel to use 1509 * 1510 * See also: drm_dp_read_sink_count_cap() 1511 * 1512 * Returns: The current sink count reported by @aux, or a negative error code 1513 * otherwise. 1514 */ 1515 int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1516 { 1517 u8 count; 1518 int ret; 1519 1520 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1521 if (ret < 0) 1522 return ret; 1523 if (ret != 1) 1524 return -EIO; 1525 1526 return DP_GET_SINK_COUNT(count); 1527 } 1528 EXPORT_SYMBOL(drm_dp_read_sink_count); 1529 1530 /* 1531 * I2C-over-AUX implementation 1532 */ 1533 1534 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1535 { 1536 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1537 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1538 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1539 I2C_FUNC_10BIT_ADDR; 1540 } 1541 1542 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1543 { 1544 /* 1545 * In case of i2c defer or short i2c ack reply to a write, 1546 * we need to switch to WRITE_STATUS_UPDATE to drain the 1547 * rest of the message 1548 */ 1549 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1550 msg->request &= DP_AUX_I2C_MOT; 1551 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1552 } 1553 } 1554 1555 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1556 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1557 #define AUX_STOP_LEN 4 1558 #define AUX_CMD_LEN 4 1559 #define AUX_ADDRESS_LEN 20 1560 #define AUX_REPLY_PAD_LEN 4 1561 #define AUX_LENGTH_LEN 8 1562 1563 /* 1564 * Calculate the duration of the AUX request/reply in usec. Gives the 1565 * "best" case estimate, ie. successful while as short as possible. 1566 */ 1567 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1568 { 1569 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1570 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1571 1572 if ((msg->request & DP_AUX_I2C_READ) == 0) 1573 len += msg->size * 8; 1574 1575 return len; 1576 } 1577 1578 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1579 { 1580 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1581 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1582 1583 /* 1584 * For read we expect what was asked. For writes there will 1585 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1586 */ 1587 if (msg->request & DP_AUX_I2C_READ) 1588 len += msg->size * 8; 1589 1590 return len; 1591 } 1592 1593 #define I2C_START_LEN 1 1594 #define I2C_STOP_LEN 1 1595 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1596 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1597 1598 /* 1599 * Calculate the length of the i2c transfer in usec, assuming 1600 * the i2c bus speed is as specified. Gives the the "worst" 1601 * case estimate, ie. successful while as long as possible. 1602 * Doesn't account the "MOT" bit, and instead assumes each 1603 * message includes a START, ADDRESS and STOP. Neither does it 1604 * account for additional random variables such as clock stretching. 1605 */ 1606 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1607 int i2c_speed_khz) 1608 { 1609 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1610 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1611 msg->size * I2C_DATA_LEN + 1612 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1613 } 1614 1615 /* 1616 * Determine how many retries should be attempted to successfully transfer 1617 * the specified message, based on the estimated durations of the 1618 * i2c and AUX transfers. 1619 */ 1620 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1621 int i2c_speed_khz) 1622 { 1623 int aux_time_us = drm_dp_aux_req_duration(msg) + 1624 drm_dp_aux_reply_duration(msg); 1625 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1626 1627 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1628 } 1629 1630 /* 1631 * FIXME currently assumes 10 kHz as some real world devices seem 1632 * to require it. We should query/set the speed via DPCD if supported. 1633 */ 1634 static int dp_aux_i2c_speed_khz __read_mostly = 10; 1635 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1636 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1637 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1638 1639 /* 1640 * Transfer a single I2C-over-AUX message and handle various error conditions, 1641 * retrying the transaction as appropriate. It is assumed that the 1642 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1643 * reply field. 1644 * 1645 * Returns bytes transferred on success, or a negative error code on failure. 1646 */ 1647 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1648 { 1649 unsigned int retry, defer_i2c; 1650 int ret; 1651 /* 1652 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1653 * is required to retry at least seven times upon receiving AUX_DEFER 1654 * before giving up the AUX transaction. 1655 * 1656 * We also try to account for the i2c bus speed. 1657 */ 1658 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1659 1660 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1661 ret = aux->transfer(aux, msg); 1662 if (ret < 0) { 1663 if (ret == -EBUSY) 1664 continue; 1665 1666 /* 1667 * While timeouts can be errors, they're usually normal 1668 * behavior (for instance, when a driver tries to 1669 * communicate with a non-existent DisplayPort device). 1670 * Avoid spamming the kernel log with timeout errors. 1671 */ 1672 if (ret == -ETIMEDOUT) 1673 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", 1674 aux->name); 1675 else 1676 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", 1677 aux->name, ret); 1678 return ret; 1679 } 1680 1681 1682 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1683 case DP_AUX_NATIVE_REPLY_ACK: 1684 /* 1685 * For I2C-over-AUX transactions this isn't enough, we 1686 * need to check for the I2C ACK reply. 1687 */ 1688 break; 1689 1690 case DP_AUX_NATIVE_REPLY_NACK: 1691 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", 1692 aux->name, ret, msg->size); 1693 return -EREMOTEIO; 1694 1695 case DP_AUX_NATIVE_REPLY_DEFER: 1696 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); 1697 /* 1698 * We could check for I2C bit rate capabilities and if 1699 * available adjust this interval. We could also be 1700 * more careful with DP-to-legacy adapters where a 1701 * long legacy cable may force very low I2C bit rates. 1702 * 1703 * For now just defer for long enough to hopefully be 1704 * safe for all use-cases. 1705 */ 1706 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1707 continue; 1708 1709 default: 1710 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", 1711 aux->name, msg->reply); 1712 return -EREMOTEIO; 1713 } 1714 1715 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1716 case DP_AUX_I2C_REPLY_ACK: 1717 /* 1718 * Both native ACK and I2C ACK replies received. We 1719 * can assume the transfer was successful. 1720 */ 1721 if (ret != msg->size) 1722 drm_dp_i2c_msg_write_status_update(msg); 1723 return ret; 1724 1725 case DP_AUX_I2C_REPLY_NACK: 1726 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", 1727 aux->name, ret, msg->size); 1728 aux->i2c_nack_count++; 1729 return -EREMOTEIO; 1730 1731 case DP_AUX_I2C_REPLY_DEFER: 1732 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); 1733 /* DP Compliance Test 4.2.2.5 Requirement: 1734 * Must have at least 7 retries for I2C defers on the 1735 * transaction to pass this test 1736 */ 1737 aux->i2c_defer_count++; 1738 if (defer_i2c < 7) 1739 defer_i2c++; 1740 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1741 drm_dp_i2c_msg_write_status_update(msg); 1742 1743 continue; 1744 1745 default: 1746 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", 1747 aux->name, msg->reply); 1748 return -EREMOTEIO; 1749 } 1750 } 1751 1752 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); 1753 return -EREMOTEIO; 1754 } 1755 1756 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 1757 const struct i2c_msg *i2c_msg) 1758 { 1759 msg->request = (i2c_msg->flags & I2C_M_RD) ? 1760 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 1761 if (!(i2c_msg->flags & I2C_M_STOP)) 1762 msg->request |= DP_AUX_I2C_MOT; 1763 } 1764 1765 /* 1766 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 1767 * 1768 * Returns an error code on failure, or a recommended transfer size on success. 1769 */ 1770 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 1771 { 1772 int err, ret = orig_msg->size; 1773 struct drm_dp_aux_msg msg = *orig_msg; 1774 1775 while (msg.size > 0) { 1776 err = drm_dp_i2c_do_msg(aux, &msg); 1777 if (err <= 0) 1778 return err == 0 ? -EPROTO : err; 1779 1780 if (err < msg.size && err < ret) { 1781 drm_dbg_kms(aux->drm_dev, 1782 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 1783 aux->name, msg.size, err); 1784 ret = err; 1785 } 1786 1787 msg.size -= err; 1788 msg.buffer += err; 1789 } 1790 1791 return ret; 1792 } 1793 1794 /* 1795 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 1796 * packets to be as large as possible. If not, the I2C transactions never 1797 * succeed. Hence the default is maximum. 1798 */ 1799 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 1800 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 1801 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 1802 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 1803 1804 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 1805 int num) 1806 { 1807 struct drm_dp_aux *aux = adapter->algo_data; 1808 unsigned int i, j; 1809 unsigned transfer_size; 1810 struct drm_dp_aux_msg msg; 1811 int err = 0; 1812 1813 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 1814 1815 memset(&msg, 0, sizeof(msg)); 1816 1817 for (i = 0; i < num; i++) { 1818 msg.address = msgs[i].addr; 1819 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1820 /* Send a bare address packet to start the transaction. 1821 * Zero sized messages specify an address only (bare 1822 * address) transaction. 1823 */ 1824 msg.buffer = NULL; 1825 msg.size = 0; 1826 err = drm_dp_i2c_do_msg(aux, &msg); 1827 1828 /* 1829 * Reset msg.request in case in case it got 1830 * changed into a WRITE_STATUS_UPDATE. 1831 */ 1832 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1833 1834 if (err < 0) 1835 break; 1836 /* We want each transaction to be as large as possible, but 1837 * we'll go to smaller sizes if the hardware gives us a 1838 * short reply. 1839 */ 1840 transfer_size = dp_aux_i2c_transfer_size; 1841 for (j = 0; j < msgs[i].len; j += msg.size) { 1842 msg.buffer = msgs[i].buf + j; 1843 msg.size = min(transfer_size, msgs[i].len - j); 1844 1845 err = drm_dp_i2c_drain_msg(aux, &msg); 1846 1847 /* 1848 * Reset msg.request in case in case it got 1849 * changed into a WRITE_STATUS_UPDATE. 1850 */ 1851 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1852 1853 if (err < 0) 1854 break; 1855 transfer_size = err; 1856 } 1857 if (err < 0) 1858 break; 1859 } 1860 if (err >= 0) 1861 err = num; 1862 /* Send a bare address packet to close out the transaction. 1863 * Zero sized messages specify an address only (bare 1864 * address) transaction. 1865 */ 1866 msg.request &= ~DP_AUX_I2C_MOT; 1867 msg.buffer = NULL; 1868 msg.size = 0; 1869 (void)drm_dp_i2c_do_msg(aux, &msg); 1870 1871 return err; 1872 } 1873 1874 static const struct i2c_algorithm drm_dp_i2c_algo = { 1875 .functionality = drm_dp_i2c_functionality, 1876 .master_xfer = drm_dp_i2c_xfer, 1877 }; 1878 1879 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 1880 { 1881 return container_of(i2c, struct drm_dp_aux, ddc); 1882 } 1883 1884 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 1885 { 1886 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 1887 } 1888 1889 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 1890 { 1891 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 1892 } 1893 1894 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 1895 { 1896 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 1897 } 1898 1899 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 1900 .lock_bus = lock_bus, 1901 .trylock_bus = trylock_bus, 1902 .unlock_bus = unlock_bus, 1903 }; 1904 1905 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 1906 { 1907 u8 buf, count; 1908 int ret; 1909 1910 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1911 if (ret < 0) 1912 return ret; 1913 1914 WARN_ON(!(buf & DP_TEST_SINK_START)); 1915 1916 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 1917 if (ret < 0) 1918 return ret; 1919 1920 count = buf & DP_TEST_COUNT_MASK; 1921 if (count == aux->crc_count) 1922 return -EAGAIN; /* No CRC yet */ 1923 1924 aux->crc_count = count; 1925 1926 /* 1927 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 1928 * per component (RGB or CrYCb). 1929 */ 1930 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 1931 if (ret < 0) 1932 return ret; 1933 1934 return 0; 1935 } 1936 1937 static void drm_dp_aux_crc_work(struct work_struct *work) 1938 { 1939 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 1940 crc_work); 1941 struct drm_crtc *crtc; 1942 u8 crc_bytes[6]; 1943 uint32_t crcs[3]; 1944 int ret; 1945 1946 if (WARN_ON(!aux->crtc)) 1947 return; 1948 1949 crtc = aux->crtc; 1950 while (crtc->crc.opened) { 1951 drm_crtc_wait_one_vblank(crtc); 1952 if (!crtc->crc.opened) 1953 break; 1954 1955 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1956 if (ret == -EAGAIN) { 1957 usleep_range(1000, 2000); 1958 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1959 } 1960 1961 if (ret == -EAGAIN) { 1962 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", 1963 aux->name, ret); 1964 continue; 1965 } else if (ret) { 1966 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); 1967 continue; 1968 } 1969 1970 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 1971 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 1972 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 1973 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 1974 } 1975 } 1976 1977 /** 1978 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 1979 * @aux: DisplayPort AUX channel 1980 * 1981 * Used for remote aux channel in general. Merely initialize the crc work 1982 * struct. 1983 */ 1984 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 1985 { 1986 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 1987 } 1988 EXPORT_SYMBOL(drm_dp_remote_aux_init); 1989 1990 /** 1991 * drm_dp_aux_init() - minimally initialise an aux channel 1992 * @aux: DisplayPort AUX channel 1993 * 1994 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with 1995 * the outside world, call drm_dp_aux_init() first. For drivers which are 1996 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a 1997 * &drm_connector), you must still call drm_dp_aux_register() once the connector 1998 * has been registered to allow userspace access to the auxiliary DP channel. 1999 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as 2000 * early as possible so that the &drm_device that corresponds to the AUX adapter 2001 * may be mentioned in debugging output from the DRM DP helpers. 2002 * 2003 * For devices which use a separate platform device for their AUX adapters, this 2004 * may be called as early as required by the driver. 2005 * 2006 */ 2007 void drm_dp_aux_init(struct drm_dp_aux *aux) 2008 { 2009 mutex_init(&aux->hw_mutex); 2010 mutex_init(&aux->cec.lock); 2011 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2012 2013 aux->ddc.algo = &drm_dp_i2c_algo; 2014 aux->ddc.algo_data = aux; 2015 aux->ddc.retries = 3; 2016 2017 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 2018 } 2019 EXPORT_SYMBOL(drm_dp_aux_init); 2020 2021 /** 2022 * drm_dp_aux_register() - initialise and register aux channel 2023 * @aux: DisplayPort AUX channel 2024 * 2025 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This 2026 * should only be called once the parent of @aux, &drm_dp_aux.dev, is 2027 * initialized. For devices which are grandparents of their AUX channels, 2028 * &drm_dp_aux.dev will typically be the &drm_connector &device which 2029 * corresponds to @aux. For these devices, it's advised to call 2030 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to 2031 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. 2032 * Functions which don't follow this will likely Oops when 2033 * %CONFIG_DRM_DP_AUX_CHARDEV is enabled. 2034 * 2035 * For devices where the AUX channel is a device that exists independently of 2036 * the &drm_device that uses it, such as SoCs and bridge devices, it is 2037 * recommended to call drm_dp_aux_register() after a &drm_device has been 2038 * assigned to &drm_dp_aux.drm_dev, and likewise to call 2039 * drm_dp_aux_unregister() once the &drm_device should no longer be associated 2040 * with the AUX channel (e.g. on bridge detach). 2041 * 2042 * Drivers which need to use the aux channel before either of the two points 2043 * mentioned above need to call drm_dp_aux_init() in order to use the AUX 2044 * channel before registration. 2045 * 2046 * Returns 0 on success or a negative error code on failure. 2047 */ 2048 int drm_dp_aux_register(struct drm_dp_aux *aux) 2049 { 2050 int ret; 2051 2052 WARN_ON_ONCE(!aux->drm_dev); 2053 2054 if (!aux->ddc.algo) 2055 drm_dp_aux_init(aux); 2056 2057 aux->ddc.class = I2C_CLASS_DDC; 2058 aux->ddc.owner = THIS_MODULE; 2059 aux->ddc.dev.parent = aux->dev; 2060 2061 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 2062 sizeof(aux->ddc.name)); 2063 2064 ret = drm_dp_aux_register_devnode(aux); 2065 if (ret) 2066 return ret; 2067 2068 ret = i2c_add_adapter(&aux->ddc); 2069 if (ret) { 2070 drm_dp_aux_unregister_devnode(aux); 2071 return ret; 2072 } 2073 2074 return 0; 2075 } 2076 EXPORT_SYMBOL(drm_dp_aux_register); 2077 2078 /** 2079 * drm_dp_aux_unregister() - unregister an AUX adapter 2080 * @aux: DisplayPort AUX channel 2081 */ 2082 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 2083 { 2084 drm_dp_aux_unregister_devnode(aux); 2085 i2c_del_adapter(&aux->ddc); 2086 } 2087 EXPORT_SYMBOL(drm_dp_aux_unregister); 2088 2089 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 2090 2091 /** 2092 * drm_dp_psr_setup_time() - PSR setup in time usec 2093 * @psr_cap: PSR capabilities from DPCD 2094 * 2095 * Returns: 2096 * PSR setup time for the panel in microseconds, negative 2097 * error code on failure. 2098 */ 2099 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 2100 { 2101 static const u16 psr_setup_time_us[] = { 2102 PSR_SETUP_TIME(330), 2103 PSR_SETUP_TIME(275), 2104 PSR_SETUP_TIME(220), 2105 PSR_SETUP_TIME(165), 2106 PSR_SETUP_TIME(110), 2107 PSR_SETUP_TIME(55), 2108 PSR_SETUP_TIME(0), 2109 }; 2110 int i; 2111 2112 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 2113 if (i >= ARRAY_SIZE(psr_setup_time_us)) 2114 return -EINVAL; 2115 2116 return psr_setup_time_us[i]; 2117 } 2118 EXPORT_SYMBOL(drm_dp_psr_setup_time); 2119 2120 #undef PSR_SETUP_TIME 2121 2122 /** 2123 * drm_dp_start_crc() - start capture of frame CRCs 2124 * @aux: DisplayPort AUX channel 2125 * @crtc: CRTC displaying the frames whose CRCs are to be captured 2126 * 2127 * Returns 0 on success or a negative error code on failure. 2128 */ 2129 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 2130 { 2131 u8 buf; 2132 int ret; 2133 2134 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2135 if (ret < 0) 2136 return ret; 2137 2138 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 2139 if (ret < 0) 2140 return ret; 2141 2142 aux->crc_count = 0; 2143 aux->crtc = crtc; 2144 schedule_work(&aux->crc_work); 2145 2146 return 0; 2147 } 2148 EXPORT_SYMBOL(drm_dp_start_crc); 2149 2150 /** 2151 * drm_dp_stop_crc() - stop capture of frame CRCs 2152 * @aux: DisplayPort AUX channel 2153 * 2154 * Returns 0 on success or a negative error code on failure. 2155 */ 2156 int drm_dp_stop_crc(struct drm_dp_aux *aux) 2157 { 2158 u8 buf; 2159 int ret; 2160 2161 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2162 if (ret < 0) 2163 return ret; 2164 2165 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 2166 if (ret < 0) 2167 return ret; 2168 2169 flush_work(&aux->crc_work); 2170 aux->crtc = NULL; 2171 2172 return 0; 2173 } 2174 EXPORT_SYMBOL(drm_dp_stop_crc); 2175 2176 struct dpcd_quirk { 2177 u8 oui[3]; 2178 u8 device_id[6]; 2179 bool is_branch; 2180 u32 quirks; 2181 }; 2182 2183 #define OUI(first, second, third) { (first), (second), (third) } 2184 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 2185 { (first), (second), (third), (fourth), (fifth), (sixth) } 2186 2187 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 2188 2189 static const struct dpcd_quirk dpcd_quirk_list[] = { 2190 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 2191 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2192 /* LG LP140WF6-SPM1 eDP panel */ 2193 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2194 /* Apple panels need some additional handling to support PSR */ 2195 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 2196 /* CH7511 seems to leave SINK_COUNT zeroed */ 2197 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 2198 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 2199 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 2200 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 2201 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 2202 }; 2203 2204 #undef OUI 2205 2206 /* 2207 * Get a bit mask of DPCD quirks for the sink/branch device identified by 2208 * ident. The quirk data is shared but it's up to the drivers to act on the 2209 * data. 2210 * 2211 * For now, only the OUI (first three bytes) is used, but this may be extended 2212 * to device identification string and hardware/firmware revisions later. 2213 */ 2214 static u32 2215 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 2216 { 2217 const struct dpcd_quirk *quirk; 2218 u32 quirks = 0; 2219 int i; 2220 u8 any_device[] = DEVICE_ID_ANY; 2221 2222 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 2223 quirk = &dpcd_quirk_list[i]; 2224 2225 if (quirk->is_branch != is_branch) 2226 continue; 2227 2228 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 2229 continue; 2230 2231 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 2232 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 2233 continue; 2234 2235 quirks |= quirk->quirks; 2236 } 2237 2238 return quirks; 2239 } 2240 2241 #undef DEVICE_ID_ANY 2242 #undef DEVICE_ID 2243 2244 /** 2245 * drm_dp_read_desc - read sink/branch descriptor from DPCD 2246 * @aux: DisplayPort AUX channel 2247 * @desc: Device descriptor to fill from DPCD 2248 * @is_branch: true for branch devices, false for sink devices 2249 * 2250 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 2251 * identification. 2252 * 2253 * Returns 0 on success or a negative error code on failure. 2254 */ 2255 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 2256 bool is_branch) 2257 { 2258 struct drm_dp_dpcd_ident *ident = &desc->ident; 2259 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 2260 int ret, dev_id_len; 2261 2262 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 2263 if (ret < 0) 2264 return ret; 2265 2266 desc->quirks = drm_dp_get_quirks(ident, is_branch); 2267 2268 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); 2269 2270 drm_dbg_kms(aux->drm_dev, 2271 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 2272 aux->name, is_branch ? "branch" : "sink", 2273 (int)sizeof(ident->oui), ident->oui, dev_id_len, 2274 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf, 2275 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks); 2276 2277 return 0; 2278 } 2279 EXPORT_SYMBOL(drm_dp_read_desc); 2280 2281 /** 2282 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2283 * supported by the DSC sink. 2284 * @dsc_dpcd: DSC capabilities from DPCD 2285 * @is_edp: true if its eDP, false for DP 2286 * 2287 * Read the slice capabilities DPCD register from DSC sink to get 2288 * the maximum slice count supported. This is used to populate 2289 * the DSC parameters in the &struct drm_dsc_config by the driver. 2290 * Driver creates an infoframe using these parameters to populate 2291 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2292 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2293 * 2294 * Returns: 2295 * Maximum slice count supported by DSC sink or 0 its invalid 2296 */ 2297 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2298 bool is_edp) 2299 { 2300 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2301 2302 if (is_edp) { 2303 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2304 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2305 return 4; 2306 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2307 return 2; 2308 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2309 return 1; 2310 } else { 2311 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2312 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2313 2314 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2315 return 24; 2316 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2317 return 20; 2318 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2319 return 16; 2320 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2321 return 12; 2322 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2323 return 10; 2324 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2325 return 8; 2326 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2327 return 6; 2328 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2329 return 4; 2330 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2331 return 2; 2332 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2333 return 1; 2334 } 2335 2336 return 0; 2337 } 2338 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2339 2340 /** 2341 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2342 * @dsc_dpcd: DSC capabilities from DPCD 2343 * 2344 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2345 * number of bits of precision within the decoder line buffer supported by 2346 * the DSC sink. This is used to populate the DSC parameters in the 2347 * &struct drm_dsc_config by the driver. 2348 * Driver creates an infoframe using these parameters to populate 2349 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2350 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2351 * 2352 * Returns: 2353 * Line buffer depth supported by DSC panel or 0 its invalid 2354 */ 2355 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2356 { 2357 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2358 2359 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2360 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2361 return 9; 2362 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2363 return 10; 2364 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2365 return 11; 2366 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2367 return 12; 2368 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2369 return 13; 2370 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2371 return 14; 2372 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2373 return 15; 2374 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2375 return 16; 2376 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2377 return 8; 2378 } 2379 2380 return 0; 2381 } 2382 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2383 2384 /** 2385 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2386 * values supported by the DSC sink. 2387 * @dsc_dpcd: DSC capabilities from DPCD 2388 * @dsc_bpc: An array to be filled by this helper with supported 2389 * input bpcs. 2390 * 2391 * Read the DSC DPCD from the sink device to parse the supported bits per 2392 * component values. This is used to populate the DSC parameters 2393 * in the &struct drm_dsc_config by the driver. 2394 * Driver creates an infoframe using these parameters to populate 2395 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2396 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2397 * 2398 * Returns: 2399 * Number of input BPC values parsed from the DPCD 2400 */ 2401 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2402 u8 dsc_bpc[3]) 2403 { 2404 int num_bpc = 0; 2405 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2406 2407 if (color_depth & DP_DSC_12_BPC) 2408 dsc_bpc[num_bpc++] = 12; 2409 if (color_depth & DP_DSC_10_BPC) 2410 dsc_bpc[num_bpc++] = 10; 2411 if (color_depth & DP_DSC_8_BPC) 2412 dsc_bpc[num_bpc++] = 8; 2413 2414 return num_bpc; 2415 } 2416 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2417 2418 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, 2419 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, 2420 u8 *buf, int buf_size) 2421 { 2422 /* 2423 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns 2424 * corrupted values when reading from the 0xF0000- range with a block 2425 * size bigger than 1. 2426 */ 2427 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; 2428 int offset; 2429 int ret; 2430 2431 for (offset = 0; offset < buf_size; offset += block_size) { 2432 ret = drm_dp_dpcd_read(aux, 2433 address + offset, 2434 &buf[offset], block_size); 2435 if (ret < 0) 2436 return ret; 2437 2438 WARN_ON(ret != block_size); 2439 } 2440 2441 return 0; 2442 } 2443 2444 /** 2445 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities 2446 * @aux: DisplayPort AUX channel 2447 * @dpcd: DisplayPort configuration data 2448 * @caps: buffer to return the capability info in 2449 * 2450 * Read capabilities common to all LTTPRs. 2451 * 2452 * Returns 0 on success or a negative error code on failure. 2453 */ 2454 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 2455 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2456 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2457 { 2458 return drm_dp_read_lttpr_regs(aux, dpcd, 2459 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 2460 caps, DP_LTTPR_COMMON_CAP_SIZE); 2461 } 2462 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 2463 2464 /** 2465 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY 2466 * @aux: DisplayPort AUX channel 2467 * @dpcd: DisplayPort configuration data 2468 * @dp_phy: LTTPR PHY to read the capabilities for 2469 * @caps: buffer to return the capability info in 2470 * 2471 * Read the capabilities for the given LTTPR PHY. 2472 * 2473 * Returns 0 on success or a negative error code on failure. 2474 */ 2475 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 2476 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2477 enum drm_dp_phy dp_phy, 2478 u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2479 { 2480 return drm_dp_read_lttpr_regs(aux, dpcd, 2481 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), 2482 caps, DP_LTTPR_PHY_CAP_SIZE); 2483 } 2484 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); 2485 2486 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) 2487 { 2488 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 2489 } 2490 2491 /** 2492 * drm_dp_lttpr_count - get the number of detected LTTPRs 2493 * @caps: LTTPR common capabilities 2494 * 2495 * Get the number of detected LTTPRs from the LTTPR common capabilities info. 2496 * 2497 * Returns: 2498 * -ERANGE if more than supported number (8) of LTTPRs are detected 2499 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value 2500 * otherwise the number of detected LTTPRs 2501 */ 2502 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2503 { 2504 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); 2505 2506 switch (hweight8(count)) { 2507 case 0: 2508 return 0; 2509 case 1: 2510 return 8 - ilog2(count); 2511 case 8: 2512 return -ERANGE; 2513 default: 2514 return -EINVAL; 2515 } 2516 } 2517 EXPORT_SYMBOL(drm_dp_lttpr_count); 2518 2519 /** 2520 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs 2521 * @caps: LTTPR common capabilities 2522 * 2523 * Returns the maximum link rate supported by all detected LTTPRs. 2524 */ 2525 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2526 { 2527 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); 2528 2529 return drm_dp_bw_code_to_link_rate(rate); 2530 } 2531 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2532 2533 /** 2534 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2535 * @caps: LTTPR common capabilities 2536 * 2537 * Returns the maximum lane count supported by all detected LTTPRs. 2538 */ 2539 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2540 { 2541 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); 2542 2543 return max_lanes & DP_MAX_LANE_COUNT_MASK; 2544 } 2545 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); 2546 2547 /** 2548 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support 2549 * @caps: LTTPR PHY capabilities 2550 * 2551 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2552 * voltage swing level 3. 2553 */ 2554 bool 2555 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2556 { 2557 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2558 2559 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; 2560 } 2561 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); 2562 2563 /** 2564 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support 2565 * @caps: LTTPR PHY capabilities 2566 * 2567 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2568 * pre-emphasis level 3. 2569 */ 2570 bool 2571 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2572 { 2573 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2574 2575 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; 2576 } 2577 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); 2578 2579 /** 2580 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2581 * @aux: DisplayPort AUX channel 2582 * @data: DP phy compliance test parameters. 2583 * 2584 * Returns 0 on success or a negative error code on failure. 2585 */ 2586 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2587 struct drm_dp_phy_test_params *data) 2588 { 2589 int err; 2590 u8 rate, lanes; 2591 2592 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2593 if (err < 0) 2594 return err; 2595 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 2596 2597 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2598 if (err < 0) 2599 return err; 2600 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2601 2602 if (lanes & DP_ENHANCED_FRAME_CAP) 2603 data->enhanced_frame_cap = true; 2604 2605 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 2606 if (err < 0) 2607 return err; 2608 2609 switch (data->phy_pattern) { 2610 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2611 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 2612 &data->custom80, sizeof(data->custom80)); 2613 if (err < 0) 2614 return err; 2615 2616 break; 2617 case DP_PHY_TEST_PATTERN_CP2520: 2618 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 2619 &data->hbr2_reset, 2620 sizeof(data->hbr2_reset)); 2621 if (err < 0) 2622 return err; 2623 } 2624 2625 return 0; 2626 } 2627 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 2628 2629 /** 2630 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 2631 * @aux: DisplayPort AUX channel 2632 * @data: DP phy compliance test parameters. 2633 * @dp_rev: DP revision to use for compliance testing 2634 * 2635 * Returns 0 on success or a negative error code on failure. 2636 */ 2637 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 2638 struct drm_dp_phy_test_params *data, u8 dp_rev) 2639 { 2640 int err, i; 2641 u8 link_config[2]; 2642 u8 test_pattern; 2643 2644 link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate); 2645 link_config[1] = data->num_lanes; 2646 if (data->enhanced_frame_cap) 2647 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2648 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2); 2649 if (err < 0) 2650 return err; 2651 2652 test_pattern = data->phy_pattern; 2653 if (dp_rev < 0x12) { 2654 test_pattern = (test_pattern << 2) & 2655 DP_LINK_QUAL_PATTERN_11_MASK; 2656 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 2657 test_pattern); 2658 if (err < 0) 2659 return err; 2660 } else { 2661 for (i = 0; i < data->num_lanes; i++) { 2662 err = drm_dp_dpcd_writeb(aux, 2663 DP_LINK_QUAL_LANE0_SET + i, 2664 test_pattern); 2665 if (err < 0) 2666 return err; 2667 } 2668 } 2669 2670 return 0; 2671 } 2672 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 2673 2674 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 2675 { 2676 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2677 return "Invalid"; 2678 2679 switch (pixelformat) { 2680 case DP_PIXELFORMAT_RGB: 2681 return "RGB"; 2682 case DP_PIXELFORMAT_YUV444: 2683 return "YUV444"; 2684 case DP_PIXELFORMAT_YUV422: 2685 return "YUV422"; 2686 case DP_PIXELFORMAT_YUV420: 2687 return "YUV420"; 2688 case DP_PIXELFORMAT_Y_ONLY: 2689 return "Y_ONLY"; 2690 case DP_PIXELFORMAT_RAW: 2691 return "RAW"; 2692 default: 2693 return "Reserved"; 2694 } 2695 } 2696 2697 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 2698 enum dp_colorimetry colorimetry) 2699 { 2700 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2701 return "Invalid"; 2702 2703 switch (colorimetry) { 2704 case DP_COLORIMETRY_DEFAULT: 2705 switch (pixelformat) { 2706 case DP_PIXELFORMAT_RGB: 2707 return "sRGB"; 2708 case DP_PIXELFORMAT_YUV444: 2709 case DP_PIXELFORMAT_YUV422: 2710 case DP_PIXELFORMAT_YUV420: 2711 return "BT.601"; 2712 case DP_PIXELFORMAT_Y_ONLY: 2713 return "DICOM PS3.14"; 2714 case DP_PIXELFORMAT_RAW: 2715 return "Custom Color Profile"; 2716 default: 2717 return "Reserved"; 2718 } 2719 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 2720 switch (pixelformat) { 2721 case DP_PIXELFORMAT_RGB: 2722 return "Wide Fixed"; 2723 case DP_PIXELFORMAT_YUV444: 2724 case DP_PIXELFORMAT_YUV422: 2725 case DP_PIXELFORMAT_YUV420: 2726 return "BT.709"; 2727 default: 2728 return "Reserved"; 2729 } 2730 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 2731 switch (pixelformat) { 2732 case DP_PIXELFORMAT_RGB: 2733 return "Wide Float"; 2734 case DP_PIXELFORMAT_YUV444: 2735 case DP_PIXELFORMAT_YUV422: 2736 case DP_PIXELFORMAT_YUV420: 2737 return "xvYCC 601"; 2738 default: 2739 return "Reserved"; 2740 } 2741 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 2742 switch (pixelformat) { 2743 case DP_PIXELFORMAT_RGB: 2744 return "OpRGB"; 2745 case DP_PIXELFORMAT_YUV444: 2746 case DP_PIXELFORMAT_YUV422: 2747 case DP_PIXELFORMAT_YUV420: 2748 return "xvYCC 709"; 2749 default: 2750 return "Reserved"; 2751 } 2752 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 2753 switch (pixelformat) { 2754 case DP_PIXELFORMAT_RGB: 2755 return "DCI-P3"; 2756 case DP_PIXELFORMAT_YUV444: 2757 case DP_PIXELFORMAT_YUV422: 2758 case DP_PIXELFORMAT_YUV420: 2759 return "sYCC 601"; 2760 default: 2761 return "Reserved"; 2762 } 2763 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 2764 switch (pixelformat) { 2765 case DP_PIXELFORMAT_RGB: 2766 return "Custom Profile"; 2767 case DP_PIXELFORMAT_YUV444: 2768 case DP_PIXELFORMAT_YUV422: 2769 case DP_PIXELFORMAT_YUV420: 2770 return "OpYCC 601"; 2771 default: 2772 return "Reserved"; 2773 } 2774 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 2775 switch (pixelformat) { 2776 case DP_PIXELFORMAT_RGB: 2777 return "BT.2020 RGB"; 2778 case DP_PIXELFORMAT_YUV444: 2779 case DP_PIXELFORMAT_YUV422: 2780 case DP_PIXELFORMAT_YUV420: 2781 return "BT.2020 CYCC"; 2782 default: 2783 return "Reserved"; 2784 } 2785 case DP_COLORIMETRY_BT2020_YCC: 2786 switch (pixelformat) { 2787 case DP_PIXELFORMAT_YUV444: 2788 case DP_PIXELFORMAT_YUV422: 2789 case DP_PIXELFORMAT_YUV420: 2790 return "BT.2020 YCC"; 2791 default: 2792 return "Reserved"; 2793 } 2794 default: 2795 return "Invalid"; 2796 } 2797 } 2798 2799 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 2800 { 2801 switch (dynamic_range) { 2802 case DP_DYNAMIC_RANGE_VESA: 2803 return "VESA range"; 2804 case DP_DYNAMIC_RANGE_CTA: 2805 return "CTA range"; 2806 default: 2807 return "Invalid"; 2808 } 2809 } 2810 2811 static const char *dp_content_type_get_name(enum dp_content_type content_type) 2812 { 2813 switch (content_type) { 2814 case DP_CONTENT_TYPE_NOT_DEFINED: 2815 return "Not defined"; 2816 case DP_CONTENT_TYPE_GRAPHICS: 2817 return "Graphics"; 2818 case DP_CONTENT_TYPE_PHOTO: 2819 return "Photo"; 2820 case DP_CONTENT_TYPE_VIDEO: 2821 return "Video"; 2822 case DP_CONTENT_TYPE_GAME: 2823 return "Game"; 2824 default: 2825 return "Reserved"; 2826 } 2827 } 2828 2829 void drm_dp_vsc_sdp_log(const char *level, struct device *dev, 2830 const struct drm_dp_vsc_sdp *vsc) 2831 { 2832 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__) 2833 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", 2834 vsc->revision, vsc->length); 2835 DP_SDP_LOG(" pixelformat: %s\n", 2836 dp_pixelformat_get_name(vsc->pixelformat)); 2837 DP_SDP_LOG(" colorimetry: %s\n", 2838 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 2839 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); 2840 DP_SDP_LOG(" dynamic range: %s\n", 2841 dp_dynamic_range_get_name(vsc->dynamic_range)); 2842 DP_SDP_LOG(" content type: %s\n", 2843 dp_content_type_get_name(vsc->content_type)); 2844 #undef DP_SDP_LOG 2845 } 2846 EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 2847 2848 /** 2849 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON 2850 * @dpcd: DisplayPort configuration data 2851 * @port_cap: port capabilities 2852 * 2853 * Returns maximum frl bandwidth supported by PCON in GBPS, 2854 * returns 0 if not supported. 2855 */ 2856 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2857 const u8 port_cap[4]) 2858 { 2859 int bw; 2860 u8 buf; 2861 2862 buf = port_cap[2]; 2863 bw = buf & DP_PCON_MAX_FRL_BW; 2864 2865 switch (bw) { 2866 case DP_PCON_MAX_9GBPS: 2867 return 9; 2868 case DP_PCON_MAX_18GBPS: 2869 return 18; 2870 case DP_PCON_MAX_24GBPS: 2871 return 24; 2872 case DP_PCON_MAX_32GBPS: 2873 return 32; 2874 case DP_PCON_MAX_40GBPS: 2875 return 40; 2876 case DP_PCON_MAX_48GBPS: 2877 return 48; 2878 case DP_PCON_MAX_0GBPS: 2879 default: 2880 return 0; 2881 } 2882 2883 return 0; 2884 } 2885 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); 2886 2887 /** 2888 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. 2889 * @aux: DisplayPort AUX channel 2890 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. 2891 * 2892 * Returns 0 if success, else returns negative error code. 2893 */ 2894 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) 2895 { 2896 int ret; 2897 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE | 2898 DP_PCON_ENABLE_LINK_FRL_MODE; 2899 2900 if (enable_frl_ready_hpd) 2901 buf |= DP_PCON_ENABLE_HPD_READY; 2902 2903 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 2904 2905 return ret; 2906 } 2907 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare); 2908 2909 /** 2910 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL 2911 * @aux: DisplayPort AUX channel 2912 * 2913 * Returns true if success, else returns false. 2914 */ 2915 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) 2916 { 2917 int ret; 2918 u8 buf; 2919 2920 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 2921 if (ret < 0) 2922 return false; 2923 2924 if (buf & DP_PCON_FRL_READY) 2925 return true; 2926 2927 return false; 2928 } 2929 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); 2930 2931 /** 2932 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 2933 * @aux: DisplayPort AUX channel 2934 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink 2935 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. 2936 * In Concurrent Mode, the FRL link bring up can be done along with 2937 * DP Link training. In Sequential mode, the FRL link bring up is done prior to 2938 * the DP Link training. 2939 * 2940 * Returns 0 if success, else returns negative error code. 2941 */ 2942 2943 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 2944 u8 frl_mode) 2945 { 2946 int ret; 2947 u8 buf; 2948 2949 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 2950 if (ret < 0) 2951 return ret; 2952 2953 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) 2954 buf |= DP_PCON_ENABLE_CONCURRENT_LINK; 2955 else 2956 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; 2957 2958 switch (max_frl_gbps) { 2959 case 9: 2960 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS; 2961 break; 2962 case 18: 2963 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS; 2964 break; 2965 case 24: 2966 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS; 2967 break; 2968 case 32: 2969 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS; 2970 break; 2971 case 40: 2972 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS; 2973 break; 2974 case 48: 2975 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS; 2976 break; 2977 case 0: 2978 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS; 2979 break; 2980 default: 2981 return -EINVAL; 2982 } 2983 2984 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 2985 if (ret < 0) 2986 return ret; 2987 2988 return 0; 2989 } 2990 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); 2991 2992 /** 2993 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 2994 * @aux: DisplayPort AUX channel 2995 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink 2996 * @frl_type : FRL training type, can be Extended, or Normal. 2997 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask 2998 * starting from min, and stops when link training is successful. In Extended 2999 * FRL training, all frl bw selected in the mask are trained by the PCON. 3000 * 3001 * Returns 0 if success, else returns negative error code. 3002 */ 3003 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 3004 u8 frl_type) 3005 { 3006 int ret; 3007 u8 buf = max_frl_mask; 3008 3009 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) 3010 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3011 else 3012 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3013 3014 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); 3015 if (ret < 0) 3016 return ret; 3017 3018 return 0; 3019 } 3020 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2); 3021 3022 /** 3023 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. 3024 * @aux: DisplayPort AUX channel 3025 * 3026 * Returns 0 if success, else returns negative error code. 3027 */ 3028 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) 3029 { 3030 int ret; 3031 3032 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); 3033 if (ret < 0) 3034 return ret; 3035 3036 return 0; 3037 } 3038 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config); 3039 3040 /** 3041 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL 3042 * @aux: DisplayPort AUX channel 3043 * 3044 * Returns 0 if success, else returns negative error code. 3045 */ 3046 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) 3047 { 3048 int ret; 3049 u8 buf = 0; 3050 3051 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3052 if (ret < 0) 3053 return ret; 3054 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) { 3055 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", 3056 aux->name); 3057 return -EINVAL; 3058 } 3059 buf |= DP_PCON_ENABLE_HDMI_LINK; 3060 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3061 if (ret < 0) 3062 return ret; 3063 3064 return 0; 3065 } 3066 EXPORT_SYMBOL(drm_dp_pcon_frl_enable); 3067 3068 /** 3069 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. 3070 * @aux: DisplayPort AUX channel 3071 * 3072 * Returns true if link is active else returns false. 3073 */ 3074 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) 3075 { 3076 u8 buf; 3077 int ret; 3078 3079 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3080 if (ret < 0) 3081 return false; 3082 3083 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; 3084 } 3085 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active); 3086 3087 /** 3088 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE 3089 * @aux: DisplayPort AUX channel 3090 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. 3091 * Valid only if the MODE returned is FRL. For Normal Link training mode 3092 * only 1 of the bits will be set, but in case of Extended mode, more than 3093 * one bits can be set. 3094 * 3095 * Returns the link mode : TMDS or FRL on success, else returns negative error 3096 * code. 3097 */ 3098 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) 3099 { 3100 u8 buf; 3101 int mode; 3102 int ret; 3103 3104 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); 3105 if (ret < 0) 3106 return ret; 3107 3108 mode = buf & DP_PCON_HDMI_LINK_MODE; 3109 3110 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode) 3111 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1; 3112 3113 return mode; 3114 } 3115 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode); 3116 3117 /** 3118 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane 3119 * during link failure between PCON and HDMI sink 3120 * @aux: DisplayPort AUX channel 3121 * @connector: DRM connector 3122 * code. 3123 **/ 3124 3125 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 3126 struct drm_connector *connector) 3127 { 3128 u8 buf, error_count; 3129 int i, num_error; 3130 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3131 3132 for (i = 0; i < hdmi->max_lanes; i++) { 3133 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) 3134 return; 3135 3136 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK; 3137 switch (error_count) { 3138 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS: 3139 num_error = 100; 3140 break; 3141 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS: 3142 num_error = 10; 3143 break; 3144 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS: 3145 num_error = 3; 3146 break; 3147 default: 3148 num_error = 0; 3149 } 3150 3151 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", 3152 aux->name, num_error, i); 3153 } 3154 } 3155 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count); 3156 3157 /* 3158 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 3159 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3160 * 3161 * Returns true is PCON encoder is DSC 1.2 else returns false. 3162 */ 3163 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3164 { 3165 u8 buf; 3166 u8 major_v, minor_v; 3167 3168 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; 3169 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT; 3170 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT; 3171 3172 if (major_v == 1 && minor_v == 2) 3173 return true; 3174 3175 return false; 3176 } 3177 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2); 3178 3179 /* 3180 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder 3181 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3182 * 3183 * Returns maximum no. of slices supported by the PCON DSC Encoder. 3184 */ 3185 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3186 { 3187 u8 slice_cap1, slice_cap2; 3188 3189 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; 3190 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; 3191 3192 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC) 3193 return 24; 3194 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC) 3195 return 20; 3196 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC) 3197 return 16; 3198 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC) 3199 return 12; 3200 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC) 3201 return 10; 3202 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC) 3203 return 8; 3204 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC) 3205 return 6; 3206 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC) 3207 return 4; 3208 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC) 3209 return 2; 3210 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC) 3211 return 1; 3212 3213 return 0; 3214 } 3215 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices); 3216 3217 /* 3218 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder 3219 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3220 * 3221 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. 3222 */ 3223 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3224 { 3225 u8 buf; 3226 3227 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; 3228 3229 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; 3230 } 3231 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width); 3232 3233 /* 3234 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder 3235 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3236 * 3237 * Returns the bpp precision supported by the PCON encoder. 3238 */ 3239 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3240 { 3241 u8 buf; 3242 3243 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; 3244 3245 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) { 3246 case DP_PCON_DSC_ONE_16TH_BPP: 3247 return 16; 3248 case DP_PCON_DSC_ONE_8TH_BPP: 3249 return 8; 3250 case DP_PCON_DSC_ONE_4TH_BPP: 3251 return 4; 3252 case DP_PCON_DSC_ONE_HALF_BPP: 3253 return 2; 3254 case DP_PCON_DSC_ONE_BPP: 3255 return 1; 3256 } 3257 3258 return 0; 3259 } 3260 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr); 3261 3262 static 3263 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) 3264 { 3265 u8 buf; 3266 int ret; 3267 3268 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3269 if (ret < 0) 3270 return ret; 3271 3272 buf |= DP_PCON_ENABLE_DSC_ENCODER; 3273 3274 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) { 3275 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK; 3276 buf |= pps_buf_config << 2; 3277 } 3278 3279 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3280 if (ret < 0) 3281 return ret; 3282 3283 return 0; 3284 } 3285 3286 /** 3287 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters 3288 * for DSC1.2 between PCON & HDMI2.1 sink 3289 * @aux: DisplayPort AUX channel 3290 * 3291 * Returns 0 on success, else returns negative error code. 3292 */ 3293 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) 3294 { 3295 int ret; 3296 3297 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); 3298 if (ret < 0) 3299 return ret; 3300 3301 return 0; 3302 } 3303 EXPORT_SYMBOL(drm_dp_pcon_pps_default); 3304 3305 /** 3306 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for 3307 * HDMI sink 3308 * @aux: DisplayPort AUX channel 3309 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. 3310 * 3311 * Returns 0 on success, else returns negative error code. 3312 */ 3313 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) 3314 { 3315 int ret; 3316 3317 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); 3318 if (ret < 0) 3319 return ret; 3320 3321 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3322 if (ret < 0) 3323 return ret; 3324 3325 return 0; 3326 } 3327 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf); 3328 3329 /* 3330 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder 3331 * override registers 3332 * @aux: DisplayPort AUX channel 3333 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, 3334 * bits_per_pixel. 3335 * 3336 * Returns 0 on success, else returns negative error code. 3337 */ 3338 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) 3339 { 3340 int ret; 3341 3342 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); 3343 if (ret < 0) 3344 return ret; 3345 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); 3346 if (ret < 0) 3347 return ret; 3348 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); 3349 if (ret < 0) 3350 return ret; 3351 3352 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3353 if (ret < 0) 3354 return ret; 3355 3356 return 0; 3357 } 3358 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param); 3359 3360 /* 3361 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr 3362 * @aux: displayPort AUX channel 3363 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. 3364 * 3365 * Returns 0 on success, else returns negative error code. 3366 */ 3367 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) 3368 { 3369 int ret; 3370 u8 buf; 3371 3372 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3373 if (ret < 0) 3374 return ret; 3375 3376 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK) 3377 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK); 3378 else 3379 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK; 3380 3381 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3382 if (ret < 0) 3383 return ret; 3384 3385 return 0; 3386 } 3387 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr); 3388 3389 /** 3390 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX 3391 * @aux: The DP AUX channel to use 3392 * @bl: Backlight capability info from drm_edp_backlight_init() 3393 * @level: The brightness level to set 3394 * 3395 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must 3396 * already have been enabled by the driver by calling drm_edp_backlight_enable(). 3397 * 3398 * Returns: %0 on success, negative error code on failure 3399 */ 3400 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3401 u16 level) 3402 { 3403 int ret; 3404 u8 buf[2] = { 0 }; 3405 3406 /* The panel uses the PWM for controlling brightness levels */ 3407 if (!bl->aux_set) 3408 return 0; 3409 3410 if (bl->lsb_reg_used) { 3411 buf[0] = (level & 0xff00) >> 8; 3412 buf[1] = (level & 0x00ff); 3413 } else { 3414 buf[0] = level; 3415 } 3416 3417 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); 3418 if (ret != sizeof(buf)) { 3419 drm_err(aux->drm_dev, 3420 "%s: Failed to write aux backlight level: %d\n", 3421 aux->name, ret); 3422 return ret < 0 ? ret : -EIO; 3423 } 3424 3425 return 0; 3426 } 3427 EXPORT_SYMBOL(drm_edp_backlight_set_level); 3428 3429 static int 3430 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3431 bool enable) 3432 { 3433 int ret; 3434 u8 buf; 3435 3436 /* This panel uses the EDP_BL_PWR GPIO for enablement */ 3437 if (!bl->aux_enable) 3438 return 0; 3439 3440 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); 3441 if (ret != 1) { 3442 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", 3443 aux->name, ret); 3444 return ret < 0 ? ret : -EIO; 3445 } 3446 if (enable) 3447 buf |= DP_EDP_BACKLIGHT_ENABLE; 3448 else 3449 buf &= ~DP_EDP_BACKLIGHT_ENABLE; 3450 3451 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); 3452 if (ret != 1) { 3453 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", 3454 aux->name, ret); 3455 return ret < 0 ? ret : -EIO; 3456 } 3457 3458 return 0; 3459 } 3460 3461 /** 3462 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD 3463 * @aux: The DP AUX channel to use 3464 * @bl: Backlight capability info from drm_edp_backlight_init() 3465 * @level: The initial backlight level to set via AUX, if there is one 3466 * 3467 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally 3468 * restoring any important backlight state such as the given backlight level, the brightness byte 3469 * count, backlight frequency, etc. 3470 * 3471 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3472 * that the driver handle enabling/disabling the panel through implementation-specific means using 3473 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3474 * this function becomes a no-op, and the driver is expected to handle powering the panel on using 3475 * the EDP_BL_PWR GPIO. 3476 * 3477 * Returns: %0 on success, negative error code on failure. 3478 */ 3479 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3480 const u16 level) 3481 { 3482 int ret; 3483 u8 dpcd_buf; 3484 3485 if (bl->aux_set) 3486 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; 3487 else 3488 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM; 3489 3490 if (bl->pwmgen_bit_count) { 3491 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); 3492 if (ret != 1) 3493 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3494 aux->name, ret); 3495 } 3496 3497 if (bl->pwm_freq_pre_divider) { 3498 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); 3499 if (ret != 1) 3500 drm_dbg_kms(aux->drm_dev, 3501 "%s: Failed to write aux backlight frequency: %d\n", 3502 aux->name, ret); 3503 else 3504 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; 3505 } 3506 3507 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); 3508 if (ret != 1) { 3509 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", 3510 aux->name, ret); 3511 return ret < 0 ? ret : -EIO; 3512 } 3513 3514 ret = drm_edp_backlight_set_level(aux, bl, level); 3515 if (ret < 0) 3516 return ret; 3517 ret = drm_edp_backlight_set_enable(aux, bl, true); 3518 if (ret < 0) 3519 return ret; 3520 3521 return 0; 3522 } 3523 EXPORT_SYMBOL(drm_edp_backlight_enable); 3524 3525 /** 3526 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported 3527 * @aux: The DP AUX channel to use 3528 * @bl: Backlight capability info from drm_edp_backlight_init() 3529 * 3530 * This function handles disabling DPCD backlight controls on a panel over AUX. 3531 * 3532 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3533 * that the driver handle enabling/disabling the panel through implementation-specific means using 3534 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3535 * this function becomes a no-op, and the driver is expected to handle powering the panel off using 3536 * the EDP_BL_PWR GPIO. 3537 * 3538 * Returns: %0 on success or no-op, negative error code on failure. 3539 */ 3540 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) 3541 { 3542 int ret; 3543 3544 ret = drm_edp_backlight_set_enable(aux, bl, false); 3545 if (ret < 0) 3546 return ret; 3547 3548 return 0; 3549 } 3550 EXPORT_SYMBOL(drm_edp_backlight_disable); 3551 3552 static inline int 3553 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3554 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 3555 { 3556 int fxp, fxp_min, fxp_max, fxp_actual, f = 1; 3557 int ret; 3558 u8 pn, pn_min, pn_max; 3559 3560 if (!bl->aux_set) 3561 return 0; 3562 3563 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); 3564 if (ret != 1) { 3565 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", 3566 aux->name, ret); 3567 return -ENODEV; 3568 } 3569 3570 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3571 bl->max = (1 << pn) - 1; 3572 if (!driver_pwm_freq_hz) 3573 return 0; 3574 3575 /* 3576 * Set PWM Frequency divider to match desired frequency provided by the driver. 3577 * The PWM Frequency is calculated as 27Mhz / (F x P). 3578 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the 3579 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) 3580 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the 3581 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) 3582 */ 3583 3584 /* Find desired value of (F x P) 3585 * Note that, if F x P is out of supported range, the maximum value or minimum value will 3586 * applied automatically. So no need to check that. 3587 */ 3588 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz); 3589 3590 /* Use highest possible value of Pn for more granularity of brightness adjustment while 3591 * satisfying the conditions below. 3592 * - Pn is in the range of Pn_min and Pn_max 3593 * - F is in the range of 1 and 255 3594 * - FxP is within 25% of desired value. 3595 * Note: 25% is arbitrary value and may need some tweak. 3596 */ 3597 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); 3598 if (ret != 1) { 3599 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", 3600 aux->name, ret); 3601 return 0; 3602 } 3603 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); 3604 if (ret != 1) { 3605 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", 3606 aux->name, ret); 3607 return 0; 3608 } 3609 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3610 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3611 3612 /* Ensure frequency is within 25% of desired value */ 3613 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); 3614 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); 3615 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { 3616 drm_dbg_kms(aux->drm_dev, 3617 "%s: Driver defined backlight frequency (%d) out of range\n", 3618 aux->name, driver_pwm_freq_hz); 3619 return 0; 3620 } 3621 3622 for (pn = pn_max; pn >= pn_min; pn--) { 3623 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); 3624 fxp_actual = f << pn; 3625 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) 3626 break; 3627 } 3628 3629 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); 3630 if (ret != 1) { 3631 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3632 aux->name, ret); 3633 return 0; 3634 } 3635 bl->pwmgen_bit_count = pn; 3636 bl->max = (1 << pn) - 1; 3637 3638 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) { 3639 bl->pwm_freq_pre_divider = f; 3640 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", 3641 aux->name, driver_pwm_freq_hz); 3642 } 3643 3644 return 0; 3645 } 3646 3647 static inline int 3648 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3649 u8 *current_mode) 3650 { 3651 int ret; 3652 u8 buf[2]; 3653 u8 mode_reg; 3654 3655 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); 3656 if (ret != 1) { 3657 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", 3658 aux->name, ret); 3659 return ret < 0 ? ret : -EIO; 3660 } 3661 3662 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK); 3663 if (!bl->aux_set) 3664 return 0; 3665 3666 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { 3667 int size = 1 + bl->lsb_reg_used; 3668 3669 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); 3670 if (ret != size) { 3671 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", 3672 aux->name, ret); 3673 return ret < 0 ? ret : -EIO; 3674 } 3675 3676 if (bl->lsb_reg_used) 3677 return (buf[0] << 8) | buf[1]; 3678 else 3679 return buf[0]; 3680 } 3681 3682 /* 3683 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and 3684 * the driver should assume max brightness 3685 */ 3686 return bl->max; 3687 } 3688 3689 /** 3690 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight 3691 * interface. 3692 * @aux: The DP aux device to use for probing 3693 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight 3694 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz 3695 * @edp_dpcd: A cached copy of the eDP DPCD 3696 * @current_level: Where to store the probed brightness level, if any 3697 * @current_mode: Where to store the currently set backlight control mode 3698 * 3699 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, 3700 * along with also probing the current and maximum supported brightness levels. 3701 * 3702 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the 3703 * default frequency from the panel is used. 3704 * 3705 * Returns: %0 on success, negative error code on failure. 3706 */ 3707 int 3708 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3709 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 3710 u16 *current_level, u8 *current_mode) 3711 { 3712 int ret; 3713 3714 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) 3715 bl->aux_enable = true; 3716 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) 3717 bl->aux_set = true; 3718 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 3719 bl->lsb_reg_used = true; 3720 3721 /* Sanity check caps */ 3722 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { 3723 drm_dbg_kms(aux->drm_dev, 3724 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", 3725 aux->name); 3726 return -EINVAL; 3727 } 3728 3729 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); 3730 if (ret < 0) 3731 return ret; 3732 3733 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); 3734 if (ret < 0) 3735 return ret; 3736 *current_level = ret; 3737 3738 drm_dbg_kms(aux->drm_dev, 3739 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n", 3740 aux->name, bl->aux_set, bl->aux_enable, *current_mode); 3741 if (bl->aux_set) { 3742 drm_dbg_kms(aux->drm_dev, 3743 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n", 3744 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, 3745 bl->lsb_reg_used); 3746 } 3747 3748 return 0; 3749 } 3750 EXPORT_SYMBOL(drm_edp_backlight_init); 3751 3752 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 3753 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) 3754 3755 static int dp_aux_backlight_update_status(struct backlight_device *bd) 3756 { 3757 struct dp_aux_backlight *bl = bl_get_data(bd); 3758 u16 brightness = backlight_get_brightness(bd); 3759 int ret = 0; 3760 3761 if (!backlight_is_blank(bd)) { 3762 if (!bl->enabled) { 3763 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); 3764 bl->enabled = true; 3765 return 0; 3766 } 3767 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); 3768 } else { 3769 if (bl->enabled) { 3770 drm_edp_backlight_disable(bl->aux, &bl->info); 3771 bl->enabled = false; 3772 } 3773 } 3774 3775 return ret; 3776 } 3777 3778 static const struct backlight_ops dp_aux_bl_ops = { 3779 .update_status = dp_aux_backlight_update_status, 3780 }; 3781 3782 /** 3783 * drm_panel_dp_aux_backlight - create and use DP AUX backlight 3784 * @panel: DRM panel 3785 * @aux: The DP AUX channel to use 3786 * 3787 * Use this function to create and handle backlight if your panel 3788 * supports backlight control over DP AUX channel using DPCD 3789 * registers as per VESA's standard backlight control interface. 3790 * 3791 * When the panel is enabled backlight will be enabled after a 3792 * successful call to &drm_panel_funcs.enable() 3793 * 3794 * When the panel is disabled backlight will be disabled before the 3795 * call to &drm_panel_funcs.disable(). 3796 * 3797 * A typical implementation for a panel driver supporting backlight 3798 * control over DP AUX will call this function at probe time. 3799 * Backlight will then be handled transparently without requiring 3800 * any intervention from the driver. 3801 * 3802 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). 3803 * 3804 * Return: 0 on success or a negative error code on failure. 3805 */ 3806 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 3807 { 3808 struct dp_aux_backlight *bl; 3809 struct backlight_properties props = { 0 }; 3810 u16 current_level; 3811 u8 current_mode; 3812 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 3813 int ret; 3814 3815 if (!panel || !panel->dev || !aux) 3816 return -EINVAL; 3817 3818 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, 3819 EDP_DISPLAY_CTL_CAP_SIZE); 3820 if (ret < 0) 3821 return ret; 3822 3823 if (!drm_edp_backlight_supported(edp_dpcd)) { 3824 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); 3825 return 0; 3826 } 3827 3828 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); 3829 if (!bl) 3830 return -ENOMEM; 3831 3832 bl->aux = aux; 3833 3834 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, 3835 ¤t_level, ¤t_mode); 3836 if (ret < 0) 3837 return ret; 3838 3839 props.type = BACKLIGHT_RAW; 3840 props.brightness = current_level; 3841 props.max_brightness = bl->info.max; 3842 3843 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", 3844 panel->dev, bl, 3845 &dp_aux_bl_ops, &props); 3846 if (IS_ERR(bl->base)) 3847 return PTR_ERR(bl->base); 3848 3849 backlight_disable(bl->base); 3850 3851 panel->backlight = bl->base; 3852 3853 return 0; 3854 } 3855 EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 3856 3857 #endif 3858