1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/errno.h> 25 #include <linux/i2c.h> 26 #include <linux/init.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/sched.h> 30 #include <linux/seq_file.h> 31 #include <linux/string_helpers.h> 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/display/drm_dp_mst_helper.h> 35 #include <drm/drm_print.h> 36 #include <drm/drm_vblank.h> 37 #include <drm/drm_panel.h> 38 39 #include "drm_dp_helper_internal.h" 40 41 struct dp_aux_backlight { 42 struct backlight_device *base; 43 struct drm_dp_aux *aux; 44 struct drm_edp_backlight_info info; 45 bool enabled; 46 }; 47 48 /** 49 * DOC: dp helpers 50 * 51 * These functions contain some common logic and helpers at various abstraction 52 * levels to deal with Display Port sink devices and related things like DP aux 53 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 54 * blocks, ... 55 */ 56 57 /* Helpers for DP link training */ 58 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 59 { 60 return link_status[r - DP_LANE0_1_STATUS]; 61 } 62 63 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 64 int lane) 65 { 66 int i = DP_LANE0_1_STATUS + (lane >> 1); 67 int s = (lane & 1) * 4; 68 u8 l = dp_link_status(link_status, i); 69 70 return (l >> s) & 0xf; 71 } 72 73 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 74 int lane_count) 75 { 76 u8 lane_align; 77 u8 lane_status; 78 int lane; 79 80 lane_align = dp_link_status(link_status, 81 DP_LANE_ALIGN_STATUS_UPDATED); 82 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 83 return false; 84 for (lane = 0; lane < lane_count; lane++) { 85 lane_status = dp_get_lane_status(link_status, lane); 86 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 87 return false; 88 } 89 return true; 90 } 91 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 92 93 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 94 int lane_count) 95 { 96 int lane; 97 u8 lane_status; 98 99 for (lane = 0; lane < lane_count; lane++) { 100 lane_status = dp_get_lane_status(link_status, lane); 101 if ((lane_status & DP_LANE_CR_DONE) == 0) 102 return false; 103 } 104 return true; 105 } 106 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 107 108 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 109 int lane) 110 { 111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 112 int s = ((lane & 1) ? 113 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 114 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 115 u8 l = dp_link_status(link_status, i); 116 117 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 118 } 119 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 120 121 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 122 int lane) 123 { 124 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 125 int s = ((lane & 1) ? 126 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 127 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 128 u8 l = dp_link_status(link_status, i); 129 130 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 131 } 132 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 133 134 /* DP 2.0 128b/132b */ 135 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 136 int lane) 137 { 138 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 139 int s = ((lane & 1) ? 140 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : 141 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); 142 u8 l = dp_link_status(link_status, i); 143 144 return (l >> s) & 0xf; 145 } 146 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); 147 148 /* DP 2.0 errata for 128b/132b */ 149 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 150 int lane_count) 151 { 152 u8 lane_align, lane_status; 153 int lane; 154 155 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 156 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 157 return false; 158 159 for (lane = 0; lane < lane_count; lane++) { 160 lane_status = dp_get_lane_status(link_status, lane); 161 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE)) 162 return false; 163 } 164 return true; 165 } 166 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done); 167 168 /* DP 2.0 errata for 128b/132b */ 169 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 170 int lane_count) 171 { 172 u8 lane_status; 173 int lane; 174 175 for (lane = 0; lane < lane_count; lane++) { 176 lane_status = dp_get_lane_status(link_status, lane); 177 if (!(lane_status & DP_LANE_SYMBOL_LOCKED)) 178 return false; 179 } 180 return true; 181 } 182 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked); 183 184 /* DP 2.0 errata for 128b/132b */ 185 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 186 { 187 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 188 189 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE; 190 } 191 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done); 192 193 /* DP 2.0 errata for 128b/132b */ 194 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 195 { 196 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 197 198 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE; 199 } 200 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done); 201 202 /* DP 2.0 errata for 128b/132b */ 203 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) 204 { 205 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 206 207 return status & DP_128B132B_LT_FAILED; 208 } 209 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed); 210 211 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 212 { 213 if (rd_interval > 4) 214 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 215 aux->name, rd_interval); 216 217 if (rd_interval == 0) 218 return 100; 219 220 return rd_interval * 4 * USEC_PER_MSEC; 221 } 222 223 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 224 { 225 if (rd_interval > 4) 226 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 227 aux->name, rd_interval); 228 229 if (rd_interval == 0) 230 return 400; 231 232 return rd_interval * 4 * USEC_PER_MSEC; 233 } 234 235 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 236 { 237 switch (rd_interval) { 238 default: 239 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", 240 aux->name, rd_interval); 241 fallthrough; 242 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US: 243 return 400; 244 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS: 245 return 4000; 246 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS: 247 return 8000; 248 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS: 249 return 12000; 250 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS: 251 return 16000; 252 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS: 253 return 32000; 254 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS: 255 return 64000; 256 } 257 } 258 259 /* 260 * The link training delays are different for: 261 * 262 * - Clock recovery vs. channel equalization 263 * - DPRX vs. LTTPR 264 * - 128b/132b vs. 8b/10b 265 * - DPCD rev 1.3 vs. later 266 * 267 * Get the correct delay in us, reading DPCD if necessary. 268 */ 269 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 270 enum drm_dp_phy dp_phy, bool uhbr, bool cr) 271 { 272 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); 273 unsigned int offset; 274 u8 rd_interval, mask; 275 276 if (dp_phy == DP_PHY_DPRX) { 277 if (uhbr) { 278 if (cr) 279 return 100; 280 281 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL; 282 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 283 parse = __128b132b_channel_eq_delay_us; 284 } else { 285 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 286 return 100; 287 288 offset = DP_TRAINING_AUX_RD_INTERVAL; 289 mask = DP_TRAINING_AUX_RD_MASK; 290 if (cr) 291 parse = __8b10b_clock_recovery_delay_us; 292 else 293 parse = __8b10b_channel_eq_delay_us; 294 } 295 } else { 296 if (uhbr) { 297 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 298 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 299 parse = __128b132b_channel_eq_delay_us; 300 } else { 301 if (cr) 302 return 100; 303 304 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 305 mask = DP_TRAINING_AUX_RD_MASK; 306 parse = __8b10b_channel_eq_delay_us; 307 } 308 } 309 310 if (offset < DP_RECEIVER_CAP_SIZE) { 311 rd_interval = dpcd[offset]; 312 } else { 313 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { 314 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", 315 aux->name); 316 /* arbitrary default delay */ 317 return 400; 318 } 319 } 320 321 return parse(aux, rd_interval & mask); 322 } 323 324 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 325 enum drm_dp_phy dp_phy, bool uhbr) 326 { 327 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 328 } 329 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay); 330 331 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 332 enum drm_dp_phy dp_phy, bool uhbr) 333 { 334 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 335 } 336 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); 337 338 /* Per DP 2.0 Errata */ 339 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) 340 { 341 int unit; 342 u8 val; 343 344 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { 345 drm_err(aux->drm_dev, "%s: failed rd interval read\n", 346 aux->name); 347 /* default to max */ 348 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 349 } 350 351 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; 352 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 353 354 return (val + 1) * unit * 1000; 355 } 356 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); 357 358 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 359 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 360 { 361 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 362 DP_TRAINING_AUX_RD_MASK; 363 int delay_us; 364 365 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 366 delay_us = 100; 367 else 368 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); 369 370 usleep_range(delay_us, delay_us * 2); 371 } 372 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 373 374 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 375 u8 rd_interval) 376 { 377 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); 378 379 usleep_range(delay_us, delay_us * 2); 380 } 381 382 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 383 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 384 { 385 __drm_dp_link_train_channel_eq_delay(aux, 386 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 387 DP_TRAINING_AUX_RD_MASK); 388 } 389 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 390 391 void drm_dp_lttpr_link_train_clock_recovery_delay(void) 392 { 393 usleep_range(100, 200); 394 } 395 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); 396 397 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) 398 { 399 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; 400 } 401 402 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 403 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) 404 { 405 u8 interval = dp_lttpr_phy_cap(phy_cap, 406 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & 407 DP_TRAINING_AUX_RD_MASK; 408 409 __drm_dp_link_train_channel_eq_delay(aux, interval); 410 } 411 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 412 413 u8 drm_dp_link_rate_to_bw_code(int link_rate) 414 { 415 switch (link_rate) { 416 case 1000000: 417 return DP_LINK_BW_10; 418 case 1350000: 419 return DP_LINK_BW_13_5; 420 case 2000000: 421 return DP_LINK_BW_20; 422 default: 423 /* Spec says link_bw = link_rate / 0.27Gbps */ 424 return link_rate / 27000; 425 } 426 } 427 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 428 429 int drm_dp_bw_code_to_link_rate(u8 link_bw) 430 { 431 switch (link_bw) { 432 case DP_LINK_BW_10: 433 return 1000000; 434 case DP_LINK_BW_13_5: 435 return 1350000; 436 case DP_LINK_BW_20: 437 return 2000000; 438 default: 439 /* Spec says link_rate = link_bw * 0.27Gbps */ 440 return link_bw * 27000; 441 } 442 } 443 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 444 445 #define AUX_RETRY_INTERVAL 500 /* us */ 446 447 static inline void 448 drm_dp_dump_access(const struct drm_dp_aux *aux, 449 u8 request, uint offset, void *buffer, int ret) 450 { 451 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 452 453 if (ret > 0) 454 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 455 aux->name, offset, arrow, ret, min(ret, 20), buffer); 456 else 457 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", 458 aux->name, offset, arrow, ret); 459 } 460 461 /** 462 * DOC: dp helpers 463 * 464 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 465 * independent access to AUX functionality. Drivers can take advantage of 466 * this by filling in the fields of the drm_dp_aux structure. 467 * 468 * Transactions are described using a hardware-independent drm_dp_aux_msg 469 * structure, which is passed into a driver's .transfer() implementation. 470 * Both native and I2C-over-AUX transactions are supported. 471 */ 472 473 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 474 unsigned int offset, void *buffer, size_t size) 475 { 476 struct drm_dp_aux_msg msg; 477 unsigned int retry, native_reply; 478 int err = 0, ret = 0; 479 480 memset(&msg, 0, sizeof(msg)); 481 msg.address = offset; 482 msg.request = request; 483 msg.buffer = buffer; 484 msg.size = size; 485 486 mutex_lock(&aux->hw_mutex); 487 488 /* 489 * The specification doesn't give any recommendation on how often to 490 * retry native transactions. We used to retry 7 times like for 491 * aux i2c transactions but real world devices this wasn't 492 * sufficient, bump to 32 which makes Dell 4k monitors happier. 493 */ 494 for (retry = 0; retry < 32; retry++) { 495 if (ret != 0 && ret != -ETIMEDOUT) { 496 usleep_range(AUX_RETRY_INTERVAL, 497 AUX_RETRY_INTERVAL + 100); 498 } 499 500 ret = aux->transfer(aux, &msg); 501 if (ret >= 0) { 502 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 503 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 504 if (ret == size) 505 goto unlock; 506 507 ret = -EPROTO; 508 } else 509 ret = -EIO; 510 } 511 512 /* 513 * We want the error we return to be the error we received on 514 * the first transaction, since we may get a different error the 515 * next time we retry 516 */ 517 if (!err) 518 err = ret; 519 } 520 521 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", 522 aux->name, err); 523 ret = err; 524 525 unlock: 526 mutex_unlock(&aux->hw_mutex); 527 return ret; 528 } 529 530 /** 531 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access 532 * @aux: DisplayPort AUX channel (SST) 533 * @offset: address of the register to probe 534 * 535 * Probe the provided DPCD address by reading 1 byte from it. The function can 536 * be used to trigger some side-effect the read access has, like waking up the 537 * sink, without the need for the read-out value. 538 * 539 * Returns 0 if the read access suceeded, or a negative error code on failure. 540 */ 541 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) 542 { 543 u8 buffer; 544 int ret; 545 546 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); 547 WARN_ON(ret == 0); 548 549 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); 550 551 return ret < 0 ? ret : 0; 552 } 553 EXPORT_SYMBOL(drm_dp_dpcd_probe); 554 555 /** 556 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 557 * @aux: DisplayPort AUX channel (SST or MST) 558 * @offset: address of the (first) register to read 559 * @buffer: buffer to store the register values 560 * @size: number of bytes in @buffer 561 * 562 * Returns the number of bytes transferred on success, or a negative error 563 * code on failure. -EIO is returned if the request was NAKed by the sink or 564 * if the retry count was exceeded. If not all bytes were transferred, this 565 * function returns -EPROTO. Errors from the underlying AUX channel transfer 566 * function, with the exception of -EBUSY (which causes the transaction to 567 * be retried), are propagated to the caller. 568 */ 569 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 570 void *buffer, size_t size) 571 { 572 int ret; 573 574 /* 575 * HP ZR24w corrupts the first DPCD access after entering power save 576 * mode. Eg. on a read, the entire buffer will be filled with the same 577 * byte. Do a throw away read to avoid corrupting anything we care 578 * about. Afterwards things will work correctly until the monitor 579 * gets woken up and subsequently re-enters power save mode. 580 * 581 * The user pressing any button on the monitor is enough to wake it 582 * up, so there is no particularly good place to do the workaround. 583 * We just have to do it before any DPCD access and hope that the 584 * monitor doesn't power down exactly after the throw away read. 585 */ 586 if (!aux->is_remote) { 587 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); 588 if (ret < 0) 589 return ret; 590 } 591 592 if (aux->is_remote) 593 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 594 else 595 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 596 buffer, size); 597 598 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 599 return ret; 600 } 601 EXPORT_SYMBOL(drm_dp_dpcd_read); 602 603 /** 604 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 605 * @aux: DisplayPort AUX channel (SST or MST) 606 * @offset: address of the (first) register to write 607 * @buffer: buffer containing the values to write 608 * @size: number of bytes in @buffer 609 * 610 * Returns the number of bytes transferred on success, or a negative error 611 * code on failure. -EIO is returned if the request was NAKed by the sink or 612 * if the retry count was exceeded. If not all bytes were transferred, this 613 * function returns -EPROTO. Errors from the underlying AUX channel transfer 614 * function, with the exception of -EBUSY (which causes the transaction to 615 * be retried), are propagated to the caller. 616 */ 617 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 618 void *buffer, size_t size) 619 { 620 int ret; 621 622 if (aux->is_remote) 623 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 624 else 625 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 626 buffer, size); 627 628 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 629 return ret; 630 } 631 EXPORT_SYMBOL(drm_dp_dpcd_write); 632 633 /** 634 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 635 * @aux: DisplayPort AUX channel 636 * @status: buffer to store the link status in (must be at least 6 bytes) 637 * 638 * Returns the number of bytes transferred on success or a negative error 639 * code on failure. 640 */ 641 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 642 u8 status[DP_LINK_STATUS_SIZE]) 643 { 644 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 645 DP_LINK_STATUS_SIZE); 646 } 647 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 648 649 /** 650 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY 651 * @aux: DisplayPort AUX channel 652 * @dp_phy: the DP PHY to get the link status for 653 * @link_status: buffer to return the status in 654 * 655 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The 656 * layout of the returned @link_status matches the DPCD register layout of the 657 * DPRX PHY link status. 658 * 659 * Returns 0 if the information was read successfully or a negative error code 660 * on failure. 661 */ 662 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 663 enum drm_dp_phy dp_phy, 664 u8 link_status[DP_LINK_STATUS_SIZE]) 665 { 666 int ret; 667 668 if (dp_phy == DP_PHY_DPRX) { 669 ret = drm_dp_dpcd_read(aux, 670 DP_LANE0_1_STATUS, 671 link_status, 672 DP_LINK_STATUS_SIZE); 673 674 if (ret < 0) 675 return ret; 676 677 WARN_ON(ret != DP_LINK_STATUS_SIZE); 678 679 return 0; 680 } 681 682 ret = drm_dp_dpcd_read(aux, 683 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), 684 link_status, 685 DP_LINK_STATUS_SIZE - 1); 686 687 if (ret < 0) 688 return ret; 689 690 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); 691 692 /* Convert the LTTPR to the sink PHY link status layout */ 693 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], 694 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], 695 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); 696 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; 697 698 return 0; 699 } 700 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 701 702 static bool is_edid_digital_input_dp(const struct edid *edid) 703 { 704 return edid && edid->revision >= 4 && 705 edid->input & DRM_EDID_INPUT_DIGITAL && 706 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 707 } 708 709 /** 710 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 711 * @dpcd: DisplayPort configuration data 712 * @port_cap: port capabilities 713 * @type: port type to be checked. Can be: 714 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 715 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 716 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 717 * 718 * Caveat: Only works with DPCD 1.1+ port caps. 719 * 720 * Returns: whether the downstream facing port matches the type. 721 */ 722 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 723 const u8 port_cap[4], u8 type) 724 { 725 return drm_dp_is_branch(dpcd) && 726 dpcd[DP_DPCD_REV] >= 0x11 && 727 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 728 } 729 EXPORT_SYMBOL(drm_dp_downstream_is_type); 730 731 /** 732 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 733 * @dpcd: DisplayPort configuration data 734 * @port_cap: port capabilities 735 * @edid: EDID 736 * 737 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 738 */ 739 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 740 const u8 port_cap[4], 741 const struct edid *edid) 742 { 743 if (dpcd[DP_DPCD_REV] < 0x11) { 744 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 745 case DP_DWN_STRM_PORT_TYPE_TMDS: 746 return true; 747 default: 748 return false; 749 } 750 } 751 752 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 753 case DP_DS_PORT_TYPE_DP_DUALMODE: 754 if (is_edid_digital_input_dp(edid)) 755 return false; 756 fallthrough; 757 case DP_DS_PORT_TYPE_DVI: 758 case DP_DS_PORT_TYPE_HDMI: 759 return true; 760 default: 761 return false; 762 } 763 } 764 EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 765 766 /** 767 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 768 * @aux: DisplayPort AUX channel 769 * @real_edid_checksum: real edid checksum for the last block 770 * 771 * Returns: 772 * True on success 773 */ 774 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 775 u8 real_edid_checksum) 776 { 777 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 778 779 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 780 &auto_test_req, 1) < 1) { 781 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 782 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 783 return false; 784 } 785 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 786 787 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 788 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 789 aux->name, DP_TEST_REQUEST); 790 return false; 791 } 792 link_edid_read &= DP_TEST_LINK_EDID_READ; 793 794 if (!auto_test_req || !link_edid_read) { 795 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", 796 aux->name); 797 return false; 798 } 799 800 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 801 &auto_test_req, 1) < 1) { 802 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 803 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 804 return false; 805 } 806 807 /* send back checksum for the last edid extension block data */ 808 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 809 &real_edid_checksum, 1) < 1) { 810 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 811 aux->name, DP_TEST_EDID_CHECKSUM); 812 return false; 813 } 814 815 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 816 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 817 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 818 aux->name, DP_TEST_RESPONSE); 819 return false; 820 } 821 822 return true; 823 } 824 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 825 826 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 827 { 828 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 829 830 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 831 port_count = 4; 832 833 return port_count; 834 } 835 836 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 837 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 838 { 839 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; 840 int ret; 841 842 /* 843 * Prior to DP1.3 the bit represented by 844 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 845 * If it is set DP_DPCD_REV at 0000h could be at a value less than 846 * the true capability of the panel. The only way to check is to 847 * then compare 0000h and 2200h. 848 */ 849 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 850 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 851 return 0; 852 853 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 854 sizeof(dpcd_ext)); 855 if (ret < 0) 856 return ret; 857 if (ret != sizeof(dpcd_ext)) 858 return -EIO; 859 860 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 861 drm_dbg_kms(aux->drm_dev, 862 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 863 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 864 return 0; 865 } 866 867 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 868 return 0; 869 870 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 871 872 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 873 874 return 0; 875 } 876 877 /** 878 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 879 * available 880 * @aux: DisplayPort AUX channel 881 * @dpcd: Buffer to store the resulting DPCD in 882 * 883 * Attempts to read the base DPCD caps for @aux. Additionally, this function 884 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 885 * present. 886 * 887 * Returns: %0 if the DPCD was read successfully, negative error code 888 * otherwise. 889 */ 890 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 891 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 892 { 893 int ret; 894 895 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 896 if (ret < 0) 897 return ret; 898 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 899 return -EIO; 900 901 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 902 if (ret < 0) 903 return ret; 904 905 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 906 907 return ret; 908 } 909 EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 910 911 /** 912 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 913 * @aux: DisplayPort AUX channel 914 * @dpcd: A cached copy of the port's DPCD 915 * @downstream_ports: buffer to store the downstream port info in 916 * 917 * See also: 918 * drm_dp_downstream_max_clock() 919 * drm_dp_downstream_max_bpc() 920 * 921 * Returns: 0 if either the downstream port info was read successfully or 922 * there was no downstream info to read, or a negative error code otherwise. 923 */ 924 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 925 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 926 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 927 { 928 int ret; 929 u8 len; 930 931 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 932 933 /* No downstream info to read */ 934 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) 935 return 0; 936 937 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 938 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 939 * some branches do it we need to handle it regardless. 940 */ 941 len = drm_dp_downstream_port_count(dpcd); 942 if (!len) 943 return 0; 944 945 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 946 len *= 4; 947 948 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 949 if (ret < 0) 950 return ret; 951 if (ret != len) 952 return -EIO; 953 954 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); 955 956 return 0; 957 } 958 EXPORT_SYMBOL(drm_dp_read_downstream_info); 959 960 /** 961 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 962 * @dpcd: DisplayPort configuration data 963 * @port_cap: port capabilities 964 * 965 * Returns: Downstream facing port max dot clock in kHz on success, 966 * or 0 if max clock not defined 967 */ 968 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 969 const u8 port_cap[4]) 970 { 971 if (!drm_dp_is_branch(dpcd)) 972 return 0; 973 974 if (dpcd[DP_DPCD_REV] < 0x11) 975 return 0; 976 977 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 978 case DP_DS_PORT_TYPE_VGA: 979 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 980 return 0; 981 return port_cap[1] * 8000; 982 default: 983 return 0; 984 } 985 } 986 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 987 988 /** 989 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 990 * @dpcd: DisplayPort configuration data 991 * @port_cap: port capabilities 992 * @edid: EDID 993 * 994 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 995 * or 0 if max TMDS clock not defined 996 */ 997 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 998 const u8 port_cap[4], 999 const struct edid *edid) 1000 { 1001 if (!drm_dp_is_branch(dpcd)) 1002 return 0; 1003 1004 if (dpcd[DP_DPCD_REV] < 0x11) { 1005 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1006 case DP_DWN_STRM_PORT_TYPE_TMDS: 1007 return 165000; 1008 default: 1009 return 0; 1010 } 1011 } 1012 1013 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1014 case DP_DS_PORT_TYPE_DP_DUALMODE: 1015 if (is_edid_digital_input_dp(edid)) 1016 return 0; 1017 /* 1018 * It's left up to the driver to check the 1019 * DP dual mode adapter's max TMDS clock. 1020 * 1021 * Unfortunately it looks like branch devices 1022 * may not fordward that the DP dual mode i2c 1023 * access so we just usually get i2c nak :( 1024 */ 1025 fallthrough; 1026 case DP_DS_PORT_TYPE_HDMI: 1027 /* 1028 * We should perhaps assume 165 MHz when detailed cap 1029 * info is not available. But looks like many typical 1030 * branch devices fall into that category and so we'd 1031 * probably end up with users complaining that they can't 1032 * get high resolution modes with their favorite dongle. 1033 * 1034 * So let's limit to 300 MHz instead since DPCD 1.4 1035 * HDMI 2.0 DFPs are required to have the detailed cap 1036 * info. So it's more likely we're dealing with a HDMI 1.4 1037 * compatible* device here. 1038 */ 1039 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1040 return 300000; 1041 return port_cap[1] * 2500; 1042 case DP_DS_PORT_TYPE_DVI: 1043 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1044 return 165000; 1045 /* FIXME what to do about DVI dual link? */ 1046 return port_cap[1] * 2500; 1047 default: 1048 return 0; 1049 } 1050 } 1051 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 1052 1053 /** 1054 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1055 * @dpcd: DisplayPort configuration data 1056 * @port_cap: port capabilities 1057 * @edid: EDID 1058 * 1059 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1060 * or 0 if max TMDS clock not defined 1061 */ 1062 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1063 const u8 port_cap[4], 1064 const struct edid *edid) 1065 { 1066 if (!drm_dp_is_branch(dpcd)) 1067 return 0; 1068 1069 if (dpcd[DP_DPCD_REV] < 0x11) { 1070 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1071 case DP_DWN_STRM_PORT_TYPE_TMDS: 1072 return 25000; 1073 default: 1074 return 0; 1075 } 1076 } 1077 1078 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1079 case DP_DS_PORT_TYPE_DP_DUALMODE: 1080 if (is_edid_digital_input_dp(edid)) 1081 return 0; 1082 fallthrough; 1083 case DP_DS_PORT_TYPE_DVI: 1084 case DP_DS_PORT_TYPE_HDMI: 1085 /* 1086 * Unclear whether the protocol converter could 1087 * utilize pixel replication. Assume it won't. 1088 */ 1089 return 25000; 1090 default: 1091 return 0; 1092 } 1093 } 1094 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 1095 1096 /** 1097 * drm_dp_downstream_max_bpc() - extract downstream facing port max 1098 * bits per component 1099 * @dpcd: DisplayPort configuration data 1100 * @port_cap: downstream facing port capabilities 1101 * @edid: EDID 1102 * 1103 * Returns: Max bpc on success or 0 if max bpc not defined 1104 */ 1105 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1106 const u8 port_cap[4], 1107 const struct edid *edid) 1108 { 1109 if (!drm_dp_is_branch(dpcd)) 1110 return 0; 1111 1112 if (dpcd[DP_DPCD_REV] < 0x11) { 1113 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1114 case DP_DWN_STRM_PORT_TYPE_DP: 1115 return 0; 1116 default: 1117 return 8; 1118 } 1119 } 1120 1121 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1122 case DP_DS_PORT_TYPE_DP: 1123 return 0; 1124 case DP_DS_PORT_TYPE_DP_DUALMODE: 1125 if (is_edid_digital_input_dp(edid)) 1126 return 0; 1127 fallthrough; 1128 case DP_DS_PORT_TYPE_HDMI: 1129 case DP_DS_PORT_TYPE_DVI: 1130 case DP_DS_PORT_TYPE_VGA: 1131 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1132 return 8; 1133 1134 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 1135 case DP_DS_8BPC: 1136 return 8; 1137 case DP_DS_10BPC: 1138 return 10; 1139 case DP_DS_12BPC: 1140 return 12; 1141 case DP_DS_16BPC: 1142 return 16; 1143 default: 1144 return 8; 1145 } 1146 break; 1147 default: 1148 return 8; 1149 } 1150 } 1151 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 1152 1153 /** 1154 * drm_dp_downstream_420_passthrough() - determine downstream facing port 1155 * YCbCr 4:2:0 pass-through capability 1156 * @dpcd: DisplayPort configuration data 1157 * @port_cap: downstream facing port capabilities 1158 * 1159 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 1160 */ 1161 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1162 const u8 port_cap[4]) 1163 { 1164 if (!drm_dp_is_branch(dpcd)) 1165 return false; 1166 1167 if (dpcd[DP_DPCD_REV] < 0x13) 1168 return false; 1169 1170 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1171 case DP_DS_PORT_TYPE_DP: 1172 return true; 1173 case DP_DS_PORT_TYPE_HDMI: 1174 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1175 return false; 1176 1177 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 1178 default: 1179 return false; 1180 } 1181 } 1182 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 1183 1184 /** 1185 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 1186 * YCbCr 4:4:4->4:2:0 conversion capability 1187 * @dpcd: DisplayPort configuration data 1188 * @port_cap: downstream facing port capabilities 1189 * 1190 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 1191 */ 1192 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1193 const u8 port_cap[4]) 1194 { 1195 if (!drm_dp_is_branch(dpcd)) 1196 return false; 1197 1198 if (dpcd[DP_DPCD_REV] < 0x13) 1199 return false; 1200 1201 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1202 case DP_DS_PORT_TYPE_HDMI: 1203 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1204 return false; 1205 1206 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 1207 default: 1208 return false; 1209 } 1210 } 1211 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 1212 1213 /** 1214 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port 1215 * RGB->YCbCr conversion capability 1216 * @dpcd: DisplayPort configuration data 1217 * @port_cap: downstream facing port capabilities 1218 * @color_spc: Colorspace for which conversion cap is sought 1219 * 1220 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given 1221 * colorspace. 1222 */ 1223 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1224 const u8 port_cap[4], 1225 u8 color_spc) 1226 { 1227 if (!drm_dp_is_branch(dpcd)) 1228 return false; 1229 1230 if (dpcd[DP_DPCD_REV] < 0x13) 1231 return false; 1232 1233 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1234 case DP_DS_PORT_TYPE_HDMI: 1235 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1236 return false; 1237 1238 return port_cap[3] & color_spc; 1239 default: 1240 return false; 1241 } 1242 } 1243 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion); 1244 1245 /** 1246 * drm_dp_downstream_mode() - return a mode for downstream facing port 1247 * @dev: DRM device 1248 * @dpcd: DisplayPort configuration data 1249 * @port_cap: port capabilities 1250 * 1251 * Provides a suitable mode for downstream facing ports without EDID. 1252 * 1253 * Returns: A new drm_display_mode on success or NULL on failure 1254 */ 1255 struct drm_display_mode * 1256 drm_dp_downstream_mode(struct drm_device *dev, 1257 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1258 const u8 port_cap[4]) 1259 1260 { 1261 u8 vic; 1262 1263 if (!drm_dp_is_branch(dpcd)) 1264 return NULL; 1265 1266 if (dpcd[DP_DPCD_REV] < 0x11) 1267 return NULL; 1268 1269 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1270 case DP_DS_PORT_TYPE_NON_EDID: 1271 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 1272 case DP_DS_NON_EDID_720x480i_60: 1273 vic = 6; 1274 break; 1275 case DP_DS_NON_EDID_720x480i_50: 1276 vic = 21; 1277 break; 1278 case DP_DS_NON_EDID_1920x1080i_60: 1279 vic = 5; 1280 break; 1281 case DP_DS_NON_EDID_1920x1080i_50: 1282 vic = 20; 1283 break; 1284 case DP_DS_NON_EDID_1280x720_60: 1285 vic = 4; 1286 break; 1287 case DP_DS_NON_EDID_1280x720_50: 1288 vic = 19; 1289 break; 1290 default: 1291 return NULL; 1292 } 1293 return drm_display_mode_from_cea_vic(dev, vic); 1294 default: 1295 return NULL; 1296 } 1297 } 1298 EXPORT_SYMBOL(drm_dp_downstream_mode); 1299 1300 /** 1301 * drm_dp_downstream_id() - identify branch device 1302 * @aux: DisplayPort AUX channel 1303 * @id: DisplayPort branch device id 1304 * 1305 * Returns branch device id on success or NULL on failure 1306 */ 1307 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 1308 { 1309 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 1310 } 1311 EXPORT_SYMBOL(drm_dp_downstream_id); 1312 1313 /** 1314 * drm_dp_downstream_debug() - debug DP branch devices 1315 * @m: pointer for debugfs file 1316 * @dpcd: DisplayPort configuration data 1317 * @port_cap: port capabilities 1318 * @edid: EDID 1319 * @aux: DisplayPort AUX channel 1320 * 1321 */ 1322 void drm_dp_downstream_debug(struct seq_file *m, 1323 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1324 const u8 port_cap[4], 1325 const struct edid *edid, 1326 struct drm_dp_aux *aux) 1327 { 1328 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1329 DP_DETAILED_CAP_INFO_AVAILABLE; 1330 int clk; 1331 int bpc; 1332 char id[7]; 1333 int len; 1334 uint8_t rev[2]; 1335 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1336 bool branch_device = drm_dp_is_branch(dpcd); 1337 1338 seq_printf(m, "\tDP branch device present: %s\n", 1339 str_yes_no(branch_device)); 1340 1341 if (!branch_device) 1342 return; 1343 1344 switch (type) { 1345 case DP_DS_PORT_TYPE_DP: 1346 seq_puts(m, "\t\tType: DisplayPort\n"); 1347 break; 1348 case DP_DS_PORT_TYPE_VGA: 1349 seq_puts(m, "\t\tType: VGA\n"); 1350 break; 1351 case DP_DS_PORT_TYPE_DVI: 1352 seq_puts(m, "\t\tType: DVI\n"); 1353 break; 1354 case DP_DS_PORT_TYPE_HDMI: 1355 seq_puts(m, "\t\tType: HDMI\n"); 1356 break; 1357 case DP_DS_PORT_TYPE_NON_EDID: 1358 seq_puts(m, "\t\tType: others without EDID support\n"); 1359 break; 1360 case DP_DS_PORT_TYPE_DP_DUALMODE: 1361 seq_puts(m, "\t\tType: DP++\n"); 1362 break; 1363 case DP_DS_PORT_TYPE_WIRELESS: 1364 seq_puts(m, "\t\tType: Wireless\n"); 1365 break; 1366 default: 1367 seq_puts(m, "\t\tType: N/A\n"); 1368 } 1369 1370 memset(id, 0, sizeof(id)); 1371 drm_dp_downstream_id(aux, id); 1372 seq_printf(m, "\t\tID: %s\n", id); 1373 1374 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1375 if (len > 0) 1376 seq_printf(m, "\t\tHW: %d.%d\n", 1377 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1378 1379 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1380 if (len > 0) 1381 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1382 1383 if (detailed_cap_info) { 1384 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1385 if (clk > 0) 1386 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1387 1388 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); 1389 if (clk > 0) 1390 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1391 1392 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); 1393 if (clk > 0) 1394 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1395 1396 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); 1397 1398 if (bpc > 0) 1399 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1400 } 1401 } 1402 EXPORT_SYMBOL(drm_dp_downstream_debug); 1403 1404 /** 1405 * drm_dp_subconnector_type() - get DP branch device type 1406 * @dpcd: DisplayPort configuration data 1407 * @port_cap: port capabilities 1408 */ 1409 enum drm_mode_subconnector 1410 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1411 const u8 port_cap[4]) 1412 { 1413 int type; 1414 if (!drm_dp_is_branch(dpcd)) 1415 return DRM_MODE_SUBCONNECTOR_Native; 1416 /* DP 1.0 approach */ 1417 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1418 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1419 DP_DWN_STRM_PORT_TYPE_MASK; 1420 1421 switch (type) { 1422 case DP_DWN_STRM_PORT_TYPE_TMDS: 1423 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1424 return DRM_MODE_SUBCONNECTOR_DVID; 1425 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1426 /* Can be VGA or DVI-A, VGA is more popular */ 1427 return DRM_MODE_SUBCONNECTOR_VGA; 1428 case DP_DWN_STRM_PORT_TYPE_DP: 1429 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1430 case DP_DWN_STRM_PORT_TYPE_OTHER: 1431 default: 1432 return DRM_MODE_SUBCONNECTOR_Unknown; 1433 } 1434 } 1435 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1436 1437 switch (type) { 1438 case DP_DS_PORT_TYPE_DP: 1439 case DP_DS_PORT_TYPE_DP_DUALMODE: 1440 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1441 case DP_DS_PORT_TYPE_VGA: 1442 return DRM_MODE_SUBCONNECTOR_VGA; 1443 case DP_DS_PORT_TYPE_DVI: 1444 return DRM_MODE_SUBCONNECTOR_DVID; 1445 case DP_DS_PORT_TYPE_HDMI: 1446 return DRM_MODE_SUBCONNECTOR_HDMIA; 1447 case DP_DS_PORT_TYPE_WIRELESS: 1448 return DRM_MODE_SUBCONNECTOR_Wireless; 1449 case DP_DS_PORT_TYPE_NON_EDID: 1450 default: 1451 return DRM_MODE_SUBCONNECTOR_Unknown; 1452 } 1453 } 1454 EXPORT_SYMBOL(drm_dp_subconnector_type); 1455 1456 /** 1457 * drm_dp_set_subconnector_property - set subconnector for DP connector 1458 * @connector: connector to set property on 1459 * @status: connector status 1460 * @dpcd: DisplayPort configuration data 1461 * @port_cap: port capabilities 1462 * 1463 * Called by a driver on every detect event. 1464 */ 1465 void drm_dp_set_subconnector_property(struct drm_connector *connector, 1466 enum drm_connector_status status, 1467 const u8 *dpcd, 1468 const u8 port_cap[4]) 1469 { 1470 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1471 1472 if (status == connector_status_connected) 1473 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1474 drm_object_property_set_value(&connector->base, 1475 connector->dev->mode_config.dp_subconnector_property, 1476 subconnector); 1477 } 1478 EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1479 1480 /** 1481 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1482 * count 1483 * @connector: The DRM connector to check 1484 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1485 * @desc: A cached copy of the connector's DP descriptor 1486 * 1487 * See also: drm_dp_read_sink_count() 1488 * 1489 * Returns: %True if the (e)DP connector has a valid sink count that should 1490 * be probed, %false otherwise. 1491 */ 1492 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1493 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1494 const struct drm_dp_desc *desc) 1495 { 1496 /* Some eDP panels don't set a valid value for the sink count */ 1497 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1498 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1499 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1500 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT); 1501 } 1502 EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1503 1504 /** 1505 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1506 * @aux: The DP AUX channel to use 1507 * 1508 * See also: drm_dp_read_sink_count_cap() 1509 * 1510 * Returns: The current sink count reported by @aux, or a negative error code 1511 * otherwise. 1512 */ 1513 int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1514 { 1515 u8 count; 1516 int ret; 1517 1518 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1519 if (ret < 0) 1520 return ret; 1521 if (ret != 1) 1522 return -EIO; 1523 1524 return DP_GET_SINK_COUNT(count); 1525 } 1526 EXPORT_SYMBOL(drm_dp_read_sink_count); 1527 1528 /* 1529 * I2C-over-AUX implementation 1530 */ 1531 1532 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1533 { 1534 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1535 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1536 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1537 I2C_FUNC_10BIT_ADDR; 1538 } 1539 1540 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1541 { 1542 /* 1543 * In case of i2c defer or short i2c ack reply to a write, 1544 * we need to switch to WRITE_STATUS_UPDATE to drain the 1545 * rest of the message 1546 */ 1547 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1548 msg->request &= DP_AUX_I2C_MOT; 1549 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1550 } 1551 } 1552 1553 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1554 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1555 #define AUX_STOP_LEN 4 1556 #define AUX_CMD_LEN 4 1557 #define AUX_ADDRESS_LEN 20 1558 #define AUX_REPLY_PAD_LEN 4 1559 #define AUX_LENGTH_LEN 8 1560 1561 /* 1562 * Calculate the duration of the AUX request/reply in usec. Gives the 1563 * "best" case estimate, ie. successful while as short as possible. 1564 */ 1565 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1566 { 1567 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1568 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1569 1570 if ((msg->request & DP_AUX_I2C_READ) == 0) 1571 len += msg->size * 8; 1572 1573 return len; 1574 } 1575 1576 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1577 { 1578 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1579 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1580 1581 /* 1582 * For read we expect what was asked. For writes there will 1583 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1584 */ 1585 if (msg->request & DP_AUX_I2C_READ) 1586 len += msg->size * 8; 1587 1588 return len; 1589 } 1590 1591 #define I2C_START_LEN 1 1592 #define I2C_STOP_LEN 1 1593 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1594 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1595 1596 /* 1597 * Calculate the length of the i2c transfer in usec, assuming 1598 * the i2c bus speed is as specified. Gives the the "worst" 1599 * case estimate, ie. successful while as long as possible. 1600 * Doesn't account the the "MOT" bit, and instead assumes each 1601 * message includes a START, ADDRESS and STOP. Neither does it 1602 * account for additional random variables such as clock stretching. 1603 */ 1604 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1605 int i2c_speed_khz) 1606 { 1607 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1608 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1609 msg->size * I2C_DATA_LEN + 1610 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1611 } 1612 1613 /* 1614 * Determine how many retries should be attempted to successfully transfer 1615 * the specified message, based on the estimated durations of the 1616 * i2c and AUX transfers. 1617 */ 1618 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1619 int i2c_speed_khz) 1620 { 1621 int aux_time_us = drm_dp_aux_req_duration(msg) + 1622 drm_dp_aux_reply_duration(msg); 1623 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1624 1625 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1626 } 1627 1628 /* 1629 * FIXME currently assumes 10 kHz as some real world devices seem 1630 * to require it. We should query/set the speed via DPCD if supported. 1631 */ 1632 static int dp_aux_i2c_speed_khz __read_mostly = 10; 1633 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1634 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1635 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1636 1637 /* 1638 * Transfer a single I2C-over-AUX message and handle various error conditions, 1639 * retrying the transaction as appropriate. It is assumed that the 1640 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1641 * reply field. 1642 * 1643 * Returns bytes transferred on success, or a negative error code on failure. 1644 */ 1645 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1646 { 1647 unsigned int retry, defer_i2c; 1648 int ret; 1649 /* 1650 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1651 * is required to retry at least seven times upon receiving AUX_DEFER 1652 * before giving up the AUX transaction. 1653 * 1654 * We also try to account for the i2c bus speed. 1655 */ 1656 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1657 1658 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1659 ret = aux->transfer(aux, msg); 1660 if (ret < 0) { 1661 if (ret == -EBUSY) 1662 continue; 1663 1664 /* 1665 * While timeouts can be errors, they're usually normal 1666 * behavior (for instance, when a driver tries to 1667 * communicate with a non-existent DisplayPort device). 1668 * Avoid spamming the kernel log with timeout errors. 1669 */ 1670 if (ret == -ETIMEDOUT) 1671 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", 1672 aux->name); 1673 else 1674 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", 1675 aux->name, ret); 1676 return ret; 1677 } 1678 1679 1680 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1681 case DP_AUX_NATIVE_REPLY_ACK: 1682 /* 1683 * For I2C-over-AUX transactions this isn't enough, we 1684 * need to check for the I2C ACK reply. 1685 */ 1686 break; 1687 1688 case DP_AUX_NATIVE_REPLY_NACK: 1689 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", 1690 aux->name, ret, msg->size); 1691 return -EREMOTEIO; 1692 1693 case DP_AUX_NATIVE_REPLY_DEFER: 1694 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); 1695 /* 1696 * We could check for I2C bit rate capabilities and if 1697 * available adjust this interval. We could also be 1698 * more careful with DP-to-legacy adapters where a 1699 * long legacy cable may force very low I2C bit rates. 1700 * 1701 * For now just defer for long enough to hopefully be 1702 * safe for all use-cases. 1703 */ 1704 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1705 continue; 1706 1707 default: 1708 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", 1709 aux->name, msg->reply); 1710 return -EREMOTEIO; 1711 } 1712 1713 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1714 case DP_AUX_I2C_REPLY_ACK: 1715 /* 1716 * Both native ACK and I2C ACK replies received. We 1717 * can assume the transfer was successful. 1718 */ 1719 if (ret != msg->size) 1720 drm_dp_i2c_msg_write_status_update(msg); 1721 return ret; 1722 1723 case DP_AUX_I2C_REPLY_NACK: 1724 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", 1725 aux->name, ret, msg->size); 1726 aux->i2c_nack_count++; 1727 return -EREMOTEIO; 1728 1729 case DP_AUX_I2C_REPLY_DEFER: 1730 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); 1731 /* DP Compliance Test 4.2.2.5 Requirement: 1732 * Must have at least 7 retries for I2C defers on the 1733 * transaction to pass this test 1734 */ 1735 aux->i2c_defer_count++; 1736 if (defer_i2c < 7) 1737 defer_i2c++; 1738 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1739 drm_dp_i2c_msg_write_status_update(msg); 1740 1741 continue; 1742 1743 default: 1744 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", 1745 aux->name, msg->reply); 1746 return -EREMOTEIO; 1747 } 1748 } 1749 1750 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); 1751 return -EREMOTEIO; 1752 } 1753 1754 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 1755 const struct i2c_msg *i2c_msg) 1756 { 1757 msg->request = (i2c_msg->flags & I2C_M_RD) ? 1758 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 1759 if (!(i2c_msg->flags & I2C_M_STOP)) 1760 msg->request |= DP_AUX_I2C_MOT; 1761 } 1762 1763 /* 1764 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 1765 * 1766 * Returns an error code on failure, or a recommended transfer size on success. 1767 */ 1768 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 1769 { 1770 int err, ret = orig_msg->size; 1771 struct drm_dp_aux_msg msg = *orig_msg; 1772 1773 while (msg.size > 0) { 1774 err = drm_dp_i2c_do_msg(aux, &msg); 1775 if (err <= 0) 1776 return err == 0 ? -EPROTO : err; 1777 1778 if (err < msg.size && err < ret) { 1779 drm_dbg_kms(aux->drm_dev, 1780 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 1781 aux->name, msg.size, err); 1782 ret = err; 1783 } 1784 1785 msg.size -= err; 1786 msg.buffer += err; 1787 } 1788 1789 return ret; 1790 } 1791 1792 /* 1793 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 1794 * packets to be as large as possible. If not, the I2C transactions never 1795 * succeed. Hence the default is maximum. 1796 */ 1797 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 1798 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 1799 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 1800 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 1801 1802 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 1803 int num) 1804 { 1805 struct drm_dp_aux *aux = adapter->algo_data; 1806 unsigned int i, j; 1807 unsigned transfer_size; 1808 struct drm_dp_aux_msg msg; 1809 int err = 0; 1810 1811 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 1812 1813 memset(&msg, 0, sizeof(msg)); 1814 1815 for (i = 0; i < num; i++) { 1816 msg.address = msgs[i].addr; 1817 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1818 /* Send a bare address packet to start the transaction. 1819 * Zero sized messages specify an address only (bare 1820 * address) transaction. 1821 */ 1822 msg.buffer = NULL; 1823 msg.size = 0; 1824 err = drm_dp_i2c_do_msg(aux, &msg); 1825 1826 /* 1827 * Reset msg.request in case in case it got 1828 * changed into a WRITE_STATUS_UPDATE. 1829 */ 1830 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1831 1832 if (err < 0) 1833 break; 1834 /* We want each transaction to be as large as possible, but 1835 * we'll go to smaller sizes if the hardware gives us a 1836 * short reply. 1837 */ 1838 transfer_size = dp_aux_i2c_transfer_size; 1839 for (j = 0; j < msgs[i].len; j += msg.size) { 1840 msg.buffer = msgs[i].buf + j; 1841 msg.size = min(transfer_size, msgs[i].len - j); 1842 1843 err = drm_dp_i2c_drain_msg(aux, &msg); 1844 1845 /* 1846 * Reset msg.request in case in case it got 1847 * changed into a WRITE_STATUS_UPDATE. 1848 */ 1849 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1850 1851 if (err < 0) 1852 break; 1853 transfer_size = err; 1854 } 1855 if (err < 0) 1856 break; 1857 } 1858 if (err >= 0) 1859 err = num; 1860 /* Send a bare address packet to close out the transaction. 1861 * Zero sized messages specify an address only (bare 1862 * address) transaction. 1863 */ 1864 msg.request &= ~DP_AUX_I2C_MOT; 1865 msg.buffer = NULL; 1866 msg.size = 0; 1867 (void)drm_dp_i2c_do_msg(aux, &msg); 1868 1869 return err; 1870 } 1871 1872 static const struct i2c_algorithm drm_dp_i2c_algo = { 1873 .functionality = drm_dp_i2c_functionality, 1874 .master_xfer = drm_dp_i2c_xfer, 1875 }; 1876 1877 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 1878 { 1879 return container_of(i2c, struct drm_dp_aux, ddc); 1880 } 1881 1882 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 1883 { 1884 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 1885 } 1886 1887 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 1888 { 1889 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 1890 } 1891 1892 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 1893 { 1894 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 1895 } 1896 1897 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 1898 .lock_bus = lock_bus, 1899 .trylock_bus = trylock_bus, 1900 .unlock_bus = unlock_bus, 1901 }; 1902 1903 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 1904 { 1905 u8 buf, count; 1906 int ret; 1907 1908 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1909 if (ret < 0) 1910 return ret; 1911 1912 WARN_ON(!(buf & DP_TEST_SINK_START)); 1913 1914 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 1915 if (ret < 0) 1916 return ret; 1917 1918 count = buf & DP_TEST_COUNT_MASK; 1919 if (count == aux->crc_count) 1920 return -EAGAIN; /* No CRC yet */ 1921 1922 aux->crc_count = count; 1923 1924 /* 1925 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 1926 * per component (RGB or CrYCb). 1927 */ 1928 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 1929 if (ret < 0) 1930 return ret; 1931 1932 return 0; 1933 } 1934 1935 static void drm_dp_aux_crc_work(struct work_struct *work) 1936 { 1937 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 1938 crc_work); 1939 struct drm_crtc *crtc; 1940 u8 crc_bytes[6]; 1941 uint32_t crcs[3]; 1942 int ret; 1943 1944 if (WARN_ON(!aux->crtc)) 1945 return; 1946 1947 crtc = aux->crtc; 1948 while (crtc->crc.opened) { 1949 drm_crtc_wait_one_vblank(crtc); 1950 if (!crtc->crc.opened) 1951 break; 1952 1953 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1954 if (ret == -EAGAIN) { 1955 usleep_range(1000, 2000); 1956 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1957 } 1958 1959 if (ret == -EAGAIN) { 1960 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", 1961 aux->name, ret); 1962 continue; 1963 } else if (ret) { 1964 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); 1965 continue; 1966 } 1967 1968 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 1969 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 1970 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 1971 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 1972 } 1973 } 1974 1975 /** 1976 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 1977 * @aux: DisplayPort AUX channel 1978 * 1979 * Used for remote aux channel in general. Merely initialize the crc work 1980 * struct. 1981 */ 1982 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 1983 { 1984 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 1985 } 1986 EXPORT_SYMBOL(drm_dp_remote_aux_init); 1987 1988 /** 1989 * drm_dp_aux_init() - minimally initialise an aux channel 1990 * @aux: DisplayPort AUX channel 1991 * 1992 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with 1993 * the outside world, call drm_dp_aux_init() first. For drivers which are 1994 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a 1995 * &drm_connector), you must still call drm_dp_aux_register() once the connector 1996 * has been registered to allow userspace access to the auxiliary DP channel. 1997 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as 1998 * early as possible so that the &drm_device that corresponds to the AUX adapter 1999 * may be mentioned in debugging output from the DRM DP helpers. 2000 * 2001 * For devices which use a separate platform device for their AUX adapters, this 2002 * may be called as early as required by the driver. 2003 * 2004 */ 2005 void drm_dp_aux_init(struct drm_dp_aux *aux) 2006 { 2007 mutex_init(&aux->hw_mutex); 2008 mutex_init(&aux->cec.lock); 2009 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2010 2011 aux->ddc.algo = &drm_dp_i2c_algo; 2012 aux->ddc.algo_data = aux; 2013 aux->ddc.retries = 3; 2014 2015 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 2016 } 2017 EXPORT_SYMBOL(drm_dp_aux_init); 2018 2019 /** 2020 * drm_dp_aux_register() - initialise and register aux channel 2021 * @aux: DisplayPort AUX channel 2022 * 2023 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This 2024 * should only be called once the parent of @aux, &drm_dp_aux.dev, is 2025 * initialized. For devices which are grandparents of their AUX channels, 2026 * &drm_dp_aux.dev will typically be the &drm_connector &device which 2027 * corresponds to @aux. For these devices, it's advised to call 2028 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to 2029 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. 2030 * Functions which don't follow this will likely Oops when 2031 * %CONFIG_DRM_DP_AUX_CHARDEV is enabled. 2032 * 2033 * For devices where the AUX channel is a device that exists independently of 2034 * the &drm_device that uses it, such as SoCs and bridge devices, it is 2035 * recommended to call drm_dp_aux_register() after a &drm_device has been 2036 * assigned to &drm_dp_aux.drm_dev, and likewise to call 2037 * drm_dp_aux_unregister() once the &drm_device should no longer be associated 2038 * with the AUX channel (e.g. on bridge detach). 2039 * 2040 * Drivers which need to use the aux channel before either of the two points 2041 * mentioned above need to call drm_dp_aux_init() in order to use the AUX 2042 * channel before registration. 2043 * 2044 * Returns 0 on success or a negative error code on failure. 2045 */ 2046 int drm_dp_aux_register(struct drm_dp_aux *aux) 2047 { 2048 int ret; 2049 2050 WARN_ON_ONCE(!aux->drm_dev); 2051 2052 if (!aux->ddc.algo) 2053 drm_dp_aux_init(aux); 2054 2055 aux->ddc.class = I2C_CLASS_DDC; 2056 aux->ddc.owner = THIS_MODULE; 2057 aux->ddc.dev.parent = aux->dev; 2058 2059 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 2060 sizeof(aux->ddc.name)); 2061 2062 ret = drm_dp_aux_register_devnode(aux); 2063 if (ret) 2064 return ret; 2065 2066 ret = i2c_add_adapter(&aux->ddc); 2067 if (ret) { 2068 drm_dp_aux_unregister_devnode(aux); 2069 return ret; 2070 } 2071 2072 return 0; 2073 } 2074 EXPORT_SYMBOL(drm_dp_aux_register); 2075 2076 /** 2077 * drm_dp_aux_unregister() - unregister an AUX adapter 2078 * @aux: DisplayPort AUX channel 2079 */ 2080 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 2081 { 2082 drm_dp_aux_unregister_devnode(aux); 2083 i2c_del_adapter(&aux->ddc); 2084 } 2085 EXPORT_SYMBOL(drm_dp_aux_unregister); 2086 2087 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 2088 2089 /** 2090 * drm_dp_psr_setup_time() - PSR setup in time usec 2091 * @psr_cap: PSR capabilities from DPCD 2092 * 2093 * Returns: 2094 * PSR setup time for the panel in microseconds, negative 2095 * error code on failure. 2096 */ 2097 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 2098 { 2099 static const u16 psr_setup_time_us[] = { 2100 PSR_SETUP_TIME(330), 2101 PSR_SETUP_TIME(275), 2102 PSR_SETUP_TIME(220), 2103 PSR_SETUP_TIME(165), 2104 PSR_SETUP_TIME(110), 2105 PSR_SETUP_TIME(55), 2106 PSR_SETUP_TIME(0), 2107 }; 2108 int i; 2109 2110 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 2111 if (i >= ARRAY_SIZE(psr_setup_time_us)) 2112 return -EINVAL; 2113 2114 return psr_setup_time_us[i]; 2115 } 2116 EXPORT_SYMBOL(drm_dp_psr_setup_time); 2117 2118 #undef PSR_SETUP_TIME 2119 2120 /** 2121 * drm_dp_start_crc() - start capture of frame CRCs 2122 * @aux: DisplayPort AUX channel 2123 * @crtc: CRTC displaying the frames whose CRCs are to be captured 2124 * 2125 * Returns 0 on success or a negative error code on failure. 2126 */ 2127 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 2128 { 2129 u8 buf; 2130 int ret; 2131 2132 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2133 if (ret < 0) 2134 return ret; 2135 2136 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 2137 if (ret < 0) 2138 return ret; 2139 2140 aux->crc_count = 0; 2141 aux->crtc = crtc; 2142 schedule_work(&aux->crc_work); 2143 2144 return 0; 2145 } 2146 EXPORT_SYMBOL(drm_dp_start_crc); 2147 2148 /** 2149 * drm_dp_stop_crc() - stop capture of frame CRCs 2150 * @aux: DisplayPort AUX channel 2151 * 2152 * Returns 0 on success or a negative error code on failure. 2153 */ 2154 int drm_dp_stop_crc(struct drm_dp_aux *aux) 2155 { 2156 u8 buf; 2157 int ret; 2158 2159 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2160 if (ret < 0) 2161 return ret; 2162 2163 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 2164 if (ret < 0) 2165 return ret; 2166 2167 flush_work(&aux->crc_work); 2168 aux->crtc = NULL; 2169 2170 return 0; 2171 } 2172 EXPORT_SYMBOL(drm_dp_stop_crc); 2173 2174 struct dpcd_quirk { 2175 u8 oui[3]; 2176 u8 device_id[6]; 2177 bool is_branch; 2178 u32 quirks; 2179 }; 2180 2181 #define OUI(first, second, third) { (first), (second), (third) } 2182 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 2183 { (first), (second), (third), (fourth), (fifth), (sixth) } 2184 2185 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 2186 2187 static const struct dpcd_quirk dpcd_quirk_list[] = { 2188 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 2189 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2190 /* LG LP140WF6-SPM1 eDP panel */ 2191 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2192 /* Apple panels need some additional handling to support PSR */ 2193 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 2194 /* CH7511 seems to leave SINK_COUNT zeroed */ 2195 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 2196 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 2197 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 2198 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 2199 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 2200 }; 2201 2202 #undef OUI 2203 2204 /* 2205 * Get a bit mask of DPCD quirks for the sink/branch device identified by 2206 * ident. The quirk data is shared but it's up to the drivers to act on the 2207 * data. 2208 * 2209 * For now, only the OUI (first three bytes) is used, but this may be extended 2210 * to device identification string and hardware/firmware revisions later. 2211 */ 2212 static u32 2213 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 2214 { 2215 const struct dpcd_quirk *quirk; 2216 u32 quirks = 0; 2217 int i; 2218 u8 any_device[] = DEVICE_ID_ANY; 2219 2220 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 2221 quirk = &dpcd_quirk_list[i]; 2222 2223 if (quirk->is_branch != is_branch) 2224 continue; 2225 2226 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 2227 continue; 2228 2229 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 2230 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 2231 continue; 2232 2233 quirks |= quirk->quirks; 2234 } 2235 2236 return quirks; 2237 } 2238 2239 #undef DEVICE_ID_ANY 2240 #undef DEVICE_ID 2241 2242 /** 2243 * drm_dp_read_desc - read sink/branch descriptor from DPCD 2244 * @aux: DisplayPort AUX channel 2245 * @desc: Device descriptor to fill from DPCD 2246 * @is_branch: true for branch devices, false for sink devices 2247 * 2248 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 2249 * identification. 2250 * 2251 * Returns 0 on success or a negative error code on failure. 2252 */ 2253 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 2254 bool is_branch) 2255 { 2256 struct drm_dp_dpcd_ident *ident = &desc->ident; 2257 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 2258 int ret, dev_id_len; 2259 2260 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 2261 if (ret < 0) 2262 return ret; 2263 2264 desc->quirks = drm_dp_get_quirks(ident, is_branch); 2265 2266 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); 2267 2268 drm_dbg_kms(aux->drm_dev, 2269 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 2270 aux->name, is_branch ? "branch" : "sink", 2271 (int)sizeof(ident->oui), ident->oui, dev_id_len, 2272 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf, 2273 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks); 2274 2275 return 0; 2276 } 2277 EXPORT_SYMBOL(drm_dp_read_desc); 2278 2279 /** 2280 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2281 * supported by the DSC sink. 2282 * @dsc_dpcd: DSC capabilities from DPCD 2283 * @is_edp: true if its eDP, false for DP 2284 * 2285 * Read the slice capabilities DPCD register from DSC sink to get 2286 * the maximum slice count supported. This is used to populate 2287 * the DSC parameters in the &struct drm_dsc_config by the driver. 2288 * Driver creates an infoframe using these parameters to populate 2289 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2290 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2291 * 2292 * Returns: 2293 * Maximum slice count supported by DSC sink or 0 its invalid 2294 */ 2295 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2296 bool is_edp) 2297 { 2298 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2299 2300 if (is_edp) { 2301 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2302 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2303 return 4; 2304 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2305 return 2; 2306 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2307 return 1; 2308 } else { 2309 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2310 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2311 2312 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2313 return 24; 2314 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2315 return 20; 2316 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2317 return 16; 2318 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2319 return 12; 2320 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2321 return 10; 2322 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2323 return 8; 2324 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2325 return 6; 2326 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2327 return 4; 2328 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2329 return 2; 2330 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2331 return 1; 2332 } 2333 2334 return 0; 2335 } 2336 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2337 2338 /** 2339 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2340 * @dsc_dpcd: DSC capabilities from DPCD 2341 * 2342 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2343 * number of bits of precision within the decoder line buffer supported by 2344 * the DSC sink. This is used to populate the DSC parameters in the 2345 * &struct drm_dsc_config by the driver. 2346 * Driver creates an infoframe using these parameters to populate 2347 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2348 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2349 * 2350 * Returns: 2351 * Line buffer depth supported by DSC panel or 0 its invalid 2352 */ 2353 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2354 { 2355 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2356 2357 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2358 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2359 return 9; 2360 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2361 return 10; 2362 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2363 return 11; 2364 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2365 return 12; 2366 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2367 return 13; 2368 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2369 return 14; 2370 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2371 return 15; 2372 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2373 return 16; 2374 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2375 return 8; 2376 } 2377 2378 return 0; 2379 } 2380 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2381 2382 /** 2383 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2384 * values supported by the DSC sink. 2385 * @dsc_dpcd: DSC capabilities from DPCD 2386 * @dsc_bpc: An array to be filled by this helper with supported 2387 * input bpcs. 2388 * 2389 * Read the DSC DPCD from the sink device to parse the supported bits per 2390 * component values. This is used to populate the DSC parameters 2391 * in the &struct drm_dsc_config by the driver. 2392 * Driver creates an infoframe using these parameters to populate 2393 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2394 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2395 * 2396 * Returns: 2397 * Number of input BPC values parsed from the DPCD 2398 */ 2399 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2400 u8 dsc_bpc[3]) 2401 { 2402 int num_bpc = 0; 2403 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2404 2405 if (color_depth & DP_DSC_12_BPC) 2406 dsc_bpc[num_bpc++] = 12; 2407 if (color_depth & DP_DSC_10_BPC) 2408 dsc_bpc[num_bpc++] = 10; 2409 if (color_depth & DP_DSC_8_BPC) 2410 dsc_bpc[num_bpc++] = 8; 2411 2412 return num_bpc; 2413 } 2414 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2415 2416 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, 2417 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, 2418 u8 *buf, int buf_size) 2419 { 2420 /* 2421 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns 2422 * corrupted values when reading from the 0xF0000- range with a block 2423 * size bigger than 1. 2424 */ 2425 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; 2426 int offset; 2427 int ret; 2428 2429 for (offset = 0; offset < buf_size; offset += block_size) { 2430 ret = drm_dp_dpcd_read(aux, 2431 address + offset, 2432 &buf[offset], block_size); 2433 if (ret < 0) 2434 return ret; 2435 2436 WARN_ON(ret != block_size); 2437 } 2438 2439 return 0; 2440 } 2441 2442 /** 2443 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities 2444 * @aux: DisplayPort AUX channel 2445 * @dpcd: DisplayPort configuration data 2446 * @caps: buffer to return the capability info in 2447 * 2448 * Read capabilities common to all LTTPRs. 2449 * 2450 * Returns 0 on success or a negative error code on failure. 2451 */ 2452 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 2453 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2454 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2455 { 2456 return drm_dp_read_lttpr_regs(aux, dpcd, 2457 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 2458 caps, DP_LTTPR_COMMON_CAP_SIZE); 2459 } 2460 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 2461 2462 /** 2463 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY 2464 * @aux: DisplayPort AUX channel 2465 * @dpcd: DisplayPort configuration data 2466 * @dp_phy: LTTPR PHY to read the capabilities for 2467 * @caps: buffer to return the capability info in 2468 * 2469 * Read the capabilities for the given LTTPR PHY. 2470 * 2471 * Returns 0 on success or a negative error code on failure. 2472 */ 2473 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 2474 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2475 enum drm_dp_phy dp_phy, 2476 u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2477 { 2478 return drm_dp_read_lttpr_regs(aux, dpcd, 2479 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), 2480 caps, DP_LTTPR_PHY_CAP_SIZE); 2481 } 2482 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); 2483 2484 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) 2485 { 2486 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 2487 } 2488 2489 /** 2490 * drm_dp_lttpr_count - get the number of detected LTTPRs 2491 * @caps: LTTPR common capabilities 2492 * 2493 * Get the number of detected LTTPRs from the LTTPR common capabilities info. 2494 * 2495 * Returns: 2496 * -ERANGE if more than supported number (8) of LTTPRs are detected 2497 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value 2498 * otherwise the number of detected LTTPRs 2499 */ 2500 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2501 { 2502 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); 2503 2504 switch (hweight8(count)) { 2505 case 0: 2506 return 0; 2507 case 1: 2508 return 8 - ilog2(count); 2509 case 8: 2510 return -ERANGE; 2511 default: 2512 return -EINVAL; 2513 } 2514 } 2515 EXPORT_SYMBOL(drm_dp_lttpr_count); 2516 2517 /** 2518 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs 2519 * @caps: LTTPR common capabilities 2520 * 2521 * Returns the maximum link rate supported by all detected LTTPRs. 2522 */ 2523 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2524 { 2525 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); 2526 2527 return drm_dp_bw_code_to_link_rate(rate); 2528 } 2529 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2530 2531 /** 2532 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2533 * @caps: LTTPR common capabilities 2534 * 2535 * Returns the maximum lane count supported by all detected LTTPRs. 2536 */ 2537 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2538 { 2539 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); 2540 2541 return max_lanes & DP_MAX_LANE_COUNT_MASK; 2542 } 2543 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); 2544 2545 /** 2546 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support 2547 * @caps: LTTPR PHY capabilities 2548 * 2549 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2550 * voltage swing level 3. 2551 */ 2552 bool 2553 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2554 { 2555 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2556 2557 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; 2558 } 2559 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); 2560 2561 /** 2562 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support 2563 * @caps: LTTPR PHY capabilities 2564 * 2565 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2566 * pre-emphasis level 3. 2567 */ 2568 bool 2569 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2570 { 2571 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2572 2573 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; 2574 } 2575 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); 2576 2577 /** 2578 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2579 * @aux: DisplayPort AUX channel 2580 * @data: DP phy compliance test parameters. 2581 * 2582 * Returns 0 on success or a negative error code on failure. 2583 */ 2584 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2585 struct drm_dp_phy_test_params *data) 2586 { 2587 int err; 2588 u8 rate, lanes; 2589 2590 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2591 if (err < 0) 2592 return err; 2593 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 2594 2595 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2596 if (err < 0) 2597 return err; 2598 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2599 2600 if (lanes & DP_ENHANCED_FRAME_CAP) 2601 data->enhanced_frame_cap = true; 2602 2603 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 2604 if (err < 0) 2605 return err; 2606 2607 switch (data->phy_pattern) { 2608 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2609 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 2610 &data->custom80, sizeof(data->custom80)); 2611 if (err < 0) 2612 return err; 2613 2614 break; 2615 case DP_PHY_TEST_PATTERN_CP2520: 2616 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 2617 &data->hbr2_reset, 2618 sizeof(data->hbr2_reset)); 2619 if (err < 0) 2620 return err; 2621 } 2622 2623 return 0; 2624 } 2625 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 2626 2627 /** 2628 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 2629 * @aux: DisplayPort AUX channel 2630 * @data: DP phy compliance test parameters. 2631 * @dp_rev: DP revision to use for compliance testing 2632 * 2633 * Returns 0 on success or a negative error code on failure. 2634 */ 2635 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 2636 struct drm_dp_phy_test_params *data, u8 dp_rev) 2637 { 2638 int err, i; 2639 u8 link_config[2]; 2640 u8 test_pattern; 2641 2642 link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate); 2643 link_config[1] = data->num_lanes; 2644 if (data->enhanced_frame_cap) 2645 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2646 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2); 2647 if (err < 0) 2648 return err; 2649 2650 test_pattern = data->phy_pattern; 2651 if (dp_rev < 0x12) { 2652 test_pattern = (test_pattern << 2) & 2653 DP_LINK_QUAL_PATTERN_11_MASK; 2654 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 2655 test_pattern); 2656 if (err < 0) 2657 return err; 2658 } else { 2659 for (i = 0; i < data->num_lanes; i++) { 2660 err = drm_dp_dpcd_writeb(aux, 2661 DP_LINK_QUAL_LANE0_SET + i, 2662 test_pattern); 2663 if (err < 0) 2664 return err; 2665 } 2666 } 2667 2668 return 0; 2669 } 2670 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 2671 2672 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 2673 { 2674 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2675 return "Invalid"; 2676 2677 switch (pixelformat) { 2678 case DP_PIXELFORMAT_RGB: 2679 return "RGB"; 2680 case DP_PIXELFORMAT_YUV444: 2681 return "YUV444"; 2682 case DP_PIXELFORMAT_YUV422: 2683 return "YUV422"; 2684 case DP_PIXELFORMAT_YUV420: 2685 return "YUV420"; 2686 case DP_PIXELFORMAT_Y_ONLY: 2687 return "Y_ONLY"; 2688 case DP_PIXELFORMAT_RAW: 2689 return "RAW"; 2690 default: 2691 return "Reserved"; 2692 } 2693 } 2694 2695 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 2696 enum dp_colorimetry colorimetry) 2697 { 2698 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2699 return "Invalid"; 2700 2701 switch (colorimetry) { 2702 case DP_COLORIMETRY_DEFAULT: 2703 switch (pixelformat) { 2704 case DP_PIXELFORMAT_RGB: 2705 return "sRGB"; 2706 case DP_PIXELFORMAT_YUV444: 2707 case DP_PIXELFORMAT_YUV422: 2708 case DP_PIXELFORMAT_YUV420: 2709 return "BT.601"; 2710 case DP_PIXELFORMAT_Y_ONLY: 2711 return "DICOM PS3.14"; 2712 case DP_PIXELFORMAT_RAW: 2713 return "Custom Color Profile"; 2714 default: 2715 return "Reserved"; 2716 } 2717 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 2718 switch (pixelformat) { 2719 case DP_PIXELFORMAT_RGB: 2720 return "Wide Fixed"; 2721 case DP_PIXELFORMAT_YUV444: 2722 case DP_PIXELFORMAT_YUV422: 2723 case DP_PIXELFORMAT_YUV420: 2724 return "BT.709"; 2725 default: 2726 return "Reserved"; 2727 } 2728 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 2729 switch (pixelformat) { 2730 case DP_PIXELFORMAT_RGB: 2731 return "Wide Float"; 2732 case DP_PIXELFORMAT_YUV444: 2733 case DP_PIXELFORMAT_YUV422: 2734 case DP_PIXELFORMAT_YUV420: 2735 return "xvYCC 601"; 2736 default: 2737 return "Reserved"; 2738 } 2739 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 2740 switch (pixelformat) { 2741 case DP_PIXELFORMAT_RGB: 2742 return "OpRGB"; 2743 case DP_PIXELFORMAT_YUV444: 2744 case DP_PIXELFORMAT_YUV422: 2745 case DP_PIXELFORMAT_YUV420: 2746 return "xvYCC 709"; 2747 default: 2748 return "Reserved"; 2749 } 2750 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 2751 switch (pixelformat) { 2752 case DP_PIXELFORMAT_RGB: 2753 return "DCI-P3"; 2754 case DP_PIXELFORMAT_YUV444: 2755 case DP_PIXELFORMAT_YUV422: 2756 case DP_PIXELFORMAT_YUV420: 2757 return "sYCC 601"; 2758 default: 2759 return "Reserved"; 2760 } 2761 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 2762 switch (pixelformat) { 2763 case DP_PIXELFORMAT_RGB: 2764 return "Custom Profile"; 2765 case DP_PIXELFORMAT_YUV444: 2766 case DP_PIXELFORMAT_YUV422: 2767 case DP_PIXELFORMAT_YUV420: 2768 return "OpYCC 601"; 2769 default: 2770 return "Reserved"; 2771 } 2772 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 2773 switch (pixelformat) { 2774 case DP_PIXELFORMAT_RGB: 2775 return "BT.2020 RGB"; 2776 case DP_PIXELFORMAT_YUV444: 2777 case DP_PIXELFORMAT_YUV422: 2778 case DP_PIXELFORMAT_YUV420: 2779 return "BT.2020 CYCC"; 2780 default: 2781 return "Reserved"; 2782 } 2783 case DP_COLORIMETRY_BT2020_YCC: 2784 switch (pixelformat) { 2785 case DP_PIXELFORMAT_YUV444: 2786 case DP_PIXELFORMAT_YUV422: 2787 case DP_PIXELFORMAT_YUV420: 2788 return "BT.2020 YCC"; 2789 default: 2790 return "Reserved"; 2791 } 2792 default: 2793 return "Invalid"; 2794 } 2795 } 2796 2797 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 2798 { 2799 switch (dynamic_range) { 2800 case DP_DYNAMIC_RANGE_VESA: 2801 return "VESA range"; 2802 case DP_DYNAMIC_RANGE_CTA: 2803 return "CTA range"; 2804 default: 2805 return "Invalid"; 2806 } 2807 } 2808 2809 static const char *dp_content_type_get_name(enum dp_content_type content_type) 2810 { 2811 switch (content_type) { 2812 case DP_CONTENT_TYPE_NOT_DEFINED: 2813 return "Not defined"; 2814 case DP_CONTENT_TYPE_GRAPHICS: 2815 return "Graphics"; 2816 case DP_CONTENT_TYPE_PHOTO: 2817 return "Photo"; 2818 case DP_CONTENT_TYPE_VIDEO: 2819 return "Video"; 2820 case DP_CONTENT_TYPE_GAME: 2821 return "Game"; 2822 default: 2823 return "Reserved"; 2824 } 2825 } 2826 2827 void drm_dp_vsc_sdp_log(const char *level, struct device *dev, 2828 const struct drm_dp_vsc_sdp *vsc) 2829 { 2830 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__) 2831 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", 2832 vsc->revision, vsc->length); 2833 DP_SDP_LOG(" pixelformat: %s\n", 2834 dp_pixelformat_get_name(vsc->pixelformat)); 2835 DP_SDP_LOG(" colorimetry: %s\n", 2836 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 2837 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); 2838 DP_SDP_LOG(" dynamic range: %s\n", 2839 dp_dynamic_range_get_name(vsc->dynamic_range)); 2840 DP_SDP_LOG(" content type: %s\n", 2841 dp_content_type_get_name(vsc->content_type)); 2842 #undef DP_SDP_LOG 2843 } 2844 EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 2845 2846 /** 2847 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON 2848 * @dpcd: DisplayPort configuration data 2849 * @port_cap: port capabilities 2850 * 2851 * Returns maximum frl bandwidth supported by PCON in GBPS, 2852 * returns 0 if not supported. 2853 */ 2854 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2855 const u8 port_cap[4]) 2856 { 2857 int bw; 2858 u8 buf; 2859 2860 buf = port_cap[2]; 2861 bw = buf & DP_PCON_MAX_FRL_BW; 2862 2863 switch (bw) { 2864 case DP_PCON_MAX_9GBPS: 2865 return 9; 2866 case DP_PCON_MAX_18GBPS: 2867 return 18; 2868 case DP_PCON_MAX_24GBPS: 2869 return 24; 2870 case DP_PCON_MAX_32GBPS: 2871 return 32; 2872 case DP_PCON_MAX_40GBPS: 2873 return 40; 2874 case DP_PCON_MAX_48GBPS: 2875 return 48; 2876 case DP_PCON_MAX_0GBPS: 2877 default: 2878 return 0; 2879 } 2880 2881 return 0; 2882 } 2883 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); 2884 2885 /** 2886 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. 2887 * @aux: DisplayPort AUX channel 2888 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. 2889 * 2890 * Returns 0 if success, else returns negative error code. 2891 */ 2892 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) 2893 { 2894 int ret; 2895 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE | 2896 DP_PCON_ENABLE_LINK_FRL_MODE; 2897 2898 if (enable_frl_ready_hpd) 2899 buf |= DP_PCON_ENABLE_HPD_READY; 2900 2901 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 2902 2903 return ret; 2904 } 2905 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare); 2906 2907 /** 2908 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL 2909 * @aux: DisplayPort AUX channel 2910 * 2911 * Returns true if success, else returns false. 2912 */ 2913 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) 2914 { 2915 int ret; 2916 u8 buf; 2917 2918 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 2919 if (ret < 0) 2920 return false; 2921 2922 if (buf & DP_PCON_FRL_READY) 2923 return true; 2924 2925 return false; 2926 } 2927 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); 2928 2929 /** 2930 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 2931 * @aux: DisplayPort AUX channel 2932 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink 2933 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. 2934 * In Concurrent Mode, the FRL link bring up can be done along with 2935 * DP Link training. In Sequential mode, the FRL link bring up is done prior to 2936 * the DP Link training. 2937 * 2938 * Returns 0 if success, else returns negative error code. 2939 */ 2940 2941 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 2942 u8 frl_mode) 2943 { 2944 int ret; 2945 u8 buf; 2946 2947 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 2948 if (ret < 0) 2949 return ret; 2950 2951 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) 2952 buf |= DP_PCON_ENABLE_CONCURRENT_LINK; 2953 else 2954 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; 2955 2956 switch (max_frl_gbps) { 2957 case 9: 2958 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS; 2959 break; 2960 case 18: 2961 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS; 2962 break; 2963 case 24: 2964 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS; 2965 break; 2966 case 32: 2967 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS; 2968 break; 2969 case 40: 2970 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS; 2971 break; 2972 case 48: 2973 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS; 2974 break; 2975 case 0: 2976 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS; 2977 break; 2978 default: 2979 return -EINVAL; 2980 } 2981 2982 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 2983 if (ret < 0) 2984 return ret; 2985 2986 return 0; 2987 } 2988 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); 2989 2990 /** 2991 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 2992 * @aux: DisplayPort AUX channel 2993 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink 2994 * @frl_type : FRL training type, can be Extended, or Normal. 2995 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask 2996 * starting from min, and stops when link training is successful. In Extended 2997 * FRL training, all frl bw selected in the mask are trained by the PCON. 2998 * 2999 * Returns 0 if success, else returns negative error code. 3000 */ 3001 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 3002 u8 frl_type) 3003 { 3004 int ret; 3005 u8 buf = max_frl_mask; 3006 3007 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) 3008 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3009 else 3010 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3011 3012 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); 3013 if (ret < 0) 3014 return ret; 3015 3016 return 0; 3017 } 3018 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2); 3019 3020 /** 3021 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. 3022 * @aux: DisplayPort AUX channel 3023 * 3024 * Returns 0 if success, else returns negative error code. 3025 */ 3026 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) 3027 { 3028 int ret; 3029 3030 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); 3031 if (ret < 0) 3032 return ret; 3033 3034 return 0; 3035 } 3036 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config); 3037 3038 /** 3039 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL 3040 * @aux: DisplayPort AUX channel 3041 * 3042 * Returns 0 if success, else returns negative error code. 3043 */ 3044 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) 3045 { 3046 int ret; 3047 u8 buf = 0; 3048 3049 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3050 if (ret < 0) 3051 return ret; 3052 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) { 3053 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", 3054 aux->name); 3055 return -EINVAL; 3056 } 3057 buf |= DP_PCON_ENABLE_HDMI_LINK; 3058 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3059 if (ret < 0) 3060 return ret; 3061 3062 return 0; 3063 } 3064 EXPORT_SYMBOL(drm_dp_pcon_frl_enable); 3065 3066 /** 3067 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. 3068 * @aux: DisplayPort AUX channel 3069 * 3070 * Returns true if link is active else returns false. 3071 */ 3072 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) 3073 { 3074 u8 buf; 3075 int ret; 3076 3077 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3078 if (ret < 0) 3079 return false; 3080 3081 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; 3082 } 3083 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active); 3084 3085 /** 3086 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE 3087 * @aux: DisplayPort AUX channel 3088 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. 3089 * Valid only if the MODE returned is FRL. For Normal Link training mode 3090 * only 1 of the bits will be set, but in case of Extended mode, more than 3091 * one bits can be set. 3092 * 3093 * Returns the link mode : TMDS or FRL on success, else returns negative error 3094 * code. 3095 */ 3096 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) 3097 { 3098 u8 buf; 3099 int mode; 3100 int ret; 3101 3102 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); 3103 if (ret < 0) 3104 return ret; 3105 3106 mode = buf & DP_PCON_HDMI_LINK_MODE; 3107 3108 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode) 3109 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1; 3110 3111 return mode; 3112 } 3113 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode); 3114 3115 /** 3116 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane 3117 * during link failure between PCON and HDMI sink 3118 * @aux: DisplayPort AUX channel 3119 * @connector: DRM connector 3120 * code. 3121 **/ 3122 3123 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 3124 struct drm_connector *connector) 3125 { 3126 u8 buf, error_count; 3127 int i, num_error; 3128 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3129 3130 for (i = 0; i < hdmi->max_lanes; i++) { 3131 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) 3132 return; 3133 3134 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK; 3135 switch (error_count) { 3136 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS: 3137 num_error = 100; 3138 break; 3139 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS: 3140 num_error = 10; 3141 break; 3142 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS: 3143 num_error = 3; 3144 break; 3145 default: 3146 num_error = 0; 3147 } 3148 3149 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", 3150 aux->name, num_error, i); 3151 } 3152 } 3153 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count); 3154 3155 /* 3156 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 3157 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3158 * 3159 * Returns true is PCON encoder is DSC 1.2 else returns false. 3160 */ 3161 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3162 { 3163 u8 buf; 3164 u8 major_v, minor_v; 3165 3166 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; 3167 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT; 3168 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT; 3169 3170 if (major_v == 1 && minor_v == 2) 3171 return true; 3172 3173 return false; 3174 } 3175 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2); 3176 3177 /* 3178 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder 3179 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3180 * 3181 * Returns maximum no. of slices supported by the PCON DSC Encoder. 3182 */ 3183 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3184 { 3185 u8 slice_cap1, slice_cap2; 3186 3187 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; 3188 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; 3189 3190 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC) 3191 return 24; 3192 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC) 3193 return 20; 3194 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC) 3195 return 16; 3196 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC) 3197 return 12; 3198 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC) 3199 return 10; 3200 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC) 3201 return 8; 3202 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC) 3203 return 6; 3204 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC) 3205 return 4; 3206 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC) 3207 return 2; 3208 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC) 3209 return 1; 3210 3211 return 0; 3212 } 3213 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices); 3214 3215 /* 3216 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder 3217 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3218 * 3219 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. 3220 */ 3221 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3222 { 3223 u8 buf; 3224 3225 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; 3226 3227 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; 3228 } 3229 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width); 3230 3231 /* 3232 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder 3233 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3234 * 3235 * Returns the bpp precision supported by the PCON encoder. 3236 */ 3237 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3238 { 3239 u8 buf; 3240 3241 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; 3242 3243 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) { 3244 case DP_PCON_DSC_ONE_16TH_BPP: 3245 return 16; 3246 case DP_PCON_DSC_ONE_8TH_BPP: 3247 return 8; 3248 case DP_PCON_DSC_ONE_4TH_BPP: 3249 return 4; 3250 case DP_PCON_DSC_ONE_HALF_BPP: 3251 return 2; 3252 case DP_PCON_DSC_ONE_BPP: 3253 return 1; 3254 } 3255 3256 return 0; 3257 } 3258 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr); 3259 3260 static 3261 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) 3262 { 3263 u8 buf; 3264 int ret; 3265 3266 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3267 if (ret < 0) 3268 return ret; 3269 3270 buf |= DP_PCON_ENABLE_DSC_ENCODER; 3271 3272 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) { 3273 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK; 3274 buf |= pps_buf_config << 2; 3275 } 3276 3277 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3278 if (ret < 0) 3279 return ret; 3280 3281 return 0; 3282 } 3283 3284 /** 3285 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters 3286 * for DSC1.2 between PCON & HDMI2.1 sink 3287 * @aux: DisplayPort AUX channel 3288 * 3289 * Returns 0 on success, else returns negative error code. 3290 */ 3291 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) 3292 { 3293 int ret; 3294 3295 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); 3296 if (ret < 0) 3297 return ret; 3298 3299 return 0; 3300 } 3301 EXPORT_SYMBOL(drm_dp_pcon_pps_default); 3302 3303 /** 3304 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for 3305 * HDMI sink 3306 * @aux: DisplayPort AUX channel 3307 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. 3308 * 3309 * Returns 0 on success, else returns negative error code. 3310 */ 3311 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) 3312 { 3313 int ret; 3314 3315 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); 3316 if (ret < 0) 3317 return ret; 3318 3319 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3320 if (ret < 0) 3321 return ret; 3322 3323 return 0; 3324 } 3325 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf); 3326 3327 /* 3328 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder 3329 * override registers 3330 * @aux: DisplayPort AUX channel 3331 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, 3332 * bits_per_pixel. 3333 * 3334 * Returns 0 on success, else returns negative error code. 3335 */ 3336 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) 3337 { 3338 int ret; 3339 3340 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); 3341 if (ret < 0) 3342 return ret; 3343 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); 3344 if (ret < 0) 3345 return ret; 3346 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); 3347 if (ret < 0) 3348 return ret; 3349 3350 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3351 if (ret < 0) 3352 return ret; 3353 3354 return 0; 3355 } 3356 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param); 3357 3358 /* 3359 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr 3360 * @aux: displayPort AUX channel 3361 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. 3362 * 3363 * Returns 0 on success, else returns negative error code. 3364 */ 3365 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) 3366 { 3367 int ret; 3368 u8 buf; 3369 3370 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3371 if (ret < 0) 3372 return ret; 3373 3374 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK) 3375 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK); 3376 else 3377 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK; 3378 3379 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3380 if (ret < 0) 3381 return ret; 3382 3383 return 0; 3384 } 3385 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr); 3386 3387 /** 3388 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX 3389 * @aux: The DP AUX channel to use 3390 * @bl: Backlight capability info from drm_edp_backlight_init() 3391 * @level: The brightness level to set 3392 * 3393 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must 3394 * already have been enabled by the driver by calling drm_edp_backlight_enable(). 3395 * 3396 * Returns: %0 on success, negative error code on failure 3397 */ 3398 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3399 u16 level) 3400 { 3401 int ret; 3402 u8 buf[2] = { 0 }; 3403 3404 /* The panel uses the PWM for controlling brightness levels */ 3405 if (!bl->aux_set) 3406 return 0; 3407 3408 if (bl->lsb_reg_used) { 3409 buf[0] = (level & 0xff00) >> 8; 3410 buf[1] = (level & 0x00ff); 3411 } else { 3412 buf[0] = level; 3413 } 3414 3415 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); 3416 if (ret != sizeof(buf)) { 3417 drm_err(aux->drm_dev, 3418 "%s: Failed to write aux backlight level: %d\n", 3419 aux->name, ret); 3420 return ret < 0 ? ret : -EIO; 3421 } 3422 3423 return 0; 3424 } 3425 EXPORT_SYMBOL(drm_edp_backlight_set_level); 3426 3427 static int 3428 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3429 bool enable) 3430 { 3431 int ret; 3432 u8 buf; 3433 3434 /* This panel uses the EDP_BL_PWR GPIO for enablement */ 3435 if (!bl->aux_enable) 3436 return 0; 3437 3438 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); 3439 if (ret != 1) { 3440 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", 3441 aux->name, ret); 3442 return ret < 0 ? ret : -EIO; 3443 } 3444 if (enable) 3445 buf |= DP_EDP_BACKLIGHT_ENABLE; 3446 else 3447 buf &= ~DP_EDP_BACKLIGHT_ENABLE; 3448 3449 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); 3450 if (ret != 1) { 3451 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", 3452 aux->name, ret); 3453 return ret < 0 ? ret : -EIO; 3454 } 3455 3456 return 0; 3457 } 3458 3459 /** 3460 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD 3461 * @aux: The DP AUX channel to use 3462 * @bl: Backlight capability info from drm_edp_backlight_init() 3463 * @level: The initial backlight level to set via AUX, if there is one 3464 * 3465 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally 3466 * restoring any important backlight state such as the given backlight level, the brightness byte 3467 * count, backlight frequency, etc. 3468 * 3469 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3470 * that the driver handle enabling/disabling the panel through implementation-specific means using 3471 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3472 * this function becomes a no-op, and the driver is expected to handle powering the panel on using 3473 * the EDP_BL_PWR GPIO. 3474 * 3475 * Returns: %0 on success, negative error code on failure. 3476 */ 3477 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3478 const u16 level) 3479 { 3480 int ret; 3481 u8 dpcd_buf; 3482 3483 if (bl->aux_set) 3484 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; 3485 else 3486 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM; 3487 3488 if (bl->pwmgen_bit_count) { 3489 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); 3490 if (ret != 1) 3491 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3492 aux->name, ret); 3493 } 3494 3495 if (bl->pwm_freq_pre_divider) { 3496 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); 3497 if (ret != 1) 3498 drm_dbg_kms(aux->drm_dev, 3499 "%s: Failed to write aux backlight frequency: %d\n", 3500 aux->name, ret); 3501 else 3502 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; 3503 } 3504 3505 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); 3506 if (ret != 1) { 3507 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", 3508 aux->name, ret); 3509 return ret < 0 ? ret : -EIO; 3510 } 3511 3512 ret = drm_edp_backlight_set_level(aux, bl, level); 3513 if (ret < 0) 3514 return ret; 3515 ret = drm_edp_backlight_set_enable(aux, bl, true); 3516 if (ret < 0) 3517 return ret; 3518 3519 return 0; 3520 } 3521 EXPORT_SYMBOL(drm_edp_backlight_enable); 3522 3523 /** 3524 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported 3525 * @aux: The DP AUX channel to use 3526 * @bl: Backlight capability info from drm_edp_backlight_init() 3527 * 3528 * This function handles disabling DPCD backlight controls on a panel over AUX. 3529 * 3530 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3531 * that the driver handle enabling/disabling the panel through implementation-specific means using 3532 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3533 * this function becomes a no-op, and the driver is expected to handle powering the panel off using 3534 * the EDP_BL_PWR GPIO. 3535 * 3536 * Returns: %0 on success or no-op, negative error code on failure. 3537 */ 3538 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) 3539 { 3540 int ret; 3541 3542 ret = drm_edp_backlight_set_enable(aux, bl, false); 3543 if (ret < 0) 3544 return ret; 3545 3546 return 0; 3547 } 3548 EXPORT_SYMBOL(drm_edp_backlight_disable); 3549 3550 static inline int 3551 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3552 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 3553 { 3554 int fxp, fxp_min, fxp_max, fxp_actual, f = 1; 3555 int ret; 3556 u8 pn, pn_min, pn_max; 3557 3558 if (!bl->aux_set) 3559 return 0; 3560 3561 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); 3562 if (ret != 1) { 3563 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", 3564 aux->name, ret); 3565 return -ENODEV; 3566 } 3567 3568 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3569 bl->max = (1 << pn) - 1; 3570 if (!driver_pwm_freq_hz) 3571 return 0; 3572 3573 /* 3574 * Set PWM Frequency divider to match desired frequency provided by the driver. 3575 * The PWM Frequency is calculated as 27Mhz / (F x P). 3576 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the 3577 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) 3578 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the 3579 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) 3580 */ 3581 3582 /* Find desired value of (F x P) 3583 * Note that, if F x P is out of supported range, the maximum value or minimum value will 3584 * applied automatically. So no need to check that. 3585 */ 3586 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz); 3587 3588 /* Use highest possible value of Pn for more granularity of brightness adjustment while 3589 * satisfying the conditions below. 3590 * - Pn is in the range of Pn_min and Pn_max 3591 * - F is in the range of 1 and 255 3592 * - FxP is within 25% of desired value. 3593 * Note: 25% is arbitrary value and may need some tweak. 3594 */ 3595 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); 3596 if (ret != 1) { 3597 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", 3598 aux->name, ret); 3599 return 0; 3600 } 3601 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); 3602 if (ret != 1) { 3603 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", 3604 aux->name, ret); 3605 return 0; 3606 } 3607 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3608 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3609 3610 /* Ensure frequency is within 25% of desired value */ 3611 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); 3612 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); 3613 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { 3614 drm_dbg_kms(aux->drm_dev, 3615 "%s: Driver defined backlight frequency (%d) out of range\n", 3616 aux->name, driver_pwm_freq_hz); 3617 return 0; 3618 } 3619 3620 for (pn = pn_max; pn >= pn_min; pn--) { 3621 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); 3622 fxp_actual = f << pn; 3623 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) 3624 break; 3625 } 3626 3627 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); 3628 if (ret != 1) { 3629 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3630 aux->name, ret); 3631 return 0; 3632 } 3633 bl->pwmgen_bit_count = pn; 3634 bl->max = (1 << pn) - 1; 3635 3636 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) { 3637 bl->pwm_freq_pre_divider = f; 3638 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", 3639 aux->name, driver_pwm_freq_hz); 3640 } 3641 3642 return 0; 3643 } 3644 3645 static inline int 3646 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3647 u8 *current_mode) 3648 { 3649 int ret; 3650 u8 buf[2]; 3651 u8 mode_reg; 3652 3653 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); 3654 if (ret != 1) { 3655 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", 3656 aux->name, ret); 3657 return ret < 0 ? ret : -EIO; 3658 } 3659 3660 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK); 3661 if (!bl->aux_set) 3662 return 0; 3663 3664 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { 3665 int size = 1 + bl->lsb_reg_used; 3666 3667 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); 3668 if (ret != size) { 3669 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", 3670 aux->name, ret); 3671 return ret < 0 ? ret : -EIO; 3672 } 3673 3674 if (bl->lsb_reg_used) 3675 return (buf[0] << 8) | buf[1]; 3676 else 3677 return buf[0]; 3678 } 3679 3680 /* 3681 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and 3682 * the driver should assume max brightness 3683 */ 3684 return bl->max; 3685 } 3686 3687 /** 3688 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight 3689 * interface. 3690 * @aux: The DP aux device to use for probing 3691 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight 3692 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz 3693 * @edp_dpcd: A cached copy of the eDP DPCD 3694 * @current_level: Where to store the probed brightness level, if any 3695 * @current_mode: Where to store the currently set backlight control mode 3696 * 3697 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, 3698 * along with also probing the current and maximum supported brightness levels. 3699 * 3700 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the 3701 * default frequency from the panel is used. 3702 * 3703 * Returns: %0 on success, negative error code on failure. 3704 */ 3705 int 3706 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3707 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 3708 u16 *current_level, u8 *current_mode) 3709 { 3710 int ret; 3711 3712 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) 3713 bl->aux_enable = true; 3714 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) 3715 bl->aux_set = true; 3716 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 3717 bl->lsb_reg_used = true; 3718 3719 /* Sanity check caps */ 3720 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { 3721 drm_dbg_kms(aux->drm_dev, 3722 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", 3723 aux->name); 3724 return -EINVAL; 3725 } 3726 3727 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); 3728 if (ret < 0) 3729 return ret; 3730 3731 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); 3732 if (ret < 0) 3733 return ret; 3734 *current_level = ret; 3735 3736 drm_dbg_kms(aux->drm_dev, 3737 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n", 3738 aux->name, bl->aux_set, bl->aux_enable, *current_mode); 3739 if (bl->aux_set) { 3740 drm_dbg_kms(aux->drm_dev, 3741 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n", 3742 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, 3743 bl->lsb_reg_used); 3744 } 3745 3746 return 0; 3747 } 3748 EXPORT_SYMBOL(drm_edp_backlight_init); 3749 3750 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 3751 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) 3752 3753 static int dp_aux_backlight_update_status(struct backlight_device *bd) 3754 { 3755 struct dp_aux_backlight *bl = bl_get_data(bd); 3756 u16 brightness = backlight_get_brightness(bd); 3757 int ret = 0; 3758 3759 if (!backlight_is_blank(bd)) { 3760 if (!bl->enabled) { 3761 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); 3762 bl->enabled = true; 3763 return 0; 3764 } 3765 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); 3766 } else { 3767 if (bl->enabled) { 3768 drm_edp_backlight_disable(bl->aux, &bl->info); 3769 bl->enabled = false; 3770 } 3771 } 3772 3773 return ret; 3774 } 3775 3776 static const struct backlight_ops dp_aux_bl_ops = { 3777 .update_status = dp_aux_backlight_update_status, 3778 }; 3779 3780 /** 3781 * drm_panel_dp_aux_backlight - create and use DP AUX backlight 3782 * @panel: DRM panel 3783 * @aux: The DP AUX channel to use 3784 * 3785 * Use this function to create and handle backlight if your panel 3786 * supports backlight control over DP AUX channel using DPCD 3787 * registers as per VESA's standard backlight control interface. 3788 * 3789 * When the panel is enabled backlight will be enabled after a 3790 * successful call to &drm_panel_funcs.enable() 3791 * 3792 * When the panel is disabled backlight will be disabled before the 3793 * call to &drm_panel_funcs.disable(). 3794 * 3795 * A typical implementation for a panel driver supporting backlight 3796 * control over DP AUX will call this function at probe time. 3797 * Backlight will then be handled transparently without requiring 3798 * any intervention from the driver. 3799 * 3800 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). 3801 * 3802 * Return: 0 on success or a negative error code on failure. 3803 */ 3804 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 3805 { 3806 struct dp_aux_backlight *bl; 3807 struct backlight_properties props = { 0 }; 3808 u16 current_level; 3809 u8 current_mode; 3810 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 3811 int ret; 3812 3813 if (!panel || !panel->dev || !aux) 3814 return -EINVAL; 3815 3816 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, 3817 EDP_DISPLAY_CTL_CAP_SIZE); 3818 if (ret < 0) 3819 return ret; 3820 3821 if (!drm_edp_backlight_supported(edp_dpcd)) { 3822 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); 3823 return 0; 3824 } 3825 3826 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); 3827 if (!bl) 3828 return -ENOMEM; 3829 3830 bl->aux = aux; 3831 3832 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, 3833 ¤t_level, ¤t_mode); 3834 if (ret < 0) 3835 return ret; 3836 3837 props.type = BACKLIGHT_RAW; 3838 props.brightness = current_level; 3839 props.max_brightness = bl->info.max; 3840 3841 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", 3842 panel->dev, bl, 3843 &dp_aux_bl_ops, &props); 3844 if (IS_ERR(bl->base)) 3845 return PTR_ERR(bl->base); 3846 3847 backlight_disable(bl->base); 3848 3849 panel->backlight = bl->base; 3850 3851 return 0; 3852 } 3853 EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 3854 3855 #endif 3856