1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <asm/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_panel.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device bridge_aux; 174 struct auxiliary_device gpio_aux; 175 struct auxiliary_device aux_aux; 176 struct auxiliary_device pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if defined(CONFIG_PWM) 200 struct pwm_chip pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata) 248 { 249 u32 bit_rate_khz, clk_freq_khz; 250 struct drm_display_mode *mode = 251 &pdata->bridge.encoder->crtc->state->adjusted_mode; 252 253 bit_rate_khz = mode->clock * 254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 256 257 return clk_freq_khz; 258 } 259 260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 261 static const u32 ti_sn_bridge_refclk_lut[] = { 262 12000000, 263 19200000, 264 26000000, 265 27000000, 266 38400000, 267 }; 268 269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 270 static const u32 ti_sn_bridge_dsiclk_lut[] = { 271 468000000, 272 384000000, 273 416000000, 274 486000000, 275 460800000, 276 }; 277 278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) 279 { 280 int i; 281 u32 refclk_rate; 282 const u32 *refclk_lut; 283 size_t refclk_lut_size; 284 285 if (pdata->refclk) { 286 refclk_rate = clk_get_rate(pdata->refclk); 287 refclk_lut = ti_sn_bridge_refclk_lut; 288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 289 clk_prepare_enable(pdata->refclk); 290 } else { 291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000; 292 refclk_lut = ti_sn_bridge_dsiclk_lut; 293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 294 } 295 296 /* for i equals to refclk_lut_size means default frequency */ 297 for (i = 0; i < refclk_lut_size; i++) 298 if (refclk_lut[i] == refclk_rate) 299 break; 300 301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 302 if (i >= refclk_lut_size) 303 i = 1; 304 305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 306 REFCLK_FREQ(i)); 307 308 /* 309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 310 * regardless of its actual sourcing. 311 */ 312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 313 } 314 315 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata) 316 { 317 mutex_lock(&pdata->comms_mutex); 318 319 /* configure bridge ref_clk */ 320 ti_sn_bridge_set_refclk_freq(pdata); 321 322 /* 323 * HPD on this bridge chip is a bit useless. This is an eDP bridge 324 * so the HPD is an internal signal that's only there to signal that 325 * the panel is done powering up. ...but the bridge chip debounces 326 * this signal by between 100 ms and 400 ms (depending on process, 327 * voltage, and temperate--I measured it at about 200 ms). One 328 * particular panel asserted HPD 84 ms after it was powered on meaning 329 * that we saw HPD 284 ms after power on. ...but the same panel said 330 * that instead of looking at HPD you could just hardcode a delay of 331 * 200 ms. We'll assume that the panel driver will have the hardcoded 332 * delay in its prepare and always disable HPD. 333 * 334 * If HPD somehow makes sense on some future panel we'll have to 335 * change this to be conditional on someone specifying that HPD should 336 * be used. 337 */ 338 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 339 HPD_DISABLE); 340 341 pdata->comms_enabled = true; 342 343 mutex_unlock(&pdata->comms_mutex); 344 } 345 346 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 347 { 348 mutex_lock(&pdata->comms_mutex); 349 350 pdata->comms_enabled = false; 351 clk_disable_unprepare(pdata->refclk); 352 353 mutex_unlock(&pdata->comms_mutex); 354 } 355 356 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 357 { 358 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 359 int ret; 360 361 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 362 if (ret) { 363 DRM_ERROR("failed to enable supplies %d\n", ret); 364 return ret; 365 } 366 367 /* td2: min 100 us after regulators before enabling the GPIO */ 368 usleep_range(100, 110); 369 370 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 371 372 /* 373 * If we have a reference clock we can enable communication w/ the 374 * panel (including the aux channel) w/out any need for an input clock 375 * so we can do it in resume which lets us read the EDID before 376 * pre_enable(). Without a reference clock we need the MIPI reference 377 * clock so reading early doesn't work. 378 */ 379 if (pdata->refclk) 380 ti_sn65dsi86_enable_comms(pdata); 381 382 return ret; 383 } 384 385 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 386 { 387 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 388 int ret; 389 390 if (pdata->refclk) 391 ti_sn65dsi86_disable_comms(pdata); 392 393 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 394 395 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 396 if (ret) 397 DRM_ERROR("failed to disable supplies %d\n", ret); 398 399 return ret; 400 } 401 402 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 403 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 404 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 405 pm_runtime_force_resume) 406 }; 407 408 static int status_show(struct seq_file *s, void *data) 409 { 410 struct ti_sn65dsi86 *pdata = s->private; 411 unsigned int reg, val; 412 413 seq_puts(s, "STATUS REGISTERS:\n"); 414 415 pm_runtime_get_sync(pdata->dev); 416 417 /* IRQ Status Registers, see Table 31 in datasheet */ 418 for (reg = 0xf0; reg <= 0xf8; reg++) { 419 regmap_read(pdata->regmap, reg, &val); 420 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 421 } 422 423 pm_runtime_put_autosuspend(pdata->dev); 424 425 return 0; 426 } 427 428 DEFINE_SHOW_ATTRIBUTE(status); 429 430 static void ti_sn65dsi86_debugfs_remove(void *data) 431 { 432 debugfs_remove_recursive(data); 433 } 434 435 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata) 436 { 437 struct device *dev = pdata->dev; 438 struct dentry *debugfs; 439 int ret; 440 441 debugfs = debugfs_create_dir(dev_name(dev), NULL); 442 443 /* 444 * We might get an error back if debugfs wasn't enabled in the kernel 445 * so let's just silently return upon failure. 446 */ 447 if (IS_ERR_OR_NULL(debugfs)) 448 return; 449 450 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs); 451 if (ret) 452 return; 453 454 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 455 } 456 457 /* ----------------------------------------------------------------------------- 458 * Auxiliary Devices (*not* AUX) 459 */ 460 461 static void ti_sn65dsi86_uninit_aux(void *data) 462 { 463 auxiliary_device_uninit(data); 464 } 465 466 static void ti_sn65dsi86_delete_aux(void *data) 467 { 468 auxiliary_device_delete(data); 469 } 470 471 /* 472 * AUX bus docs say that a non-NULL release is mandatory, but it makes no 473 * sense for the model used here where all of the aux devices are allocated 474 * in the single shared structure. We'll use this noop as a workaround. 475 */ 476 static void ti_sn65dsi86_noop(struct device *dev) {} 477 478 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 479 struct auxiliary_device *aux, 480 const char *name) 481 { 482 struct device *dev = pdata->dev; 483 int ret; 484 485 aux->name = name; 486 aux->dev.parent = dev; 487 aux->dev.release = ti_sn65dsi86_noop; 488 device_set_of_node_from_dev(&aux->dev, dev); 489 ret = auxiliary_device_init(aux); 490 if (ret) 491 return ret; 492 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux); 493 if (ret) 494 return ret; 495 496 ret = auxiliary_device_add(aux); 497 if (ret) 498 return ret; 499 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux); 500 501 return ret; 502 } 503 504 /* ----------------------------------------------------------------------------- 505 * AUX Adapter 506 */ 507 508 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 509 { 510 return container_of(aux, struct ti_sn65dsi86, aux); 511 } 512 513 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 514 struct drm_dp_aux_msg *msg) 515 { 516 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 517 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 518 u32 request_val = AUX_CMD_REQ(msg->request); 519 u8 *buf = msg->buffer; 520 unsigned int len = msg->size; 521 unsigned int val; 522 int ret; 523 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 524 525 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 526 return -EINVAL; 527 528 pm_runtime_get_sync(pdata->dev); 529 mutex_lock(&pdata->comms_mutex); 530 531 /* 532 * If someone tries to do a DDC over AUX transaction before pre_enable() 533 * on a device without a dedicated reference clock then we just can't 534 * do it. Fail right away. This prevents non-refclk users from reading 535 * the EDID before enabling the panel but such is life. 536 */ 537 if (!pdata->comms_enabled) { 538 ret = -EIO; 539 goto exit; 540 } 541 542 switch (request) { 543 case DP_AUX_NATIVE_WRITE: 544 case DP_AUX_I2C_WRITE: 545 case DP_AUX_NATIVE_READ: 546 case DP_AUX_I2C_READ: 547 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 548 /* Assume it's good */ 549 msg->reply = 0; 550 break; 551 default: 552 ret = -EINVAL; 553 goto exit; 554 } 555 556 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 557 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 558 addr_len); 559 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 560 ARRAY_SIZE(addr_len)); 561 562 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 563 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 564 565 /* Clear old status bits before start so we don't get confused */ 566 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 567 AUX_IRQ_STATUS_NAT_I2C_FAIL | 568 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 569 AUX_IRQ_STATUS_AUX_SHORT); 570 571 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 572 573 /* Zero delay loop because i2c transactions are slow already */ 574 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 575 !(val & AUX_CMD_SEND), 0, 50 * 1000); 576 if (ret) 577 goto exit; 578 579 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 580 if (ret) 581 goto exit; 582 583 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 584 /* 585 * The hardware tried the message seven times per the DP spec 586 * but it hit a timeout. We ignore defers here because they're 587 * handled in hardware. 588 */ 589 ret = -ETIMEDOUT; 590 goto exit; 591 } 592 593 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 594 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len); 595 if (ret) 596 goto exit; 597 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 598 switch (request) { 599 case DP_AUX_I2C_WRITE: 600 case DP_AUX_I2C_READ: 601 msg->reply |= DP_AUX_I2C_REPLY_NACK; 602 break; 603 case DP_AUX_NATIVE_READ: 604 case DP_AUX_NATIVE_WRITE: 605 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 606 break; 607 } 608 len = 0; 609 goto exit; 610 } 611 612 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 613 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 614 615 exit: 616 mutex_unlock(&pdata->comms_mutex); 617 pm_runtime_mark_last_busy(pdata->dev); 618 pm_runtime_put_autosuspend(pdata->dev); 619 620 if (ret) 621 return ret; 622 return len; 623 } 624 625 static int ti_sn_aux_probe(struct auxiliary_device *adev, 626 const struct auxiliary_device_id *id) 627 { 628 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 629 int ret; 630 631 pdata->aux.name = "ti-sn65dsi86-aux"; 632 pdata->aux.dev = &adev->dev; 633 pdata->aux.transfer = ti_sn_aux_transfer; 634 drm_dp_aux_init(&pdata->aux); 635 636 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 637 if (ret) 638 return ret; 639 640 /* 641 * The eDP to MIPI bridge parts don't work until the AUX channel is 642 * setup so we don't add it in the main driver probe, we add it now. 643 */ 644 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 645 } 646 647 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 648 { .name = "ti_sn65dsi86.aux", }, 649 {}, 650 }; 651 652 static struct auxiliary_driver ti_sn_aux_driver = { 653 .name = "aux", 654 .probe = ti_sn_aux_probe, 655 .id_table = ti_sn_aux_id_table, 656 }; 657 658 /*------------------------------------------------------------------------------ 659 * DRM Bridge 660 */ 661 662 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 663 { 664 return container_of(bridge, struct ti_sn65dsi86, bridge); 665 } 666 667 static int ti_sn_attach_host(struct ti_sn65dsi86 *pdata) 668 { 669 int val; 670 struct mipi_dsi_host *host; 671 struct mipi_dsi_device *dsi; 672 struct device *dev = pdata->dev; 673 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 674 .channel = 0, 675 .node = NULL, 676 }; 677 678 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 679 if (!host) 680 return -EPROBE_DEFER; 681 682 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 683 if (IS_ERR(dsi)) 684 return PTR_ERR(dsi); 685 686 /* TODO: setting to 4 MIPI lanes always for now */ 687 dsi->lanes = 4; 688 dsi->format = MIPI_DSI_FMT_RGB888; 689 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 690 691 /* check if continuous dsi clock is required or not */ 692 pm_runtime_get_sync(dev); 693 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 694 pm_runtime_put_autosuspend(dev); 695 if (!(val & DPPLL_CLK_SRC_DSICLK)) 696 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 697 698 pdata->dsi = dsi; 699 700 return devm_mipi_dsi_attach(dev, dsi); 701 } 702 703 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 704 enum drm_bridge_attach_flags flags) 705 { 706 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 707 int ret; 708 709 pdata->aux.drm_dev = bridge->dev; 710 ret = drm_dp_aux_register(&pdata->aux); 711 if (ret < 0) { 712 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 713 return ret; 714 } 715 716 /* 717 * Attach the next bridge. 718 * We never want the next bridge to *also* create a connector. 719 */ 720 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge, 721 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 722 if (ret < 0) 723 goto err_initted_aux; 724 725 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 726 return 0; 727 728 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 729 pdata->bridge.encoder); 730 if (IS_ERR(pdata->connector)) { 731 ret = PTR_ERR(pdata->connector); 732 goto err_initted_aux; 733 } 734 735 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 736 737 return 0; 738 739 err_initted_aux: 740 drm_dp_aux_unregister(&pdata->aux); 741 return ret; 742 } 743 744 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 745 { 746 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 747 } 748 749 static enum drm_mode_status 750 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 751 const struct drm_display_info *info, 752 const struct drm_display_mode *mode) 753 { 754 /* maximum supported resolution is 4K at 60 fps */ 755 if (mode->clock > 594000) 756 return MODE_CLOCK_HIGH; 757 758 /* 759 * The front and back porch registers are 8 bits, and pulse width 760 * registers are 15 bits, so reject any modes with larger periods. 761 */ 762 763 if ((mode->hsync_start - mode->hdisplay) > 0xff) 764 return MODE_HBLANK_WIDE; 765 766 if ((mode->vsync_start - mode->vdisplay) > 0xff) 767 return MODE_VBLANK_WIDE; 768 769 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 770 return MODE_HSYNC_WIDE; 771 772 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 773 return MODE_VSYNC_WIDE; 774 775 if ((mode->htotal - mode->hsync_end) > 0xff) 776 return MODE_HBLANK_WIDE; 777 778 if ((mode->vtotal - mode->vsync_end) > 0xff) 779 return MODE_VBLANK_WIDE; 780 781 return MODE_OK; 782 } 783 784 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 785 struct drm_bridge_state *old_bridge_state) 786 { 787 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 788 789 /* disable video stream */ 790 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 791 } 792 793 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata) 794 { 795 unsigned int bit_rate_mhz, clk_freq_mhz; 796 unsigned int val; 797 struct drm_display_mode *mode = 798 &pdata->bridge.encoder->crtc->state->adjusted_mode; 799 800 /* set DSIA clk frequency */ 801 bit_rate_mhz = (mode->clock / 1000) * 802 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 803 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 804 805 /* for each increment in val, frequency increases by 5MHz */ 806 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 807 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 808 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 809 } 810 811 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 812 { 813 if (connector->display_info.bpc <= 6) 814 return 18; 815 else 816 return 24; 817 } 818 819 /* 820 * LUT index corresponds to register value and 821 * LUT values corresponds to dp data rate supported 822 * by the bridge in Mbps unit. 823 */ 824 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 825 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 826 }; 827 828 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp) 829 { 830 unsigned int bit_rate_khz, dp_rate_mhz; 831 unsigned int i; 832 struct drm_display_mode *mode = 833 &pdata->bridge.encoder->crtc->state->adjusted_mode; 834 835 /* Calculate minimum bit rate based on our pixel clock. */ 836 bit_rate_khz = mode->clock * bpp; 837 838 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 839 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 840 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 841 842 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 843 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 844 break; 845 846 return i; 847 } 848 849 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 850 { 851 unsigned int valid_rates = 0; 852 unsigned int rate_per_200khz; 853 unsigned int rate_mhz; 854 u8 dpcd_val; 855 int ret; 856 int i, j; 857 858 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 859 if (ret != 1) { 860 DRM_DEV_ERROR(pdata->dev, 861 "Can't read eDP rev (%d), assuming 1.1\n", ret); 862 dpcd_val = DP_EDP_11; 863 } 864 865 if (dpcd_val >= DP_EDP_14) { 866 /* eDP 1.4 devices must provide a custom table */ 867 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 868 869 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 870 sink_rates, sizeof(sink_rates)); 871 872 if (ret != sizeof(sink_rates)) { 873 DRM_DEV_ERROR(pdata->dev, 874 "Can't read supported rate table (%d)\n", ret); 875 876 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 877 memset(sink_rates, 0, sizeof(sink_rates)); 878 } 879 880 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 881 rate_per_200khz = le16_to_cpu(sink_rates[i]); 882 883 if (!rate_per_200khz) 884 break; 885 886 rate_mhz = rate_per_200khz * 200 / 1000; 887 for (j = 0; 888 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 889 j++) { 890 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 891 valid_rates |= BIT(j); 892 } 893 } 894 895 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 896 if (valid_rates & BIT(i)) 897 return valid_rates; 898 } 899 DRM_DEV_ERROR(pdata->dev, 900 "No matching eDP rates in table; falling back\n"); 901 } 902 903 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 904 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 905 if (ret != 1) { 906 DRM_DEV_ERROR(pdata->dev, 907 "Can't read max rate (%d); assuming 5.4 GHz\n", 908 ret); 909 dpcd_val = DP_LINK_BW_5_4; 910 } 911 912 switch (dpcd_val) { 913 default: 914 DRM_DEV_ERROR(pdata->dev, 915 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 916 (int)dpcd_val); 917 fallthrough; 918 case DP_LINK_BW_5_4: 919 valid_rates |= BIT(7); 920 fallthrough; 921 case DP_LINK_BW_2_7: 922 valid_rates |= BIT(4); 923 fallthrough; 924 case DP_LINK_BW_1_62: 925 valid_rates |= BIT(1); 926 break; 927 } 928 929 return valid_rates; 930 } 931 932 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata) 933 { 934 struct drm_display_mode *mode = 935 &pdata->bridge.encoder->crtc->state->adjusted_mode; 936 u8 hsync_polarity = 0, vsync_polarity = 0; 937 938 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 939 hsync_polarity = CHA_HSYNC_POLARITY; 940 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 941 vsync_polarity = CHA_VSYNC_POLARITY; 942 943 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 944 mode->hdisplay); 945 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 946 mode->vdisplay); 947 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 948 (mode->hsync_end - mode->hsync_start) & 0xFF); 949 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 950 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 951 hsync_polarity); 952 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 953 (mode->vsync_end - mode->vsync_start) & 0xFF); 954 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 955 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 956 vsync_polarity); 957 958 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 959 (mode->htotal - mode->hsync_end) & 0xFF); 960 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 961 (mode->vtotal - mode->vsync_end) & 0xFF); 962 963 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 964 (mode->hsync_start - mode->hdisplay) & 0xFF); 965 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 966 (mode->vsync_start - mode->vdisplay) & 0xFF); 967 968 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 969 } 970 971 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 972 { 973 u8 data; 974 int ret; 975 976 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 977 if (ret != 1) { 978 DRM_DEV_ERROR(pdata->dev, 979 "Can't read lane count (%d); assuming 4\n", ret); 980 return 4; 981 } 982 983 return data & DP_LANE_COUNT_MASK; 984 } 985 986 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 987 const char **last_err_str) 988 { 989 unsigned int val; 990 int ret; 991 int i; 992 993 /* set dp clk frequency value */ 994 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 995 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 996 997 /* enable DP PLL */ 998 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 999 1000 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 1001 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 1002 50 * 1000); 1003 if (ret) { 1004 *last_err_str = "DP_PLL_LOCK polling failed"; 1005 goto exit; 1006 } 1007 1008 /* 1009 * We'll try to link train several times. As part of link training 1010 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1011 * the panel isn't ready quite it might respond NAK here which means 1012 * we need to try again. 1013 */ 1014 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1015 /* Semi auto link training mode */ 1016 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1017 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1018 val == ML_TX_MAIN_LINK_OFF || 1019 val == ML_TX_NORMAL_MODE, 1000, 1020 500 * 1000); 1021 if (ret) { 1022 *last_err_str = "Training complete polling failed"; 1023 } else if (val == ML_TX_MAIN_LINK_OFF) { 1024 *last_err_str = "Link training failed, link is off"; 1025 ret = -EIO; 1026 continue; 1027 } 1028 1029 break; 1030 } 1031 1032 /* If we saw quite a few retries, add a note about it */ 1033 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1034 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1035 1036 exit: 1037 /* Disable the PLL if we failed */ 1038 if (ret) 1039 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1040 1041 return ret; 1042 } 1043 1044 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1045 struct drm_bridge_state *old_bridge_state) 1046 { 1047 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1048 struct drm_connector *connector; 1049 const char *last_err_str = "No supported DP rate"; 1050 unsigned int valid_rates; 1051 int dp_rate_idx; 1052 unsigned int val; 1053 int ret = -EINVAL; 1054 int max_dp_lanes; 1055 unsigned int bpp; 1056 1057 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state, 1058 bridge->encoder); 1059 if (!connector) { 1060 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1061 return; 1062 } 1063 1064 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1065 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1066 1067 /* DSI_A lane config */ 1068 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1069 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1070 CHA_DSI_LANES_MASK, val); 1071 1072 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1073 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1074 pdata->ln_polrs << LN_POLRS_OFFSET); 1075 1076 /* set dsi clk frequency value */ 1077 ti_sn_bridge_set_dsi_rate(pdata); 1078 1079 /* 1080 * The SN65DSI86 only supports ASSR Display Authentication method and 1081 * this method is enabled for eDP panels. An eDP panel must support this 1082 * authentication method. We need to enable this method in the eDP panel 1083 * at DisplayPort address 0x0010A prior to link training. 1084 * 1085 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1086 * we need to disable the scrambler. 1087 */ 1088 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1089 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1090 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1091 1092 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1093 SCRAMBLE_DISABLE, 0); 1094 } else { 1095 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1096 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1097 } 1098 1099 bpp = ti_sn_bridge_get_bpp(connector); 1100 /* Set the DP output format (18 bpp or 24 bpp) */ 1101 val = bpp == 18 ? BPP_18_RGB : 0; 1102 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1103 1104 /* DP lane config */ 1105 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1106 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1107 val); 1108 1109 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1110 1111 /* Train until we run out of rates */ 1112 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp); 1113 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1114 dp_rate_idx++) { 1115 if (!(valid_rates & BIT(dp_rate_idx))) 1116 continue; 1117 1118 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1119 if (!ret) 1120 break; 1121 } 1122 if (ret) { 1123 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1124 return; 1125 } 1126 1127 /* config video parameters */ 1128 ti_sn_bridge_set_video_timings(pdata); 1129 1130 /* enable video stream */ 1131 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1132 VSTREAM_ENABLE); 1133 } 1134 1135 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1136 struct drm_bridge_state *old_bridge_state) 1137 { 1138 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1139 1140 pm_runtime_get_sync(pdata->dev); 1141 1142 if (!pdata->refclk) 1143 ti_sn65dsi86_enable_comms(pdata); 1144 1145 /* td7: min 100 us after enable before DSI data */ 1146 usleep_range(100, 110); 1147 } 1148 1149 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1150 struct drm_bridge_state *old_bridge_state) 1151 { 1152 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1153 1154 /* semi auto link training mode OFF */ 1155 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1156 /* Num lanes to 0 as per power sequencing in data sheet */ 1157 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1158 /* disable DP PLL */ 1159 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1160 1161 if (!pdata->refclk) 1162 ti_sn65dsi86_disable_comms(pdata); 1163 1164 pm_runtime_put_sync(pdata->dev); 1165 } 1166 1167 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge) 1168 { 1169 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1170 int val = 0; 1171 1172 pm_runtime_get_sync(pdata->dev); 1173 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1174 pm_runtime_put_autosuspend(pdata->dev); 1175 1176 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1177 : connector_status_disconnected; 1178 } 1179 1180 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge, 1181 struct drm_connector *connector) 1182 { 1183 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1184 1185 return drm_get_edid(connector, &pdata->aux.ddc); 1186 } 1187 1188 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1189 .attach = ti_sn_bridge_attach, 1190 .detach = ti_sn_bridge_detach, 1191 .mode_valid = ti_sn_bridge_mode_valid, 1192 .get_edid = ti_sn_bridge_get_edid, 1193 .detect = ti_sn_bridge_detect, 1194 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1195 .atomic_enable = ti_sn_bridge_atomic_enable, 1196 .atomic_disable = ti_sn_bridge_atomic_disable, 1197 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1198 .atomic_reset = drm_atomic_helper_bridge_reset, 1199 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1200 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1201 }; 1202 1203 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1204 struct device_node *np) 1205 { 1206 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1207 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1208 struct device_node *endpoint; 1209 u8 ln_assign = 0; 1210 u8 ln_polrs = 0; 1211 int dp_lanes; 1212 int i; 1213 1214 /* 1215 * Read config from the device tree about lane remapping and lane 1216 * polarities. These are optional and we assume identity map and 1217 * normal polarity if nothing is specified. It's OK to specify just 1218 * data-lanes but not lane-polarities but not vice versa. 1219 * 1220 * Error checking is light (we just make sure we don't crash or 1221 * buffer overrun) and we assume dts is well formed and specifying 1222 * mappings that the hardware supports. 1223 */ 1224 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1225 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1226 if (dp_lanes > 0) { 1227 of_property_read_u32_array(endpoint, "data-lanes", 1228 lane_assignments, dp_lanes); 1229 of_property_read_u32_array(endpoint, "lane-polarities", 1230 lane_polarities, dp_lanes); 1231 } else { 1232 dp_lanes = SN_MAX_DP_LANES; 1233 } 1234 of_node_put(endpoint); 1235 1236 /* 1237 * Convert into register format. Loop over all lanes even if 1238 * data-lanes had fewer elements so that we nicely initialize 1239 * the LN_ASSIGN register. 1240 */ 1241 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1242 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1243 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1244 } 1245 1246 /* Stash in our struct for when we power on */ 1247 pdata->dp_lanes = dp_lanes; 1248 pdata->ln_assign = ln_assign; 1249 pdata->ln_polrs = ln_polrs; 1250 } 1251 1252 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1253 { 1254 struct device_node *np = pdata->dev->of_node; 1255 1256 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1257 1258 if (!pdata->host_node) { 1259 DRM_ERROR("remote dsi host node not found\n"); 1260 return -ENODEV; 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1267 const struct auxiliary_device_id *id) 1268 { 1269 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1270 struct device_node *np = pdata->dev->of_node; 1271 int ret; 1272 1273 pdata->next_bridge = devm_drm_of_get_bridge(pdata->dev, np, 1, 0); 1274 if (IS_ERR(pdata->next_bridge)) 1275 return dev_err_probe(pdata->dev, PTR_ERR(pdata->next_bridge), 1276 "failed to create panel bridge\n"); 1277 1278 ti_sn_bridge_parse_lanes(pdata, np); 1279 1280 ret = ti_sn_bridge_parse_dsi_host(pdata); 1281 if (ret) 1282 return ret; 1283 1284 pdata->bridge.funcs = &ti_sn_bridge_funcs; 1285 pdata->bridge.of_node = np; 1286 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1287 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1288 1289 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) 1290 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 1291 1292 drm_bridge_add(&pdata->bridge); 1293 1294 ret = ti_sn_attach_host(pdata); 1295 if (ret) { 1296 dev_err_probe(pdata->dev, ret, "failed to attach dsi host\n"); 1297 goto err_remove_bridge; 1298 } 1299 1300 return 0; 1301 1302 err_remove_bridge: 1303 drm_bridge_remove(&pdata->bridge); 1304 return ret; 1305 } 1306 1307 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1308 { 1309 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1310 1311 if (!pdata) 1312 return; 1313 1314 drm_bridge_remove(&pdata->bridge); 1315 1316 of_node_put(pdata->host_node); 1317 } 1318 1319 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1320 { .name = "ti_sn65dsi86.bridge", }, 1321 {}, 1322 }; 1323 1324 static struct auxiliary_driver ti_sn_bridge_driver = { 1325 .name = "bridge", 1326 .probe = ti_sn_bridge_probe, 1327 .remove = ti_sn_bridge_remove, 1328 .id_table = ti_sn_bridge_id_table, 1329 }; 1330 1331 /* ----------------------------------------------------------------------------- 1332 * PWM Controller 1333 */ 1334 #if defined(CONFIG_PWM) 1335 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1336 { 1337 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1338 } 1339 1340 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1341 { 1342 atomic_set(&pdata->pwm_pin_busy, 0); 1343 } 1344 1345 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1346 { 1347 return container_of(chip, struct ti_sn65dsi86, pchip); 1348 } 1349 1350 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1351 { 1352 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1353 1354 return ti_sn_pwm_pin_request(pdata); 1355 } 1356 1357 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1358 { 1359 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1360 1361 ti_sn_pwm_pin_release(pdata); 1362 } 1363 1364 /* 1365 * Limitations: 1366 * - The PWM signal is not driven when the chip is powered down, or in its 1367 * reset state and the driver does not implement the "suspend state" 1368 * described in the documentation. In order to save power, state->enabled is 1369 * interpreted as denoting if the signal is expected to be valid, and is used 1370 * to determine if the chip needs to be kept powered. 1371 * - Changing both period and duty_cycle is not done atomically, neither is the 1372 * multi-byte register updates, so the output might briefly be undefined 1373 * during update. 1374 */ 1375 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1376 const struct pwm_state *state) 1377 { 1378 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1379 unsigned int pwm_en_inv; 1380 unsigned int backlight; 1381 unsigned int pre_div; 1382 unsigned int scale; 1383 u64 period_max; 1384 u64 period; 1385 int ret; 1386 1387 if (!pdata->pwm_enabled) { 1388 ret = pm_runtime_get_sync(pdata->dev); 1389 if (ret < 0) { 1390 pm_runtime_put_sync(pdata->dev); 1391 return ret; 1392 } 1393 } 1394 1395 if (state->enabled) { 1396 if (!pdata->pwm_enabled) { 1397 /* 1398 * The chip might have been powered down while we 1399 * didn't hold a PM runtime reference, so mux in the 1400 * PWM function on the GPIO pin again. 1401 */ 1402 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1403 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1404 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1405 if (ret) { 1406 dev_err(pdata->dev, "failed to mux in PWM function\n"); 1407 goto out; 1408 } 1409 } 1410 1411 /* 1412 * Per the datasheet the PWM frequency is given by: 1413 * 1414 * REFCLK_FREQ 1415 * PWM_FREQ = ----------------------------------- 1416 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1417 * 1418 * However, after careful review the author is convinced that 1419 * the documentation has lost some parenthesis around 1420 * "BACKLIGHT_SCALE + 1". 1421 * 1422 * With the period T_pwm = 1/PWM_FREQ this can be written: 1423 * 1424 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1425 * 1426 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1427 * PWM_PRE_DIV must be: 1428 * 1429 * T_pwm * REFCLK_FREQ 1430 * PWM_PRE_DIV >= ------------------------- 1431 * BACKLIGHT_SCALE_MAX + 1 1432 * 1433 * To simplify the search and to favour higher resolution of 1434 * the duty cycle over accuracy of the period, the lowest 1435 * possible PWM_PRE_DIV is used. Finally the scale is 1436 * calculated as: 1437 * 1438 * T_pwm * REFCLK_FREQ 1439 * BACKLIGHT_SCALE = ---------------------- - 1 1440 * PWM_PRE_DIV 1441 * 1442 * Here T_pwm is represented in seconds, so appropriate scaling 1443 * to nanoseconds is necessary. 1444 */ 1445 1446 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1447 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1448 ret = -EINVAL; 1449 goto out; 1450 } 1451 1452 /* 1453 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1454 * Limit period to this to avoid overflows 1455 */ 1456 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1457 pdata->pwm_refclk_freq); 1458 period = min(state->period, period_max); 1459 1460 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1461 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1462 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1463 1464 /* 1465 * The documentation has the duty ratio given as: 1466 * 1467 * duty BACKLIGHT 1468 * ------- = --------------------- 1469 * period BACKLIGHT_SCALE + 1 1470 * 1471 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1472 * to definition above and adjusting for nanosecond 1473 * representation of duty cycle gives us: 1474 */ 1475 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1476 (u64)NSEC_PER_SEC * pre_div); 1477 if (backlight > scale) 1478 backlight = scale; 1479 1480 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1481 if (ret) { 1482 dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n"); 1483 goto out; 1484 } 1485 1486 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1487 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1488 } 1489 1490 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1491 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1492 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1493 if (ret) { 1494 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n"); 1495 goto out; 1496 } 1497 1498 pdata->pwm_enabled = state->enabled; 1499 out: 1500 1501 if (!pdata->pwm_enabled) 1502 pm_runtime_put_sync(pdata->dev); 1503 1504 return ret; 1505 } 1506 1507 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1508 struct pwm_state *state) 1509 { 1510 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1511 unsigned int pwm_en_inv; 1512 unsigned int pre_div; 1513 u16 backlight; 1514 u16 scale; 1515 int ret; 1516 1517 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1518 if (ret) 1519 return ret; 1520 1521 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1522 if (ret) 1523 return ret; 1524 1525 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1526 if (ret) 1527 return ret; 1528 1529 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1530 if (ret) 1531 return ret; 1532 1533 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1534 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1535 state->polarity = PWM_POLARITY_INVERSED; 1536 else 1537 state->polarity = PWM_POLARITY_NORMAL; 1538 1539 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1540 pdata->pwm_refclk_freq); 1541 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1542 pdata->pwm_refclk_freq); 1543 1544 if (state->duty_cycle > state->period) 1545 state->duty_cycle = state->period; 1546 1547 return 0; 1548 } 1549 1550 static const struct pwm_ops ti_sn_pwm_ops = { 1551 .request = ti_sn_pwm_request, 1552 .free = ti_sn_pwm_free, 1553 .apply = ti_sn_pwm_apply, 1554 .get_state = ti_sn_pwm_get_state, 1555 .owner = THIS_MODULE, 1556 }; 1557 1558 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1559 const struct auxiliary_device_id *id) 1560 { 1561 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1562 1563 pdata->pchip.dev = pdata->dev; 1564 pdata->pchip.ops = &ti_sn_pwm_ops; 1565 pdata->pchip.npwm = 1; 1566 pdata->pchip.of_xlate = of_pwm_single_xlate; 1567 pdata->pchip.of_pwm_n_cells = 1; 1568 1569 return pwmchip_add(&pdata->pchip); 1570 } 1571 1572 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1573 { 1574 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1575 1576 pwmchip_remove(&pdata->pchip); 1577 1578 if (pdata->pwm_enabled) 1579 pm_runtime_put_sync(pdata->dev); 1580 } 1581 1582 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1583 { .name = "ti_sn65dsi86.pwm", }, 1584 {}, 1585 }; 1586 1587 static struct auxiliary_driver ti_sn_pwm_driver = { 1588 .name = "pwm", 1589 .probe = ti_sn_pwm_probe, 1590 .remove = ti_sn_pwm_remove, 1591 .id_table = ti_sn_pwm_id_table, 1592 }; 1593 1594 static int __init ti_sn_pwm_register(void) 1595 { 1596 return auxiliary_driver_register(&ti_sn_pwm_driver); 1597 } 1598 1599 static void ti_sn_pwm_unregister(void) 1600 { 1601 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1602 } 1603 1604 #else 1605 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1606 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1607 1608 static inline int ti_sn_pwm_register(void) { return 0; } 1609 static inline void ti_sn_pwm_unregister(void) {} 1610 #endif 1611 1612 /* ----------------------------------------------------------------------------- 1613 * GPIO Controller 1614 */ 1615 #if defined(CONFIG_OF_GPIO) 1616 1617 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1618 const struct of_phandle_args *gpiospec, 1619 u32 *flags) 1620 { 1621 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1622 return -EINVAL; 1623 1624 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1625 return -EINVAL; 1626 1627 if (flags) 1628 *flags = gpiospec->args[1]; 1629 1630 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1631 } 1632 1633 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1634 unsigned int offset) 1635 { 1636 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1637 1638 /* 1639 * We already have to keep track of the direction because we use 1640 * that to figure out whether we've powered the device. We can 1641 * just return that rather than (maybe) powering up the device 1642 * to ask its direction. 1643 */ 1644 return test_bit(offset, pdata->gchip_output) ? 1645 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1646 } 1647 1648 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1649 { 1650 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1651 unsigned int val; 1652 int ret; 1653 1654 /* 1655 * When the pin is an input we don't forcibly keep the bridge 1656 * powered--we just power it on to read the pin. NOTE: part of 1657 * the reason this works is that the bridge defaults (when 1658 * powered back on) to all 4 GPIOs being configured as GPIO input. 1659 * Also note that if something else is keeping the chip powered the 1660 * pm_runtime functions are lightweight increments of a refcount. 1661 */ 1662 pm_runtime_get_sync(pdata->dev); 1663 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1664 pm_runtime_put_autosuspend(pdata->dev); 1665 1666 if (ret) 1667 return ret; 1668 1669 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1670 } 1671 1672 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1673 int val) 1674 { 1675 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1676 int ret; 1677 1678 if (!test_bit(offset, pdata->gchip_output)) { 1679 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); 1680 return; 1681 } 1682 1683 val &= 1; 1684 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1685 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1686 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1687 if (ret) 1688 dev_warn(pdata->dev, 1689 "Failed to set bridge GPIO %u: %d\n", offset, ret); 1690 } 1691 1692 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1693 unsigned int offset) 1694 { 1695 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1696 int shift = offset * 2; 1697 int ret; 1698 1699 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1700 return 0; 1701 1702 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1703 SN_GPIO_MUX_MASK << shift, 1704 SN_GPIO_MUX_INPUT << shift); 1705 if (ret) { 1706 set_bit(offset, pdata->gchip_output); 1707 return ret; 1708 } 1709 1710 /* 1711 * NOTE: if nobody else is powering the device this may fully power 1712 * it off and when it comes back it will have lost all state, but 1713 * that's OK because the default is input and we're now an input. 1714 */ 1715 pm_runtime_put_autosuspend(pdata->dev); 1716 1717 return 0; 1718 } 1719 1720 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1721 unsigned int offset, int val) 1722 { 1723 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1724 int shift = offset * 2; 1725 int ret; 1726 1727 if (test_and_set_bit(offset, pdata->gchip_output)) 1728 return 0; 1729 1730 pm_runtime_get_sync(pdata->dev); 1731 1732 /* Set value first to avoid glitching */ 1733 ti_sn_bridge_gpio_set(chip, offset, val); 1734 1735 /* Set direction */ 1736 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1737 SN_GPIO_MUX_MASK << shift, 1738 SN_GPIO_MUX_OUTPUT << shift); 1739 if (ret) { 1740 clear_bit(offset, pdata->gchip_output); 1741 pm_runtime_put_autosuspend(pdata->dev); 1742 } 1743 1744 return ret; 1745 } 1746 1747 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1748 { 1749 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1750 1751 if (offset == SN_PWM_GPIO_IDX) 1752 return ti_sn_pwm_pin_request(pdata); 1753 1754 return 0; 1755 } 1756 1757 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1758 { 1759 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1760 1761 /* We won't keep pm_runtime if we're input, so switch there on free */ 1762 ti_sn_bridge_gpio_direction_input(chip, offset); 1763 1764 if (offset == SN_PWM_GPIO_IDX) 1765 ti_sn_pwm_pin_release(pdata); 1766 } 1767 1768 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1769 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1770 }; 1771 1772 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1773 const struct auxiliary_device_id *id) 1774 { 1775 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1776 int ret; 1777 1778 /* Only init if someone is going to use us as a GPIO controller */ 1779 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1780 return 0; 1781 1782 pdata->gchip.label = dev_name(pdata->dev); 1783 pdata->gchip.parent = pdata->dev; 1784 pdata->gchip.owner = THIS_MODULE; 1785 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1786 pdata->gchip.of_gpio_n_cells = 2; 1787 pdata->gchip.request = ti_sn_bridge_gpio_request; 1788 pdata->gchip.free = ti_sn_bridge_gpio_free; 1789 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1790 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1791 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1792 pdata->gchip.get = ti_sn_bridge_gpio_get; 1793 pdata->gchip.set = ti_sn_bridge_gpio_set; 1794 pdata->gchip.can_sleep = true; 1795 pdata->gchip.names = ti_sn_bridge_gpio_names; 1796 pdata->gchip.ngpio = SN_NUM_GPIOS; 1797 pdata->gchip.base = -1; 1798 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1799 if (ret) 1800 dev_err(pdata->dev, "can't add gpio chip\n"); 1801 1802 return ret; 1803 } 1804 1805 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1806 { .name = "ti_sn65dsi86.gpio", }, 1807 {}, 1808 }; 1809 1810 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1811 1812 static struct auxiliary_driver ti_sn_gpio_driver = { 1813 .name = "gpio", 1814 .probe = ti_sn_gpio_probe, 1815 .id_table = ti_sn_gpio_id_table, 1816 }; 1817 1818 static int __init ti_sn_gpio_register(void) 1819 { 1820 return auxiliary_driver_register(&ti_sn_gpio_driver); 1821 } 1822 1823 static void ti_sn_gpio_unregister(void) 1824 { 1825 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1826 } 1827 1828 #else 1829 1830 static inline int ti_sn_gpio_register(void) { return 0; } 1831 static inline void ti_sn_gpio_unregister(void) {} 1832 1833 #endif 1834 1835 /* ----------------------------------------------------------------------------- 1836 * Probe & Remove 1837 */ 1838 1839 static void ti_sn65dsi86_runtime_disable(void *data) 1840 { 1841 pm_runtime_dont_use_autosuspend(data); 1842 pm_runtime_disable(data); 1843 } 1844 1845 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1846 { 1847 unsigned int i; 1848 const char * const ti_sn_bridge_supply_names[] = { 1849 "vcca", "vcc", "vccio", "vpll", 1850 }; 1851 1852 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1853 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1854 1855 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1856 pdata->supplies); 1857 } 1858 1859 static int ti_sn65dsi86_probe(struct i2c_client *client) 1860 { 1861 struct device *dev = &client->dev; 1862 struct ti_sn65dsi86 *pdata; 1863 int ret; 1864 1865 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1866 DRM_ERROR("device doesn't support I2C\n"); 1867 return -ENODEV; 1868 } 1869 1870 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL); 1871 if (!pdata) 1872 return -ENOMEM; 1873 dev_set_drvdata(dev, pdata); 1874 pdata->dev = dev; 1875 1876 mutex_init(&pdata->comms_mutex); 1877 1878 pdata->regmap = devm_regmap_init_i2c(client, 1879 &ti_sn65dsi86_regmap_config); 1880 if (IS_ERR(pdata->regmap)) 1881 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1882 "regmap i2c init failed\n"); 1883 1884 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1885 GPIOD_OUT_LOW); 1886 if (IS_ERR(pdata->enable_gpio)) 1887 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1888 "failed to get enable gpio from DT\n"); 1889 1890 ret = ti_sn65dsi86_parse_regulators(pdata); 1891 if (ret) 1892 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1893 1894 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1895 if (IS_ERR(pdata->refclk)) 1896 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1897 "failed to get reference clock\n"); 1898 1899 pm_runtime_enable(dev); 1900 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1901 pm_runtime_use_autosuspend(pdata->dev); 1902 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1903 if (ret) 1904 return ret; 1905 1906 ti_sn65dsi86_debugfs_init(pdata); 1907 1908 /* 1909 * Break ourselves up into a collection of aux devices. The only real 1910 * motiviation here is to solve the chicken-and-egg problem of probe 1911 * ordering. The bridge wants the panel to be there when it probes. 1912 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1913 * when it probes. The panel and maybe backlight might want the DDC 1914 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1915 * to finish probing even if others return -EPROBE_DEFER and gets us 1916 * around the problems. 1917 */ 1918 1919 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1920 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1921 if (ret) 1922 return ret; 1923 } 1924 1925 if (IS_ENABLED(CONFIG_PWM)) { 1926 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1927 if (ret) 1928 return ret; 1929 } 1930 1931 /* 1932 * NOTE: At the end of the AUX channel probe we'll add the aux device 1933 * for the bridge. This is because the bridge can't be used until the 1934 * AUX channel is there and this is a very simple solution to the 1935 * dependency problem. 1936 */ 1937 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 1938 } 1939 1940 static struct i2c_device_id ti_sn65dsi86_id[] = { 1941 { "ti,sn65dsi86", 0}, 1942 {}, 1943 }; 1944 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 1945 1946 static const struct of_device_id ti_sn65dsi86_match_table[] = { 1947 {.compatible = "ti,sn65dsi86"}, 1948 {}, 1949 }; 1950 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 1951 1952 static struct i2c_driver ti_sn65dsi86_driver = { 1953 .driver = { 1954 .name = "ti_sn65dsi86", 1955 .of_match_table = ti_sn65dsi86_match_table, 1956 .pm = &ti_sn65dsi86_pm_ops, 1957 }, 1958 .probe_new = ti_sn65dsi86_probe, 1959 .id_table = ti_sn65dsi86_id, 1960 }; 1961 1962 static int __init ti_sn65dsi86_init(void) 1963 { 1964 int ret; 1965 1966 ret = i2c_add_driver(&ti_sn65dsi86_driver); 1967 if (ret) 1968 return ret; 1969 1970 ret = ti_sn_gpio_register(); 1971 if (ret) 1972 goto err_main_was_registered; 1973 1974 ret = ti_sn_pwm_register(); 1975 if (ret) 1976 goto err_gpio_was_registered; 1977 1978 ret = auxiliary_driver_register(&ti_sn_aux_driver); 1979 if (ret) 1980 goto err_pwm_was_registered; 1981 1982 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 1983 if (ret) 1984 goto err_aux_was_registered; 1985 1986 return 0; 1987 1988 err_aux_was_registered: 1989 auxiliary_driver_unregister(&ti_sn_aux_driver); 1990 err_pwm_was_registered: 1991 ti_sn_pwm_unregister(); 1992 err_gpio_was_registered: 1993 ti_sn_gpio_unregister(); 1994 err_main_was_registered: 1995 i2c_del_driver(&ti_sn65dsi86_driver); 1996 1997 return ret; 1998 } 1999 module_init(ti_sn65dsi86_init); 2000 2001 static void __exit ti_sn65dsi86_exit(void) 2002 { 2003 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2004 auxiliary_driver_unregister(&ti_sn_aux_driver); 2005 ti_sn_pwm_unregister(); 2006 ti_sn_gpio_unregister(); 2007 i2c_del_driver(&ti_sn65dsi86_driver); 2008 } 2009 module_exit(ti_sn65dsi86_exit); 2010 2011 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2012 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2013 MODULE_LICENSE("GPL v2"); 2014