1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <asm/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_panel.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device bridge_aux; 174 struct auxiliary_device gpio_aux; 175 struct auxiliary_device aux_aux; 176 struct auxiliary_device pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if defined(CONFIG_PWM) 200 struct pwm_chip pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata) 248 { 249 u32 bit_rate_khz, clk_freq_khz; 250 struct drm_display_mode *mode = 251 &pdata->bridge.encoder->crtc->state->adjusted_mode; 252 253 bit_rate_khz = mode->clock * 254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 256 257 return clk_freq_khz; 258 } 259 260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 261 static const u32 ti_sn_bridge_refclk_lut[] = { 262 12000000, 263 19200000, 264 26000000, 265 27000000, 266 38400000, 267 }; 268 269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 270 static const u32 ti_sn_bridge_dsiclk_lut[] = { 271 468000000, 272 384000000, 273 416000000, 274 486000000, 275 460800000, 276 }; 277 278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) 279 { 280 int i; 281 u32 refclk_rate; 282 const u32 *refclk_lut; 283 size_t refclk_lut_size; 284 285 if (pdata->refclk) { 286 refclk_rate = clk_get_rate(pdata->refclk); 287 refclk_lut = ti_sn_bridge_refclk_lut; 288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 289 clk_prepare_enable(pdata->refclk); 290 } else { 291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000; 292 refclk_lut = ti_sn_bridge_dsiclk_lut; 293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 294 } 295 296 /* for i equals to refclk_lut_size means default frequency */ 297 for (i = 0; i < refclk_lut_size; i++) 298 if (refclk_lut[i] == refclk_rate) 299 break; 300 301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 302 if (i >= refclk_lut_size) 303 i = 1; 304 305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 306 REFCLK_FREQ(i)); 307 308 /* 309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 310 * regardless of its actual sourcing. 311 */ 312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 313 } 314 315 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata) 316 { 317 mutex_lock(&pdata->comms_mutex); 318 319 /* configure bridge ref_clk */ 320 ti_sn_bridge_set_refclk_freq(pdata); 321 322 /* 323 * HPD on this bridge chip is a bit useless. This is an eDP bridge 324 * so the HPD is an internal signal that's only there to signal that 325 * the panel is done powering up. ...but the bridge chip debounces 326 * this signal by between 100 ms and 400 ms (depending on process, 327 * voltage, and temperate--I measured it at about 200 ms). One 328 * particular panel asserted HPD 84 ms after it was powered on meaning 329 * that we saw HPD 284 ms after power on. ...but the same panel said 330 * that instead of looking at HPD you could just hardcode a delay of 331 * 200 ms. We'll assume that the panel driver will have the hardcoded 332 * delay in its prepare and always disable HPD. 333 * 334 * If HPD somehow makes sense on some future panel we'll have to 335 * change this to be conditional on someone specifying that HPD should 336 * be used. 337 */ 338 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 339 HPD_DISABLE); 340 341 pdata->comms_enabled = true; 342 343 mutex_unlock(&pdata->comms_mutex); 344 } 345 346 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 347 { 348 mutex_lock(&pdata->comms_mutex); 349 350 pdata->comms_enabled = false; 351 clk_disable_unprepare(pdata->refclk); 352 353 mutex_unlock(&pdata->comms_mutex); 354 } 355 356 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 357 { 358 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 359 int ret; 360 361 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 362 if (ret) { 363 DRM_ERROR("failed to enable supplies %d\n", ret); 364 return ret; 365 } 366 367 /* td2: min 100 us after regulators before enabling the GPIO */ 368 usleep_range(100, 110); 369 370 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 371 372 /* 373 * If we have a reference clock we can enable communication w/ the 374 * panel (including the aux channel) w/out any need for an input clock 375 * so we can do it in resume which lets us read the EDID before 376 * pre_enable(). Without a reference clock we need the MIPI reference 377 * clock so reading early doesn't work. 378 */ 379 if (pdata->refclk) 380 ti_sn65dsi86_enable_comms(pdata); 381 382 return ret; 383 } 384 385 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 386 { 387 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 388 int ret; 389 390 if (pdata->refclk) 391 ti_sn65dsi86_disable_comms(pdata); 392 393 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 394 395 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 396 if (ret) 397 DRM_ERROR("failed to disable supplies %d\n", ret); 398 399 return ret; 400 } 401 402 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 403 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 404 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 405 pm_runtime_force_resume) 406 }; 407 408 static int status_show(struct seq_file *s, void *data) 409 { 410 struct ti_sn65dsi86 *pdata = s->private; 411 unsigned int reg, val; 412 413 seq_puts(s, "STATUS REGISTERS:\n"); 414 415 pm_runtime_get_sync(pdata->dev); 416 417 /* IRQ Status Registers, see Table 31 in datasheet */ 418 for (reg = 0xf0; reg <= 0xf8; reg++) { 419 regmap_read(pdata->regmap, reg, &val); 420 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 421 } 422 423 pm_runtime_put_autosuspend(pdata->dev); 424 425 return 0; 426 } 427 428 DEFINE_SHOW_ATTRIBUTE(status); 429 430 static void ti_sn65dsi86_debugfs_remove(void *data) 431 { 432 debugfs_remove_recursive(data); 433 } 434 435 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata) 436 { 437 struct device *dev = pdata->dev; 438 struct dentry *debugfs; 439 int ret; 440 441 debugfs = debugfs_create_dir(dev_name(dev), NULL); 442 443 /* 444 * We might get an error back if debugfs wasn't enabled in the kernel 445 * so let's just silently return upon failure. 446 */ 447 if (IS_ERR_OR_NULL(debugfs)) 448 return; 449 450 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs); 451 if (ret) 452 return; 453 454 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 455 } 456 457 /* ----------------------------------------------------------------------------- 458 * Auxiliary Devices (*not* AUX) 459 */ 460 461 static void ti_sn65dsi86_uninit_aux(void *data) 462 { 463 auxiliary_device_uninit(data); 464 } 465 466 static void ti_sn65dsi86_delete_aux(void *data) 467 { 468 auxiliary_device_delete(data); 469 } 470 471 /* 472 * AUX bus docs say that a non-NULL release is mandatory, but it makes no 473 * sense for the model used here where all of the aux devices are allocated 474 * in the single shared structure. We'll use this noop as a workaround. 475 */ 476 static void ti_sn65dsi86_noop(struct device *dev) {} 477 478 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 479 struct auxiliary_device *aux, 480 const char *name) 481 { 482 struct device *dev = pdata->dev; 483 int ret; 484 485 aux->name = name; 486 aux->dev.parent = dev; 487 aux->dev.release = ti_sn65dsi86_noop; 488 device_set_of_node_from_dev(&aux->dev, dev); 489 ret = auxiliary_device_init(aux); 490 if (ret) 491 return ret; 492 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux); 493 if (ret) 494 return ret; 495 496 ret = auxiliary_device_add(aux); 497 if (ret) 498 return ret; 499 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux); 500 501 return ret; 502 } 503 504 /* ----------------------------------------------------------------------------- 505 * AUX Adapter 506 */ 507 508 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 509 { 510 return container_of(aux, struct ti_sn65dsi86, aux); 511 } 512 513 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 514 struct drm_dp_aux_msg *msg) 515 { 516 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 517 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 518 u32 request_val = AUX_CMD_REQ(msg->request); 519 u8 *buf = msg->buffer; 520 unsigned int len = msg->size; 521 unsigned int val; 522 int ret; 523 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 524 525 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 526 return -EINVAL; 527 528 pm_runtime_get_sync(pdata->dev); 529 mutex_lock(&pdata->comms_mutex); 530 531 /* 532 * If someone tries to do a DDC over AUX transaction before pre_enable() 533 * on a device without a dedicated reference clock then we just can't 534 * do it. Fail right away. This prevents non-refclk users from reading 535 * the EDID before enabling the panel but such is life. 536 */ 537 if (!pdata->comms_enabled) { 538 ret = -EIO; 539 goto exit; 540 } 541 542 switch (request) { 543 case DP_AUX_NATIVE_WRITE: 544 case DP_AUX_I2C_WRITE: 545 case DP_AUX_NATIVE_READ: 546 case DP_AUX_I2C_READ: 547 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 548 /* Assume it's good */ 549 msg->reply = 0; 550 break; 551 default: 552 ret = -EINVAL; 553 goto exit; 554 } 555 556 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 557 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 558 addr_len); 559 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 560 ARRAY_SIZE(addr_len)); 561 562 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 563 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 564 565 /* Clear old status bits before start so we don't get confused */ 566 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 567 AUX_IRQ_STATUS_NAT_I2C_FAIL | 568 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 569 AUX_IRQ_STATUS_AUX_SHORT); 570 571 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 572 573 /* Zero delay loop because i2c transactions are slow already */ 574 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 575 !(val & AUX_CMD_SEND), 0, 50 * 1000); 576 if (ret) 577 goto exit; 578 579 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 580 if (ret) 581 goto exit; 582 583 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 584 /* 585 * The hardware tried the message seven times per the DP spec 586 * but it hit a timeout. We ignore defers here because they're 587 * handled in hardware. 588 */ 589 ret = -ETIMEDOUT; 590 goto exit; 591 } 592 593 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 594 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len); 595 if (ret) 596 goto exit; 597 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 598 switch (request) { 599 case DP_AUX_I2C_WRITE: 600 case DP_AUX_I2C_READ: 601 msg->reply |= DP_AUX_I2C_REPLY_NACK; 602 break; 603 case DP_AUX_NATIVE_READ: 604 case DP_AUX_NATIVE_WRITE: 605 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 606 break; 607 } 608 len = 0; 609 goto exit; 610 } 611 612 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 613 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 614 615 exit: 616 mutex_unlock(&pdata->comms_mutex); 617 pm_runtime_mark_last_busy(pdata->dev); 618 pm_runtime_put_autosuspend(pdata->dev); 619 620 if (ret) 621 return ret; 622 return len; 623 } 624 625 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 626 { 627 /* 628 * The HPD in this chip is a bit useless (See comment in 629 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait 630 * for HPD, we just assume it's asserted after the wait_us delay. 631 * 632 * In case we are asked to wait forever (wait_us=0) take conservative 633 * 500ms delay. 634 */ 635 if (wait_us == 0) 636 wait_us = 500000; 637 638 usleep_range(wait_us, wait_us + 1000); 639 640 return 0; 641 } 642 643 static int ti_sn_aux_probe(struct auxiliary_device *adev, 644 const struct auxiliary_device_id *id) 645 { 646 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 647 int ret; 648 649 pdata->aux.name = "ti-sn65dsi86-aux"; 650 pdata->aux.dev = &adev->dev; 651 pdata->aux.transfer = ti_sn_aux_transfer; 652 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; 653 drm_dp_aux_init(&pdata->aux); 654 655 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 656 if (ret) 657 return ret; 658 659 /* 660 * The eDP to MIPI bridge parts don't work until the AUX channel is 661 * setup so we don't add it in the main driver probe, we add it now. 662 */ 663 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 664 } 665 666 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 667 { .name = "ti_sn65dsi86.aux", }, 668 {}, 669 }; 670 671 static struct auxiliary_driver ti_sn_aux_driver = { 672 .name = "aux", 673 .probe = ti_sn_aux_probe, 674 .id_table = ti_sn_aux_id_table, 675 }; 676 677 /*------------------------------------------------------------------------------ 678 * DRM Bridge 679 */ 680 681 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 682 { 683 return container_of(bridge, struct ti_sn65dsi86, bridge); 684 } 685 686 static int ti_sn_attach_host(struct ti_sn65dsi86 *pdata) 687 { 688 int val; 689 struct mipi_dsi_host *host; 690 struct mipi_dsi_device *dsi; 691 struct device *dev = pdata->dev; 692 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 693 .channel = 0, 694 .node = NULL, 695 }; 696 697 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 698 if (!host) 699 return -EPROBE_DEFER; 700 701 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 702 if (IS_ERR(dsi)) 703 return PTR_ERR(dsi); 704 705 /* TODO: setting to 4 MIPI lanes always for now */ 706 dsi->lanes = 4; 707 dsi->format = MIPI_DSI_FMT_RGB888; 708 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 709 710 /* check if continuous dsi clock is required or not */ 711 pm_runtime_get_sync(dev); 712 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 713 pm_runtime_put_autosuspend(dev); 714 if (!(val & DPPLL_CLK_SRC_DSICLK)) 715 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 716 717 pdata->dsi = dsi; 718 719 return devm_mipi_dsi_attach(dev, dsi); 720 } 721 722 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 723 enum drm_bridge_attach_flags flags) 724 { 725 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 726 int ret; 727 728 pdata->aux.drm_dev = bridge->dev; 729 ret = drm_dp_aux_register(&pdata->aux); 730 if (ret < 0) { 731 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 732 return ret; 733 } 734 735 /* 736 * Attach the next bridge. 737 * We never want the next bridge to *also* create a connector. 738 */ 739 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge, 740 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 741 if (ret < 0) 742 goto err_initted_aux; 743 744 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 745 return 0; 746 747 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 748 pdata->bridge.encoder); 749 if (IS_ERR(pdata->connector)) { 750 ret = PTR_ERR(pdata->connector); 751 goto err_initted_aux; 752 } 753 754 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 755 756 return 0; 757 758 err_initted_aux: 759 drm_dp_aux_unregister(&pdata->aux); 760 return ret; 761 } 762 763 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 764 { 765 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 766 } 767 768 static enum drm_mode_status 769 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 770 const struct drm_display_info *info, 771 const struct drm_display_mode *mode) 772 { 773 /* maximum supported resolution is 4K at 60 fps */ 774 if (mode->clock > 594000) 775 return MODE_CLOCK_HIGH; 776 777 /* 778 * The front and back porch registers are 8 bits, and pulse width 779 * registers are 15 bits, so reject any modes with larger periods. 780 */ 781 782 if ((mode->hsync_start - mode->hdisplay) > 0xff) 783 return MODE_HBLANK_WIDE; 784 785 if ((mode->vsync_start - mode->vdisplay) > 0xff) 786 return MODE_VBLANK_WIDE; 787 788 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 789 return MODE_HSYNC_WIDE; 790 791 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 792 return MODE_VSYNC_WIDE; 793 794 if ((mode->htotal - mode->hsync_end) > 0xff) 795 return MODE_HBLANK_WIDE; 796 797 if ((mode->vtotal - mode->vsync_end) > 0xff) 798 return MODE_VBLANK_WIDE; 799 800 return MODE_OK; 801 } 802 803 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 804 struct drm_bridge_state *old_bridge_state) 805 { 806 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 807 808 /* disable video stream */ 809 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 810 } 811 812 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata) 813 { 814 unsigned int bit_rate_mhz, clk_freq_mhz; 815 unsigned int val; 816 struct drm_display_mode *mode = 817 &pdata->bridge.encoder->crtc->state->adjusted_mode; 818 819 /* set DSIA clk frequency */ 820 bit_rate_mhz = (mode->clock / 1000) * 821 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 822 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 823 824 /* for each increment in val, frequency increases by 5MHz */ 825 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 826 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 827 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 828 } 829 830 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 831 { 832 if (connector->display_info.bpc <= 6) 833 return 18; 834 else 835 return 24; 836 } 837 838 /* 839 * LUT index corresponds to register value and 840 * LUT values corresponds to dp data rate supported 841 * by the bridge in Mbps unit. 842 */ 843 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 844 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 845 }; 846 847 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp) 848 { 849 unsigned int bit_rate_khz, dp_rate_mhz; 850 unsigned int i; 851 struct drm_display_mode *mode = 852 &pdata->bridge.encoder->crtc->state->adjusted_mode; 853 854 /* Calculate minimum bit rate based on our pixel clock. */ 855 bit_rate_khz = mode->clock * bpp; 856 857 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 858 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 859 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 860 861 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 862 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 863 break; 864 865 return i; 866 } 867 868 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 869 { 870 unsigned int valid_rates = 0; 871 unsigned int rate_per_200khz; 872 unsigned int rate_mhz; 873 u8 dpcd_val; 874 int ret; 875 int i, j; 876 877 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 878 if (ret != 1) { 879 DRM_DEV_ERROR(pdata->dev, 880 "Can't read eDP rev (%d), assuming 1.1\n", ret); 881 dpcd_val = DP_EDP_11; 882 } 883 884 if (dpcd_val >= DP_EDP_14) { 885 /* eDP 1.4 devices must provide a custom table */ 886 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 887 888 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 889 sink_rates, sizeof(sink_rates)); 890 891 if (ret != sizeof(sink_rates)) { 892 DRM_DEV_ERROR(pdata->dev, 893 "Can't read supported rate table (%d)\n", ret); 894 895 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 896 memset(sink_rates, 0, sizeof(sink_rates)); 897 } 898 899 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 900 rate_per_200khz = le16_to_cpu(sink_rates[i]); 901 902 if (!rate_per_200khz) 903 break; 904 905 rate_mhz = rate_per_200khz * 200 / 1000; 906 for (j = 0; 907 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 908 j++) { 909 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 910 valid_rates |= BIT(j); 911 } 912 } 913 914 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 915 if (valid_rates & BIT(i)) 916 return valid_rates; 917 } 918 DRM_DEV_ERROR(pdata->dev, 919 "No matching eDP rates in table; falling back\n"); 920 } 921 922 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 923 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 924 if (ret != 1) { 925 DRM_DEV_ERROR(pdata->dev, 926 "Can't read max rate (%d); assuming 5.4 GHz\n", 927 ret); 928 dpcd_val = DP_LINK_BW_5_4; 929 } 930 931 switch (dpcd_val) { 932 default: 933 DRM_DEV_ERROR(pdata->dev, 934 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 935 (int)dpcd_val); 936 fallthrough; 937 case DP_LINK_BW_5_4: 938 valid_rates |= BIT(7); 939 fallthrough; 940 case DP_LINK_BW_2_7: 941 valid_rates |= BIT(4); 942 fallthrough; 943 case DP_LINK_BW_1_62: 944 valid_rates |= BIT(1); 945 break; 946 } 947 948 return valid_rates; 949 } 950 951 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata) 952 { 953 struct drm_display_mode *mode = 954 &pdata->bridge.encoder->crtc->state->adjusted_mode; 955 u8 hsync_polarity = 0, vsync_polarity = 0; 956 957 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 958 hsync_polarity = CHA_HSYNC_POLARITY; 959 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 960 vsync_polarity = CHA_VSYNC_POLARITY; 961 962 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 963 mode->hdisplay); 964 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 965 mode->vdisplay); 966 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 967 (mode->hsync_end - mode->hsync_start) & 0xFF); 968 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 969 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 970 hsync_polarity); 971 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 972 (mode->vsync_end - mode->vsync_start) & 0xFF); 973 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 974 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 975 vsync_polarity); 976 977 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 978 (mode->htotal - mode->hsync_end) & 0xFF); 979 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 980 (mode->vtotal - mode->vsync_end) & 0xFF); 981 982 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 983 (mode->hsync_start - mode->hdisplay) & 0xFF); 984 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 985 (mode->vsync_start - mode->vdisplay) & 0xFF); 986 987 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 988 } 989 990 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 991 { 992 u8 data; 993 int ret; 994 995 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 996 if (ret != 1) { 997 DRM_DEV_ERROR(pdata->dev, 998 "Can't read lane count (%d); assuming 4\n", ret); 999 return 4; 1000 } 1001 1002 return data & DP_LANE_COUNT_MASK; 1003 } 1004 1005 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 1006 const char **last_err_str) 1007 { 1008 unsigned int val; 1009 int ret; 1010 int i; 1011 1012 /* set dp clk frequency value */ 1013 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 1014 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 1015 1016 /* enable DP PLL */ 1017 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 1018 1019 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 1020 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 1021 50 * 1000); 1022 if (ret) { 1023 *last_err_str = "DP_PLL_LOCK polling failed"; 1024 goto exit; 1025 } 1026 1027 /* 1028 * We'll try to link train several times. As part of link training 1029 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1030 * the panel isn't ready quite it might respond NAK here which means 1031 * we need to try again. 1032 */ 1033 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1034 /* Semi auto link training mode */ 1035 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1036 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1037 val == ML_TX_MAIN_LINK_OFF || 1038 val == ML_TX_NORMAL_MODE, 1000, 1039 500 * 1000); 1040 if (ret) { 1041 *last_err_str = "Training complete polling failed"; 1042 } else if (val == ML_TX_MAIN_LINK_OFF) { 1043 *last_err_str = "Link training failed, link is off"; 1044 ret = -EIO; 1045 continue; 1046 } 1047 1048 break; 1049 } 1050 1051 /* If we saw quite a few retries, add a note about it */ 1052 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1053 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1054 1055 exit: 1056 /* Disable the PLL if we failed */ 1057 if (ret) 1058 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1059 1060 return ret; 1061 } 1062 1063 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1064 struct drm_bridge_state *old_bridge_state) 1065 { 1066 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1067 struct drm_connector *connector; 1068 const char *last_err_str = "No supported DP rate"; 1069 unsigned int valid_rates; 1070 int dp_rate_idx; 1071 unsigned int val; 1072 int ret = -EINVAL; 1073 int max_dp_lanes; 1074 unsigned int bpp; 1075 1076 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state, 1077 bridge->encoder); 1078 if (!connector) { 1079 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1080 return; 1081 } 1082 1083 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1084 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1085 1086 /* DSI_A lane config */ 1087 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1088 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1089 CHA_DSI_LANES_MASK, val); 1090 1091 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1092 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1093 pdata->ln_polrs << LN_POLRS_OFFSET); 1094 1095 /* set dsi clk frequency value */ 1096 ti_sn_bridge_set_dsi_rate(pdata); 1097 1098 /* 1099 * The SN65DSI86 only supports ASSR Display Authentication method and 1100 * this method is enabled for eDP panels. An eDP panel must support this 1101 * authentication method. We need to enable this method in the eDP panel 1102 * at DisplayPort address 0x0010A prior to link training. 1103 * 1104 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1105 * we need to disable the scrambler. 1106 */ 1107 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1108 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1109 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1110 1111 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1112 SCRAMBLE_DISABLE, 0); 1113 } else { 1114 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1115 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1116 } 1117 1118 bpp = ti_sn_bridge_get_bpp(connector); 1119 /* Set the DP output format (18 bpp or 24 bpp) */ 1120 val = bpp == 18 ? BPP_18_RGB : 0; 1121 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1122 1123 /* DP lane config */ 1124 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1125 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1126 val); 1127 1128 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1129 1130 /* Train until we run out of rates */ 1131 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp); 1132 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1133 dp_rate_idx++) { 1134 if (!(valid_rates & BIT(dp_rate_idx))) 1135 continue; 1136 1137 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1138 if (!ret) 1139 break; 1140 } 1141 if (ret) { 1142 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1143 return; 1144 } 1145 1146 /* config video parameters */ 1147 ti_sn_bridge_set_video_timings(pdata); 1148 1149 /* enable video stream */ 1150 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1151 VSTREAM_ENABLE); 1152 } 1153 1154 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1155 struct drm_bridge_state *old_bridge_state) 1156 { 1157 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1158 1159 pm_runtime_get_sync(pdata->dev); 1160 1161 if (!pdata->refclk) 1162 ti_sn65dsi86_enable_comms(pdata); 1163 1164 /* td7: min 100 us after enable before DSI data */ 1165 usleep_range(100, 110); 1166 } 1167 1168 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1169 struct drm_bridge_state *old_bridge_state) 1170 { 1171 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1172 1173 /* semi auto link training mode OFF */ 1174 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1175 /* Num lanes to 0 as per power sequencing in data sheet */ 1176 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1177 /* disable DP PLL */ 1178 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1179 1180 if (!pdata->refclk) 1181 ti_sn65dsi86_disable_comms(pdata); 1182 1183 pm_runtime_put_sync(pdata->dev); 1184 } 1185 1186 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge) 1187 { 1188 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1189 int val = 0; 1190 1191 pm_runtime_get_sync(pdata->dev); 1192 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1193 pm_runtime_put_autosuspend(pdata->dev); 1194 1195 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1196 : connector_status_disconnected; 1197 } 1198 1199 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge, 1200 struct drm_connector *connector) 1201 { 1202 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1203 1204 return drm_get_edid(connector, &pdata->aux.ddc); 1205 } 1206 1207 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1208 .attach = ti_sn_bridge_attach, 1209 .detach = ti_sn_bridge_detach, 1210 .mode_valid = ti_sn_bridge_mode_valid, 1211 .get_edid = ti_sn_bridge_get_edid, 1212 .detect = ti_sn_bridge_detect, 1213 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1214 .atomic_enable = ti_sn_bridge_atomic_enable, 1215 .atomic_disable = ti_sn_bridge_atomic_disable, 1216 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1217 .atomic_reset = drm_atomic_helper_bridge_reset, 1218 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1219 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1220 }; 1221 1222 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1223 struct device_node *np) 1224 { 1225 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1226 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1227 struct device_node *endpoint; 1228 u8 ln_assign = 0; 1229 u8 ln_polrs = 0; 1230 int dp_lanes; 1231 int i; 1232 1233 /* 1234 * Read config from the device tree about lane remapping and lane 1235 * polarities. These are optional and we assume identity map and 1236 * normal polarity if nothing is specified. It's OK to specify just 1237 * data-lanes but not lane-polarities but not vice versa. 1238 * 1239 * Error checking is light (we just make sure we don't crash or 1240 * buffer overrun) and we assume dts is well formed and specifying 1241 * mappings that the hardware supports. 1242 */ 1243 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1244 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1245 if (dp_lanes > 0) { 1246 of_property_read_u32_array(endpoint, "data-lanes", 1247 lane_assignments, dp_lanes); 1248 of_property_read_u32_array(endpoint, "lane-polarities", 1249 lane_polarities, dp_lanes); 1250 } else { 1251 dp_lanes = SN_MAX_DP_LANES; 1252 } 1253 of_node_put(endpoint); 1254 1255 /* 1256 * Convert into register format. Loop over all lanes even if 1257 * data-lanes had fewer elements so that we nicely initialize 1258 * the LN_ASSIGN register. 1259 */ 1260 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1261 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1262 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1263 } 1264 1265 /* Stash in our struct for when we power on */ 1266 pdata->dp_lanes = dp_lanes; 1267 pdata->ln_assign = ln_assign; 1268 pdata->ln_polrs = ln_polrs; 1269 } 1270 1271 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1272 { 1273 struct device_node *np = pdata->dev->of_node; 1274 1275 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1276 1277 if (!pdata->host_node) { 1278 DRM_ERROR("remote dsi host node not found\n"); 1279 return -ENODEV; 1280 } 1281 1282 return 0; 1283 } 1284 1285 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1286 const struct auxiliary_device_id *id) 1287 { 1288 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1289 struct device_node *np = pdata->dev->of_node; 1290 int ret; 1291 1292 pdata->next_bridge = devm_drm_of_get_bridge(pdata->dev, np, 1, 0); 1293 if (IS_ERR(pdata->next_bridge)) 1294 return dev_err_probe(pdata->dev, PTR_ERR(pdata->next_bridge), 1295 "failed to create panel bridge\n"); 1296 1297 ti_sn_bridge_parse_lanes(pdata, np); 1298 1299 ret = ti_sn_bridge_parse_dsi_host(pdata); 1300 if (ret) 1301 return ret; 1302 1303 pdata->bridge.funcs = &ti_sn_bridge_funcs; 1304 pdata->bridge.of_node = np; 1305 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1306 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1307 1308 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) 1309 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 1310 1311 drm_bridge_add(&pdata->bridge); 1312 1313 ret = ti_sn_attach_host(pdata); 1314 if (ret) { 1315 dev_err_probe(pdata->dev, ret, "failed to attach dsi host\n"); 1316 goto err_remove_bridge; 1317 } 1318 1319 return 0; 1320 1321 err_remove_bridge: 1322 drm_bridge_remove(&pdata->bridge); 1323 return ret; 1324 } 1325 1326 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1327 { 1328 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1329 1330 if (!pdata) 1331 return; 1332 1333 drm_bridge_remove(&pdata->bridge); 1334 1335 of_node_put(pdata->host_node); 1336 } 1337 1338 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1339 { .name = "ti_sn65dsi86.bridge", }, 1340 {}, 1341 }; 1342 1343 static struct auxiliary_driver ti_sn_bridge_driver = { 1344 .name = "bridge", 1345 .probe = ti_sn_bridge_probe, 1346 .remove = ti_sn_bridge_remove, 1347 .id_table = ti_sn_bridge_id_table, 1348 }; 1349 1350 /* ----------------------------------------------------------------------------- 1351 * PWM Controller 1352 */ 1353 #if defined(CONFIG_PWM) 1354 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1355 { 1356 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1357 } 1358 1359 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1360 { 1361 atomic_set(&pdata->pwm_pin_busy, 0); 1362 } 1363 1364 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1365 { 1366 return container_of(chip, struct ti_sn65dsi86, pchip); 1367 } 1368 1369 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1370 { 1371 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1372 1373 return ti_sn_pwm_pin_request(pdata); 1374 } 1375 1376 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1377 { 1378 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1379 1380 ti_sn_pwm_pin_release(pdata); 1381 } 1382 1383 /* 1384 * Limitations: 1385 * - The PWM signal is not driven when the chip is powered down, or in its 1386 * reset state and the driver does not implement the "suspend state" 1387 * described in the documentation. In order to save power, state->enabled is 1388 * interpreted as denoting if the signal is expected to be valid, and is used 1389 * to determine if the chip needs to be kept powered. 1390 * - Changing both period and duty_cycle is not done atomically, neither is the 1391 * multi-byte register updates, so the output might briefly be undefined 1392 * during update. 1393 */ 1394 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1395 const struct pwm_state *state) 1396 { 1397 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1398 unsigned int pwm_en_inv; 1399 unsigned int backlight; 1400 unsigned int pre_div; 1401 unsigned int scale; 1402 u64 period_max; 1403 u64 period; 1404 int ret; 1405 1406 if (!pdata->pwm_enabled) { 1407 ret = pm_runtime_get_sync(pdata->dev); 1408 if (ret < 0) { 1409 pm_runtime_put_sync(pdata->dev); 1410 return ret; 1411 } 1412 } 1413 1414 if (state->enabled) { 1415 if (!pdata->pwm_enabled) { 1416 /* 1417 * The chip might have been powered down while we 1418 * didn't hold a PM runtime reference, so mux in the 1419 * PWM function on the GPIO pin again. 1420 */ 1421 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1422 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1423 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1424 if (ret) { 1425 dev_err(pdata->dev, "failed to mux in PWM function\n"); 1426 goto out; 1427 } 1428 } 1429 1430 /* 1431 * Per the datasheet the PWM frequency is given by: 1432 * 1433 * REFCLK_FREQ 1434 * PWM_FREQ = ----------------------------------- 1435 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1436 * 1437 * However, after careful review the author is convinced that 1438 * the documentation has lost some parenthesis around 1439 * "BACKLIGHT_SCALE + 1". 1440 * 1441 * With the period T_pwm = 1/PWM_FREQ this can be written: 1442 * 1443 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1444 * 1445 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1446 * PWM_PRE_DIV must be: 1447 * 1448 * T_pwm * REFCLK_FREQ 1449 * PWM_PRE_DIV >= ------------------------- 1450 * BACKLIGHT_SCALE_MAX + 1 1451 * 1452 * To simplify the search and to favour higher resolution of 1453 * the duty cycle over accuracy of the period, the lowest 1454 * possible PWM_PRE_DIV is used. Finally the scale is 1455 * calculated as: 1456 * 1457 * T_pwm * REFCLK_FREQ 1458 * BACKLIGHT_SCALE = ---------------------- - 1 1459 * PWM_PRE_DIV 1460 * 1461 * Here T_pwm is represented in seconds, so appropriate scaling 1462 * to nanoseconds is necessary. 1463 */ 1464 1465 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1466 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1467 ret = -EINVAL; 1468 goto out; 1469 } 1470 1471 /* 1472 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1473 * Limit period to this to avoid overflows 1474 */ 1475 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1476 pdata->pwm_refclk_freq); 1477 period = min(state->period, period_max); 1478 1479 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1480 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1481 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1482 1483 /* 1484 * The documentation has the duty ratio given as: 1485 * 1486 * duty BACKLIGHT 1487 * ------- = --------------------- 1488 * period BACKLIGHT_SCALE + 1 1489 * 1490 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1491 * to definition above and adjusting for nanosecond 1492 * representation of duty cycle gives us: 1493 */ 1494 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1495 (u64)NSEC_PER_SEC * pre_div); 1496 if (backlight > scale) 1497 backlight = scale; 1498 1499 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1500 if (ret) { 1501 dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n"); 1502 goto out; 1503 } 1504 1505 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1506 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1507 } 1508 1509 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1510 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1511 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1512 if (ret) { 1513 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n"); 1514 goto out; 1515 } 1516 1517 pdata->pwm_enabled = state->enabled; 1518 out: 1519 1520 if (!pdata->pwm_enabled) 1521 pm_runtime_put_sync(pdata->dev); 1522 1523 return ret; 1524 } 1525 1526 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1527 struct pwm_state *state) 1528 { 1529 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1530 unsigned int pwm_en_inv; 1531 unsigned int pre_div; 1532 u16 backlight; 1533 u16 scale; 1534 int ret; 1535 1536 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1537 if (ret) 1538 return ret; 1539 1540 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1541 if (ret) 1542 return ret; 1543 1544 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1545 if (ret) 1546 return ret; 1547 1548 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1549 if (ret) 1550 return ret; 1551 1552 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1553 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1554 state->polarity = PWM_POLARITY_INVERSED; 1555 else 1556 state->polarity = PWM_POLARITY_NORMAL; 1557 1558 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1559 pdata->pwm_refclk_freq); 1560 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1561 pdata->pwm_refclk_freq); 1562 1563 if (state->duty_cycle > state->period) 1564 state->duty_cycle = state->period; 1565 1566 return 0; 1567 } 1568 1569 static const struct pwm_ops ti_sn_pwm_ops = { 1570 .request = ti_sn_pwm_request, 1571 .free = ti_sn_pwm_free, 1572 .apply = ti_sn_pwm_apply, 1573 .get_state = ti_sn_pwm_get_state, 1574 .owner = THIS_MODULE, 1575 }; 1576 1577 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1578 const struct auxiliary_device_id *id) 1579 { 1580 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1581 1582 pdata->pchip.dev = pdata->dev; 1583 pdata->pchip.ops = &ti_sn_pwm_ops; 1584 pdata->pchip.npwm = 1; 1585 pdata->pchip.of_xlate = of_pwm_single_xlate; 1586 pdata->pchip.of_pwm_n_cells = 1; 1587 1588 return pwmchip_add(&pdata->pchip); 1589 } 1590 1591 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1592 { 1593 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1594 1595 pwmchip_remove(&pdata->pchip); 1596 1597 if (pdata->pwm_enabled) 1598 pm_runtime_put_sync(pdata->dev); 1599 } 1600 1601 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1602 { .name = "ti_sn65dsi86.pwm", }, 1603 {}, 1604 }; 1605 1606 static struct auxiliary_driver ti_sn_pwm_driver = { 1607 .name = "pwm", 1608 .probe = ti_sn_pwm_probe, 1609 .remove = ti_sn_pwm_remove, 1610 .id_table = ti_sn_pwm_id_table, 1611 }; 1612 1613 static int __init ti_sn_pwm_register(void) 1614 { 1615 return auxiliary_driver_register(&ti_sn_pwm_driver); 1616 } 1617 1618 static void ti_sn_pwm_unregister(void) 1619 { 1620 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1621 } 1622 1623 #else 1624 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1625 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1626 1627 static inline int ti_sn_pwm_register(void) { return 0; } 1628 static inline void ti_sn_pwm_unregister(void) {} 1629 #endif 1630 1631 /* ----------------------------------------------------------------------------- 1632 * GPIO Controller 1633 */ 1634 #if defined(CONFIG_OF_GPIO) 1635 1636 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1637 const struct of_phandle_args *gpiospec, 1638 u32 *flags) 1639 { 1640 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1641 return -EINVAL; 1642 1643 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1644 return -EINVAL; 1645 1646 if (flags) 1647 *flags = gpiospec->args[1]; 1648 1649 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1650 } 1651 1652 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1653 unsigned int offset) 1654 { 1655 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1656 1657 /* 1658 * We already have to keep track of the direction because we use 1659 * that to figure out whether we've powered the device. We can 1660 * just return that rather than (maybe) powering up the device 1661 * to ask its direction. 1662 */ 1663 return test_bit(offset, pdata->gchip_output) ? 1664 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1665 } 1666 1667 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1668 { 1669 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1670 unsigned int val; 1671 int ret; 1672 1673 /* 1674 * When the pin is an input we don't forcibly keep the bridge 1675 * powered--we just power it on to read the pin. NOTE: part of 1676 * the reason this works is that the bridge defaults (when 1677 * powered back on) to all 4 GPIOs being configured as GPIO input. 1678 * Also note that if something else is keeping the chip powered the 1679 * pm_runtime functions are lightweight increments of a refcount. 1680 */ 1681 pm_runtime_get_sync(pdata->dev); 1682 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1683 pm_runtime_put_autosuspend(pdata->dev); 1684 1685 if (ret) 1686 return ret; 1687 1688 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1689 } 1690 1691 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1692 int val) 1693 { 1694 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1695 int ret; 1696 1697 if (!test_bit(offset, pdata->gchip_output)) { 1698 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); 1699 return; 1700 } 1701 1702 val &= 1; 1703 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1704 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1705 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1706 if (ret) 1707 dev_warn(pdata->dev, 1708 "Failed to set bridge GPIO %u: %d\n", offset, ret); 1709 } 1710 1711 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1712 unsigned int offset) 1713 { 1714 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1715 int shift = offset * 2; 1716 int ret; 1717 1718 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1719 return 0; 1720 1721 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1722 SN_GPIO_MUX_MASK << shift, 1723 SN_GPIO_MUX_INPUT << shift); 1724 if (ret) { 1725 set_bit(offset, pdata->gchip_output); 1726 return ret; 1727 } 1728 1729 /* 1730 * NOTE: if nobody else is powering the device this may fully power 1731 * it off and when it comes back it will have lost all state, but 1732 * that's OK because the default is input and we're now an input. 1733 */ 1734 pm_runtime_put_autosuspend(pdata->dev); 1735 1736 return 0; 1737 } 1738 1739 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1740 unsigned int offset, int val) 1741 { 1742 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1743 int shift = offset * 2; 1744 int ret; 1745 1746 if (test_and_set_bit(offset, pdata->gchip_output)) 1747 return 0; 1748 1749 pm_runtime_get_sync(pdata->dev); 1750 1751 /* Set value first to avoid glitching */ 1752 ti_sn_bridge_gpio_set(chip, offset, val); 1753 1754 /* Set direction */ 1755 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1756 SN_GPIO_MUX_MASK << shift, 1757 SN_GPIO_MUX_OUTPUT << shift); 1758 if (ret) { 1759 clear_bit(offset, pdata->gchip_output); 1760 pm_runtime_put_autosuspend(pdata->dev); 1761 } 1762 1763 return ret; 1764 } 1765 1766 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1767 { 1768 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1769 1770 if (offset == SN_PWM_GPIO_IDX) 1771 return ti_sn_pwm_pin_request(pdata); 1772 1773 return 0; 1774 } 1775 1776 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1777 { 1778 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1779 1780 /* We won't keep pm_runtime if we're input, so switch there on free */ 1781 ti_sn_bridge_gpio_direction_input(chip, offset); 1782 1783 if (offset == SN_PWM_GPIO_IDX) 1784 ti_sn_pwm_pin_release(pdata); 1785 } 1786 1787 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1788 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1789 }; 1790 1791 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1792 const struct auxiliary_device_id *id) 1793 { 1794 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1795 int ret; 1796 1797 /* Only init if someone is going to use us as a GPIO controller */ 1798 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1799 return 0; 1800 1801 pdata->gchip.label = dev_name(pdata->dev); 1802 pdata->gchip.parent = pdata->dev; 1803 pdata->gchip.owner = THIS_MODULE; 1804 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1805 pdata->gchip.of_gpio_n_cells = 2; 1806 pdata->gchip.request = ti_sn_bridge_gpio_request; 1807 pdata->gchip.free = ti_sn_bridge_gpio_free; 1808 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1809 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1810 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1811 pdata->gchip.get = ti_sn_bridge_gpio_get; 1812 pdata->gchip.set = ti_sn_bridge_gpio_set; 1813 pdata->gchip.can_sleep = true; 1814 pdata->gchip.names = ti_sn_bridge_gpio_names; 1815 pdata->gchip.ngpio = SN_NUM_GPIOS; 1816 pdata->gchip.base = -1; 1817 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1818 if (ret) 1819 dev_err(pdata->dev, "can't add gpio chip\n"); 1820 1821 return ret; 1822 } 1823 1824 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1825 { .name = "ti_sn65dsi86.gpio", }, 1826 {}, 1827 }; 1828 1829 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1830 1831 static struct auxiliary_driver ti_sn_gpio_driver = { 1832 .name = "gpio", 1833 .probe = ti_sn_gpio_probe, 1834 .id_table = ti_sn_gpio_id_table, 1835 }; 1836 1837 static int __init ti_sn_gpio_register(void) 1838 { 1839 return auxiliary_driver_register(&ti_sn_gpio_driver); 1840 } 1841 1842 static void ti_sn_gpio_unregister(void) 1843 { 1844 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1845 } 1846 1847 #else 1848 1849 static inline int ti_sn_gpio_register(void) { return 0; } 1850 static inline void ti_sn_gpio_unregister(void) {} 1851 1852 #endif 1853 1854 /* ----------------------------------------------------------------------------- 1855 * Probe & Remove 1856 */ 1857 1858 static void ti_sn65dsi86_runtime_disable(void *data) 1859 { 1860 pm_runtime_dont_use_autosuspend(data); 1861 pm_runtime_disable(data); 1862 } 1863 1864 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1865 { 1866 unsigned int i; 1867 const char * const ti_sn_bridge_supply_names[] = { 1868 "vcca", "vcc", "vccio", "vpll", 1869 }; 1870 1871 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1872 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1873 1874 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1875 pdata->supplies); 1876 } 1877 1878 static int ti_sn65dsi86_probe(struct i2c_client *client) 1879 { 1880 struct device *dev = &client->dev; 1881 struct ti_sn65dsi86 *pdata; 1882 int ret; 1883 1884 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1885 DRM_ERROR("device doesn't support I2C\n"); 1886 return -ENODEV; 1887 } 1888 1889 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL); 1890 if (!pdata) 1891 return -ENOMEM; 1892 dev_set_drvdata(dev, pdata); 1893 pdata->dev = dev; 1894 1895 mutex_init(&pdata->comms_mutex); 1896 1897 pdata->regmap = devm_regmap_init_i2c(client, 1898 &ti_sn65dsi86_regmap_config); 1899 if (IS_ERR(pdata->regmap)) 1900 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1901 "regmap i2c init failed\n"); 1902 1903 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1904 GPIOD_OUT_LOW); 1905 if (IS_ERR(pdata->enable_gpio)) 1906 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1907 "failed to get enable gpio from DT\n"); 1908 1909 ret = ti_sn65dsi86_parse_regulators(pdata); 1910 if (ret) 1911 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1912 1913 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1914 if (IS_ERR(pdata->refclk)) 1915 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1916 "failed to get reference clock\n"); 1917 1918 pm_runtime_enable(dev); 1919 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1920 pm_runtime_use_autosuspend(pdata->dev); 1921 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1922 if (ret) 1923 return ret; 1924 1925 ti_sn65dsi86_debugfs_init(pdata); 1926 1927 /* 1928 * Break ourselves up into a collection of aux devices. The only real 1929 * motiviation here is to solve the chicken-and-egg problem of probe 1930 * ordering. The bridge wants the panel to be there when it probes. 1931 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1932 * when it probes. The panel and maybe backlight might want the DDC 1933 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1934 * to finish probing even if others return -EPROBE_DEFER and gets us 1935 * around the problems. 1936 */ 1937 1938 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1939 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1940 if (ret) 1941 return ret; 1942 } 1943 1944 if (IS_ENABLED(CONFIG_PWM)) { 1945 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1946 if (ret) 1947 return ret; 1948 } 1949 1950 /* 1951 * NOTE: At the end of the AUX channel probe we'll add the aux device 1952 * for the bridge. This is because the bridge can't be used until the 1953 * AUX channel is there and this is a very simple solution to the 1954 * dependency problem. 1955 */ 1956 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 1957 } 1958 1959 static struct i2c_device_id ti_sn65dsi86_id[] = { 1960 { "ti,sn65dsi86", 0}, 1961 {}, 1962 }; 1963 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 1964 1965 static const struct of_device_id ti_sn65dsi86_match_table[] = { 1966 {.compatible = "ti,sn65dsi86"}, 1967 {}, 1968 }; 1969 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 1970 1971 static struct i2c_driver ti_sn65dsi86_driver = { 1972 .driver = { 1973 .name = "ti_sn65dsi86", 1974 .of_match_table = ti_sn65dsi86_match_table, 1975 .pm = &ti_sn65dsi86_pm_ops, 1976 }, 1977 .probe = ti_sn65dsi86_probe, 1978 .id_table = ti_sn65dsi86_id, 1979 }; 1980 1981 static int __init ti_sn65dsi86_init(void) 1982 { 1983 int ret; 1984 1985 ret = i2c_add_driver(&ti_sn65dsi86_driver); 1986 if (ret) 1987 return ret; 1988 1989 ret = ti_sn_gpio_register(); 1990 if (ret) 1991 goto err_main_was_registered; 1992 1993 ret = ti_sn_pwm_register(); 1994 if (ret) 1995 goto err_gpio_was_registered; 1996 1997 ret = auxiliary_driver_register(&ti_sn_aux_driver); 1998 if (ret) 1999 goto err_pwm_was_registered; 2000 2001 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 2002 if (ret) 2003 goto err_aux_was_registered; 2004 2005 return 0; 2006 2007 err_aux_was_registered: 2008 auxiliary_driver_unregister(&ti_sn_aux_driver); 2009 err_pwm_was_registered: 2010 ti_sn_pwm_unregister(); 2011 err_gpio_was_registered: 2012 ti_sn_gpio_unregister(); 2013 err_main_was_registered: 2014 i2c_del_driver(&ti_sn65dsi86_driver); 2015 2016 return ret; 2017 } 2018 module_init(ti_sn65dsi86_init); 2019 2020 static void __exit ti_sn65dsi86_exit(void) 2021 { 2022 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2023 auxiliary_driver_unregister(&ti_sn_aux_driver); 2024 ti_sn_pwm_unregister(); 2025 ti_sn_gpio_unregister(); 2026 i2c_del_driver(&ti_sn65dsi86_driver); 2027 } 2028 module_exit(ti_sn65dsi86_exit); 2029 2030 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2031 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2032 MODULE_LICENSE("GPL v2"); 2033