1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <asm/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_panel.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device bridge_aux; 174 struct auxiliary_device gpio_aux; 175 struct auxiliary_device aux_aux; 176 struct auxiliary_device pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if defined(CONFIG_PWM) 200 struct pwm_chip pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata) 248 { 249 u32 bit_rate_khz, clk_freq_khz; 250 struct drm_display_mode *mode = 251 &pdata->bridge.encoder->crtc->state->adjusted_mode; 252 253 bit_rate_khz = mode->clock * 254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 256 257 return clk_freq_khz; 258 } 259 260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 261 static const u32 ti_sn_bridge_refclk_lut[] = { 262 12000000, 263 19200000, 264 26000000, 265 27000000, 266 38400000, 267 }; 268 269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 270 static const u32 ti_sn_bridge_dsiclk_lut[] = { 271 468000000, 272 384000000, 273 416000000, 274 486000000, 275 460800000, 276 }; 277 278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) 279 { 280 int i; 281 u32 refclk_rate; 282 const u32 *refclk_lut; 283 size_t refclk_lut_size; 284 285 if (pdata->refclk) { 286 refclk_rate = clk_get_rate(pdata->refclk); 287 refclk_lut = ti_sn_bridge_refclk_lut; 288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 289 clk_prepare_enable(pdata->refclk); 290 } else { 291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000; 292 refclk_lut = ti_sn_bridge_dsiclk_lut; 293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 294 } 295 296 /* for i equals to refclk_lut_size means default frequency */ 297 for (i = 0; i < refclk_lut_size; i++) 298 if (refclk_lut[i] == refclk_rate) 299 break; 300 301 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 302 REFCLK_FREQ(i)); 303 304 /* 305 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 306 * regardless of its actual sourcing. 307 */ 308 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 309 } 310 311 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata) 312 { 313 mutex_lock(&pdata->comms_mutex); 314 315 /* configure bridge ref_clk */ 316 ti_sn_bridge_set_refclk_freq(pdata); 317 318 /* 319 * HPD on this bridge chip is a bit useless. This is an eDP bridge 320 * so the HPD is an internal signal that's only there to signal that 321 * the panel is done powering up. ...but the bridge chip debounces 322 * this signal by between 100 ms and 400 ms (depending on process, 323 * voltage, and temperate--I measured it at about 200 ms). One 324 * particular panel asserted HPD 84 ms after it was powered on meaning 325 * that we saw HPD 284 ms after power on. ...but the same panel said 326 * that instead of looking at HPD you could just hardcode a delay of 327 * 200 ms. We'll assume that the panel driver will have the hardcoded 328 * delay in its prepare and always disable HPD. 329 * 330 * If HPD somehow makes sense on some future panel we'll have to 331 * change this to be conditional on someone specifying that HPD should 332 * be used. 333 */ 334 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 335 HPD_DISABLE); 336 337 pdata->comms_enabled = true; 338 339 mutex_unlock(&pdata->comms_mutex); 340 } 341 342 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 343 { 344 mutex_lock(&pdata->comms_mutex); 345 346 pdata->comms_enabled = false; 347 clk_disable_unprepare(pdata->refclk); 348 349 mutex_unlock(&pdata->comms_mutex); 350 } 351 352 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 353 { 354 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 355 int ret; 356 357 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 358 if (ret) { 359 DRM_ERROR("failed to enable supplies %d\n", ret); 360 return ret; 361 } 362 363 /* td2: min 100 us after regulators before enabling the GPIO */ 364 usleep_range(100, 110); 365 366 gpiod_set_value(pdata->enable_gpio, 1); 367 368 /* 369 * If we have a reference clock we can enable communication w/ the 370 * panel (including the aux channel) w/out any need for an input clock 371 * so we can do it in resume which lets us read the EDID before 372 * pre_enable(). Without a reference clock we need the MIPI reference 373 * clock so reading early doesn't work. 374 */ 375 if (pdata->refclk) 376 ti_sn65dsi86_enable_comms(pdata); 377 378 return ret; 379 } 380 381 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 382 { 383 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 384 int ret; 385 386 if (pdata->refclk) 387 ti_sn65dsi86_disable_comms(pdata); 388 389 gpiod_set_value(pdata->enable_gpio, 0); 390 391 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 392 if (ret) 393 DRM_ERROR("failed to disable supplies %d\n", ret); 394 395 return ret; 396 } 397 398 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 399 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 400 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 401 pm_runtime_force_resume) 402 }; 403 404 static int status_show(struct seq_file *s, void *data) 405 { 406 struct ti_sn65dsi86 *pdata = s->private; 407 unsigned int reg, val; 408 409 seq_puts(s, "STATUS REGISTERS:\n"); 410 411 pm_runtime_get_sync(pdata->dev); 412 413 /* IRQ Status Registers, see Table 31 in datasheet */ 414 for (reg = 0xf0; reg <= 0xf8; reg++) { 415 regmap_read(pdata->regmap, reg, &val); 416 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 417 } 418 419 pm_runtime_put_autosuspend(pdata->dev); 420 421 return 0; 422 } 423 424 DEFINE_SHOW_ATTRIBUTE(status); 425 426 static void ti_sn65dsi86_debugfs_remove(void *data) 427 { 428 debugfs_remove_recursive(data); 429 } 430 431 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata) 432 { 433 struct device *dev = pdata->dev; 434 struct dentry *debugfs; 435 int ret; 436 437 debugfs = debugfs_create_dir(dev_name(dev), NULL); 438 439 /* 440 * We might get an error back if debugfs wasn't enabled in the kernel 441 * so let's just silently return upon failure. 442 */ 443 if (IS_ERR_OR_NULL(debugfs)) 444 return; 445 446 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs); 447 if (ret) 448 return; 449 450 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 451 } 452 453 /* ----------------------------------------------------------------------------- 454 * Auxiliary Devices (*not* AUX) 455 */ 456 457 static void ti_sn65dsi86_uninit_aux(void *data) 458 { 459 auxiliary_device_uninit(data); 460 } 461 462 static void ti_sn65dsi86_delete_aux(void *data) 463 { 464 auxiliary_device_delete(data); 465 } 466 467 /* 468 * AUX bus docs say that a non-NULL release is mandatory, but it makes no 469 * sense for the model used here where all of the aux devices are allocated 470 * in the single shared structure. We'll use this noop as a workaround. 471 */ 472 static void ti_sn65dsi86_noop(struct device *dev) {} 473 474 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 475 struct auxiliary_device *aux, 476 const char *name) 477 { 478 struct device *dev = pdata->dev; 479 int ret; 480 481 aux->name = name; 482 aux->dev.parent = dev; 483 aux->dev.release = ti_sn65dsi86_noop; 484 device_set_of_node_from_dev(&aux->dev, dev); 485 ret = auxiliary_device_init(aux); 486 if (ret) 487 return ret; 488 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux); 489 if (ret) 490 return ret; 491 492 ret = auxiliary_device_add(aux); 493 if (ret) 494 return ret; 495 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux); 496 497 return ret; 498 } 499 500 /* ----------------------------------------------------------------------------- 501 * AUX Adapter 502 */ 503 504 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 505 { 506 return container_of(aux, struct ti_sn65dsi86, aux); 507 } 508 509 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 510 struct drm_dp_aux_msg *msg) 511 { 512 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 513 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 514 u32 request_val = AUX_CMD_REQ(msg->request); 515 u8 *buf = msg->buffer; 516 unsigned int len = msg->size; 517 unsigned int val; 518 int ret; 519 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 520 521 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 522 return -EINVAL; 523 524 pm_runtime_get_sync(pdata->dev); 525 mutex_lock(&pdata->comms_mutex); 526 527 /* 528 * If someone tries to do a DDC over AUX transaction before pre_enable() 529 * on a device without a dedicated reference clock then we just can't 530 * do it. Fail right away. This prevents non-refclk users from reading 531 * the EDID before enabling the panel but such is life. 532 */ 533 if (!pdata->comms_enabled) { 534 ret = -EIO; 535 goto exit; 536 } 537 538 switch (request) { 539 case DP_AUX_NATIVE_WRITE: 540 case DP_AUX_I2C_WRITE: 541 case DP_AUX_NATIVE_READ: 542 case DP_AUX_I2C_READ: 543 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 544 /* Assume it's good */ 545 msg->reply = 0; 546 break; 547 default: 548 ret = -EINVAL; 549 goto exit; 550 } 551 552 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 553 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 554 addr_len); 555 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 556 ARRAY_SIZE(addr_len)); 557 558 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 559 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 560 561 /* Clear old status bits before start so we don't get confused */ 562 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 563 AUX_IRQ_STATUS_NAT_I2C_FAIL | 564 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 565 AUX_IRQ_STATUS_AUX_SHORT); 566 567 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 568 569 /* Zero delay loop because i2c transactions are slow already */ 570 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 571 !(val & AUX_CMD_SEND), 0, 50 * 1000); 572 if (ret) 573 goto exit; 574 575 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 576 if (ret) 577 goto exit; 578 579 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 580 /* 581 * The hardware tried the message seven times per the DP spec 582 * but it hit a timeout. We ignore defers here because they're 583 * handled in hardware. 584 */ 585 ret = -ETIMEDOUT; 586 goto exit; 587 } 588 589 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 590 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len); 591 if (ret) 592 goto exit; 593 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 594 switch (request) { 595 case DP_AUX_I2C_WRITE: 596 case DP_AUX_I2C_READ: 597 msg->reply |= DP_AUX_I2C_REPLY_NACK; 598 break; 599 case DP_AUX_NATIVE_READ: 600 case DP_AUX_NATIVE_WRITE: 601 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 602 break; 603 } 604 len = 0; 605 goto exit; 606 } 607 608 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 609 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 610 611 exit: 612 mutex_unlock(&pdata->comms_mutex); 613 pm_runtime_mark_last_busy(pdata->dev); 614 pm_runtime_put_autosuspend(pdata->dev); 615 616 if (ret) 617 return ret; 618 return len; 619 } 620 621 static int ti_sn_aux_probe(struct auxiliary_device *adev, 622 const struct auxiliary_device_id *id) 623 { 624 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 625 int ret; 626 627 pdata->aux.name = "ti-sn65dsi86-aux"; 628 pdata->aux.dev = &adev->dev; 629 pdata->aux.transfer = ti_sn_aux_transfer; 630 drm_dp_aux_init(&pdata->aux); 631 632 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 633 if (ret) 634 return ret; 635 636 /* 637 * The eDP to MIPI bridge parts don't work until the AUX channel is 638 * setup so we don't add it in the main driver probe, we add it now. 639 */ 640 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 641 } 642 643 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 644 { .name = "ti_sn65dsi86.aux", }, 645 {}, 646 }; 647 648 static struct auxiliary_driver ti_sn_aux_driver = { 649 .name = "aux", 650 .probe = ti_sn_aux_probe, 651 .id_table = ti_sn_aux_id_table, 652 }; 653 654 /*------------------------------------------------------------------------------ 655 * DRM Bridge 656 */ 657 658 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 659 { 660 return container_of(bridge, struct ti_sn65dsi86, bridge); 661 } 662 663 static int ti_sn_attach_host(struct ti_sn65dsi86 *pdata) 664 { 665 int val; 666 struct mipi_dsi_host *host; 667 struct mipi_dsi_device *dsi; 668 struct device *dev = pdata->dev; 669 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 670 .channel = 0, 671 .node = NULL, 672 }; 673 674 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 675 if (!host) 676 return -EPROBE_DEFER; 677 678 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 679 if (IS_ERR(dsi)) 680 return PTR_ERR(dsi); 681 682 /* TODO: setting to 4 MIPI lanes always for now */ 683 dsi->lanes = 4; 684 dsi->format = MIPI_DSI_FMT_RGB888; 685 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 686 687 /* check if continuous dsi clock is required or not */ 688 pm_runtime_get_sync(dev); 689 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 690 pm_runtime_put_autosuspend(dev); 691 if (!(val & DPPLL_CLK_SRC_DSICLK)) 692 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 693 694 pdata->dsi = dsi; 695 696 return devm_mipi_dsi_attach(dev, dsi); 697 } 698 699 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 700 enum drm_bridge_attach_flags flags) 701 { 702 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 703 int ret; 704 705 pdata->aux.drm_dev = bridge->dev; 706 ret = drm_dp_aux_register(&pdata->aux); 707 if (ret < 0) { 708 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 709 return ret; 710 } 711 712 /* 713 * Attach the next bridge. 714 * We never want the next bridge to *also* create a connector. 715 */ 716 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge, 717 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 718 if (ret < 0) 719 goto err_initted_aux; 720 721 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 722 return 0; 723 724 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 725 pdata->bridge.encoder); 726 if (IS_ERR(pdata->connector)) { 727 ret = PTR_ERR(pdata->connector); 728 goto err_initted_aux; 729 } 730 731 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 732 733 return 0; 734 735 err_initted_aux: 736 drm_dp_aux_unregister(&pdata->aux); 737 return ret; 738 } 739 740 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 741 { 742 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 743 } 744 745 static enum drm_mode_status 746 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 747 const struct drm_display_info *info, 748 const struct drm_display_mode *mode) 749 { 750 /* maximum supported resolution is 4K at 60 fps */ 751 if (mode->clock > 594000) 752 return MODE_CLOCK_HIGH; 753 754 /* 755 * The front and back porch registers are 8 bits, and pulse width 756 * registers are 15 bits, so reject any modes with larger periods. 757 */ 758 759 if ((mode->hsync_start - mode->hdisplay) > 0xff) 760 return MODE_HBLANK_WIDE; 761 762 if ((mode->vsync_start - mode->vdisplay) > 0xff) 763 return MODE_VBLANK_WIDE; 764 765 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 766 return MODE_HSYNC_WIDE; 767 768 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 769 return MODE_VSYNC_WIDE; 770 771 if ((mode->htotal - mode->hsync_end) > 0xff) 772 return MODE_HBLANK_WIDE; 773 774 if ((mode->vtotal - mode->vsync_end) > 0xff) 775 return MODE_VBLANK_WIDE; 776 777 return MODE_OK; 778 } 779 780 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 781 struct drm_bridge_state *old_bridge_state) 782 { 783 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 784 785 /* disable video stream */ 786 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 787 } 788 789 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata) 790 { 791 unsigned int bit_rate_mhz, clk_freq_mhz; 792 unsigned int val; 793 struct drm_display_mode *mode = 794 &pdata->bridge.encoder->crtc->state->adjusted_mode; 795 796 /* set DSIA clk frequency */ 797 bit_rate_mhz = (mode->clock / 1000) * 798 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 799 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 800 801 /* for each increment in val, frequency increases by 5MHz */ 802 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 803 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 804 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 805 } 806 807 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 808 { 809 if (connector->display_info.bpc <= 6) 810 return 18; 811 else 812 return 24; 813 } 814 815 /* 816 * LUT index corresponds to register value and 817 * LUT values corresponds to dp data rate supported 818 * by the bridge in Mbps unit. 819 */ 820 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 821 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 822 }; 823 824 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp) 825 { 826 unsigned int bit_rate_khz, dp_rate_mhz; 827 unsigned int i; 828 struct drm_display_mode *mode = 829 &pdata->bridge.encoder->crtc->state->adjusted_mode; 830 831 /* Calculate minimum bit rate based on our pixel clock. */ 832 bit_rate_khz = mode->clock * bpp; 833 834 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 835 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 836 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 837 838 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 839 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 840 break; 841 842 return i; 843 } 844 845 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 846 { 847 unsigned int valid_rates = 0; 848 unsigned int rate_per_200khz; 849 unsigned int rate_mhz; 850 u8 dpcd_val; 851 int ret; 852 int i, j; 853 854 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 855 if (ret != 1) { 856 DRM_DEV_ERROR(pdata->dev, 857 "Can't read eDP rev (%d), assuming 1.1\n", ret); 858 dpcd_val = DP_EDP_11; 859 } 860 861 if (dpcd_val >= DP_EDP_14) { 862 /* eDP 1.4 devices must provide a custom table */ 863 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 864 865 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 866 sink_rates, sizeof(sink_rates)); 867 868 if (ret != sizeof(sink_rates)) { 869 DRM_DEV_ERROR(pdata->dev, 870 "Can't read supported rate table (%d)\n", ret); 871 872 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 873 memset(sink_rates, 0, sizeof(sink_rates)); 874 } 875 876 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 877 rate_per_200khz = le16_to_cpu(sink_rates[i]); 878 879 if (!rate_per_200khz) 880 break; 881 882 rate_mhz = rate_per_200khz * 200 / 1000; 883 for (j = 0; 884 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 885 j++) { 886 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 887 valid_rates |= BIT(j); 888 } 889 } 890 891 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 892 if (valid_rates & BIT(i)) 893 return valid_rates; 894 } 895 DRM_DEV_ERROR(pdata->dev, 896 "No matching eDP rates in table; falling back\n"); 897 } 898 899 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 900 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 901 if (ret != 1) { 902 DRM_DEV_ERROR(pdata->dev, 903 "Can't read max rate (%d); assuming 5.4 GHz\n", 904 ret); 905 dpcd_val = DP_LINK_BW_5_4; 906 } 907 908 switch (dpcd_val) { 909 default: 910 DRM_DEV_ERROR(pdata->dev, 911 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 912 (int)dpcd_val); 913 fallthrough; 914 case DP_LINK_BW_5_4: 915 valid_rates |= BIT(7); 916 fallthrough; 917 case DP_LINK_BW_2_7: 918 valid_rates |= BIT(4); 919 fallthrough; 920 case DP_LINK_BW_1_62: 921 valid_rates |= BIT(1); 922 break; 923 } 924 925 return valid_rates; 926 } 927 928 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata) 929 { 930 struct drm_display_mode *mode = 931 &pdata->bridge.encoder->crtc->state->adjusted_mode; 932 u8 hsync_polarity = 0, vsync_polarity = 0; 933 934 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 935 hsync_polarity = CHA_HSYNC_POLARITY; 936 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 937 vsync_polarity = CHA_VSYNC_POLARITY; 938 939 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 940 mode->hdisplay); 941 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 942 mode->vdisplay); 943 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 944 (mode->hsync_end - mode->hsync_start) & 0xFF); 945 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 946 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 947 hsync_polarity); 948 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 949 (mode->vsync_end - mode->vsync_start) & 0xFF); 950 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 951 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 952 vsync_polarity); 953 954 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 955 (mode->htotal - mode->hsync_end) & 0xFF); 956 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 957 (mode->vtotal - mode->vsync_end) & 0xFF); 958 959 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 960 (mode->hsync_start - mode->hdisplay) & 0xFF); 961 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 962 (mode->vsync_start - mode->vdisplay) & 0xFF); 963 964 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 965 } 966 967 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 968 { 969 u8 data; 970 int ret; 971 972 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 973 if (ret != 1) { 974 DRM_DEV_ERROR(pdata->dev, 975 "Can't read lane count (%d); assuming 4\n", ret); 976 return 4; 977 } 978 979 return data & DP_LANE_COUNT_MASK; 980 } 981 982 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 983 const char **last_err_str) 984 { 985 unsigned int val; 986 int ret; 987 int i; 988 989 /* set dp clk frequency value */ 990 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 991 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 992 993 /* enable DP PLL */ 994 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 995 996 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 997 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 998 50 * 1000); 999 if (ret) { 1000 *last_err_str = "DP_PLL_LOCK polling failed"; 1001 goto exit; 1002 } 1003 1004 /* 1005 * We'll try to link train several times. As part of link training 1006 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1007 * the panel isn't ready quite it might respond NAK here which means 1008 * we need to try again. 1009 */ 1010 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1011 /* Semi auto link training mode */ 1012 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1013 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1014 val == ML_TX_MAIN_LINK_OFF || 1015 val == ML_TX_NORMAL_MODE, 1000, 1016 500 * 1000); 1017 if (ret) { 1018 *last_err_str = "Training complete polling failed"; 1019 } else if (val == ML_TX_MAIN_LINK_OFF) { 1020 *last_err_str = "Link training failed, link is off"; 1021 ret = -EIO; 1022 continue; 1023 } 1024 1025 break; 1026 } 1027 1028 /* If we saw quite a few retries, add a note about it */ 1029 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1030 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1031 1032 exit: 1033 /* Disable the PLL if we failed */ 1034 if (ret) 1035 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1036 1037 return ret; 1038 } 1039 1040 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1041 struct drm_bridge_state *old_bridge_state) 1042 { 1043 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1044 struct drm_connector *connector; 1045 const char *last_err_str = "No supported DP rate"; 1046 unsigned int valid_rates; 1047 int dp_rate_idx; 1048 unsigned int val; 1049 int ret = -EINVAL; 1050 int max_dp_lanes; 1051 unsigned int bpp; 1052 1053 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state, 1054 bridge->encoder); 1055 if (!connector) { 1056 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1057 return; 1058 } 1059 1060 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1061 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1062 1063 /* DSI_A lane config */ 1064 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1065 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1066 CHA_DSI_LANES_MASK, val); 1067 1068 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1069 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1070 pdata->ln_polrs << LN_POLRS_OFFSET); 1071 1072 /* set dsi clk frequency value */ 1073 ti_sn_bridge_set_dsi_rate(pdata); 1074 1075 /* 1076 * The SN65DSI86 only supports ASSR Display Authentication method and 1077 * this method is enabled for eDP panels. An eDP panel must support this 1078 * authentication method. We need to enable this method in the eDP panel 1079 * at DisplayPort address 0x0010A prior to link training. 1080 * 1081 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1082 * we need to disable the scrambler. 1083 */ 1084 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1085 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1086 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1087 1088 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1089 SCRAMBLE_DISABLE, 0); 1090 } else { 1091 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1092 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1093 } 1094 1095 bpp = ti_sn_bridge_get_bpp(connector); 1096 /* Set the DP output format (18 bpp or 24 bpp) */ 1097 val = bpp == 18 ? BPP_18_RGB : 0; 1098 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1099 1100 /* DP lane config */ 1101 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1102 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1103 val); 1104 1105 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1106 1107 /* Train until we run out of rates */ 1108 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp); 1109 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1110 dp_rate_idx++) { 1111 if (!(valid_rates & BIT(dp_rate_idx))) 1112 continue; 1113 1114 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1115 if (!ret) 1116 break; 1117 } 1118 if (ret) { 1119 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1120 return; 1121 } 1122 1123 /* config video parameters */ 1124 ti_sn_bridge_set_video_timings(pdata); 1125 1126 /* enable video stream */ 1127 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1128 VSTREAM_ENABLE); 1129 } 1130 1131 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1132 struct drm_bridge_state *old_bridge_state) 1133 { 1134 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1135 1136 pm_runtime_get_sync(pdata->dev); 1137 1138 if (!pdata->refclk) 1139 ti_sn65dsi86_enable_comms(pdata); 1140 1141 /* td7: min 100 us after enable before DSI data */ 1142 usleep_range(100, 110); 1143 } 1144 1145 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1146 struct drm_bridge_state *old_bridge_state) 1147 { 1148 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1149 1150 /* semi auto link training mode OFF */ 1151 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1152 /* Num lanes to 0 as per power sequencing in data sheet */ 1153 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1154 /* disable DP PLL */ 1155 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1156 1157 if (!pdata->refclk) 1158 ti_sn65dsi86_disable_comms(pdata); 1159 1160 pm_runtime_put_sync(pdata->dev); 1161 } 1162 1163 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge) 1164 { 1165 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1166 int val = 0; 1167 1168 pm_runtime_get_sync(pdata->dev); 1169 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1170 pm_runtime_put_autosuspend(pdata->dev); 1171 1172 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1173 : connector_status_disconnected; 1174 } 1175 1176 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge, 1177 struct drm_connector *connector) 1178 { 1179 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1180 1181 return drm_get_edid(connector, &pdata->aux.ddc); 1182 } 1183 1184 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1185 .attach = ti_sn_bridge_attach, 1186 .detach = ti_sn_bridge_detach, 1187 .mode_valid = ti_sn_bridge_mode_valid, 1188 .get_edid = ti_sn_bridge_get_edid, 1189 .detect = ti_sn_bridge_detect, 1190 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1191 .atomic_enable = ti_sn_bridge_atomic_enable, 1192 .atomic_disable = ti_sn_bridge_atomic_disable, 1193 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1194 .atomic_reset = drm_atomic_helper_bridge_reset, 1195 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1196 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1197 }; 1198 1199 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1200 struct device_node *np) 1201 { 1202 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1203 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1204 struct device_node *endpoint; 1205 u8 ln_assign = 0; 1206 u8 ln_polrs = 0; 1207 int dp_lanes; 1208 int i; 1209 1210 /* 1211 * Read config from the device tree about lane remapping and lane 1212 * polarities. These are optional and we assume identity map and 1213 * normal polarity if nothing is specified. It's OK to specify just 1214 * data-lanes but not lane-polarities but not vice versa. 1215 * 1216 * Error checking is light (we just make sure we don't crash or 1217 * buffer overrun) and we assume dts is well formed and specifying 1218 * mappings that the hardware supports. 1219 */ 1220 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1221 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1222 if (dp_lanes > 0) { 1223 of_property_read_u32_array(endpoint, "data-lanes", 1224 lane_assignments, dp_lanes); 1225 of_property_read_u32_array(endpoint, "lane-polarities", 1226 lane_polarities, dp_lanes); 1227 } else { 1228 dp_lanes = SN_MAX_DP_LANES; 1229 } 1230 of_node_put(endpoint); 1231 1232 /* 1233 * Convert into register format. Loop over all lanes even if 1234 * data-lanes had fewer elements so that we nicely initialize 1235 * the LN_ASSIGN register. 1236 */ 1237 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1238 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1239 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1240 } 1241 1242 /* Stash in our struct for when we power on */ 1243 pdata->dp_lanes = dp_lanes; 1244 pdata->ln_assign = ln_assign; 1245 pdata->ln_polrs = ln_polrs; 1246 } 1247 1248 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1249 { 1250 struct device_node *np = pdata->dev->of_node; 1251 1252 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1253 1254 if (!pdata->host_node) { 1255 DRM_ERROR("remote dsi host node not found\n"); 1256 return -ENODEV; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1263 const struct auxiliary_device_id *id) 1264 { 1265 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1266 struct device_node *np = pdata->dev->of_node; 1267 int ret; 1268 1269 pdata->next_bridge = devm_drm_of_get_bridge(pdata->dev, np, 1, 0); 1270 if (IS_ERR(pdata->next_bridge)) 1271 return dev_err_probe(pdata->dev, PTR_ERR(pdata->next_bridge), 1272 "failed to create panel bridge\n"); 1273 1274 ti_sn_bridge_parse_lanes(pdata, np); 1275 1276 ret = ti_sn_bridge_parse_dsi_host(pdata); 1277 if (ret) 1278 return ret; 1279 1280 pdata->bridge.funcs = &ti_sn_bridge_funcs; 1281 pdata->bridge.of_node = np; 1282 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1283 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1284 1285 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) 1286 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 1287 1288 drm_bridge_add(&pdata->bridge); 1289 1290 ret = ti_sn_attach_host(pdata); 1291 if (ret) { 1292 dev_err_probe(pdata->dev, ret, "failed to attach dsi host\n"); 1293 goto err_remove_bridge; 1294 } 1295 1296 return 0; 1297 1298 err_remove_bridge: 1299 drm_bridge_remove(&pdata->bridge); 1300 return ret; 1301 } 1302 1303 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1304 { 1305 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1306 1307 if (!pdata) 1308 return; 1309 1310 drm_bridge_remove(&pdata->bridge); 1311 1312 of_node_put(pdata->host_node); 1313 } 1314 1315 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1316 { .name = "ti_sn65dsi86.bridge", }, 1317 {}, 1318 }; 1319 1320 static struct auxiliary_driver ti_sn_bridge_driver = { 1321 .name = "bridge", 1322 .probe = ti_sn_bridge_probe, 1323 .remove = ti_sn_bridge_remove, 1324 .id_table = ti_sn_bridge_id_table, 1325 }; 1326 1327 /* ----------------------------------------------------------------------------- 1328 * PWM Controller 1329 */ 1330 #if defined(CONFIG_PWM) 1331 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1332 { 1333 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1334 } 1335 1336 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1337 { 1338 atomic_set(&pdata->pwm_pin_busy, 0); 1339 } 1340 1341 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1342 { 1343 return container_of(chip, struct ti_sn65dsi86, pchip); 1344 } 1345 1346 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1347 { 1348 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1349 1350 return ti_sn_pwm_pin_request(pdata); 1351 } 1352 1353 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1354 { 1355 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1356 1357 ti_sn_pwm_pin_release(pdata); 1358 } 1359 1360 /* 1361 * Limitations: 1362 * - The PWM signal is not driven when the chip is powered down, or in its 1363 * reset state and the driver does not implement the "suspend state" 1364 * described in the documentation. In order to save power, state->enabled is 1365 * interpreted as denoting if the signal is expected to be valid, and is used 1366 * to determine if the chip needs to be kept powered. 1367 * - Changing both period and duty_cycle is not done atomically, neither is the 1368 * multi-byte register updates, so the output might briefly be undefined 1369 * during update. 1370 */ 1371 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1372 const struct pwm_state *state) 1373 { 1374 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1375 unsigned int pwm_en_inv; 1376 unsigned int backlight; 1377 unsigned int pre_div; 1378 unsigned int scale; 1379 u64 period_max; 1380 u64 period; 1381 int ret; 1382 1383 if (!pdata->pwm_enabled) { 1384 ret = pm_runtime_get_sync(pdata->dev); 1385 if (ret < 0) { 1386 pm_runtime_put_sync(pdata->dev); 1387 return ret; 1388 } 1389 } 1390 1391 if (state->enabled) { 1392 if (!pdata->pwm_enabled) { 1393 /* 1394 * The chip might have been powered down while we 1395 * didn't hold a PM runtime reference, so mux in the 1396 * PWM function on the GPIO pin again. 1397 */ 1398 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1399 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1400 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1401 if (ret) { 1402 dev_err(pdata->dev, "failed to mux in PWM function\n"); 1403 goto out; 1404 } 1405 } 1406 1407 /* 1408 * Per the datasheet the PWM frequency is given by: 1409 * 1410 * REFCLK_FREQ 1411 * PWM_FREQ = ----------------------------------- 1412 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1413 * 1414 * However, after careful review the author is convinced that 1415 * the documentation has lost some parenthesis around 1416 * "BACKLIGHT_SCALE + 1". 1417 * 1418 * With the period T_pwm = 1/PWM_FREQ this can be written: 1419 * 1420 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1421 * 1422 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1423 * PWM_PRE_DIV must be: 1424 * 1425 * T_pwm * REFCLK_FREQ 1426 * PWM_PRE_DIV >= ------------------------- 1427 * BACKLIGHT_SCALE_MAX + 1 1428 * 1429 * To simplify the search and to favour higher resolution of 1430 * the duty cycle over accuracy of the period, the lowest 1431 * possible PWM_PRE_DIV is used. Finally the scale is 1432 * calculated as: 1433 * 1434 * T_pwm * REFCLK_FREQ 1435 * BACKLIGHT_SCALE = ---------------------- - 1 1436 * PWM_PRE_DIV 1437 * 1438 * Here T_pwm is represented in seconds, so appropriate scaling 1439 * to nanoseconds is necessary. 1440 */ 1441 1442 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1443 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1444 ret = -EINVAL; 1445 goto out; 1446 } 1447 1448 /* 1449 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1450 * Limit period to this to avoid overflows 1451 */ 1452 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1453 pdata->pwm_refclk_freq); 1454 period = min(state->period, period_max); 1455 1456 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1457 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1458 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1459 1460 /* 1461 * The documentation has the duty ratio given as: 1462 * 1463 * duty BACKLIGHT 1464 * ------- = --------------------- 1465 * period BACKLIGHT_SCALE + 1 1466 * 1467 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1468 * to definition above and adjusting for nanosecond 1469 * representation of duty cycle gives us: 1470 */ 1471 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1472 (u64)NSEC_PER_SEC * pre_div); 1473 if (backlight > scale) 1474 backlight = scale; 1475 1476 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1477 if (ret) { 1478 dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n"); 1479 goto out; 1480 } 1481 1482 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1483 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1484 } 1485 1486 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1487 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1488 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1489 if (ret) { 1490 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n"); 1491 goto out; 1492 } 1493 1494 pdata->pwm_enabled = state->enabled; 1495 out: 1496 1497 if (!pdata->pwm_enabled) 1498 pm_runtime_put_sync(pdata->dev); 1499 1500 return ret; 1501 } 1502 1503 static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1504 struct pwm_state *state) 1505 { 1506 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1507 unsigned int pwm_en_inv; 1508 unsigned int pre_div; 1509 u16 backlight; 1510 u16 scale; 1511 int ret; 1512 1513 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1514 if (ret) 1515 return; 1516 1517 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1518 if (ret) 1519 return; 1520 1521 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1522 if (ret) 1523 return; 1524 1525 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1526 if (ret) 1527 return; 1528 1529 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1530 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1531 state->polarity = PWM_POLARITY_INVERSED; 1532 else 1533 state->polarity = PWM_POLARITY_NORMAL; 1534 1535 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1536 pdata->pwm_refclk_freq); 1537 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1538 pdata->pwm_refclk_freq); 1539 1540 if (state->duty_cycle > state->period) 1541 state->duty_cycle = state->period; 1542 } 1543 1544 static const struct pwm_ops ti_sn_pwm_ops = { 1545 .request = ti_sn_pwm_request, 1546 .free = ti_sn_pwm_free, 1547 .apply = ti_sn_pwm_apply, 1548 .get_state = ti_sn_pwm_get_state, 1549 .owner = THIS_MODULE, 1550 }; 1551 1552 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1553 const struct auxiliary_device_id *id) 1554 { 1555 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1556 1557 pdata->pchip.dev = pdata->dev; 1558 pdata->pchip.ops = &ti_sn_pwm_ops; 1559 pdata->pchip.npwm = 1; 1560 pdata->pchip.of_xlate = of_pwm_single_xlate; 1561 pdata->pchip.of_pwm_n_cells = 1; 1562 1563 return pwmchip_add(&pdata->pchip); 1564 } 1565 1566 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1567 { 1568 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1569 1570 pwmchip_remove(&pdata->pchip); 1571 1572 if (pdata->pwm_enabled) 1573 pm_runtime_put_sync(pdata->dev); 1574 } 1575 1576 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1577 { .name = "ti_sn65dsi86.pwm", }, 1578 {}, 1579 }; 1580 1581 static struct auxiliary_driver ti_sn_pwm_driver = { 1582 .name = "pwm", 1583 .probe = ti_sn_pwm_probe, 1584 .remove = ti_sn_pwm_remove, 1585 .id_table = ti_sn_pwm_id_table, 1586 }; 1587 1588 static int __init ti_sn_pwm_register(void) 1589 { 1590 return auxiliary_driver_register(&ti_sn_pwm_driver); 1591 } 1592 1593 static void ti_sn_pwm_unregister(void) 1594 { 1595 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1596 } 1597 1598 #else 1599 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1600 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1601 1602 static inline int ti_sn_pwm_register(void) { return 0; } 1603 static inline void ti_sn_pwm_unregister(void) {} 1604 #endif 1605 1606 /* ----------------------------------------------------------------------------- 1607 * GPIO Controller 1608 */ 1609 #if defined(CONFIG_OF_GPIO) 1610 1611 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1612 const struct of_phandle_args *gpiospec, 1613 u32 *flags) 1614 { 1615 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1616 return -EINVAL; 1617 1618 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1619 return -EINVAL; 1620 1621 if (flags) 1622 *flags = gpiospec->args[1]; 1623 1624 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1625 } 1626 1627 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1628 unsigned int offset) 1629 { 1630 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1631 1632 /* 1633 * We already have to keep track of the direction because we use 1634 * that to figure out whether we've powered the device. We can 1635 * just return that rather than (maybe) powering up the device 1636 * to ask its direction. 1637 */ 1638 return test_bit(offset, pdata->gchip_output) ? 1639 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1640 } 1641 1642 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1643 { 1644 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1645 unsigned int val; 1646 int ret; 1647 1648 /* 1649 * When the pin is an input we don't forcibly keep the bridge 1650 * powered--we just power it on to read the pin. NOTE: part of 1651 * the reason this works is that the bridge defaults (when 1652 * powered back on) to all 4 GPIOs being configured as GPIO input. 1653 * Also note that if something else is keeping the chip powered the 1654 * pm_runtime functions are lightweight increments of a refcount. 1655 */ 1656 pm_runtime_get_sync(pdata->dev); 1657 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1658 pm_runtime_put_autosuspend(pdata->dev); 1659 1660 if (ret) 1661 return ret; 1662 1663 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1664 } 1665 1666 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1667 int val) 1668 { 1669 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1670 int ret; 1671 1672 if (!test_bit(offset, pdata->gchip_output)) { 1673 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); 1674 return; 1675 } 1676 1677 val &= 1; 1678 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1679 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1680 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1681 if (ret) 1682 dev_warn(pdata->dev, 1683 "Failed to set bridge GPIO %u: %d\n", offset, ret); 1684 } 1685 1686 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1687 unsigned int offset) 1688 { 1689 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1690 int shift = offset * 2; 1691 int ret; 1692 1693 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1694 return 0; 1695 1696 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1697 SN_GPIO_MUX_MASK << shift, 1698 SN_GPIO_MUX_INPUT << shift); 1699 if (ret) { 1700 set_bit(offset, pdata->gchip_output); 1701 return ret; 1702 } 1703 1704 /* 1705 * NOTE: if nobody else is powering the device this may fully power 1706 * it off and when it comes back it will have lost all state, but 1707 * that's OK because the default is input and we're now an input. 1708 */ 1709 pm_runtime_put_autosuspend(pdata->dev); 1710 1711 return 0; 1712 } 1713 1714 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1715 unsigned int offset, int val) 1716 { 1717 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1718 int shift = offset * 2; 1719 int ret; 1720 1721 if (test_and_set_bit(offset, pdata->gchip_output)) 1722 return 0; 1723 1724 pm_runtime_get_sync(pdata->dev); 1725 1726 /* Set value first to avoid glitching */ 1727 ti_sn_bridge_gpio_set(chip, offset, val); 1728 1729 /* Set direction */ 1730 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1731 SN_GPIO_MUX_MASK << shift, 1732 SN_GPIO_MUX_OUTPUT << shift); 1733 if (ret) { 1734 clear_bit(offset, pdata->gchip_output); 1735 pm_runtime_put_autosuspend(pdata->dev); 1736 } 1737 1738 return ret; 1739 } 1740 1741 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1742 { 1743 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1744 1745 if (offset == SN_PWM_GPIO_IDX) 1746 return ti_sn_pwm_pin_request(pdata); 1747 1748 return 0; 1749 } 1750 1751 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1752 { 1753 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1754 1755 /* We won't keep pm_runtime if we're input, so switch there on free */ 1756 ti_sn_bridge_gpio_direction_input(chip, offset); 1757 1758 if (offset == SN_PWM_GPIO_IDX) 1759 ti_sn_pwm_pin_release(pdata); 1760 } 1761 1762 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1763 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1764 }; 1765 1766 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1767 const struct auxiliary_device_id *id) 1768 { 1769 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1770 int ret; 1771 1772 /* Only init if someone is going to use us as a GPIO controller */ 1773 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1774 return 0; 1775 1776 pdata->gchip.label = dev_name(pdata->dev); 1777 pdata->gchip.parent = pdata->dev; 1778 pdata->gchip.owner = THIS_MODULE; 1779 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1780 pdata->gchip.of_gpio_n_cells = 2; 1781 pdata->gchip.request = ti_sn_bridge_gpio_request; 1782 pdata->gchip.free = ti_sn_bridge_gpio_free; 1783 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1784 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1785 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1786 pdata->gchip.get = ti_sn_bridge_gpio_get; 1787 pdata->gchip.set = ti_sn_bridge_gpio_set; 1788 pdata->gchip.can_sleep = true; 1789 pdata->gchip.names = ti_sn_bridge_gpio_names; 1790 pdata->gchip.ngpio = SN_NUM_GPIOS; 1791 pdata->gchip.base = -1; 1792 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1793 if (ret) 1794 dev_err(pdata->dev, "can't add gpio chip\n"); 1795 1796 return ret; 1797 } 1798 1799 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1800 { .name = "ti_sn65dsi86.gpio", }, 1801 {}, 1802 }; 1803 1804 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1805 1806 static struct auxiliary_driver ti_sn_gpio_driver = { 1807 .name = "gpio", 1808 .probe = ti_sn_gpio_probe, 1809 .id_table = ti_sn_gpio_id_table, 1810 }; 1811 1812 static int __init ti_sn_gpio_register(void) 1813 { 1814 return auxiliary_driver_register(&ti_sn_gpio_driver); 1815 } 1816 1817 static void ti_sn_gpio_unregister(void) 1818 { 1819 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1820 } 1821 1822 #else 1823 1824 static inline int ti_sn_gpio_register(void) { return 0; } 1825 static inline void ti_sn_gpio_unregister(void) {} 1826 1827 #endif 1828 1829 /* ----------------------------------------------------------------------------- 1830 * Probe & Remove 1831 */ 1832 1833 static void ti_sn65dsi86_runtime_disable(void *data) 1834 { 1835 pm_runtime_dont_use_autosuspend(data); 1836 pm_runtime_disable(data); 1837 } 1838 1839 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1840 { 1841 unsigned int i; 1842 const char * const ti_sn_bridge_supply_names[] = { 1843 "vcca", "vcc", "vccio", "vpll", 1844 }; 1845 1846 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1847 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1848 1849 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1850 pdata->supplies); 1851 } 1852 1853 static int ti_sn65dsi86_probe(struct i2c_client *client, 1854 const struct i2c_device_id *id) 1855 { 1856 struct device *dev = &client->dev; 1857 struct ti_sn65dsi86 *pdata; 1858 int ret; 1859 1860 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1861 DRM_ERROR("device doesn't support I2C\n"); 1862 return -ENODEV; 1863 } 1864 1865 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL); 1866 if (!pdata) 1867 return -ENOMEM; 1868 dev_set_drvdata(dev, pdata); 1869 pdata->dev = dev; 1870 1871 mutex_init(&pdata->comms_mutex); 1872 1873 pdata->regmap = devm_regmap_init_i2c(client, 1874 &ti_sn65dsi86_regmap_config); 1875 if (IS_ERR(pdata->regmap)) 1876 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1877 "regmap i2c init failed\n"); 1878 1879 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1880 GPIOD_OUT_LOW); 1881 if (IS_ERR(pdata->enable_gpio)) 1882 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1883 "failed to get enable gpio from DT\n"); 1884 1885 ret = ti_sn65dsi86_parse_regulators(pdata); 1886 if (ret) 1887 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1888 1889 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1890 if (IS_ERR(pdata->refclk)) 1891 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1892 "failed to get reference clock\n"); 1893 1894 pm_runtime_enable(dev); 1895 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1896 pm_runtime_use_autosuspend(pdata->dev); 1897 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1898 if (ret) 1899 return ret; 1900 1901 ti_sn65dsi86_debugfs_init(pdata); 1902 1903 /* 1904 * Break ourselves up into a collection of aux devices. The only real 1905 * motiviation here is to solve the chicken-and-egg problem of probe 1906 * ordering. The bridge wants the panel to be there when it probes. 1907 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1908 * when it probes. The panel and maybe backlight might want the DDC 1909 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1910 * to finish probing even if others return -EPROBE_DEFER and gets us 1911 * around the problems. 1912 */ 1913 1914 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1915 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1916 if (ret) 1917 return ret; 1918 } 1919 1920 if (IS_ENABLED(CONFIG_PWM)) { 1921 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1922 if (ret) 1923 return ret; 1924 } 1925 1926 /* 1927 * NOTE: At the end of the AUX channel probe we'll add the aux device 1928 * for the bridge. This is because the bridge can't be used until the 1929 * AUX channel is there and this is a very simple solution to the 1930 * dependency problem. 1931 */ 1932 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 1933 } 1934 1935 static struct i2c_device_id ti_sn65dsi86_id[] = { 1936 { "ti,sn65dsi86", 0}, 1937 {}, 1938 }; 1939 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 1940 1941 static const struct of_device_id ti_sn65dsi86_match_table[] = { 1942 {.compatible = "ti,sn65dsi86"}, 1943 {}, 1944 }; 1945 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 1946 1947 static struct i2c_driver ti_sn65dsi86_driver = { 1948 .driver = { 1949 .name = "ti_sn65dsi86", 1950 .of_match_table = ti_sn65dsi86_match_table, 1951 .pm = &ti_sn65dsi86_pm_ops, 1952 }, 1953 .probe = ti_sn65dsi86_probe, 1954 .id_table = ti_sn65dsi86_id, 1955 }; 1956 1957 static int __init ti_sn65dsi86_init(void) 1958 { 1959 int ret; 1960 1961 ret = i2c_add_driver(&ti_sn65dsi86_driver); 1962 if (ret) 1963 return ret; 1964 1965 ret = ti_sn_gpio_register(); 1966 if (ret) 1967 goto err_main_was_registered; 1968 1969 ret = ti_sn_pwm_register(); 1970 if (ret) 1971 goto err_gpio_was_registered; 1972 1973 ret = auxiliary_driver_register(&ti_sn_aux_driver); 1974 if (ret) 1975 goto err_pwm_was_registered; 1976 1977 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 1978 if (ret) 1979 goto err_aux_was_registered; 1980 1981 return 0; 1982 1983 err_aux_was_registered: 1984 auxiliary_driver_unregister(&ti_sn_aux_driver); 1985 err_pwm_was_registered: 1986 ti_sn_pwm_unregister(); 1987 err_gpio_was_registered: 1988 ti_sn_gpio_unregister(); 1989 err_main_was_registered: 1990 i2c_del_driver(&ti_sn65dsi86_driver); 1991 1992 return ret; 1993 } 1994 module_init(ti_sn65dsi86_init); 1995 1996 static void __exit ti_sn65dsi86_exit(void) 1997 { 1998 auxiliary_driver_unregister(&ti_sn_bridge_driver); 1999 auxiliary_driver_unregister(&ti_sn_aux_driver); 2000 ti_sn_pwm_unregister(); 2001 ti_sn_gpio_unregister(); 2002 i2c_del_driver(&ti_sn65dsi86_driver); 2003 } 2004 module_exit(ti_sn65dsi86_exit); 2005 2006 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2007 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2008 MODULE_LICENSE("GPL v2"); 2009