1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/debugfs.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/i2c.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_graph.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 20 #include <asm/unaligned.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_dp_helper.h> 26 #include <drm/drm_mipi_dsi.h> 27 #include <drm/drm_of.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_probe_helper.h> 31 32 #define SN_DEVICE_REV_REG 0x08 33 #define SN_DPPLL_SRC_REG 0x0A 34 #define DPPLL_CLK_SRC_DSICLK BIT(0) 35 #define REFCLK_FREQ_MASK GENMASK(3, 1) 36 #define REFCLK_FREQ(x) ((x) << 1) 37 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 38 #define SN_PLL_ENABLE_REG 0x0D 39 #define SN_DSI_LANES_REG 0x10 40 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 41 #define CHA_DSI_LANES(x) ((x) << 3) 42 #define SN_DSIA_CLK_FREQ_REG 0x12 43 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 44 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 45 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 46 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 47 #define CHA_HSYNC_POLARITY BIT(7) 48 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 49 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 50 #define CHA_VSYNC_POLARITY BIT(7) 51 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 52 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 53 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 54 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 55 #define SN_LN_ASSIGN_REG 0x59 56 #define LN_ASSIGN_WIDTH 2 57 #define SN_ENH_FRAME_REG 0x5A 58 #define VSTREAM_ENABLE BIT(3) 59 #define LN_POLRS_OFFSET 4 60 #define LN_POLRS_MASK 0xf0 61 #define SN_DATA_FORMAT_REG 0x5B 62 #define BPP_18_RGB BIT(0) 63 #define SN_HPD_DISABLE_REG 0x5C 64 #define HPD_DISABLE BIT(0) 65 #define SN_GPIO_IO_REG 0x5E 66 #define SN_GPIO_INPUT_SHIFT 4 67 #define SN_GPIO_OUTPUT_SHIFT 0 68 #define SN_GPIO_CTRL_REG 0x5F 69 #define SN_GPIO_MUX_INPUT 0 70 #define SN_GPIO_MUX_OUTPUT 1 71 #define SN_GPIO_MUX_SPECIAL 2 72 #define SN_GPIO_MUX_MASK 0x3 73 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 74 #define SN_AUX_ADDR_19_16_REG 0x74 75 #define SN_AUX_ADDR_15_8_REG 0x75 76 #define SN_AUX_ADDR_7_0_REG 0x76 77 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 78 #define SN_AUX_LENGTH_REG 0x77 79 #define SN_AUX_CMD_REG 0x78 80 #define AUX_CMD_SEND BIT(0) 81 #define AUX_CMD_REQ(x) ((x) << 4) 82 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 83 #define SN_SSC_CONFIG_REG 0x93 84 #define DP_NUM_LANES_MASK GENMASK(5, 4) 85 #define DP_NUM_LANES(x) ((x) << 4) 86 #define SN_DATARATE_CONFIG_REG 0x94 87 #define DP_DATARATE_MASK GENMASK(7, 5) 88 #define DP_DATARATE(x) ((x) << 5) 89 #define SN_ML_TX_MODE_REG 0x96 90 #define ML_TX_MAIN_LINK_OFF 0 91 #define ML_TX_NORMAL_MODE BIT(0) 92 #define SN_AUX_CMD_STATUS_REG 0xF4 93 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 94 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 95 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 96 97 #define MIN_DSI_CLK_FREQ_MHZ 40 98 99 /* fudge factor required to account for 8b/10b encoding */ 100 #define DP_CLK_FUDGE_NUM 10 101 #define DP_CLK_FUDGE_DEN 8 102 103 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 104 #define SN_AUX_MAX_PAYLOAD_BYTES 16 105 106 #define SN_REGULATOR_SUPPLY_NUM 4 107 108 #define SN_MAX_DP_LANES 4 109 #define SN_NUM_GPIOS 4 110 #define SN_GPIO_PHYSICAL_OFFSET 1 111 112 #define SN_LINK_TRAINING_TRIES 10 113 114 /** 115 * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver. 116 * @dev: Pointer to our device. 117 * @regmap: Regmap for accessing i2c. 118 * @aux: Our aux channel. 119 * @bridge: Our bridge. 120 * @connector: Our connector. 121 * @debugfs: Used for managing our debugfs. 122 * @host_node: Remote DSI node. 123 * @dsi: Our MIPI DSI source. 124 * @edid: Detected EDID of eDP panel. 125 * @refclk: Our reference clock. 126 * @panel: Our panel. 127 * @enable_gpio: The GPIO we toggle to enable the bridge. 128 * @supplies: Data for bulk enabling/disabling our regulators. 129 * @dp_lanes: Count of dp_lanes we're using. 130 * @ln_assign: Value to program to the LN_ASSIGN register. 131 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 132 * 133 * @gchip: If we expose our GPIOs, this is used. 134 * @gchip_output: A cache of whether we've set GPIOs to output. This 135 * serves double-duty of keeping track of the direction and 136 * also keeping track of whether we've incremented the 137 * pm_runtime reference count for this pin, which we do 138 * whenever a pin is configured as an output. This is a 139 * bitmap so we can do atomic ops on it without an extra 140 * lock so concurrent users of our 4 GPIOs don't stomp on 141 * each other's read-modify-write. 142 */ 143 struct ti_sn_bridge { 144 struct device *dev; 145 struct regmap *regmap; 146 struct drm_dp_aux aux; 147 struct drm_bridge bridge; 148 struct drm_connector connector; 149 struct dentry *debugfs; 150 struct edid *edid; 151 struct device_node *host_node; 152 struct mipi_dsi_device *dsi; 153 struct clk *refclk; 154 struct drm_panel *panel; 155 struct gpio_desc *enable_gpio; 156 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 157 int dp_lanes; 158 u8 ln_assign; 159 u8 ln_polrs; 160 161 #if defined(CONFIG_OF_GPIO) 162 struct gpio_chip gchip; 163 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 164 #endif 165 }; 166 167 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = { 168 { .range_min = 0, .range_max = 0xFF }, 169 }; 170 171 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 172 .yes_ranges = ti_sn_bridge_volatile_ranges, 173 .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges), 174 }; 175 176 static const struct regmap_config ti_sn_bridge_regmap_config = { 177 .reg_bits = 8, 178 .val_bits = 8, 179 .volatile_table = &ti_sn_bridge_volatile_table, 180 .cache_type = REGCACHE_NONE, 181 }; 182 183 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata, 184 unsigned int reg, u16 val) 185 { 186 regmap_write(pdata->regmap, reg, val & 0xFF); 187 regmap_write(pdata->regmap, reg + 1, val >> 8); 188 } 189 190 static int __maybe_unused ti_sn_bridge_resume(struct device *dev) 191 { 192 struct ti_sn_bridge *pdata = dev_get_drvdata(dev); 193 int ret; 194 195 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 196 if (ret) { 197 DRM_ERROR("failed to enable supplies %d\n", ret); 198 return ret; 199 } 200 201 gpiod_set_value(pdata->enable_gpio, 1); 202 203 return ret; 204 } 205 206 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev) 207 { 208 struct ti_sn_bridge *pdata = dev_get_drvdata(dev); 209 int ret; 210 211 gpiod_set_value(pdata->enable_gpio, 0); 212 213 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 214 if (ret) 215 DRM_ERROR("failed to disable supplies %d\n", ret); 216 217 return ret; 218 } 219 220 static const struct dev_pm_ops ti_sn_bridge_pm_ops = { 221 SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL) 222 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 223 pm_runtime_force_resume) 224 }; 225 226 static int status_show(struct seq_file *s, void *data) 227 { 228 struct ti_sn_bridge *pdata = s->private; 229 unsigned int reg, val; 230 231 seq_puts(s, "STATUS REGISTERS:\n"); 232 233 pm_runtime_get_sync(pdata->dev); 234 235 /* IRQ Status Registers, see Table 31 in datasheet */ 236 for (reg = 0xf0; reg <= 0xf8; reg++) { 237 regmap_read(pdata->regmap, reg, &val); 238 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 239 } 240 241 pm_runtime_put(pdata->dev); 242 243 return 0; 244 } 245 246 DEFINE_SHOW_ATTRIBUTE(status); 247 248 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata) 249 { 250 pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL); 251 252 debugfs_create_file("status", 0600, pdata->debugfs, pdata, 253 &status_fops); 254 } 255 256 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata) 257 { 258 debugfs_remove_recursive(pdata->debugfs); 259 pdata->debugfs = NULL; 260 } 261 262 /* Connector funcs */ 263 static struct ti_sn_bridge * 264 connector_to_ti_sn_bridge(struct drm_connector *connector) 265 { 266 return container_of(connector, struct ti_sn_bridge, connector); 267 } 268 269 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector) 270 { 271 struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector); 272 struct edid *edid = pdata->edid; 273 int num, ret; 274 275 if (!edid) { 276 pm_runtime_get_sync(pdata->dev); 277 edid = pdata->edid = drm_get_edid(connector, &pdata->aux.ddc); 278 pm_runtime_put(pdata->dev); 279 } 280 281 if (edid && drm_edid_is_valid(edid)) { 282 ret = drm_connector_update_edid_property(connector, edid); 283 if (!ret) { 284 num = drm_add_edid_modes(connector, edid); 285 if (num) 286 return num; 287 } 288 } 289 290 return drm_panel_get_modes(pdata->panel, connector); 291 } 292 293 static enum drm_mode_status 294 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector, 295 struct drm_display_mode *mode) 296 { 297 /* maximum supported resolution is 4K at 60 fps */ 298 if (mode->clock > 594000) 299 return MODE_CLOCK_HIGH; 300 301 return MODE_OK; 302 } 303 304 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = { 305 .get_modes = ti_sn_bridge_connector_get_modes, 306 .mode_valid = ti_sn_bridge_connector_mode_valid, 307 }; 308 309 static enum drm_connector_status 310 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force) 311 { 312 /** 313 * TODO: Currently if drm_panel is present, then always 314 * return the status as connected. Need to add support to detect 315 * device state for hot pluggable scenarios. 316 */ 317 return connector_status_connected; 318 } 319 320 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = { 321 .fill_modes = drm_helper_probe_single_connector_modes, 322 .detect = ti_sn_bridge_connector_detect, 323 .destroy = drm_connector_cleanup, 324 .reset = drm_atomic_helper_connector_reset, 325 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 326 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 327 }; 328 329 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge) 330 { 331 return container_of(bridge, struct ti_sn_bridge, bridge); 332 } 333 334 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata) 335 { 336 unsigned int i; 337 const char * const ti_sn_bridge_supply_names[] = { 338 "vcca", "vcc", "vccio", "vpll", 339 }; 340 341 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 342 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 343 344 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 345 pdata->supplies); 346 } 347 348 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 349 enum drm_bridge_attach_flags flags) 350 { 351 int ret, val; 352 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 353 struct mipi_dsi_host *host; 354 struct mipi_dsi_device *dsi; 355 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 356 .channel = 0, 357 .node = NULL, 358 }; 359 360 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 361 DRM_ERROR("Fix bridge driver to make connector optional!"); 362 return -EINVAL; 363 } 364 365 ret = drm_connector_init(bridge->dev, &pdata->connector, 366 &ti_sn_bridge_connector_funcs, 367 DRM_MODE_CONNECTOR_eDP); 368 if (ret) { 369 DRM_ERROR("Failed to initialize connector with drm\n"); 370 return ret; 371 } 372 373 drm_connector_helper_add(&pdata->connector, 374 &ti_sn_bridge_connector_helper_funcs); 375 drm_connector_attach_encoder(&pdata->connector, bridge->encoder); 376 377 /* 378 * TODO: ideally finding host resource and dsi dev registration needs 379 * to be done in bridge probe. But some existing DSI host drivers will 380 * wait for any of the drm_bridge/drm_panel to get added to the global 381 * bridge/panel list, before completing their probe. So if we do the 382 * dsi dev registration part in bridge probe, before populating in 383 * the global bridge list, then it will cause deadlock as dsi host probe 384 * will never complete, neither our bridge probe. So keeping it here 385 * will satisfy most of the existing host drivers. Once the host driver 386 * is fixed we can move the below code to bridge probe safely. 387 */ 388 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 389 if (!host) { 390 DRM_ERROR("failed to find dsi host\n"); 391 ret = -ENODEV; 392 goto err_dsi_host; 393 } 394 395 dsi = mipi_dsi_device_register_full(host, &info); 396 if (IS_ERR(dsi)) { 397 DRM_ERROR("failed to create dsi device\n"); 398 ret = PTR_ERR(dsi); 399 goto err_dsi_host; 400 } 401 402 /* TODO: setting to 4 MIPI lanes always for now */ 403 dsi->lanes = 4; 404 dsi->format = MIPI_DSI_FMT_RGB888; 405 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 406 407 /* check if continuous dsi clock is required or not */ 408 pm_runtime_get_sync(pdata->dev); 409 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 410 pm_runtime_put(pdata->dev); 411 if (!(val & DPPLL_CLK_SRC_DSICLK)) 412 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 413 414 ret = mipi_dsi_attach(dsi); 415 if (ret < 0) { 416 DRM_ERROR("failed to attach dsi to host\n"); 417 goto err_dsi_attach; 418 } 419 pdata->dsi = dsi; 420 421 return 0; 422 423 err_dsi_attach: 424 mipi_dsi_device_unregister(dsi); 425 err_dsi_host: 426 drm_connector_cleanup(&pdata->connector); 427 return ret; 428 } 429 430 static void ti_sn_bridge_disable(struct drm_bridge *bridge) 431 { 432 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 433 434 drm_panel_disable(pdata->panel); 435 436 /* disable video stream */ 437 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 438 /* semi auto link training mode OFF */ 439 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 440 /* disable DP PLL */ 441 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 442 443 drm_panel_unprepare(pdata->panel); 444 } 445 446 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata) 447 { 448 u32 bit_rate_khz, clk_freq_khz; 449 struct drm_display_mode *mode = 450 &pdata->bridge.encoder->crtc->state->adjusted_mode; 451 452 bit_rate_khz = mode->clock * 453 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 454 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 455 456 return clk_freq_khz; 457 } 458 459 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 460 static const u32 ti_sn_bridge_refclk_lut[] = { 461 12000000, 462 19200000, 463 26000000, 464 27000000, 465 38400000, 466 }; 467 468 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 469 static const u32 ti_sn_bridge_dsiclk_lut[] = { 470 468000000, 471 384000000, 472 416000000, 473 486000000, 474 460800000, 475 }; 476 477 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata) 478 { 479 int i; 480 u32 refclk_rate; 481 const u32 *refclk_lut; 482 size_t refclk_lut_size; 483 484 if (pdata->refclk) { 485 refclk_rate = clk_get_rate(pdata->refclk); 486 refclk_lut = ti_sn_bridge_refclk_lut; 487 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 488 clk_prepare_enable(pdata->refclk); 489 } else { 490 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000; 491 refclk_lut = ti_sn_bridge_dsiclk_lut; 492 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 493 } 494 495 /* for i equals to refclk_lut_size means default frequency */ 496 for (i = 0; i < refclk_lut_size; i++) 497 if (refclk_lut[i] == refclk_rate) 498 break; 499 500 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 501 REFCLK_FREQ(i)); 502 } 503 504 static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata) 505 { 506 unsigned int bit_rate_mhz, clk_freq_mhz; 507 unsigned int val; 508 struct drm_display_mode *mode = 509 &pdata->bridge.encoder->crtc->state->adjusted_mode; 510 511 /* set DSIA clk frequency */ 512 bit_rate_mhz = (mode->clock / 1000) * 513 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 514 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 515 516 /* for each increment in val, frequency increases by 5MHz */ 517 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 518 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 519 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 520 } 521 522 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata) 523 { 524 if (pdata->connector.display_info.bpc <= 6) 525 return 18; 526 else 527 return 24; 528 } 529 530 /* 531 * LUT index corresponds to register value and 532 * LUT values corresponds to dp data rate supported 533 * by the bridge in Mbps unit. 534 */ 535 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 536 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 537 }; 538 539 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) 540 { 541 unsigned int bit_rate_khz, dp_rate_mhz; 542 unsigned int i; 543 struct drm_display_mode *mode = 544 &pdata->bridge.encoder->crtc->state->adjusted_mode; 545 546 /* Calculate minimum bit rate based on our pixel clock. */ 547 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata); 548 549 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 550 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 551 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 552 553 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 554 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 555 break; 556 557 return i; 558 } 559 560 static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata, 561 bool rate_valid[]) 562 { 563 unsigned int rate_per_200khz; 564 unsigned int rate_mhz; 565 u8 dpcd_val; 566 int ret; 567 int i, j; 568 569 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 570 if (ret != 1) { 571 DRM_DEV_ERROR(pdata->dev, 572 "Can't read eDP rev (%d), assuming 1.1\n", ret); 573 dpcd_val = DP_EDP_11; 574 } 575 576 if (dpcd_val >= DP_EDP_14) { 577 /* eDP 1.4 devices must provide a custom table */ 578 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 579 580 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 581 sink_rates, sizeof(sink_rates)); 582 583 if (ret != sizeof(sink_rates)) { 584 DRM_DEV_ERROR(pdata->dev, 585 "Can't read supported rate table (%d)\n", ret); 586 587 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 588 memset(sink_rates, 0, sizeof(sink_rates)); 589 } 590 591 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 592 rate_per_200khz = le16_to_cpu(sink_rates[i]); 593 594 if (!rate_per_200khz) 595 break; 596 597 rate_mhz = rate_per_200khz * 200 / 1000; 598 for (j = 0; 599 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 600 j++) { 601 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 602 rate_valid[j] = true; 603 } 604 } 605 606 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 607 if (rate_valid[i]) 608 return; 609 } 610 DRM_DEV_ERROR(pdata->dev, 611 "No matching eDP rates in table; falling back\n"); 612 } 613 614 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 615 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 616 if (ret != 1) { 617 DRM_DEV_ERROR(pdata->dev, 618 "Can't read max rate (%d); assuming 5.4 GHz\n", 619 ret); 620 dpcd_val = DP_LINK_BW_5_4; 621 } 622 623 switch (dpcd_val) { 624 default: 625 DRM_DEV_ERROR(pdata->dev, 626 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 627 (int)dpcd_val); 628 fallthrough; 629 case DP_LINK_BW_5_4: 630 rate_valid[7] = 1; 631 fallthrough; 632 case DP_LINK_BW_2_7: 633 rate_valid[4] = 1; 634 fallthrough; 635 case DP_LINK_BW_1_62: 636 rate_valid[1] = 1; 637 break; 638 } 639 } 640 641 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) 642 { 643 struct drm_display_mode *mode = 644 &pdata->bridge.encoder->crtc->state->adjusted_mode; 645 u8 hsync_polarity = 0, vsync_polarity = 0; 646 647 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 648 hsync_polarity = CHA_HSYNC_POLARITY; 649 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 650 vsync_polarity = CHA_VSYNC_POLARITY; 651 652 ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 653 mode->hdisplay); 654 ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 655 mode->vdisplay); 656 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 657 (mode->hsync_end - mode->hsync_start) & 0xFF); 658 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 659 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 660 hsync_polarity); 661 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 662 (mode->vsync_end - mode->vsync_start) & 0xFF); 663 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 664 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 665 vsync_polarity); 666 667 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 668 (mode->htotal - mode->hsync_end) & 0xFF); 669 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 670 (mode->vtotal - mode->vsync_end) & 0xFF); 671 672 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 673 (mode->hsync_start - mode->hdisplay) & 0xFF); 674 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 675 (mode->vsync_start - mode->vdisplay) & 0xFF); 676 677 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 678 } 679 680 static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) 681 { 682 u8 data; 683 int ret; 684 685 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 686 if (ret != 1) { 687 DRM_DEV_ERROR(pdata->dev, 688 "Can't read lane count (%d); assuming 4\n", ret); 689 return 4; 690 } 691 692 return data & DP_LANE_COUNT_MASK; 693 } 694 695 static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, 696 const char **last_err_str) 697 { 698 unsigned int val; 699 int ret; 700 int i; 701 702 /* set dp clk frequency value */ 703 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 704 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 705 706 /* enable DP PLL */ 707 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 708 709 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 710 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 711 50 * 1000); 712 if (ret) { 713 *last_err_str = "DP_PLL_LOCK polling failed"; 714 goto exit; 715 } 716 717 /* 718 * We'll try to link train several times. As part of link training 719 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 720 * the panel isn't ready quite it might respond NAK here which means 721 * we need to try again. 722 */ 723 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 724 /* Semi auto link training mode */ 725 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 726 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 727 val == ML_TX_MAIN_LINK_OFF || 728 val == ML_TX_NORMAL_MODE, 1000, 729 500 * 1000); 730 if (ret) { 731 *last_err_str = "Training complete polling failed"; 732 } else if (val == ML_TX_MAIN_LINK_OFF) { 733 *last_err_str = "Link training failed, link is off"; 734 ret = -EIO; 735 continue; 736 } 737 738 break; 739 } 740 741 /* If we saw quite a few retries, add a note about it */ 742 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 743 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 744 745 exit: 746 /* Disable the PLL if we failed */ 747 if (ret) 748 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 749 750 return ret; 751 } 752 753 static void ti_sn_bridge_enable(struct drm_bridge *bridge) 754 { 755 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 756 bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { }; 757 const char *last_err_str = "No supported DP rate"; 758 int dp_rate_idx; 759 unsigned int val; 760 int ret = -EINVAL; 761 int max_dp_lanes; 762 763 max_dp_lanes = ti_sn_get_max_lanes(pdata); 764 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 765 766 /* DSI_A lane config */ 767 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 768 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 769 CHA_DSI_LANES_MASK, val); 770 771 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 772 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 773 pdata->ln_polrs << LN_POLRS_OFFSET); 774 775 /* set dsi clk frequency value */ 776 ti_sn_bridge_set_dsi_rate(pdata); 777 778 /** 779 * The SN65DSI86 only supports ASSR Display Authentication method and 780 * this method is enabled by default. An eDP panel must support this 781 * authentication method. We need to enable this method in the eDP panel 782 * at DisplayPort address 0x0010A prior to link training. 783 */ 784 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 785 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 786 787 /* Set the DP output format (18 bpp or 24 bpp) */ 788 val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; 789 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 790 791 /* DP lane config */ 792 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 793 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 794 val); 795 796 ti_sn_bridge_read_valid_rates(pdata, rate_valid); 797 798 /* Train until we run out of rates */ 799 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); 800 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 801 dp_rate_idx++) { 802 if (!rate_valid[dp_rate_idx]) 803 continue; 804 805 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 806 if (!ret) 807 break; 808 } 809 if (ret) { 810 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 811 return; 812 } 813 814 /* config video parameters */ 815 ti_sn_bridge_set_video_timings(pdata); 816 817 /* enable video stream */ 818 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 819 VSTREAM_ENABLE); 820 821 drm_panel_enable(pdata->panel); 822 } 823 824 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge) 825 { 826 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 827 828 pm_runtime_get_sync(pdata->dev); 829 830 /* configure bridge ref_clk */ 831 ti_sn_bridge_set_refclk_freq(pdata); 832 833 /* 834 * HPD on this bridge chip is a bit useless. This is an eDP bridge 835 * so the HPD is an internal signal that's only there to signal that 836 * the panel is done powering up. ...but the bridge chip debounces 837 * this signal by between 100 ms and 400 ms (depending on process, 838 * voltage, and temperate--I measured it at about 200 ms). One 839 * particular panel asserted HPD 84 ms after it was powered on meaning 840 * that we saw HPD 284 ms after power on. ...but the same panel said 841 * that instead of looking at HPD you could just hardcode a delay of 842 * 200 ms. We'll assume that the panel driver will have the hardcoded 843 * delay in its prepare and always disable HPD. 844 * 845 * If HPD somehow makes sense on some future panel we'll have to 846 * change this to be conditional on someone specifying that HPD should 847 * be used. 848 */ 849 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 850 HPD_DISABLE); 851 852 drm_panel_prepare(pdata->panel); 853 } 854 855 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge) 856 { 857 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); 858 859 clk_disable_unprepare(pdata->refclk); 860 861 pm_runtime_put_sync(pdata->dev); 862 } 863 864 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 865 .attach = ti_sn_bridge_attach, 866 .pre_enable = ti_sn_bridge_pre_enable, 867 .enable = ti_sn_bridge_enable, 868 .disable = ti_sn_bridge_disable, 869 .post_disable = ti_sn_bridge_post_disable, 870 }; 871 872 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux) 873 { 874 return container_of(aux, struct ti_sn_bridge, aux); 875 } 876 877 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 878 struct drm_dp_aux_msg *msg) 879 { 880 struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux); 881 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 882 u32 request_val = AUX_CMD_REQ(msg->request); 883 u8 *buf = msg->buffer; 884 unsigned int len = msg->size; 885 unsigned int val; 886 int ret; 887 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 888 889 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 890 return -EINVAL; 891 892 switch (request) { 893 case DP_AUX_NATIVE_WRITE: 894 case DP_AUX_I2C_WRITE: 895 case DP_AUX_NATIVE_READ: 896 case DP_AUX_I2C_READ: 897 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 898 /* Assume it's good */ 899 msg->reply = 0; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 906 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 907 addr_len); 908 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 909 ARRAY_SIZE(addr_len)); 910 911 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 912 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 913 914 /* Clear old status bits before start so we don't get confused */ 915 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 916 AUX_IRQ_STATUS_NAT_I2C_FAIL | 917 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 918 AUX_IRQ_STATUS_AUX_SHORT); 919 920 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 921 922 /* Zero delay loop because i2c transactions are slow already */ 923 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 924 !(val & AUX_CMD_SEND), 0, 50 * 1000); 925 if (ret) 926 return ret; 927 928 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 929 if (ret) 930 return ret; 931 932 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 933 /* 934 * The hardware tried the message seven times per the DP spec 935 * but it hit a timeout. We ignore defers here because they're 936 * handled in hardware. 937 */ 938 return -ETIMEDOUT; 939 } 940 941 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 942 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len); 943 if (ret) 944 return ret; 945 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 946 switch (request) { 947 case DP_AUX_I2C_WRITE: 948 case DP_AUX_I2C_READ: 949 msg->reply |= DP_AUX_I2C_REPLY_NACK; 950 break; 951 case DP_AUX_NATIVE_READ: 952 case DP_AUX_NATIVE_WRITE: 953 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 954 break; 955 } 956 return 0; 957 } 958 959 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE || 960 len == 0) 961 return len; 962 963 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 964 if (ret) 965 return ret; 966 967 return len; 968 } 969 970 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata) 971 { 972 struct device_node *np = pdata->dev->of_node; 973 974 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 975 976 if (!pdata->host_node) { 977 DRM_ERROR("remote dsi host node not found\n"); 978 return -ENODEV; 979 } 980 981 return 0; 982 } 983 984 #if defined(CONFIG_OF_GPIO) 985 986 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 987 const struct of_phandle_args *gpiospec, 988 u32 *flags) 989 { 990 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 991 return -EINVAL; 992 993 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 994 return -EINVAL; 995 996 if (flags) 997 *flags = gpiospec->args[1]; 998 999 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1000 } 1001 1002 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1003 unsigned int offset) 1004 { 1005 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1006 1007 /* 1008 * We already have to keep track of the direction because we use 1009 * that to figure out whether we've powered the device. We can 1010 * just return that rather than (maybe) powering up the device 1011 * to ask its direction. 1012 */ 1013 return test_bit(offset, pdata->gchip_output) ? 1014 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1015 } 1016 1017 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1018 { 1019 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1020 unsigned int val; 1021 int ret; 1022 1023 /* 1024 * When the pin is an input we don't forcibly keep the bridge 1025 * powered--we just power it on to read the pin. NOTE: part of 1026 * the reason this works is that the bridge defaults (when 1027 * powered back on) to all 4 GPIOs being configured as GPIO input. 1028 * Also note that if something else is keeping the chip powered the 1029 * pm_runtime functions are lightweight increments of a refcount. 1030 */ 1031 pm_runtime_get_sync(pdata->dev); 1032 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1033 pm_runtime_put(pdata->dev); 1034 1035 if (ret) 1036 return ret; 1037 1038 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1039 } 1040 1041 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1042 int val) 1043 { 1044 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1045 int ret; 1046 1047 if (!test_bit(offset, pdata->gchip_output)) { 1048 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); 1049 return; 1050 } 1051 1052 val &= 1; 1053 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1054 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1055 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1056 if (ret) 1057 dev_warn(pdata->dev, 1058 "Failed to set bridge GPIO %u: %d\n", offset, ret); 1059 } 1060 1061 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1062 unsigned int offset) 1063 { 1064 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1065 int shift = offset * 2; 1066 int ret; 1067 1068 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1069 return 0; 1070 1071 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1072 SN_GPIO_MUX_MASK << shift, 1073 SN_GPIO_MUX_INPUT << shift); 1074 if (ret) { 1075 set_bit(offset, pdata->gchip_output); 1076 return ret; 1077 } 1078 1079 /* 1080 * NOTE: if nobody else is powering the device this may fully power 1081 * it off and when it comes back it will have lost all state, but 1082 * that's OK because the default is input and we're now an input. 1083 */ 1084 pm_runtime_put(pdata->dev); 1085 1086 return 0; 1087 } 1088 1089 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1090 unsigned int offset, int val) 1091 { 1092 struct ti_sn_bridge *pdata = gpiochip_get_data(chip); 1093 int shift = offset * 2; 1094 int ret; 1095 1096 if (test_and_set_bit(offset, pdata->gchip_output)) 1097 return 0; 1098 1099 pm_runtime_get_sync(pdata->dev); 1100 1101 /* Set value first to avoid glitching */ 1102 ti_sn_bridge_gpio_set(chip, offset, val); 1103 1104 /* Set direction */ 1105 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1106 SN_GPIO_MUX_MASK << shift, 1107 SN_GPIO_MUX_OUTPUT << shift); 1108 if (ret) { 1109 clear_bit(offset, pdata->gchip_output); 1110 pm_runtime_put(pdata->dev); 1111 } 1112 1113 return ret; 1114 } 1115 1116 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1117 { 1118 /* We won't keep pm_runtime if we're input, so switch there on free */ 1119 ti_sn_bridge_gpio_direction_input(chip, offset); 1120 } 1121 1122 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1123 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1124 }; 1125 1126 static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) 1127 { 1128 int ret; 1129 1130 /* Only init if someone is going to use us as a GPIO controller */ 1131 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1132 return 0; 1133 1134 pdata->gchip.label = dev_name(pdata->dev); 1135 pdata->gchip.parent = pdata->dev; 1136 pdata->gchip.owner = THIS_MODULE; 1137 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1138 pdata->gchip.of_gpio_n_cells = 2; 1139 pdata->gchip.free = ti_sn_bridge_gpio_free; 1140 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1141 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1142 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1143 pdata->gchip.get = ti_sn_bridge_gpio_get; 1144 pdata->gchip.set = ti_sn_bridge_gpio_set; 1145 pdata->gchip.can_sleep = true; 1146 pdata->gchip.names = ti_sn_bridge_gpio_names; 1147 pdata->gchip.ngpio = SN_NUM_GPIOS; 1148 pdata->gchip.base = -1; 1149 ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata); 1150 if (ret) 1151 dev_err(pdata->dev, "can't add gpio chip\n"); 1152 1153 return ret; 1154 } 1155 1156 #else 1157 1158 static inline int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) 1159 { 1160 return 0; 1161 } 1162 1163 #endif 1164 1165 static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata, 1166 struct device_node *np) 1167 { 1168 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1169 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1170 struct device_node *endpoint; 1171 u8 ln_assign = 0; 1172 u8 ln_polrs = 0; 1173 int dp_lanes; 1174 int i; 1175 1176 /* 1177 * Read config from the device tree about lane remapping and lane 1178 * polarities. These are optional and we assume identity map and 1179 * normal polarity if nothing is specified. It's OK to specify just 1180 * data-lanes but not lane-polarities but not vice versa. 1181 * 1182 * Error checking is light (we just make sure we don't crash or 1183 * buffer overrun) and we assume dts is well formed and specifying 1184 * mappings that the hardware supports. 1185 */ 1186 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1187 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 1188 if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) { 1189 of_property_read_u32_array(endpoint, "data-lanes", 1190 lane_assignments, dp_lanes); 1191 of_property_read_u32_array(endpoint, "lane-polarities", 1192 lane_polarities, dp_lanes); 1193 } else { 1194 dp_lanes = SN_MAX_DP_LANES; 1195 } 1196 of_node_put(endpoint); 1197 1198 /* 1199 * Convert into register format. Loop over all lanes even if 1200 * data-lanes had fewer elements so that we nicely initialize 1201 * the LN_ASSIGN register. 1202 */ 1203 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1204 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1205 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1206 } 1207 1208 /* Stash in our struct for when we power on */ 1209 pdata->dp_lanes = dp_lanes; 1210 pdata->ln_assign = ln_assign; 1211 pdata->ln_polrs = ln_polrs; 1212 } 1213 1214 static int ti_sn_bridge_probe(struct i2c_client *client, 1215 const struct i2c_device_id *id) 1216 { 1217 struct ti_sn_bridge *pdata; 1218 int ret; 1219 1220 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1221 DRM_ERROR("device doesn't support I2C\n"); 1222 return -ENODEV; 1223 } 1224 1225 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge), 1226 GFP_KERNEL); 1227 if (!pdata) 1228 return -ENOMEM; 1229 1230 pdata->regmap = devm_regmap_init_i2c(client, 1231 &ti_sn_bridge_regmap_config); 1232 if (IS_ERR(pdata->regmap)) { 1233 DRM_ERROR("regmap i2c init failed\n"); 1234 return PTR_ERR(pdata->regmap); 1235 } 1236 1237 pdata->dev = &client->dev; 1238 1239 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0, 1240 &pdata->panel, NULL); 1241 if (ret) { 1242 DRM_ERROR("could not find any panel node\n"); 1243 return ret; 1244 } 1245 1246 dev_set_drvdata(&client->dev, pdata); 1247 1248 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable", 1249 GPIOD_OUT_LOW); 1250 if (IS_ERR(pdata->enable_gpio)) { 1251 DRM_ERROR("failed to get enable gpio from DT\n"); 1252 ret = PTR_ERR(pdata->enable_gpio); 1253 return ret; 1254 } 1255 1256 ti_sn_bridge_parse_lanes(pdata, client->dev.of_node); 1257 1258 ret = ti_sn_bridge_parse_regulators(pdata); 1259 if (ret) { 1260 DRM_ERROR("failed to parse regulators\n"); 1261 return ret; 1262 } 1263 1264 pdata->refclk = devm_clk_get(pdata->dev, "refclk"); 1265 if (IS_ERR(pdata->refclk)) { 1266 ret = PTR_ERR(pdata->refclk); 1267 if (ret == -EPROBE_DEFER) 1268 return ret; 1269 DRM_DEBUG_KMS("refclk not found\n"); 1270 pdata->refclk = NULL; 1271 } 1272 1273 ret = ti_sn_bridge_parse_dsi_host(pdata); 1274 if (ret) 1275 return ret; 1276 1277 pm_runtime_enable(pdata->dev); 1278 1279 ret = ti_sn_setup_gpio_controller(pdata); 1280 if (ret) { 1281 pm_runtime_disable(pdata->dev); 1282 return ret; 1283 } 1284 1285 i2c_set_clientdata(client, pdata); 1286 1287 pdata->aux.name = "ti-sn65dsi86-aux"; 1288 pdata->aux.dev = pdata->dev; 1289 pdata->aux.transfer = ti_sn_aux_transfer; 1290 drm_dp_aux_register(&pdata->aux); 1291 1292 pdata->bridge.funcs = &ti_sn_bridge_funcs; 1293 pdata->bridge.of_node = client->dev.of_node; 1294 1295 drm_bridge_add(&pdata->bridge); 1296 1297 ti_sn_debugfs_init(pdata); 1298 1299 return 0; 1300 } 1301 1302 static int ti_sn_bridge_remove(struct i2c_client *client) 1303 { 1304 struct ti_sn_bridge *pdata = i2c_get_clientdata(client); 1305 1306 if (!pdata) 1307 return -EINVAL; 1308 1309 kfree(pdata->edid); 1310 ti_sn_debugfs_remove(pdata); 1311 1312 of_node_put(pdata->host_node); 1313 1314 pm_runtime_disable(pdata->dev); 1315 1316 if (pdata->dsi) { 1317 mipi_dsi_detach(pdata->dsi); 1318 mipi_dsi_device_unregister(pdata->dsi); 1319 } 1320 1321 drm_bridge_remove(&pdata->bridge); 1322 1323 return 0; 1324 } 1325 1326 static struct i2c_device_id ti_sn_bridge_id[] = { 1327 { "ti,sn65dsi86", 0}, 1328 {}, 1329 }; 1330 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id); 1331 1332 static const struct of_device_id ti_sn_bridge_match_table[] = { 1333 {.compatible = "ti,sn65dsi86"}, 1334 {}, 1335 }; 1336 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table); 1337 1338 static struct i2c_driver ti_sn_bridge_driver = { 1339 .driver = { 1340 .name = "ti_sn65dsi86", 1341 .of_match_table = ti_sn_bridge_match_table, 1342 .pm = &ti_sn_bridge_pm_ops, 1343 }, 1344 .probe = ti_sn_bridge_probe, 1345 .remove = ti_sn_bridge_remove, 1346 .id_table = ti_sn_bridge_id, 1347 }; 1348 module_i2c_driver(ti_sn_bridge_driver); 1349 1350 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 1351 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 1352 MODULE_LICENSE("GPL v2"); 1353